3094 Dell Latitude d630 Compalm08 (Dis) Briscoe La-3302

A
COMPAL CONFIDENTIAL
1
MODEL NAME : IBQ00

PCB NO : LA-3302P ( DAA00000K0L)
BOM P/N : 45144731L01
M08 (DIS) Briscoe
uFCPGA Mobile Merom

Intel Crestline + ICH8M
2007-03-07
REV : 0.4 (X03)
3
@ : Nopop Component
1@ : Populate for G72MV
2@ : Populate for G86MV
45144731L01 pop for G86MV
45144XXXXX pop for G72MV
4
MB PCB
Part Number
DELL CONFIDENTIAL/PROPRIETARY
Description
DAA00000K0L
PCB ZGX LA-3302P

REV0 M/B DIS
Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Cover Sheet
Size
Document Number
Date:
Wednesday, March 07, 2007
Rev
0.4
LA-3302P
Sheet
E
of
66
Block Diagram
Compal confidential
Model : IBQ01
FAN
1
Pentium-M
Merom -4MB (Socket P)
uFCPGA CPU
Thermal
GUARDIAN III
EMC4001
+FAN1_VOUT
page 18
+3.3V_SUS
+VCC_CORE
CRT CONN
+5V_RUN
CPU ITP Port
+1.05V_VCCP
page 18
H_A#(3..35)
page 20
+1.05V_VCCP page 7
page 7,8,9
478pin
System Bus
Clock Generator
CK505
+3.3V_M
page6
H_D#(0..63)
FSB 800 MHz
RGB
+LCDVDD page 19
DVI
INTEL
Crestline
NV G86
LVDS CONN
+INV_PWR_SRC
PCI-E 16X
+1.25V_GFX_PCIE
+1.25V_RUN
+GPU_CORE(1.1V)
+1.5V_RUN
page 51,52,53,54,55,56,57
+1.8V_SUS
Memory BUS
(DDR2) +1.8V_SUS
DDRII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
533 / 667MHz
page 16,17
+0.9V_DDR_VTT
1299pin BGA
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
TV
PCI BUS
PCI_PIRQA#
REQ#0
GNT#0
DOCKING
BUFFER
DOCKING
PORT
page 36
DOCK LPC BUS
+5V_RUN page 35
(+3VRUN 33MHz)
+5V_RUN
USB[2,3]
page 30
Mini Card2
WLAN
+3.3V_WLAN
+1.5V_RUN page 34
Mini Card 1
WWAN
+3.3V_RUN
+1.5V_RUN page 34
+RTC_CELL
+3.3V_RUN
IEEE1394
+3.3V_SUS
page 30
USB[6]
USB[8]
+1.25V_RUN
+1.5V_RUN
(+1.5V_RUN 100MHz)
SIDE
page 32
USB Ports X2
USB0 : side pair top,

USB1 : side pair bottom
Azalia I/F
PATA
page 21,22,23,24
+3VRUN
33MHz
USB[0,1]
USB2 : Rear Left as viewed from the back,

USB3 Rear Right as viewed from the back
+5V_SUS IO/Board
+1.05V_VCCP
GIGA Enthernet
BCM5755M
SATA
SPI
SC_USB
M DC
LPC BUS
+3.3V_SUS
page 33
+3.3V_LAN
+2.5V_LAN
+1.2V_LAN
page 28,29
USB[9]
INTEL
ICH8-M
676pin BGA
SLOT
page 31
USB Ports X2
+5V_SUS
48MHz
CardBus
OZ711 LQFP
+3.3V_RUN
REAR
+1.5V_RUN
100MHz
IDSEL:AD17
(PIRQD#,GNT#1,REQ#1)
PCI Express BUS
page 10,11,12,13,14,15
DMI
Smart Card
OZ77CR6
USB[4]
+1.8V_RUN
DOCK LPC BUS
RJ45
+3.3V_ALW page 38
IO/B
Cable
SMSC SIO
ECE5028
S-HDD
D Moudle
+5V_HDD
page 25
+5V_MOD
page 25
Azalia Codec
STAC9205
+3.3V_RUN
+VDDA
page 26
RJ11
IO/B
COM
+3.3V_SUS
page 37
1.8V / 0.9V/1.25V
PWR Sequence
page 42
MEC5025
ECE1077
1.5V / 1.05V
ME & LED
SPI
page 46
page 43
+3.3V_ALW
page 37
page 47
+RTC_CELL
+3.3V_ALW page 39
AMP & INT.

Speaker
INT MIC
+VDDA
page 27
+5V_RUN page 27
DC IN
Vccore
page 44
Int.KBD &
Stick page
page 48
HeadPhone
& MIC Jack
+3.3V_RUN page 27
ST M25P16
+3.3V_SUS page 39
40
Charger
Battery IN
page 44
3V / 5V /15V
Bluetooth
page 49
Touch Pad
+5V_RUN
USB[7]
Battery Select
page 45
Stick
+3.3V_RUN page 40
page 40
Biometric
+3.3V_RUN page 40
USB[5]
Title
Block Diagram
Trough Cable
Size
page 50
Document Number
Rev
0.4
LA-3302P
Date:
A
Monday, February 26, 2007
Sheet
E
of
66
POWER STATES
Signal
State
S0 (Full ON) / M0
SLP
S3#
SLP
S4#
SLP
S5#
S4
STATE#
SLP
M#
ALWAYS
PLANE
HIGH
HIGH
HIGH
HIGH
HIGH
ON
M
PLANE
SUS
PLANE
RUN
PLANE
ON
ON
ON
CLOCKS
USB PORT#
DESTINATION
Side Top
Side Bottom
Rear Left
Rear Right
Smart Card
Biometric
Card Bus
Bluetooth
Docking
WWAN
None
None
None
None
ON
S3 (Suspend to RAM) / M1
LOW
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
OFF
ON
S4 (Suspend to DISK) / M1
LOW
HIGH
HIGH
LOW
HIGH
ON
ON
ON
OFF
ON
S5 (SOFT OFF) / M1
LOW
HIGH
LOW
LOW
HIGH
ON
ON
ON
OFF
ON
S3 (Suspend to RAM) / M-OFF
LOW
HIGH
HIGH
HIGH
LOW
ON
OFF
ON
OFF
OFF
S4 (Suspend to DISK) / M-OFF
LOW
LOW
HIGH
LOW
LOW
ON
OFF
OFF
OFF
OFF
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
ICH8-M
PM TABLE
+15V_ALW
power
plane
+5V_SUS
+5V_RUN
+3.3V_M
+1.25V_M
+5V_ALW
+3.3V_SUS
+3.3V_RUN
+1.25V_M +3.3V_M
+3.3V_ALW
+1.8V_SUS
+2.5V_RUN
+1.05V_M +1.05V_M
(M-OFF)
+1.8V_RUN
+3.3V_RTC_LDO
+1.5V_RUN
ECE 5028
+VCC_+1P2V_GPU_CORE
+0.9V_DDR_VTT
+GPU_CORE
State
+VCC_CORE
+1.05V_VCCP
S0
ON
ON
ON
ON
ON
S3
ON
ON
OFF
ON
OFF
S5 S4/AC
ON
OFF
OFF
ON
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
OFF
PCI EXPRESS
DESTINATION
Lane 1
MINI CARD-1 WWAN
Lane 2
MINI CARD-2 WLAN
Lane 3
None
Lane 4
None
Lane 5
None
Lane 6
GIGA LAN
PCI TABLE
PCI DEVICE
IDSEL
REQ#/GNT#
PIRQ
OZ711
AD17
REQ#1 / GNT#1
PIRQD
Docking
AD24
REQ#0 / GNT#0
PIRQA
Title
Index and Config.

Size
Rev
0.4
LA-3302P
Date:
Document Number
Sheet
1
of
66
RUN_ON
FDS4435
(Q24)
+INV_PWR_SRC
RUN_ON
M_ON
ADAPTER
MAX1510E
(PU26)
+1.25V_RUN
+1.25V_M
D
ISL6236
(PU25)
MAX1510E
(PU26)
+1.05V_M
GFX_CORE_ON
+GPU_CORE
+PWR_SRC
BATTERY
+15V_ALW
ALWON
+5V_ALW
CHARGER
ISL6260
(PU11)
ISL88550A
(PU6)
ISL6236
(PU21)
ISL6236
(PU20)
RUN_ON
SI4810DY
(Q52)
ALWON
+1.05V_VCCP
+1.5V_RUN
M_ON
1.5V_RUN_ON
1.05V_RUN_ON
+0.9V_DDR_VTT
SI3456BDV
(Q44)
SI4810DY
(Q58)
+3.3V_LAN
+3.3V_RUN
SI4800BDY
(Q67)
MAX9789A
(U37)
SI3456BDV
(Q54)
BCP69
(Q45)
+5V_HDD
+5V_MOD
+3.3V_M
CTRL_10
SI3456
(Q48)
CTRL_18
SI3456BDV
(Q56)
MODC_EN#
HDDC_EN#
AUDIO_AVDD_ON
RUN_ON
+3.3V_SUS
RUN_ON
+1.8V_SUS
ENAB_3VLAN
+VCC_CORE
+5V_SUS
DDR_ON
SUS_ON
ISlL88550_AVDD
RUNPWROK
+3.3V_ALW
+5V_RUN
BCP69
(Q46)
+VDDA
+1.8VRUN
+1.8V_LAN
+1.0V_LAN
Title
Power Rail
Size
Rev
0.4
LA-3302P
Date:
Document Number
Sheet
1
of
66
2.2K
2.2K
+3.3V_SUS
2.2K
ICH8-M
AJ26
ICH_SMBCLK
AD19
ICH_SMBDATA
2.2K
2N7002
+3.3V_RUN
MEM_SCLK
197
MEM_SDATA
195
DIMMA
SMBUS Address [TBD]
DIMMB
SMBUS Address [TBD]
2N7002
32
30
C7
C8
32
30
197
WWAN
2.2K
Intel LAN
195
2.2K
SMBUS Address [TBD]
SMBUS Address [TBD]
WLAN_SMBCLK
2N7002
+3.3V_WLAN
WLAN_SMBDATA
WLAN
@ 0
CLK_SCLK
@ 0
CLK_SDATA
2N7002
SMBUS Address [TBD]
8.2K
+3.3V_ALW
8.2K
8
LCD_SMBCLK
LCD_SMDATA
INVERTER
(JLVDS)
4.7K
SMBUS Address [TBD]

C
10
+3.3V_ALW
4.7K
100
THRM_SMBCLK
99
THRM_SMBDAT
Charger
SMBUS Address [TBD]
EMC4001
SMBUS Address [TBD]
2'nd
BATTERY
SMBUS Address [TBD]
BATTERY
CONN
SMBUS Address [TBD]
12
11
2.2K
+3.3V_ALW
2.2K
SIO
10
SBAT_SMBCLK
100 ohm
SBAT_SMBDAT
100 ohm
2.2K
+3.3V_ALW
2.2K
111
PBAT_SMBCLK
112
PBAT_SMBDAT
100 ohm
100 ohm
9
10 CHARGER
SMBUS Address [TBD]
8.2K
+5V_ALW
8.2K
MEC 5025
DOCK_SMB_CLK
DOCK_SMB_DAT
6
5
DOCKING
SMBUS Address [TBD]
2.2K
2.2K
12
CKG_SMBDAT
13
CKG_SMBCLK
2N7002
2N7002
+3.3V_RUN
CLK_SDATA
17
CLK_SCLK
16 CLK GEN
SMBUS Address [TBD]

Title
SMBUS TOPOLOGY
Size
Document Number
Rev
0.4
LA-3302P
Date:
5
Sheet
1
of
66
+3.3V_RUN
2
G
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
PCI
MHz
266
100
33.3
133
100
33.3
200
100
33.3
333
100
33.3
100
100
33.3
400
100
33.3
200
100
33.3
C483
X1
27P_0402_50V8J~D 14.31818MHz_20P_1BX14318CC1A~D
2
1
Place crystal within

500 mils of CK410
CLK_ICH_48M
CLK_SMC_48M
CLK_PCI_TPM
CLK_PCI_DOCK
28 CLK_PCI_TPM
36 CLK_PCI_DOCK
0
30 CLK_PCI_PCM
39 CLK_PCI_5025
166
38 CLK_PCI_5018
23 CLK_ICH_14M
38 CLK_SIO_14M
1
2
1@ R697
84.5_0402_1%~D
R290
10K_0402_5%~D
52 CLK_NVSS_27M
21 CLK_PCI_ICH
23 CLK_PWRGD
PCI_PCM
VTT_PWRGD#/PD
CKPWRGD/PD#
@ R391
10K_0402_5%~D
VDD_REF
40
VDD_48
25
H_STP_PCI#
CPU_STP#
24
H_STP_CPU#
CPU_1
11
MCH_BCLK
CPU_1#
10
MCH_BCLK#
CPU_0
14
CPU_BCLK
CPU_0#
13
CPU_BCLK#
XTAL_IN
19
XTAL_OUT
41
USB_48MHz/FSLA
45
FSL_B/TEST_MODE
R314 1
2 8.2K_0402_5%~D
FSC
23
REF_0/FSL_C/TEST_SEL
R277 2
R596 2
1 33_0402_5%~D
1 33_0402_5%~D
PCI_LOM
34
PCICLK4/FCT_SEL
PCI_DOCK
33
PCICLK3
PCI_PCM
32
PCICLK2/TME
PCI_SIO
27
PCICLK1
CLKREF
22
1 33_0402_5%~D
1 15_0402_5%~D
CLK_PCI_5018
R333 1
2 15_0402_5%~D
CLK_ICH_14M
CLK_SIO_14M
R284 1
R285 1
2 15_0402_5%~D
2 15_0402_5%~D
CLK_NVSS_27M
2@ R286 1
1@ R833 1
R287 1
CLK_PCI_ICH
R291 2
2 33_0402_5%~D
2 147_0402_1%~D
2 33_0402_5%~D
1 33_0402_5%~D
DOT96
CPU_ITP/SRC_10
CPU_ITP
CPU_ITP#/SRC_10#
CPU_ITP#
SRC_9
PCIE_MINI1
PCIE_MINI1#
DOT_96/27M
CLK_NVSS
44
DOT_96#/27M_SS
PCI_ICH
37
CLK_PWRGD
@
+3.3V_RUN
R295
10K_0402_5%~D
1
2
@ R298
1
2
10K_0402_5%~D
39
34 CLK_SDATA
PGMODE
CLK_SCLK
16
CLK_SDATA
17
CLKREQ_9#
72
SRC_8
70
PCIE_MINI2
SRC_8#
69
PCIE_MINI2#
71
SRC_7
66
PCIE_ICH
PCIE_ICH#
SRC_7#
67
CLKREQ_7#
38
63
PCIE_LOM
64
PCIE_LOM#
CLKREQ_6#
62
SRC_5
60
PCIE_VGA
PCIE_VGA#
SRC_5#
61
CLKREQ_5#
29
SRC_4
58
SRC_4#
59
PGMODE
SMBCLK
57
MCH_3GPLL
56
MCH_3GPLL#
SRC_3#
CLKREQ_3#
28
VSS_REF
SRC_2
52
Pin 5/6 as SRC_10
31
VSS_PCI
SRC_2#
53
Pin 5/6 as CPU_ITP
35
VSS_PCI
CLKREQ_2#
26
42
VSS_48
68
VSS_SRC
73
74
75
76
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
Normal Operation
Trusted Mode Enabled
FCTSEL1
PIN43
PIN44
PIN47
PIN48
0=UMA
DOT96T
DOT96C
96/100M_T
96/100M_C
1=DIS
27M_out
27M SSout
SRCT0
SRCC0
1
R267
1
R268
CLK_MCH_BCLK
2
33_0402_5%~D
CLK_MCH_BCLK#
2
33_0402_5%~D
1
R269
1
R270
CLK_CPU_BCLK
2
33_0402_5%~D
CLK_CPU_BCLK#
2
33_0402_5%~D
1
R272
1
R274
CLK_CPU_ITP
2
33_0402_5%~D
CLK_CPU_ITP#
2
33_0402_5%~D
1
R311
1
R313
CLK_PCIE_MINI1
2
33_0402_5%~D
CLK_PCIE_MINI1#
2
33_0402_5%~D
1
R306
1
R307
CLK_PCIE_MINI2
2
33_0402_5%~D
CLK_PCIE_MINI2#
2
33_0402_5%~D
1
R288
1
R289
CLK_PCIE_ICH
2
33_0402_5%~D
CLK_PCIE_ICH#
2
33_0402_5%~D
0=UMA
1=Disc. GRFX down
1
R302
1
R303
CLK_PCIE_LOM
2
33_0402_5%~D
CLK_PCIE_LOM#
2
33_0402_5%~D
1
R299
1
R168
CLK_PCIE_VGA
2
33_0402_5%~D
CLK_PCIE_VGA#
2
33_0402_5%~D
SRC_1/SATA
50
PCIE_SATA
SRC_1#/SATA#
51
PCIE_SATA#
CLKREQ_1#
46
LCD_CLK/SRC_0
47
LCD_CLK#/SRC_0#
48
1
R293
1
R294
1
R419
CLK_MCH_3GPLL
2
33_0402_5%~D
CLK_MCH_3GPLL#
2
33_0402_5%~D
2
475_0402_1%~D
1
R279
1
R281
CLK_PCIE_SATA
2
33_0402_5%~D
CLK_PCIE_SATA#
2
33_0402_5%~D
CLK_PCI_TPM
CLK_MCH_BCLK# 10
1
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
C777
3.3P_0402_50V8C~D
@
CLK_PCI_DOCK
CLK_CPU_ITP 7
1
CLK_CPU_ITP# 7
CLK_PCIE_MINI1 34
C778
3.3P_0402_50V8C~D
@
CLK_PCIE_MINI1# 34
CLK_PCI_PCM
1
CLK_PCIE_MINI2 34
CLK_PCIE_MINI2# 34
C779
3.3P_0402_50V8C~D
@
CLK_PCI_5025
CLK_PCIE_ICH 23
CLK_PCIE_ICH# 23
C780
3.3P_0402_50V8C~D
@
CLK_PCIE_LOM 28
CLK_PCI_5018
CLK_PCIE_LOM# 28
1
CLK_PCIE_VGA 52
C781
3.3P_0402_50V8C~D
@
CLK_PCIE_VGA# 52
CLK_PCI_ICH
C785
3.3P_0402_50V8C~D
@
CLK_MCH_3GPLL 10
CLK_MCH_3GPLL# 10
CLK_3GPLLREQ# 10
CLK_PCIE_SATA 22
CLK_PCIE_SATA# 22
SATA_CLKREQ# 23
A
SLG8LP550_QFN72~D

Title
Clock Generator
Size
Document Number
Rev
0.4
LA-3302P
Date:
C776
3.3P_0402_50V8C~D
@
CLK_MCH_BCLK 10
55
VSS_SRC
SRC_3
4
23
H_STP_CPU# 23
LOM_CLKREQ# 28
CLKREQ_4#
SMBDAT
H_STP_PCI#
SRC_6
VSS_CPU
PIN 32
C775
3.3P_0402_50V8C~D
@
MINI2CLK_REQ# 34
SRC_6#
PCICLK_F0/ITP_EN
CKPWRGD/PD#
CLK_ICH_14M
1
MINI1CLK_REQ# 34
CLKREQ_8#
REF_1
43
CLK_SIO_14M
PCI_STP#
21
C477
0.1U_0402_16V4Z~D
C475
0.1U_0402_16V4Z~D
C476
0.1U_0402_16V4Z~D
8
15
18
VSS_A
@ R319
10K_0402_5%~D
2
FSA
VDD_CPU
VDD_A
PIN 37
TME
@ R329
10K_0402_5%~D
12
20
PCI_LOM
R318
10K_0402_5%~D
A
+3.3V_RUN
VDD_PCI
VDD_PCI
FSA
PIN 9
ITP_EN
+3.3V_RUN
30
36
SLG8LP550
CLK_XTAL_OUT
1
2
PGMODE
PCI_ICH
VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC
1 15_0402_5%~D
2 15_0402_5%~D
2 2.2K_0402_5%~D
34 CLK_SCLK
R304
10K_0402_5%~D
R273 2
R275 1
R309 1
R280 2
R282 2
Populate R697,R833 for G72MV

Populate R286 for G86MV.
R833,R286 place overlap
+3.3V_RUN
R271
0_0402_5%~D
1
2
CLK_PCI_PCM
CLK_PCI_5025
CLK_NV_27M
52 CLK_NV_27M
+3.3V_RUN
SRC_9#
CPU_BSEL2(FSC) CPU_BSEL1(FSB)
0
2 +CK_VDD_REF
1_0603_5%~D
2 +CK_VDD_48
2.2_0603_5%~D
CLK_XTAL_IN
8,10 CPU_MCH_BSEL2
133
R760
1
R758
C484
33P_0402_50V8J~D
2
1
23 CLK_ICH_48M
31 CLK_SMC_48M
8,10 CPU_MCH_BSEL0
8,10 CPU_MCH_BSEL1
Table : ICS954305AK
CPU_BSEL
1
49
54
65
33.3
100
166
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
+CK_VDD_A
2.2_0603_5%~D
1
R315
1
R310
CLK_3GPLLREQ# 1
R297
SATA_CLKREQ#
1
R283
LOM_CLKREQ#
1
R301
MINI2CLK_REQ#
CLK_SMC_48M
MINI1CLK_REQ#
R759
1
C774
3.3P_0402_50V8C~D
C708
3.3P_0402_50V8C~D
U28
CLK_ICH_48M
C479
0.047U_0402_16V4Z~D
FSA
C478
4.7U_0603_6.3V4Z~D
FSB
C189
0.047U_0402_16V4Z~D
1
2
@ R440
0_0402_5%~D
C799
0.047U_0402_16V4Z~D
FSC
+CK_VDD_REF
CLK_SCLK
+CK_VDD_48
C99
4.7U_0603_6.3V4Z~D
2
G
1
39 CKG_SMBCLK
Q35
2N7002W-7-F_SOT323-3~D
3
C474
0.1U_0402_16V4Z~D
1
2
L87
BLM21PG600SN1D_0805~D
+3.3V_RUN
+3.3V_RUN
1
C482
0.1U_0402_16V4Z~D
+CK_VDD_MAIN2
C473
0.1U_0402_16V4Z~D
C481
0.1U_0402_16V4Z~D
CLK_SDATA
3
Q34
2N7002W-7-F_SOT323-3~D
+CK_VDD_MAIN
1
2
L28
C472
10U_0805_10V4Z~D
C471
0.1U_0402_16V4Z~D
39 CKG_SMBDAT
R266
2.2K_0402_5%~D
2
1
@ R435
1
2
0_0402_5%~D
R265
2.2K_0402_5%~D
2
1
+3.3V_RUN
+CK_VDD_MAIN
C480
10U_0805_10V4Z~D
Thursday, March 01, 2007
Sheet
1
of
66
JCPUA
H_ADSTB#1
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]
H_LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
HIT#
HITM#
G6
E4
H_HIT#
H_HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
ITP_BPM#0
AD4
ITP_BPM#1
AD3
ITP_BPM#2
AD1
ITP_BPM#3
AC4
ITP_BPM#4
AC2
ITP_BPM#5
AC1
ITP_TCK
AC5
ITP_TDI
AA6
ITP_TDO
AB3
ITP_TMS
AB5
ITP_TRST#
AB6
C20 ITP_DBRESET#
CONTROL
H_LOCK#
10
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
10
10
10
10
10
T47
T48
T49
T50
T51
T52
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
THERMTRIP#
ITP_DBRESET# 23,38
H_THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
CLK_CPU_BCLK
CLK_CPU_BCLK#
A22
A21
6
6
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_CPU_ITP
CLK_CPU_ITP#
+1.05V_VCCP
29
@ MOLEX_52435-2891_28P~D
H_THERMDA 18
H_THERMDC
R321
22.6_0402_1%~D
1
2
EC_CPU_PROCHOT# 39
H_THERMDA
C7
H_RESET#
R323
56_0402_5%~D
EC_CPU_PROCHOT#
D21
A24
B25
+1.05V_VCCP
H_HIT# 10
H_HITM# 10
THERMAL
PROCHOT#
THERMDA
THERMDC
56_0402_5%~D
GND7
STPCLK#
LINT0
LINT1
SMI#
H4
R320
2
22
30
D5
C6
B4
A3
LOCK#
H_BR0# 10
H_INIT#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
H_IERR#
H_INIT#
JCPUD
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
A20M#
FERR#
IGNNE#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
XDP/ITP SIGNALS
A6
A5
C4
D20
B3
BR0#
+1.05V_VCCP
C417
2200P_0402_50V7K~D
H_THERMDC 18
H_THERMTRIP# 18
CLK_CPU_BCLK 6
CLK_CPU_BCLK# 6
H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil
1
C486
H_A20M#
H_FERR#
H_IGNNE#
IERR#
INIT#
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
0.1U_0402_16V4Z~D
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
H_BR0#
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
H_DEFER# 10
H_DRDY# 10
H_DBSY# 10
C485
H_STPCLK#
H_INTR
H_NMI
H_SMI#
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
F1
DEFER#
DRDY#
DBSY#
0.1U_0402_16V4Z~D
22
22
22
22
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
H5
F21
E1
H_DEFER#
H_DRD Y#
H_DBSY#
H_ADS# 10
H_BNR# 10
H_BPRI# 10
ITP_DBRESET#
ICH
22 H_A20M#
22 H_FERR#
22 H_IGNNE#
K3
H2
K2
J3
L1
H_ADS#
H_BNR#
H_BPRI#
Place near JITP
RESERVED
10
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H1
E2
G5
ADS#
BNR#
BPRI#
ADDR GROUP 1
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP 0
10
10
10
10
10
H_ADSTB#0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
GND6
JITP
10
+1.05V_VCCP
H_A#[3..35]
10
+3.3V_SUS
R324
150_0402_5%~D
ITP_DBRESET#
1
2
TYCO_1-1674770-2_Merom~D
+1.05V_VCCP
R325
51_0402_5%~D
B
ITP_TDO
R326
51_0402_1%~D
+1.05V_VCCP
R327
56_0402_5%~D
1
2 H_THERMTRIP#
H_RESET#
R328
39_0402_1%~D
ITP_TMS
R330
150_0402_5%~D
ITP_TDI
This shall place near CPU

R331
649_0402_1%~D
1
2
ITP_TRST#
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
R332
27_0402_1%~D
ITP_TCK
5
Title
Merom Processor(1/2)
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
of
66
+VCC_CORE
+VCC_CORE
JCPUC
10
H_D#[0..63]
1
2
1
2
10,22,48
22
10
22
10
48
BSEL[0]
BSEL[1]
BSEL[2]
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PW RGOOD
H_CPUSLP#
H_PSI#
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA[1]
VCCA[2]
B26
C26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
AF7
VCCSENSE
VSSSENSE
AE7
VSSSENSE
+1.05V_VCCP
1
+
2
CRB was 270uF
VID0
VID1
VID2
VID3
VID4
VID5
VID6
48
48
48
48
48
48
48
VCCSENSE
48
VSSSENSE
48
+1.5V_RUN
C489
E5
B5
D24
D6
D7
AE6
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
10U_0805_10V4Z~D
C488
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
R340
COMP0
COMP1
COMP2
COMP3
27.4_0402_1%~D
R26
U26
AA1
Y1
54.9_0402_1%~D
COMP[0]
COMP[1]
COMP[2]
COMP[3]
MISC
R339
CPU_MCH_BSEL0 B22
CPU_MCH_BSEL1 B23
CPU_MCH_BSEL2 C21
H_DSTBN#3 10
H_DSTBP#3 10
H_DINV#3 10
27.4_0402_1%~D
6,10 CPU_MCH_BSEL0
6,10 CPU_MCH_BSEL1
6,10 CPU_MCH_BSEL2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
R338
TSET1
TEST2
TEST3
TEST4
TEST5
TEST6
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R337
GTLREF
C23
D25
C24
AF26
AF1
A26
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
H_DSTBN#2 10
H_DSTBP#2 10
H_DINV#2 10
54.9_0402_1%~D
AD26
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
0.01U_0402_16V7K~D
V_CPU_GTLREF
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
C487
H_DSTBN#1
H_DSTBP#1
H_DINV#1
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
220U_D2_4VY_R15M~D
10
10
10
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
DATA GRP 1
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
DATA GRP 3
H_DSTBN#0
H_DSTBP#0
H_DINV#0
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 0
10
10
10
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP 2
JCPUB
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
Resistor placed within 0.5" of

CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.
R394
0_0402_5%~D
1
2
C490
0.1U_0402_16V4Z~D
@R336
1K_0402_5%~D
1
2
@R335
1K_0402_5%~D
1
2
TEST1
TEST2
TEST4
TEST6
PAD~D T30
PAD~D T31
TEST3
TEST5
Length match within 25 mils, Z0=27.4 ohm

B
Place R342 and R343 near CPU
+VCC_CORE
R342
For the purpose of testability, route these signals

through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
VCCSENSE
100_0402_1%~D
R343
1
VSSSENSE
100_0402_1%~D
FSB
BCLK
BSEL2
BSEL1
BSEL0
533
133
667
166
+1.05V_VCCP
Route VCCSENSE and VSSSENSE trace at

27.4 ohms, 7 mils spacing and 1 inch (max)
Place C490 close to the

CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.
R341
V_CPU_GTLREF
200
1K_0402_1%~D
2
800
R344
2K_0402_1%~D
2
Layout close CPU PIN AD26

55 ohm, 0.5 inch (max)
3
Title
Merom Processor(2/2)
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
of
66
+VCC_CORE
Place these inside 1

socket cavity on L8
(North side
Secondary)
2
1
C329
10U_0805_4VAM~D
2
1
C330
10U_0805_4VAM~D
1
C331
10U_0805_4VAM~D
1
C332
10U_0805_4VAM~D
C333
10U_0805_4VAM~D
C334
10U_0805_4VAM~D
2
1
C335
10U_0805_4VAM~D
1
C336
10U_0805_4VAM~D
1
C55
10U_0805_4VAM~D
C190
10U_0805_4VAM~D
+VCC_CORE

socket cavity on L8
(Sorth side
Secondary)
2
1
C222
10U_0805_4VAM~D
2
1
C223
10U_0805_4VAM~D
1
C224
10U_0805_4VAM~D
1
C225
10U_0805_4VAM~D
C227
10U_0805_4VAM~D
C226
10U_0805_4VAM~D
2
1
C228
10U_0805_4VAM~D
1
C229
10U_0805_4VAM~D
1
C69
10U_0805_4VAM~D
C185
10U_0805_4VAM~D
+VCC_CORE

socket cavity on L8
(North side
Primary)
2
1
C363
10U_0805_4VAM~D
2
1
C64
10U_0805_4VAM~D
1
C65
10U_0805_4VAM~D
1
C66
10U_0805_4VAM~D
1
C67
10U_0805_4VAM~D
C68
10U_0805_4VAM~D
+VCC_CORE

socket cavity on L8
(Sorth side
Primary)
2
1
C364
10U_0805_4VAM~D
2
1
C50
10U_0805_4VAM~D
1
C51
10U_0805_4VAM~D
1
C52
10U_0805_4VAM~D
10uF 0805 X6S -> 85 degree C
1
C53
10U_0805_4VAM~D
C54
10U_0805_4VAM~D
C
High Frequence Decoupling
Near VCORE regulator.
1
+
2
1
+
2
C365
220U_X_2VM_R7M~D
@ C338
220U_X_2VM_R7M~D
C366
220U_X_2VM_R7M~D
@ C178
220U_X_2VM_R7M~D
+VCC_CORE
C179
220U_X_2VM_R7M~D
South Side Secondary
C177
220U_X_2VM_R7M~D
+VCC_CORE
1
+
2
North Side Secondary
ESR <= 1.5m ohm

Capacitor > 1980uF
+
2
1
C870
0.1U_0402_10V7K~D
@
1
C871
0.1U_0402_10V7K~D
@
1
C872
0.1U_0402_10V7K~D
@
C873
0.1U_0402_10V7K~D
@
BITs WI97837
+1.05V_VCCP
1
C312
0.1U_0402_10V7K~D
1
C256
0.1U_0402_10V7K~D
1
C293
0.1U_0402_10V7K~D
1
C250
0.1U_0402_10V7K~D
1
C310
0.1U_0402_10V7K~D
C264
0.1U_0402_10V7K~D
Place these inside

socket cavity on L8
(North side
Secondary)
Title
CPU Bypass
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
of
66
H_SCOMP
H_SCOMP#
H_RESET#
H_CPUSLP#
B6
E5
H_CPURST#
H_CPUSLP#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
8
8
8
8
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L7
K2
AC2
AJ10
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
8
8
8
8
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
M14
E13
A11
H13
B12
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
E12
D7
D8
H_RS#0
H_RS#1
H_RS#2
R350
B9
A9
H_VREF
H_AVREF
H_DVREF
R346
20_0402_1%~D
C491
0.1U_0402_16V4Z~D
V_DDR_MCH_REF
1
6 CLK_MCH_3GPLL
6 CLK_MCH_3GPLL#
8
8
8
8
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
7
7
7
1
2
C498
0.01U_0402_16V7K~D
R363
1K_0402_1%~D
23
23
23
23
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
23
23
23
23
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
23
23
23
23
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
SM_RCOMP
SM_RCOMP#
BK31
BL31
SM_RCOMP_VOH
SM_RCOMP_VOL
V_DDR_MCH_REF
AR49
AW4
SM_VREF_0
SM_VREF_1
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
B42
C42
H48
H47
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
K44
K45
PEG_CLK
PEG_CLK#
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
AN47
AJ38
AN42
AN46
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
AM47
AJ39
AN41
AN45
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
AJ46
AJ41
AM40
AM44
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
AJ47
AJ42
AM39
AM43
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
T42
T43
T44
T45
E35
A39
C38
B39
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
PAD~D T46
E36
GFX_VR_EN
CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
CL_VREF
6 CLK_3GPLLREQ#
23 MCH_ICH_SYNC#
CLK_3GPLLREQ#
MCH_ICH_SYNC#
R774
2
2
AM49
AK50
AT43
AN49
AM50
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
H35
K36
G39
G40
0_0402_5%~D
A37
1
R32
1
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
TEST_1
TEST_2
R357
20K_0402_5%~D
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
CFG5
CFG9
CFG16
CFG19
CFG20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
G41
L39
L36
J36
AW49
AV20
N20
G36
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
CPU_MCH_BSEL0 6,8
CPU_MCH_BSEL1 6,8
CPU_MCH_BSEL2 6,8
T63 PAD~D
T64 PAD~D
CFG5
12
T65 PAD~D
T66 PAD~D
T67 PAD~D
CFG9
12
T68 PAD~D
T69 PAD~D
T70 PAD~D
T71 PAD~D
T72 PAD~D
T73 PAD~D
CFG16
12
T74 PAD~D
T75 PAD~D
CFG19
12
CFG20
12
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR
+1.05V_VCCP
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
23
8,22,48
16
17
23,42
THERMTRIP_MCH# 18
DPRSLPVR
23,48
PM_EXTTS#0
+3.3V_RUN
R352
10K_0402_5%~D
2
1
R354
10K_0402_5%~D
PM_EXTTS#1 2
1
R589
@ 0_0402_5%~D
2
1
R36
LE88CLPM A0 QM21_FCBGA1299~D
100_0402_5%~D
PLTRST1#_R 1
2
THERMTRIP_MCH# 1
R358
56_0402_5%~D
SMRCOMP_VOL
2
2
C497
0.1U_0402_16V4Z~D
2K_0402_1%~D
R362
100_0402_1%~D
C496
0.1U_0402_16V4Z~D
H_SWNG
R361
BL15
BK14
C495
2.2U_0603_6.3V6K~D
R359
3.01K_0402_1%~D
C494
0.01U_0402_16V7K~D
221_0402_1%~D
H_VREF
1K_0402_1%~D
SMRCOMP
SMRCOMP#
SMRCOMP_VOH
SMRCOMP_VOL
C493
0.1U_0402_16V4Z~D
SMRCOMP_VOH
+1.05V_VCCP
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
1
R351
392_0402_1~D
R353
1K_0402_1%~D
R356
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
23
CL_CLK0
23
CL_DATA0
23,39 ICH_CL_PWROK
23 CL_RST0#
R349
1K_0402_1%~D
+1.8V_SUS
R355
BH18
BJ15
BJ14
BE16
NC
+1.05V_VCCP
Layout Note:
H_RCOMP trace width
and spacing is 10/20
M_ODT0
M_ODT1
M_ODT2
M_ODT3
+1.25V_RUN
C499
2.2U_0603_6.3V6K~D
23
23
23
23
PAD~D
PAD~D
PAD~D
PAD~D
7
7
7
7
7
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
H_ADS#
7
H_ADSTB#0
7
H_ADSTB#1
7
H_BNR#
7
H_BPRI#
7
H_BR0#
7
H_DEFER#
7
H_DBSY#
7
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
H_DPWR#
8
H_DRDY#
7
H_HIT#
7
H_HITM#
7
H_LOCK# 7
H_TRDY#
7
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
BG20
BK16
BG16
BE13
24.9_0402_1%~D
M_ODT0
M_ODT1
M_ODT2
M_ODT3
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
DDR
M7
K3
AD2
AH11
R345
20_0402_1%~D
1
2
1
2
16
16
17
17
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
CLK
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
BE29
AY32
BD39
BG37
DMI
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_SWING
H_RCOMP
K5
L2
AD13
AE13
16
16
17
17
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
ME
W1
W2
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
MISC
H_RESET#
H_CPUSLP#
B3
C2
H_SCOMP
H_SCOMP#
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRD Y#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
+1.8V_SUS
16
16
17
17
AW30
BA23
AW25
AW23
PM
7
8
H_SWNG
H_RCOMP
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
1
2
54.9_0402_1%~D
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
CFG
R347
54.9_0402_1%~D
R348
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
16
16
17
17
AV29
BB23
BA25
AV23
RSVD
+1.05V_VCCP
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
GRAPHICS VID
U29A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_A#[3..35]
C492
0.1U_0402_16V4Z~D
H_D#[0..63]
HOST
16
16
17
17
MUXING
U29B
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
SB_NB_PCIE_RST# 21
R583
0_0402_5%~D
2
1PLTRST1#
PLTRST1#
21
Title
Crestline(1 of 6)
Size
Date:
Document Number
Rev
0.4
LA-3302P
Sheet
1
10
of
66
DDR_A_D[0..63] 16
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BJ29
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BL17
BE18
BA19
SA_CAS#
SA_RAS#
SA_WE#
AY20
SA_RCVEN#
16 DDR_A_MA[0..14]
16 DDR_A_CAS#
16 DDR_A_RAS#
16 DDR_A_WE#
T10
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVEN#
MEMORY
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SYSTEM
16 DDR_A_DQS#[0..7]
DDR
16 DDR_A_DQS[0..7]
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
DDR_B_D[0..63] 17
U29E
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
17 DDR_B_BS0
17 DDR_B_BS1
17 DDR_B_BS2
17 DDR_B_DM[0..7]
AY17
BG18
BG36
SB_BS_0
SB_BS_1
SB_BS_2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE24
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
BE17
AV16
BC17
SB_CAS#
SB_RAS#
SB_WE#
SB_RCVEN#
AY18
SB_RCVEN#
17 DDR_B_DQS[0..7]
17 DDR_B_DQS#[0..7]
17 DDR_B_MA[0..14]
17 DDR_B_CAS#
17 DDR_B_RAS#
17 DDR_B_WE#
T11
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
MEMORY
SA_BS_0
SA_BS_1
SA_BS_2
SYSTEM
BB19
BK19
BF29
DDR
U29D
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
16 DDR_A_BS0
16 DDR_A_BS1
16 DDR_A_BS2
16 DDR_A_DM[0..7]
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
Title
Crestline(2 of 6)
Size
Date:
Document Number
Rev
0.4
LA-3302P
Sheet
1
11
of
66
+VCC_PEG
R366
24.9_0402_1%~D
Strap Pin Table
U29C
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
D46
C45
D44
E42
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
G51
E51
F49
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
G50
E50
F48
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
G44
B47
B45
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
E44
A47
A45
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
E27
G27
K27
M35
P33
TV_DCONSEL_0
TV_DCONSEL_1
H32
G32
K29
J29
F29
E29
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
K33
G35
F33
E33
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
C32
CRT_TVO_IREF
VGA
TVA_RTN
TVB_RTN
TVC_RTN
TV
TVA_DAC
TVB_DAC
TVC_DAC
F27
J27
L27
N43 PEGCOMP
M43
Low = DMI x 2
CFG5
DMI X2 Select
CFG9
PCI Express
Graphic Lane
Low = Reverse Lane
CFG16
FSB Dynamic
ODT
Low=Dynamic ODT Disable
DMI Lane
Reversal
Low=Normal (default)
SDVO/PCIE
Concurrent
Operation
High = DMI x 4 (Default)
PEG_MRX_GTX_N[0..15] 52
GRAPHICS
L41
L43
N41
N40
PEG_COMPI
PEG_COMPO
LVDS
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
PCI-EXPRESS
J40
H39
E39
E40
C37
D35
K40
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
PEG_MRX_GTX_N0
PEG_MRX_GTX_N1
PEG_MRX_GTX_N2
PEG_MRX_GTX_N3
PEG_MRX_GTX_N4
PEG_MRX_GTX_N5
PEG_MRX_GTX_N6
PEG_MRX_GTX_N7
PEG_MRX_GTX_N8
PEG_MRX_GTX_N9
PEG_MRX_GTX_N10
PEG_MRX_GTX_N11
PEG_MRX_GTX_N12
PEG_MRX_GTX_N13
PEG_MRX_GTX_N14
PEG_MRX_GTX_N15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
PEG_MRX_GTX_P0
PEG_MRX_GTX_P1
PEG_MRX_GTX_P2
PEG_MRX_GTX_P3
PEG_MRX_GTX_P4
PEG_MRX_GTX_P5
PEG_MRX_GTX_P6
PEG_MRX_GTX_P7
PEG_MRX_GTX_P8
PEG_MRX_GTX_P9
PEG_MRX_GTX_P10
PEG_MRX_GTX_P11
PEG_MRX_GTX_P12
PEG_MRX_GTX_P13
PEG_MRX_GTX_P14
PEG_MRX_GTX_P15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_N15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_P15
CFG19
PEG_MRX_GTX_P[0..15] 52
CFG20
SDVO_CRTL_DATA
High = Normal Operation (Default)
High=Dynamic ODT Enable(default)
10
CFG5
R365 1
2 @ 4.02K_0402_1%~D
Low=Only SDVO or PCIEx1 is

operational (defaults)
10
CFG9
R368 1
2 @ 4.02K_0402_1%~D
High=SDVO and PCIEx1 are operating

simultaneously via PEG port
10
CFG16
R372 1
2 @ 4.02K_0402_1%~D
High=Lane Reversed
CFG[3:17] have internal pullup
Low=No SDVO Device Present

(default)
High=SDVO Device Present
+3.3V_RUN
PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_N[0..15]
PEG_MTX_GRX_P[0..15] 52
PEG_MTX_GRX_N[0..15] 52
10
10
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0
C500 1
2 0.1U_0402_10V7K~D
C501 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1
C502 1
2 0.1U_0402_10V7K~D
C503 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_N2
C504 1
2 0.1U_0402_10V7K~D
C505 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3
C506 1
2 0.1U_0402_10V7K~D
C507 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
2 @ 4.02K_0402_1%~D
CFG20
R374 1
2 @ 4.02K_0402_1%~D
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_N4
C508 1
2 0.1U_0402_10V7K~D
C509 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5
C510 1
2 0.1U_0402_10V7K~D
C511 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6
C512 1
2 0.1U_0402_10V7K~D
C513 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7
C514 1
2 0.1U_0402_10V7K~D
C515 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8
C516 1
2 0.1U_0402_10V7K~D
C517 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9
C518 1
2 0.1U_0402_10V7K~D
C519 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_N10
C520 1
2 0.1U_0402_10V7K~D
C521 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_N11
C522 1
2 0.1U_0402_10V7K~D
C523 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_N12
C524 1
2 0.1U_0402_10V7K~D
C525 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_N13
C526 1
2 0.1U_0402_10V7K~D
C527 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_N14
C528 1
2 0.1U_0402_10V7K~D
C529 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_C_P15
PEG_MTX_GRX_C_N15
C530 1
2 0.1U_0402_10V7K~D
C531 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
Title
Crestline(3 of 6)
Size
Document Number
Rev
0.4
LA-3302P
Date:
R373 1
CFG[18:19] have internal pulldown
CFG19
Sheet
1
12
of
66
U48
1
VCCD_LVDS_1
VCCD_LVDS_2
J41
H42
2
C567
10U_0805_4VAM~D
2
1
+1.05V_VCCP
R409
1_0402_5%~D
+1.25V_RUN
+1.25V_RUN_PEGPLL 1
+1.25V_RUN_PEGPLL
+1.5V_RUN
1
2
B
+1.25V_RUN_HPLL
45mA Max.
C571
0.1U_0402_16V4Z~D
+1.25V_RUN
+1.8V_SUS
+1.8V_SM_CK
L41
Place caps close

to VCC_AXF (Pin
A21, B21, B23)
C574
C573
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C575
22U_0805_6.3VAM~D
+1.05V_VCCP
+3.3V_RUN
2
1
1
2
D16
RB751V_SOD323~D
R417
10_0603_5%~D

Title
Crestline(4 of 6)
Size
Document Number
Rev
0.4
LA-3302P
Date:
+1.25V_RUN
L38
2
1
BLM18AG121SN1D_0603~D
45mA Max.
C593
22U_0805_6.3V6M~D
C594
10U_0805_4VAM~D
2
1
C592
0.1U_0402_16V4Z~D
1
R416
1_0603_5%~D
C590
10U_0805_4VAM~D
C589
1U_0603_10V4Z~D
2
1
1
1
+1.25V_RUN_MPLL
+1.25V_RUN
L37
C572
22U_0805_6.3VAM~D
AN2
C556
220U_D2_4VY_R15M~D
CLK
PEG
DMI
VCCD_HPLL
VCCD_PEG_PLL
+1.25V_RUN
L35
1
2
+1.25V_RUN
C554
0.1U_0402_16V4Z~D
VTTLF
N28
2
R408
0_0603_5%~D
L34
BLM18PG181SN1_0603~D
2
1
C568
VCCD_QDAC
+1.05V_VCCP
0.1U_0402_16V4Z~D
M32
L29
L32
2
1
C584
VCCD_CRT
VCCD_TVDAC
0.1U_0402_16V4Z~D
VCC_RXR_DMI_1
VCC_RXR_DMI_2
C566
1U_0603_10V4Z~D
AH50
AH51
C25
B25
C27
B27
B28
A28
0_0805_5%~D
1
C561
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
C562
22U_0805_6.3V6M~D
+VCCA_SM_CK
VCC_HV_1
VCC_HV_2
VTTLF1
VTTLF2
VTTLF3
R406
+VCC_RXR_DMI
+1.25V_RUN
1
+
C557
10U_0805_4VAM~D
C565
1U_0603_10V4Z~D
BC29
BB29
LVDS
+1.25V_RUN_PEGPLL
C564
22U_0805_6.3V6M~D
VCCA_SM_CK_1
VCCA_SM_CK_2
VCC_TX_LVDS
TV/CRT
22U_0805_6.3V6M~D
C560
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
C578
0.47U_0402_10V4Z~D
C577
0.47U_0402_10V4Z~D
C576
0.47U_0402_10V4Z~D
U51
+VCC_PEG
+3.3V_RUN
C558
100U_D2E_6.3VM_R18M~D
VCC_DMI
AD51
W50
W51
V49
V50
A7
F2
AH1
VCCA_PEG_PLL
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
TV
C597
0.1U_0402_16V4Z~D
+VCC_RXR_DMI
VCCA_PEG_BG
VSSA_PEG_BG
K50
K49
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
+VCC_PEG
B41
C563
0.1U_0402_16V4Z~D
C40
B40
1
A41
VSSA_LVDS
+VCCA_SM
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
POWER
+3.3V_RUN
VCCA_LVDS
4.7U_0603_6.3V6M~D
C559
A43
+1.25V_RUN_MPLL
1U_0603_10V4Z~D
+1.25V_RUN_HPLL
AM2
VCC_AXD_NCTF
SM
BK24
BK23
BJ24
BJ23
AL2
VCCA_MPLL
C583
0.022U_0402_16V7K~D
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
+1.8V_SM_CK
C591
0.1U_0402_16V4Z~D
H49
VCCA_HPLL
C582
10U_0805_4VAM~D
AJ50
B49
VCCA_DPLLB
10U_0805_4VAM~D
C549
B23
B21
A21
VCCA_DPLLA
220U_D2_4VY_R15M~D
C548
AR29
+1.25V_RUN
C550
0.1U_0402_16V4Z~D
C552
+1.25V_RUN
1U_0603_10V4Z~D
C551
22U_0805_6.3V6M~D
B32
PEG
AT23
AU28
AU24
AT29
AT25
AT30
L33
2
1
A30
VSSA_DAC_BG
LVDS
+1.25V_RUN
VCCA_DAC_BG
C642
0.1U_0402_16V4Z~D
A33
B33
PLL
C544
2.2U_0603_6.3V6K~D
C543
4.7U_0603_6.3V6M~D
J32
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VTT
AXD
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
AXF
VCCSYNC
CRT
C535
C542
4.7U_0603_6.3V6M~D
220U_D2_4VY_R15M~D
U13
U12
U11
U9
U8
U7
2
U5
U3
U2
U1
T13
T11
T10
T9
1
T7
T6
T5
2
T3
T2
R3
R2
R1
+1.25V_RUN_AXD
U29H
C537
0.47U_0402_10V4Z~D
+1.05V_VCCP
CRB 270uF
Sheet
1
13
of
66
+1.05V_VCCP
+1.05V_VCCP
U29G
D17
+3.3V_RUN
R420
10_0603_5%~D
1
2
2
1
3
U29F
C620
0.1U_0402_10V7K~D
C619
0.1U_0402_10V7K~D
C618
0.1U_0402_10V7K~D
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
AW45
BC39
BE39
BD17
BD4
AW8
AT6
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
C627
1U_0402_6.3V4Z~D
C626
1U_0402_6.3V4Z~D
C625
0.47U_0402_10V4Z~D
C624
0.22U_0402_10V4Z~D
C623
0.22U_0402_10V4Z~D
C622
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
0.1U_0402_10V7K~D
C621
R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
0.1U_0402_10V7K~D
Layout Note: Inside GMCH cavity.
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC GFX NCTF
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
VCC GFX
Layout Note:
Place
close to GMCH edge.
VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19
Layout Note:
Place on the edge
+1.05V_VCCP
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_6
VCC_AXM_5
VCC_AXM_7
VCC_13
VCC SM
C617
0.22U_0402_10V4Z~D
C616
0.22U_0402_10V4Z~D
C615
22U_0805_6.3V6M~D
Layout Note:
Place C901 where
LVDS and DDR2 taps.
POWER
+1.05V_VCCP
AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33
C607
Layout Note:
Inside GMCH cavity.
A3
B2
C1
BL1
BL51
A51
C605
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
R30
POWER
330U_D2E_2.5VM~D
C614
0.1U_0402_10V7K~D
C613
0.22U_0402_10V4Z~D
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
+1.8V_SUS
C608
Layout Note:
370 mils from edge
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
22U_0805_6.3V6M~D
C606
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
22U_0805_6.3V6M~D
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50
0.1U_0402_10V7K~D
C604
0.22U_0402_10V4Z~D
C603
22U_0805_6.3VAM~D
C602
220U_D2_4VY_R15M~D
AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
VCC CORE
BAT54CW_SOT323~D
+1.05V_VCCP
VCC SM LF
Title
Crestline(5 of 6)
Size
Date:
Document Number
Rev
0.4
LA-3302P
Sheet
1
14
of
66
U29I
A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
U29J
C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
VSS
Title
Crestline(6 of 6)
Size
Date:
Document Number
Rev
0.4
LA-3302P
Sheet
1
15
of
66
+1.8V_SUS
+1.8V_SUS
ON TOP SIDE
11 DDR_A_DQS#[0..7]
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D3
DDR_A_D7
DDR_A_D13
DDR_A_D12
+1.8V_SUS
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
C116
C117
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C437
C132
2.2U_0603_6.3V6K~D
C133
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_A_D17
DDR_A_D21
DDR_A_D22
DDR_A_D23
C118
0.1U_0402_16V4Z~D
C119
C131
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C130
0.1U_0402_16V4Z~D
DDR_A_D29
DDR_A_D25
DDR_A_DM3
DDR_A_D27
DDR_A_D30
10 DDR_CKE0_DIMMA
11
DDR_A_BS2
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
11
11
DDR_A_BS0
DDR_A_WE#
11 DDR_A_CAS#
10 DDR_CS1_DIMMA#
+0.9V_DDR_VTT
10
M_ODT1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D33
DDR_A_D32
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D39
2
C707
C110
C109
C108
C107
C106
C105
C104
C141
C140
C139
C138
C137
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C136
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_A_D41
DDR_A_D40
DDR_A_DM5
DDR_A_D46
DDR_A_D43
DDR_A_D49
DDR_A_D52
+0.9V_DDR_VTT
RN4
DDR_A_MA1
1
DDR_A_MA3
2
56_0404_4P2R_5%~D
RN12
4
3
RN5
4
3
4
3
4
3
4
3
DDR_A_DM7
DDR_A_D58
DDR_A_D62
1 DDR_A_MA4
2 DDR_A_MA2
56_0404_4P2R_5%~D
MEM_SDATA
17,23 MEM_SDATA
MEM_SCLK
17,23 MEM_SCLK
+3.3V_RUN
4
3
RN8
DDR_CKE1_DIMMA 2
1
R223
56_0402_5%~D
RN13
RN7
DDR_CKE0_DIMMA 2
DDR_A_BS2
1
56_0404_4P2R_5%~D
1 M_ODT0
2 DDR_A_MA13
56_0404_4P2R_5%~D
4
3
3
4
4
3
1 DDR_A_MA14
2 DDR_A_MA11
56_0404_4P2R_5%~D
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
C115
2.2U_0603_6.3V6K~D
1 DDR_A_MA0
2 DDR_A_BS1
56_0404_4P2R_5%~D
C113
4
3
0.1U_0402_16V4Z~D
DDR_A_D60
DDR_A_D56
1 DDR_A_MA5
2 DDR_A_MA8
56_0404_4P2R_5%~D
RN10
RN1
M_ODT1
1
DDR_CS1_DIMMA# 2
56_0404_4P2R_5%~D
DDR_A_D51
DDR_A_D54
Layout Note:
closely DIMM0,all
trace length<750 mil
RN11
RN2
DDR_A_CAS#
1
DDR_A_WE#
2
56_0404_4P2R_5%~D
1 DDR_A_MA7
2 DDR_A_MA6
56_0404_4P2R_5%~D
4
3
RN9
DDR_A_RAS#
1
DDR_CS0_DIMMA# 2
56_0404_4P2R_5%~D
1 DDR_A_MA9
2 DDR_A_MA12
56_0404_4P2R_5%~D
4
3
RN3
DDR_A_BS0
1
DDR_A_MA10
2
56_0404_4P2R_5%~D
DDR_A_DQS#6
DDR_A_DQS6
RN6
4
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDR_A_D4
DDR_A_D6
DDR_A_DM0
DDR_A_D1
DDR_A_D2
DDR_A_D9
DDR_A_D8
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 10
M_CLK_DDR#0 10
DDR_A_D15
DDR_A_D14
DDR_A_DQS#2
DDR_A_DQS2
1
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C112
11 DDR_A_MA[0..14]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C114
DDR_A_D0
DDR_A_D5
Layout Note:
Place near JDIM1
11 DDR_A_DQS[0..7]
0.1U_0402_16V4Z~D
JDIM2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
11 DDR_A_DM[0..7]
2.2U_0603_6.3V6K~D
11 DDR_A_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF
201
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
GND
202
DDR_A_D20
DDR_A_D16
PM_EXTTS#0
DDR_A_DM2
PM_EXTTS#0 10
DDR_A_D18
DDR_A_D19
DDR_A_D28
DDR_A_D24
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D31
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA 10
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_BS1 11
DDR_A_RAS# 11
DDR_CS0_DIMMA# 10
M_ODT0
10
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D35
DDR_A_D38
DDR_A_D44
DDR_A_D45
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D42
DDR_A_D47
DDR_A_D48
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 10
M_CLK_DDR#1 10
DDR_A_DM6
DDR_A_D50
DDR_A_D55
DDR_A_D61
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D59
DDR_A_D63
R122 1
R127 1
2 10K_0402_5%~D
2 10K_0402_5%~D
TYCO_1470815-2~D
DIMMA
RESERVE
Title
DDRII-SODIMM SLOT1
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
16
of
66
+1.8V_SUS
11 DDR_B_DQS#[0..7]
V_DDR_MCH_REF
+1.8V_SUS
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D21
DDR_B_DQS#2
DDR_B_DQS2
C414
C411
C413
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
C433
C438
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C412
C434
0.1U_0402_16V4Z~D
C440
2.2U_0603_6.3V6K~D
C439
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
DDR_B_D19
DDR_B_D18
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
10 DDR_CKE2_DIMMB
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
11
DDR_B_BS2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
11
11
+0.9V_DDR_VTT
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
11 DDR_B_CAS#
10 DDR_CS3_DIMMB#
M_ODT3
M_ODT3
DDR_B_D32
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4
C405
C406
C407
C408
C409
C410
C450
C451
C452
C453
C454
C455
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C456
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10
DDR_B_D35
DDR_B_D34
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D46
DDR_B_D42
DDR_B_D53
DDR_B_D49
+0.9V_DDR_VTT
RN21
RN23
DDR_B_MA1
1
DDR_B_MA3
2
56_0404_4P2R_5%~D
4
3
4
3
RN22
4
3
4
3
4
3
4
3
DDR_B_MA5
1
DDR_B_MA8
2
56_0404_4P2R_5%~D
DDR_B_DM7
DDR_B_D58
DDR_B_D59
RN15
DDR_B_MA7
1
DDR_B_MA6
2
56_0404_4P2R_5%~D
MEM_SDATA
16,23 MEM_SDATA
MEM_SCLK
16,23 MEM_SCLK
+3.3V_RUN
RN20
RN26
DDR_CS3_DIMMB# 2
M_ODT3
1
3
4
56_0404_4P2R_5%~D
M_ODT2
1
DDR_B_MA13
2
56_0404_4P2R_5%~D
4
3
4
3
DDR_B_BS2
1
DDR_CKE2_DIMMB
2
56_0404_4P2R_5%~D
Layout Note:
closely DIMM0,all
trace length
Max=1.3"
C429
RN19
DDR_CKE3_DIMMB 2
1
R312
56_0402_5%~D
C431
DDR_B_MA4
1
DDR_B_MA2
2
56_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
RN16
201
GND
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
GND
202
DDR_B_D2
DDR_B_D3
DDR_B_D13
DDR_B_D12
DDR_B_DM1
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 10
M_CLK_DDR#2 10
DDR_B_D10
DDR_B_D11
DDR_B_D20
DDR_B_D17
PM_EXTTS#1
DDR_B_DM2
PM_EXTTS#1
10
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB 10
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_BS1 11
DDR_B_RAS# 11
DDR_CS2_DIMMB# 10
M_ODT2
DDR_B_MA13
M_ODT2
10
DDR_B_D33
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
B
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D43
DDR_B_D47
DDR_B_D52
DDR_B_D48
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 10
M_CLK_DDR#3 10
DDR_B_DM6
DDR_B_D54
DDR_B_D51
DDR_B_D57
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
TYCO_1565917-4~D
DIMMB
STANDARD
+3.3V_RUN
1
R243
10K_0402_5%~D
R241
4
3
DDR_B_D56
DDR_B_D60
Layout Note:
closely DIMM0,all
trace length<750 mil
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DDR_B_DM0
10K_0402_5%~D
4
3
RN25
DDR_B_CAS#
1
DDR_B_WE#
2
56_0404_4P2R_5%~D
DDR_B_MA14
1
DDR_B_MA11
2
56_0404_4P2R_5%~D
4
3
RN18
DDR_B_RAS#
1
DDR_CS2_DIMMB# 2
56_0404_4P2R_5%~D
DDR_B_D55
DDR_B_D50
RN14
RN17
DDR_B_MA0
1
DDR_B_BS1
2
56_0404_4P2R_5%~D
DDR_B_MA9
1
DDR_B_MA12
2
56_0404_4P2R_5%~D
4
3
RN24
DDR_B_BS0
1
DDR_B_MA10
2
56_0404_4P2R_5%~D
DDR_B_DQS#6
DDR_B_DQS6
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_B_D5
DDR_B_D4
DDR_B_D6
DDR_B_D7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DDR_B_DQS#0
DDR_B_DQS0
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C436
11 DDR_B_MA[0..14]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C447
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DDR_B_D1
DDR_B_D0
0.1U_0402_16V4Z~D
Layout Note:
Place near JDIM2
11 DDR_B_DM[0..7]
2.2U_0603_6.3V6K~D
JDIM1
11 DDR_B_DQS[0..7]
V_DDR_MCH_REF
ON BOTTOM SIDE
11 DDR_B_D[0..63]
+1.8V_SUS
Title
DDRII-SODIMM SLOT2
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
17
of
66
FAN1 Control and Tachometer
R438
VSET=
+3.3V_SUS
x 3.3V =0.865V
R436+R438
+3.3V_RUN
R423
8.2K_0402_5%~D
Tp-70
=> Tp = 88.2 C
21
THERMATRIP1#
R424
10K_0402_5%~D
C628
0.1U_0402_16V4Z~D
FAN1_TACH
+5V_SUS
39
1
R772
@ D19
RB751S40T1_SOD523-2~D
2
+1.05V_VCCP
THERMATRIP2#
R427
C
2.2K_0402_5%~D
2
2
B
Q39 E
MMST3904-7-F_SOT323-3~D
22U_0805_6.3VAM~D
R426
8.2K_0402_5%~D
C630
+FAN1_VOUT
FAN1_TACH_FB
1
2
3
1
2
3
C750
2 2200P_0402_50V7K~D
Discrete
1
3
@ C633
2200P_0402_50V7K~D

Guardian pins as possible.
2
B
Q40
MMST3904-7-F_SOT323-3~D
C706
470P_0402_50V7K~D
Q41
MMST3904-7-F_SOT323-3~D
2
B
C649
2200P_0402_50V7K~D
Q41 Place near the

bottom SODIMM

Guardian pins as possible
REM_DIODE3_N, REM_DIODE3_P routing together.

Trace width / Spacing = 10 / 10 mil
VGA_THERMDN 53
Place Capacitor close to Guardian Chip
2200P_0402_50V7K~D
C634
This thermistor circuit is located near

Top side DDR connector.
VGA_THERMDN 2
5V_CAL_SIO#
VGA_THERMDP 53
1
10 THERMTRIP_MCH#
Q102
2N7002W-7-F_SOT323-3~D
2
G
PWR_MON 48
VGA_THERMDP
Place under CPU
R773
10K_0402_5%~D
2
D
MOLEX_53398-0371~D
C632
0.1U_0402_16V4Z~D
10K_0603_1%_TSM1A103F34D3RZ~D
+3.3V_SUS
VCP2
R771
2.21K_0603_1%~D
JFAN1
R414
0_0402_5%~D
7 H_THERMTRIP#
+3.3V_SUS
1
+1.05V_VCCP
R425
C
2.2K_0402_5%~D
1
2
2
B
Q38 E
MMST3904-7-F_SOT323-3~D
VSET =
C650
2200P_0402_50V7K~D
@
Place C650
close to Q41
Place C633 close to the Q40 as possible

U31
+RTC_CELL
1
C637
0.1U_0402_16V4Z~D
42 ICH_PWRGD#
DP4
DN4
35
3V_SUS
DP5
DN5
2
1
18
THERMATRIP3#
+3.3V_SUS
19
RTC_PWR3V
42
1
R436
332K_0402_1%~D
1
C100
2200P_0402_50V7K~D
10K_0402_5%~D
R438
118K_0402_1%~D
33 MDC_RST_DIS#
@ R194
1
2
1
MDC_RST_DIS#
SIO_GFX_PWR
10K_0402_5%~D
MDC_RST_DIS#
SIO_GFX_PWR
5V_CAL_SIO#
AUDIO_AVDD_ON
THERMATRIP3#
C
25
SYS_SHDN#
24
LDO_SHDN#/ADDR
27
LDO_POK
33
THERMTRIP3#
VSET
XEN
34
VSS
7
8
FAN_OUT
FAN_OUT
39
FAN_DAC1
10
13
14
15
22
36
49
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6/FAN_DAC2
PAD_GND
C645
10U_0805_10V4Z~D
R433
8.2K_0402_5%~D
THERM_B3 2
B
THERMTRIP_SIO
THERMTRIP2#
LDO_SET
28
LDO_OUT
LDO_OUT
32
31
LDO_IN
LDO_IN
30
29
VDD_3V
VDD_5V
VDD_5V
5
6
Q76
MMST3904-7-F_SOT323-3~D
2@
2200P_0402_50V7K~D
ATF_INT#
R434
2
1
7.5K_0402_5%~D
C418 close to Guardian and

C904 close to diode Q19.
+3.3V_SUS
R430
10K_0402_5%~D
2
1
39,49,50
+3.3V_ALW
THERMTRIP_SIO
THERM_STP#
2
1
+RTC_CELL
@ R431
10K_0402_5%~D
+3.3V_SUS
45
B
2.5V_RUN_PWRGD 42
LDO_SET
+3V_LDOIN
+5V_RUN
+2.5V_RUN
+2.5V_RUN
1
C641
0.1U_0402_16V4Z~D
@
R439
2
+3.3V_RUN
LDO_SET
+3.3V_RUN
1
Ra
0_1210_5%~D
C644
0.1U_0402_16V4Z~D
Rb
Voltage margining
circuit for LDO output.
For Vmargin, stuff
Ra=31.6K and Rb=30K.
Rb=1K for production
C648
0.1U_0402_16V4Z~D
C203
0.1U_0402_16V4Z~D
2@
52 THERMTRIP_VGA#
C904
2200P_0402_50V7K~D
@
38
POWER_SW# 39,40
ACAV_IN
R96
10K_0402_5%~D
2
1
ATF_INT#
SMBUS ADDRESS : 2F
1
1
1
2
R187
2.2K_0402_5%~D
2@
THERMTRIP1#
26
EMC4001_QFN48~D
+3.3V_SUS
+3.3V_RUN
R186
8.2K_0402_5%~D
ACAVAIL_CLR
3V_PWROK#
R441
1K_0402_1%~D
27 AUDIO_AVDD_ON
+FAN1_VOUT
Q19
MMST3904-7-F_SOT323-3~D
2
B
C418
R485
31.6K_0402_1%~D
@ R196
1
R437
1K_0402_5%~D
C639
0.1U_0402_16V4Z~D
+3.3V_SUS
POWER_SW#
20
ATF_INT#
VSUS_PWRGD
VGA_THERMDP
VGA_THERMDN
DP2
DN2
23
1
2
R429
1K_0402_5%~D
16
1
2
R432
1K_0402_5%~D
THERMATRIP1#
17
THERMATRIP2#
REM_DIODE4_P
REM_DIODE4_N
48
47
21
42 SUSPWROK
REM_DIODE3_P
REM_DIODE3_N
C646
0.1U_0402_16V4Z~D
C638
0.1U_0402_16V4Z~D
49.9_0603_1%~D
45
44
+3VSUS_THRM
DP3
DN3
41
40
R428
1
+3.3V_SUS
VCP2
DP1
DN1
43
46
7 H_THERMDC
38
37
Diode circuit at DP4/DN4 is used for skin temp

sensor (placed optimally between CPU, MCH and GPU).
VCP1
VCP2
REM_DIODE1_P
REM_DIODE1_N
1
C636
470P_0402_50V7K~D
SMDATA
SMBCLK
7 H_THERMDA
11
12
39,49 THRM_SMBDAT
39,49 THRM_SMBCLK
C647
C643
1@ C640
10U_0805_10V4Z~D 1U_0603_10V4Z~D 10U_0805_10V4Z~D
Place C636 close to the Guardian pins as possible
Title
FAN & Thermal Sensor

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
18
of
66
LCD_ACLKLCD_ACLK+
53
53
LCD_A2LCD_A2+
53
53
LCD_A1LCD_A1+
53
53
LCD_A0LCD_A0+
53
53
39 LCD_VCC_TEST_EN
52
+LCDVDD
38
2
C44
0.1U_0402_16V4Z~D
2
2
3
1
R155
10K_0402_5%~D
1
@ R156
LCD_SMBCLK 39
LCD_SMBDAT 39
2
0_0402_5%~D
BIA_PWM
+5V_ALW
LAMP_STAT#
Q7
DDTC124EUA-7-F_SOT323-3~D
1
2
R527
0_0402_5%~D
0.1U_0402_16V4Z~D
+3.3V_RUN
2
@ R25
100K_0402_5%~D
BAT54CW_SOT323~D
+3.3V_RUN
LCD_TST
ENVDD
2
G
LCD_DDCCLK 52
LCD_DDCDATA 52
C45
LCD_TST
2
G
S
LCD_A0LCD_A0+
LCD_DDCCLK
LCD_DDCDATA
D24
LCD_A1LCD_A1+
LCD_A2LCD_A2+
LCD_ACLKLCD_ACLK+
53
53
LCD_B0LCD_B0+
LCD_B0LCD_B0+
R24
100K_0402_5%~D
R23
100K_0402_5%~D
R26
470_0402_5%~D
53
53
C30
0.1U_0603_50V4Z~D
53
53
LCD_B1LCD_B1+
+3.3V_RUN
6
5
2
1
Q8
2N7002W-7-F_SOT323-3~D
LCD_B2LCD_B2+
+15V_ALW
Q9
2N7002W-7-F_SOT323-3~D
LCD_B1LCD_B1+
Q11
SI3456BDV-T1-E3_TSOP6~D
+LCDVDD
+LCDVDD
1
LCD_B2LCD_B2+
+15V_ALW
53
53
LCD_BCLKLCD_BCLK+
LCD_BCLKLCD_BCLK+
52
Populate R155 and de-pop R156

for discrete because it
doesn't support DPST
T28 PAD~D
1
C176
0.1U_0402_16V4Z~D
+3.3V_RUN
2
G
I2CH_SCL
I2CH_SCL 52
@ Q12
2N7002W-7-F_SOT323-3~D
+3.3V_RUN
3
S
LCD_SMBDAT
2
G
I2CH_SDA
+INV_PWR_SRC
40mil
8
7
6
5
1
2
3
1
R154
200K_0402_5%~D
C174
0.1U_0603_50V4Z~D
I2CH_SDA 52
R153
1
2
1
100K_0402_5%~D
Q25
3 2N7002W-7-F_SOT323-3~D
2
G
@ Q13
2N7002W-7-F_SOT323-3~D
C463
2200P_0402_50V7K~D
C180
0.1U_0603_50V4Z~D
C427
0.1U_0603_50V4Z~D
LCD_SMBCLK
+INV_PWR_SRC
Q24
FDS4435BZ_SO8~D
+PWR_SRC
40mil
IPEX_20330-044E-11F~D
C173
1000P_0402_50V7K~D
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TXUCLKUTTXUCLKUT+
GND1
TXUOUT2TXUOUT2+
GND2
TXUOUT1TXUOUT1+
GND3
TXUOUT0TXUOUT0+
GND4
TXLCLKOUTTXLCLKOUT+
GND5
TXLOUT2TXLOUT2+
GND6
TXLOUT1TXLOUT1+
GND7
TXLOUT0TXLOUT0+
GND8
PANEL_I2C_CLK
PANEL_I2C_DAT
GND9
VEDID
GND10
LCDVDD1
LCDVDD2
PNL_SLFTST
LCDPWR_SRC
LCDPWR_SRC
LCDPWR_SRC
GND11
FPBACK
GND12
PBAT_SMBCLK
PBAT_SMBDAT
GND13
+5V_ALWF
LAMP_START
GND14
MGND1
MGND2
MGND3
MGND4
MGND5
MGND6
MGND7
MGND8
MGND9
MGND10
MGND11
NC
NC
C42
0.1U_0402_16V4Z~D
JLVDS
45
46
47
48
49
50
51
52
53
54
55
56
57
37,39,41,42,51 RUN_ON
FDS4435: P CHANNAL
Title
Internal LVDS
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
19
of
66
C149
10P_0402_50V8J~D
@
C148
10P_0402_50V8J~D
2
@
2
1
C151
0.01U_0402_16V7K~D
C147
10P_0402_50V8J~D
@
R792
0_1206_5%~D
C165
22P_0402_50V8J~D
1
C161
C162
CRT_VCC
22P_0402_50V8J~D
CRT_BLU
22P_0402_50V8J~D
CRT_BLU
R143
150_0402_1%~D
2
1
CRT_GRN
36,52
CRT_GRN
R141
150_0402_1%~D
2
1
36,52
L11
BLM18BB750SN1D_0603~D
1
2
L10
1
2
L9
1
2
CRT_RED
CRT_RED
R142
150_0402_1%~D
2
1
36,52
+3.3V_RUN
+5V_RUN
D8
SDM10U45-7_SOD523-2~D
D9
DA204U_SOT323~D
@
F3
0.12A_48V_NANOSMDC012F~D
2
1
D10
DA204U_SOT323~D
@
D11
DA204U_SOT323~D
@
JCRT
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
+5V_RUN_SYNC
RED
36,52
DAT_DDC2
GREEN
PAD~D
R2
2.2K_0402_5%~D
C160
0.1U_0402_16V4Z~D
JVGA_HS
BLUE
JVGA_VS
M_ID2#
R137
2.2K_0402_5%~D
R5
1K_0402_5%~D
@
2
1
Evaluate Package
R3
1K_0402_5%~D
@
2
1
T5
CLK_DDC2
DAT_DDC2
16
17
SUYIN_070915FR015S201CU~D
36,52 CLK_DDC2
U15
Y
R146
10_0402_5%~D
SN74AHCT1G125GW_SC70-5~D
L1
1
2
HSYNC_R
36
VSYNC_R
36
1
R138
10_0402_5%~D
SN74AHCT1G125GW_SC70-5~D
C712
10P_0402_50V8J~D
1
Y
U14
C719
10P_0402_50V8J~D
A
3
C4
10P_0402_50V8J~D
30_0402_1%~D
L2
1
2
C5
10P_0402_50V8J~D
52 CRT_VSYNC
R59
OE#
30_0402_1%~D
5
1
R144
1K_0402_5%~D
1
2
52 CRT_HSYNC
R60
B
OE#
+5V_RUN
D6
+5V_RUN_SYNC
SDM10U45-7_SOD523-2~D
2
1
DA204U
K1 A2
A1
K2
Title
CRT
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
20
of
66
+3.3V_RUN
PCI_PIRQA#
2
8.2K_0402_5%~D
PCI_PIRQB#
2
8.2K_0402_5%~D
PCI_PIRQC#
2
8.2K_0402_5%~D
PCI_PIRQD#
2
8.2K_0402_5%~D
1
R454
ICH_GPIO2_PIRQE#
2
8.2K_0402_5%~D
35
PCI_PIRQA#
30
PCI_PIRQD#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
C8
D9
G6
D16
A7
B7
F10
C16
C9
A17
PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
AG24
B10
G7
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
C651
0.1U_0402_16V4Z~D
30,35
30,35
30,35
30,35
14
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
+3.3V_SUS
PCI_PCIRST#
PCI_IRDY# 30,35,36
PCI_PAR 30,35
1
2
PCI_DEVSEL# 30,35
PCI_PERR# 30,35
PCI_PLOCK# 35
PCI_SERR# 30,35
PCI_STOP# 30,35
PCI_TRDY# 30,35
PCI_FRAME# 30,35,36
IN1
OUT
CLK_PCI_ICH 6
ICH_PME#
38
PCI_PLTRST#
4
5
Interrupt I/F
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
ICH_GPIO2_PIRQE#
SB_WLAN_PCIE_RST#
SB_NB_PCIE_RST#
F8
G11
F12
B3
PCI_RST#
PCI_RST#
30,31,35
IN2
74VHC08MTCX_NL_TSSOP14~D
+3.3V_SUS
U33B
IN1
OUT
PLTRST1#
PLTRST1#
10
IN2
+3.3V_SUS
SB_WLAN_PCIE_RST# 34
SB_NB_PCIE_RST# 10
PCIE_MCARD2_DET# 34
ICH8M_BGA676~D
10
9
PCI_REQ0#
2
8.2K_0402_5%~D
PCI_REQ1#
2
8.2K_0402_5%~D
U33C
IN1
OUT
PLTRST2#
PLTRST2#
38,39
PLTRST3#
28,34
IN2
1
R458
1
R459
U33A
PIRQA#
PIRQB#
PIRQC#
PIRQD#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
C17
E15
F16
E17
SB_LOM_PCIE_RST#
PCI_GNT3#
PCI_REQ0#
36
PCI_GNT0# 35,36
PCI_REQ1#
30
PCI_GNT1# 30
SB_WWAN_PCIE_RST# 34
T1 PAD~D
SB_LOM_PCIE_RST# 28
T2 PAD~D
F9
B5
C5
A10
PCI
A4
D7
E18
C18
B19
F18
A11
C10
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
SB_WWAN_PCIE_RST#
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
14
1
R450
1
R451
1
R452
1
R453
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
+3.3V_RUN
D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3
PCI_PLOCK#
2
8.2K_0402_5%~D
PCI _IRDY#
2
8.2K_0402_5%~D
PCI_SERR#
2
8.2K_0402_5%~D
PCI_PERR#
2
8.2K_0402_5%~D
U32B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
1
R446
1
R447
1
R448
1
R449
30,35 PCI_AD[0..31]
14
PCI_DEVSEL#
2
8.2K_0402_5%~D
PCI_STOP#
2
8.2K_0402_5%~D
PCI_TRDY#
2
8.2K_0402_5%~D
PCI_FRAME#
2
8.2K_0402_5%~D
1
R442
1
R443
1
R444
1
R445
12
PCI_GNT0#
23 ICH_SPI_CS1#
IN1
OUT
BIOS should not enable the internal

GPIO pull up resistor
ICH_SPI_CS1#
R462
R477
1K_0402_5%~D
@
PLTRST3#
11
IN2
PCI_GNT3#
R463
@ 1K_0402_5%~D
1K_0402_5%~D
2
U33D
13
SB_LOM_PCIE_RST#
2
20K_0402_5%~D
SB_WWAN_PCIE_RST#
2
20K_0402_5%~D
SB_WLAN_PCIE_RST#
2
20K_0402_5%~D
SB_NB_PCIE_RST#
2
20K_0402_5%~D
1
R461
1
R460
1
R601
1
R631
14
+3.3V_SUS
Place closely pin U19.A9

2
CLK_PCI_ICH
A16 away override strap.
R464
@ 10_0402_5%~D
Low = A16 swap override enabled.

High = Default.
PCI_GNT0#
SPI_CS1#
Boot BIOS Location
SPI
PCI
CLK_ICH_TERM 1
PCI_GNT3#
Boot BIOS Strap
LPC
C652
@ 8.2P_0402_50V8J~D
Title
ICH8(1/4)
Size
Date:
Document Number
Rev
0.4
LA-3302P
Sheet
1
21
of
66
+RTC_CELL
+RTC_CELL
1
R475
332K_0402_1%~D
LAN100_SLP
ICH_INTVRMEN
R472
332K_0402_1%~D
R478
0_0402_1%
@ R476
0_0402_5%~D
D
Package
9.6X4.06 mm
ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
C653
15P_0402_50V8J~D
2
1
ICH_RTCX1
ICH_INTVRMEN
Y4
32.768K_12.5P_1TJS125DJ4A420P~D
CMOS_CLR @SHORT PADS~D

2
C655
1U_0603_10V4Z~D
Close to U19
26 ICH_AZ_CODEC_SDOUT
1
R493
2 ICH_AZ_SDOUT
33_0402_5%~D
26 ICH_AZ_CODEC_SYNC
1
R494
2 I CH_AZ_SYNC
33_0402_5%~D
33 ICH_AZ_MDC_BITCLK
33 ICH_AZ_MDC_SYNC
33 ICH_AZ_MDC_RST#
26 ICH_AZ_CODEC_SDIN0
33 ICH_AZ_MDC_SDIN1
2 ICH_AZ_RST#
33_0402_5%~D
1
R495
26 ICH_AZ_CODEC_RST#
R496
1
26 ICH_AZ_CODEC_BITCLK
C660
27P_0402_50V8J~D
ICH_AZ_BITCLK
1
R487
33 ICH_AZ_MDC_SDOUT
2 ICH_AZ_SDOUT
33_0402_5%~D
SATA_ACT#_R
43 SATA_ACT#_R
D22
LAN_RSTSYNC
C21
B21
C22
LAN_RXD0
LAN_RXD1
LAN_RXD2
D21
E20
C20
LAN_TXD_0
LAN_TXD_1
LAN_TXD_2
+1.5V_RUN_PCIE_ICH R480
AH21
24.9_0402_1%~D
C656
27P_0402_50V8J~D
D25
1
2
C25
2
1
R481 33_0402_5%~D
AJ16
1
2 ICH_AZ_BITCLK
AJ15
1
2 I CH_AZ_SYNC
R483
33_0402_5%~D
AE14
1
2 ICH_AZ_RST#
R484
33_0402_5%~D
ICH_AZ_CODEC_SDIN0 AJ17
ICH_AZ_MDC_SDIN1
AH17
AH15
AD13
33_0402_5%~D
PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
SATA_TX0-_N0
SATA_TX0+_P0
25 PSATA_IRX_DTX_N0_C
25 PSATA_IRX_DTX_P0_C
GLAN_CLK
B24
2
1
C658 3900P_0402_50V7K~D
2
1
C659 3900P_0402_50V7K~D
25 PSATA_ITX_DRX_N0
25 PSATA_ITX_DRX_P0
CLK_PCIE_SATA#
CLK_PCIE_SATA
6 CLK_PCIE_SATA#
6 CLK_PCIE_SATA
1
R491
2
24.9_0402_1%~D
GLAN_DOCK#/GPIO13
GLAN_COMPI
GLAN_COMPO
C4
LPC_LFRAME#
LDRQ0#
LDRQ1#/GPIO23
G9
E6
LPC_LDRQ0#
LPC_LDRQ1#
A20GATE
A20M#
AF13
AG26
SIO_A20GATE
H_A20M#
DPRSTP#
DPSLP#
AF26
AE26
H_DPRSTP#
H_DPSLP#
FERR#
AD24
H_FERR#
CPUPWRGD/GPIO49
AG29
H_PW RGOOD
IGNNE#
AF27
H_IGNNE#
INIT#
INTR
RCIN#
AE24
AC20
AH14
H_INIT#
H_INTR
SIO_RCIN#
HDA_BIT_CLK
HDA_SYNC
NMI
SMI#
AD23
AG28
H_NMI
H_SMI#
STPCLK#
AA24
H_STPCLK#
THRMTRIP#
AE27
THRMTRIP_ICH#
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
AE13
HDA_SDOUT
AE10
AG14
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AF10
SATALED#
AF6
AF5
AH5
AH6
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AG3
AG4
AJ4
AJ3
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AF2
AF1
AE4
AE3
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AB7
AC6
SATA_CLKN
SATA_CLKP
AG1
AG2
SATARBIAS#
SATARBIAS
Within 500 mils
AA23
ICH_TP8
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
DA0
DA1
DA2
AA4
AA1
AB3
IDE_DA0
IDE_DA1
IDE_DA2
TP8
DCS1#
DCS3#
Y6
Y5
IDE_DCS1#
IDE_DCS3#
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
W4
W3
Y2
Y3
Y1
W5
IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_ DIORDY
IDE_DDREQ
LPC_LFRAME# 28,38,39
LPC_LDRQ0# 38
LPC_LDRQ1# 38
SIO_A20GATE 39
H_A20M#
7
FWH4/LFRAME#
@
2
INTVRMEN
LAN100_SLP
R474
56_0402_1%~D
INTRUDER#
AF25
AD21
+1.05V_VCCP
R473
56_0402_1%~D
2
1
AD22
ICH_INTVRMEN
LAN100_SLP
28,38,39
28,38,39
28,38,39
28,38,39
H_DPRSTP#
H_DPSLP#
H_FERR#
8,10,48
8
H_PWRGOOD 8
H_IGNNE#
H_INIT#
H_INTR
SIO_RCIN#
7
7
39
H_NMI
H_SMI#
7
7
H_STPCLK#
+1.05V_VCCP
1
INTRUDER#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
R482
56_0402_5%~D
+3.3V_RUN
RTCRST#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
T12PAD~D
C470
AF23
LPC
ICH_RTCRST#
E5
F5
G8
F6
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
0.1U_0402_16V4Z~D
RTCX1
RTCX2
CPU
AG25
AF24
RTC
2
20K_0402_5%~D
2
1M_0402_5%~D
ICH_RTCX2
IDE
1
2
0_0402_5%~D
LAN / GLAN
1
R470
1
R471
+RTC_CELL
U32A
R469
IHDA
IDE_IRQ
2
8.2K_0402_5%~D
Low = Internal VR Disabled

High = Internal VR Enabled(Default)
10M_0402_5%~D
2
C654
15P_0402_50V8J~D
2
1
ICH_LAN100_SLP
Low = Internal VR Disabled

High = Internal VR Enabled(Default)
R467
SATA
+3.3V_RUN
1
R490
ICH8M LAN100 SLP Strap

(Internal VR for VccLAN1.05 and VccCL1.05)
R465
1
SIO_A20GATE
10K_0402_5%~D
2
R466
SIO_RCIN#
10K_0402_5%~D
+1.05V_VCCP
B
R468
H_FERR#
56_0402_5%~D
IDE_DD[0..15] 25
IDE_DA0
25
IDE_DA1
25
IDE_DA2
25
IDE_DCS1#
IDE_DCS3#
IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_DIORDY
IDE_DDREQ
25
25
25
25
25
25
25
25
ICH8M_BGA676~D
+3.3V_RUN
XOR Chain Entrance Strap

HDA SDOUT
R385
1K_0402_5%~D
@
Description
2
ICH RSVD
A
ICH_AZ_SDOUT
RSVD
23
ICH_RSVD
Enter XOR Chain
Normal Operation (Default)
Set PCIE port config bit 1
R386
1K_0402_5%~D
@
2

Title
ICH8(2/4)
Size
Date:
Document Number
Rev
0.4
LA-3302P
Sheet
1
22
of
66
+3.3V_RUN
38 SIO_EXT_WAKE#
34 PCIE_MCARD1_DET#
34 USB_MCARD1_DET#
R505
8.2K_0402_5%~D
34 USB_MCARD2_DET#
C877 47P_0402_50V8J~D
Option to " Disable "

clkrun. Pulling it
down
will keep the clks
running.
C878 47P_0402_50V8J~D
R508
10_0402_5%~D
@
C874
47P_0402_50V8J~D
CLKRUN#
C876 47P_0402_50V8J~D
C875 47P_0402_50V8J~D
2
0_0603_5%~D
39 SIO_EXT_SMI#
0_0603_5%~D
39 SIO_EXT_SCI#
2
2
4.7K_0603_5%~D
2
0_0603_5%~D
PAD~D T24
25 IDE_RST_MOD
6 SATA_CLKREQ#
52 PLTRST_DELAY#
PAD~D T14
26
10 MCH_ICH_SYNC#
22
ICH_RSVD
SMB
AG22
SMBALERT#/GPIO11
AE20
AG18
AH11
ICH_PCIE_WAKE#AE17
IRQ_SERIRQ
AF12
RSV_THRM#
AC13
STP_PCI#/GPIO15
STP_CPU#/GPIO25
CLKRUN#/GPIO32
WAKE#
SERIRQ
THRM#
IMVP_PWRGD
AJ20
VRMPWRGD
ICH_TP7
AJ22
TP7
AJ8
AJ9
AH9
AE16
AC19
AG8
AH12
AE11
AG10
AH25
AD16
AG13
AF9
AJ11
AD10
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SIO_EXT_SMI#
SIO_EXT_SCI#
RSVD_GPIO27
IDE_RST_MOD
SATA_CLKREQ#
PLTRST_DELAY#
RSVD_GPIO39
RSVD_GPIO48
SPKR
SPKR
BMBUSY#/GPIO0
MCH_ICH_SYNC#
ICH_RSVD
AD9
SPKR
AJ13
MCH_SYNC#
AJ21
TP3
CLK_ICH_14M 6
CLK_ICH_48M 6
SUSCLK
D3
ICH_SUSCLK
T13 PAD~D
SLP_S3#
SLP_S4#
SLP_S5#
AG23
AF21
AD18
SIO_SLP_S3#
SIO_SLP_S3# 39
S4_STATE#/GPIO26
AH27
PWROK
AE23
ICH_PWRGD
DPRSLPVR/GPIO16
AJ14
DPRSLPVR
BATLOW#
AE21
SIO_SLP_S5#
ICH_RSMRST#
1
R515
2
10K_0402_5%~D
Place closely pin U19.AC1

ICH_PWRGD 10,42
DPRSLPVR
CLK_ICH_14M
10,48
PWRBTN#
C2
LAN_RST#
AH20
ICH_LAN_RST#
RSMRST#
AG27
ICH_RSMRST#
CK_PWRGD
E1
CLK_PWRGD
CLPWROK
E3
ICH_CL_PWROK
R510
@ 10_0402_5%~D
ICH_RSMRST# 39
CLK_PWRGD 6
ICH_CL_PWROK 10,39
CL_CLK0
CL_CLK1
F23
AE18
CL_CLK0
CL_DATA0
CL_DATA1
F22
AF19
CL_DATA0
CL_VREF0
CL_VREF1
D24
AH23
CL_VREF0_ICH
CL_RST#
AJ23
CL_RST0#
MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
WOL_EN/GPIO9
AJ27
AJ24
AF22
AG19
EC_ME_ALERT
CL_CLK0
CL_DATA0 10
Place closely pin U19.B2

CLK_ICH_48M
T86 PAD~D
CL_RST0#
10
R520
@ 10_0402_5%~D
U32D
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
C667 1
C668 1
+3.3V_SUS
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2
M27
M26
L29
L28
PERN2
PERP2
PETN2
PETP2
K27
K26
J29
J28
PERN3
PERP3
PETN3
PETP3
H27
H26
G29
G28
PERN4
PERP4
PETN4
PETP4
F27
F26
E29
E28
PERN5
PERP5
PETN5
PETP5
RP1
B
USB_OC0_1#
USB_OC2_3#
USB_OC4#
USB_OC5#
4
3
2
1
5
6
7
8
10K_1206_8P4R_5%~D
RP2
USB_OC6#
USB_OC8#
USB_OC9#
USB_OC7#
4
3
2
1
5
6
7
8
10K_1206_8P4R_5%~D
GIGA LAN --->
28
28
28
28
PCIE_RX6-/GLAN_RXPCIE_RX6+/GLAN_RX+
PCIE_TX6-/GLAN_TXPCIE_TX6+/GLAN_TX+
39 ICH_EC_SPI_CLK
39 ICH_SPI_CS0#
21 ICH_SPI_CS1#
39 ICH_EC_SPI_DO
39 ICH_EC_SPI_DIN
C669 1
C670 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
R99
2.2K_0402_5%~D
2
1
R278
2.2K_0402_5%~D
2
1
2
G
ICH_SMBDATA
1
1
1
2 15_0402_5%~D
2 15_0402_5%~D
2 15_0402_5%~D
C23
B23
E22
SPI_CLK
SPI_CS0#
SPI_CS1#
ICH_EC_SPI_DO
ICH_EC_SPI_DIN
R763
2 15_0402_5%~D
D23
F21
SPI_MOSI
SPI_MISO
USB_OC0_1#
USB_OC2_3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#
MEM_SDATA
MEM_SDATA
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
R530
R531
R532
32 USB_OC2_3#
D27
D26
C29
C28
ICH_EC_SPI_CLK
ICH_SPI_CS0#
ICH_SPI_CS1#
32 USB_OC0_1#
+3.3V_RUN
PCIE_RX6-/GLAN_RXPCIE_RX6+/GLAN_RX+
GLAN_TXN_C
GLAN_TXP_C
AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18
OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#
USB
16,17
V27
V26
U29
U28
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA29
AA28
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
DMI_CLKN
DMI_CLKP
T26
T25
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_ZCOMP
DMI_IRCOMP
Y23
Y24
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBRBIAS#
USBRBIAS
F2
F3
USBRBIAS
ICH8M_BGA676~D
Q21
2N7002W-7-F_SOT323-3~D
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
10
10
10
10
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
10
10
10
10
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
10
10
10
10
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
10
10
10
10
1
R533
CL_VREF0_ICH
Within 500 mils
+1.5V_RUN_PCIE_ICH
2
22.6_0402_1%~D
Within 500 mils
2
G
1
MEM_SCLK
MEM_SCLK
16,17
Q27
2N7002W-7-F_SOT323-3~D
Title
ICH8(3/4)
Size
Document Number
Rev
0.4
LA-3302P
Date:
----->Side Top
----->Side Bottom
----->Rear Left
----->Rear Right
----->Smart Card
----->Biometric
----->Card Bus
----->Blue Tooth
----->Dock
----->WWAN
+3.3V_RUN
ICH_SMBCLK
R519
3.24K_0402_1%~D
R529 24.9_0402_1%~D
1
2
32
32
32
32
32
32
32
32
31
31
40
40
30
30
40
40
36
36
34
34
@ 4.7P_0402_50V8C~D
+3.3V_RUN
CLK_PCIE_ICH# 6
CLK_PCIE_ICH 6
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
C663
34
34
34
34
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
Direct Media Interface
MiniWLAN (Mini Card 2)--->
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
PERN1
PERP1
PETN1
PETP1
PCI - Express
C664 1
C666 1
P27
P26
N29
N28
SPI
MiniWWAN (Mini Card 1)--->
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1
@ 4.7P_0402_50V8C~D
10
ICH8M_BGA676~D
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
C661
AJ25
34
34
34
34
SIO_SLP_S5# 39
ICH_BATLOW# 2
1
+3.3V_SUS
R518 8.2K_0402_5%~D
SIO_PWRBTN#
SIO_PWRBTN# 39
SLP_M#
2
10K_0402_5%~D
1
R817
R819
1
1
R820
1
R818
PAD~D T15
AG12
CLK_ICH_14M
CLK_ICH_48M
1
R512
R816
0_0603_5%~D
1
2
USB_IDE#
PM_BMBUSY#
AG9
G5
ICH_PWRGD
R522
453_0402_1%~D
25
+3.3V_RUN
SUS_STAT#/LPCPD#
SYS_RESET#
CLK14
CLK48
clocks
2
100K_0402_5%~D
2 SIO_EXT_SMI#
10K_0402_5%~D
F4
AD15
CLKRUN#
39,42,48 IMVP_PWRGD
1
R509
ITP_DBRESET#
2LOM_ICH_SMBALERT#
0_0402_5%~D
H_STP_PCI#
6 H_STP_PCI#
H_STP_CPU#
6 H_STP_CPU#
38 ICH_PCIE_WAKE#
28,30,38,39 IRQ_SERIRQ
+3.3V_SUS
RI#
1
@ R793
30,38,39 CLKRUN#
High = No Reboot
AF17
AJ12
AJ10
AF11
AG11
1
R501
Low = Default
SPKR
I CH_RI#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
2
10K_0402_5%~D
DPRSLPVR
28,39 LOM_SMB_ALERT#
No Reboot Strap
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
2
1M_0402_1%~D
ICH_LAN_RST# 1
R834
1
10 PM_BMBUSY#
AJ26
AD19
AG21
AC17
AE19
Power MGT
7,38 ITP_DBRESET#
ICH_SMBCLK
ICH_SMBDATA
ICH_CL_RST1#
ICH_SMLINK0
ICH_SMLINK1
SYS / GPIO
28,34 ICH_SMBCLK
28,34 ICH_SMBDATA
SATA
GPIO
U32C
MISC
GPIO
Controller Link
@
@
R500
2 ICH_CL_RST1#
10K_0402_5%~D
2 ICH_SMLINK0
10K_0402_5%~D
1 ICH_SMLINK1
10K_0402_5%~D
2 I CH_RI#
10K_0402_5%~D
2 SIO_EXT_SCI#
10K_0402_5%~D
2 ICH_PCIE_WAKE#
1K_0402_5%~D
2 ICH_SMBCLK
2.2K_0402_5%~D
2 ICH_SMBDATA
2.2K_0402_5%~D
2 EC_ME_ALERT
8.2K_0402_5%~D
2 LOM_ICH_SMBALERT#
10K_0402_5%~D
1
@ R514
1
R503
2
R502
1
R506
1
R516
1
R521
1
R498
1
R499
1
R690
1
R807
8.2K_0402_5%~D
1
2 IMVP_PWRGD
R411 @ 2.2K_0402_5%~D
1
2 MCH_ICH_SYNC#
R524
@ 10K_0402_5%~D
RSV_THRM#
2
1
R497
10K_0402_5%~D
IRQ_SERIRQ
2
1
R504
10K_0402_5%~D
RSVD_GPIO39
1
2
R523
10K_0402_5%~D
RSVD_GPIO48
1
2
R528
10K_0402_5%~D
SPKR
1
2
R115
@ 1K_0402_5%~D
ICH_CL_PWROK 1
R42
+3.3V_SUS
C662
0.1U_0402_16V4Z~D
+3.3V_RUN
Sheet
1
23
of
66
+RTC_CELL
2
0_0603_5%~D
VCCUSBPLL
F1
L6
L7
M6
M7
VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
W23
VCC1_5_A[25]
1
+1.5V_RUN
Place Cap as close

to A24 as possible
TP_VCCLAN1.05_INT_ICH1 F17
TP_VCCLAN1.05_INT_ICH2 G18
+1.5V_RUN_PCIE_ICH
+3.3V_RUN
1
VCCLAN3_3[1]
VCCLAN3_3[2]
A24
VCCGLANPLL
A26
A27
B26
B27
B28
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]
B25
VCCGLAN3_3
C691
0.1U_0402_16V4Z~D
+3.3V_RUN
AD11
VCCSUS1_05[1]
VCCSUS1_05[2]
J6
AF20
TP_VCCSUS1.05_INT_ICH1
TP_VCCSUS1.05_INT_ICH2
VCCSUS1_5[1]
AC16
VCCSUS1_5_ICH_1
VCCSUS1_5_ICH_2
C3
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]
AC18
AC21
AC22
AG20
AH28
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6
VCCCL1_05
G22
VCCCL1_5
A22
VCCCL3_3[1]
VCCCL3_3[2]
F20
G21
+3.3V_RUN
C695
0.1U_0402_16V4Z~D
+3.3V_SUS
AC12
VCCSUS1_5[2]
C687
0.1U_0402_16V4Z~D
VCCP_CORE
PCI
IDE
VCCLAN1_05[1]
VCCLAN1_05[2]
F19
G20
GLAN POWER
+1.5V_RUN
PAD~DT21
PAD~DT22
C705
0.1U_0402_16V4Z~D
C703
0.1U_0402_16V4Z~D
VCCHDA
VCCSUS3_3[01]
1
T17PAD~D
T18PAD~D
2
C698
0.1U_0402_16V4Z~D
T19
T20
+3.3V_SUS
+3.3V_SUS
VCCCL1_05_ICH
C704
0.1U_0402_16V4Z~D
D1
+3.3V_RUN
VCCSUSHDA
J7
C688
0.1U_0402_16V4Z~D
VCC1_5_A[18]
VCC1_5_A[19]
C681
10U_0805_4VAM~D
AC7
AD7
C680
0.01U_0402_16V7K~D
VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]
CORE
G12
G17
H7
A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11
C702
1
R538
0.1U_0402_16V4Z~D
VCC1_5_A[13]
VCC1_5_A[14]
VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]
+3.3V_RUN
0.022U_0402_16V7K~D
C701
+3.3V_RUN
C700
AA5
AA6
USB CORE
0.1U_0402_16V4Z~D
VCC1_5_A[11]
VCC1_5_A[12]
AA3
U7
V7
W1
W6
W7
Y7
+3.3V_RUN
0.022U_0402_16V7K~D
C699
AC10
AC9
VCCPSUS
220U_D2_4VY_R15M~D
C676
1
2
1
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]
VCCPUSB
1
2
2
2
B
AC1
AC2
AC3
AC4
AC5
VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
C686
AC8
AD8
AE8
AF8
+1.05V_VCCP
C694
C697
1U_0603_10V4Z~D
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
+1.25V_RUN
1
+3.3V_RUN
0.1U_0402_16V4Z~D
C693
AE7
AF7
AG7
AH7
AJ7
AD2
0.1U_0402_16V4Z~D
C692
C696
1U_0603_10V4Z~D
VCCSATAPLL
AF29
VCC3_3[02]
0.1U_0402_16V4Z~D
AJ6
VCC3_3[01]
0.1U_0402_16V4Z~D
C685
AC23
AC24
C684
C690
C689
1U_0603_10V4Z~D
10U_0805_4VAM~D
V_CPU_IO[1]
V_CPU_IO[2]
+1.5V_RUN
L44
1
2
2
1
R535
1_0603_1%~D
0.1U_0402_16V4Z~D
0_0603_5%~D
AE28
AE29
10_0805_5%~D
4.7U_0603_6.3V6M~D
+1.5V_RUN_SATAPLL
L45
10UH_LB2012T100MR_20%_0805~D
+VCCSATAPLLR 1
2
VCC_DMI[1]
VCC_DMI[2]
A23
A5
AA2
AA7
A25
AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29
AD3
AD4
AD6
AE1
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
J27
J4
J5
K23
K28
K29
K3
K6
MMBD4148-7-F_SOT23-3~D
C682
R537
R29
22U_0805_6.3V6M~D
+1.5V_RUN
VCCDMIPLL
C202
0.1U_0402_16V4Z~D
VCCA3GP
C683
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
0.1U_0402_16V4Z~D
ICH_V5REF_SUS
AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25
ATX
V5REF_SUS
ARX
C679
2.2U_0603_6.3V6K~D
G4
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]
C674
V5REF[1]
V5REF[2]
ICH_V5REF_SUS
RB751V_SOD323~D
C678
10_0402_5%~D
22U_0805_6.3V6M~D
D21
C677
+3.3V_SUS
R536
A16
T7
+1.5V_RUN_PCIE_ICH
1
2
22U_0805_6.3V6M~D
+5V_SUS
ICH_V5REF_RUN
L43
0.1U_0402_16V4Z~D
VCCRTC
0.1U_0402_16V4Z~D
C675
AD25
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
ICH8M_BGA676~D
A
+3.3V_RUN
ICH8M_BGA676~D
C709
4.7U_0603_6.3V6M~D
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
T23
Title
ICH8(4/4)
Size
Document Number
Rev
0.4
LA-3302P
Date:
U32E
R182
1
C673
+1.5V_RUN_PCIE_ICH
+1.5V_RUN
+1.5V_RUN
+1.05V_VCCP
U32F
0.1U_0402_16V4Z~D
ICH_V5REF_RUN
C672
RB751V_SOD323~D
+1.05V_VCCP
D34
0.1U_0402_16V4Z~D
100_0402_5%~D
D
C671
D20
C200
R534
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
+5V_RUN +3.3V_RUN
Sheet
1
24
of
66
+5V_ALW
+15V_ALW
D Q48
G
2 MOD_EN
IDE_RST_MOD
R230
100K_0402_5%~D
1
2
38
MODPRES#
+3.3V_ALW
31
33
33
34
34
36
36
35
35
37
37
IDE_DIOR#
38
38
IDE_DIOW#
40
40
39
39
41
41
IDE_DDREQ
42
42
44
44
IDE_DD1
43
43
IDE_DD0
45
45
IDE_DD14
46
46
IDE_DD2
48
48
IDE_DD12
50
47
47
IDE_DD13
49
49
51
51
IDE_DD3
53
53
IDE_DD4
55
55
IDE_DD10
57
57
IDE_DD9
59
59
61
61
63
63
65
65
67
67
50
52
52
54
54
IDE_DD5
56
56
IDE_DD6
58
58
60
MOD_RST
62
62
USB_IDE#
64
64
66
SC_USBP- 31
DASP#
HDD PWR
IDE_DCS1#
IDE_DCS1# 22
PDIAG#
+5V_ALW
+15V_ALW
IDE_IRQ
IDE_DDACK#_R
IDE_IRQ
1
2
R392
0_0402_5%~D
IDE_ DIORDY
22
+3.3V_RUN
IDE_DIORDY 22
+3.3V_ALW2
IDE_DDACK# 22
R627
100K_0402_5%~D
R206
4.7K_0402_5%~D
R626
IDE_DDREQ 22
G
HDD_EN_5V
100K_0402_5%~D
Q57
2N7002W-7-F_SOT323-3~D
2
G
38
HDDC_EN
Q69
2N7002W-7-F_SOT323-3~D
2
G
R692
100K_0402_5%~D
+5V_HDD
Pleace near HD CONN
Open
JSATA
C461
3900P_0402_50V7K~D
2
1
22 PSATA_IRX_DTX_N0_C
68
22 PSATA_IRX_DTX_P0_C
TYCO_1770530-1~D
C462
3900P_0402_50V7K~D
22 PSATA_ITX_DRX_P0
22 PSATA_ITX_DRX_N0
PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0
PSATA_IRX_DTX_N0
PSATA_IRX_DTX_P0
+3.3V_RUN
C464
0.1U_0402_10V7K~D
@ C466
0.1U_0402_16V4Z~D
C465
10U_0805_10V4Z~D
1
2
3
4
5
6
7
GND
RX+
RXGND
TXTX+
GND
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3.3V_RUN
C469
0.1U_0402_16V4Z~D
C145
1000P_0402_50V7K~D
@ PAD-OPEN 4x4m
+5V_HDD Source
+5V_HDD
IDE_DD7
+5V_HDD
+5V_RUN
PJP2003
1
close SATA connector
Q56
R217
10K_0402_5%~D
31
SC_USBP+ 31
R629
100K_0402_5%~D
32
+5VMOD Source
30
32
30
IDE_DA1
29
29
27
C813
10U_0805_10V4Z~D
25
27
C812
0.1U_0603_50V4Z~D
25
23
23
SC_USBP-
SC_USBP+
21
19
21
28
IDE_DA0
19
+5V_MOD
1
2
5
6
26
28
69
17
R691
100K_0402_5%~D
26
IDE_DA2
68
15
17
C818
10U_0805_10V4Z~D
IDE_DCS3#
MODPRES#
15
Q68
2N7002W-7-F_SOT323-3~D
C817
0.1U_0603_50V4Z~D
20
66
13
2
G
MODC_EN
20
60
13
38
18
8.3
+3.3V_RUN
16
18
24
IDE_DD8
USB_IDE#
16
22
IDE_DD11
R209
56_0402_5%~D
1
2
14
24
IDE_DD15
IDE_DD[0..15]
12
14
22 IDE_DIOW#
11
22 IDE_DIOR#
12
22
CSEL2
11
10
IDE_DA1
2
G
IDE_DA0
22
22
IDE_DA2
TOP VIEW
23
WF1F068N1A
22
R205
470_0402_5%~D
1
2
23 IDE_RST_MOD
8
10
22 IDE_DCS3#
22 IDE_DD[0..15]
Q50
2N7002W-7-F_SOT323-3~D
C262
0.1U_0402_16V4Z~D
C60
10U_0805_10V4Z~D
1
2
70
3
D
C268
0.1U_0402_16V4Z~D
C211
0.01U_0402_16V7K~D
R618
100K_0402_5%~D
+5V_MOD
72
JMOD
1
2
5
6
R619
100K_0402_5%~D
71
R622
100K_0402_5%~D
+3.3V_ALW2
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
GND1
GND2
23
24
TYCO_1775191-1_RV~D
1
Main SATA +5V Default
Pleace near HD CONN
Title
DVD MODULE
Size
Rev
0.4
LA-3302P
Date:
Document Number
Sheet
1
25
of
66
+VDDA
1
D
Y
A
BEEP1
R540
20K_0402_5%~D
1
2
C711
0.1U_0402_10V6K~D
AUD_PC_BEEP
1
2
BEEP2
1
74AHCT1G86GW_SOT353-5~D
TRACE>15 mil
+VDDA
R542
5.11K_0402_1%~D
2
1
R541
10K_0402_5%~D
ICH_AZ_CODEC_BITCLK
ICH_AC_SDIN0_R
1
2
R544 33_0402_5%~D
22 ICH_AZ_CODEC_SDOUT
ICH_AZ_CODEC_SDOUT
1
9
40
3
DVDD_CORE
DVDD_CORE
DVDD_CORE/VPP
DVDD_IO
AUD_HP_OUT_L 27
41
AUD_HP_OUT_R 27
VREFOUT_A
37
22 ICH_AZ_CODEC_RST#
PORT_B_L
21
AUD_EXT_MIC_L 27
22
AUD_EXT_MIC_R 27
VREFOUT_B
28
HDA_RST#
STAC9205
43
NC1
44
NC2
45
NC3
C721
10P_0402_50V8J~D
46
23
PORT_C_R
24
VREFOUT_C
29
35
AUD_LINE_OUT_L
36
AUD_LINE_OUT_R
PORT_E_L
PORT_E_R
15
VOL_UP/DMIC0/GPIO1
VOL_DN/DMIC1/GPIO2
VREFOUT_E/GPIO4
31
PORT_F_L
16
PORT_F_R
17
VREFOUT_F/GPIO3
30
CD_L
CD_GND
CD_R
18
19
20
PC_BEEP
12
MONO_OUT
32
2
1
AUD_SENSE_B
R543
10K_0402_5%~D
2
1
DOCK_HP_MUTE#
2
R546
1
10K_0402_5%~D
AUD_SPDIF_SHDN
2
R547
1
10K_0402_5%~D
AUD_LINE_OUT_L 27
AUD_LINE_OUT_R 27
B
DOCK_HP_MUTE#
DOCK_HP_MUTE# 38
AUD_SPDIF_SHDN 38
R479
47_0402_5%~D
@
2
AUD_MIC_SWITCH 27
G
Q75
2N7002W-7-F_SOT323~D
AUD_INT_MIC_IN 27
PORT_D_L
14
VREFOUT
PORT_D_R
DMIC_CLK
ICH_AZ_CODEC_SDOUT
PORT_C_L
+VDDA
PORT_B_R
HDA_SYNC
R710
39.2K_0402_1%~D
1
2
1
39
11
PORT_A_L
HDA_SDO
AUD_SENSE_A
AUD_SENSE_B
PORT_A_R
AUD_HP_NB_SENSE 2
G
Q74
2N7002W-7-F_SOT323~D
2 @
HDA_SDI_CODEC
13
34
HDA_BIT_CLK
ICH_AZ_CODEC_BITCLK
SENSE_A
SENSE_B
27,38 AUD_HP_NB_SENSE
10
Close to Pin 6
25
38
22 ICH_AZ_CODEC_SYNC
R545
10_0402_5%~D
AVDD1
AVDD2
1
U35
C718
10U_0805_10V4Z~D
2 @
C717
0.1U_0402_16V4Z~D
C726
1U_0603_10V4Z~D
22 ICH_AZ_CODEC_BITCLK
22 ICH_AZ_CODEC_SDIN0
+3.3V_RUN
+VDDA
C172
10U_0805_10V4Z~D
W=30 mil
C716
0.1U_0402_16V4Z~D
C715
1U_0603_10V4Z~D
C759
1000P_0402_50V7K~D
C714
0.1U_0402_16V4Z~D
R821
100K_0402_5%~D
1
2
R711
20K_0402_1%~D
+3.3V_RUN
AUD_SENSE_A
U34 place as close to CODEC as possible
C713
1000P_0402_50V7K~D
5
P
U34
BEEP
39
SPKR
single gate TTL
2
23
C710
0.1U_0402_16V4Z~D
SPDIF_ IN//GPIO0/EAPD
AUD_SPDIF_OUT
48
SPDIF _OUT
36 AUD_SPDIF_OUT
C782
0.1U_0402_16V4Z~D
@
47
R823
10K_0402_5%~D
2
7
26
42
49
DVSS
AVSS1
AVSS2
CAP2
Thermal PAD GND
VREFFILT
QFN 7x7 & LQFP 9x9 colay footprint.
STAC9205X5NBEB1XR_QFN48_COMON~D
AUD_PC_BEEP
33
27
1
2
A
C725
10U_0805_10V4Z~D
27 AUD_EAPD
AUD_EAPD
C724
10U_0805_10V4Z~D
Close to Pin 5
Title
Azalia (HD) Codec

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
26
of
66
C727
VREFOUT_R
R551
4.7K_0402_5%~D
2
1
R580
0_0402_5%~D
+VDDA
AUD_INT_MIC_IN 26
R565
100K_0402_5%~D
2
1
R567
100K_0402_5%~D
JSPK
SPKR_INR
OUTL-
26 AUD_HP_OUT_L
C749
1
1U_1206_25V7K~D
2
HP_INL_C
27
26 AUD_HP_OUT_R
C751
1
1U_1206_25V7K~D
2
HP_INR_C
26
15
HP_SPK_R1
22
HP_EN
25
MUTE#
GAIN1
31
AUD_GAIN1
GAIN2
32
AUD_GAIN2
REGEN
C1P
C1N
12
C1N
1U_0603_10V4Z~D
29
1
CPGND
1
2
R573
100K_0402_5%~D
SET
SET
MAX9789A_TQFN32~D
AUDIO_AVDD_ON 18
+VDDA
GAIN1
GAIN2
AV(inv)
MINIMAM 150 mA
INPUT
IMPEDANCE
6dB
82K ohm
10dB
66K ohm
15.6dB
45K ohm
21.6dB
26K ohm
2 @
For
TPA6040A,
pop
C304,depop
R584
C747
10U_0805_10V4Z~D
C746
1U_0603_10V4Z~D
1
VOUT
11
For TPA6040A,pop C301,depop R585
C304
0.033U_1206_50V7K~D
10
R572
@ 100K_0402_5%~D
R585 0_0402_5%~D
1
2
1
2
@
C301
0.033U_1206_50V7K~D
C1P
R570
@ 100K_0402_5%~D
AUD_GAIN2
CPVDD
AUD_GAIN1
C757
1U_0603_10V4Z~D
HPVDD
R569
100K_0402_5%~D
C756
1U_0603_10V4Z~D
17
Gain Setting
HPR
C758
2
@
1
3
C232
10P_0402_50V8J~D
SPKR_EN#
Q42
2N7002W-7-F_SOT323-3~D
23
C745
10U_0805_10V4Z~D
HP_SPK_L1
R790
10_0402_5%~D
2
G
C744
1U_0603_10V4Z~D
16
INT_SPK_R2
R584
OUTR-
20
19
HPL
C755
1U_0603_10V4Z~D
1 C754
1U_0603_10V4Z~D
OUTR+
0_0402_5%~D
AUD_AMP_MUTE#
R822
1M_0402_1%~D
2
1
AUD_EAPD
INT_SPK_R1
BIAS
EP
GND
PGND1
PGND2
AUD_SPK_ENABLE#
C753
10U_0805_10V4Z~D
+5V_SPK+AMP
74AHCT1G08GW_SOT353-5~D
1
24
2
G
MAX9789A
PVSS
CPVSS
2 @
1
1U_0603_10V4Z~D
HP_INR
33
28
5
21
2
C752
HP_INL
14
13
Y
B
2 @
U40
2
1
1
2 @
FOX_JA9033L-B1N6-7F~D
+5V_SPK+AMP
C96
47P_0402_50V8J~D
+5V_SPK+AMP
R712
100K_0402_5%~D
8
18
26 AUD_LINE_OUT_R
NB_MUTE#
PVDD1
PVDD2
Q43
2N7002W-7-F_SOT323-3~D
38
30
OUTL+
+5V_SPK+AMP
AUD_EAPD
VDD
SPKR_INL
C907
47P_0402_50V8J~D
SPKR_INR_C
NB_MUTE#
26
2
U37
SPKR_INL_C
AUD_HP_NB_SENSE 2
AUD_SPK_ENABLE#
0.033U_1206_50V7K~D
1
AUD_AMP_MUTE#
R571
100K_0402_5%~D
0.033U_1206_50V7K~D
1
2
AUDIO_AVDD_ON 1
2
@ R714
0_0402_5%~D
C748
2
5
7
8
W=40mils
C77
2
Place Close to Audio Chip
26 AUD_LINE_OUT_L
R713
100K_0402_5%~D
For TPA6040A,pop
R714,depop R713
C783
0.1U_0402_16V4Z~D
+5V_SPK+AMP
+5V_SPK+AMP
1
C743
1U_0603_10V4Z~D
C742
1U_0603_10V4Z~D
+5V_SPK+AMP
Place Close to Audio Chip
C906
47P_0402_50V8J~D
MOLEX_53398-0271~D
C905
47P_0402_50V8J~D
C741
100P_0402_50V8J~D
C740
100P_0402_50V8J~D
L51
1
2
+5V_RUN
1
2
HP_SPK_R2
C739
100P_0402_50V8J~D
Speaker Connector
JAUDIO
1
2
6
3
HP_SPK_L2
2
1
L50
BLM18BD121SN1D_0603~D
C738
100P_0402_50V8J~D
L49
HP_SPK_L1
2
1
HP_SPK_R1
15 mils trace
FOX_JA9033L-B1N6-7F~D
+3.3V_RUN
1
2
5
7
8
26 AUD_MIC_SWITCH
R568
1K_0402_5%~D
INT_SPK_R1
INT_SPK_R2
C735
100P_0402_50V8J~D
+3.3V_RUN
C734
100P_0402_50V8J~D
JMIC
1
2
6
3
1
2
1
0_0402_5%~D
L48
C730
1U_0603_10V6K~D
C733
0.1U_0805_25V7K~D
1
R566
1K_0402_5%~D
2
R797
8
IN-
C736
R563
0.1U_0402_10V6K~D 10K_0402_5%~D
C737
2.2U_0805_10V6K~D
2
1
L47
1
2
1
0_0402_5%~D
2
R796
IN+
2
10U_0805_10V4Z~D
R562
20K_0402_1%~D
MIC_R2
MIC_R1 1
32 AUD_INT_MIC-
32 AUD_INT_MIC+
C732
2.2U_0805_10V6K~D
C728
1U_0603_10V6K~D
MIC_L1 1
MIC_L2
2
U36B
LM358DR2G_SOIC8~D
G
4
C731
R560
0.1U_0402_10V6K~D 10K_0402_5%~D
5
1
2
1
2
R557
5.1_0402_1%~D
+VDDA
2
3
IN-
26 AUD_EXT_MIC_R
R558
1K_0402_5%~D
R559
100K_0402_5%~D
AUD_MIC_BIAS 1
26 AUD_EXT_MIC_L
8
IN+
U36A
LM358DR2G_SOIC8~D
R555
5.1_0402_1%~D
2
1
AUD_MIC_BIAS
1
R556
100K_0402_5%~D
R554
0_0402_5%~D
1
2
R561
20K_0402_1%~D
2
1
R553
1K_0402_5%~D
C729
2.2U_0805_10V6K~D
2
1
R564
100K_0402_5%~D
+VDDA
+VDDA
2
1
R552
4.7K_0402_5%~D
VREFOUT
Title
AMP and PHONE JACK

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
27
of
66
REGCTL_PNP12
Q71
PBSS5540Z_SOT223-3~D
C849
0.1U_0402_16V4Z~D
C850
0.1U_0402_16V4Z~D
XTALI
C862
Y5
25MHZ_18PF_1BX25000CK1D~D
REGSEN12
REGSUP25
REGCTL25
J12
L12
M11
REGSEN25
M12
+2.5V_LAN
PCIE_TXDN
M3
GLAN_RXN_C
C851
0.1U_0402_10V7K~D
1
2
PCIE_RX6-/GLAN_RX- 23
PCIE_TXDP
L3
GLAN_RXP_C
PCIE_RXDN
L7
PCIE_RXDP
M7
WAKE
REFCLKREFCLK+
CLKREQ#
REFCLK_SEL
PERST
A4
L5
M5
F2
B3
B1
TCK
TDI
TDO
TMS
TRST
GPHY_TVCOI
NC
NC
B5
F3
B4
E3
D4
C6
J1
M4
RDAC
REGCTL_PNP12
REGCTL_PNP25
2
C853
0.1U_0402_10V7K~D
2
0_0402_5%~D
1
2
+3.3V_LAN
@ R663
4.7K_0402_5%~D
@ C863
4.7U_0603_6.3V4Z~D
BCM5755M_FBGA144~D
VDDIO_0
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
A5
G3
L11
VDDP_0
VDDP_1
VDDP_2
+XTALVDD
H12
XTALVDD
+PCIE_SDS_VDD
K4
+BIASVDD
A12
BIASVDD
+AVDDL
F10
F11
AVDDL_0
AVDDL_1
+AVDD
A11
F12
AVDD_0
AVDD_1
+PCIE_PLLVDD
1
C860
0.1U_0402_16V4Z~D
+PCIE_SDS_VDD
1
C864
@
0.1U_0402_16V4Z~D
GND
K6
+PCIE_PLLVDD
G12
PCIE_SDSVDD
BIAS
Analog
power
PCIE_PLLVDD
PLL
GPHY_PLLVDD
+3.3V_LAN
+3.3V_LAN
C835
0.1U_0402_16V4Z~D
2
D
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
B2
B10
E4
E5
E6
E7
E8
E9
F4
F5
F6
F7
F8
F9
G5
G6
G7
G8
L2
L6
M6
DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8
DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
A1
A6
A7
B7
C1
C3
D1
D2
D3
E1
G2
H2
K1
K2
K3
K7
K8
L4
L8
M8
A2
E2
G1
G9
H1
H10
J10
K10
K11
BCM5755M_FBGA144~D
Reserved for BCM5752

as back-up solution
+3.3V_LAN
1
2
R661
4.7K_0402_5%~D
U44
8
7
6
5
Q
VSS
VCC
W#
D
C
RESET#
S#
1
2
3
4
LOM_SO
LOM_SCLK
NV_STRAP1
LOM_CS#
@
8
7
6
5
SO
GND
VCC
WP#
SO
SI
CS#
SCLK
Atmel AT45BCM021B
ST M45PE20
Auto-Sense Mode
M45PE20-VMN6TP_SO8~D
C834
0.1U_0402_16V4Z~D
C833
0.1U_0402_16V4Z~D
C832
0.1U_0402_16V4Z~D
C831
0.1U_0402_16V4Z~D
C858
0.1U_0402_16V4Z~D
NV_STRAP0
(Default)
U45
SI
SCK
RESET#
CS#
1
2
3
4
AT45BCM021B-SU_SO8~D
Title
BCM5755M
Size
Document Number
Rev
0.4
LA-3302P
Date:
+2.5V_LAN
+GPHY_PLLVDD
LOM_SI
R663 Reserved for

BCM5752 as back-up
solution
C856
0.1U_0402_16V4Z~D
Place R666 as
close to the ASIC
as possible. Pad
is needed to
measure 125MHz
clock for
debugging
BCM5755M
VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
A3
C2
D10
F1
G10
J2
L1
+GPHY_PLLVDD
2
1
BK1608LM182-T_0603~D1
PCIE_TX6-/GLAN_TX- 23
Digial power
L88
PCIE_WAKE#
PCIE_WAKE# 34,38
CLK_PCIE_LOM#
CLK_PCIE_LOM# 6
CLK_PCIE_LOM
CLK_PCIE_LOM 6
1
2
LOM_CLKREQ# 6
R656
0_0402_5%~D
1
2
@ R657
4.7K_0402_5%~D
2
1
SB_LOM_PCIE_RST# 21
0_0402_5%~D @ R582
LOM_RST_R# 2
1 PLTRST3#
PLTRST3#
21,34
0_0402_5%~D
R581
@ R658
4.7K_0402_5%~D
1
2
A8
LOM_CABLE_DETECT goes to an input on a system microcontroller that can

poll this signal periodically and can de-assert the LOM_LOW_PWR when
LOM_CABLE_DETECT signal is high. Connect to an EC GPIOC defined by the
GPIO mapping.
C859
4.7U_0603_6.3V4Z~D
PCIE_RX6+/GLAN_RX+ 23
Monitor GPHY PLL Clk
Layout Notice : No high

speed signal should be
routed near RDAC or on
adjacent layer to RDAC
2
1
BK1608LM182-T_0603~D1
L68
2
1
BK1608LM182-T_0603~D1
PCIE_TX6+/GLAN_TX+ 23
PHYTVCOI 1
@ R666
+3.3V_LAN
+AVDDL
C857
4.7U_0603_6.3V4Z~D
+1.2V_LAN
+3.3V_LAN
L67
K12
J11
U38B
D5
D6
D7
D8
H5
H6
H8
J4
R276
39K_0402_5%~D
REGSUP12
REGCTL12
+3.3V_LAN
C855
4.7U_0603_6.3V4Z~D
1
+3.3V_RUN
1K_0402_5%~D
1
+3.3V_LAN
1K_0402_5%~D
+1.2V_LAN
L66
2
1
BK1608LM182-T_0603~D1
R647
20K_0402_5%~D
2
1
LOM_SUPER_IDDQ 38
LOM_LOW_PWR 38
C865
XTALI
Logic High Voltage must

be 0.7V to 2.75V
0.1U_0402_16V4Z~D
Need to ensure
crystal at least
300uW max power
drive-level
L9
XTALO
B6
R665
4.7K_0402_5%~D
2
1
M9
0_0402_5%~D
R488 1
2
R650
2
R652
XTALO
22P_0402_50V8J~D
22P_0402_50V8J~D
2
1
200_0402_1%~D
Clock
C861
R659
VAUXPRSNT
G11
R669
LINKLED
SPD100LED
SPD1000LED
TRAFFICLED
VMAINPRSNT
H4
K5
29 LOM_ACTLED_YEL#
LOM_SPD10LED_GRN# A9
LOM_SPD100LED_ORG# B9
A10
LOM_ACTLED_YEL#
B8
SCLK
SI
SO
CS
NV_STRAP0
NV_STRAP1
LED
29 LOM_SPD10LED_GRN#
29 LOM_SPD100LED_ORG#
C9
E10
D9
C10
M2
M1
SPI
LOM_SCLK
LOM_SI
LOM_SO
LOM_CS#
NV_STRAP0
+3.3V_LAN
@ R655
4.7K_0402_5%~D
1
2
SMB_CLK
SMB_DATA
SMBUS
C8
C7
Regulator
Control
GPIO
LOW_PWR
Super_Low_PWR
PCI-E
GPIO0
GPIO1_SERIAL_DI
GPIO2_SERIAL_DO
EnergyDet
R646, R648, R649 Reserved for

BCM5752 as back-up solution
23,34 ICH_SMBCLK
23,34 ICH_SMBDATA
TPM_GPIO0
TPM_GPIO1
TPM_GPIO2/TPM_STATUS
TPM_EN
29
29
29
29
29
29
29
29
1.13K_0402_1%~D
LFRAME
LRESET
SERIRQ
TEST
G4
1 10K_0402_5%~D TPM_GPIO0
J3
1 10K_0402_5%~D TPM_GPIO1
H3
1 10K_0402_5%~D TPM_GPIO2
1
J6
38 LOM_TPM_EN#
0_0402_5%~D
2
1
@ R653 4.7K_0402_5%~D
LOM_SMB_ALERT#
H9
23,39 LOM_SMB_ALERT#
GPIO1_SERIAL_DI
H11
LOM_LOW_PWR 1
2 GPIO2_SERIAL_DO C5
R422
C4
1K_0402_5%~D
38 LOM_CABLE_DETECT
2
2
2
2
R651
Media
J9
M10
H7
Power
Control
LPC_LFRAME#
PLTRST3#
IRQ_SERIRQ
Bias
@@@
LAD0
LAD1
LAD2
LAD3
LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-
C848
J7
L10
J5
K9
LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-
B11
B12
C11
C12
D11
D12
E11
E12
0.1U_0402_16V4Z~D
R646
R648
R649
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
TRD3+
TRD3TRD2+
TRD2TRD1+
TRD1TRD0+
TRD0-
0.1U_0402_16V4Z~D
C852
0.1U_0402_16V4Z~D
+1.2V_LAN
+AVDD
C847
22,38,39 LPC_LFRAME#
21,34 PLTRST3#
LCLK
LPC/TPM
J8
+2.5V_LAN
2
1
BK2125LM182-T_0805~D 1
BCM5755M
CLK_PCI_TPM
L65
U38A
6 CLK_PCI_TPM
22,38,39 LPC_LAD[0..3]
+BIASVDD
1
R664
4.7K_0402_5%~D
2
1
1
2
@
C846
10U_0805_10V4Z~D
2
1 LOM_LOW_PWR
R421
4.7K_0402_5%~D
2
1
BK1608LM182-T_0603~D
1
C843
R415
4.7K_0402_5%~D
2
1 GPIO1_SERIAL_DI
C845
C854
22P_0402_50V8J~D
L64
+3.3V_LAN
+1.2V_LAN
0.1U_0402_16V4Z~D
R654
33_0402_5%~D
@
+2.5V_LAN
2 @
C842
2
4
1
@ C772
0.047U_0402_16V4Z~D
1
+XTALVDD
1
C830
0.1U_0402_16V4Z~D
L63
2
1
BK2125LM182-T_0805~D
C829
0.1U_0402_16V4Z~D
+2.5V_LAN
R670
4.7K_0402_5%~D
2
1
1
2
5
6
REGCTL_PNP25
C771
0.047U_0402_16V4Z~D
1
2
R644
2_1210_5%~D
1
R643
2
C840
0.1U_0402_16V4Z~D
C839
0.1U_0402_16V4Z~D
C838
0.1U_0402_16V4Z~D
C837
0.1U_0402_16V4Z~D
C836
4.7U_0603_6.3V4Z~D
R7, R9 are 1/2 W rating
2_1210_5%~D
D
G
3
C316
0.1U_0402_16V4Z~D
C309
4.7U_0603_6.3V4Z~D
+1.2V_LAN
10U_0805_10V4Z~D
CLK_PCI_TPM
0.1U_0402_16V4Z~D
Place closely pin J8
1
C825
41 ENAB_3VLAN
1
C824
+3.3V_LAN
4.7U_0603_6.3V4Z~D
C827
6
5
2
1
Q70
MBT35200MT1G_TSOP6~D
0.1U_0402_16V4Z~D
E
3
C826
C
4
0.1U_0402_16V4Z~D
Layout Notice : 1.2V filter. Place as close

chip as possible.
+3.3V_LAN
B
1
Q44
+3.3V_LAN
4.7U_0603_6.3V4Z~D
+3.3V_ALW
C828
0.1U_0402_16V4Z~D
Layout Notice : Place as close

chip as possible.
MMJT9435
C
2
C629
4.7U_0603_6.3V4Z~D
Sheet
1
28
of
66
LAN ANALOG
SWITCH
C866
2 0.1U_0402_16V4Z~D
C867
2 0.1U_0402_16V4Z~D
C868
2 0.1U_0402_16V4Z~D
@
D
C869
2 0.1U_0402_16V4Z~D
R671
R672
R673
R674
R675
R676
R677
R678
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
@ 49.9_0402_1%~D
@ 49.9_0402_1%~D
@ 49.9_0402_1%~D
@ 49.9_0402_1%~D
@ 49.9_0402_1%~D
@ 49.9_0402_1%~D
@ 49.9_0402_1%~D
@ 49.9_0402_1%~D
LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+
Layout Notice : Place

termination as close as
ASIC as possible
The resistors need at
least 1/16W
U46
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
56
50
38
27
18
10
4
+3.3V_LAN
28
LAN_TX0-
28
LAN_TX0+
28
LAN_TX1-
28
LAN_TX1+
28
LAN_TX2-
28
LAN_TX2+
28
LAN_TX3-
28
LAN_TX3+
36,38
DOCKED
LAN_TX0LAN_TX0-R
1
2
L69
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX0+ 1
LAN_TX0+R
2
L70
36NH_0603CS-360EJTS_5%_0603~D
2
3
0B1
1B1
48
47
SW_LAN_TX0SW_LAN_TX0+
A1
2B1
3B1
43
42
4B1
5B1
37
36
A0
SW_LAN_TX0- 32
SW_LAN_TX0+ 32
SW_LAN_TX1- 32
SW_LAN_TX1+ 32
A2
A3
6B1
7B1
32
31
LAN_TX2LAN_TX2-R
1
2
L73
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX2+ 1
LAN_TX2+R
2
L74
36NH_0603CS-360EJTS_5%_0603~D
11
A4
12
A5
0LED1
1LED1
2LED1
22
23
52
LAN_LEDACT#
LINK_LED10#
LINK_LED100#
LAN_TX3LAN_TX3-R
1
2
L75
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX3+ 1
LAN_TX3+R
2
L76
36NH_0603CS-360EJTS_5%_0603~D
14
A6
0B2
1B2
46
45
DOCK_LAN_TX0DOCK_LAN_TX0+
15
A7
2B2
3B2
41
40
DOCKED
17
SEL
4B2
5B2
35
34
19
20
54
LED0
LED1
LED2
6B2
7B2
30
29
0LED2
1LED2
2LED2
25
26
51
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_SPD100LED_ORG#
Layout Notice : Place bead as

close PI3L500 as possible
28 LOM_ACTLED_YEL#
28 LOM_SPD10LED_GRN#
28 LOM_SPD100LED_ORG#
NC
SW_LAN_TX3- 32
SW_LAN_TX3+ 32
DOCK_LAN_TX0- 36
DOCK_LAN_TX0+ 36
DOCK_LAN_TX1- 36
DOCK_LAN_TX1+ 36
DOCK_LAN_TX2- 36
DOCK_LAN_TX2+ 36
DOCK_LAN_TX3- 36
DOCK_LAN_TX3+ 36
DOCK_LOM_ACTLED_YEL# 36
DOCK_LOM_SPD10LED_GRN# 36
DOCK_LOM_SPD100LED_ORG# 36
PAD_GND
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
57
SW_LAN_TX2- 32
SW_LAN_TX2+ 32
LAN_TX1LAN_TX1-R
1
2
L71
36NH_0603CS-360EJTS_5%_0603~D
LAN_TX1+ 1
LAN_TX1+R
2
L72
36NH_0603CS-360EJTS_5%_0603~D
FROM NIC
DOCKED
1: TO DOCK
1
6
9
13
16
21
24
28
33
39
44
49
53
55
PI3L500-AZFEX_TQFN56~D
TO
DOCK
0: TO RJ45
10K_0402_5%~D
@
10K_0402_5%~D
R681
@
2
1
1
R679
2
10K_0402_5%~D
@
R680
2
1
+3.3V_LAN
LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#
R682
LAN_LEDACT#
LINK_LED10#
150_0402_5%~D
R683
1
2
LED_10_GRN_R#
LINK_LED100#
110_0402_5%~D
R684
1
2
LED_100_ORG_R#
LAN_ACTLED_YEL_R#
LAN_ACTLED_YEL_R# 32
LED_10_GRN_R# 32
LED_100_ORG_R# 32
200_0402_5%~D
Title
5
LAN TRANSFOMER
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
29
of
66
C792
0.1U_0402_16V4Z~D
+3.3V_RUN
C791
0.1U_0402_16V4Z~D
C790
4.7U_0603_6.3V4Z~D
+5V_RUN
4.7U_0603_6.3V4Z~D
C793
R602
5
4
USB_A0
USB_B0
USB_A1
USB_B1
14
13
12
11
USBP6CBS_CAD15
USBP6+
CBS_CAD13
USBP6-
23
USBP6+
23
2
1
R604
0_0402_5%~D
1
2
R606
0_0402_5%~D
1
2
L61
CCLK
CFRAME#
CIRDY#
CTRDY#
CDEVSEL#
CSTOP#
CPAR
CPERR#
CSERR#
CREQ#
CGNT#
CINT#
CBLOCK#
CCLKRUN#
CRST#
R2_D2
R2_D14
R2_A18
CVS1
CVS2
CCD1#
CCD2#
106
110
109
107
105
103
98
100
119
121
102
104
101
4
117
2
85
99
12
15
10
14
CBS_CFRAME#
C BS_CIRDY#
CBS_CTRDY#
CBS_CDEVSEL#
CBS_CSTOP#
CBS_CPAR
CBS_CPERR#
CBS_CSERR#
CBS_CREQ#
CBS_CGNT#
CBS_CINT#
CBS_CBLOCK#
CBS_CCLKRUN#
CBS_CRST#
CBS_RSVD/D2
CBS_RSVD/D14
CBS_RSVD/A18
CBS_CVS1
CBS_CVS2
CBS_CCD1#
CBS_CCD2#
CSTSCHG
13
CBS_CSTSCHNG
R614
123
111
95
86
TPA0+
TPA0-
TPB0+
TPB0-
0_0402_5%~D
1
2
1
L62
R642
56.2_0402_1%~D
CBS_CAD9
CBS_CAD11
CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR
CBS_CPERR#
CBS_CGNT#
CBS_CINT#
+CBS_VCC
CBS_CCLK
C BS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#
OZ711EZ1TN C_E-LQFP128_16X16~D
TPA0_D-
TPB0_D+
4
3
2
1
TPA+
TPATPB+
TPB-
GND
GND
GND
GND
5
6
7
8
TPB0_D-
@ DLW21SN121SQ2_0805~D
R611
0_0402_5%~D
1
2
R612
0_0402_5%~D
1
2
JCBUS
CBS_CCLK
J1394
Layout Note: Place close to 1394 connector
CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#
TPA0_D+
TYCO_2-1775815-2~D
2
1
@ DLW21SN121SQ2_0805~D
4
3 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND1
A_CAD0
A_CAD1
A_CAD3
A_CAD5
A_CAD7
A_PCI_C/BE0#
GND2
A_CAD9
A_CAD11
A_CAD12
GND3
A_CAD14
A_PCI_C/BE1#
A_CPAR
GND4
A_CPERR#
A_CGNT#
A_CINT#
+AVCC0
+AVPP0
A_CCLK
A_CIRDY
A_PCI_C/BE2#
A_CAD18
A_CAD20
GND5
A_CAD21
A_CAD22
A_CAD23
A_CAD24
GND6
A_CAD25
A_CAD26
A_CAD27
GND7
A_CAD29
CB_A_D2
A_CCLKRUN#
GND8
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND9
A_CCD1#
A_CAD2
A_CAD4
A_CAD6
CB_A_D14
A_CAD8
GND10
A_CAD10
A_CVS1
A_CAD13
GND11
A_CAD15
A_CAD16
CB_A_A18
GND12
A_CBLOCK#
A_CSTOP#
A_CDEVSEL#
+AVCC1
+AVPP1
A_CTRDY#
A_CFRAME#
A_CAD17
A_CAD19
A_CVS2
GND13
A_CRST#
A_CSERR#
A_CREQ#
A_PCI_C/BE3#
GND14
A_CAUDIO
A_CSTSCHG
A_CAD28
GND15
A_CAD30
A_CAD31
A_CCD2#
GND16
CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13
CBS_CAD15
CBS_CAD16
CBS_RSVD/A18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#
+CBS_VCC
CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
C810
0.1U_0402_16V4Z~D
CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD15
CBS_CAD14
CBS_CAD13
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0
3
1
128
127
126
125
124
122
120
118
116
115
114
113
112
96
94
93
92
91
90
89
88
87
84
83
81
80
79
78
77
76
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CC/BE3#
CC/BE2#
CC/BE1#
CC/BE0#
VCC/VPP
VCC/VPP
+CBS_VCC
12P_0402_50V8J~D
IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
REQ#
GNT#
PCI_RST#
PME#
SERIRQ
TPBIAS0
9
45
42
39
40
41
43
44
17
18
5
7
6
C809
0.1U_0402_16V4Z~D
C/BE3#
C/BE2#
C/BE1#
C/BE0#
OZ711EZ1
71
70
69
67
66
2
0_0402_5%~D
28
38
46
55
GND
GND
+3.3V
+3.3V
C823
1
R114
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
33
20
16
15
18
17
24.576MHz_16P_1BG24576CKIA~D
C805
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
1
@
2
1.8VOUT
EPSI
270P_0402_50V7K~D
IRQ_SERIRQ
19
20
21
22
23
24
25
27
29
30
31
32
34
35
36
37
47
48
49
50
51
52
53
54
57
58
59
60
61
62
63
64
BIAS
TPA+
TPATPB+
TPB-
X2
R613
5.11K_0402_1%~D
CBS_IDSEL
CLK_PCI_PCM
PCI_DEVSEL#
PCI_FRAME#
PCI _IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_REQ1#
PCI_GNT1#
PCI_RST#
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
74
75
R609
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
19
1
+5V
+5V
OZ2532SN_SSOP20~D
56.2_0402_1%~D
21,35
21,35
21,35
R615
21,35
100_0402_5%~D
PCI_AD17
1
2
6 CLK_PCI_PCM
21,35 PCI_DEVSEL#
21,35,36 PCI_FRAME#
21,35,36 PCI_IRDY#
21,35 PCI_TRDY#
21,35 PCI_STOP#
21,35 PCI_PAR
21 PCI_REQ1#
21 PCI_GNT1#
21,31,35 PCI_RST#
35,38 SYS_PME#
CORE_3.3A
CORE_3.3A
CORE_3.3A
XI
XO
R603
5.9K_0402_1%~D
1
2
R608
65
68
73
72
C807
1U_0603_10V4Z~D
PCI_VCC
PCI_VCC
U42
REF
R607
56.2_0402_1%~D
R610
10_0402_5%~D
CLK
PERR#
SERR#
RST#
CLKRUN#
INTA#
SKT_LED
C806
12P_0402_50V8J~D
1
2
56.2_0402_1%~D
CLK_PCI_PCM
CORE_1.8
CORE_1.8
26
56
33_0402_5%~D
CORE_3.3
CORE_3.3
GND
11
97
Place closely pin 45
23,38,39 CLKRUN#
21 PCI_PIRQD#
2
7
8
10
6
3
9
129
108
C804
0.1U_0402_16V4Z~D
21,35 PCI_AD[0..31]
C808
4.7P_0402_50V8C~D
16
82
EPSI
C798
0.1U_0402_16V4Z~D
C801
0.1U_0402_16V4Z~D
CLK_PCI_PCM
PCI_PERR#
PCI_SERR#
PCI_RST#
CLKRUN#
PCI_PIRQD#
21,35 PCI_PERR#
21,35 PCI_SERR#
+OZ1.8V_RUN
C797
4.7U_0603_6.3V4Z~D
L60
1
2
C800
0.1U_0402_16V4Z~D
C796
0.1U_0402_16V4Z~D
C803
0.1U_0402_16V4Z~D
C802
4.7U_0603_6.3V4Z~D
+3.3V_RUN
C795
0.1U_0402_16V4Z~D
+3.3V_RUN
C794
4.7U_0603_6.3V4Z~D
U41
D
CBS_CSTSCHNG
CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#
TYCO_1734648-1~D
A
Ground pin 129 exposed die pad, dimension

5.72mm x 5.72mm, should connect to PCB solder
pad of same dimension
Title
8
Cardbus and 1394 OZ711EZ1 Controller

Size
Document Number
Date:
Rev
0.4
LA-3302P
2
Sheet
30
1
of
66
USB SMARTCARD READER.

TYPE A (5V), B (3V), AB (5V/3V)
& USB SMARTCARDS ARE SUPPORTED.
R296
15K_0402_5%~D
2
1
6 CLK_SMC_48M
CLK_SMC_48M
MD0
R259
4.7K_0402_5%~D
2
1
R264
15K_0402_5%~D
2
1
R251
15K_0402_5%~D
2
1
R255
15K_0402_5%~D
2
1
PAD~D T40
PAD~D T41
12
RST#
14
15
RFIO0
RFIO1
3
4
32
1
2
XI/48M_IN
XO
MODE0/LED#
MODE1
MODE2
15K_0402_5%~D
15K_0402_5%~D
R257
2
1
R256
2
+SC_PWR
SC_RST#
SC_CLK
SC_C4
SC_IO
SC_DET#
NC1
NC2
NC3
7
30
31
GND0
GND1
GND2
9
11
26
SC_DET#
R129
27
24
23
22
25
13
R125
R126
R260
2
2
2
1 220_0402_5%~D
1 33_0402_5%~D
1 220_0402_5%~D
R130
1 220_0402_5%~D
SC_VCC
SC_RST#
SC_CLK
SC_C4
SC_IO
SC_DET#
47K_0402_5%~D
21
20
C129
1U_0603_10V4Z~D
EGATEDEGATED+
2
1U_0603_10V4Z~D
SCCDSCCD+
1
C305
C448
0.1U_0402_16V4Z~D
UPDUPD+
DPDDPD+
6
10
29
R263
10K_0402_5%~D
VCC5V_IN0
VCC5V_IN1
17
16
19
18
VR_CPR0
VR_CPR1
3V_CPR
38
OZ77CR6LN_QFN32~D
JSC
SCCD+
SCCDC91
0.1U_0402_16V4Z~D
PCI_RST#
3.3VCC
5
28
C425
1U_0603_10V4Z~D
1
2
21,30,35 PCI_RST#
+SC_PWR
U26
USBP4USBP4+
USBP4USBP4+
SC_USBPSC_USBP+
C446
4.7U_0603_6.3V4Z~D
23
23
25
25
C442
0.1U_0402_16V4Z~D
R252
1.5K_0402_1%~D
C435
0.1U_0402_16V4Z~D
2
+3.3V_RUN
+3.3V_RUN
C443
0.1U_0402_16V4Z~D
C428
4.7U_0603_6.3V4Z~D
+5V_RUN
C441
4.7U_0603_6.3V4Z~D
12
11
GND
GND
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
MOLEX_52207-1085~D
Place closely pin 3
CLK_SMC_48M
@
R258
10_0402_5%~D
@
C432
4.7P_0402_50V8C~D
Title
Smart Card OZ77CR6

Size
Document Number
Date:
Rev
0.4
LA-3302P
2
Sheet
31
1
of
66
@ FUSE4
L0603
1
2
@ FUSE1
LF453
1
2
+USB_BACK_PWR
D
+5V_ALW
38 USB_BACK_EN#
C169
0.1U_0402_16V4Z~D
U4
1
2
3
4
USB_BACK_EN#
GND
IN
EN1#
EN2#
USB_OC2_3#
8
7
6
5
OC1#
OUT1
OUT2
OC2#
USB_OC2_3#
23
C3
0.1U_0402_16V4Z~D
PJP4
PAD-OPEN 4x4m
2
1
TPS2062DR_SO8~D
C170
10U_0805_10V4Z~D
@
@ FUSE2
LF453
1
2
43
43
43
43
43
+USB_SIDE_PWR
+5V_ALW
PJP3
PAD-OPEN 4x4m
2
1
38 USB_SIDE_EN#
C2
0.1U_0402_16V4Z~D
U1
1
2
3
4
USB_SIDE_EN#
GND
IN
EN1#
EN2#
OC1#
OUT1
OUT2
OC2#
8
7
6
5
USB_OC0_1#
USB_OC0_1#
23
1
JIO
2
USBP0USBP0+
23 USBP023 USBP0+
@ FUSE5
L0603
1
2
+USB_SIDE_PWR
23 USBP123 USBP1+
BREATH_GREEN_LED
BATT_GREEN_LED
BATT_AMBER_LED
R_BT_ACT
R_MPCI_ACT
27 AUD_INT_MIC+
27 AUD_INT_MIC-
USBP1USBP1+
BREATH_GREEN_LED
BATT_GREEN_LED
BATT_AMBER_LED
R_BT_ACT
R_MPCI_ACT
TPS2062DR_SO8~D
C1
10U_0805_10V4Z~D
@
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
32
33
GND
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
GND
GND
GND
34
35
36
LAN_ACTLED_YEL_R#
SW_LAN_TX0+
SW_LAN_TX3-
LAN_ACTLED_YEL_R# 29
+3.3V_LAN
SW_LAN_TX0+
SW_LAN_TX1-
29
29
29
29
SW_LAN_TX2+
SW_LAN_TX3-
29
29
29
29
+2.5V_LAN
LED_10_GRN_R#
LED_100_ORG_R#
HDD_LED
LED_10_GRN_R# 29
LED_100_ORG_R# 29
HDD_LED 43
TYCO_3-1775014-0~D
+USB_SIDE_PWR
+USB_BACK_PWR
@
@
USBP0+
USBP1-
USBP3-
U2
D1+
GND
D2-
D2+
USBP1+
VCC
D1-
USBP2+
USBP0-
U16
D1+
D2+
GND
VCC
D1-
D2-
USBP2-
USBP3+
IP4220CZ6_SO6~D
IP4220CZ6_SO6~D
Place ESD diodes as close as USB connector.
L12
DLW21SN900SQ2_0805~D
23
USBP2+
@
23
23
USBP3-
USBP3+
L13
4
1
3
2
R149
0_0402_5%~D
1
2
R147
0_0402_5%~D
1
2
USBP2_D-
USBP2_D+
+USB_BACK_PWR
1
+
2
C9
0.1U_0402_16V4Z~D
1
JUSB1
2
3
2
R148
0_0402_5%~D
1
2
R150
0_0402_5%~D
1
2
USBP3_D-
USBP3_D+
C8
0.1U_0402_16V4Z~D
USBP2-
C168
150U_D2_6.3VM~D
23
USBP3_DUSBP3_D+
1
2
3
4
A_VCC
A_DA_D+
A_GND
USBP2_DUSBP2_D+
5
6
7
8
B_VCC
B_DB_D+
B_GND
9
10
11
12
G1
G2
G3
G4
FOX_UB9112C-SB201-4F~D
Rear USB Port
Rear USB Ports

A
Title
USB 2.0 Port

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
32
of
66
R235
0_0402_5%~D
1
2
RES 2
3 IAC_SDATA0
RES 4
5 GND
3.3V 6
7 IAC_SYNC
GND 8
9 IAC_SDATAIN
GND 10
ICH_RST_MDC_R#
3
Q31
BSS138W-7-F_SOT323~D
22 ICH_AZ_MDC_RST#
New MDC connector.

1 GND
2
G
+5V_SUS
1
R233
100K_0402_5%~D
R239
10K_0402_5%~D
18 MDC_RST_DIS#
11 IAC_RESET#
IAC_BITCLK 12
JMDC
Connector for MDC Rev1.5
C128
10P_0402_50V8J~D
A
ICH_AC_SDOUT_MDCTERM
TYCO_1-1775149-2~D
C127
10P_0402_50V8J~D
13
14
15
16
17
18
GND
GND
GND
GND
GND
GND
ICH_AZ_MDC_BITCLK
ICH_AZ_MDC_SYNC
MDC_SDIN
ICH_RST_MDC_R#
MDC_AC_BITCLK_TERM
22 ICH_AZ_MDC_SYNC
2
R128
33_0402_5%~D
R123
10_0402_5%~D
22 ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_BITCLK
22 ICH_AZ_MDC_BITCLK
W=20 mil
C125
0.1U_0402_16V4Z~D
2
4
6
8
10
12
C126
4.7U_0603_6.3V4Z~D
22 ICH_AZ_MDC_SDIN1
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK
R124
@ 10_0402_5%~D
+3.3V_SUS
ICH_AZ_MDC_SDOUT
1
3
5
7
9
11
Title
BT PORT and MDC

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
33
of
66
L8
23
USBP9-
23
USBP9+
1
4
@
2 2
USBP9_D-
USBP9_D+
3
R120
0_0402_5%~D
1
2
R121
0_0402_5%~D
1
2
JCLIP1
1
2
3
4
GND1
GND2
GND3
GND4
TYCO_1775837-1~D
SB_WWAN_PCIE_RST#
21 SB_WWAN_PCIE_RST#
@ R598
0_0402_5%~D
2
1
Mini WWAN
Mini-Card Latch
D
+3.3V_RUN
+3.3V_RUN
JMINI1
R18
1
@
2
+PWR_SRC
+3.3V_ALW
0_0402_5%~D
TYCO_1775837-1~D
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
6 CLK_PCIE_MINI1#
6 CLK_PCIE_MINI1
Q94
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
23 PCIE_IRX_WANTX_N1
23 PCIE_IRX_WANTX_P1
1
R782
470K_0402_5%~D
R786
100K_0402_5%~D
2
G
MINI1CLK_REQ#
6 MINI1CLK_REQ#
1
2
1
R783
200K_0402_5%~D
39 WLAN_3V_ENABLE
GND1
GND2
GND3
GND4
JCLIP2
1
2
3
4
2
G
Q96
2N7002W-7-F_SOT323-3~D
6
5
2
1
Q95
2N7002W-7-F_SOT323-3~D
WLAN_RADIO_DIS#_R
D1
RB751S40T1_SOD523-2~D
R784
100K_0402_5%~D
+3.3V_WLAN
R785
100K_0402_5%~D
2
1
38 WLAN_RADIO_DIS#
PCIE_WAKE#
28,38 PCIE_WAKE#
1
C270
4700P_0402_25V7K~D
23 PCIE_ITX_WANRX_N1_C
23 PCIE_ITX_WANRX_P1_C
21 PCIE_MCARD2_DET#
+3.3V_RUN
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
PCIE_MCARD2_DET#
1
R550
2
100K_0402_5%~D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
GND1
Mini-Card Latch
+1.5V_RUN
+SIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
WWAN_RADIO_DIS#
WWAN_PLTRST3#_R
WWAN_RADIO_DIS# 38
PLTRST3#
21,28
1 PLTRST3#
R597
0_0402_5%~D
+3.3V_RUN
ICH_SMBCLK
ICH_SMBDATA
ICH_SMBCLK 23,28
ICH_SMBDATA 23,28
USBP9_DUSBP9_D+
USB_MCARD2_DET# 23
T16 PAD~D
2
1
R574
100K_0402_5%~D
+3.3V_RUN
TYCO_1775838-1~D
@ R599
0_0402_5%~D
2
1
U53
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
23 PCIE_ITX_WLANRX_N2_C
23 PCIE_ITX_WLANRX_P2_C
23 PCIE_MCARD1_DET#
1
2
R548
100K_0402_5%~D
+3.3V_RUN
53
GND1
PLTRST3#
21,28
+SIM_PWR
UIM_DATA
SRV05-4.TCT_SOT23-6~D
+3.3V_RUN
WLAN_SMBCLK
WLAN_SMBDATA
R549 100K_0402_5%~D
1
2
+3.3V_RUN
1
USB_MCARD1_DET# 23
8051_RX
39
LED_WLAN_OUT# 43
BT_ACTIVE
40,43
8051_RX
LED_WLAN_OUT#
1
2
@ R11
0_0402_5%~D
C122
33P_0402_50V8J~D
GND2
54
HOST_DEBUG_TX 39
WLAN_RADIO_DIS#_R
WLAN_PLTRST3#_R
2
1PLTRST3#
R600
0_0402_5%~D
UIM_VPP
1
+
2
+1.5V_RUN
+3.3V_WLAN
C120
0.047U_0402_16V4Z~D
SUYIN_254020MA006G502ZL~D
2
C121
33P_0402_50V8J~D
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
23 PCIE_IRX_WLANTX_N2
23 PCIE_IRX_WLANTX_P2
HOST_DEBUG_TX
UIM_CLK
C445
330U_D2E_6.3VM_R25~D
HOST_DEBUG_RX
8051_TX
39 HOST_DEBUG_RX
39 8051_TX
C773
33P_0402_50V8J~D
6 CLK_PCIE_MINI2#
6 CLK_PCIE_MINI2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NC
UIM_VPP
UIM_DATA
C111
22U_0805_6.3VAM~D
2 0_0402_5%~D
2 0_0402_5%~D
1
1
NC
4
5
6
C444
33P_0402_50V8J~D
R91
R27
GND
VPP
I/O
C416
0.047U_0402_16V4Z~D
28,38 PCIE_WAKE#
40 COEX2_WLAN_ACTIVE
40 COEX1_BT_ACTIVE
6 MINI2CLK_REQ#
VCC
RST
CLK
C460
33P_0402_50V8J~D
+1.5V_RUN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
2
3
UIM_RESET
C124
33P_0402_50V8J~D
+3.3V_WLAN
JMINI2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
JSIM
UIM_RESET
UIM_CLK
C459
1U_0603_10V4Z~D
+3.3V_WLAN
+SIM_PWR
C123
33P_0402_50V8J~D
Mini WLAN
C449
0.047U_0402_16V4Z~D
SB_WLAN_PCIE_RST#
21 SB_WLAN_PCIE_RST#
R645
2.2K_0402_5%~D
2
1
R640
2.2K_0402_5%~D
2
1
TYCO_1775838-1~D
WLAN_SMBCLK
C163
4.7U_0603_6.3V4Z~D
C164
0.1U_0402_16V4Z~D
C36
0.1U_0402_16V4Z~D
C166
0.047U_0402_16V4Z~D
C41
0.047U_0402_16V4Z~D
C16
0.1U_0402_16V4Z~D
C15
0.047U_0402_16V4Z~D
C34
0.047U_0402_16V4Z~D
1
+
2
1
D
+3.3V_WLAN
1 R660
2
@ 0_0402_5%~D
WLAN_SMBDATA
+1.5V_RUN
PWR
Rail
@ Q45
2N7002W-7-F_SOT323-3~D
Q46
2N7002W-7-F_SOT323-3~D
1
2
@ R662
0_0402_5%~D
Voltage
Tolerance
Primary Power
Peak
Normal
ICH_SMBCLK 23,28
+3.3V
+-9%
1000
750
CLK_SCLK 6
+3.3Vaux
+-9%
330
250
+1.5V
+-5%
500
375
Aux Power
Normal
250 (Wake enable)

5 (Not wake enable)
NA
ICH_SMBDATA 23,28
CLK_SDATA 6
C283
330U_D2E_6.3VM_R25~D

Title
Mini Card
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
34
of
66
+5V_RUN
QUIETE#
U19
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD8
PCI_AD9
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC1
A1
A2
A3
A4
A5
A6
A7
A8
GND1
NC2
A9
A10
A11
A12
A13
A14
A15
A16
GND2
NC3
A17
A18
A19
A20
A21
A22
A23
A24
GND3
NC4
A25
A26
A27
A28
A29
A30
A31
A32
GND4
VCC4
OE1#
B1
B2
B3
B4
B5
B6
B7
B8
VCC3
OE2#
B9
B10
B11
B12
B13
B14
B15
B16
VCC2
OE3#
B17
B18
B19
B20
B21
B22
B23
B24
VCC1
OE4#
B25
B26
B27
B28
B29
B30
B31
B32
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
C33
0.047U_0402_16V4Z~D
1
R19
1K_0402_5%~D
C32
0.1U_0402_16V4Z~D
D3
RB751S40T1_SOD523-2~D
2
1
C28
0.1U_0402_16V4Z~D
+VCC_QBUF
D2
RB751S40T1_SOD523-2~D
+VCC_QBUFD
2
1
C29
0.1U_0402_16V4Z~D
1
2
DOCK_AD31
DOCK_AD30
DOCK_AD29
DOCK_AD28
DOCK_AD27
DOCK_AD26
DOCK_AD25
DOCK_AD24
DOCK_AD23
DOCK_AD22
DOCK_AD21
DOCK_AD20
DOCK_AD19
DOCK_AD18
DOCK_AD17
DOCK_AD16
DOCK_AD15
DOCK_AD14
DOCK_AD13
DOCK_AD12
DOCK_AD11
DOCK_AD10
DOCK_AD8
DOCK_AD9
DOCK_AD7
DOCK_AD6
DOCK_AD5
DOCK_AD4
DOCK_AD3
DOCK_AD2
DOCK_AD1
DOCK_AD0
PI5C34X2245BE_BQSOP80~D
DOCK_AD[0..31] 36
21,30 PCI_AD[0..31]
+3.3V_RUN
C31
0.047U_0402_16V4Z~D
1
2
2
3
4
5
6
7
8
9
10
11
21,30
21,30
21
21,30
21,30
21,30
21,30
PCI_TRDY#
PCI_STOP#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_TRDY#
PCI_STOP#
PCI_PLOCK#
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PAR
PCI_AD24
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
46
45
44
43
42
41
40
39
38
37
DOCK_PIRQA#
DOCK_GNT0#
DOCK_PCIRST#
DOCK_SPME#
DOCK_C_BE3#
DOCK_C_BE2#
DOCK_C_BE1#
DOCK_C_BE0#
DOCK_IRDY#
DOCK_FRAME#
14
15
16
17
18
19
20
21
22
23
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
34
33
32
31
30
29
28
27
26
25
DOCK_TRDY#
DOCK_STOP#
DOCK_LOCK#
DOCK_DEVSEL#
DOCK_PERR#
DOCK_SERR#
DOCK_PAR
DOCK_PCI_IDSEL
1
13
NC1
NC2
GND1
GND2
12
24
2
DOCK_PIRQA# 36
DOCK_GNT0# 36
DOCK_PCIRST# 36
DOCK_SPME# 36
DOCK_C_BE3# 36
DOCK_C_BE2# 36
DOCK_C_BE1# 36
DOCK_C_BE0# 36
DOCK_IRDY# 36
DOCK_FRAME# 36
21 PCI_PIRQA#
21,36 PCI_GNT0#
21,30,31 PCI_RST#
30,38 SYS_PME#
21,30 PCI_C_BE3#
21,30 PCI_C_BE2#
21,30 PCI_C_BE1#
21,30 PCI_C_BE0#
21,30,36 PCI_IRDY#
21,30,36 PCI_FRAME#
C35
0.1U_0402_16V4Z~D
36 DOCK_PCI_EN#
38 QBUFEN#
DOCK_PCI_EN#
INB
QBUFEN#
INA
U5
PCI_PIRQA#
PCI_GNT0#
PCI_RST#
SYS_PME#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI _IRDY#
PCI_FRAME#
VCC1
VCC2
1
R22
100K_0402_5%~D
QUIETE#
OE1
OE2
C26
0.1U_0402_16V4Z~D
1
2
36
48
47
35
U18
QUIETE#
TC7SH32FU_SSOP5~D
DOCK_TRDY# 36
DOCK_STOP# 36
DOCK_LOCK# 36
DOCK_DEVSEL# 36
DOCK_PERR# 36
DOCK_SERR# 36
DOCK_PAR 36
DOCK_PCI_IDSEL 36
PI5C162861BE_BQSOP48~D
Title
5
DOCKING BUFFER
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
35
of
66
+DC_IN
+DOCK_PWR_SRC
44
DOCK_PSID
DVI_TX5+
DVI_TX5-
53
53
53
53
53
53
DVI_TX2+
DVI_TX2DVI_TX1+
DVI_TX1DVI_TX0+
DVI_TX0DOCK_AD31
6 CLK_PCI_DOCK
35 DOCK_PIRQA#
39 DOCK_SMB_CLK
39 DOCK_SMB_DAT
39 CLK_DOCK
39
DAT_DOCK
CLK_PCI_DOCK
S15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
45
S45
47
48
49
50
51
52
53
54
55
S47
S48
S49
S50
S51
S52
S53
S54
S55
R20
10_0402_5%~D
15
@
C25
4.7P_0402_50V8C~D
125
126
127
128
M136
136
DOCK_RING
CRT_BLU
D_SERIRQ 38
DOCK_PCI_IDSEL 35
38
38
38
D_LAD1
D_LAD2
D_LAD3
D_LAD1
D_LAD2
D_LAD3
D_DLRQ1# 38
D_LFRAME# 38
DOCK_AD1
DOCK_AD0
DOCK_AD3
DOCK_AD4
DOCK_AD7
DVI_SCLK 52
DVI_SDATA 52
DVI_DETECT 52
DOCK_AD8
DOCK_C_BE0#
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_C_BE0# 35
DOCK_AD14
DOCK_AD15
35 DOCK_PAR
35 DOCK_SERR#
35 DOCK_LOCK#
DOCK_DEVSEL# 35
DOCK_IRDY# 35
35 DOCK_FRAME#
35 DOCK_C_BE2#
DOCK_C_BE2#
DOCK_AD16
DOCK_AD19
DOCK_AD20
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD27
DOCK_AD28
DOCK_AD30
DOCK_AD29
35 DOCK_SPME#
DOCK_GNT0# 35
USBP8USBP8+
TV_C
USBP8- 23
USBP8+ 23
35 DOCK_PCI_EN#
26 AUD_SPDIF_OUT
DOCK_SMB_PME# 38
CLK_KBD 39
29 DOCK_LOM_SPD10LED_GRN#
DAT_KBD 39
29 DOCK_LOM_SPD100LED_ORG#
DOCK_OWNS_PCI
+2.5V_LAN
C23
0.01U_0402_16V7K~D
1
2
C21
0.01U_0402_16V7K~D
2
1
C24
0.01U_0402_16V7K~D
1
2
C22
0.01U_0402_16V7K~D
2
1
29
29
29
29
29
29
29
29
DOCK_TIP
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
S160
S161
S162
S163
S164
S165
S166
S167
S168
S169
S170
S171
S172
S173
S174
S175
S176
S177
S178
S179
S180
S181
S182
S183
S184
S185
S186
S187
S188
S189
S190
193
194
195
196
S193
S194
S195
S196
205
206
207
208
209
210
211
212
213
214
215
216
217
218
S220
220
S222
S223
S224
S225
S226
S227
S228
S229
S230
S231
S232
S233
S234
S235
S236
S237
S238
S239
S240
S241
S242
S243
S244
S245
S246
S247
S248
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
S250
250
S252
S253
S254
S255
S256
S257
S258
S259
252
253
254
255
256
257
258
259
DOCK_DET#
DAT_DDC2 20,52
CLK_DDC2
20,52
HSYNC_R
VSYNC_R
HSYNC_R
VSYNC_R
20
20
D_CLKRUN# 38
D_LAD0 38
DOCK_SMB_ALERT# 39
D_LAD0
DOCK_SMB_ALERT#
DOCK_AD2
DOCK_AD5
DOCK_AD6
DOCK_AD12
DOCK_AD13
DOCK_C_BE1#
DOCK_PERR#
DOCK_STOP#
DOCK_TRDY#
DOCK_PERR# 35
DOCK_STOP# 35
DOCK_TRDY# 35
DOCK_C_BE3#
DOCK_AD25
DOCK_AD26
PCI_REQ0#
DOCK_PCIRST#
TV_CVBS
TV_Y
DOCK_LOM_ACTLED_YEL# 29
R_PIDEACT
R_PIDEACT
43
AUD_SPDIF_OUT
R791
10_0402_5%~D
M204
52
DOCK_DET#
TV_CVBS
20,52
CRT_RED
20,52
CRT_GRN
IN1
CRT_RED
DOCK_RING
CRT_GRN
DOCK_TIP
C150
JW IRE
1 1
2 2
3 3
4 4
Z3308
+3.3V_SUS
0.1U_0402_10V7K~D
1
CRT_BLU
CRT_BLU
U13
74AHC1G08GW_SOT353-5~D
IN2
TV_CVBS
MOLEX_53398-0471~D
20,52
DOCK_PWR_EN
52
MH7
SHLD4
MH8
MH9
SHLD5
SHLD7
MH11
MH10
SHLD6
SHLD8
MH12
MH13
MH15
MH13
MH15
MH14
MH16
MH14
MH16
TV_C
R12
TV_CVBS
R13
TV_Y
R14
2
150_0402_1%~D
2
150_0402_1%~D
2
150_0402_1%~D
1
1
DOCK_AD[0..31] 35
+DOCK_PWR_SRC
1
C18
1000P_0402_50V7K~D
Q3
DDTC144EUA-7-F_SOT323-3~D
3
38 DOCK_PWR_EN
SHLD3
SHLD2
TV_Y
TV_Y
2
1
2
2
Z3306
TV_C
TV_C
SHLD1
NB
no power dock
PWR_SRC
D
self power dock
Q2
2N7002W-7-F_SOT323-3~D
2
G
52
MH6
Z3307
R16
100K_0402_5%~D
MH2
R17
100K_0402_5%~D
29,38
IN2
DOCKED
R8
100K_0402_5%~D
1
2
IN1
MH5
MH2
0.1U_0402_16V4Z~D
PCI_FRAME# 2
MH1
PCI _IRDY#
DOCK_OWNS_PCI
21,30,35 PCI_IRDY#
21,30,35 PCI_FRAME#
U7
P8
G_DOC_PWRSRC
R4
100K_0402_5%~D
+5V_ALW
P7
P8
IN2
P7
P4
MH1
IN1
C40
0.1U_0402_16V4Z~D
U8
8
7
6
5
1
2
3
+3.3V_ALW
Z3305
+3.3V_RUN
C38
1
R10
200K_0402_5%~D
P3
P4
+DC_IN
C11
0.47U_0805_25V7K~D
1
P3
Q6
FDS4435BZ_SO8~D
C37
0.1U_0402_16V4Z~D
U6
NC7SZ04P5X_NL_SC70-5~D
P6
DOCK_AD0
DOCK_AD1
DOCK_AD2
DOCK_AD3
DOCK_AD4
DOCK_AD5
DOCK_AD6
DOCK_AD7
DOCK_AD8
DOCK_AD9
DOCK_AD10
DOCK_AD11
DOCK_AD12
DOCK_AD13
DOCK_AD14
DOCK_AD15
DOCK_AD16
DOCK_AD17
DOCK_AD18
DOCK_AD19
DOCK_AD20
DOCK_AD21
DOCK_AD22
DOCK_AD23
DOCK_AD24
DOCK_AD25
DOCK_AD26
DOCK_AD27
DOCK_AD28
DOCK_AD29
DOCK_AD30
DOCK_AD31
PCI_REQ0# 21
DOCK_PCIRST# 35
C267
10P_0402_50V8J~D
+3.3V_RUN
5
P
3
NC
A
G
PCI_GNT0# 2
P5
P6
DOCK_C_BE3# 35
+PWR_SRC
21,35 PCI_GNT0#
P5
P2
TYCO_2-1612415-1~D
TYCO_2-1612415-1~D
P1
P2
DOCK_AD17
DOCK_AD18
DOCK_AD21
+3.3V_RUN
P1
DOCK_C_BE1# 35
PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR
204
TYCO_2-1612415-1~D
S205
S206
S207
S208
S209
S210
S211
S212
S213
S214
S215
S216
S217
S218
C14
1000P_0402_50V7K~D
S125
S126
S127
S128
CRT_RED
C13
0.1U_0603_50V4Z~D
DVI_TX3+
DVI_TX3-
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
C20
0.1U_0603_50V4Z~D
DOCK_DET#
CRT_GRN
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
DVI_TX4DVI_TX4+
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
1
2
3
4
5
6
7
8
9
10
11
12
13
DVI_CLKDVI_CLK+
JDOCKC
53
53
JDOCKB
JDOCKA
R7
0_0402_5%~D
Title
5
DOCKING CONN
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
36
of
66
+3.3V_SUS
C167
0.1U_0402_16V4Z~D
C10
0.47U_0402_10V4Z~D
1
2
+3.3V_SUS
19,39,41,42,51 RUN_ON
23
FORCEON
22
FORCEOFF#
T1OUT
T2OUT
T3OUT
R1IN
R2IN
R3IN
R4IN
R5IN
9
10
11
4
5
6
7
8
TXD0#
RTS0
DTR0
DCD0
R I0
RXD0#
CTS0
DSR0
INVALID#
21
GND
25
10
11
C159
270P_0402_50V7K~D
C2T1IN
T2IN
T3IN
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
R2OUTB
C158
270P_0402_50V7K~D
2
14
13
12
19
18
17
16
15
20
3243V-
1
6
2
7
3
8
4
9
5
C157
270P_0402_50V7K~D
3243C2TXD0
RTS0#
DTR0#
DCD0#
RI0#
RXD0
CTS0#
DSR0#
V-
DCD0
DSR0
RXD0#
RTS0
TXD0#
CTS0
DTR0
R I0
C7
0.47U_0402_10V4Z~D
1
2
C156
270P_0402_50V7K~D
C1C2+
3243V+
C155
270P_0402_50V7K~D
24
1
27
C154
270P_0402_50V7K~D
3243C13243C2+
JSIO
V+
C153
270P_0402_50V7K~D
TXD0
RTS0#
DTR0#
DCD0#
RI0#
RXD0
CTS0#
DSR0#
C1+
C152
270P_0402_50V7K~D
38
38
38
38
38
38
38
38
U3
28
VCC
C6
0.1U_0402_10V7K~D
1
2
26
2
C12
0.1U_0402_10V7K~D
3243C1+
1
2
DCD0
DSR0
RXD0#
RTS0F
TXD0F#
CTS0
DTR0F
RI0
GND0
GND1
GND2
SUYIN_070921MR009S203BR~D
MAX3243ECUI+T_TSSOP28~D
C
C171
0.1U_0402_16V4Z~D
C175
0.1U_0402_16V4Z~D
+3.3V_ALW
U39
30
10
VCC1
VCC1
39
NC3
37
38
NC1
NC2
BC_A_DAT
34
BC_DATA
BC_A_CLK
35
BC_CLK
BC_A_INT#
36
BC_INT#
+3.3V_ALW
@ R131
100K_0402_5%~D
39
BC_A_DAT
39
BC_A_CLK
39
BC_A_INT#
R28
1K_0402_5%~D
2
1
40
TEST_PIN
41
GND_PAD
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16/GPIO_0
KSO17/GPIO_1
KSO18/GPIO_2
KSO19/GPIO_3
KSO20/GPIO_4
KSO21/GPIO_5
KSO22/GPIO_6
ECE1077
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
9
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
32
33
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
1
2
3
4
5
6
7
8
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO[0..17]
40
KYBD_DET# 40
KSI[0..7]
40
ECE1077-FZG_QFN40~D
Title
Serial & FIR

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
37
of
66
+3.3V_ALW
+3.3V_ALW
1
R248
SYS_PME#
2
10K_0402_5%~D
1
R247
PCIE_WAKE#
2
10K_0402_5%~D
+5V_ALW
1
R245
DOCK_SMB_PME#
2
10K_0402_5%~D
+3.3V_RUN
2
2 IMVP6_PROCHOT#
100K_0402_5%~D
1
R1
1
C101
0.1U_0402_16V4Z~D
1
C420
0.1U_0402_10V7K~D
1
C403
0.1U_0402_16V4Z~D
C95
0.1U_0402_16V4Z~D
34
57
85
108
U25
44 PSID_DISABLE#
52 PANEL_BKEN
29,36 DOCKED
36 DOCK_SMB_PME#
27 NB_MUTE#
47 1.05V_RUN_ON
51 GFX_CORE_ON
25 MODPRES#
GPIOD[3]/VBUS_DET
GPIOD[4]/OCS1_N
GPIOD[5]/OCS2_N
GPIOD[6]/OCS3_N
GPIOD[7]/OCS4_N
32
33
GPIOH[6]
GPIOH[7]
48 IMVP6_PROCHOT#
42 5V_3V_1.8V_1.25V_RUN_PWRGD
R220
100K_0402_5%~D
28 LOM_LOW_PWR
31 SC_DET#
43 LED_MASK#
52 GFX_DEVID2
R242 1
23 SIO_EXT_WAKE#
21 ICH_PME#
23 ICH_PCIE_WAKE#
34 WLAN_RADIO_DIS#
VGA_IDENTIFY
1 = Discrete Gfx
0 = UMA
34 WWAN_RADIO_DIS#
28 LOM_CABLE_DETECT
28 LOM_TPM_EN#
28 LOM_SUPER_IDDQ
2
1 PANEL_BKEN
R237
100K_0402_5%~D
18 ATF_INT#
LOM_LOW_PWR
SC_DET#
LED_MASK#
2 0_0402_5%~D
ICH_PME#
ICH_PCIE_WAKE#
WLAN_RADIO_DIS#
WWAN_RADIO_DIS#
1
2
R308
0_0402_5%~D
LOM_TPM_EN#
LOM_SUPER_IDDQ
VGA_IDENTIFY
CHIPSET_ID
R112
10K_0402_5%~D
2
1
BID1
BID0
ATF_INT#
88
89
90
91
92
93
94
95
CLK
126
123
122
RBIAS
SYSOPT1/GPIOH[2]
SYSOPT0/GPIOH[3]
109
110
111
112
GPIOF[7]
GPIOF[6]
GPIOF[5]
GPIOF[4]
113
114
IRTX
IRRX
115
116
117
118
GPIOF[3]/IRMODE/IRRX3B
GPIOF[2]/IRTX2
GPIOF[1]/IRRX2
GPIOF[0]/IRMODE/IRRX3A
REG_EN
CLKI (14.318 MHz)
64
CLK_SIO_14M
VSS
96
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLK_RUN#
DLDRQ1#
DSER_IRQ
55
53
50
48
43
38
45
40
DLPC
106
107
R108
10K_0402_5%~D
1
2
R107
10K_0402_5%~D
1
2
R238
10K_0402_5%~D
1
2
REV
X00
X01
X02
X03
@
BID0
@ R106
10K_0402_5%~D
BID1
@ R109
10K_0402_5%~D
R236
10K_0402_5%~D
CHIPSET_ID
LPC_LAD[0..3] 22,28,39
1
LPC_LFRAME# 22,28,39
PLTRST2# 21,39
CLK_PCI_5018 6
CLKRUN# 23,30,39
LPC_LDRQ0# 22
LPC_LDRQ1# 22
IRQ_SERIRQ 23,28,30,39
R94
10_0402_5%~D
2
1
LID_CL#
LID_CL#
40
C84
0.047U_0402_16V4Z~D
CLK_SIO_14M 6
RUNPWROK
105
LCD_TST
GPIOJ[4](VSS)
VSS
GPIOK[7](VSS)
VSS
VSS
VSS
VSS
VSS
GPIOJ[1](VSS)
11
17
23
36
51
72
87
121
128
D_LAD0 36
D_LAD1 36
D_LAD2 36
D_LAD3 36
D_LFRAME# 36
D_CLKRUN# 36
D_DLRQ1# 36
D_SERIRQ 36
RUNPWROK
39,42,48,54
LCD_TST
19
R240
10_0402_5%~D
1
C402
4.7P_0402_50V8C~D
2 @
BID1 BID0
0
0
1
1
0
1
0
1
LID_CL_SIO#
CLK_PCI_5018
R95
1M_0402_5%~D
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLRQ1#
D_SERIRQ
OUT65
PWRGD
ECE5028-NU_VTQFP128_14X14~D
+3.3V_ALW
+3.3V_ALW
1
2
@ R72
10K_0402_5%~D
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5018
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
LPC
GPIOG[0]
GPIOG[1]
GPIOG[2]
GPIOG[3]
GPIOG[4]
GPIOG[5]
GPIOG[6]
GPIOG[7]
@ R221
10K_0402_5%~D
Route RBIAS and its

return to pin 128 very
short.
54
52
49
47
42
41
56
37
46
44
39
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
+3.3V_ALW
35
GPIOI[7](ATEST)
C93
4.7U_0603_6.3V4Z~D
63
28
29
30
31
D_DLRQ1#
125
124
120
86
127
GPIOI[4](XTAL1/CLKIN)
GPIOI[3](XTAL2)
C88
0.1U_0402_16V4Z~D
GFX_CORE_ON
MODPRES#
TEST
C94
0.1U_0402_16V4Z~D
GPIOD[1]
GPIOD[2]
GPIO
2
R231
2
R232
2
R234
D_SERIRQ
TEST_PIN is a No Connect
TEST_PIN
C90
0.1U_0402_16V4Z~D
61
62
HD DC_EN
MODC_EN
25 HDDC_EN
25 MODC_EN
+3.3V_ALW
LID_CL_SIO#
1.05V_RUN_ON
AUD_SPDIF_SHDN
DOCK_HP_MUTE#
AUD_HP_NB_SENSE
26 AUD_SPDIF_SHDN
26 DOCK_HP_MUTE#
D_CLKRUN#
2
0_0402_5%~D
GPIOB[0]/INIT#
GPIOB[1]/SLCTIN#
GPIOC[2]/SCLT
GPIOC[3]/PE
GPIOC[4]/BUSY
GPIOC[5]/ACK#
GPIOC[6]/ERROR#
GPIOC[7]/ALF#
GPIOD[0]/STROBE#
GPIOC[1]/PD7
GPIOC[0]/PD6
GPIOB[7]/PD5
GPIOB[6]/PD4
GPIOB[5]/PD3
GPIOB[4]/PD2
GPIOB[3]/PD1
GPIOB[2]/PD0
QBUFEN#
DOCK_PWR_EN
ADAPT_OC
ADAPT_TRIP_SET
ITP_DBRESET#_R
PSID_DISABLE#
PANEL_BKEN
DOCKED
DOCK_SMB_PME#
NB_MUTE#
35
QBUFEN#
36 DOCK_PWR_EN
49
ADAPT_OC
49 ADAPT_TRIP_SET
+3.3V_RUN
1
@ R806
65
66
67
68
69
70
71
73
74
75
76
77
78
79
80
81
82
@ C89
4.7U_0603_6.3V4Z~D
7,23 ITP_DBRESET#
USB_SIDE_EN#
GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)
GPIOI[2](VDD18)
CAP_LDO
GPIOJ[0](RBIAS)
32 USB_SIDE_EN#
GPIOE[0]/RXD
GPIOE[1]/TXD
GPIOE[2]/RTS#
GPIOE[3]/DSR#
GPIOE[4]/CTS#
GPIOE[5]/DTR#
GPIOE[6]/RI#
GPIOE[7]/DCD#
2
0_0603_5%~D
DCD0#
1
2
3
4
5
84
83
6
2 @
1
1
37
RI0#
RXD0
TXD0
RTS0#
DSR0#
CTS0#
DTR0#
RI0#
DCD0#
RXD0
TXD0
RTS0#
DSR0#
CTS0#
DTR0#
USB
2 @
37
37
37
37
37
37
37
BC_INT#
BC_DAT
BC_CLK
2 @
9
10
13
12
15
16
19
18
21
22
C92
4.7U_0603_6.3V4Z~D
R250
10K_0402_5%~D
BC_INT#
BC_DAT
BC_CLK
GPIOH[0]
GPIOH[1]
GPIOH[4]
GPIOH[5]
BC_INT#
BC_DAT
BC_CLK
119
@ C97
4.7U_0603_6.3V4Z~D
39
39
24
25
26
27
58
59
60
GPIOI[1](VCC1)
GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)
GPIOJ[5](USBDN1)
GPIOK[0](USBDP2)
GPIOK[1](USBDN2)
GPIOK[3](USBDP3)
GPIOK[2](USBDN3)
GPIOK[5](USBDP4)
GPIOK[6](USBDN4)
39
+3.3V_SUS
ECE5028-NU
(ECE5018)
SIO_VDDA
8
14
20
R227
12K_0402_1%~D
+3.3V_ALW
C98
0.1U_0402_16V4Z~D
R814
VCC1(VDDA33)
GPIOJ[7](VDDA33)
GPIOK[4](VDDA33)
WIRELESS_ON/OFF#
BT_RADIO_DIS#
43 WIRELESS_ON/OFF#
40 BT_RADIO_DIS#
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
C401
0.1U_0402_16V4Z~D
SYS_PME#
PCIE_WAKE#
USB_BACK_EN#
97
98
99
100
101
102
103
104
C421
4.7U_0603_6.3V4Z~D
1
2
R246
10_0402_5%~D
@
C415
4.7P_0402_50V8C~D
@
PBAT_PRES#
SBAT_PRES#
CHG_PBATT
CHG_SBATT
44 PBAT_PRES#
44,50 SBAT_PRES#
50 CHG_PBATT
50 CHG_SBATT
50 PBAT_DSCHG
30,35 SYS_PME#
28,34 PCIE_WAKE#
32 USB_BACK_EN#
VCC1
VCC1
VCC1
VCC1

CLK_SIO_14M
Title
ECE5028
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
38
of
66
+RTC_CELL
1
+3.3V_ALW
+RTC_CELL
+3.3V_ALW
R211
100K_0402_5%~D
VCC0
1
@
2
23 SIO_PWRBTN#
43 SNIFFER_YELLOW#
1
38
38
102
105
107
EC_FLASH_SPI_CLK
EC_FLASH_SPI_DIN
EC_FLASH_SPI_DO
103
106
108
FLCLK
FLDATAIN
FLDATAOUT
SIO_PWRBTN#
SNIFFER_YELLOW#
109
110
GPIO80
GPIO81
87
86
85
BC_CLK
BC_DAT
BC_INT#
BC_CLK
BC_DAT
BC_INT#
BC_CLK
BC_DAT
38 BC_INT#
MEC5004_XTAL1
MEC5004_XTAL2
2
1
R214
0_0402_5%~D
MEC5004_XOSEL
122
124
123
OUT2/PWM3
OUT9/PWM2
OUT11/PWM1
OUT10/PWM0
48
47
46
45
nEC_SCI/SPDIN2
SGPIO45/MSDATA/SPDOUT2
SGPIO44/MSCLK/SPCLK2
SGPIO46/SPDIN1
SGPIO47/SPDOUT1
SGPIO31/TIN1/SPCLK1
66
55
54
69
68
67
SIO_EXT_SCI#
PS_ID
S IO_RCIN#
BEEP
1.25V_GFX_PCIE_ON
DEBUG_ENABLE#
SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX
70
71
HOST_DEBUG_TX
HOST_DEBUG_RX
SGPIO40
SGPIO41
SGPIO42
SGPIO43
91
90
89
4
NUM_LED#
SIO_SPI_CS#
1
2
3
LOM_SMB_ALERT#
SFPI_EN
DOCK_SMB_ALERT#
52
0.9V_DDR_VTT_ON
11
115
114
SIO_EXT_SMI#
BAT2_LED#
BAT1_LED#
nFWP
84
FW P#
GPIOA3/WINDMON
73
GPIO83/32KHZ_OUT
117
SGPIO35
SGPIO36 (SFPI_EN)
SGPIO37
OUT7/nSMI
nPWR_LED
nBAT_LED
XOSEL
AGND
1 125
L24
MEC5004_XTAL1
2
Y1
32.768K_12.5P_1TJS125DJ4A420P~D
MEC5004_XTAL2
4
1
PBAT_SMBDAT
PBAT_SMBCLK
SBAT_SMBDAT
SBAT_SMBCLK
1.5V_RUN_ON
1.25V_RUN_ON
THRM_SMBDAT
THRM_SMBCLK
1
R176
BREATH_LED
IMVP_VR_ON 48
WLAN_3V_ENABLE 34
3.3V_SUS_ON 41
BREATH_LED 43
HOST_DEBUG_TX 34
HOST_DEBUG_RX 34
+3.3V_LAN
@ C146
0.1U_0402_16V4Z~D
1
2
23 ICH_SPI_CS0#
IN1
IN2
43
43
43
Pin15 of 5025
3.3V_M_PWRGD
49
RUNPW ROK
RESET_OUT#
TEST_PIN
72
EC_FLASH_PAD
@SHORT PADS~D
DOCK_SMB_ALERT# 36
0.9V_DDR_VTT_ON 46
SIO_EXT_SMI# 23
BAT2_LED#
43
BAT1_LED#
43
R76
Bat2 = Amber LED

Bat1 = Green LED
RUNPWROK
38,42,48,54
RESET_OUT#
42
SFPI_EN 2
MEC5025-NU_VTQFP128~D
Place R84 within 500 mils from SPI flash.

Place R32 & R33 within 500 mils of the
MEC5025.
Pin24 of 5025
NC
SIO_SLP_M#
Pin25 of 5025
NC
1.05V_1.25V_M_PWRGD
Pin37 of 5025
NC
R238
Pin24 of 5025
NC
LOM_SUPER_IDDQ
NC
Refer to UMA
LOM_LOW_PWR
NC
Refer to UMA
LOM_CABLE_DETECT
NC
Refer to UMA
1=Flash Recovery Enabled

0=Flash Recovery Disabled
T39 PAD~D
Populate
for flash
corruption
issue.
+3.3V_SUS
1
2
+3.3V_ALW
L6
C398
1
2
L3
R219
10K_0402_5%~D
2
SPI_CS0#
EC_FLASH_SPI_DIN
2
R84
15_0402_5%~D
R92
100K_0402_5%~D
FW P#
M_ON
1K_0402_5%~D
MEC_TEST_PIN
NC
NC
R80
1K_0402_5%~D
Non-AMT Broacom
Pin23 of 5025
+3.3V_ALW
Layout Note:
53
0.1U_0402_16V4Z~D
CH_RSMRST#
2
4.7K_0402_5%~D
2
R397
0_0402_5%~D
LOM_SMB_ALERT# 23,28
AMT Intel
1
R730
R218
10K_0402_5%~D
U23
1
2
3
4
CS#
SO
WP#
GND
VCC
HOLD#
SCLK
SI
8
7
6
5
M25P16-VMW6TP_SO8~D
R84 place close to

Flash ROM
low=write protected
0.1U_0402_16V4Z~D
R398
15_0402_5%~D
1
2EC_FLASH_SPI_CLK
1
2EC_FLASH_SPI_DO
R399
15_0402_5%~D
R398, R399, place

close to M5025
Flash ROM
200 MIL SO8
@ R93
100K_0402_5%~D
2
Net & Part
LOM_SMB_ALERT#
@ R396
15_0402_5%~D
SPI_CS0#
1
2
@ U30
CAP_LED#
SCRL_LED#
NUM_LED#
1
10K_0402_5%~D
2
8.2K_0402_5%~D
2
8.2K_0402_5%~D
2
4.7K_0402_5%~D
2
4.7K_0402_5%~D
2
2.2K_0402_5%~D
2
2.2K_0402_5%~D
2
2.2K_0402_5%~D
2
2.2K_0402_5%~D
2
1M_0402_5%~D
+3.3V_ALW
SIO_EXT_SCI# 23
PS_ID
44
SIO_RCIN# 22
BEEP
26
1.25V_GFX_PCIE_ON 54
20mA drive pins
PWRGD
+3.3V_ALW
DOCK_SMB_ALERT#
2
R794
LCD_SMBCLK
1
R161
LCD_SMBDAT
1
R162
THRM_SMBDAT
1
R64
THRM_SMBCLK
1
R65
SBAT_SMBDAT
1
R75
SBAT_SMBCLK
1
R81
PBAT_SMBDAT
1
R62
PBAT_SMBCLK
1
R63
HOST_DEBUG_RX
1
R400
SIO_SPI_CS#
nRESET_OUT/OUT6
C80
1
LCD_SMBCLK 19
LCD_SMBDAT 19
DOCK_SMB_CLK 36
DOCK_SMB_DAT 36
1.8V_RUN_ON 41
LCD_VCC_TEST_EN 19
T87 PAD~D
T88 PAD~D
PBAT_SMBDAT 44
PBAT_SMBCLK 44
SBAT_SMBDAT 44
SBAT_SMBCLK 44
1.5V_RUN_ON 47
1.25V_RUN_ON 51
THRM_SMBDAT 18,49
THRM_SMBCLK 18,49
FAN1_TACH 18
2
0_0402_5%~D
2
R66
ACAV_IN
18,49,50
T37 PAD~D
IMVP_PWRGD 23,42,48
FAN1_TACH
C385
22P_0402_50V8J~D
C379
33P_0402_50V8J~D
1
8.2K_0402_5%~D
1
8.2K_0402_5%~D
R67
DOCK_SMB_CLK
+3.3V_ALW
1
IMVP_PWRGD
XTAL1
XTAL2
Sam e as Laguna
43
42
41
GPIO96/TOUT1
R213
10K_0402_5%~D
32 KHz Clock
GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1
HSTCLK
HSTDATAIN
HSTDATAOUT
LRESET#
PCICLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
SER_IRQ
ICH_EC_SPI_CLK
ICH_EC_SPI_DIN
ICH_EC_SPI_DO
DOCK_SMB_DAT
+RTC_CELL
57
58
59
60
61
62
63
64
56
1
100K_0402_5%~D
PLTRST2#
CLK_PCI_5025
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
IRQ_SERIRQ
R83
10_0402_5%~D
C81
4.7P_0402_50V8C~D
GPIO94/IMCLK
GPIO95/IMDAT
KCLK
KDAT
GPIOA6/EMCLK
GPIOA7/EMDAT
GPIO20/PS2CLK/8051RX
GPIO21/PS2DAT/8051TX
PLTRST2#
CLK_PCI_5025
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLK RUN#
IRQ_SERIRQ
23 ICH_EC_SPI_CLK
23 ICH_EC_SPI_DIN
23 ICH_EC_SPI_DO
CLK_PCI_5025
SGPIO34/A20M
OUT5/KBRST
75
76
77
78
79
80
81
82
92
50
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
8051_RX
8051_TX
POWER_SW_IN1#
R69
21,38
6
22,28,38
22,28,38
22,28,38
22,28,38
22,28,38
23,30,38
23,28,30,38
R1752 no stuff when doing

flash recovery
SIO_A20GATE
SNIFFER_GREEN#
POWER_SW# 18,40
DEBUG_ENABLE#
2
0_0402_5%~D
40
CLK_TP_SIO
40
DAT_TP_SIO
36 CLK_KBD
36
DAT_KBD
36 CLK_DOCK
36
DAT_DOCK
34 8051_RX
34 8051_TX
R210
10K_0402_5%~D
2 POWER_SW#
8051_RX
8051_TX
1
R101
KSI7/GPIO19
KSI6/GPIO17
KSI5/GPIO10
KSI4/GPIO9
KSI3/GPIO8
KSI2/GPIO7/BC_A_INT#
KSI1/GPIO6/BC_A_DAT
KSI0/SGPIO30/BC_A_CLK
1
1
ALWON
45
SNIFFER_PWR_SW# 43
5
4
3
2
1
33
34
35
36
37
38
39
40
Molex_53261
@ JDEBUG
5
4
3
2
1
22 SIO_A20GATE
43 SNIFFER_GREEN#
2
1
R90
10K_0402_5%~D
2
1
R100
10K_0402_5%~D
2
1
R395
1M_0402_5%~D
+3.3V_ALW
AUX_ON
SUS_ON
RUN_ON
A C_OFF
1.05V_1.25V_M_PWRGD
BC_A_INT#
BC_A_DAT
BC_A_CLK
POWER_SW_IN#
C369
0.1U_0402_16V4Z~D
41 AUX_ON
41,42 SUS_ON
19,37,41,42,51 RUN_ON
44 AC_OFF
PAD~D T35
37 BC_A_INT#
37 BC_A_DAT
37 BC_A_CLK
VCC_PLL
DAT_DOCK
2
4.7K_0402_5%~D
8
7
6
5
93
94
95
96
111
112
9
10
97
98
99
100
104
1
R85
AB1B_CLK/GPIOA4
AB1B_DATA/GPIOA2
AB1A_CLK
AB1A_DATA
GPIO11/AB2_DATA
GPIO12/AB2_CLK
GPIO13/AB1G_DATA
GPIO14/AB1G_CLK
GPIO87/AB1C_DATA
GPIO86/AB1C_CLK
GPIO85/AB1D_DATA
GPIO84/AB1D_CLK
GPIO93/AB1F_DATA
GPIO92/AB1F_CLK
GPIO91/AB1E_DATA
GPIO90/AB1E_CLK
LCD_SMBCLK
LCD_SMBDAT
DOCK_SMB_CLK
DOCK_SMB_DAT
1.8V_RUN_ON
LCD_VCC_TEST_EN
VSS_PLL
CLK_DOCK
2
4.7K_0402_5%~D
1
C82
0.1U_0402_16V4Z~D
+5V_ALW
A LWON
S NIFFER_PWR_SW#
POWER_SW_IN1#
POWER_SW_IN#
ACAV_IN
SNIFFER_RTC_GPO
101
DAT_KBD
2
4.7K_0402_5%~D
1
R86
23 ICH_RSMRST#
PAD~D T33
PAD~D T34
46 DDR_ON
40 TP_DET#
45,46 ALW_PWRGD_3V_5V
23 SIO_SLP_S3#
23 SIO_SLP_S5#
41 3.3V_RUN_ON
120
119
126
127
128
118
ALWON
POWER_ SW_IN2#/GPIO23
POWER_ SW_IN1#/GPIO22
POWER_ SW_IN0#
ACAV_IN
BGPO0/GPIOA5
VR_CAP
1
R87
ICH_RSMRST#
M_ON
SIO_SLP_M#
DDR_ON
TP_DET#
ALW_PWRGD_3V_5V
SIO_SLP_S3#
SIO_SLP_S5#
3.3V_RUN_ON
I CH_CL_PWROK
10,23 ICH_CL_PWROK
CLK_KBD
2
4.7K_0402_5%~D
1
R88
KSO17/GPIOA1/AB1H_DATA
KSO16/GPIOA0/AB1H_CLK
GPIO5/KSO15
GPIO4/KSO14
KSO13/GPIO18
KSO12/OUT8
KSO11/GPIOC7
KSO10/GPIOC6
KSO9/GPIOC5
KSO8/GPIOC4
KSO7/GPIO3
KSO6/GPIO2
KSO5/GPIO1
KSO4/GPIO0
KSO3/GPIOC3
KSO2/GPIOC2
KSO1/GPIOC1
KSO0/GPIOC0
VSS
VSS
VSS
VSS
VSS
+5V_RUN
12
13
14
15
16
17
18
19
20
23
24
25
27
28
29
30
31
32
26
51
74
88
113
PAD~D T36
46 1.8V_SUS_PWRGD
7 EC_CPU_PROCHOT#
C74
4.7U_0603_6.3V4Z~D
CKG_SMBDAT
CKG_SMBCLK
ATI_ Intel_IDENTIFY
3.3V_M_PWRGD
1.8V_SUS_PWRGD
EC_CPU_PROCHOT#
6 CKG_SMBDAT
6 CKG_SMBCLK
1
C76
10U_0805_10V4Z~D
ATI_ Intel_IDENTIFY
2
1
R795
0_0402_5%~D
1
C79
0.1U_0402_16V4Z~D
U22
1
C83
0.1U_0402_16V4Z~D
R222
0_0402_5%~D
2
1
1
C75
0.1U_0402_16V4Z~D
C368
1U_0603_10V4Z~D
21
44
65
83
116
R70
0_0402_5%~D
VCC1
VCC1
VCC1
VCC1
VCC1
22
SNIFFER_GREEN#
2
100K_0402_5%~D
SNIFFER_YELLOW#
2
100K_0402_5%~D
CKG_SMBDAT
2
2.2K_0402_5%~D
CKG_SMBCLK
2
2.2K_0402_5%~D
BC_DAT
2
100K_0402_5%~D
1
@ R77
1
@ R104
1
R105
1
R111
1
R401
SUS_ON
1
2.7K_0402_5%~D
M_ON
1
1M_0402_5%~D
RUN_ON
1
2.7K_0402_5%~D
DDR_ON
2
100K_0402_5%~D
AUX_ON
2
2.7K_0402_5%~D
A C_OFF
2
2.7K_0402_5%~D
121
2
R387
2
R388
2
R389
1
R526
1
R788
1
@ R789
Flash write protect bottom 4K

of internal bootblock flash
Title
EMC5025
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
39
of
66
Touch PAD
+3.3V_RUN
JTPAD
+5V_RUN
USBP5-
Part Number
SP_GND
SP_X
SP_V+
SP_Y
PCMCIA BODY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
@ D40
DA204U_SOT323~D
@ D39
DA204U_SOT323~D
Description
DC02000CS0L
H-CONN SET ZGX

MB-MDC
100P_0402_50V8J~D
35
36
37
38
39
40
35
36
37
38
39
40
GND
GND
41
42
1
2
4.7K_0402_5%~D
R229
Part Number
Description
DC020003Y0L
H-CONN SET ZJX MB-LCD

14 WXGA+(-1ch)
LVDS cable
CLK_TP_SIO
H-CONN SET ZJX

MB-B/T-TP-FP
LVDS cable
DAT_TP_SIO
Description
DC02000840L
Part Number
Description
DAT_TP_SIO 39
DC02000870L
CLK_TP_SIO 39
H-CONN SET ZJX

MB-LCD 14 WXGA+(-2ch)
RTC BATT
Part Number
Description
BATT CR2032 3V
220MAH MAXELL
GC20323MX00
SP_GND
SP_X
SP_V+
SP_Y
Power Switch
FOX_GS12403-0001K-8F~D
POWER_SW#
C78
100P_0402_50V8J~D
100P_0402_50V8J~D
C388
100P_0402_50V8J~D
100P_0402_50V8J~D
@
C375
C377
C391
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
@
C396
C373
C374
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
@
C376
C378
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
@
C389
C372
C371
100P_0402_50V8J~D
100P_0402_50V8J~D
C380
C393
100P_0402_50V8J~D
100P_0402_50V8J~D
@
C397
C386
100P_0402_50V8J~D
100P_0402_50V8J~D
@
C390
C384
C394
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
@
C383
C395
100P_0402_50V8J~D
C381
100P_0402_50V8J~D
@
C392
100P_0402_50V8J~D
2
C382
C387
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
L26
1
10P_0402_50V8J~D
C87
KYBD_DET#
37 KYBD_DET#
10P_0402_50V8J~D
C86
1
JKYBRD
+3.3V_ALW
Part Number
C399
10P_0402_50V8J~D
L25
1
2
TP_DATA
C400
10P_0402_50V8J~D
2
R407
0_0402_5%~D
1
2
R410
0_0402_5%~D
1
2
KSO10
KSO11
KSO9
KSO14
KSO13
KSO15
KSO16
KSO12
KSO0
KSO2
KSO1
KSO3
KSO8
KSO6
KSO7
KSO4
KSO5
KSI0
KSI3
KSI1
KSI5
KSI2
KSI4
KSI6
KSI7
POWER_SW#
R_NUM_LED#
R_CAP_LED#
R_SCRL_LED#
KSO17
MDC wire set cable
+5V_RUN
R575
100K_0402_5%~D
PCMCIA TYCO
1759096-1
T/P wire set cable
USBP5_D+
TP_CLK
POWER_SW#
R_NUM_LED#
R_CAP_LED#
R_SCRL_LED#
Description
DC000001Q0L
USBP5_D-
+3.3V_ALW
18,39
43
43
43
Part Number
4.7K_0402_5%~D
R228
USBP5+
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
Description
SP070007V0L S SOCKET TYCO 1770551-1

10P H5.9 SMART
Part Number
23
SM CARD BODY
2
23
@ L4
4 4
3 3
Description
SPK PACK ZJX 2.0W 4 OHM FG
PK230003Q0L
+3.3V_RUN
Part Number
C102
0.1U_0402_16V4Z~D
Speak
@ D38
DA204U_SOT323~D
FOX_HT1315F-P2~D
C103
100P_0402_50V8J~D
1
2
Description
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
DC28A000800
TP_CLK
TP_DATA
Part Number
34,43
SP_GND
SP_X
SP_Y
SP_V+
FAN
BT_RADIO_DIS# 38
PAD~D
T4
BT_ACTIVE
@ D37
DA204U_SOT323~D
KSI[0..7]
+3.3V_ALW
1
C423
0.1U_0402_16V4Z~D
LID_CL#
C424
0.1U_0402_16V4Z~D
38
TP_DET#
BT_RADIO_DIS#
COEX3
R119
10K_0402_5%~D
39
C426
0.1U_0402_16V4Z~D
USBP5_DUSBP5_D+
+3.3V_RUN
KSO[0..17]
KSO17
KSO16
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
37
C419
33P_0402_50V8J~D
R249
10K_0402_5%~D
2
1
34 COEX2_WLAN_ACTIVE
37
USBP7USBP7+
USBP7USBP7+
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
G2
C430
0.1U_0402_16V4Z~D
23
23
COEX2_WLAN_ACTIVE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
G1
C210
0.047U_0402_16V4Z~D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
34 COEX1_BT_ACTIVE
@
@ C367
100P_0402_50V8J~D
PWR_SW
@SHORT PADS~D
Title
INT KB
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
40
of
66
+5VSUS Source
1
1
2
4
1
3
2 @
Q88
2N7002W-7-F_SOT323-3~D
S
Q87
2N7002W-7-F_SOT323-3~D
2
G
39 3.3V_SUS_ON
2
G
Q65
2N7002W-7-F_SOT323-3~D
3
2
G
39 1.8V_RUN_ON
2
G
S
R305
0_0402_5%~D
Q60
2N7002W-7-F_SOT323-3~D
2
1
Q90
2N7002W-7-F_SOT323-3~D
2
G
3
39 3.3V_RUN_ON
2
G
C144
470P_0402_50V7K~D
@
@ R113
1K_0402_5%~D
R729
1K_0402_5%~D
2
G
2
G
Q30
2N7002W-7-F_SOT323-3~D
@
D
+1.25V_RUN
Q81
2N7002W-7-F_SOT323-3~D
2
G
1
2
1
1
2
2
G
+1.8V_RUN
@
D
R636
1K_0402_5%~D
Q64
2N7002W-7-F_SOT323-3~D
@
D
+0.9V_DDR_VTT
1
2
2
G
R635
1K_0402_5%~D
Q63
2N7002W-7-F_SOT323-3~D
+1.5V_RUN
2
G
@
D
R634
1K_0402_5%~D
Q62
2N7002W-7-F_SOT323-3~D
1
2
1
+3.3V_RUN
R633
1K_0402_5%~D
Q61
2N7002W-7-F_SOT323-3~D
1
1
2
S
RUN_ON_5V#
R117
1K_0402_5%~D
Q93
2N7002W-7-F_SOT323-3~D
1
1
2
S
+5V_RUN
@
D
2
G
3
2
G
3
R118
1K_0402_5%~D
Q92
2N7002W-7-F_SOT323-3~D
R151
75_0603_5%~D
Q91
2N7002W-7-F_SOT323-3~D
1
2
1
3
SUS_ON_3.3V# 2
G
+3.3V_SUS
@
D
Discharg Circuit
+5V_SUS
Discharg Circuit
+1.8V_SUS
1
2
R413
0_0402_5%~D
Q89
2N7002W-7-F_SOT323-3~D
R630
20K_0402_5%~D
@ D36
RB751V_SOD323~D
1
2
R766
100K_0402_5%~D
+3.3V_RUN
1
R641
100K_0402_5%~D
Q58
SI4336DY-T1-E3_SO8~D
1
2
3
C819
10U_0805_10V4Z~D
1
2
+3.3V_ALW2
R700
470K_0402_5%~D
C208
4700P_0402_25V7K~D
1
3
R701
200K_0402_5%~D
2
1
Q72
2N7002W-7-F_SOT323-3~D
8
7
6
5
1
2
1
2
G
Q73
2N7002W-7-F_SOT323-3~D
AUX_ON
39
+3.3V_RUN Source
+15V_ALW
ENAB_3VLAN 28
D
C194
0.047U_0402_16V4Z~D
R698
100K_0402_5%~D
2
G
@ Q10
8
1
7
2
6
3
5
+PWR_SRC
N21917830
+3.3V_ALW
R699
100K_0402_5%~D
R628
20K_0402_5%~D
2
1
2
2
@ D35
RB751V_SOD323~D
1
2
1
R637
100K_0402_5%~D
+1.8V_RUN
Q54
8
1
7
2
6
3
5
C816
10U_0805_10V4Z~D
+3.3V_ALW2
R632
100K_0402_5%~D
R625
20K_0402_5%~D
+1.8V_RUN Source
+1.8V_SUS
+15V_ALW
C815
4700P_0402_25V7K~D
2
1
1
2
1
3
2
G
1
2
3
C814
10U_0805_10V4Z~D
8
7
6
5
RUN_ENABLE
2
G
Q53
S
2N7002W-7-F_SOT323-3~D
+PWR_SRC
+5VRUN Source
RUN_ON_5V#
S Q55
2N7002W-7-F_SOT323-3~D
C195
4700P_0402_25V7K~D
@
+5V_ALWQ52
SI4810BDY-T1-E3_SO8~D
R624
100K_0402_5%~D
+3.3V_SUS
1
2
3
+5V_RUN
R623
100K_0402_5%~D
19,37,39,42,51 RUN_ON
R765
100K_0402_5%~D
SUS_ON_3.3V#
+15V_ALW
8
7
6
5
Q51
2N7002W-7-F_SOT323-3~D
S
R762
20K_0402_5%~D
+3.3V_ALW2
+3.3V_ALW Q47
R764
100K_0402_5%~D
SUS_ON 2
G
+3VSUS Source
+3.3V_ALW2
C142
4700P_0402_25V7K~D
SUS_ON_5V# 2
G
3
1
SUS_ON
39,42
SUS_ENABLE
Q49
2N7002W-7-F_SOT323-3~D
R621
100K_0402_5%~D
C143
10U_0805_10V4Z~D
R617
100K_0402_5%~D
+15V_ALW
+5V_SUS
6
5
2
1
+3.3V_ALW2
Q80
+5V_ALW
+15V_ALW
R620
20K_0402_5%~D
DC/DC Interface
C811
10U_0805_10V4Z~D
Title
POWER CONTROL
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
41
of
66
+3.3V_ALW
2
R207
1
0_0402_5%~D
47 1.05V_RUN_PWRGD
2
R208
1
0_0402_5%~D
51 GFX_CORE_PWRGD
2
R185
1
0_0402_5%~D
+3.3V_ALW
C135
0.1U_0402_16V4Z~D
1
2
1
R132
20K_0402_5%~D
U12A
6
74LVC3G14DC_VSSOP8~D
IN1
OUT
C458
0.1U_0402_16V4Z~D
2
U27A
3
IN2
+3.3V_ALW
14
2
2
R418
0_0402_5%~D
19,37,39,41,51 RUN_ON
14
+3.3V_ALW
3
1
Q84
MMST3904-7-F_SOT323-3~D
12
C19
2200P_0402_50V7K~D
P
OUT
C
Q85
MMST3904-7-F_SOT323-3~D
39,41
RUNPWROK
RUNPWROK 38,39,48,54
SUS_ON
11
IN2
R134
4.7K_0402_5%~D
1
2
2
B
U27D
IN1
13
5V_3V_1.8V_1.25V_RUN_PWRGD 38
Q78
MMBT3906WT1G_SC70-3~D
1
1
2
R364
10K_0402_5%~D
1
2
C134
0.01U_0402_16V7K~D
R616
200K_0402_5%~D
C47
0.1U_0402_16V4Z~D
+1.8V_SUS
C17
2200P_0402_50V7K~D
RB751V_SOD323~D
2
R133
4.7K_0402_5%~D
1
2
2
B
R68
200K_0402_5%~D
D26
1
+1.8V_RUN
2
C46
0.1U_0402_16V4Z~D
RB751V_SOD323~D
Q77
U12B
3VRUNRC
R334
10K_0402_5%~D
1
2
D25
+5V_RUN
+3.3V_ALW
+5V_ALW
+3.3V_SUS
U12C
47 1.5V_RUN_PWRGD
1
0_0402_5%~D
2
@ R216
18 2.5V_RUN_PWRGD
2
0_0402_5%~D
1
R486
51 1.25V_RUN_PWRGD
+3.3V_ALW
+3.3V_ALW
14
10
IN1
OUT
C
Q86
MMST3904-7-F_SOT323-3~D
SUSPWROK 18
9 IN2
U27C
R164
4.7K_0402_5%~D
1
2
2
B
+3.3V_SUS
1
C27
2200P_0402_50V7K~D
1
2
R82
200K_0402_5%~D
C49
0.1U_0402_16V4Z~D
Q79
RB751V_SOD323~D
2
C
R367
10K_0402_5%~D
1
2
D27
+3.3V_RUN
R79
100K_0402_5%~D
2
+3.3V_ALW
RESET_OUT#
IN2
U27B
1
IN1
OUT
ICH_PWRGD
39 RESET_OUT#
IMVP_PWRGD
ICH_PWRGD# 18
Q17
2N7002W-7-F_SOT323-3~D
2
G
23,39,48 IMVP_PWRGD
14
ICH_PWRGD#
D
ICH_PWRGD 10,23
+3.3V_ALW
3
2
8
6
U48B
Y
3.3V_5V_SUS_PWRGD
D32
RB751V_SOD323~D
Q20
R135
200K_0402_5%~D
C422
2200P_0402_50V7K~D
1
2
R139
200K_0402_5%~D
C457
0.1U_0402_16V4Z~D
C186
0.1U_0402_16V4Z~D
1
2
R159
10K_0402_5%~D
1
2
2
D23
RB751V_SOD323~D
2
1
+3.3V_ALW
+3.3V_SUS
+5V_ALW
1
R136
200K_0402_5%~D
A
1
1
2
Q26
D33
RB751V_SOD323~D
2
1
R157
200K_0402_5%~D
C404
2200P_0402_50V7K~D
1
2
A
R158
200K_0402_5%~D
C199
0.1U_0402_16V4Z~D
R160
10K_0402_5%~D
1
2
2
D31
RB751V_SOD323~D
2
1
+5V_SUS
Title
Power Good
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
42
of
66
Fiducial Mark
EMI CLIP
FD1
H11
H12
H15
H16
H17
H13
H14
H18
@H_C315B236D118 @H_C315D118 @H_C315D118 @H_C291B236D118 @H_C295D118 @H_C217B276D98@H_C217B276D98@H_C217D91
GND
FD22
GND
CLIP1
EMI_CLIP
H20
@H_C217B276D98
H26
H27
H28
H29
H30
@H_C472D376 @H_C472D431X376 @H_O115X31D115X31N @H_O115X31D115X31N @H_O115X31D115X31N
GND
FD17
GND
39
CAP_LED#
R226
330_0402_5%~D
2
1
39
NUM_LED#
+3.3V_RUN
R181
100K_0402_5%~D
@
R140
@ 0_0402_5%~D
1
2
SCRL_LED#
R225
330_0402_5%~D
2
1
39
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FD7
1
R_CAP_LED# 40
FIDUCIAL MARK~D
R_NUM_LED#
R_NUM_LED# 40
R_SCRL_LED#
R_SCRL_LED# 40
FD8
R_CAP_LED#
R224
330_0402_5%~D
1
+3.3V_RUN
R78
10K_0402_5%~D
FD6
FIDUCIAL MARK~D FIDUCIAL MARK~D
FIDUCIAL MARK~D
+3.3V_RUN
This circuit is
only needed if the
platform has the
SNIFFER.
FIDUCIAL MARK~D
FD4
FD16
FD3
1
FIDUCIAL MARK~D
1
FIDUCIAL MARK~D
FD19
FD18
1
FIDUCIAL MARK~D
FD20
FIDUCIAL MARK~D
FD21
FD24
FIDUCIAL MARK~D
CLIP2
EMI_CLIP
1
FIDUCIAL MARK~D
FD15
FIDUCIAL MARK~D
FD9
FD25
FIDUCIAL MARK~D
FD23
FD14
FIDUCIAL MARK~D
CLIP3
EMI_CLIP
FD12
FIDUCIAL MARK~D
FD11
CLIP6
EMI_CLIP
FD10
FIDUCIAL MARK~D
FD13
GND
H19
@H_C217D91
FD5
FIDUCIAL MARK~D
CLIP4
EMI_CLIP
H10
@H_C236B315D110
FD2
H5
H6
H7
H3
H4
H8
H9
@H_C315D110 H_C256B63D47 @H_C236B315D110 @H_C236B256D110 @H_C236B315D110 @H_C217B276D98 @H_C236B315D110
H2
H_C146B217D91
H1
H_C146B217D91
Q22
PDTA114EU_SC70-3~D
SATA_ACT#
Q23
1
2
R179
0_0402_5%~D
+5V_RUN
+3.3V_ALW
R97
10K_0402_5%~D
@
HDD_LED
Q28
PDTA114EU_SC70-3~D
32
2
R145
330_0402_5%~D
1
2
22 SATA_ACT#_R
38
LED_MASK#
BT_ACTIVE
R74
10K_0402_5%~D
1
2
2
G
S
1
Q29
R212
1K_0402_5%~D
R_BT_ACT
2
R_BT_ACT
32
34,40 BT_ACTIVE
R_PIDEACT 36
E
B
Q18
38 LED_MASK#
COIN RTC Battery
+COINCELL
R21
1K_0402_5%~D
5
P
MOLEX_53398-0271~D
R71
100_0402_5%~D
1
2
BREATH_GREEN_LED 32
NC7SZ04P5X_NL_SC70-5~D
34 LED_WLAN_OUT#
2
R639
10K_0402_5%~D
Q5
+3.3V_ALW
C370
1U_0603_10V4Z~D
R638
47K_0402_5%~D
U43
Y
D13
BAT54CW_SOT323~D
1
A
3
+3.3V_RUN
+RTC_CELL
39 BREATH_LED
+3.3V_WLAN
NC
Z4012
JCOIN
C OINCELL 1
1
2 2
+COINCELL
+3.3V_SUS
+3.3V_RTC_LDO
Q1
PDTA114EU_SC70-3~D
R15
1
+3.3V_SUS
R_MPCI_ACT 32
39
BAT1_LED#
BAT1_LED#
BATT_GREEN_LED
2
220_0402_5%~D
BATT_GREEN_LED 32
JSNIFF
+3.3V_ALW
3
4
Q4
PDTA114EU_SC70-3~D
39
BAT2_LED#
BAT2_LED#
39 SNIFFER_PWR_SW#
38 WIRELESS_ON/OFF#
R6
1
R102
100K_0402_5%~D
+3.3V_RUN
R180
100K_0402_5%~D
2
1
+RTC_CELL
Q32
PDTA114EU_SC70-3~D
39 SNIFFER_YELLOW#
R_MPCI_ACT
2
150_0402_5%~D
1BS008-13130-7F_4P~D
R9
1
BATT_AMBER_LED
2
220_0402_5%~D
BATT_AMBER_LED 32
+3.3V_SUS
Q33
PDTA114EU_SC70-3~D
39 SNIFFER_GREEN#
1
R261
1
R262
SNIFFE R_Y
2
220_0402_5%~D
SNIFFER_G
2
220_0402_5%~D
D14
3 Y
1
2
G
12-22AUYSYGC/530-A2/TR8_G/Y~D

Title
PAD and Standoff

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
43
of
66
+3.3V_ALW
PL32
FBMA-L18-453215-900LMA90T_1812~D
1
2
+3.3V_ALW
D
PD43
PD44
PD45
@ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D
1
PD42
@ DA204U_SOT323~D
Secondary Battery Connector
PJP60
10
11
1
2
3
4
5
6
7
8
9
BATT1+
BATT2+
SMB_CLK
SMB_DAT
BATT_PRES#
SYSPRES#
BATT_VOLT
GND
BATT1GND
BATT2-
PR301
100_0402_5%~D
1
2
Z4301
Z4302
Z4303
PR302
100_0402_5%~D
1
2
PR303
100_0402_5%~D
PR304
1
2
100_0402_5%~D
1
2
PC230
0.1U_0603_25V7K~D
2
1
PC231
2200P_0402_50V7K~D
2
1
PJP1
SBAT_SMBCLK 39
SBAT_SMBDAT 39
SBAT_ALARM#
SBATT+
PAD-OPEN 4x4m
PR300
10K_0402_5%~D
2
1
ESD Diodes
SBAT_PRES#
38,50
TYCO_1734077-1~D
+3.3V_ALW
PL6
FBMA-L18-453215-900LMA90T_1812~D
1
2
1
+3.3V_ALW
PD10
PD11
PD12
@ DA204U_SOT323~D
@ DA204U_SOT323~D @ DA204U_SOT323~D
1
PD9
@ DA204U_SOT323~D
Primary Battery Connector
PJP61
PC9
0.1U_0603_25V7K~D
2
1
PC10
2200P_0402_50V7K~D
2
1
PBATT1
BATT1+
BATT2+
SMB_CLK
SMB_DAT
BATT_PRES#
SYSPRES#
BATT_VOLT
GND
BATT1GND
BATT2-
10
11
1
2
3
4
5
6
7
8
9
PR20
100_0402_5%~D
1
2
Z4304
Z4305
Z4306
PR21
100_0402_5%~D
1
2
PR22
100_0402_5%~D
1
2
PBAT_SMBCLK 39
PBAT_SMBDAT 39
PR23
100_0402_5%~D
1
2
PBAT_ALARM#
PBATT+
PAD-OPEN 4x4m
PR19
10K_0402_1%~D
2
1
ESD Diodes
PBAT_PRES#
38
SUYIN_200277MR009G506ZR~D
+5V_ALW
PD59
VZ0603M260APT_0603
PL34
FBCA-K5B-302340-L1-T_1812~D
PR10
15K_0402_1%~D
1
2
39
PD41
DA204U_SOT323~D
PR7
10K_0402_1%~D
PQ2
MMST3904-7-F_SOT323~D
PR299
1
PSID_DISABLE# 38
@ 10K_0402_5%~D
39
5
AC_OFF
@ PQ100A
IMD2AT-108_SC74-6~D
THESE CAPS MUST BE

NEXT TO JCHG
Title
2
G
1
1
PC6
10U_1206_25V6M~D
PR12
4.7K_0805_5%
2
1
1
2
240K_0402_5%~D
PR11
@
2
PC5
0.1U_0603_25V7K~D
2
1
-D CIN_JACK
PC4
0.1U_0603_25V7K~D
2
1
@
PD53
SM24_SOT23
2
B
PC3
0.1U_0603_25V7K~D
2
1
DC-_2
PQ100B
IMD2AT-108_SC74-6~D
@
3
4
+DC_IN_SS
PS_ID
+5V_ALW
+5V_ALW
FDV301N_SOT23~D
PR13
47K_0402_1%~D
2
1
DC-_1
GND_1
MH1
MH2
GND_2
PC2
0.47U_0805_25V7k
1
2
+D C_IN
DC_IN+ Source
8
7
6
5
PR184
33_0402_5%~D
1
2
DC+_2
GND_3
+ DCIN_JACK
DC+_1
PR495
0_0402_5%~D
Low_PWR
GND_4
PD58
VZ0603M260APT_0603
PC397
0.1U_0603_25V7K~D
2
1
PL2
FBCA-K5B-302340-L1-T_1812~D
1
2
PJPDC1
TYCO_1566065-2~D
9
1
2
3
3
PQ1
PR6
100K_0402_1%~D
1
2
2
PQ3
FDS6679AZ_SO8~D
+DC_IN
Z-series AC Adaptor
Connctor
DOCK_PSID
3
36
PL1
2
1
GPIO Input from EC
PR2
2.2K_0402_5%~D
1
2
PR346
1
2
0_0402_5%~D
PD2
DA204U_SOT323~D
+3.3V_ALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
+DCIN
Size
Document Number
Date:
Rev
0.0
LA-3302P
Sheet
1
44
of
66
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP
+DC1_PWR_SRC
D
PJP33
1
+PWR_SRC
PC277
10U_1206_25V6M~D
PC276
10U_1206_25V6M~D
PC275
0.1U_0805_50V7K
2
1
PC274
2200P_0402_50V7K~D
2
1
5
D
3
2
1
3.0U_HMP1362-3R0-R_17A~D
5
6
7
8
GNDA_3V5V
PQ85
FDS6676AS_NL_SO8~D
+3.3V_ALW_LGATE
PC290
330U_D3L_6.3VM_R25~D
+5V_ALW_LGATE
+3.3V_ALWP
PR385
0_0402_5%~D
2
1
1
PR387
1_0603_5%~D
+3.3V_ALW_BOOT1
2
PL37
S
S
S
GNDA_3V5V
PR389
0_0402_5%~D
2
1
PC385
0.1U_0402_10V7K~D
2
1
EN_3V_5V
8
7
6
5
4
3
2
1
PAD
2 PR517 1 0_0402_5%~D
POK2
EN_3V_5V
+3.3V_ALW_UGATE
+3.3V_ALW_PHASE
GNDA_3V5V
PR386
1_0603_5%~D
1
2 +5V_ALW_BOOT
3.3 Volt +/-5%

Thermal Design Current:9.0A
Peak current: 12.9A
OCP min:15.79A
PQ83
BSC079N03S G_PG-TDSON-8~D
3
2
1
1
2
3
32
31
30
29
28
27
26
25
PR382
267K_0402_1%
1
2
PC288
0.1U_0603_25V7K~D
FDS6676AS_NL_SO8~D
33
PC287
0.1U_0603_25V7K~D
2
1
PQ84
@ PR501
1
0_0402_5%~D @
BYP
REFIN2
OUT1
ILIM2
FB1
OUT2
PU20
ILIM1 ISL6236IRZA_QFN32~D SKIP#
POK1
POK2
EN1
EN2
UGATE1
UGATE2
PHASE1
PHASE2
PR499
S
S
S
2
8
7
6
5
PR384
0_0402_5%~D
1
2
PR383
150K_0402_1%~D
1
2
POK1
EN_3V_5V
+5V_ALW_UGATE
+5V_ALW_PHASE
PR388
0_0402_5%~D
1
2
PC291
0.1U_0402_10V7K~D
2
1
PC289
330U_D3L_6.3VM_R25~D
GNDA_3V5V
9
10
11
12
13
14
15
16
0_0402_5%~D
+5V_ALWP
1
2
3
PL36
4.7U_HMU1356-4R7-R_10A~D
GNDA_3V5V
GNDA_3V5V
@ PR500
0_0402_5%~D
LDOREFIN
LDO
VIN
VREF3
EN_LDO
VCC
TON
REF
+5V_ALWP
PC286
0.1U_0603_25V7K~D
1
2
BOOT1
LGATE1
PVCC
SECFB
GND
PGND
LGATE2
BOOT2
PR380
0_0402_5%~D
1
2
17
18
19
20
21
22
23
24
8
7
6
5
D
D
D
D
PQ82
FDS8880_NL_SO8~D
PC386
0.1U_0402_10V7K~D
2
1
PC292
0.1U_0402_10V7K~D
2
1
PR379
@ 0_0402_5%~D
1
2
PC283
1U_0603_10V6K~D
2
1
PC282
4.7U_0805_6.3V6K
2
1
+3.3V_ALW2
@ PR376
10_0603_5%~D
2
1
PR375
0_0805_5%
1
2
GNDA_3V5V
5 Volt +/-5%
Peck current: 8.8A
OCP min: 10.52A
+5V_VCC1
2
PAD-OPEN1x1m
PC285
0.1U_0603_25V7K~D
2
1
PJP63
1
+5V_ALW2
PC284
0.1U_0603_25V7K~D
2
1
PR374
0_0805_5%
1
2
PC281
10U_1206_25V6M~D
PC280
10U_1206_25V6M~D
PC279
0.1U_0805_50V7K
2
1
PC278
2200P_0402_50V7K~D
2
1
PAD-OPEN 4x4m
1
+
2
@
GNDA_3V5V
PD55
S SCH DIO BAT54SW-7-F SOT323-3
PC295
0.1U_0603_25V7K~D
1 1
2
+3.3V_ALWP
PAD-OPEN1x1m
GNDA_3V5V
PD57
BAT54CW_SOT323~D
POK1
PAD-OPEN1x1m
PJP36
2
+5V_ALW
+15V_ALWP
PC296
0.1U_0603_25V7K~D
2
1
ALW_PWRGD_3V_5V 39,46
PR397
200K_0402_1%~D
2
1
PJP35
PR393
0_0402_5%~D
2
1
PR395
0_0402_5%~D
2
1
+15V_ALW
+5V_ALWP
PR398
39.2K_0402_1%~D
1
2
18 THERM_STP#
PD56
S SCH DIO BAT54SW-7-F SOT323-3
3
ALWON
POK2
PR392
2K_0402_5%~D
2
1
PR394
200K_0402_5%
1
2
39
+3.3V_ALWP
PR390
100K_0402_1%~D
1
2
GNDA_3V5V
PJP34
1
PR391
100K_0402_1%~D
1
2
PC293
0.1U_0603_25V7K~D
1 1
2
+5V_ALW2
PC294
0.1U_0603_25V7K~D
2
1
+5V_ALWP
PC403
1U_0603_10V6K~D
2
1
GNDA_3V5V
PAD-OPEN 4x4m
GNDA_3V5V
PJP37
+3.3V_ALWP
+3.3V_ALW
PAD-OPEN 4x4m
Title
DC/DC +3V/ +5V

Size
Document Number
Date:
Rev
0.0
LA-3302P
Sheet
1
45
of
66
+1.8VSUSP/ +0.9V_DDR_VTT
DDR2 Termination
+DDR_PWR_SRC
+5V_ALW
PR195
100K_0402_1%~D
1
2
PR194
20K_0402_5%~D
1
2
ISL88550_AVDD
PC63
19
LX
26
22
28
TP0
AVDD
SHDN
27
STBY
VTTI
13
REFIN
14
PGND2
11
VTT
12
1.8V_SUS_PWRGD 39
DDR_ON
39
PGND1
16
VOUT
+1.8V_SUSP
PC146
10U_0805_6.3V6M~D
PC77
0.1U_0402_10V7K~D
PC157
10U_0805_6.3V6M~D
+0.9V_DDR_VTTP
PC154
10U_0805_6.3V6M~D
VTTR
10
GNDA_DDR
PC153
10U_0805_6.3V6M~D
GND
SS
VTTS
Design current 0.7A for +0.9V_DDR_VTTP

Peak current 1A for +0.9V_DDR_VTTP
@
V_DDR_MCH_REF
PC66
1000P_0402_50V7K~D
@
PR202
100K_0402_1%~D
ISL88550_ILIM
ILIM
4
PR200
100K_0402_1%~D
1
2
REF
PC155
0.22U_0402_6.3V 5K~D
TON
ISL88550_AVDD
FB
GND
24
15
ISL88550A_TQFN28~D
SKIP
1
2
3
ISL88550_FB
PR84
@ 0_0402_5%~D
2
1
0.9V_DDR_VTT_ON 39
+1.8V_SUSP
PR204
20_0603_1%~D
ISL88550_REFIN
2
1
1
23
4
PR212
0_0402_5%~D
2
1
DL
29
21
ISL88550_REF 3
POK2
8
7
6
5
FDS6676AS_NL_SO8~D
PR348
0_0402_5%~D
1
2
17
5
PQ11
PR471
17.4K_0402_1%~D
@
VDD
DH
25
PC401
1000P_0402_50V7K~D
2
1
PR470
27.4K_0402_1%
1
2
1
2
PC72
0.1U_0402_10V7K~D
PC71
330U_D2E_2.5VM_R15~D
PC70
330U_D2E_2.5VM_R15~D
ISL88550_LX
18
VIN
POK1
+1.8VSUSP_L
PL14
1.4UH_HMU1350-1R4PF_15A_20%~D
BST
PR518
0_0402_5%~D
1
2
20
ISL88550_DH
1
2
3
1
PC68
PR73
0.22U_0603_10V7K~D
1
2
2
1
1_0603_5%~D
OVP/ UVP
S
S
S
+1.8V_SUSP
GNDA_DDR
8
7
6
5
PU6
G
PR506
0_0402_5%~D
1
2
D
D
D
D
PQ34
FDS8880_NL_SO8~D
PR505 @
0_0402_5%~D
GNDA_DDR
1.8 Volt +/-5%

Peck current: 10.9A
OCP min: 11.09A
+3.3V_ALW
ALW_PWRGD_3V_5V
1U_0603_10V6K~D
PC62
4.7U_0805_6.3V6K
2
1
39,45
PR193
2
1
10_1206_5%~D
PD20
RB751V-40_SOD323~D
PR193, PD20 are only used with the second-source MAX8632.
PC58
2200P_0402_50V7K~D
2
1
PC57
0.1U_0603_25V7K~D
2
1
PC55
10U_1206_25V6M~D
PC56
10U_1206_25V6M~D
PJP32
PAD-OPEN 4x4m
1
2
+PWR_SRC
GNDA_DDR
PC64
1U_0603_10V6K~D
GNDA_DDR
PJP59
GNDA_DDR
GNDA_DDR
1
PAD-OPEN1x1m
GNDA_DDR
PJP9
PAD-OPEN 4x4m
1
2
+1.8V_SUSP
PJP10
PAD-OPEN 4x4m
1
2
+1.8V_SUS
PJP11
+0.9V_DDR_VTTP
+0.9V_DDR_VTT
PAD-OPEN 4x4m

Title
+1.8VSUSP/ +0.9V_DDR_VT
Size
Document Number
Date:
Rev
0.0
LA-3302P
Sheet
1
46
of
66
+1.5V_RUN / +1.05V_VCCP / +3.3V_ALW / +3.3V_RTC_LDO

+DC2_PWR_SRC
PJP38
1
+PWR_SRC
PC304
2200P_0402_50V7K~D
2
1
PC303
0.1U_0603_25V7K~D
2
1
PC302
10U_1206_25V6M~D
1.05 Volt +/-5%

Thermal Design Current: 4.2A
Peack current: 6.1A
OCP min: 9.61A
PQ86
+1.05V_VCCP_P
+
2
1
+
2
PC388
0.1U_0402_10V7K~D
1
2
PC311
10U_1206_6.3V7K
2
1
PC310
330U_D2E_2.5VM_R9
5
6
7
8
3
2
1
PC315
0.1U_0603_25V7K~D
1
2
FDS6690AS_NL_SO8~D
PQ88
PL39
1UH_MPLC0730L1R0_11A_20%~D
PC309
330U_D2E_2.5VM_R9
5
6
7
8
D
D
D
D
G
S
S
S
GNDA_1P5V_1P05V
4
3
2
1
PC387
0.1U_0402_10V7K~D
LDOREFIN
LDO
VIN
VREF3
EN_LDO
VCC
TON
REF
BOOT1
LGATE1
PVCC
SECFB
GND
PGND
LGATE2
BOOT2
PAD
1.5V_LGATE
REFIN2_1_05
@
32
31
1
2
30 PR407 249K_0402_1%~D
GNDA_1P5V_1P05V
29 PR51920_0402_5%~D
1
GNDA_1P5V_1P05V
POK2
28
EN2
27
1.05V_UGATE
26
1.05V_PHASE
25
17
18
19
20
21
22
23
24
2
1
GNDA_1P5V_1P05V
BYP
REFIN2
OUT1
ILIM2
FB1
OUT2
ILIM1
SKIP#
PU21
POK1 ISL6236IRZA_QFN32~DPOK2
EN1
EN2
UGATE1
UGATE2
PHASE1
PHASE2
33
9
10
11
12
13
14
15
16
GNDA_1P5V_1P05V
PR411
1_0603_5%~D
1
2
@ PR503
0_0402_5%~D
8
7
6
5
4
3
2
1
2
1
PR504
@ 0_0402_5%~D
2
PR496
0_0402_5%~D
PR405
@ 0_0402_5%~D
1
2
PR497
0_0402_5%~D
1
2
POK1
EN1
1.5V_UGATE
1.5V_PHASE
PC314
0.1U_0603_25V7K~D
1
2
GNDA_1P5V_1P05V
PR401
0_0402_5%~D
PC306
0.1U_0603_25V7K~D
REF 1
2
GNDA_1P5V_1P05V
PR408
1
2
100K_0402_1%~D
8
7
6
5
G
PC404
0.1U_0402_10V7K~D
8
7
6
5
1
2
3
GNDA_1P5V_1P05V
D
D
D
D
PQ89
PR409
0_0402_5%~D
1
2
@
PR410
0_0402_5%~D
1
2
+
2
PC389
0.1U_0402_10V7K~D
1
2
PC313
10U_1206_6.3V7K
2
1
PC312
330U_D2E_2.5VM_R9
PL40
3.3UH_MPL73-3R3_6A_20%~D
2
1
S
S
S
+1.5V_RUN_P
1
2
3
PQ87
SI4800BDY-T1_SO8~D
1.5 Volt +/-5%

Thermal Design Current: 1.9A
Maximum current: 2.7A
OCP min: 3.04A
+3.3V_RTC_LDO
PC308
0.01U_0402_25V7K~D
2
1
+5V_VCC2
PC301
10U_1206_25V6M~D
PC305
PR400
0.1U_0603_25V7K~D 0_0805_5%
1
2
1
2
PC300
2200P_0402_50V7K~D
2
1
PC297
10U_1206_25V6M~D
PR399
0_0805_5%
1
2
PAD-OPEN 4x4m
PC299
0.1U_0603_25V7K~D
2
1
PR412
1_0603_5%~D
1
2
GNDA_1P5V_1P05V
+3.3V_SUS
1.05V_LGATE
GNDA_1P5V_1P05V
EN1
1.5V_RUN_ON 39
+5V_VCC2
PR416
100K_0402_1%~D
1
2
PC317
1U_0603_10V6K~D
2
1
PC316
1U_0603_10V6K~D
2
1
@ PR413
10_0603_5%~D
2
1
PR415
100K_0402_1%~D
2
1
+5V_ALW
EN2
PR478
0_0402_5%~D
1
2
1.05V_RUN_ON 38
POK2
1.05V_RUN_PWRGD 42
GNDA_1P5V_1P05V
POK1
1.5V_RUN_PWRGD 42
PJP39
1
PJP40
1
2
PJP41
PAD-OPEN 4x4m
2
PJP43
+1.5V_RUN_P
PAD-OPEN 4x4m
+1.5V_RUN
PJP42
1
+1.05V_VCCP_P
+1.05V_VCCP
PAD-OPEN 4x4m
PAD-OPEN1x1m
PAD-OPEN 4x4m
GNDA_1P5V_1P05V
A
OK to Short if CAD
System can Support
Title
+1.5V_RUN / +1.05V_VCCP
Size
Document Number
Date:
Rev
0.0
LA-3302P
Sheet
1
47
of
66
PWM PHASE
GND
1 @
PC380
100U_25V_M~D
PC270
10U_1206_25V6M~D
2
1
PC176
10U_1206_25V6M~D
PC224
2200P_0402_50V7K~D
2
1
2
PC177
10U_1206_25V6M~D
PC240
2200P_0402_50V7K~D
2
1
PC239
0.1U_0603_25V7K~D
2
1
8
7
6
5
D
D
D
D
PC271
10U_1206_25V6M~D
2
1
+VCC_CORE
2
1
PR514
0_0402_5%~D
2
VSUM
VO
PC228
2200P_0402_50V7K~D
2
1
PC227
0.1U_0603_25V7K~D
2
1
4
+VCC_CORE
18
PR269
10K_0402_1%~D
1
2
PR271
10_0402_1%~D
PC200
0.22U_0603_10V7K~D
2
1
PR270
7.68K_0805_1%~D
1
PC193
10U_1206_25V6M~D
2
1
PC272
10U_1206_25V6M~D
2
1
8
7
6
5
D
D
D
D
S
S
S
G
D
LGATE
GND
PHASE3
PL31
0.45UH_ETQP4LR45XFC_25A_20%~D
UGATE3
PC248
1500P_0603_25V7K~D
2
1
PWM PHASE
PWR_MON
2
1
PR331
7.68K_0805_1%~D
PQ61
FDS7088SN3_SO8~D
FCCM UGATE
LGATE3
PR329
10_0402_1%~D
1
PC243
0.22U_0603_10V7K~D
2
1
PR330
10K_0402_1%~D
1
2
1
2
3
4
PR262
PC198
0_0603_5%~D 0.22U_0603_10V7K~D
1 2
1
1
2
PQ50
6
BOOT
ISL6208CRZ-T_QFN8~D
PR515
0_0402_5%~D
VSUM
VO
A

Title
GNDA_VCORE
+VCORE
GNDA_VCORE
8
PC412
4700P_0402_25V7K~D
PC201
1
330P_0402_50V7K~D
2
PC411
4700P_0402_25V7K~D
PC197
1
S
S
S
G
S
1
VCC
PR268
1K_0402_1%~D
2
1
PU13
5
IRF7821TRPBF_SO8~D
PR259
82.5K_0402_1%~D
PR264
6.34K_0402_1%~D
PR267
10.5K_0402_1%
2
1
1000P_0402_50V7K~D
GNDA_VCORE
GNDA_VCORE
PC413
PR516
0.01U_0402_16V7K~D
1K_0402_1%~D
2
1
2
1
0_0402_5%~D
PC195
220P_0402_50V8J~D
1
2
VO
2
PC250
1500P_0402_50V7K~D
0_0603_5%~D
PC190
PR258
680P_0402_50V7K~D 2
1
1.69K_0402_1%~D
PC247
1500P_0603_25V7K~D
2
1
LGATE
PQ60
GND
FDS7088SN3_SO8~D
2
14
1
PC196
1U_0603_10V6K~D
GND
VSUM
17
VSUM
PR512
2
1
0_0402_5%~D
VO
PL33
30K_0402_5%~D
VW
1
PR487
0_0402_5%~D
+5V_ALW
GNDA_VCORE
COMP
PR513
0_0402_5%~D
VSUM
PHASE2
PR260
11.5K_0402_1%~D
2
1
PR232
10_0402_1%~D
+CPU_PWR_SRC
@ PR508
226K_0402_1%~D
2
1
OCSET
PR287
1
21
FB
41
PR257
2
1
332_0402_1%~D
ISEN3
PR482
VDIFF
PC214 1000P_0402_50V7K~D
2
1
GNDA_VCORE
PR231
7.68K_0805_1%~D
UGATE2
1
2
3
4
39
VIN
3V3
40
PWM PHASE
RTN
11
25
PC392
0.1U_0402_16V7K~D
13
PWM3
PR480
0_0402_5%~D
2
1
VSEN
VR_ON
12
35
PC213 1000P_0402_50V7K~D
2
1
VSSSENSE
24
FCCM
PR266
15K_0402_1%~D
CLK_EN#
PR261
2.43K_0402_1%~D
2
1
PMON
10
PR486
2
1
4.99K_0402_1%
PR481
FCCM UGATE
LGATE2
PH2
PSI#
2
38
VCC
PR328
PC242
0_0603_5%~D 0.22U_0603_10V7K~D
2
1
1
2
ISL6260CCRZ_QFN40~D
S THERM_ 6.8K +-5% TSM1A682J4302RE 0603
DPRSLPVR
ISEN2
PC260
0.1U_0402_16V7K~D
@ PH3
10KB_0603_1%_ERTJ1VG103FA~D
BOOT
ISL6208CRZ-T_QFN8~D
PC215
0.033U_0402_16V7K~D
1
2
0_0402_5%~D
1
39 IMVP_VR_ON
PU16
5
22
PC229
0.01U_0402_16V7K~D
PR509
2
VCCSENSE
DPRSTP#
36
VO
@ PR254 0_0402_5%~D
2
8 1
38,39,42,54 RUNPWROK
PWM2
26
16
GNDA_VCORE
37
DROOP
PC391
1U_0603_10V6K~D
CLK_ENABLE#
@ PR479
0_0402_5%~D
2
1
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PR263
4.53K_0402_1%~D
2
1
PC191
0.33U_0603_10V7K
PR252
2
1
10K_0402_5%~D
PWR_MON
PR248
2
1
499_0402_1%~D
28
29
30
31
32
33
34
DFB
PR249
2
1
0_0402_5%~D
H_PSI#
18
23
15
8,10,22 H_DPRSTP#
ISEN1
SOFT
27
PQ57
PWM1
IRF7821TRPBF_SO8~D
NTC
RBIAS
PC241
1U_0603_10V6K~D
VR_TT#
PU11
10,23 DPRSLPVR
D
D
D
D
S
1
2
1
470KB_0402_5%_NCP15WM474J03RB~D
2 PR239 1
0_0402_5%~D
2 PR240 1
0_0402_5%~D 2 PR241 1
0_0402_5%~D
2 PR242 1
0_0402_5%~D 2 PR243 1
0_0402_5%~D
2 PR244 1
0_0402_5%~D 2 PR245 1
0_0402_5%~D
VID0
VID1
VID2
VID3
VID4
VID5
VID6
+VCC_CORE
PC181
0.22U_0603_10V7K~D
2
1
PR230
10K_0402_1%~D
1
2
PGOOD
PH1
18
20
19
GNDA_VCORE
8
8
8
8
8
8
8
+5V_ALW
VDD
2
@
2
+CPU_PWR_SRC
38 IMVP6_PROCHOT#
PC187
0.015U_0402_16V7K~D
2
1
IMVP_PWRGD 23,39,42
VSS
1
2
PR234
1.91K_0603_1%~D
GNDA_VCORE
@ PC409
2200P_0402_50V7K~D
2
1
D
LGATE1
PR485
13K_0402_5%~D
@ PR284
0_0402_5%~D
2
1
+3.3V_RUN
GNDA_VCORE
PR290
0_0603_5%~D
1
PC182
PR233
1U_0603_10V6K~D 10_0603_5%~D
2
1
1
2
PR238
147K_0402_1%~D
2
1
PHASE1
ISL6208CRZ-T_QFN8~D
+5V_ALW
LGATE
PL29
UGATE1
FCCM UGATE
PJP31
1
PQ56
PC246
1500P_0603_25V7K~D
2
1
BOOT
PAD-OPEN 4x4m
Iccmax=44A
I_TDC=35A
OCP=65A, Intel spec=50A
FDS7088SN3_SO8~D
VCC
PR229
PC179
0_0603_5%~D 0.22U_0603_10V7K~D
2
1
1
2
PU10
5
PAD-OPEN 4x4m
0.01U_0402_25V7K~D
PC180
2
1
PR228
10_0603_5%~D
+PWR_SRC
PJP30
S
S
S
G
PC178
1U_0603_10V6K~D
2
1
+5V_ALW
@
PL47
FBMA-L18-453215-900LMA90T_1812~D
1
2
1
2
3
4
PQ42
+CPU_PWR_SRC
8
7
6
5
IRF7821TRPBF_SO8~D
PC223
0.1U_0603_25V7K~D
2
1
PC249
0.1U_0603_25V7K~D
2
1
+CPU_PWR_SRC
Size
Document Number
Date:
Rev
0.0
LA-3302P
2
48
Sheet
1
of
66
+DC_IN discharge path

+SDC_IN
PR138
0.01_2512_1%~D
CHAGER_SRC
PJP62
1
PAD-OPEN 4x4m
PR472
10_0402_1%~D
1
PR142
215K_0402_1%
PC383
1
PC128
0.1U_0603_25V7K~D
2
1
PC127
2200P_0402_50V7K~D
2
1
PC99
10U_1206_25V6M~D
+DC_IN_SS
0.22U_0402_6.3V6K
29
VFB
15
NC
16
GND
GND
+VCHGR
PR368
0_0603_5%~D
1+VCHGR_L1
5.6U_HMU1356-5R6_8.8A_20%~D 2
PQ76
SI4810BDY_SO8~D
ISL88731_TQFN28~D
@ PR373
2
1K_0603_1%~D
1
PC384
PD54
1SS355_SOD323~D
1
2
PC106
10U_1206_25V6M~D
PC104
0.1U_0603_25V7K~D
2
1
PC103
2200P_0402_50V7K~D
2
1
PC105
10U_1206_25V6M~D
+VCHGR
PR145
0.01_2512_1%~D
+VCHGR_B
5
6
7
8
PL20
PC379
10U_1206_25V6M~D
17
PC114
10U_1206_25V6M~D
19
18
CSON
PC253 @
220P_0402_50V7K~D
+5V_ALW
PC113
10U_1206_25V6M~D
PGND
CSOP
NC
PC112
0.1U_0603_25V7K~D
2
1
VREF
5
6
7
8
28
27
20
12
LGATE
2 PR360 1
1 0_0603_1%~D
PQ79
SI4800BDY-T1_SO8~D
ICOMP
23
3
2
1
NC
PHASE
PQ75
SI4800BDY-T1_SO8~D
UGATE
PC204
1U_0603_10V6K~D
1
2
PR473
10_0402_1%~D
1
PC120
0.1U_0402_10V7K~D
2
1
VCOMP
24
PR274
33_0603_1%~D
5
6
7
8
PC119
0.01U_0402_25V7K~D
2
1
PC212
0.01U_0402_25V7K~D
2
1
PR148
2.2K_0402_5%~D
2
1
@
ICM
21 ISL88731_VDDP
VDDP
NC
PR275
0_0603_5%~D
1
2
SDA
ISL88731_VREF
PC122
1U_0603_10V6K~D
2
1
PC121
0.1U_0402_10V7K~D
2
1
PR150
16.2K_0402_1%~D
2
1
18,39 THRM_SMBDAT
PC118
0.01U_0402_25V7K~D
2
1
GNDA_CHG
ISL88731_ICM
18,39 THRM_SMBCLK
SCL
14
GNDA_CHG
PC221
0.1U_0402_10V7K~D
VDDSMB
10
25
3
2
1
+5V_ALW
Vin Detector
High 17.9 V
Low 17.24 V
ACOK
11
VCC
BOOT
3
2
1
GNDA_CHG
13
GNDA_CHG
PC267
3300PF_0402_50V7K~D
2
1
0.01U_0402_25V7K~D
1
2
0_0402_5%~D
CSSN
ACIN
26
PD40
RB751V_SOD323~D
2
1
18,39,50 ACAV_IN
DCIN
PC202
1U_0603_10V6K~D
1
2
PC203
0.1U_0603_25V7K~D
2
1
PC110
C
22
PR146
PR341
15.8K_0402_1%~D
2
1
PU8
NC
PR143
49.9K_0402_1%~D
1
GNDA_CHG
PC102
1U_0805_25V4Z~D
2
1
CSSP
PR149
10K_0402_1%~D
2
1
ISL88731_VDDP
0.22U_0402_6.3V6K
1
GNDA_CHG
PJP65
ISL88731_VREF
+5V_ALW
+3.3V_ALW
Maximum charging current is 6.24A
8
IN+
IN-
O
G
+5V_ALW
PC258
0.01U_0402_25V7K~D
2
1
PC257
100P_0402_50V8K
2
1
2
G
S
PQ81
RHU002N06_SOT323
1K_0402_5%~D
PC259
10P_0402_50V8J~D
2
1
+5V_ALW
GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG
ADAPT_OC 38
D
@ PR474
2
1
IN+
GNDA_CHG
PU19A
LM393DR_SO8~D
O 1
GNDA_CHG
PR366
100K_0402_1%~D
2
1
IN-
PC256
100P_0402_50V8K
2
1
PR362
57.6K_0402_1%~D
2
1
GNDA_CHG GNDA_CHG
PC255
100P_0402_50V8K
2
1
PR363
13K_0402_1%
2
1
PC393
0.01U_0402_25V7K~D
2
1
@ PR475
33.2K_0402_1%~D
1
2
PC254
0.1U_0402_16V7K~D
2
1
38 ADAPT_TRIP_SET
PR361
1
2
8.45K_0402_1%~D
PR364
105_0402_1%~D
2
1
ISL88731_ICM
PR367
100K_0402_5%~D
2
1
PAD-OPEN1x1m
PR365
1M_0402_1%~D
1
2
GNDA_CHG
GNDA_CHG
GNDA_CHG
7
PU19B
LM393DR_SO8~D
GNDA_CHG
GNDA_CHG
GNDA_CHG
Title
3
Charger
Size
Document Number
Date:
Rev
0.0
LA-3302P
Sheet
1
49
of
66
+DC_IN discharge path

PQ62
+VCHGR
D2
D2
D1
D1
S2
G2
S1
G1
PQ64
RHU002N06_SOT323
PD47
B540C~D
2
1
FDS4935BZ_SO8~D
8
7
6
5
SBATT+
PC234
0.1U_0603_25V7K~D
1
2
PQ67
RHU002N06_SOT323
2
G
CHG_SBATT
PR310
100K_0402_5%~D
2
1
PQ66
1
2
3
PD48
+
2
PC381
100U_25V_M~D
PC382
100U_25V_M~D
+
2
+PWR_SRC
1
38
CHG_SBAT_N
D
PR309
10K_0402_5%~D
2
1
PC233
0.1U_0603_25V7K~D
2
1
PR307
100K_0402_5%~D
2
1
PC232
2200P_0402_50V7K~D
2
1
1
3
1CHG_SBAT
2CHG_SBATT_N
3
4
PR306
10K_0402_5%~D
2
1
PQ63
2
RHU002N06_SOT323 G
2
@ PR308
G
100K_0402_5%~D
2
1
18,39,49 ACAV_IN
PQ65
8
7
6
5
PR305
10K_0402_5%~D
1
2
+SDC_IN
D
+PWR_SRC
8
1
7
2
6
3
5
SBAT_G
1
3
CHG_SBATT_N
PR311
33K_0402_5%~D
1
2
RB715F_SOT323
PD49
B540C~D
2
1
3 CHG_PBAT
2
1
PQ72
5
6
7
8
PQ69
8
7
6
5
8
7
6
5
PQ70
1
2
3
PR323
42.2K_0402_1%~D
1
2
2
G
PQ74
RHU002N06_SOT323
PC237
0.1U_0603_25V7K~D
1
2
8
6
PR325
100K_0402_5%~D
PR318
33K_0402_5%~D
1
2
PR317
10K_0402_5%~D
2
1
D
IN-
RB715F_SOT323
PBAT_G
PQ73
RHU002N06_SOT323
2
G
PD51
2
IN+
O
IN-
1
3
+3.3V_ALW
PR326
32.4K_0402_1%~D
1
2
I1
I0
5
2
PR324
10K_0402_5%~D
1
2
38 PBAT_DSCHG
38,44 SBAT_PRES#
PU15
TC7SH32FU_SSOP5~D
PC236
0.1U_0603_25V7K~D
1
2
@
+3.3V_ALW
PR322
100K_0402_5%~D
1
2
PU14A
LM393DR_SO8~D
IN+
PR320
470K_0402_5%~D
2
1
PR321
147K_0402_1%~D
1
2
PBATT+
SBATT+
PBATT+
PR319
47K_0402_1%~D
1
2
PD50
2
PR315
470K_0402_5%~D
1
2
PR316
47K_0402_1%~D
1
2
PR314
470K_0402_5%~D
2
1
3
2
1
1
2
3
PQ71
5
6
7
8
+VCHGR
PBATT+
PR313
100K_0402_5%~D
2
1
4
CHG_PBATT
RHU002N06_SOT323
PQ68
PR312
10K_0402_5%~D
CHG_PBAT_N
2
1
38
PC235
0.1U_0603_25V7K~D
1
2
CHG_PBATT_N
3
LM393DR_SO8~D
PU14B RB715F_SOT323
+3.3V_ALW
Title
Selector
Size
Document Number
Date:
Rev
0.0
LA-3302P
Sheet
1
50
of
66
GPU_COREP/ +1.25V_RUN
PJP51
PC356
2200P_0402_50V7K~D
2
1
PC355
0.1U_0603_25V7K~D
2
1
@ PR447
196K_0402_1%~D
1
2
PR455
@ 10K_0402_1%~D
1
2
PR454
@ 10K_0402_1%~D
1
2
2
1
@ PQ98
@ PR458
16.9K_0402_1%~D
2
1
2
G
3
@
PR461
100K_0402_1%~D
1
2
2
G
GFX_CORE_CNTRL 52
@ PQ99
1
2
PC372
1U_0603_10V6K~D
2
1
PC373
1U_0603_10V6K~D
2
1
version
BOM structure
PJP54
GNDA_1P25V_GPU_CORE
PAD-OPEN 4x4m
PJP55
38 GFX_CORE_ON
+GPU_CORE
GNDA_1P25V_GPU_CORE
Table 1
1
GNDA_1P25V_GPU_CORE
@ PR464
10_0603_5%~D
2
1
PAD-OPEN1x1m
+5V_VCC4
PJP52
2
+GPU_COREP
PR452
0_0402_1%~D
1.25V_RUN_PWRGD 42
+5V_ALW
39 1.25V_RUN_ON
PC402
330U_D2E_2.5VM_R9~D
PC367
0.1U_0402_10V7K~D
2
1
PC365
330U_D2E_2.5VM_R9~D
+3.3V_RUN
@
PC371
0.01U_0402_25V7K~D
2
1
3
2
1
1
2
PQ97
FDS6676AS_NL_SO8~D
5
6
7
8
GNDA_1P25V_GPU_CORE
PL46
0.82UH_MPL73-R82_13A_20%~D
2
1
GFX_CORE_PWRGD 42
PR484
100K_0402_1%~D
GNDA_1P25V_GPU_CORE
GPU_CORE
Peak current: 11A
OCP min: 12.23A
5
6
7
8
D
D
D
D
S
S
S
3
2
1
2@ PR449
18.7K_0402_1%~D
1
2
G
+GPU_COREP
1
2
PR520 0_0402_5%~D
PR459
1_0603_5%~D
1
2
PQ95
FDS8880_NL_SO8~D
GNDA_1P25V_GPU_CORE
+3.3V_ALW
PR457
@ 10K_0402_1%~D
1
2
PC370
100P_0402_50V8K
2
1
PR460
1_0603_5%~D
1
2GNDA_1P25V_GPU_CORE
PC408
0.1U_0402_10V7K~D
32
31
30
29
28
27
26
25
1@ PR521
PC360
13.7K_0402_1%~D 1000P_0402_50V7K~D
1
2
2
1
1
8
7
6
5
4
3
2
1
LDOREFIN
LDO
VIN
VREF3
EN_LDO
VCC
TON
REF
BYP
REFIN2
OUT1
ILIM2
FB1
OUT2
ILIM1
SKIP#
PU25
POK1 ISL6236IRZA_QFN32~DPOK2
EN1
EN2
UGATE1
UGATE2
PHASE1
PHASE2
1@ PR451
205K_0402_1%~D
2
1
PC369
0.1U_0603_25V7K~D
1
2
GNDA_1P25V_GPU_CORE
9
10
11
12
13
14
15
16
BOOT1
LGATE1
PVCC
SECFB
GND
PGND
LGATE2
BOOT2
PR453
205K_0402_1%~D
1
2
2@ PR522
196K_0402_1%~D
2
1
17
18
19
20
21
22
23
24
1
G2
PAD
D2
33
PC407
0.1U_0402_10V7K~D
D2
S2
S1
GNDA_1P25V_GPU_CORE
GNDA_1P25V_GPU_CORE
PC368
0.1U_0603_25V7K~D
1
2
PC399
1000P_0402_50V7K~D
2
1
PR456
8.45K_0402_1%
G1
PR463
10.7K_0402_1%
PC363
220U_D2E_2.5VM_R15~D
PC364
0.1U_0402_10V7K~D
2
1
PL45
3.3UH_MPL73-3R3_6A_20%~D
2
1
PQ96
FDS6982AS_NL_SO8~D
D1
D1
PR448
@ 0_0402_5%~D
1
2
PC362
0.1U_0603_25V7K~D
VGA_ISL6236_REF
+1.25V_RUNP
PR445
0_0402_5%~D
1
2
PR446
13.7K_0402_1%~D
1
2
1.25 Volt +/-5%

Peak current: 3A
OCP min: 6.31A
PC354
10U_1206_25V6M~D
PC353
10U_1206_25V6M~D
PR443
0_0805_5%
1
2
+5V_VCC4
PR444
0_0402_5%~D
2
PC357
PR442
0.1U_0603_25V7K~D 0_0805_5%
1
2
1
2
PC352
2200P_0402_50V7K~D
2
1
PC410
10U_1206_25V6M~D
PC351
0.1U_0603_25V7K~D
2
1
PAD-OPEN 4x4m
PC349
10U_1206_25V6M~D
+PWR_SRC
PAD-OPEN 4x4m
19,37,39,41,42 RUN_ON
G86(1.15V)
2@
G72(1.0V)
1@
location
PR449,PR522
PR466
0_0402_5%~D
1
2
PR467
@ 0_0402_5%~D
1
2
PR521,PR451
PJP56
1
+1.25V_RUNP
+1.25V_RUN
PAD-OPEN 4x4m

Title
PWR_NVG72 +VDD_CORE
Size
Document Number
Date:
Rev
0.0
LA-3302P
Sheet
1
51
of
66
R103
U10A
1 C349
PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
1 C362
PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
1 C354
PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
1 C360
PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
1 C348
PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
1 C358
PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
1 C321
PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
1 C361
PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
1 C344
PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
1 C353
PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
1 C325
PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
1 C343
PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
1 C327
PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
1 C342
PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
1 C326
PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
1 C351
PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15
6 CLK_PCIE_VGA
6 CLK_PCIE_VGA#
1
R755
23 PLTRST_DELAY#
PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15
AD5
AD6
AE6
AE7
AD7
AC7
AE9
AE10
AD10
AC10
AE12
AE13
AD13
AC13
AC15
AD15
AE15
AE16
AC18
AD18
AE18
AE19
AC21
AD21
AE21
AE22
AD22
AD23
AF25
AE25
AE24
AD24
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
CLK_PCIE_VGA
CLK_PCIE_VGA#
AE3
AE4
AC6
2
0_0402_5%~D
MIOB_HSYNC
MIOB_VSYNC
MIOB_DE
MIOB_CTL3
G4
F1
G1
F2
MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT_N
R2
K2
K3
MIOB_VREF
J4
PEX_REFCLK
PEX_REFCLK_N
PEX_RST_N
DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_BLUE
DACA_GREEN
DACA_IDUMP
DACA_RSET
AD4
AC4
AE1
AD2
AD1
U9
AD3
DACA_VREF
AB4
DACB_HSYNC
DACB_VSYNC
DACB_RED
DACB_BLUE
DACB_GREEN
DACB_IDUMP
DACB_RSET
E6
F5
F4
D5
E4
L9
D6
DACB_VREF
E7
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA
IFPAB_VPROBE
IFPCD_VPROBE
6 CLK_NV_27M
For G8x use. CLK_NV_27M is 3.3V Level.

For G7x use. CLK_NV_27M is 1.2V Level
XTALOUTBUFF
R166
1
2
0_0402_5%~D
6 CLK_NVSS_27M
1
@ R165
XTALSSIN_R
PCI_DEVID0
PCI_DEVID1
T26 PAD~D
PCI_IOBAR
RAM_CFG2
RAM_CFG3
T27 PAD~D
PCI_DEVID3
RAM_CFG2
RAM_CFG3
PCI_DEVID3
1
2
@ R48
2K_0402_5%~D
BAR2_SIZE
PCI_DEVID4
1
@ R215
2
0_0402_5%~D
GFX_DEVID2 38
PCI_DEVID2 57
57
57
57
57
57
57
+3.3V_RUN
Reserved for GFx debug
BAR2_SIZE 57
PCI_DEVID4 57
+3.3V_RUN
1
2
R58
10K_0402_5%~D
LCD_DDCCLK
LCD_DDCDATA
DVI_SCLK
CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_BLU
CRT_GRN
R204 1
CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_BLU
CRT_GRN
2
DACAVREF
1
C299
DACB_RSET
R171
C217
I2CH_SDA
T8
T9
36
36
36
2
124_0402_1%~D
2 0.01U_0402_16V7K~D
CRTDDCCLK
CRTDDCDAT
DVI_SCLK
DVI_SDATA
LCD_DDCCLK
LCD_DDCDATA
I2CH_SCL
I2CH_SDA
N6
M5
I2CH_SCL
1
R169
1
R167
1
R170
1
R175
2
2.2K_0402_5%~D
2
2.2K_0402_5%~D
2
2.2K_0402_5%~D
2
2.2K_0402_5%~D
1
R163
1
R30
2
10K_0402_5%~D
2
10K_0402_5%~D
2
0.01U_0402_16V7K~D
TV_C
TV_CVBS
TV_Y
DACBVREF
DVI_SDATA
20
20
20,36
20,36
20,36
124_0402_1%~D
TV_C
TV_CVBS
TV_Y
D10
E10
F9
F10
E9
D8
C7
B7
C2
XTALOUT
C3
XTALOUTBUFF
C1
XTALSSIN
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE
AE27
AD27
AE26
AD26
AD25
D7
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
AF13
AF14
G86-620-A2_BGA533~D
2
0_0402_5%~D
RAM_CFG0 57
RAM_CFG1 57
T25 PAD~D
PCI_DEVID2
PCI_DEVID0
PCI_DEVID1
<---CRT
TV_C
1
R776
2
150_0402_5%~D
TV_CVBS
1
R777
2
150_0402_5%~D
TV_Y
1
R778
2
150_0402_5%~D
CRT_RED
1
R779
2
150_0402_5%~D
CRT_BLU
1
R780
2
150_0402_5%~D
CRT_GRN
1
R781
2
150_0402_5%~D
<---DVI
DVI_SCLK 36
DVI_SDATA 36
LCD_DDCCLK 19
LCD_DDCDATA 19
I2CH_SCL 19
I2CH_SDA 19
<---SVIDEO
PAD
PAD
T76 PAD~D
T77 PAD~D
T78 PAD~D
R203
10K_0402_5%~D
+3.3V_RUN
+3.3V_RUN
57 XTALSSIN
RAM_CFG0
RAM_CFG1
57 XTALOUTBUFF
GPIO10_SW_VREF 53,56
XTALIN
TEST
B1
CLK
THERMTRIP_VGA# 18
GPIO10_SW_VREF
1
2
R787
2K_0402_5%~D
G2
G3
J2
J1
K4
K1
M2
M1
N1
N2
N3
R3
BIA_PWM
19
ENVDD
19
PANEL_BKEN 38
GFX_CORE_CNTRL 51
PEG_MRX_GTX_P0
0.1U_0402_10V7K~D
PEG_MRX_GTX_N0
2
1
0.1U_0402_10V7K~D
C346
PEG_MRX_GTX_P1
0.1U_0402_10V7K~D
PEG_MRX_GTX_N1
2
1
0.1U_0402_10V7K~D
C359
PEG_MRX_GTX_P2
0.1U_0402_10V7K~D
PEG_MRX_GTX_N2
2
1
0.1U_0402_10V7K~D
C352
PEG_MRX_GTX_P3
0.1U_0402_10V7K~D
PEG_MRX_GTX_N3
2
1
0.1U_0402_10V7K~D
C356
PEG_MRX_GTX_P4
0.1U_0402_10V7K~D
PEG_MRX_GTX_N4
2
1
0.1U_0402_10V7K~D
C345
PEG_MRX_GTX_P5
0.1U_0402_10V7K~D
PEG_MRX_GTX_N5
2
1
0.1U_0402_10V7K~D
C355
PEG_MRX_GTX_P6
0.1U_0402_10V7K~D
PEG_MRX_GTX_N6
2
1
0.1U_0402_10V7K~D
C320
PEG_MRX_GTX_P7
0.1U_0402_10V7K~D
PEG_MRX_GTX_N7
2
1
0.1U_0402_10V7K~D
C357
PEG_MRX_GTX_P8
0.1U_0402_10V7K~D
PEG_MRX_GTX_N8
2
1
0.1U_0402_10V7K~D
C341
PEG_MRX_GTX_P9
0.1U_0402_10V7K~D
PEG_MRX_GTX_N9
2
1
0.1U_0402_10V7K~D
C347
PEG_MRX_GTX_P10 0.1U_0402_10V7K~D
PEG_MRX_GTX_N10
2
1
0.1U_0402_10V7K~D
C319
PEG_MRX_GTX_N11
2
1
0.1U_0402_10V7K~D
C339
PEG_MRX_GTX_N12
2
1
0.1U_0402_10V7K~D
C323
PEG_MRX_GTX_N13
2
1
0.1U_0402_10V7K~D
C340
PEG_MRX_GTX_N14
2
1
0.1U_0402_10V7K~D
C322
PEG_MRX_GTX_N15
2
1
0.1U_0402_10V7K~D
C350
MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11
DVI_DETECT 36
BIA_PWM
ENVDD
PANEL_BKEN
GFX_CORE_CNTRL
2@ R756
0_0402_5%~D
1
2
PEG_MRX_GTX_N[0..15]
DVI_DETECT
PEG_MRX_GTX_P[0..15]
A9
D9
A10
B10
C10
C12
B12
A12
A13
B13
B15
A15
B16
R173
10K_0402_5%~D
12 PEG_MRX_GTX_N[0..15]
PEG_MTX_GRX_N[0..15]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
DVO / GPIO
12 PEG_MRX_GTX_P[0..15]
1
2
2K_0402_5%~D
Part 1 of 5
DACs
PEG_MTX_GRX_P[0..15]
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
I2C
12 PEG_MTX_GRX_N[0..15]
AF1
AG2
AG3
AG4
AF4
AF5
AG6
AG7
AF7
AF8
AG9
AG10
AF10
AF11
AG12
AG13
AG15
AG16
AF16
AF17
AG18
AG19
AF19
AF20
AG21
AG22
AF22
AF23
AG24
AG25
AG26
AF27
PCI EXPRESS
12 PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
20,36
DAT_DDC2
DAT_DDC2
3
S
CRTDDCCLK
Q36
2N7002W-7-F_SOT323-3~D
CLK_DDC2
20,36 CLK_DDC2
2 PLTRST_DELAY#
10K_0402_5%~D
1
R525
R38
2.2K_0402_5%~D
2
G
2
G
R37
2.2K_0402_5%~D
CRTDDCDAT
Q37
2N7002W-7-F_SOT323-3~D
Title
NVG86 PCIE,GPIO,CLK
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
52
of
66
@ C39
3.3P_0402_50V8C
FBBA[2:5] 56
DQMA#[0:7]
U10C
LCD_ACLKLCD_BCLK+
1
DQMA#[0:7] 56
@ C43
3.3P_0402_50V8C~D
LCD_BCLK-
19
19
19
19
19
19
19
19
LCD_ACLK+
LCD_ACLKLCD_A0+
LCD_A0LCD_A1+
LCD_A1LCD_A2+
LCD_A2-
19
19
19
19
19
19
19
19
LCD_BCLK+
LCD_BCLKLCD_B0+
LCD_B0LCD_B1+
LCD_B1LCD_B2+
LCD_B2-
LCD_ACLK+
LCD_ACLKLCD_A0+
LCD_A0LCD_A1+
LCD_A1LCD_A2+
LCD_A2-
Keep stub for caps

as small as possible
U10B
G27
D25
F26
F25
G25
J25
J27
M26
C27
C25
D24
N27
G24
J26
M27
C26
M25
D26
D27
K26
K25
K24
F27
K27
G26
B27
N24
FBAA4
FBARAS#
FBAA5
FBA_BA1
FBBA2
FBBA4
FBBA3
FBACS1#
FBACS0#
FBAA11
FBACAS#
FBAWE#
FBA_BA0
FBBA5
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
D21
F22
F20
A21
V27
W22
V22
V24
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7
A22
E22
F21
B21
V26
W23
V23
W27
DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
DQSA_RN4
DQSA_RN5
DQSA_RN6
DQSA_RN7
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7
B22
D22
E21
C21
V25
W24
U24
W26
DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3
DQSA_WP4
DQSA_WP5
DQSA_WP6
DQSA_WP7
FBACS1#
FBACS0#
56
56
FBACAS#
FBAWE#
FBA_BA0
56
56
56
FBA_RST#
R200
1K_0402_5%~D
2
1
36
36
36
36
36
36
36
36
56
FBA_CKE
DVI_CLK+
DVI_CLKDVI_TX0+
DVI_TX0DVI_TX1+
DVI_TX1DVI_TX2+
DVI_TX2-
DVI_CLK+
DVI_CLKDVI_TX0+
DVI_TX0DVI_TX1+
DVI_TX1DVI_TX2+
DVI_TX2-
U6
IFPAB_RSET
V1
W1
T1
R1
T3
T2
V2
V3
IFPC_TXC
IFPC_TXC_N
IFPC_TXD0
IFPC_TXD0_N
IFPC_TXD1
IFPC_TXD1_N
IFPC_TXD2
IFPC_TXD2_N
J3
IFPCD_RSET
MIO_A_D0
MIO_A_D1
MIO_A_D2
MIO_A_D3
MIO_A_D4
MIO_A_D5
MIO_A_D6
MIO_A_D7
MIO_A_D8
MIO_A_D9
MIO_A_D10
A2
B3
A3
D4
A4
B4
B6
P4
C6
G5
V4
PEX_PLL_EN_TERM100
SUB_VENDOR
MIO_A_HSYNC
C4
MIOA_HSYNC
Part 3 of 5
NC_0
NC_1
NC_2
NC_3
PEX_PLL_EN_TERM100 57
SUB_VENDOR 57
PAD~D
PAD~D
PAD~D
PAD~D
3GIO_ADR_0 57
T83 PAD~D
3GIO_ADR_1 57
3GIO_ADR_2 57
T84 PAD~D
T79
T80
T81
T82
3GIO_ADR_0
3GIO_ADR_1
3GIO_ADR_2
T85 PAD~D
D12
E12
F12
C13
BUFRST_N
A6
STEREO
F7
SWAPRDY
THERMDN
THERMDP
A7
C9
B9
ROM_SCLK
ROM_SI
ROM_SO
ROMCS_N
D2
F3
D3
D1
T90 PAD~D
+3.3V_RUN
R34
10K_0402_5%~D
2
1
VGA_THERMDN
VGA_THERMDN 18
VGA_THERMDP
VGA_THERMDP 18
56
R190
10K_0402_5%~D
SERIAL
G86-620-A2_BGA533~D
C
+IFPC_IOVDD
DQSA_WP[0:7]
DQSA_RN[0:7]
DQSA_WP[0:7] 56
DVI_CLK+
DQSA_RN[0:7] 56
DVI_CLKDVI_TX0+
DVI_TX0DVI_TX1+
DVI_TX1-
+1.8V_RUN
1
DVI_TX2+
Populate R828 for G86

Populate R605 for G72.
PAD
GPU_SW_VREF
1
52,56 GPIO10_SW_VREF
G86-620-A2_BGA533~D
2
0.01U_0402_16V7K~D
2
0.01U_0402_16V7K~D
1
C286
2
0.01U_0402_16V7K~D
1
C276
2
0.01U_0402_16V7K~D
C56
R31
1.18K_0402_1%~D
B
2
LCD_A0+
@
LCD_A1+
@
LCD_A2+
@
LCD_B0+
@
LCD_B1+
@
LCD_B2+
@
Q59
2N7002W-7-F_SOT323-3~D
2
G
C58
1@ R605
909_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
1
49.9_0402_1%~D
10mil
56
56
56
56
2
R202
2
R201
2
R192
2
R191
2
R193
2
R188
2
R197
2
R195
10mil
CLKA0
CLKA0#
CLKA1
CLKA1#
DVI_TX2R29
511_0402_1%~D
C48
0.022U_0402_16V7K~D
FBA_VREF
CLKA0
CLKA0#
CLKA1
CLKA1#
T6
56
A16
L24
K23
M22
N22
M23
M24
K22
FBA_BA1
56
FB_VREF
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_REFCLK
FBA_REFCLK_N
FBA_DEBUG
FBA_RST#
FBAA7
FBAA10
FBA_CKE
FBAA0
FBAA9
FBAA6
FBAA2
FBAA8
FBAA3
FBAA1
FBARAS#
R50
1K_0402_5%~D
2
1
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
Part 2 of 5
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
2@R828
487_0402_1%~D
2
1
A26
C24
B24
A24
C22
A25
B25
D23
G22
J23
E24
F23
J24
F24
G23
H24
D16
E16
D17
F18
E19
E18
D20
D19
A18
B18
A19
B19
D18
C19
C16
C18
N26
N25
R25
R26
R27
T25
T27
T26
AB23
Y24
AB24
AB22
AC24
AC22
AA23
AA22
T24
T23
R24
R23
R22
T22
N23
P24
AA24
AA27
AA26
AB25
AB26
AB27
AA25
W25
MEMORY INTERFACE
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
LCD_BCLK+
LCD_BCLKLCD_B0+
LCD_B0LCD_B1+
LCD_B1LCD_B2+
LCD_B2-
T4
U4
N4
N5
R5
R4
T5
T6
R6
P6
W5
W6
W3
W2
AA2
AA3
AB1
AA1
AB3
AB2
NC
GENERAL
FBAA[0:11] 56
FBBA[2:5]
LCD_ACLK+
FBAD[0:63] 56
FBAA[0:11]
LVDS/TMDS
FBAD[0:63]
LCD_A02
3.3P_0402_50V8C~D
LCD_A12
3.3P_0402_50V8C~D
LCD_A22
3.3P_0402_50V8C~D
LCD_B02
3.3P_0402_50V8C~D
LCD_B12
3.3P_0402_50V8C~D
LCD_B22
3.3P_0402_50V8C~D
1
C181
1
C192
1
C193
1
C196
1
C207
1
C209
Keep stub for

caps as small
as possible
Title
NVG86 Memory Interface

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
53
of
66
2@ L53
2
@ Q97
8
1
7
2
6
3
5
40mA
+IFPAB_PLLVDD
IFPCD_PLLVDD
M4
40mA
+IFPCD_PLLVDD
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
@ Q98
2 @
2N7002W-7-F_SOT323-3~D
+PLLVDD
D13
+FBA_PLLAVDD
FBA_PLLVDD
D14
+FBA_PLLVDD
FBCAL_PD_VDDQ
D15
CLAMP
D11
2
1
R35
2@ 45.3_0402_1%~D
2
1
R825
1@ 60.4_0402_1%~D
PLLVDD
C337
10U_0805_10V4Z~D
C73
10U_0805_10V4Z~D
C71
4.7U_0603_6.3V4Z~D
C72
4.7U_0603_6.3V4Z~D
C298
0.1U_0402_10V7K~D
C288
0.1U_0402_10V7K~D
C296
0.1U_0402_10V7K~D
C306
0.1U_0402_10V7K~D
+1.8V_RUN
1@ L21
1
2
Q15
2N7002W-7-F_SOT323-3~D
2
G
3
2
R61
10K_0402_5%~D
+IFPC_IOVDD
C70
4.7U_0603_6.3V4Z~D
0.1U_0402_10V7K~D
C62
+1.8V_RUN
+2.5V_RUN
2@ L54
1
2
+1.8V_RUN
+2.5V_RUN for G7x

+1.8V_RUN for G8x.
L18
2
1
1@ L20
1
2
+3.3V_RUN
+2.5V_RUN for G7x

+1.8V_RUN for G8x.
Q14
SI1303DL-T1-E3_SOT323-3~D
3
+1.25V_RUN
+2.5V_RUN
2@ L55
1
2
+3.3V_RUN
2
G
2
2
Populate R825 for G72MV

1
2
R244
470K_0402_5%~D
@
2
C85
470P_0402_50V7K~D
1
@
1
3
Q99
2N7002W-7-F_SOT323-3~D
2
G
2
G
C290
4700P_0402_25V7K~D
H4
FBA_PLLAVDD
38,39,42,48 RUNPWROK
2
5
1
39 1.25V_GFX_PCIE_ON
C300
0.1U_0402_10V7K~D
+DACA_VDD 70mA
+DACB_VDD 140mA
AE2
F8
+1.25V_GFX_PCIE
L23
1
2
+1.8V_RUN
1
L22
2
1
+DACA_VDD
L15
2
1
C313
470P_0402_50V7K~D
V5
+IFPC_IOVDD
+DACB_VDD
1
C198
470P_0402_50V7K~D
IFPAB_PLLVDD
+IFPAB_IOVDD
C63
1U_0603_10V4Z~D
W4
Y4
L4
C239
0.1U_0402_10V7K~D
C275
0.01U_0402_16V7K~D 0.01U_0402_16V7K~D
IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
C206
10U_1206_6.3V7K~D
R292
100K_0402_5%~D
1
1
@ R300
100K_0402_5%~D
C279
0.1U_0402_10V7K~D
+3.3V_RUN
G86-620-A2_BGA533~D
PJP2
PAD-OPEN 4x4m
1
2
+1.25V_RUN
C243
0.1U_0402_10V7K~D
C328
2.2U_0603_6.3V6K~D
C205
10U_0805_4VAM~D
+15V_ALW
+3.3V_ALW2
T7
PAD
1
F6
G6
J6
4700P_0402_25V7K~D
C266
4700P_0402_25V7K~D
C235
0.022U_0402_16V7K~D
C257
0.022U_0402_16V7K~D
C244
0.1U_0402_10V7K~D
C214
0.1U_0402_10V7K~D
C230
0.1U_0402_10V7K~D
C212
0.1U_0402_10V7K~D
C213
0.1U_0402_10V7K~D
C277
4.7U_0603_6.3V4Z~D
C303
+MIOBCAL_PD_VDDQ
J5
L5
10NH_LQG15HS10NJ02D_5%_0402~D
2
1
C191
2.2U_0603_6.3V6K~D
F17
F19
J19
J22
L22
M19
P22
T19
U22
Y22
+1.8V_RUN
+3.3V_RUN
1
C318
4700P_0402_25V7K~D
K5
K6
L6
DACA_VDD
DACB_VDD
C204
4700P_0402_25V7K~D
FBVTT_0
FBVTT_1
FBVTT_2
FBVTT_3
FBVTT_4
FBVTT_5
FBVTT_6
FBVTT_7
FBVTT_8
FBVTT_9
180mA
20mA
C253
4700P_0402_25V7K~D
E15
F15
F16
J17
J18
L19
N19
R19
U19
W19
4700P_0402_25V7K~D
C254
4700P_0402_25V7K~D
C263
0.022U_0402_16V7K~D
C269
0.022U_0402_16V7K~D
C280
0.022U_0402_16V7K~D
C240
0.022U_0402_16V7K~D
C265
0.1U_0402_10V7K~D
C249
0.1U_0402_10V7K~D
C252
4.7U_0603_6.3V4Z~D
C289
+PEX_PLLAVDD
+PEX_PLLDVDD
Y6
AA5
+1.8V_RUN
C59
4.7U_0603_6.3V4Z~D
+1.25V_GFX_PCIE
MIO_A_VDDQ_0
MIO_A_VDDQ_1
MIO_A_VDDQ_2
VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
+PEX_PLLAVDD
C308
4.7U_0603_6.3V4Z~D
C307
4.7U_0603_6.3V4Z~D
C216
4700P_0402_25V7K~D
C237
4700P_0402_25V7K~D
C215
4700P_0402_25V7K~D
C234
0.1U_0402_10V7K~D
C221
0.1U_0402_10V7K~D
C236
0.1U_0402_10V7K~D
For G8x use. NC for G7x
F13
F14
J12
J13
J15
J16
VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3
C285
W9
W10
W11
W12
C311
4700P_0402_25V7K~D
C242
470P_0402_50V7K~D
C281
0.022U_0402_16V7K~D
C247
0.1U_0402_10V7K~D
C241
0.1U_0402_16V4Z~D
+3.3V_RUN
C218
1U_0603_10V4Z~D
2@ C315
0.1U_0402_10V7K~D
2@ C314
4.7U_0603_6.3V4Z~D
+FBA_PLLVDD
1
2
2@ L27
BLM18AG121SN1D_0603~D 1
1
C324
4.7U_0603_6.3V4Z~D
+1.25V_GFX_PCIE
C302
470P_0402_50V7K~D
C294
470P_0402_50V7K~D
Populate C251, C255 for G86

and G72 solution per Nvidia
C272
220P_0402_50V7K~D
C273
C271
0.022U_0402_16V7K~D 2200P_0402_50V7K~D
C261
0.1U_0402_10V7K~D
C274
0.1U_0402_16V4Z~D
C187
10U_0805_4VAM~D
C255
4.7U_0603_6.3V4Z~D
C295
0.1U_0402_10V7K~D
C317
470P_0402_50V7K~D
C278
0.022U_0402_16V7K~D
C260
2200P_0402_50V7K~D
2
C292
0.022U_0402_16V7K~D
W17
W18
AB10
AB11
AB14
AB15
AB20
AB21
AA4
AB5
AB6
AB7
AB8
AB9
AB12
AB13
AB16
AB17
AB18
AB19
AC9
AC11
AC12
AC16
AC17
AC19
AC20
VDD_0
PEX_IOVDD_0
Part 4 of 5
VDD_1
PEX_IOVDD_1
VDD_2
PEX_IOVDD_2
VDD_3
PEX_IOVDD_3
VDD_4
PEX_IOVDD_4
VDD_5
PEX_IOVDD_5
VDD_6
PEX_IOVDD_6
VDD_7
PEX_IOVDD_7
VDD_8
PEX_IOVDDQ_0
VDD_9
PEX_IOVDDQ_1
VDD_10
PEX_IOVDDQ_2
VDD_11
PEX_IOVDDQ_3
VDD_12
PEX_IOVDDQ_4
VDD_13
PEX_IOVDDQ_5
VDD_14
PEX_IOVDDQ_6
NV_PLLAVDD
PEX_IOVDDQ_7
VDD_16
PEX_IOVDDQ_8
VDD_17
PEX_IOVDDQ_9
VDD_18
PEX_IOVDDQ_10
VDD_19
PEX_IOVDDQ_11
VDD_20
PEX_IOVDDQ_12
VDD_21
PEX_IOVDDQ_13
VDD_22
PEX_IOVDDQ_14
VDD_23
PEX_IOVDDQ_15
VDD_24
PEX_IOVDDQ_16
VDD_25
PEX_IOVDDQ_17
VDD_26
PEX_IOVDDQ_18
VDD_27
VDD_28
PEX_PLLAVDD
VDD_29
PEX_PLLDVDD
VDD_30
VDD_31
VDD_32
MIOB_VDDQ_0
VDD_33
MIOB_VDDQ_1
VDD_34
MIOB_VDDQ_2
VDD_35
MIOBCAL_PD_VDDQ
POWER
+G72_PLLVDD
0.1U_0402_10V7K~D
C251
J9
J10
J11
L12
L13
L15
L16
M9
M11
M12
M13
M14
M15
M16
M17
+G72_PLLVDD
N9
N11
N17
R9
R11
R17
T9
T11
T12
T13
T14
T15
T16
T17
U12
U13
U15
U16
W13
W15
W16
C245
0.022U_0402_16V7K~D
C246
0.1U_0402_10V7K~D
+1.25V_GFX_PCIE
2
1
1@ L17
C248
0.1U_0402_10V7K~D
C258
0.022U_0402_16V7K~D
U10D
C57
10U_0805_4VAM~D
C291
0.1U_0402_10V7K~D
+GPU_CORE
2
C259
0.1U_0402_10V7K~D
6.6
+1.25V_GFX_PCIE
1808mA
+FBA_PLLAVDD
C197
0.1U_0402_10V7K~D
C188
4.7U_0603_6.3V4Z~D
40mA
1
C238
0.1U_0402_10V7K~D
C61
10U_0805_4VAM~D
+1.25V_GFX_PCIE
L14
1
2
1
+2.5V_RUN for G7x

+1.25V_GFX_PCIE for G8x.
C219
470P_0402_50V7K~D
C233
2.2U_0603_6.3V6K~D
+PLLVDD
1
2
+2.5V_RUN
1 @ L16
C220
4700P_0402_25V7K~D
C201
1000P_0402_50V7K~D
+1.25V_GFX_PCIE
Title
NVG86 Power
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
54
of
66
U10E
PEX_PLLGND
PLLGND
V6
M6
M3
AA6
H5
FBCAL_PU_GND
FBCAL_TERM_GND
E13
H22
1
FBA_PLLGND
C15
G86-620-A2_BGA533~D
1@ R824
40.2_0402_1%~D
MIOBCAL_PU_GND
IFPAB_PLLGND
IFPCD_PLLGND
U17
U23
U26
V9
V19
W14
Y2
Y5
Y23
Y26
AC2
AC8
AC14
AC23
AC26
AD8
AD9
AD11
AD12
AD14
AD16
AD17
AD19
AD20
AC5
AF2
AF3
AF6
AF9
AF12
AF15
AF18
AF21
AF24
AF26
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
2@ R174
24.9_0402_1%~D
2
1
Part 5 of 5
R757
40.2_0402_1%~D
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
PAD~DT89
B2
B5
B8
B11
B14
B17
B20
B23
B26
E2
E5
E8
E11
E14
E17
E20
E23
E26
F11
H2
H6
H23
H26
J14
K9
K19
L2
L5
L11
L14
L17
L23
L26
N12
N13
N14
N15
N16
P2
P5
P9
P11
P12
P13
P14
P15
P16
P17
P19
P23
P26
R12
R13
R14
R15
R16
U2
U5
U11
U14
GND
Populate R824 for G72MV

Populate R174 for G86.
Title
NVG86 Ground
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
55
of
66
VREF=VDDQ x Rb/(Ra+Rb)
+1.8V_RUN
VREF=0.7 x VDDQ for G86 trun on, 0.4x VDDQ when trun off
DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
1@ R172
120_0402_5%~D
+1.8V_RUN
CLKA0

and close to U49
FBA_RST#
FBACS1#
FBA_RST#
FBACS1#
ZQ
MF
RDQS0
RDQS1
RDQS2
RDQS3
A2
A11
F1
F12
M1
M12
V2
V11
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V4
V9
H10
SEN
RESET
BA2
J1
J12
VSSA
VSSA
FBA_VDDA0
FBA_VDDA1
0.047U_0402_16V4Z~D
2
0.047U_0402_16V4Z~D
2
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
H4
J11
J10
CKE
CK
CK#
DQSA_RN4
DQSA_RN7
DQSA_RN5
DQSA_RN6
+1.8V_RUN
ZQ
MF
D3
D10
P10
P3
RDQS0
RDQS1
RDQS2
RDQS3
A2
A11
F1
F12
M1
M12
V2
V11
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V4
V9
H10
SEN
RESET
BA2
J1
J12
VSSA
VSSA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
VDDA
VDDA
K1
K12
FBAD33
FBAD32
FBAD34
FBAD35
FBAD38
FBAD37
FBAD36
FBAD39
FBAD56
FBAD63
FBAD59
FBAD62
FBAD60
FBAD61
FBAD58
FBAD57
FBAD45
FBAD47
FBAD44
FBAD43
FBAD46
FBAD41
FBAD40
FBAD42
FBAD54
FBAD52
FBAD51
FBAD55
FBAD50
FBAD53
FBAD49
FBAD48
FBBA2
FBBA4
FBBA3
FBBA5
FBAA2
FBAA3
+1.8V_RUN
+1.8V_RUN
FBA_VDDA2
FBA_VDDA3
2
2
L84 BLM18PG181SN1_0603~D
1
1
L86 BLM18PG181SN1_0603~D
Change to 220ohm/100MHz
K4J52324QE-BC14_FBGA136~D
B
1@ R177
120_0402_5%~D
C913
1
C915
1
CLKA1
0.047U_0402_16V4Z~D
2
0.047U_0402_16V4Z~D
2
FBAD[0:63]
FBBA[2:5]
DQSA_WP[0:7]
DQMA#[0:7]
FBAD[0:63] 53
FBAA[0:11] 53
FBBA[2:5] 53
DQSA_WP[0:7] 53
DQSA_RN[0:7] 53
DQMA#[0:7] 53
0.01U_0402_16V7K~D
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C951
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C967
C950
0.1U_0402_10V7K~D
C948
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C966
C949
C943
470P_0402_50V7K~D
C965
0.1U_0402_10V7K~D
C947
470P_0402_50V7K~D
C964
0.1U_0402_10V7K~D
C946
FBAWE#
CLKA1
CLKA1#
FBA_RST#
FBARAS#
FBAA[0:11]
Place below decoupling caps close U14 VDDQ Pins
470P_0402_50V7K~D
C963
RAS#
CAS#
WE#
CS#
A4
A9
DQSA_RN[0:7]
1000P_0402_50V7K~D 4.7U_0603_6.3V6M~D
C962
C945
0.01U_0402_16V7K~D
H3
F4
H9
F9
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

and close to U50
100P_0402_50V8J~D
470P_0402_50V7K~D
C933
0.01U_0402_16V7K~D
C931
1000P_0402_50V7K~D
C932
0.01U_0402_16V7K~D
C930
1000P_0402_50V7K~D 4.7U_0603_6.3V6M~D
C961
C944
FBACS1#
FBACS0#
FBA_CKE
FBACAS#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
C960
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C942
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C959
C941
0.1U_0402_10V7K~D
C939
100P_0402_50V8J~D 0.01U_0402_16V7K~D
C958
C940
470P_0402_50V7K~D
C957
0.1U_0402_10V7K~D
C938
470P_0402_50V7K~D
C956
0.1U_0402_10V7K~D
C937
470P_0402_50V7K~D
C955
1000P_0402_50V7K~D 4.7U_0603_6.3V6M~D
C954
C936
C934
C952
1000P_0402_50V7K~D 4.7U_0603_6.3V6M~D
C953
C935
VREF
VREF
RFU1
RFU2
CLKA1#
+1.8V_RUN
Place below decoupling caps close U11 VDDQ Pins
0.1U_0402_10V7K~D
C929
+1.8V_RUN
2
2
Place below decoupling caps close U14 VDD Pins

0.1U_0402_10V7K~D
C928
H1
H12
J2
J3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
1
2
121_0402_1%~D
R733
1
2
121_0402_1%~D
R734
1
2
121_0402_1%~D
R735
1
2
121_0402_1%~D
R736
1
2
121_0402_1%~D
R739
1
2
121_0402_1%~D
R740
1
2
121_0402_1%~D
R741
1
2
121_0402_1%~D

0.1U_0402_10V7K~D
C927
10mil FBA_VREF1
10mil FBA_VREF3
+1.8V_RUN
K4J52324QE-BC14_FBGA136~D
4.7U_0603_6.3V6M~D
C926
100P_0402_50V8J~D
470P_0402_50V7K~D
C924
1000P_0402_50V7K~D
C923
0.01U_0402_16V7K~D
C922
0.01U_0402_16V7K~D
C921
0.1U_0402_10V7K~D
C920
0.1U_0402_10V7K~D
C919
0.1U_0402_10V7K~D
C918
C916
WDQS0
WDQS1
WDQS2
WDQS3
CLKA1
CLKA1#
L83 BLM18PG181SN1_0603~D
1
1
L85 BLM18PG181SN1_0603~D
+1.8V_RUN
4.7U_0603_6.3V6M~D
C917
D2
D11
P11
P2
Change to 220ohm/100MHz
C925
+1.8V_RUN
DQSA_WP4
DQSA_WP7
DQSA_WP5
DQSA_WP6
+1.8V_RUN
C912
1
C914
1
Place below decoupling caps close U11 VDD Pins
2
53
53
A3
A10
G1
G12
L1
L12
V3
V10
R752
10K_0402_5%~D
DM0
DM1
DM2
DM3
0.1U_0402_10V7K~D
K1
K12
C909
VDDA
VDDA
+1.8V_RUN
53
53
A4
A9
D3
D10
P10
P3
E3
E10
N10
N3
FBAA5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
240_0402_5%~D
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
FBAA4
A3
A10
G1
G12
L1
L12
V3
V10
1
R748
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CKE
CK
CK#
1.18K_0402_1%~D
H4
J11
J10
R743
FBA_CKE
CLKA0
CLKA0#
R749
240_0402_5%~D
2
1
FBA_CKE
CLKA0
CLKA0#
DQMA#4
DQMA#7
DQMA#5
DQMA#6
0.1U_0402_10V7K~D
53
53
53
1
2
2@ R832
487_0402_1%~D
RAS#
CAS#
WE#
CS#
1@ R405
909_0402_1%~D
VREF_SW_A2 1
2
C911
H3
F4
H9
F9
FBARAS#
FBACAS#
FBAWE#
FBACS0#
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
FBARAS#
FBACAS#
FBAWE#
FBACS0#
S
Q67
2N7002W-7-F_SOT323-3~D
53
53
53
53
+1.8V_RUN
VREF
VREF
RFU1
RFU2
2
G
H1
H12
J2
J3
1@ R404
909_0402_1%~D
VREF_SW_A2 1
2
R747
WDQS0
WDQS1
WDQS2
WDQS3
2@ R831
487_0402_1%~D
1
2
D2
D11
P11
P2
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
+1.8V_RUN
2@ R826
243_0402_1%~D
2
1
C910
0.1U_0402_10V7K~D
CLKA0#
DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3
10mil FBA_VREF0
10mil FBA_VREF2
2@ R827
243_0402_1%~D
2
1
DM0
DM1
DM2
DM3
FBBA4
FBBA5
FBAA6
FBAA9
FBAA0
FBAA1
FBBA2
FBAA11
FBAA10
FBBA3
FBAA8
FBAA7
FBA_BA1
FBA_BA0
C908
0.1U_0402_10V7K~D
1
2
1
R742
2
1.18K_0402_1%~D
511_0402_1%~D
1
1
R744
E3
E10
N10
N3
FBAD4
FBAD7
FBAD1
FBAD3
FBAD2
FBAD5
FBAD0
FBAD6
FBAD9
FBAD12
FBAD15
FBAD8
FBAD11
FBAD10
FBAD13
FBAD14
FBAD17
FBAD23
FBAD20
FBAD22
FBAD19
FBAD18
FBAD16
FBAD21
FBAD31
FBAD30
FBAD26
FBAD24
FBAD25
FBAD29
FBAD27
FBAD28
511_0402_1%~D
1
2
2@ R830
487_0402_1%~D
DQMA#0
DQMA#1
DQMA#2
DQMA#3
B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3
R745
1@ R403
909_0402_1%~D
VREF_SW_A1
1
2
R746
1.18K_0402_1%~D
+1.8V_RUN
FBA_BA0
FBA_BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
R738
2
G
Q66
S
2N7002W-7-F_SOT323-3~D
53
53
A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1
511_0402_1%~D
1@ R402
909_0402_1%~D
VREF_SW_A1
1
2
R737
511_0402_1%~D
+1.8V_RUN
K4
H2
K3
M4
K9
H11
K10
L9
K11
M9
K2
L4
G4
G9
FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBA_BA0
FBA_BA1
R732
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2@ R829
487_0402_1%~D
1
2
U50
R831,R832 for G86

R404,R405 for G72MV.
R831,R404 and R832,R405 place overlap
1.18K_0402_1%~D
U49
R829,R830 for G86

R402,R403 for G72MV.
R829,R402 and R830,R403 place overlap
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
VREF=0.7 x VDDQ for G72MV trun on, 0.5x VDDQ when trun off
Title
NVG86 External DDR

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
56
of
66
G72MV STRAPS
+3.3V_RUN
R802 2
R51
2K_0402_5%~D
2
1
R52
2K_0402_5%~D
2
1
1@ R49
2K_0402_5%~D
2
1
2@ R57
2K_0402_5%~D
2
1
R43
2K_0402_5%~D
2
1
R360
2K_0402_5%~D
2
1
R371
2K_0402_5%~D
2
1
R184
2K_0402_5%~D
2
1
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
R32
2K_0402_5%~D
2
1
1
1
1
1
R33
2K_0402_5%~D
2
1
2
2
2
2
R54
2K_0402_5%~D
2
1
R798
R799
R800
R801
R53
2K_0402_5%~D
2
1
RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
SUB_VENDOR
3GIO_ADR_0
3GIO_ADR_1
3GIO_ADR_2
52 RAM_CFG0
52 RAM_CFG1
52 RAM_CFG2
52 RAM_CFG3
53 SUB_VENDOR
53 3GIO_ADR_0
53 3GIO_ADR_1
53 3GIO_ADR_2
R44
2K_0402_5%~D
2
1
R46
2K_0402_5%~D
2
1
STRAPS
PIN
DESCRIPTION
Value
ROM_TYPE[1:0]
MIOBD10
MIOB_VSYNC
Parallel=00, SERIAL AT25F=01 DEFAULT,

Serial SST45VF=10, LPC=11
01
SUB_VENDOR
MIOAD1
VBIOS on card (pull high)

VBIOS with system BIOS (pull down)
PEX_PLL_TERM
MIOAD0
8Mx32 DDR monolithic (64bit)
0001
1 0_0402_5%~D
300MHz, 1.8V
BAR2_SIZE
PCI_IOBAR
PEX_PLL_EN_TERM100
PCI_DEVID4
PCI_DEVID3
R805 2
PCI_DEVID2
PCI_DEVID1
PCI_DEVID0
52 BAR2_SIZE
52 PCI_IOBAR
53 PEX_PLL_EN_TERM100
52 PCI_DEVID4
52 PCI_DEVID3
52 PCI_DEVID2
52 PCI_DEVID1
52 PCI_DEVID0
8Mx32 DDR monolithic (32bit)

1 0_0402_5%~D
1001
300MHz, 1.8V
For GDDR1
0010
8Mx32 DDR (Samsung K4D55323QF-GC)
R370
2K_0402_5%~D
2
1
R40
2K_0402_5%~D
2
1
R56
10K_0402_5%~D
2
1
R55
10K_0402_5%~D
2
1
@ R45
10K_0402_5%~D
2
1
@ R47
10K_0402_5%~D
2
1
300MHz, 1.8V
MIOBD0
4Mx32 DDR generic (64bit)
0100
MIOBD1
1.8V I/O
RAM_CFG[3:0]
MIOBD8
4Mx32 DDR generic (32bit)
MIOBD9
1100
1.8V I/O
Infineon 16Mx32
0001
500MHz, 1.8V
Hynix 16Mx32
For GDDR3
0010
500MHz, 1.8V
Device ID strapping
Samsung 16Mx32
0011
500MHz, 1.8V
DEVID3 DEVID2 DEVID1 DEVID0

1
G72M
G72MV
G86MV
C282
C297
10U_0805_10V4Z~D
R199
10K_0402_5%~D
R198
1
1
8
7
6
5
XIN/CLKIN XOUT
VSS
VDD
D_C
PD#
ModOUT REFCLK
L19
1
2
+3VL
+3.3V_RUN
P1819GF-08SR_SO8~D
R183
10K_0402_5%~D
2
R189
0_0402_5%~D
2
1
52 XTALSSIN
U21
1
2
3
4
52 XTALOUTBUFF
10K_0402_5%~D
2
1
+3.3V_RUN
0.1U_0402_10V7K~D
G72GLM
S0
-1.75% (DOWN)
0.875% (CENTER)
S0 Internal pull up
Title
NVG86 Spread Spectrum & Strapping

Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
57
of
66
Version Change List ( P. I. R. List )

Item Page#
D
Date
Request
Owner
Issue Description
Solution Description
Rev.
38
HW
08/2/2006
Compal
BID change to X01
Pop R108, depop R106
X01
18
HW
08/10/2006
Compal
Change SOT23 package to SOT323 package
Change Q102, Q59 to SOT323 package
X01
HW
08/21/2006
Compal
BITS issue WI86517 (S5 state back driver issue)
Change R324 pin1 connect from +3.3V_ALW to +3.3V_SUS
X01
41
HW
08/21/2006
Compal
Bits issue WI84312 (Derating issue)
Change R151 from 30 ohm to 75 ohm
X01
X01
23
HW
08/21/2006
Compal
Bits issue WI86509
Populate R761 and change value from 100k to 10k.

Change R761 pin1 connect from +3.3V_ALW to +3.3V_SUS
39
HW
08/21/2006
Compal
Bits issue WI86511
Add R401 (100K) for signal BC_DAT pull up to +3.3V_ALW
X01
37
HW
08/21/2006
Compal
Bits issue WI86512
Change R131 to no-stuff and from 4.7k to 100k per SMSC
X01
8
C
Title
23
HW
08/21/2006
Compal
Bits issue WI86516
38,39
HW
08/21/2006
Compal
Bits issue WI86518
10
38,39
HW
08/21/2006
Compal
Bits issue WI86532
HW
08/21/2006
Compal
Bits issue WI86752
11
18
R509 PU for SIO_EXT_SMI# change from +3.3V_ALW to

+3.3V_SUS to prevent backdrive through the ICH in S4/S5
Swap PSID GPIO from ECE5018 pin 71 with MEC5025
ITP_DBRESET# pin 55
Swap BEEP (ECE5018 GPIOB[6]) with PLTRST_DELAY#
(MEC5025 SGPIO46)
X01
Change pull-up rail for R773 from +5V_SUS to +3.3V_SUS
X01
12
21
HW
08/30/2006
Compal
13
21
HW
09/7/2006
Compal
Bits issue WI86529
Move SB_NB_PCIE_RST# to GPIO4/PIRQG# pinF12 per M08

design
Move SB_WLAN_PCIE_RST# to GPIO3/PIRQF# U32 pin G11 per
M08 direction, add test point T1 on pin F18
Change U23 from ( ST M25P80 8M bit ) to ( MXIC
MX25L1605AM2C 16M bit )
Bits issue WI86530
X01
C
X01
X01
X01
14
39
HW
09/7/2006
Compal
Bits issue WI86376. Due to increase in number of

payloads the BIOS is carrying
15
54
HW
09/7/2006
Compal
Bits issue WI87262. Add depopulated soft start capacitor
Add C85 (470PF_0402) across R244
X01
X01
X01
16
43
HW
09/11/2006
Compal
Bits issue WI90535
Change Q5 to MMBT3906WT1G, R15 to 150 ohm. Add R638 on

LED_WLAN_OUT# pull up to +3.3V_WLAN. Add R639 (10K ohm)
in series on LED_WLAN_OUT#
17
HW
09/14/2006
Compal
Briscoe ESD/EMI Improvement Requests on PT
Remove ITP port and just keep ITP test point
X01
18
34
HW
09/14/2006
Compal
Bits issue WI90713
No stuff C16
X01
19
43
HW
09/14/2006
Compal
Bits issue WI90712
Remove R73, R178, C192, and C193
X01
20
43
HW
09/14/2006
Compal
Bits issue WI90705
Add SMBus isolation circuit for WLAN,

R640,R645,R660,R662,Q45,Q46
X01
21
34
HW
09/14/2006
Compal
Bits issue WI90696
JMINI1 connect to +3.3V_RUN. Removed C427
X01
22
12
HW
09/14/2006
Compal
Shunt caps on LVDS for improving WWAN
Add C181,C192,C193,C196,C207,C209 cross LVDS signals
X01
23
27
HW
09/14/2006
Compal
Bits issue WI90516
Remove C759 from mic amp bias circuit
X01
24
26
HW
09/14/2006
Compal
Bits issue WI90487
Populate R541to cut BEEP level in half
X01
5
Title
Changed-List History
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
58
of
66

Item Page#
D
25
26
18,52
43
Date
Request
Owner
Issue Description
Rev.
HW
09/14/2006
Compal
Bits issue WI90207
Connect THERMTRIP_VGA# from U10 pinB13 to U10 pin A13.

Populate R186 for THERMTRIP_VGA# pull up
HW
09/14/2006
Compal
Bits issue WI89637
Populate EMI Clips Clip1, Clip2, Clip3, Clip4, Clip6
X01
No stuff R516, add R690 (8.2K ohm) for pull up ICH8 pin
AF22 to +3.3V_SUS
Add Q68, Q69, R691, R692 for HDDC_EN and MODC_EN
circuits
Change connect R765 pin1, R623 pin1, R621 pin1, R766
pin1, R637 pin1, R300 pin1 from +5V_ALW to +5V_ALW2
Change R387,R389 from 1M to 2.7K. Add R778,R779 for
AUX_ON,AC_OFF
23
HW
09/14/2006
Compal
Bits issue WI89409
28
25
HW
09/14/2006
Compal
Bits issue WI89407
29
41
HW
09/14/2006
Compal
Bits issue WI89394
HW
09/14/2006
Compal
Bits issue WI89379
HW
09/15/2006
Compal
Bits issue WI92249
Change R730 from 100K to 4.7K ohm
X01
Remove R39
X01
31
32
33
37,39
39
57
53,55
X01
X01
X01
X01
HW
09/15/2006
Compal
Bits issue WI92188. The MIO_A_D0 signal has an internal

pull-down in the GPU
HW
09/18/2006
Compal
Bits issue WI92289
U10 (NV86) pin F11,F12 connect to test point T89,T90

for testing and debug
X01
34
23
HW
09/18/2006
Compal
Bits issue WI92296
PLTRST_DELAY# move from ECE5018 GPOB[6] to ICH8 GPIO38
X01
35
34
HW
09/18/2006
Compal
Bits issue WI92287,WI90716
R660 and R662 connected to CLK_SCLK and CLK_SDATA.
X01
36
37
38
57,37,
22,33,
28,19,
20
23,36
23
HW
09/18/2006
Compal
EMI solutions
HW
09/18/2006
Compal
Bits issue WI92298
HW
09/18/2006
Compal
Bits issue WI92299
Populate SSCG U21,R189,R198,R199,L19,C297,C282,R166.

depopR165. Populate RS232 C152,153,154,155,156,
157,158,159. Resume ICH_AZ_MDC_BITCLK C656,R123,C128.
Add R790,R791,C232, C267. Change L63,L65 from 0603size
to 0805size. Add C309,C316 for LOM. Add C427,C463 for
LVDS. Add fuse F3, R792 for CRT. Populate C660, R545 (10
ohm),C721 (10P)
Move SIO_EXT_SCI# from to ICH8 GPIO11/SMBALERT# pin AG22
to GPO12 pin AC19. Remove D22 and R761 and net DOCK_DET#
ICH8 Pin AG22 tie to LOM_ICH_SMBALERT#. Add R793 (0 ohm)
series on LOM_ICH_SMBALERT# and LOM_SMB_ALERT#. Change
R730 pull up rail from +3.3V_ALW to +3.3V_LAN. Add R807
pull up to +3.3V_SUS for LOM_ICH_SMBALERT#
Move ALW_PWRGD_3V_5V from MEC5025 pin 18 to MEC5025
pin 29. Remove 3.3V_5V_SUS_PWRGD from MEC5025 pin 29
Swap DOCK_SMB_PME and DOCK_SMB_ALERT# from MEC5025 pin3
and ECE5028 pin76
Removed 3.3V_LAN_PWRGD from MEC5025 KSO15/GPIO5.
Remove U52,Q83,D29,R89,R98,R381,C784,C182,C183,C184
39
39
HW
09/18/2006
Compal
Bits issue WI92301
40
38,39
HW
09/18/2006
Compal
Bits issue WI92305
41
39,42
HW
09/18/2006
Compal
Bits issue WI92308
X01
27
30
Title
X01
X01
X01
B
X01
X01
X01
42
39
HW
09/18/2006
Compal
Bits issue WI92312
Add R795 (10K ohm) pull down for MEC5025 pin 14
X01
43
29
HW
09/19/2006
Compal
EMI issue
Populate R671~R678 and C866~C869. Change L69~L76 from

24NH to 36NH inductor
X01
44
27
HW
09/19/2006
Compal
Bits issue WI90510
Add R796,R797 (0ohm) between L47/L48 and C728/C730
X01
45
57
HW
09/20/2006
Compal
EMI request
Add R798~R803 for strap damping
X01
5
Title
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
59
of
66

Item Page#
D
Title
Date
Request
Owner
Issue Description
Rev.
46
18
HW
09/20/2006
Compal
Bits issue WI92860
Depop Q39 and R427
X01
47
28
HW
09/20/2006
Compal
Bits issue WI92858
Change R669 to from 1.15K to 1.13K. Depop C771 & C772.

Change C861 and C862 to 22pF
X01
48
38
HW
09/20/2006
Compal
Bits issue WI92857
Add no-stuff series 0-ohm for ITP_DBRESET# on ECE5028
X01
49
33
HW
09/21/2006
Compal
Bits issue WI93157
Remove R586 and make JMDC pin2 NC
X01
50
34
HW
09/21/2006
Compal
Bits issue WI93158
Depop Q45, Q46
X01
51
HW
09/25/2006
Compal
Bits issue WI93403
C484 change to 33pF, C861/C862 change to 22pF
X01
52
29
HW
09/26/2006
Compal
Bits issue DF86424
No Populate C866-C869/R671-R678
X01
53
40
HW
09/26/2006
Compal
EMI request
Add D37-D40 for stick point signals
X01
54
32
HW
09/27/2006
Compal
Bits issue DF94094
Add FUSE4,FUSE5
X01
55
HW
09/28/2006
Compal
Bits issue WI94923
C329,C330 chagne back to 10 0805 X6S
X01
56
18
HW
10/05/2006
Compal
Bits issue WI94892
Populate R771, C750, R772, Q102, R773
X01
Change R603 from 6.2k to 5.9k.

Change C805 from 820pF to 270pF
X01
57
30
HW
10/05/2006
Compal
Bits issue WI95910
58
38,23
27,6
HW
10/05/2006
Compal
Bits issue WI95932
59
36
HW
10/14/2006
Dell
Bits issue WI97539
60
HW
10/17/2006
Dell
Bits issue WI97837
61
23
HW
10/18/2006
Dell
62
38
HW
10/24/2006
Dell
Board ID Changed to X02
62
38
HW
10/24/2006
Dell
Bits issue WI98660
63
23
HW
11/16/2006
Dell
Bits issue WI104573
64
6,23,34
HW
11/16/2006
Dell
Bits issue WI103311
65
39
HW
11/18/2006
Dell
Bits issue WI103986
Change C379 from 22pF to 33pF per KDS X'tal report
X02
66
25,41
HW
11/20/2006
Compal
Bits issue WI105207
Change net name from +5V_ALW2 to +3.3V_ALW2 at R618.1,

R626.1, R623.1, R621.1, R766.1, R765.1, R637.1, R300.
X03
No stuff R227, R221, C89, C93, C97, c401, C92, r72, C90,
C94. No stuff C775-C781, C785. No stuff R514 (no iAMT).
Populate R515.
Added signal DOCK_DET# to JDOCKBpin137, pin205 and
Q3pin2
Add 0.1 uf (0402) caps on +Vcc_Core to Gnd. Four
total, bottom of board. (C870 ~ C873)
Bits issue WI98222 (Change for ASF2.0 due to ICH8M errata ) 1. No stuff R502, R503
2. Connect the pad of R503.2 to the pad of R498.2
3. Connect the pad of R502.1 to the pad of R499.2
X01
X02
X02
B
X02
X02
Populated R106, R107. Depopulated R108, R109.

The DevID for G86 on Briscoe needs to be updated to 1011
Add R816,C874 for USB_IDE#. R817,C875 for SIO_EXT_WAKE#.
R819,C876 for PCIE_MCARD1_DET#. R820,C878 for
USB_MCARD1_DET#. R818,C877 for USB_MCARD2_DET#. Remove
net RSVD_GPIO6 and R513
Change R309 from 8.2K to 2.2K. No stuff R820.
No stuff R550
X02
X02
X02
5
Title
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
60
of
66

Item Page#
D
Title
Date
Request
Owner
Issue Description
67
28
HW
11/21/2006
Dell
Bits issue WI105200
68
6,54,57
HW
11/21/2006
Dell
Bits issue WI105712
69
38,39
HW
11/21/2006
Dell
Bits issue WI105754
HW
11/21/2006
Dell
Bits issue WI105758. Updates for potential Back Drive
HW
12/1/2006
Dell
Bits issue WI106999
70
71
26
21,23,34
Rev.
Change L64,L66,L67,L68 from BLM18AG601SN1D to

BK1608LM182. Change R668 to L88 BK1608LM182.Change L63,
L65 from BLM21AG601SN1D to BK2125LM182.
Depop R697,change R286 to 0 ohm.Pop L53,depop L16.Pop
L27,C314,C315.Depop L20,L21,pop L54,L55.Depop L17.
Change R794 pin1 from +5V_ALW to +3.3V_ALW.
Change R245 pin1 from +3.3V_ALW to +5V_ALW
Add 100kohm resistor R721 between U35 pin 40 and
+3.3V_RUN and 1000pF cap C759
Please populate R820 with a 4.7k-ohm resistor. Move
signal PCIE_MCARD2_DET# from ICH8m GPIO20 pinAE11 to
PIRQH#/GPIO5 pinB3. Delete R457 and net
ICH_GPIO5_PIRQH#. Populate R550
X02
X02
X02
X02
X02
72
41
HW
12/1/2006
Dell
Bits issue WI107466. +2.5V_LAN in-rush current test fai.
Populate C208
X02
73
HW
12/5/2006
Dell
Bits issue WI107881
Change R286 from 0 ohm to 33 ohms
X02
74
27
HW
12/6/2006
Dell
Bits issue WI107896
Change R554 from 10K to 0 ohm
X02
75
36,38
HW
12/6/2006
Dell
Bits issue WI108259. Per M08 GPIO map rev A15 Change list
Change net DOCK_SMB_PME to DOCK_SMB_PME#
X02
76
HW
12/6/2006
Dell
Bits issue WI108223
Change C177,C179,C178,C366,C338,C365 to
EEFSX0D221E7 220uF
X02
77
52
HW
12/12/2006
Dell
Bits issue WI109622. Per NB8M PUN document
Change R35 from 60.4 ohm to 40.2 ohm
X02
78
55
HW
12/13/2006
Dell
Bits issue WI109627
Change R174 from 40.2 ohm to 30 ohm
X02
Add EC_FLASH_PAD pin1 connect to +3.3V_ALW,pin2 connect

to R76 pin1 and R80 pin1
Add R822 (1M_0402) from Pin 10 (C1P) pin of MAX9789A
to ground
Add R823 (10K_0402) to ground on pin 47 of STAC9205
(U37)
Change R683 from 150ohms to 110 ohms, R684from
150ohms to 200ohms
Change C500~C531,C664,C666~C670,C851,C853 from 0.1uF Y5V
to 0.1uF X7R
Change R174 to 24.9 ohm for G86, Add R824 40.2 ohm for
G72. Change R35 to 45.3 ohm G86, add R825 60.4 ohm for
G72MV
X02
79
39
HW
12/14/2006
Dell
Bits issue WI110179
80
27
HW
12/15/2006
Dell
Bits issue WI110158
81
26
HW
12/18/2006
Dell
Bits issue WI110749
82
29
HW
12/20/2006
Dell
Bits issue WI111288
83
12,23
28
HW
12/25/2006
Dell
Change AC Coupling Cap SPEC for PCIE
84
54,55
HW
1/5/2007
Dell
Bits issue WI113179
85
56
HW
1/5/2007
Dell
Bits issue WI113180
Add R826,R827 243 ohm for G86
X03
86
53,56
HW
1/5/2007
Dell
Bits issue WI113227
Add R828,R829,R830,R831,R832 487 ohm for G86
X03
87
38
HW
1/5/2007
Dell
Chagne Board ID to X03
Populate R108, de-pop R106
X03
88
HW
1/8/2007
Dell
Bits issue WI113588
Change U10 value to G86-620-A2. Add R833=147 ohm with

R697 use 1@ for G72. R286=33 ohm use 2@ for G86.
Change R48 note to "Reserved for GFx debug".
X03
X02
X02
B
X02
X02
X03
5
Title
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
61
of
66

Item Page#
D
Title
Date
Request
Owner
Issue Description
Rev.
89
38
HW
1/26/2007
Dell
Bits issue WI115658. M08 GPIO map rev A16 change
Change ECE5028 GPIOF4 from BID2 to CHIPSET_ID.
X03
90
23
HW
2/12/2007
Dell
Bits issue WI121957
Add R834 (1M_0402_1%) for ICH_LAN_RST#
X03
91
27
HW
2/12/2007
Dell
Bits issue WI121438
Change R565 from 10K to 100k ohm
X03
92
41
HW
2/12/2007
Dell
Bits issue DF116813
Depop C194, changed C815 from 4700pF to 2200pF
X03
93
54
HW
2/14/2007
Dell
Modify pop option symbol for G72M/G86M power bead
L53,L27,L55,L54, with 2@, L16,L17,L21, L20, with 1@
X03
94
57
HW
2/14/2007
Dell
Modify NV strap table
Change GDDR3 table from 500 MHz to 700 MHz
X03
95
18
HW
2/26/2007
Dell
Bits issue WI124164
populate C640 = 10uF for G72MV. Add 1@ for C640
X03
96
54 57
HW
2/26/2007
Dell
Bits issue WI124408
Add note "Populate C251, C255 for G86 and G72 solution
per Nvidia". Add 2@ for C314, C315, R805 and R57. Add
1@ for R49.
X03
C
97
54
HW
2/27/2007
Dell
Bits issue WI123608
Change C233 from X5R to X7R
X03
98
23
HW
2/27/2007
Dell
Bits issue WI125173. Per Intel's latest recommendation
Change R834 from 1M to 10K
X03
99
54
HW
2/28/2007
Dell
Bits issue WI123608
Change C233 back to X5R
X03
Add 2@ for R756, R187, Q76, C203
X03
100
18 52
HW
2/28/2007
Dell
Bits issue WI124613. Need to connect THERMTRIP_VGA to the

thermal sensor for G86
101
18
HW
3/1/2007
Dell
Bits issue WI125873. Populate circuit for THERMTRIP_MCH#
Populate R427 and Q39
X03
102
27
HW
3/7/2007
Dell
Bits issue WI127300
Change U40 from 74AHC1G08 to 74AHCT1G08
X03
5
Title
Size
Document Number
Date:
Rev
0.4
LA-3302P
Sheet
1
62
of
66

Item Page#
Title
Date
Request
Owner
Issue Description
48/50
PWR
9/14
Elick
45
PWR
9/14
DELL
change to correct parts for 15ALW
48
PWR
DELL
change to PSL of DELL
44
PWR
9/14
DELL
44
PWR
9/14
DELL
10
PWR
46
PWR
45
PWR
47
PWR
49
PWR
51
9/14
change the AL CAP
to 2000hr
12
PWR
47
PWR
44
0.1
change PD55 from SCSB717F08L to SCS00001U8L.

change PD56 from SCSB717F08L to SCS00001U8L.
0.1
change PH2 from SL20000030L to SL200000F8L
0.1
change PL1 from SM01001680L to SM010008U0L.
0.1
BITS-WI89364
The 0.9V_DDR_VTT_PWRGD net is not used at
the MEC5025.
The 0.9V_DDR_VTT_PWRGD net should be no
connect
at the MEC5025 pin 73.
DELL
9/14
DELL
9/14
DELL
BITS-WI91278
following DELL rule
9/14
DELL
BITS-WI91289
be compliant with the reference schematic.
Change PR274 from 4.7 ohm(SD000006T8L) to 33 ohm(SD014330A8L).

Populate PR373 and PD54.
0.1
Add PC410 10uF, 1206, 25V at the input rail (+PWR_SRC) of

the 1.25V_RUN regulator.
Change PR460 from 0 ohm(SD01300008L) to 1 ohm(SD013100B8L).
Change PR459 from 0 ohm (SD01300008L) to 1 ohm(SD013100B8L).
Change PR449 ground connection from AGND to PGND.
0.1
DELL
BITS-WI91295
Implement changes to 1.25V_RUN and
GPU Core regulators
DELL
BITS-WI91372
following DELL rule
Change PR408 from 75K(SD03475028L) to 82.5K(SD00000278L).
0.1
BITS-WI91682
DC IN schematic changes.
Change
Change
PQ100A
Change
PQ100B
Change
0.1
9/14
BITS-WI91011
change to correct current limits
9/14
9/14
DELL
remove
PR437, PR438, PR441, PQ93 and PQ94.
DELL
BITS-WI90985
following DELL rule
Change PC285 pin 2 pad connection

from PGND to AGND.
14
45
PWR
9/14
DELL
BITS-WI90988
Change PQ83 from FDS8880 to
BSC079N03SG PPAK
Change PQ83 from SB000004U8L to SB000004D8L.
9/15
DELL
0.1
PL1 from SM01001680L to SM010008U0L.

PQ100 from SI2301BDS(SB923010020) to
depopulated IMD2A(SB000009N8L).
PQ101 from SI2301BDS(SB923010020) to
depopulated IMD2A(SB000009N8L).
PR12 from 10K,0603(SD01310028L) to 4.7K,0805(SD00247018L).
9/14
PWR
0.1
Depopulate PR415 and PR416 resistors.
PWR
0.1
Change PR383 from 124K(SD03412438L) to 150K(SD03415038L).

Change PR382 from 187K(SD03418738L) to 226K(SD03422638L).
45
51
0.1
9/14
13
15
change PC380 from SF10004M08L to SF000000S8L.

change PL2 from SM01001418L to SM010009C8L.

change PL34 from SM01001418L to SM010009C8L.
11
Rev.
0.1
0.1
BITS-WI92173
correct the current limit on
GPU CORE regulator
Change PR451 from 140K(SD03414038L) to 182K(SD03418238L)
0.1
Title
5
Changed-List History 1
Size
Document Number
Date:
Rev
0.6
LA-3302P
Sheet
1
63
of
66

Item Page#
D
16
17
18
19
Title
Date
Request
Owner
Issue Description
51
PWR
9/15
DELL
46
PWR
9/15
DELL
46
PWR
9/18
DELL
BITS-WI92459
follow BITS of DELL
DELL
BITS-WI92462
improve transients at load dump.
and reduce jittering.
48
PWR
9/18
Rev.
BITS-WI92161
1.25V_RUN regulator.
Change PR453 from 140K(SD03414038L) to 205K (SD03420538L)
0.1
BITS-WI91932
1.8V output
Change PR202 from 61.9K(SD03461928L) to 100K (SD03410038L)
0.1
change PR193
change PR506
change PR505
0.1
to be populate.
to be populate.
to be depopulate.
Add depopulate PR516(SD03410018L) and depopulate PC413(SE076103K8L)

between pin 9 of PU11 and AGND.
Add depopulated PC411(SE075472K8L),4700pF between pin 14 of PU11 and AGND .0.1
Add depopulated PC412(SE075472K8L),4700pF between pin 15 of PU11 and AGND
20
21
22
51
PWR
51
PWR
44
PWR
9/18
9/20
9/21
DELL
Elick
DELL
BITS-WI87245
PWRGD signals are reversed coming from the
wrong side of the IC.
change GPU_CORE voltage
Change the node name at pin 13 of PU25 from

1.25V_RUN_PWRGD.
Change the node name at pin 28 of PU25 from
GFX_CORE_PWRGD .
Remove +3.3V_RUN node connected to pin 2 of
Remove +3.3V_ALW node connected to pin 1 of
Remove +3.3V_ALW node connected to pin 1 of
Remove totally PR462 pad, PR483, PR450.
GFX_CORE_PWRGD to
1.25V_RUN_PWRGD to
0.1
PR462.
PR483.
PR450.
change PR446 from 10k to 13.7k(SD03413728L)
BITS-WI91682
change PL1 from BK1608HM to BLM18BD102SN1D.
0.1
change PL1 from SM010008U0L to SM010007C8L.
0.1
BITS-WI87563
change populate PC380 from 25CE100AX
to 25CE100LS
change PC381 from 25CE100AX to 25CE100LS
change PC382 from 25CE100AX to 25CE100LS
23
48/50
PWR
9/21
DELL
24
49
PWR
9/29
DELL
25
49
PWR
9/29
DELL
26
49
PWR
9/29
DELL
match Maxim's response time of ICM input

to comparator.
ICM is voltage source and does not
need this component.
Increase BW from 20kHz to 25kHz while
maintaining 80degrees phase margin.
27
49
PWR
9/29
DELL
following DELL rule
28
48
PWR
10/27
DELL
change populate PC380 from SF000000S8L to SF000000T8L.

change PC381 from SF000000S8L to SF000000T8L.
change PC382 from SF000000S8L to SF000000T8L.
0.1
change PR361 from 0 Ohm (SD02800008L) to 8.45K (SD00000068L).

change PC254 from 0.01uF 25V (SE068103K8L) to 0.1uF 16V (SE076104K8L).
0.1
depopulate PR150.
0.1
change PR148 from 4.7K (SD03447018L) to 10K (SD03410028L).
0.1
depopulate PD54 and PR373
0.1
A
Add bead to connect +PWR_SRC to

+CPU_PWR_SRC
0.2
Add PL47(SM01002078L) to parallel PJP30.
Title
5
Size
Document Number
Date:
Rev
0.6
LA-3302P
Sheet
1
64
of
66

Item Page#
D
29
45,46,
47,51
Title
Date
Request
Owner
PWR
10/27
DELL
30
49
PWR
31
45
PWR
32
49
PWR
10/27
11/20
12/06
Issue Description
BITS-WI99895
This is to add an optional ultrasonic mode
in case the regulators experience an
audible noise.
Add
Add
Add
Add
PR517
PR519
PR520
PR518
0
0
0
0
ohm
ohm
ohm
ohm
0402(SD02800008L)
0402(SD02800008L)
0402(SD02800008L)
0402(SD02800008L)
between
between
between
between
pin
pin
pin
pin
29
29
29
26
of
of
of
of
Rev.
D
PU20 and AGND .

PU21 and AGND .
PU25 and AGND .
PU6 and AGND .
0.2
DELL
BITS: WI102600
Change PR148 from 10K_0402_1% to 2.2K_0402 change PR148 from 10k 0402 1%(SD03410028L) to 2.2k 0402 5%(SD02822018L)
_5%
0.3
DELL
BITS-WI105406
Add node name +3.3V_ALW2 for the trace
connected to the pin 5 (VREF3) of PU20.
Populate PC285 with 0.1uF cap.
Add node name +3.3V_ALW2 between pin5 of PU20 and PC285.

Populate PC285.
0.3
BITS-WI106278
make sure that PC113, PC114 and PC379 are
X5R/X7R caps, need to stuff PC379.
change PC379 is populated.
0.3
DELL
33
34
35
36
48
51
49
44
PWR
12/06
DELL
PWR
01/04
ELICK
BITS-WI108229
Change PC187 from 10nF to 15nF.
Change PR258 from 2.21K to 1.69K.
Populate PR516 with 1K resistor.
Populate C413 with 0.01uF.
change PR187 from 10nF(SE076103K8L) to 15nF(SE076153K8L).

change PR258 from 2.21K(SD03422118L) to 1.69K(SD00000JB8L).
populate PC413.
populate PR516.
0.3
Add PL3 to parallel PJP54.

add PC414 to connect between GPU_CORE to GND.
add PC415 to connect between GPU_CORE to GND.
EMI CLK issue
PWR
01/25
ELICK
change to new part number for PSL
PWR
01/26
ELICK
change bead to 9A 1812 in DC-IN.
0.3
change PR138 from SD021100D8L to SD021100D3L(S RES 1W .01 +-1% 2512

FOR M08 PROJECTS)
change PR145 from SD021100D8L to SD021100D3L(S RES 1W .01 +-1% 2512
FOR M08 PROJECTS)
0.4
change PL2 from SM010009C8L(TAIYO FBMJ4516HS720NT 1806)

to SM01000BI0L(KC FBCA-K5B-302340-L1-T 1812 ).
change PL32 from SM010009C8L(TAIYO FBMJ4516HS720NT 1806)
to SM01000BI0L(KC FBCA-K5B-302340-L1-T 1812 ).
37
45/47/51
PWR
02/05
DELL
BITS-WI119950
Increase current limits for 3.3V, 1.5V
and GPU_CORE regulators.
38
49
PWR
02/06
DELL
additional 1206 resistor on +VCHGR for

Maxim solution.
39
49
PWR
02/12
DELL
delete 1206 resistor on +VCHGR

not to implement for Maxim solution.
0.4
change PR382 from 226K to 267k (SD02822018L).

Change PR408 from 82.5K to 100K(SD03410038L).
Change PR451 from 182K to 205K(SD03420538L) .
0.4
add an unpopulation
+VCHGR to PGND.
0.4
delete an unpopulate
+VCHGR to PGND.
PR522 (1.8K 1206 1%(SD00000JN8L))between
PR520 (1.8K 1206 1%(SD00000JN8L))between
0.4
Title
5
Size
Document Number
Date:
Rev
0.6
LA-3302P
Sheet
1
65
of
66

Item Page#
Title
Date
Request
Owner
Issue Description
40
51
PWR
02/26
DELL
BITS-WI123151
GPU Core Voltage for G86MV is staying at
1.15V all the time
Rev.
D
Nostuff: PR447, PR457, PC370, PR452, PQ98, PR461, PC371, PR458, PQ99,
PR454, PR455.
Change 2@PR449 from 20.5K to 18.7K 0402 1%(SD03418728L )
Add 2@PR522 = 196K, 0402. <-- This would be a 2@ resistor added in
parallel to the existing PR451
0.4
Title
5
Size
Document Number
Date:
Rev
0.6
LA-3302P
Sheet
1
66
of
66

3094 Dell Latitude d630 Compalm08 (Dis) Briscoe La-3302

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3094 Dell Latitude d630 Compalm08 (Dis) Briscoe La-3302

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A

MODEL NAME : IBQ00

M08 (DIS) Briscoe

uFCPGA Mobile Merom

PCB ZGX LA-3302P

Compal Electronics, Inc.

Wednesday, March 07, 2007

CPU ITP Port

FSB 800 MHz

USB0 : side pair top,

USB2 : Rear Left as viewed from the back,

PCI Express BUS

DOCK LPC BUS

AMP & INT.

Monday, February 26, 2007

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

S5 S4/AC don't exist

MINI CARD-1 WWAN

MINI CARD-2 WLAN

Index and Config.

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

Compal Electronics, Inc.

Monday, February 26, 2007

Place crystal within

Pin 5/6 as SRC_10

Pin 5/6 as CPU_ITP

Compal Electronics, Inc.

Populate R697,R833 for G72MV

Thursday, March 01, 2007

H_THERMDA, H_THERMDC routing together,

Place near JITP

This shall place near CPU

Thursday, March 01, 2007

CRB was 270uF

Resistor placed within 0.5" of

Length match within 25 mils, Z0=27.4 ohm

Place R342 and R343 near CPU

For the purpose of testability, route these signals

Route VCCSENSE and VSSSENSE trace at

Place C490 close to the

Layout close CPU PIN AD26

Thursday, March 01, 2007

Place these inside 1

Place these inside 1

Place these inside 1

Place these inside 1

10uF 0805 X6S -> 85 degree C

High Frequence Decoupling

Near VCORE regulator.

South Side Secondary

North Side Secondary