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Experiment-1 Realization of Basic Gates using Verilog

AIM: To realize the basic gates (AND, OR, NOT, NAND, NOR) using Gate Level Description and Dataflow Description styles of Verilog CODE: Gate-Level Description module Basicgates(a,abar,b,c,d,e,f,g,h,i,j,k,l,m); input a, b, c, e, f, h, i, k, l ; output abar, d ,g ,j ,m; //Structural Flow Description not a1(abar,a); and an1(d,b,c); or o1(g,e,f); nand na1(j,h,i); nor no1(m,k,l); endmodule DATAFLOW DESCRIPTION module basegateda(a,abar,b,c,d,e,f,g,h,i,j,k,l,m); input a, b, c, e, f, h, i, k, l ; output abar, d ,g ,j ,m; //Dataflow Style assign abar = ~a; assign d = b & c;
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assign g = e | f; assign j = ~(h & i); assign m = ~(k | l); endmodule TEST BENCH module testbasigat; // Inputs reg a, b, c, e, f, h, i, k, l ; // Outputs wire abar, d ,g ,j ,m; // Instantiate the Unit Under Test (UUT) basegateda uut ( .a(a), .abar(abar), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .i(i), .j(j), .k(k), .l(l), .m(m) ); initial begin // Initialize Inputs a = 0; b = 0; c = 0; e = 0; f = 0; h = 0; i = 0; k = 0; l = 0; #100; a = 1; // Wait 100 ns for global reset to finish

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b = 0; c = 1; e = 0; f = 1; h = 0; i = 1; k = 0; l = 1; #100; a = 0; b = 1; c = 0; e = 1; f = 0; h = 1; i = 0; k = 1; l = 0; #100; a = 1; b = 1; c = 1; e = 1; f = 1; h = 1; i = 1; k = 1; l = 1; end endmodule // Wait 100 ns for global reset to finish // Wait 100 ns for global reset to finish

SIMULATION:
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Experiment-2 Realization of Half Adder using Verilog

AIM: To realize Half Adder using Gate Level Description and Dataflow Description styles of Verilog CODE: GATE LEVEL DESCRIPTION: module strhalad(a, b, s , c); input a,b; output s,c; //Structural Style of Programming FOr Half Adder xor x1(s,a,b); //Sum output is defined using the structural style and a1(c,a,b); //Carry output is defined using the structural style endmodule DATAFLOW DESCRIPTION: module halvade(a, b, s, c); input a,b; output s,c; // Data Flow style Program for Half Adder

assign s= a ^ b; assign c= a endmodule TEST BENCH: module testhalad; reg a,b; // Inputs & b;

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wire s,c;

// Outputs

// Instantiate the Unit Under Test (UUT) halvade uut (.a(a), .b(b), .s(s), .c(c) initial begin a = 0; b = 0; // Initialize Inputs );

#100; // Wait 100 ns for global reset to finish a = 0; b = 1; #100; // Wait 100 ns for global reset to finish a = 1; b = 0; #100; // Wait 100 ns for global reset to finish a = 1; b = 1; #100; // Wait 100 ns for global reset to finish end endmodule

SIMUATION:

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Experiment-3 Realization of Full Adder using Verilog

AIM: To realize Full Adder using Gate Level Description and Dataflow Description styles of Verilog CODE: GATE LEVEL DESCRIPTION: module strfulad(a, b, c, s, ca); input a, b, c; output s,ca; wire w1,w2,w3; //Structural Description Code for Full Adder xor x1(s,a,b,c); //Description for a xor b xor c resulting in sum /*Description for ab or bc or ac resulting in carry */ and a1(w1,a,b); and a2(w2,b,c); and a3(w3,a,c); or o1(ca,w1,w2,w3); endmodule DATAFLOW DESCRIPTION: module fuladat(a, b, c, s, ca); input a, b, c; output s,ca; //Dataflow Description code for Full Adder

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assign s= (a ^ b ^ c); //Defining the output Sum by a xor b xor c assign ca=((a & b) | (b & c) | (c & a)); /*defining the output Carry by (a and b) or (b and c) or (c and a)*/ endmodule TEST BENCH: module fuadat; // Inputs reg a; reg b; reg c; // Outputs wire s; wire ca; // Instantiate the Unit Under Test (UUT) fuladat uut (.a(a), .b(b), .c(c), .s(s), .ca(ca)); initial begin // Initialize Inputs a = 0; b = 0; c = 0; #100; // Wait 100 ns for global reset to finish a = 0; b = 0; c = 1; #100; // Wait 100 ns for global reset to finish a = 0; b = 1; c = 0; #100; // Wait 100 ns for global reset to finish a = 0; b = 1; c = 1;

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#100; // Wait 100 ns for global reset to finish a = 1; b = 0; c = 0; #100; // Wait 100 ns for global reset to finish a = 1; b = 0; c = 1; #100; // Wait 100 ns for global reset to finish a = 1; b = 1; c = 0; #100; // Wait 100 ns for global reset to finish a = 1; b = 1; c = 1; end endmodule

SIMULATION:

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Experiment-4 Realization of Half Subtractor using Verilog

AIM: To realize Half Subtractor using Gate Level Description and Dataflow Description styles of Verilog CODE: GATE LEVEL DESCRIPTION: module Halsustr(a ,b ,di, bo); input a,b; output di,bo; wire w1; //Defining the Structural Code for Half Subtarctor xor x1(di,a,b); not n1(w1,a); and a1(bo,w1,b); endmodule DATAFLOW DESCRIPTION: module halsubdat(a ,b ,di ,bo); input a,b; output di,bo; wire w1; //Dataflow Description Code for Half Subtractor assign di= a ^ b; assign w1= ~(a); // Defining the output Difference using a xor b /* Defining the output Borrow using abar and b */
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//Defining the Difference //Defining the Borrow part

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assign bo= w1 & b; endmodule TESTBENCH: module testhalsub; reg a,b; wire di,bo; // Inputs // Outputs

// Instantiate the Unit Under Test (UUT) halsubdat uut (.a(a), .b(b), .di(di), .bo(bo)); initial begin // Initialize Inputs a = 0; b = 0; #100; // Wait 100 ns for global reset to finish a = 0; b = 1; #100; // Wait 100 ns for global reset to finish a = 1; b = 0; #100; // Wait 100 ns for global reset to finish a = 1; b = 1; end endmodule

SIMULATION:

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Experiment-5 Realization of Full Subtractor using Verilog

AIM: To realize Full Subtractor using Gate Level Description and Dataflow Description styles of Verilog CODE: GATE LEVEL DESCRIPTION: module fulsubst( a, b, c, di, bo); input a, b, c; output di,bo; wire w1,w2,w3,w4; xor x1(di,a,b,c); not n1(w1,a); and a1(w2,w1,b); and a2(w3,w1,c); and a3(w4,b,c); or o1(bo,w2,w3,w4); endmodule DATA FLOW DESCRIPTION: module fulsubda(a ,b ,c ,di ,bo); input a, b, c; output di, bo; wire w1,w2,w3,w4; //Data flow Code for Full Subtractor
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//Structural Code for Full Subtractor //Difference Output //Borrow Output

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assign di= ( a ^ b ^ c); assign w1= ~a; assign w2= (w1 & b); assign w3= (w1 & c); assign w4= (b & c); assign bo= (w2 | w3 | w4); endmodule TESTBENCH: module testfulsub; reg a; reg b; reg c; wire di; wire bo; // Outputs // Inputs

//Difference Part //Borrow Output

// Instantiate the Unit Under Test (UUT) fulsubda uut ( .a(a), .b(b), .c(c), initial begin // Initialize Inputs a = 0; b = 0; c = 0; #100; a = 0; b = 0; c = 1; #100; a = 0; b = 1; c = 0; #100; // Wait 100 ns for global reset to finish
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.di(di), .bo(bo) );

// Wait 100 ns for global reset to finish

// Wait 100 ns for global reset to finish

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a = 0; b = 1; c = 1; #100; a = 1; b = 0; c = 0; #100; a = 1; b = 0; c = 1; #100; a = 1; b = 1; c = 0; #100; a = 1; b = 1; c = 1; end endmodule // Wait 100 ns for global reset to finish // Wait 100 ns for global reset to finish // Wait 100 ns for global reset to finish // Wait 100 ns for global reset to finish

SIMULATION:

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Experiment-6 Realization of 2:1 Multiplexer using Verilog

AIM: To realize 2:1 Multiplexer using Gate Level Description and Dataflow Description styles of Verilog CODE: GATE LEVEL DESCRIPTION: module muxtoekstr(a , b, s, y); input a, b, s; output y; wire w1,w2,w3; //Multiplexer 2 to 1 in Structural Style not n1(w1,s); and a1(w2,w1,a); and a2(w3,s,b); or o1(y,w2,w3); endmodule

DATA FLOW DESCRIPTION: module mul2to1(a ,b ,s ,y); input a, b, s; output y; wire w1,w2,w3; // Dataflow code for Multiplexer 2 to 1
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assign w1 = ~s; assign w2 = a & w1 ; assign w3 = b & s ; assign y = w2 | w3 ; endmodule TEST BENCH: module testmux; reg a; reg b; reg s; wire y; // Outputs // Inputs

// Instantiate the Unit Under Test (UUT) mul2to1 uut (.a(a), .b(b), .s(s), .y(y) ); initial begin // Initialize Inputs a = 0; b = 0; s = 0; #100; a = 1; b = 0; s = 0; #100; a = 0; b = 0; s = 1; #100; a = 0; b = 1; s = 1; #100; a = 1; b = 1; s = 0;
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// Wait 100 ns for global reset to finish

// Wait 100 ns for global reset to finish

// Wait 100 ns for global reset to finish

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#100;

// Wait 100 ns for global reset to finish

a = 1; b = 1; s = 1; end endmodule

SIMULATION:

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Experiment-7 Realization of 4:1 Multiplexer using Verilog

AIM: To realize 4:1 Multiplexer using Gate Level Description and Dataflow Description styles of Verilog CODE: GATE LEVEL DESCRIPTION: module muxstrchartoek(a ,b ,c ,d ,s0 ,s1 ,y); input a,b ,c ,d ,s0 ,s1; output y; wire w1,w2,w3,w4,w5,w6; // Structural Modelling for 4 to 1 Mux not n1(w1,s0); not n2(w2,s1); and a1(w3,a,w1,w2); and a2(w4,b,w1,s1); and a3(w5,c,s0,w2); and a4(w6,d,s0,s1); or o1(y,w3,w4,w5,w6); endmodule DATAFLOW DESCRIPTION: module Datamuxchartoek(a ,b ,c ,d ,s0 ,s1 ,y); input a, b, c, d, s0, s1; output y;
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wire w1,w2,w3,w4,w5,w6; //Data Multiplexer for 4 to 1 assign w1 = ~s0; assign w2 = ~s1; assign w3 = (a & w1 & w2); assign w4 = (b & w1 & s1); assign w5 = (c & s0 & w1); assign w6 = (d & s0 & s1); assign y = (w3 | w4 | w5 | w6); endmodule TESTBENCH: module testmuxctoek; // Inputs reg a,b,c,d,s0,s1; // Outputs wire y; // Instantiate the Unit Under Test (UUT) Datamuxchartoek uut (.a(a), .b(b), .c(c), .d(d), .s0(s0), .s1(s1), .y(y) ); initial begin a = 0; b = 0; c = 0; d = 0; s0 = 0; s1 = 0; #100; // Wait 100 ns for global reset to finish

a = 1; b = 0; c = 0; d = 0; s0 = 0; s1 = 0; #100; // Wait 100 ns for global reset to finish

a = 0; b = 0; c = 0; d = 0; s0 = 0; s1 = 1;
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#100;

// Wait 100 ns for global reset to finish

a = 0; b = 1; c = 0; d = 0; s0 = 0; s1 = 1; #100; // Wait 100 ns for global reset to finish

a = 0; b = 0; c = 0; d = 0; s0 = 1; s1 = 0; #100; // Wait 100 ns for global reset to finish

a = 0; b = 0; c = 1; d = 0; s0 = 1; s1 = 0; #100; // Wait 100 ns for global reset to finish

a = 0; b = 0; c = 0; d = 0; s0 = 1; s1 = 1; #100; // Wait 100 ns for global reset to finish

a = 0; b = 0; c = 0; d = 1; s0 = 1; s1 = 1; end endmodule SIMULATION:

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Experiment-8a Realization of BCD TO EXCESS-3 Code Converter using Verilog

AIM: To realize BCD to EXCESS-3 Code Converter uaing Dataflow Description style of Verilog CODE: DATAFLOW DESCRIPTION: module bcdtoecxses(b0,b1,b2,b3,e0,e1,e2,e3); input b0,b1,b2,b3; output e0,e1,e2,e3; //Code assign e0 = (~b0); assign e1 = (b1~^b0); assign e2 = (b2&(~b1)&(~b0))|(~b2&b0)|(~b2&b1); assign e3 = (b3&(~b2))|(b0&b2)|(b1&b2); endmodule TESTBENCH: module testcodeconv; reg b0; reg b1; reg b2; reg b3; wire e0; wire e1; // Outputs // Inputs

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wire e2; wire e3; // Instantiate the Unit Under Test (UUT) bcdtoecxses uut ( .b0(b0), .b1(b1), .b2(b2), .b3(b3), .e0(e0), .e1(e1), .e2(e2), .e3(e3) ); initial begin // Initialize Inputs b0 = 0; b1 = 0; b2 = 0; b3 = 0; #100; // Wait 100 ns for global reset to finish

b0 = 1; b1 = 0; b2 = 0; b3 = 0; #100; b0 = 0; b1 = 1; b2 = 0; b3 = 0; #100; b0 = 1; b1 = 1; b2 = 0; b3 = 0; #100; b0 = 0; b1 = 0; b2 = 1; b3 = 0; #100; b0 = 1; b1 = 0; b2 = 1; b3 = 0; #100; b0 = 0; b1 = 1; b2 = 1; b3 = 0; #100; b0 = 1; b1 = 1; b2 = 1; b3 = 0; #100; b0 = 0; b1 = 0; b2 = 0; b3 = 1;

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#100; b0 = 1; b1 = 0; b2 = 0; b3 = 1; end endmodule

SIMULATION:

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Experiment-8b Realization of BCD TO GRAY Code Converter using Verilog

AIM: To realize BCD to Gray Code Converter using Dataflow Description style of Verilog CODE: DATAFLOW DESCRIPTION: module btogconv(b0,b1,b2,b3,g0,g1,g2,g3 ); input b0,b1,b2,b3; output g0,g1,g2,g3; //Code assign g3 = b3; assign g2 = b3 ^ b2; assign g1 = b2 ^ b1; assign g0 = b1 ^ b0; endmodule TESTBENCH: module testbtog; // Inputs reg b0; reg b1; reg b2; reg b3; // Outputs

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wire g0; wire g1; wire g2; wire g3; // Instantiate the Unit Under Test (UUT) btogconv uut ( .b0(b0), .b1(b1), .b2(b2), .b3(b3), .g0(g0), .g1(g1), .g2(g2), .g3(g3) ); initial begin // Initialize Inputs b0 = 0; b1 = 0; b2 = 0; b3 = 0; #100; // Wait 100 ns for global reset to finish

b0 = 1; b1 = 0; b2 = 0; b3 = 0; #100; b0 = 0; b1 = 1; b2 = 0; b3 = 0; #100; b0 = 1; b1 = 1; b2 = 0; b3 = 0; #100; b0 = 0; b1 = 0; b2 = 1; b3 = 0; #100; b0 = 1; b1 = 0; b2 = 1; b3 = 0; #100; b0 = 0; b1 = 1; b2 = 1; b3 = 0; #100; b0 = 1; b1 = 1; b2 = 1; b3 = 0;

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#100; b0 = 0; b1 = 0; b2 = 0; b3 = 1; #100; b0 = 1; b1 = 0; b2 = 0; b3 = 1; #100; b0 = 0; b1 = 1; b2 = 0; b3 = 1; #100; b0 = 1; b1 = 1; b2 = 0; b3 = 1; #100; b0 = 0; b1 = 0; b2 = 1; b3 = 1; #100; b0 = 1; b1 = 0; b2 = 1; b3 = 1; #100; b0 = 0; b1 = 1; b2 = 1; b3 = 1; #100; b0 = 1; b1 = 1; b2 = 1; b3 = 1; end endmodule

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SIMULATION:

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Experiment-9a Realization of SR Flip Flop using Verilog

AIM: To realize SR Flip Flop using Behavioral Description style of Verilog CODE: BEHAVIORAL DESCRIPTION: module srflipflo(r,s,clk,q ); input r,s,clk; output q; reg q; //Behavioral Description always @ (posedge clk) if(r==0 & s==1)begin q=1; end else if(r==0 & s==0)begin q<=q; end else if(r==1 & s==0)begin q=0; end else begin q=1'bz;

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end endmodule TESTBENCH: module testsrfliflo; // Inputs reg r; reg s; reg clk; // Outputs wire q; // Instantiate the Unit Under Test (UUT) srflipflo uut (.r(r), .s(s), .clk(clk), .q(q) ); initial begin clk=1; #100 $finish; end always #10 clk=~clk; initial begin r=0; #20 r=~r; #40 r=~r; end initial begin
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s=1; #20 s=~s; #40 s=~s; #60 s=~s; end endmodule SIMULATION:

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Experiment-9b Realization of D Flip Flop using Verilog

AIM: To realize D Flip Flop using Behavioral Description style of Verilog CODE: BEHAVIORAL DESCRIPTION: module dflflo(d,clk,q); input d,clk; output q; reg q; //Code always @ (posedge clk) begin if (d==0) begin q=0; end else begin q = 1; end end endmodule TESTBENCH: module testdflflo;

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// Inputs reg d; reg clk; // Outputs wire q; // Instantiate the Unit Under Test (UUT) dflflo uut (.d(d), .clk(clk), .q(q)); initial begin clk=1; #60 $finish; end always #10 clk=~clk; initial begin d=0; #20 d=~d; #10 d=~d; #10 d=~d; end endmodule

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SIMULATION:

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Experiment-9c Realization of JK Flip Flop using Verilog

AIM: To realize JK Flip Flop using Behavioral Description style of Verilog CODE: BEHAVIORAL DESCRIPTION: module jkfloflli(j,k,clk,q); input j,k,clk; output q; reg q; //Code always @ (posedge clk) if(k==0 & j==1)begin q=1; end else if(k==0 & j==0)begin q<=q; end else if(k==1 & j==0)begin q=0; end else begin q<=~q;

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end endmodule TESTBENCH: module testjkfliflo; // Inputs reg j; reg k; reg clk; // Outputs wire q; // Instantiate the Unit Under Test (UUT) jkfloflli uut (.j(j), .k(k), .clk(clk), .q(q)); initial begin clk=1; #60 $finish; end always #10 clk=~clk; initial begin k=0; #20 k=~k; #40 k=~k; end initial begin
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j=1; #20 j=~j; #40 j=~j; #60 j=~j; end endmodule SIMULATION:

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Experiment-9d Realization of T Flip Flop using Verilog

AIM: To realize T Flip Flop using Behavioral Description style of Verilog CODE: BEHAVIORAL DESCRIPTION: module tflofli( t,clk, q ); input t,clk; output q; reg q; //Code always @ (posedge clk) begin if (t==0) begin q=1; end else begin q = 0; end end endmodule TESTBENCH: module testtflflo; // Inputs

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reg t; reg clk; // Outputs wire q; // Instantiate the Unit Under Test (UUT) tflofli uut (.t(t), .clk(clk), .q(q)); initial begin clk=1; #60 $finish; end always #10 clk=~clk; initial begin t=0; #20 t=~t; #5 t=~t; #10 t=~t; end endmodule

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SIMULATION:

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Experiment-10a Realization of MOD-13 Counter using Verilog

AIM: To realize mod-13 Counter using Behavioral Description style of Verilog CODE: BEHAVIORAL DESCRIPTION: module modte(clk,reset,Q ); input clk,reset; output [3:0] Q; reg [3:0] Q; //CODE always @ (posedge clk) begin if (~reset) begin if(Q==4'b1100) begin Q<= 4'b0; end else begin Q<= Q+1; end end end always @(posedge reset) begin Q<= 4'b0000;

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end endmodule TESTBENCH: module testmodte; // Inputs reg clk; reg reset; // Outputs wire [3:0]Q; // Instantiate the Unit Under Test (UUT) modte uut (.clk(clk), .reset(reset), .Q(Q)); initial begin forever begin clk <= 0; #5 clk <= 1; #5 clk <= 0; end end initial begin reset = 1; #12 reset = 0;
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#170 reset = 1; #12 reset = 0; end endmodule SIMULATION:

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Experiment-10b Realization of MOD-5 Counter using Verilog

AIM: To realize mod-5 Counter using Behavioral Description style of Verilog CODE: BEHAVIORAL DESCRIPTION: module modteencoun(clk, reset, Q ); input clk,reset; output [2:0] Q; reg [2:0] Q; //Code always @(posedge clk)begin if(~reset) begin if(Q == 3'b100) begin Q <= 3'b0; end else begin Q <= end end end always @ (posedge reset) begin Q <= 3'b000; Q+1;

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end endmodule TESTBENCH: module testmodteen; // Inputs reg clk; reg reset; // Outputs wire [2:0] Q; // Instantiate the Unit Under Test (UUT) modteencoun uut ( .clk(clk), .reset(reset), .Q(Q)); initial begin forever begin clk <= 0; #5 clk <= 1; #5 clk <= 0; end end initial begin reset = 1; #12 reset = 0;
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#170 reset = 1; #12 reset = 0; end endmodule SIMULATION:

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Experiment-11 Realization of 4-Bit Magnitude Comparator using Verilog

AIM: To realize 4-Bit Magnitude Comparator using Dataflow Description style of Verilog CODE: DATAFLOW DESCRIPTION: module charbitcomp(A,B,x,y,z); input [3:0] A,B; output x,y,z; //Code assign x=(A>B); assign y=(A==B); assign z=(A<B); endmodule TESTBENCH: module testcomp; // Inputs reg [3:0] A; reg [3:0] B; // Outputs wire x; wire y; wire z;

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// Instantiate the Unit Under Test (UUT) charbitcomp uut ( .A(A), .B(B), .x(x), .y(y), .z(z)); initial begin // Initialize Inputs A = 0000; #100; A = 0000; #100; A = 0010; #100; A = 1000; end endmodule B = 1001; B = 0001; B = 0000; // Wait 100 ns for global reset to finish B = 0001;

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SIMULATION:

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