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INDEX CHAPTER 1. INTRODUCTION 3 CHAPTER 2. DESCRIPTION OF HARDWARE COMPONENTS 2.1 AT89S52 28 2.1.1 Introduction to AT89S52 2.1.2 Features 2.1.

3 Architectural overview 2.1.4 Pin description for AT89S52 2.1.5 Memories 2.1.1. ZIG-BEE MODULES 2.2 POWER SUPPLY 2.2.1 Introduction 2.2.2Regulator 2.4 SERIAL COMMUNICATION 2.8 DC MOTOR CHAPTER 3: CIRCUIT AND OPERATION 82 3.1 Circuit diagram 3.2 Operation of circuit CHAPTER 5: SOFTWARE DEVELOPMENT 5.1 Introduction 5.2 Tools used 5.3 C51 Compiler & A51 macro assembler
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5.4 Start vision 5.5 over view of Keil cross compiler 5.6 Benefits of Keil compiler 5.7 Flashmagic 5.8 Source code 5.9 Flowchart

CHAPTER 6: RESULTS AND CONCLUSION 6.1 Advantages 6.2 Disadvantages 6.3 Applications 6.4 Conclusion REFERENCES

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The XBee/XBee-PRO ZNET2.5 OEM(formerly known as series 2 and series 2 PRO) RF Modules were engineered to operate within the ZigBee protocol and support the unique needs of low-cost,low-power wireless sensor networks.The modules require minimal power reliable delivery of data between remote devices. Project Description: The project XBEE BASED AUTOMATION SYSTEM system is an exclusive project which allows the user to switch the different loads for the industry or home and when ever a signal triggers the modem sends the commands to the respective department by sending messages to the controlling
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system,and the receiving system decodes the signal and switches on the respective load and similarly for off condition. A modem provides the communication interface.It transports device protocols transparently over the network through a serial interface. A wireless modem behaves like a dial-up modem. The main difference between them is that a dial-up modem sends and receives data through a fixed telephone line while a wireless modem sends and receives data through radio waves. The XBEE modem will be interfaced to the microcontroller section through serial port interface. The controller section will be controlled by the controller i.e., to the microcontroller section.The microcontroller in return,sends a message to the receiver about the status of all the loads. HARDWARE REQUIREMENTS 1. 2. 3. 4. . 7. DCMOTORS AT89S52 CONTROLLER ZIG-BEE MODULES MAX232. POWER SUPPLY.


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Microprocessor has following instructions to perform: 1. Reading instructions or data from program memory ROM. 2. Interpreting the instruction and executing it. 3. Microprocessor Program is a collection of instructions stored in a nonvolatile memory.
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4. Read Data from I/O device 5. Process the input read, as per the instructions read in program memory. 6. Read or write data to Data memory. 7. Write data to I/O device and output the result of processing to O/P device. NECESSITY OF MICROCONTROLLERS: Microprocessors brought the concept of programmable devices and made many applications of intelligent equipment. Most applications, which do not need large amount of data and program memory, tended to be costly. The microprocessor system had to satisfy the data and program requirements so, sufficient RAM and ROM are used to satisfy most applications .The peripheral control equipment also had to be satisfied. Therefore, almost allperipheral chips were used in the design. Because of these additional peripherals cost will be comparatively high. An example: 8085 chip needs: An Address latch for separating address from multiplex address and data.32-KB RAM and 32-KB ROM to be able to satisfy most applications. As also Timer / Counter, Parallel programmable port, Serial port, and Interrupt controller are needed for its efficient applications. In comparison a typical Micro controller 8051 chip has all that the 8051 board has except a reduced memory as follows. 4K bytes of ROM as compared to 32-KB, 128 Bytes of RAM as compared to 32-KB. Bulky:

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On comparing a board full of chips (Microprocessors) with one chip with all components in it (Micro controller). Debugging: Lots of Microprocessor circuitry and program to debug. In Micro controller there is no Microprocessor circuitry to debug. Slower Development time: As we have observed Microprocessors need a lot of debugging at board level and at program level, where as, Micro controller do not have the excessive circuitry and the built-in peripheral chips are easier to program for operation. So peripheral devices like Timer/Counter, Parallel programmable port, Serial Communication Port, Interrupt controller and so on, which were most often used were integrated with the Microprocessor to present the Micro controller .RAM and ROM also were integrated in the same chip. The ROM size was anything from 256 bytes to 32Kb or more. RAM was optimized to minimum of 64 bytes to 256 bytes or more. 2.1.2 FEATURES Typical Micro controller has all the following features: 8/16/32 CPU Instruction set rich in I/O & bit operations. One or more I/O ports. One or more timer/counters. One or more interrupt inputs and an interrupt controller One or more serial communication ports. Analog to Digital /Digital to Analog converter One or more PWM output
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Network controlled interface Why AT89S52? The system requirements and control specifications clearly rule out the use of 16, 32 or 64 bit micro controllers or microprocessors. Systems using these may be earlier to implement due to large number of internal features. They are also faster and more reliable but, the above application is satisfactorily served by 8-bit micro controller. Using an inexpensive 8-bit Microcontroller will doom the 32-bit product failure in any competitive market place. Coming to the question of why to use 89S52 of all the 8-bit Microcontroller available in the market the main answer would be because it has 64 kB Flash and 1024 bytes of data RAM. . The Flash program memory supports both parallel programming and in Serial In-System Programming (ISP). The 89S52 is also In-Application Programmable (IAP), allowing the Flash program memory to be reconfigured even while the application is running.

2.1.3 ARCHITECTURE OVERVIEW 8051 micro controller architecture: The 8051 architecture consists of these specific features: Eight bit CPU with registers A (the accumulator) and B Sixteen-bit program counter (PC) and data pointer (DPTR) Eight- bit stack pointer (PSW) Eight-bit stack pointer (Sp) Internal ROM or EPROM (8751) of 0(8031) to 4K (8051) Internal RAM of 128 bytes: 1. Four register banks, each containing eight registers 2. Sixteen bytes, which maybe addressed at the bit level
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3. Eighty bytes of general- purpose data memory Thirty two input/output pins arranged as four 8-bit ports:p0-p3 Two 16-bit timer/counters: T0 and T1 Full duplex serial data receiver/transmitter: SBUF Control registers: TCON, TMOD, SCON, PCON, IP, and IE Two external and three internal interrupts sources. Oscillator and clock circuits.


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VCC : Supply voltage. GND: Ground. Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. W hen 1s are written to port 0 pins, the pins can be used as high- impedance inputs. Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external pro-gram and data m em ory. In this mode, P0 has internal pullups Port 0 also receives the code bytes during Flash program- mi ng an d ou tpu t s t he c o de b y t es du r i n g pr o g r a m verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification
Port Pin P1.0 P1.1 Alternate Functions T2 (external count input to Timer/Counter 2), clock-out T2EX (Timer/Counter 2 capture/reload trigger and direction control)

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Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pul- lups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for Flash pro- gramming and verification.

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Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RST

Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write RD (external data memory read

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external mem- ory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only dur-ing a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode.

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FIG-3 Functional block diagram of micro controller

The 8052 Oscillator and Clock: The heart of the 8051 circuitry that generates the clock pulses by w hich all the internal all internal operations are synchronized. Pins X TA L 1 A n d X TA L 2 i s p r o v i d e d f o r c o n n e c t i n g a r e s o n a n t n e t w o r k t o f o r m a n o s c i l l a t o r. Ty p i c a l l y a q u a rt z c r y s t a l a n d c a p a c it o r s a r e e m p l o y e d . T h e c r y s t a l f re q u e n c y i s t h e b a s i c i n t e r n a l c l o c k f r e q u e n c y o f t h e
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m i c r o c o n t r o l l e r. T h e m a n u f a c t u r e r s m a k e 8 0 5 1 d e s i g n s t h a t r u n a t s p e c i f i c m inim u m and m axim um frequencies typically 1 to 16 M H z.

Fig-4 Oscillator and timing circuit

2.1.5 MEMORIES Types of memory:

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The 8052 have three general types of memory. They are on-chip memory, external Code memory and external Ram. On-Chip memory refers to physically existing memory on the micro controller itself. External code memory is the code memory that resides off chip. This is often in the form of an external EPROM. External RAM is the Ram that resides off chip. This often is in the form of standard static RAM or flash RAM. a) Code memory Code memory is the memory that holds the actual 8052 programs that is to be run. This memory is limited to 64K. Code memory may be found on-chip or off-chip. It is possible to have 8K of code memory on-chip and 60K off chip memory simultaneously. If only off-chip memory is available then there can be 64K of off chip ROM. This is controlled by pin provided as EA. b) Internal RAM The 8052 have a bank of 256 bytes of internal RAM. The internal RAM is found on-chip. So it is the fastest Ram available. And also it is most flexible in terms of reading and writing. Internal Ram is volatile, so when 8051 is reset, this memory is cleared. 256 bytes of internal memory are subdivided. The first 32 bytes are divided into 4 register banks. Each bank contains 8 registers. Internal RAM also contains 256 bits, which are addressed from 20h to 2Fh. These bits are bit addressed i.e. each individual bit of a byte can be addressed by the user. They are numbered 00h to FFh. The user may make use of these variables with commands such as SETB and CLR. Special Function registered memory: Special function registers are the areas of memory that control specific functionality of the 8052 micro controller. a) Accumulator (0E0h)
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As its name suggests, it is used to accumulate the results of large no of instructions. It can hold 8 bit values. b) B registers (0F0h) The B register is very similar to accumulator. It may hold 8-bit value. The b register is only used by MUL AB and DIV AB instructions. In MUL AB the higher byte of the product gets stored in B register. In div AB the quotient gets stored in B with the remainder in A. c) Stack pointer (81h) The stack pointer holds 8-bit value. This is used to indicate where the next value to be removed from the stack should be taken from. When a value is to be pushed onto the stack, the 8052 first store the value of SP and then store the value at the resulting memory location. When a value is to be popped from the stack, the 8052 returns the value from the memory location indicated by SP and then decrements the value of SP. d) Data pointer The SFRs DPL and DPH work together work together to represent a 16bit value called the data pointer. The data pointer is used in operations regarding external RAM and some instructions code memory. It is a 16-bit SFR and also an addressable SFR. e) Program counter The program counter is a 16 bit register, which contains the 2 byte address, which tells the 8052 where the next instruction to execute to be found in memory. When the 8052 is initialized PC starts at 0000h. And is incremented each time an instruction is executes. It is not addressable SFR. f) PCON (power control, 87h)
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The power control SFR is used to control the 8051s power control modes. Certain operation modes of the 8051 allow the 8051 to go into a type of sleep mode which consumes much lee power.

g) TCON (timer control, 88h) The timer control SFR is used to configure and modify the way in which the 8051s two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in TCON SFR. These bits are used to configure the way in which the external interrupt flags are activated, which are set when an external interrupt occurs.

h) TMOD (Timer Mode, 89h) The timer mode SFR is used to configure the mode of operation of each of the two timers. Using this SFR your program may configure each timer to be a 16-bit timer, or 13 bit timer, 8-bit auto reload timer, or two separate timers. Additionally you may configure the timers to only count when an external pin is activated or to count events that are indicated on an external pin.

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i) TO (Timer 0 low/high, address 8A/8C h) These two SFRs taken together represent timer 0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value. j) T1 (Timer 1 Low/High, address 8B/ 8D h) These two SFRs, taken together, represent timer 1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up.. k) P0 (Port 0, address 90h, bit addressable) This is port 0 latch. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port 0 is pin P0.0, bit 7 is pin p0.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level. l) P1 (port 1, address 90h, bit addressable) This is port latch1. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port 0 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level

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m) P2 (port 2, address 0A0h, bit addressable): This is a port latch2. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port 0 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level. n) P3 (port 3, address B0h, bit addressable) :

This is a port latch3. Each bit of this SFR corresponds to one of the pins on a micro controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0 of port 0 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to low level. o) IE (interrupt enable, 0A8h): The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where the MSB bit is used to enable or disable all the interrupts. Thus, if the high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt is enabled by setting a lower bit.

p) IP (Interrupt Priority, 0B8h) The interrupt priority SFR is used to specify the relative priority of each interrupt. On 8051, an interrupt maybe either low or high priority. An interrupt may interrupt interrupts. For e.g., if we configure all interrupts as low priority other than serial interrupt. The serial interrupt always interrupts the system, even if another interrupt is currently executing. However, if a serial interrupt is
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executing no other interrupt will be able to interrupt the serial interrupt routine since the serial interrupt routine has the highest priority.

q) PSW (Program Status Word, 0D0h) The program Status Word is used to store a number of important bits that are set and cleared by 8052 instructions. The PSW SFR contains the carry flag, the auxiliary carry flag, the parity flag and the overflow flag. Additionally, it also contains the register bank select flags, which are used to select, which of the R register banks currently in use.

r) SBUF (Serial Buffer, 99h) SBUF is used to hold data in serial communication. It is physically two registers. One is writing only and is used to hold data to be transmitted out of 8052 via TXD. The other is read only and holds received data from external sources via RXD. Both mutually exclusive registers use address 99h. I/O ports: One major feature of a microcontroller is the versatility built into the input/output (I/O) circuits that connect the 8052 to the outside world. The main constraint that limits numerous functions is the number of pins available in the 8051 circuit. The DIP had 40 pins and the success of the design depends on the flexibility incorporated into use of these pins. For this reason, 24 of the pins may each used for one of the two entirely different functions which depend, first, on what is physically connected to it and, then, on what software programs are used to program the pins.
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PORT 0 Port 0 pins may serve as inputs, outputs, or, when used together, as a bi directional low-order address and data bus for external memory. To configure a pin as input, 1 must be written into the corresponding port 0 latch by the program. When used for interfacing with the external memory, the lower byte of address is first sent via PORT0, latched using Address latch enable (ALE) pulse and then the bus is turned around to become the data bus for external memory. PORT 1 Port 1 is exclusively used for input/output operations. PORTS 1 pin have no dual function. When a pin is to be configured as input, 1 is to be written into the corresponding Port 1 latch. PORT 2 Port 2 maybe used as an input/output port. It may also be used to supply a high order address byte in conjunction with Port 0 low-order byte to address external memory. Port 2 pins are momentarily changed by the address control signals when supplying the high byte a 16-bit address. Port 2 latches remain stable when external memory is addressed, as they do not have to be turned around (set to 1) for data input as in the case for Port 0. PORT 3 Port 3 may be used to input /output port. The input and output functions can be programmed under the control of the P3 latches or under the control of various special function registers. Unlike Port 0 and Port 2, which can have external addressing functions and change all eight-port b se, each pin of port 3 maybe individually programmed to be used as I/O or as one of the alternate functions. The Port 3 alternate uses are: Pin (SFR) P3.0-RXD (SBUF) P3.1-TXD (SBUF)
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Alternate Use Serial data input Serial data output

P3.2-INTO 0 (TCON.1) P3.4 - T0 (TMOD) P3.5 T1 (TMOD) P3.6 - WR P3.7 - RD

External interrupt 0 External Timer 0 input External timer 1 input External memory write pulse External memory read pulse

P3.3 - INTO 1 (TCON.3) External interrupt 1

INTERRUPTS: Interrupts are hardware signals that are used to determine conditions that exist in external and internal circuits. Any interrupt can cause the 8051 to perform a hardware call to an interrupt handling subroutine that is located at a predetermined absolute address in the program memory. Five interrupts are provided in the 8051. Three of these are generated automatically by the internal operations: Timer flag 0, Timer Flag 1, and the serial port interrupt (RI or TI) Two interrupts are triggered by external signals provided by the circuitry that is connected to the pins INTO 0 and INTO1. The interrupts maybe enable or disabled, given priority or otherwise controlled by altering the bits in the Interrupt Enabled (IE) register, Interrupt Priority (IP) register, and the Timer Control (TCON) register. . These interrupts are mask able i.e. they can be disabled. Reset is a non mask able interrupt which has the highest priority. It is generated when a high is applied to the reset pin. Upon reset, the registers are loaded with the default values. Each interrupt source causes the program to do store the address in PC onto the stack and causes a hardware call to one of the dedicated addresses in the program memory. The appropriate memory locations for each for each interrupt are as follows:
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Interrupt RESET IE0 (External interrupt 0) TF0 (Timer 0 interrupt) IE1 (External interrupt 1) TF1 (Timer 1 interrupt) SERIAL

Address 0000 0003 000B 0013 001B 0023


ZigBee is the name of a specification for a suite of high level communication protocols using small, low-power, low data rate digital radios based on the IEEE 802.15.4 standard for wireless personal area networks (WPANs), such as wireless headphones connecting with cell phones via short-range radio. The technology is intended to be simpler and cheaper than other WPANs, such as Bluetooth. ZigBee is targeted at radio-frequency (RF) applications which require a low data rate, long battery life, and secure networking. ZigBee is a low data rate, two-way standard for home automation and data networks. The standard specification for up to 254 nodes including one master, managed from a single remote control. Real usage examples of ZigBee includes home automation tasks such as turning lights on, setting the home security system, or starting the VCR. With ZigBee all these tasks can be done from
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anywhere in the home at the touch of a button. ZigBee also allows for dial-in access via the Internet for automation control. The ZigBee standard uses small very low-power devices to connect together to form a wireless control web. A ZigBee network is capable of supporting up to 254 client nodes plus one full functional device (master). ZigBee protocol is optimized for very long battery life measured in months to years from inexpensive, off-the-shelf non-rechargeable batteries, and can control lighting, air conditioning and heating, smoke and fire alarms, and other security devices. The standard supports 2.4 GHz (worldwide), 868 MHz (Europe) and 915 MHz (Americas) unlicensed radio bands with range up to 75 meters. IEEE 802.15.4 IEEE 802.15.4 is a standard which specifies the physical layer and medium access control for low-rate wireless personal area networks (LRWPAN's).This standard was chartered to investigate a low data rate solution with multi-month to multi-year battery life and very low complexity. It is operating in an unlicensed, international frequency band. Potential applications are sensors, interactive toys, smart badges, remote controls, and home automation.

802.15.4 Is part of the 802.15 wireless personal-area network effort at the IEEE? It is a simple packet-based radio protocol aimed at very low-cost, battery-operated widgets and sensors (whose batteries last years, not hours) that can intercommunicate and send low-bandwidth data to a centralized device. As of 2007, the current version of the standard is the 2006 revision. It is maintained by the IEEE 802.15 working group.

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It is the basis for the ZigBee specification, which further attempts to offer a complete networking solution by developing the upper layers which are not covered by the standard 802.15.4 Protocol

Data rates of 250 kbps with 10-100 meter range. Two addressing modes; 16-bit short and 64-bit IEEE addressing. Support for critical latency devices, such as joysticks. CSMA-CA channel access. Automatic network establishment by the coordinator. Fully handshaked protocol for transfer reliability. Power management to ensure low power consumption. 16 channels in the 2.4GHz ISM band Low duty cycle - Provides long battery life Low latency Support for multiple network topologies: Static, dynamic, star and mesh Direct Sequence Spread Spectrum (DSSS) Up to 65,000 nodes on a network 128-bit AES encryption Provides secure connections between devices

ZigBee Applications ZigBee enables broad-based deployment of wireless networks with low-cost, low-power solutions. It provides the ability to run for years on inexpensive batteries for a host of monitoring applications: Lighting controls, AMR (Automatic Meter Reading), smoke and CO detectors, wireless telemetry, HVAC control, heating control, home security, Environmental controls and shade controls, etc.

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Standard Transmission Range (meters) Battery Life (days) Network Size (# of nodes) Application Stack Size (KB) Throughput kb/s)

ZigBee 802.15.4 1 100* 100 1,000 > 64,000 Monitoring & Control 4 32 20 250

Wi-Fi 802.11b 1 - 100 0.5 5.0 32 Web, Email, Video 1,000 11,000

Bluetooth 802.15.1 1 10 1-7 7 Cable Replacement 250 720

Use Case Scenario When installed in house it just gets control over all the electronic devices.so one can control all the devices using a remote controller/system/cellphone basing on ones requirement we can extend this project by small modules. It allows flexibility and authority over electronics in our home & make us efficient in power saving which inturn reduces cost over its consumption green effect.

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Zigbee stack architecture

ZigBee stack architecture It may be helpful to think of IEEE 802.15.4 as the physical radio and ZigBee as the logical network and application software, as Figure 1 illustrates. Following the standard Open Systems Interconnection (OSI) reference model, ZigBee's protocol stack is structured in layers. The first two layers, physical (PHY) and media access (MAC), are defined by the IEEE 802.15.4 standard. The layers above them are defined by the ZigBee Alliance. The IEEE working group passed the first draft of PHY and MAC in 2003. A final version of the network (NWK) layer is expected sometime this year. ZigBee-compliant products operate in unlicensed bands worldwide, including 2.4GHz (global), 902 to 928MHz (Americas), and 868MHz (Europe). Raw data throughput rates of 250Kbps can be achieved at 2.4GHz (16 channels), 40Kbps at 915MHz (10 channels), and 20Kbps at 868MHz (1 channel). The transmission distance is expected to range from 10 to 75m, depending on power output and environmental characteristics. Like Wi-Fi, Zigbee uses direct-sequence spread spectrum in the 2.4GHz band, with offset[Type text]

quadrature phase-shift keying modulation. Channel width is 2MHz with 5MHz channel spacing. The 868 and 900MHz bands also use direct-sequence spread spectrum but with binary-phase-shift keying modulation. Frame structure Figure 2 illustrates the four basic frame types defined in 802.15.4: data, ACK, MAC command, and beacon.

The data frame provides a payload of up to 104 bytes. The frame is numbered to ensure that all packets are tracked. A frame-check sequence ensures that packets are received without error. This frame structure improves reliability in difficult conditions. Another important structure for 802.15.4 is the acknowledgment (ACK) frame. It provides feedback from the receiver to the sender confirming that the packet was received without error. The device takes advantage of specified "quiet

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time" between frames to send a short packet immediately after the data-packet transmission. A MAC command frame provides the mechanism for remote control and configuration of client nodes. A centralized network manager uses MAC to configure individual clients' command frames no matter how large the network. Finally, the beacon frame wakes up client devices, which listen for their address and go back to sleep if they don't receive it. Beacons are important for mesh and cluster-tree networks to keep all the nodes synchronized without requiring those nodes to consume precious battery energy by listening for long periods of time. Channel access, addressing Two channel-access mechanisms are implemented in 802.15.4. For a nonebeacon network, a standard CSMA-CA (carrier-sense medium-access with collision avoidance) communicates with positive acknowledgement for successfully received packets. In a beacon-enabled network, a super frame structure is used to control channel access. The super frame is set up by the network coordinator to transmit beacons at predetermined intervals (multiples of 15.38ms, up to 252s) and provides 16 equal-width time slots between beacons for contention-free channel access in each time slot. The structure guarantees dedicated bandwidth and low latency. Channel access in each time slot is contention-based. However, the network coordinator can dedicate up to seven guaranteed time slots per beacon interval for quality of service. Device addresses employ 64-bit IEEE and optional 16-bit short addressing. The address field within the MAC can contain both source and destination address information (needed for peer-to-peer operation). This dual address information is used in mesh networks to prevent a single point of failure within the network.
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Networks A key component of the ZigBee protocol is the ability to support mesh networks. In a mesh network, nodes are interconnected with other nodes so that at least two pathways connect each node. Connections between nodes are dynamically updated and optimized in difficult conditions. In some cases, a partial mesh network is established with some of the nodes only connected to one other node. Mesh networks are decentralized in nature; each node is self-routing, self healing and able to connect to other nodes as needed. The characteristics of mesh topology and ad-hoc routing provide greater stability in changing conditions or failure at single nodes. The ZigBee specification identifies three kinds of devices that incorporate ZigBee radios, with all three found in a typical ZigBee network.

A coordinator, which organizes the network and maintains routing tables. Routers, which can talk to the coordinator, to other routers and to Reduced-function end devices, which can talk to routers and the

reduced-function end devices.

coordinator, but not to each other.

ZigBee network model

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In a star topology, one of the FFD/RFD-type devices assumes the role of network coordinator and is responsible for initiating and maintaining the devices on the network. All other devices, known as end devices, directly communicate with the coordinator. In a mesh topology, the ZigBee coordinator is responsible for starting the network and for choosing key network parameters, but the network may be extended through the use of ZigBee routers. The routing algorithm uses a request-response protocol to eliminate sub-optimal routing. Ultimate network size can reach 264 nodes (more than we'll probably need). Using local addressing, you can configure simple networks of more than 65,000 (216) nodes, thereby reducing address overhead. The General Operation Framework (GOF) is a glue layer between applications and rest of the protocol stack. The GOF currently covers various elements that are common for all devices. It includes sub addressing and addressing modes and device descriptions, such as type of device, power source, sleep modes, and coordinators. Using an object model, the GOF specifies methods, events, and data formats that are used by application profiles to construct set/get commands and their responses. Actual application profiles are defined in the individual profiles of the IEEE's working groups. Each ZigBee device can support up to 30 different profiles. Currently, only one profile, Commercial and Residential Lighting, is defined. It includes switching and dimming load controllers, corresponding remote-control devices, and occupancy and light sensors. The ZigBee stack is small in comparison to other wireless standards. For network-edge devices with limited capabilities, the stack requires about 4Kb of the memory. Full implementation of the protocol stack takes less than 32Kb of memory. The network coordinator may require extra RAM for a node devices
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database and for transaction and pairing tables. The 802.15.4 standard defines 26 primitives for the PHY and MAC layers; probably another dozen will be added after finalizing the NWK layer specification. Those numbers are still modest compared to 131 primitives defined for Bluetooth. Such a compact footprint enables you to run Zigbee on a simple 8-bit microcontroller such as an HC08- or 8051-based processor core. Secure Connections ZigBee leverages the security model of the IEEE 802.15.4 MAC sub layer which specifies four security services:

access controlthe device maintains a list of trusted devices within the Data encryption, which uses symmetric key 128-bit advanced encryption frame integrity to protect data from being modified by parties without sequential freshness to reject data frames that have been replayedthe


standard (AES).

cryptographic keys

network controller compares the freshness value with the last known value from the device and rejects it if the freshness value has not been updated to a new value The actual security implementation is specified by the implementer using a standardized toolbox of ZigBee security software. Power consumption Ultra-low power consumption is how ZigBee technology promotes a long lifetime for devices with non rechargeable batteries. ZigBee networks are designed to conserve the power of the slave nodes. For most of the time, a slave device is in deep-sleep mode and wakes up only for a fraction of a second to confirm its presence in the network. For example, the transition from sleep

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mode to data transition is around 15ms and new slave enumeration typically takes just 30ms. To minimize power consumption and promote long battery life in batterypowered devices, end devices can spend most of their time asleep, waking up only when they need to communicate and then going immediately back to sleep. ZigBee envisions that routers and the coordinator will be mains-powered and will not go to sleep. Zigbee benefits: In all of its uses, ZigBee offers four inherent, beneficial characteristics:

Low cost Range and obstruction issues avoidance Multi-source products Low power consumption

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2.2 Power supply: 2.2.1 Introduction to power supply There are many types of power supply. Most are designed to convert high voltage AC mains electricity to a suitable low voltage supply for electronics circuits and other devices. A power supply can by broken down into a series of blocks, each of which performs a particular function. For example a 5V regulated supply can be shown as below

2.2.5 Regulator: Regulator eliminates ripple by setting DC output to a fixed voltage. Voltage regulator ICs are available with fixed (typically 5V, 12V and 15V) or variable output voltages. Negative voltage regulators are also available.Many of the fixed voltage regulator ICs has 3 leads (input, output and high impedance). They include a hole for attaching a heat sink if necessary. Zener diode is an example of fixed regulator which is shown here.

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Figure 3.7 Regulator Transformer + Rectifier + Smoothing + Regulator:

pression) commands. .

2.3 Serial communication When a processor communicates with the outside world, it provides data in byte sized chunks. Computers transfer data in two ways: parallel and serial. In parallel data transfers, often more lines are used to transfer data to a device and 8 bit data path is expensive. The serial communication transfer uses only a single data line instead of the 8 bit data line of parallel communication which makes the data transfer not only cheaper but also makes it possible for two computers located in two different cities to communicate over telephone. Serial data communication uses two methods, asynchronous and synchronous. The synchronous method transfers data at a time while the asynchronous
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transfers a single byte at a time. There are some special IC chips made by many manufacturers for data communications. These chips are commonly referred to as UART (universal asynchronous receiver-transmitter) and USART (universal synchronous asynchronous receiver transmitter). The AT89C51 chip has a built in UART. In asynchronous method, each character is placed between start and stop bits. This is called framing. In data framing of asynchronous communications, the data, such as ASCII characters, are packed in between a start and stop bit. We have a total of 10 bits for a character: 8 bits for the ASCII code and 1 bit each for the start and stop bits. The rate of serial data transfer communication is stated in bps or it can be called as baud rate. To allow the compatibility among data communication equipment made by various manufacturers, and interfacing standard called RS232 was set by the Electronics industries Association in 1960. Today RS232 is the most widely used I/O interfacing standard. This standard is used in PCs and numerous types of equipment. However, since the standard was set long before the advent of the TTL logic family, its input and output voltage levels are not TTL compatible. In RS232, a 1 bit is represented by -3 to -25V, while a 0 bit is represented +3 to +25 V, making -3 to +3 undefined. For this reason, to connect any RS232 to a microcontroller system we must use voltage converters such as MAX232 to connect the TTL logic levels to RS232 voltage levels and vice versa. MAX232 ICs are commonly referred to as line drivers.

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The RS232 cables are generally referred to as DB-9 connector. In labeling, DB-9P refers to the plug connector (male) and DB-9S is for the socket connector (female). The simplest connection between a PC and microcontroller requires a minimum of three pin, TXD, RXD, and ground. Many of the pins of the RS232 connector are used for handshaking signals. They are bypassed since they are not supported by the 8051 UART chip.

IBM PC/ compatible computers based on x86(8086, 80286, 386, 486 and Pentium) microprocessors normally have two COM ports. Both COM ports have RS232 type connectors. Many PCs use one each of the DB-25 and DB-9 RS232 connectors. The COM ports are designated as COM1 and COM2. We can connect the serial port to the COM 2 port of a PC for serial communication experiments. We use a DB9 connector in our arrangement. The AT89C52 has two pins that are used specifically for transferring and receiving data serially. These two pins are called TXD and RXD and are part of the port3 (P3.0 and P3.1). These pins are TTL compatible; therefore they require a line driver to make them RS232 compatible. One such line driver is the MAX232 chip. One advantage of MAX232 chip is that it uses a +5v power source which is the same as the source voltage for the at89c51. The MAX232
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has two sets of line drivers for receiving and transferring data. The line drivers for TXD are called T1 and T2 while the line drivers for RXD are designated as R1 and R2. T1 and R1 are used for TXD and RXD of the 89c51 and the second set is left unused. In MAX232 that the TI line driver has a designation of T1 in and T1 out on pin numbers 11 and 14, respectively. The T1 in pin is the TTL side and is connected to TXD of the microcontroller, while TI out is the RS232 side that is connected to the RXD pin of the DB9 connector. To allow data transfer between PC and the microcontroller system without any error, we must make sure that the baud rate of the 8051 system matches the baud rate of the PCs COM port.

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2.7 DC MOTOR DC motors are configured in many types and sizes, including brush less, servo, and gear motor types. A motor consists of a rotor and a permanent magnetic field stator. The magnetic field is maintained using either permanent magnets or electromagnetic windings. DC motors are most commonly used in variable speed and torque. Motion and controls cover a wide range of components that in some way are used to generate and/or control motion. Areas within this category include bearings and bushings, clutches and brakes, controls and drives, drive components, encoders and resolves, Integrated motion control, limit switches, linear actuators, linear and rotary motion components, linear position sensing,
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motors (both AC and DC motors), orientation position sensing, pneumatics and pneumatic components, positioning stages, slides and guides, power transmission (mechanical), seals, slip rings, solenoids, springs. Motors are the devices that provide the actual speed and torque in a drive system. This family includes AC motor types (single and multiphase motors, universal, servo motors, induction, synchronous, and gear motor) and DC motors (brush less, servo motor, and gear motor) as well as linear, stepper and air motors, and motor contactors and starters. In any electric motor, operation is based on simple electromagnetism. A current-carrying conductor generates a magnetic field; when this is then placed in an external magnetic field, it will experience a force proportional to the current in the conductor, and to the strength of the external magnetic field. As you are well aware of from playing with magnets as a kid, opposite (North and South) polarities attract, while like polarities (North and North, South and South) repel. The internal configuration of a DC motor is designed to harness the magnetic interaction between a current-carrying conductor and an external magnetic field to generate rotational motion. Let's start by looking at a simple 2-pole DC electric motor (here red represents a magnet or winding with a "North" polarization, while green represents a magnet or winding with a "South" polarization).

Every DC motor has six basic parts -- axle, rotor (a.k.a., armature), stator, commutator, field magnet(s), and brushes. In most common DC motors (and all
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that Beamers will see), the external magnetic field is produced by high-strength permanent magnets1. The stator is the stationary part of the motor -- this includes the motor casing, as well as two or more permanent magnet pole pieces. The rotor (together with the axle and attached commutator) rotates with respect to the stator. The rotor consists of windings (generally on a core), the windings being electrically connected to the commutator. The above diagram shows a common motor layout -with the rotor inside the stator (field) magnets. The geometry of the brushes, commutator contacts, and rotor windings are such that when power is applied, the polarities of the energized winding and the stator magnet(s) are misaligned, and the rotor will rotate until it is almost aligned with the stator's field magnets. As the rotor reaches alignment, the brushes move to the next commutator contacts, and energize the next winding. Given our example two-pole motor, the rotation reverses the direction of current through the rotor winding, leading to a "flip" of the rotor's magnetic field, and driving it to continue rotating. In real life, though, DC motors will always have more than two poles (three is a very common number). In particular, this avoids "dead spots" in the commutator. You can imagine how with our example two-pole motor, if the rotor is exactly at the middle of its rotation (perfectly aligned with the field magnets), it will get "stuck" there. Meanwhile, with a two-pole motor, there is a moment where the commutator shorts out the power supply (i.e., both brushes touch both commutator contacts simultaneously). This would be bad for the power supply, waste energy, and damage motor components as well. Yet another disadvantage of such a simple motor is that it would exhibit a high amount of torque ripple" (the amount of torque it could produce is cyclic with the position of the rotor).

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So since most small DC motors are of a three-pole design, let's tinker with the workings of one via an interactive animation (JavaScript required):

You'll notice a few things from this -- namely, one pole is fully energized at a time (but two others are "partially" energized). As each brush transitions from one commutator contact to the next, one coil's field will rapidly collapse, as the next coil's field will rapidly charge up (this occurs within a few microsecond). We'll see more about the effects of this later, but in the meantime you can see that this is a direct result of the coil windings' series wiring:

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There's probably no better way to see how an average dc motor is put together, than by just opening one up. Unfortunately this is tedious work, as well as requiring the destruction of a perfectly good motor.\ CHAPTER 3 CIRCUIT AND OPERATION

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5 SOFTWARE DEVELOPMENT 5.1 Introduction: In this chapter the software used and the language in which the program code is defined is mentioned and the program code dumping tools are explained. The chapter also documents the development of the program for the application. This program has been termed as Source code. Before we look at the source code we define the two header files that we have used in the code. 5.2 Tools Used:

Figure 4.1 Keil Software- internal stages

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Keil development tools for the 8051 Microcontroller Architecture support every level of software developer from the professional applications 5.3 C51 Compiler & A51 Macro Assembler: Source files are created by the Vision IDE and are passed to the C51 Compiler or A51 Macro Assembler. The compiler and assembler process source files and create replaceable object files. The Keil C51 Compiler is a full ANSI implementation of the C programming language that supports all standard features of the C language. In addition, numerous features for direct support of the 8051 architecture have been added. 5.4VISION

What's New in Vision3? Vision3 adds many new features to the Editor like Text Templates, Quick Function Navigation, and Syntax Coloring with brace high lighting Configuration Wizard for dialog based startup and debugger setup. Vision3 is fully compatible to Vision2 and can be used in parallel with Vision2. What is Vision3? Vision3 is an IDE (Integrated Development Environment) that helps you write, compile, and debug embedded programs. It encapsulates the following components:

A project manager. A make facility. Tool configuration. Editor. A powerful debugger.

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To help you get started, several example programs (located in the \C51\Examples, \C251\Examples, \C166\Examples, and \ARM\...\Examples) are provided.

HELLO is a simple program that prints the string "Hello World" using the Serial Interface. MEASURE is a data acquisition system for analog and digital systems. TRAFFIC is a traffic light controller with the RTX Tiny operating system. SIEVE is the SIEVE Benchmark. DHRY is the Dhrystone Benchmark. WHETS is the Single-Precision Whetstone Benchmark.

Additional example programs not listed here are provided for each device architecture. 7.3 BUILDING AN APPLICATION IN VISION To build (compile, assemble, and link) an application in Vision2, you must:

Select Project -(forexample,166\EXAMPLES\HELLO\HELLO.UV2). Vision2 compiles, assembles, and links the files in your project.

2. Select Project - Rebuild all target files or Build target.

Creating Your Own Application in Vision2 To create a new project in Vision2, you must: 1. Select Project - New Project. 2. Select a directory and enter the name of the project file.

Select Project - Select Device and select an 8051, 251, or C16x/ST10 device from the Device Database.

4. Create source files to add to the project.

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5. Select Project - Targets, Groups, Files. Add/Files, select Source Group1, and add the source files to the project.

Select Project - Options and set the tool options. Note when you select the target device from the Device Database all special options are set automatically. You typically only need to configure the memory map of your target hardware. Default memory model settings are optimal for most applications.

7. Select Project - Rebuild all target files or Build target. Debugging an Application in Vision2 To debug an application created using Vision2, you must: 1. Select Debug - Start/Stop Debug Session.

Use the Step toolbar buttons to single-step through your program. You may enter G, main in the Output Window to execute to the main C function. Open the Serial Window using the Serial #1 button on the toolbar.


Debug your program using standard options like Step, Go, Break, and so on. Starting Vision2 and Creating a Project Vision2 is a standard Windows application and started by clicking on the program icon. To create a new project file select from the Vision2 menu Project New Project. This opens a standard Windows dialog that asks you for the new project file name. We suggest that you use a separate folder for each project. You can simply use the icon Create New Folder in this dialog to get a new empty folder. Then select this folder and enter the file name for the new project, i.e. Project1.

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Vision2 creates a new project file with the name PROJECT1.UV2 which contains a default target and file group name. You can see these names in the Project Window Files. Now use from the menu Project Select Device for Target and select a CPU for your project. The Select Device dialog box shows the Vision2 device database. Just select the microcontroller you use. We are using for our examples the Philips 80C51RD+ CPU. This selection sets necessary tool options for the 80C51RD+ device and simplifies in this way the tool Configuration Building Projects and Creating a HEX Files Typical, the tool settings under Options Target are all you need to start a new application. You may translate all source files and line the application with a click on the Build Target toolbar icon. When you build an application with syntax errors, Vision2 will display errors and warning messages in the Output Window Build page. A double click on a message line opens the source file on the correct location in a Vision2 editor window. Once you have successfully generated your application you can start debugging. After you have tested your application, it is required to create an Intel HEX file to download the software into an EPROM programmer or simulator. Vision2 creates HEX files with each build process when Create HEX files under Options for Target Output is enabled. You may start your PROM
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programming utility after the make process when you specify the program under the option Run User Program #1. CPU Simulation Vision2 simulates up to 16 Mbytes of memory from which areas can be mapped for read, write, or code execution access. The Vision2 simulator traps and reports illegal memory accesses. In addition to memory mapping, the simulator also provides support for the integrated peripherals of the various 8051 derivatives. The on-chip peripherals of the CPU you have selected are configured from the Device Database selection You have made when you create your project target. Refer to page 58 for more Information about selecting a device. You may select and display the on-chip peripheral components using the Debug menu. You can also change the aspects of each peripheral using the controls in the dialog boxes. Start Debugging You start the debug mode of Vision2 with the Debug Start/Stop Debug Session command. Depending on the Options for Target Debug Configuration, Vision2 will load the application program and run the startup code Vision2 saves the editor screen layout and restores the screen layout of the last debug session. If the program execution stops, Vision2 opens an
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editor window with the source text or shows CPU instructions in the disassembly window. The next executable statement is marked with a yellow arrow. During debugging, most editor features are still available.

For example, you can use the find command or correct program errors. Program source text of your application is shown in the same windows. The Vision2 debug mode differs from the edit mode in the following aspects: The Debug Menu and Debug Commands described below are available. The additional debug windows are discussed in the following. The project structure or tool parameters cannot be modified. All build Commands are disabled. Disassembly Window The Disassembly window shows your target program as mixed source and assembly program or just assembly code. A trace history of previously executed instructions may be displayed with Debug View Trace Records. To enable the trace history, set Debug Enable/Disable Trace Recording. If you select the Disassembly Window as the active window all program step commands work on CPU instruction level rather than program source lines. You can select a text line and set or modify code breakpoints using toolbar buttons or the context menu commands. You may use the dialog Debug Inline Assembly to modify the CPU instructions. That allows you to correct mistakes or to make temporary changes to the target program you are debugging. 5.8 SOURCE CODE

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1. 2.

Click on the Keil uVision Icon on Desktop The following fig will appear

3. 4.

Click on the Project menu from the title bar Then Click on New Project

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Save the Project by typing suitable project name with no extension in u r own folder sited in either C:\ or D:\

6. 7. 8.

Then Click on Save button above. Select the component for u r project. i.e. Atmel Click on the + Symbol beside of Atmel

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Select AT89C51 as shown below

10. 11.

Then Click on OK The Following fig will appear

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Then Click either YES or NOmostly NO

13. 14.

Now your project is ready to USE Now double click on the Target1, you would get another option Source group 1 as shown in next page.

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Click on the file option from menu bar and select new


The next screen will be as shown in next page, and just maximize it by double clicking on its blue boarder.


Now start writing program in either in C or ASM

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For a program written in Assembly, then save it with extension . asm and for C based program save it with extension .C


Now right click on Source group 1 and click on Add files to Group


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Now you will get another window, on which by default C files will


21. 22. 23.

Now select as per your file extension given while saving the file Click only one time on option ADD Now Press function key F7 to compile. Any error will appear if so


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24. 25.

If the file contains no error, then press Control+F5 simultaneously. The new window is as follows

26. 27.

Then Click OK Now Click on the Peripherals from menu bar, and check your required

port as shown in fig below

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Drag the port a side and click in the program file.

29. 30.

Now keep Pressing function key F11 slowly and observe. You are running your program successfully

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5.9 Flash Magic: Features: Straightforward and intuitive user interface Five simple steps to erasing and programming a device and setting any options desired Programs Intel Hex Files Automatic verifying after programming Fills unused flash to increase firmware security Ability to automatically program checksums. Using the supplied checksum calculation routine your firmware can easily verify the integrity of a Flash block, ensuring no unauthorized or corrupted code can ever be executed Program security bits Check which Flash blocks are blank or in use with the ability to easily erase all blocks in use Read the device signature
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Read any section of Flash and save as an Intel Hex File Reprogram the Boot Vector and Status Byte with the help of confirmation features that prevent accidentally programming incorrect values Displays the contents of Flash in ASCII and Hexadecimal formats Single-click access to the manual, Flash Magic home page and NXP Microcontrollers home page Ability to use high-speed serial communications on devices that support it. Flash Magic calculates the highest baud rate that both the device and your PC can use and switches to that baud rate transparently Command Line interface allowing Flash Magic to be used in IDEs and Batch Files Manual in PDF format supports half-duplex communications Verify Hex Files previously programmed Save and open settings Able to reset Rx2 and 66x devices (revision G or higher) Able to control the DTR and RTS RS232 signals when connected to RST and /PSEN to place the device into Boot ROM and Execute modes automatically. An example circuit diagram is included in the Manual. This is essential for ISP with target hardware that is hard to access. This enables us to send commands to place the device in Boot ROM mode, with support for command line interfaces. The installation includes an example project for the Keil and Raisonance 8051 compilers that show how to build support for this feature into applications. Able to play any Wave file when finished programming. built in automated version checker - helps ensure you always have the latest version.

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Powerful, flexible Just In Time Code feature. Write your own JIT Modules to generate last minute code for programming. Uses include: Serial number generation Copy protection and copy authorization Storing program date and time - manufacture date Storing program operator and location Lookup table generation Language tables or language selection Centralized record keeping Obtaining latest firmware from the Corporate Web site or project intranet Requirements: Flash Magic works on any versions of Windows, except Windows 95. 10Mb of disk space is required. As mentioned earlier, we are automating two different routines in our project and hence we used the method of polling to continuously monitor those tasks and act accordingly

OPERATION OF ROBOT : 1. Initially we will assume the rest position of entire system, i.e. state when no object is placed. 2. As soon as object is placed at the picking platform, the sensor gets interrupted and outputs low. This signal is sent to the microcontroller which is burnt with program which tells what operation is to be performed at this stage. 3. For understanding operation, let us rename the two motors used here. Let the name of motor be M1 and motor is M2. 4. As microcontroller detects and
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For forward direction, when the motor M1 & motor M2 be ON stage then the both the motors move in forward direction For reverse direction, when the motor M1 &motor M2 be OFF stage then the both the motors move in reverse direction For left side, when the motor M1 is OFF stage &M2 be ON stage then the motor M1 move in reverse direction and motor M2 move in forward direction For Right side, when the motor M1 is OFF stage &M2 be ON stage then the motor M1 move in reverse direction and motor M2 move in forward direction 5. For Arm movement, Let us rename the two motors arm used here. Let the name of motor be M3 and motor is M4. 6. Now as microcontroller detects and If the motor M3 is in ON stage it moves in clockwise direction for a fixed time due to which whole arm moves towards the direction and the motor M4 is in OFF stage. 7. As it reaches there, M3 stops and now motor M4 is started in say clockwise direction to hold the object by closing jaw. This motor also, is on for particular fixed time instant. 8. As M4 gets OFF, motor M3 is moved again in anticlockwise direction till the time it reaches the placing platform. 9. As it reaches placing platform, the motor M3 stops and M4 is switched ON in anticlockwise direction till it releases object properly on desired place. 10)These motors are driven through the motor driver called L293D.

Operating the L293D motor driver

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Using the L293D motor driver, makes controlling a motor as simple as operating a buffer gate IC. It totally isolates the TTL logic inputs from the high current outputs. Putting a logic 1 on the pin In1 will make Out1 pin go to Vpower (36 Volts MAX.), while a logic 0 will make it go to 0V Each couple of channels can be enabled and disabled using E1 and E2 pins. When disabled a channel provide a very high impedance (resistance) to the motor, exactly as if the motor wasn't connected to the driver IC at all, which makes this feature very useful for PWM speed control. Figure 5.C shows different ways to connect a motor to the IC. One way is to use 2 channels to build

Fig.5C: Using the L293D motor driver

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a bi-directional motor driver, another way is to use 1 channel per motor, building a unidirectional driver. In this project, we will be using the 4 channels to drive the 2 motors in both directions.

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