Agenda

CCS Introduction CCS vs. NLDM Timing Modeling Mechanism CCS Driver Model, Characterization, and Example CCS Receiver Model, Characterization, and Example CCS vs. NLDM Experiment, Comparison CCS Power & Noise modeling. Summary

Introduction
I

The conventional delay calculation using voltage source driver model can deliver acceptable accuracy when output waveform is mostly linear and interconnect resistance is low Unfortunately, in very deep sub-micron process, the output waveform can become highly nonlinear and interconnect resistance can become large

Introduction.. cont
To improve VDSM delay calculation accuracy, Synopsys has
proposed Composite Current-Source (CCS) model which consists of two components: Driver Model captures the time-variant output current waveform

Receiver Model uses two values of pin capacitance to capture

the nonlinear pin capacitance of the load pin

CCS vs. NLDM Timing Modeling Mechanism NLDM uses a ramp voltage source for the driver model and a single capacitive value for the receiver model CCS uses time-varying nonlinear current source for the driver model and a variable input capacitance for the receiver model

CCS Driver Model

CCS driver model is a set of extracted current vs. time waveforms of output pins in different input slew, output load,and timing arc.

Example of CCS Driver Model

Index_1: input slew Index_2: output load Values: output current Index_3: time

CCS Receiver Model

CCS receiver model uses two values, C1 and C2, to represent the nonlinear pin capacitance during transition in different input slew, output load, and timing arc. C1 and C2 model the input capacitance variation effected by Miller Effect during transition

Example of CCS Receiver Model

Index_1: input slew Index_2: output load Values: capacitance

Comparison of CCS Driver Model with NLDM

The conventional delay calculation uses voltage source driver model. When the interconnect impedance is much greater than the drive resistance, the conventional voltage source driver model can lose accuracy It may occur when a big driving cell drives a long net Primetime shows RC-009 warning message under this circumstance and uses an empirical formula to calculate delay

Long net

Liberty: Keeping Up With Emerging Challenges Key modeling challenges at 90nm and below: High impedance interconnect Miller effect Broader support for multi-voltage designs Dynamic IR-Drop Noise propagation, driver weakening Temperature inversion Larger number of cells in library Increasing variations

Miller effect accounts for the increase in the equivalent input capacitance of an inverting voltage amplifier due to amplification of the effect of capacitance between the input and output terminals. The virtually increased input capacitance due to the Miller effect is given by

where is the gain of the amplifier and C is the feedback capacitance. Although the term Miller effect normally refers to capacitance, any impedance connected between the input and another node exhibiting gain can modify the amplifier input impedance via this effect. These properties of the Miller effect are generalized in the Miller theorem.

CCS Delay Calculation