`include "reg_piso.

v" `timescale 1ns/100ps module reg_piso_tb; reg reg reg reg reg reg wire wire wire wire wire [7:0]data_in; load; shift; rl; reset_n; clk; data_out; data_valid; eoc; [7:0]data; [3:0]cnt; (data_in, load, shift, rl, reset_n, clk, data_out, data_valid, data, eoc, cnt);

reg_piso a1

always #10 clk=!clk; initial begin data_in =0; load=0; shift=0; rl=0; reset_n=0; clk=0; #10 data_in =8'hfa; load=1; shift=0; rl=1; reset_n=1; #20 load=0; shift=1; rl=1; reset_n=1; #180

$finish; $stop; end endmodule