---------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 17:19:38 12/11/2012 -- Design Name: -- Module Name: DEMLENXUONGNHAPNHAYCHUSTOP - Behavioral -- Project

Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity DEMLENXUONGNHAPNHAYCHUSTOP is Port ( CK100MHZ : in STD_LOGIC; SW : in STD_LOGIC; START : in STD_LOGIC; STOP : in STD_LOGIC; AN : out STD_LOGIC_VECTOR (3 downto 0); SSEG : out STD_LOGIC_VECTOR (7 downto 0)); end DEMLENXUONGNHAPNHAYCHUSTOP; architecture Behavioral of DEMLENXUONGNHAPNHAYCHUSTOP is SIGNAL CK1HZ: STD_LOGIC; SIGNAL CKQ: STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL BCD0,BCD1,BCD2,BCD3,BCD: INTEGER:=0; begin --- CHIA XUNG PROCESS(CK100MHZ) VARIABLE CHIA1: STD_LOGIC_VECTOR(27 DOWNTO 0):=X"0000000"; VARIABLE CK1HZT: STD_LOGIC:='0'; BEGIN IF FALLING_EDGE(CK100MHZ) THEN IF CHIA1= X"2FAF080" THEN CHIA1:=X"0000000";CK1HZT:= NOT CK1HZT; ELSE CHIA1:= CHIA1+1; END IF;

END IF; CK1HZ<= CK1HZT; CKQ<= CHIA1(15 DOWNTO 14); END PROCESS; -- DEM PROCESS(CK1HZ, SW, START, STOP) VARIABLE TT,SWT: INTEGER RANGE 0 TO 1:=0; VARIABLE BCD0T, BCD1T, BCD2T, BCD3T: INTEGER:=0; BEGIN IF START ='1' THEN TT:=1; ELSIF STOP ='1' THEN TT:=0; ELSE IF TT=1 THEN TT:= 1; ELSIF TT=0 THEN TT:=0; END IF; END IF; IF TT=0 THEN BCD3T:= 1; BCD2T:=7; BCD1T:=3; BCD0T:=6; IF SW='0' THEN SWT:=0; ELSIF SW ='1' THEN SWT:=1; END IF; BCD0<= BCD0T; BCD1<= BCD1T; BCD2<= BCD2T;BCD3<= BCD3T; ELSIF TT=1 THEN IF SWT=1 THEN -- DEM LEN IF FALLING_EDGE(CK1HZ) THEN IF BCD3T=7 AND BCD2T=2 THEN IF CK1HZ='1' THEN BCD3<= 10; BCD2<= 11;B CD1<= 12; BCD0<= 13; ELSIF CK1HZ='0' THEN BCD3<= 15; BCD2<= 1 5;BCD1<= 15; BCD0<= 15; END IF; ELSE IF BCD2T=9 THEN BCD2T:=0; IF BCD3T =9 THEN BCD3T:=0; ELSE BCD3T:= BCD3T+1; END IF; ELSE BCD2T:= BCD2T+1; END IF; BCD0<= BCD0T; BCD1<= BCD1T; BCD2<= B CD2T;BCD3<= BCD3T; END IF; END IF; ELSIF SWT=0 THEN -- DEM XUONG IF FALLING_EDGE(CK1HZ) THEN IF BCD1T=2 AND BCD0T=7 THEN IF CK1HZ='1' THEN BCD3<= 10; BCD2<= 11;B CD1<= 12; BCD0<= 13;-- STOP ELSIF CK1HZ='0' THEN BCD3<= 15; BCD2<= 1 5;BCD1<= 15; BCD0<= 15;-- TAT HET END IF; ELSE IF BCD0T=0 THEN BCD0T:=9; IF BCD1T =0 THEN BCD1T:=9; ELSE BCD1T:= BCD1T-1; END IF; ELSE BCD0T:= BCD0T-1;

END IF; BCD0<= BCD0T; CD2T;BCD3<= BCD3T; END IF; END IF; END IF; END IF; END PROCESS; --GHEP KENH PROCESS(CKQ) BEGIN CASE CKQ IS WHEN WHEN WHEN WHEN WHEN END CASE; END PROCESS; --- HIENTHI PROCESS(BCD) BEGIN CASE BCD IS WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN END CASE; END PROCESS; end Behavioral;

BCD1<= BCD1T;

BCD2<= B

"00" => BCD<= BCD0; "01" => BCD<= BCD1; "10" => BCD<= BCD2; "11" => BCD<= BCD3; OTHERS => NULL;

AN<="1110"; AN<="1101"; AN<="1011"; AN<="0111";

0 => SSEG<=X"F9"; 1 => SSEG<=X"C0"; 2 => SSEG<=X"A4"; 3 => SSEG<=X"B0"; 4 => SSEG<=X"99"; 5 => SSEG<=X"92"; 6 => SSEG<=X"82"; 7 => SSEG<=X"F8"; 8 => SSEG<=X"80"; 9 => SSEG<=X"90"; 10 => SSEG<=X"12";--S 11 => SSEG<=X"87";--T 12 => SSEG<=X"F9";--O 13 => SSEG<=X"8C";--P 15=> SSEG<=X"FF"; OTHERS => NULL;

# PlanAhead Generated physical constraints NET NET NET NET NET NET NET NET "AN[0]" "AN[1]" "AN[2]" "AN[3]" LOC LOC LOC LOC = = = = N16; N15; P18; P17;

"CK100MHZ" LOC = V10; "SW" LOC = T10; "START" LOC = C4; "STOP" LOC = D9;

NET "SSEG[0]" LOC = T17; NET "SSEG[1]" LOC = T18; NET "SSEG[2]" LOC = U17;

NET NET NET NET NET

"SSEG[3]" "SSEG[4]" "SSEG[5]" "SSEG[6]" "SSEG[7]"

LOC LOC LOC LOC LOC

= = = = =

U18; M14; N14; L14; M13;