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  • Verilog Code To Divide Clock Frequency in FPGA

    Transféré par

    Pradeep Joy
    115 vues3 pages
    This document contains a Verilog module that divides an input clock by 2 and outputs the divided clock. It uses a delay counter to divide the clock and toggle an internal divided clock signal. It also contains a second always block that doubles the value of an output register on each edge of the divided clock, resetting it to 1 when it reaches 8. This module divides a clock by 2 and outputs a signal that doubles on each divided clock edge from 1 to 8 before resetting.

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    Verilog code to divide clock Frequency in FPGA

    Titre original

    Verilog code to divide clock Frequency in FPGA

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    © Attribution Non-Commercial (BY-NC)

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    This document contains a Verilog module that divides an input clock by 2 and outputs the divided clock. It uses a delay counter to divide the clock and toggle an internal divided clock signal. It also contains a second always block that doubles the value of an output register on each edge of the divided clock, resetting it to 1 when it reaches 8. This module divides a clock by 2 and outputs a signal that doubles on each divided clock edge from 1 to 8 before resetting.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    115 vues3 pages

    Verilog Code To Divide Clock Frequency in FPGA

    Transféré par

    Pradeep Joy
    This document contains a Verilog module that divides an input clock by 2 and outputs the divided clock. It uses a delay counter to divide the clock and toggle an internal divided clock signal. It also contains a second always block that doubles the value of an output register on each edge of the divided clock, resetting it to 1 when it reaches 8. This module divides a clock by 2 and outputs a signal that doubles on each divided clock edge from 1 to 8 before resetting.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 3

    `timescale 1ns / 1ps

    //////////////////////////////////////////////////////////////////////////////////
    // Company:
    // Engineer:
    //
    // Create Date: 13:26:03 08/27/2012
    // Design Name:
    // Module Name: ClockDivide3
    // Project Name:
    // Target Devices:
    // Tool versions:
    // Description:
    //
    // Dependencies:
    //
    // Revision:
    // Revision 0.01 - File Created
    // Additional Comments:
    //
    //////////////////////////////////////////////////////////////////////////////////
    module power_2(
    input clk,
    input clk_e,
    input reset,
    output reg[3:0] out
    );
    //reg [3:0] o_put;

    reg div_clk;
    reg [26:0]delay_count;

    //////////clock division block////////////////////


    always @(posedge clk or posedge reset)
    begin

    if(reset)
    begin
    delay_count<=27'd0;
    div_clk <= 1'b0;
    end
    else
    if(delay_count==27'd67108864)
    begin
    delay_count<=27'd0;
    div_clk <= ~div_clk;
    end
    else
    begin
    delay_count<=delay_count+1;
    end
    end

    always @(posedge div_clk or posedge reset)


    begin

    if (reset)
    out <= 1;
    else
    if (clk_e)
    //#500000;
    begin
    out <= out*2;
    if(out==8)
    out <=1 ;
    end
    end

    endmodule

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