Verilog - 1

More Verilog
Pegisfers
Counfers
Shiff regisfers
FSMs
DeIoyed ossignmenfs
Tesf Fixfures
Verilog - 2
module reg8 (reset, CLK, D, Q);
input reset;
input CLK;
input [7:0] D;
output [7:0] Q;
reg [7:0] Q;
always @(posedge CLK)
if (reset)
Q = 0;
else
Q = D;
endmodule // reg8
8-bit Register with Synchronous Reset
Verilog - 3
module regN (reset, CLK, D, Q);
input reset;
input CLK;
parameter N = 8; // Allow N to be changed
input [N-1:0] D;
output [N-1:0] Q;
reg [N-1:0] Q;
always @(posedge CLK or posedge reset)
if (reset)
Q = 0;
else if (CLK == 1)
Q = D;
endmodule // regN
N-bit Register with Asynchronous Reset
Verilog - 4
Shift Register Example
// 8-bit register can be cleared, loaded, shifted left
// Retains value if no control signal is asserted
module shiftReg (CLK, clr, shift, ld, Din, SI, Dout);
input CLK;
input clr; // clear register
input shift; // shift
input ld; // load register from Din
input [7:0] Din; // Data input for load
input SI; // Input bit to shift in
output [7:0] Dout;
reg [7:0] Dout;
always @(posedge CLK) begin
if (clr) Dout <= 0;
else if (ld) Dout <= Din;
else if (shift) Dout <= { Dout[6:0], SI };
end
endmodule // shiftReg
Verilog - 5
always @(posedge CLK)
begin
temp = B;
B = A;
A = temp;
end
always @(posedge CLK)
begin
A <= B;
B <= A;
end
Blocking and Non-Blocking Assignments
8Iocking ossignmenfs (Q = A)
voriobIe is ossigned immediofeIy before confinuing fo nexf sfofemenf
new voriobIe voIue is used by subsequenf sfofemenfs
Mon-bIocking ossignmenfs (Q <= A)
voriobIe is ossigned onIy offer oII sfofemenfs oIreody scheduIed
ore execufed
voIue fo be ossigned is compufed here buf soved for Iofer
usuoI use: regisfer ossignmenf
regisfers simuIfoneousIy foke fheir new voIues
offer fhe cIock fick
ExompIe: swop
Verilog - 6
Swap (continued)
The reoI probIem is poroIIeI bIocks
one of fhe bIocks is execufed firsf
previous voIue of voriobIe is Iosf
Use deIoyed ossignmenf fo fix fhis
bofh bIocks ore scheduIed by posedge CLK
always @(posedge CLK)
begin
A = B;
end
always @(posedge CLK)
begin
B = A;
end
always @(posedge CLK)
begin
A <= B;
end
always @(posedge CLK)
begin
B <= A;
end
Verilog - 7
Non-Blocking Assignment
Mon-bIocking ossignmenf is oIso known os on PTL ossignmenf
if used in on oIwoys bIock friggered by o cIock edge
mimic regisfer-fronsfer-IeveI semonfics - oII fIip-fIops chonge fogefher
My ruIe: ALWAYS use ~ in sequenfioI (posedge cIk) bIocks
// this implements 3 parallel flip-flops
always @(posedge clk)
begin
B = A;
C = B;
D = C;
end
// this implements a shift register
always @(posedge clk)
begin
B <= A;
C <= B;
D <= C;
end
// this implements a shift register
always @(posedge clk)
begin
{D, C, B} = {C, B, A};
end
Verilog - 8
Counter Example
SimpIe componenfs wifh o regisfer ond exfro compufofion
Cusfomi;ed inferfoce ond behovior, e.g.
counfers
shiff regisfers
// 8-bit counter with clear and count enable controls
module count8 (CLK, clr, cntEn, Dout);
input CLK;
input clr; // clear counter
input cntEn; // enable count
output [7:0] Dout; // counter value
reg [7:0] Dout;
always @(posedge CLK)
if (clr) Dout <= 0;
else if (cntEn) Dout <= Dout + 1;
endmodule
Verilog - 9
Finite State Machines
PecoII FSM modeI
Pecommended FSM impIemenfofion sfyIe
ImpIemenf combinofionoI Iogic using o one oIwoys bIock
ImpIemenf on expIicif sfofe regisfer using o second oIwoys bIock
inputs
Moore outputs
Mealy outputs
next state
current state
combinational
logic
Verilog - 10
// State assignment
parameter zero = 0, one1 = 1, two1s = 2;
module reduce (clk, reset, in, out);
input clk, reset, in;
output out;
reg out;
reg [1:0] state; // state register
reg [1:0] next_state;
// Implement the state register
always @(posedge clk)
if (reset) state = zero;
else state = next_state;
Verilog FSM - Reduce 1s example
Chonge fhe firsf I fo 0 in eoch sfring of I's
ExompIe Moore mochine impIemenofion
1
0
0
0
1
1
zero
[0]
one1
[0]
two1s
[1]
Verilog - 11
6
always @(in or state)
case (state)
out = 0; // defaults
next_state = zero;
zero: begin // last input was a zero
if (in) next_state = one1;
end
one1: begin // we've seen one 1
if (in) next_state = two1s;
end
two1s: begin // we've seen at least 2 ones
out = 1;
if (in) next_state = two1s;
end
// Dont need case default because of default assignments
endcase
endmodule
crucial to include
all signals that are
input to state and
output equations
Moore Verilog FSM (contd)
Verilog - 12
module reduce (clk, reset, in, out);
input clk, reset, in;
output out;
reg out;
reg state; // state register
reg next_state;
parameter zero = 0, one = 1;
always @(posedge clk)
if (reset) state = zero;
else state = next_state;
always @(in or state)
out = 0;
next_state = zero;
case (state)
zero: begin // last input was a zero
if (in) next_state = one;
end
one: // we've seen one 1
if (in) begin
next_state = one; out = 1;
end
endcase
endmodule
Mealy Verilog FSM for Reduce-1s example
1J0 0J0
0J0
1J1
zero
[0]
one1
[0]
Verilog - 13
Restricted FSM Implementation Style
MeoIy mochine requires fwo oIwoys bIocks
regisfer needs posedge CLI bIock
inpuf fo oufpuf needs combinofionoI bIock
Moore mochine con be done wifh one oIwoys bIock
e.g. simpIe counfer
Not u good ideu for generuI FSMs
Con be very confusing (see exompIe)
Moore oufpufs
Shore wifh sfofe regisfer, use suifobIe sfofe encoding
Verilog - 14
module reduce (clk, reset, in, out);
input clk, reset, in;
output out;
reg out;
reg [1:0] state; // state register
parameter zero = 0, one1 = 1, two1s = 2;
Single-always Moore Machine
(Not Recommended!)
1
0
0
0
1
1
zero
[0]
one1
[0]
two1s
[1]
Verilog - 15
6
always @(posedge clk)
case (state)
zero: begin
out = 0;
if (in) state = one1;
else state = zero;
end
one1:
if (in) begin
state = two1s;
out = 1;
end else begin
state = zero;
out = 0;
end
two1s:
if (in) begin
state = two1s;
out = 1;
end else begin
state = zero;
out = 0;
end
default: begin
state = zero;
out = 0;
end
endcase
endmodule
This is confusing: the
output does not change
until the next clock cycle
Single-always Moore Machine
(Not Recommended!)
All outputs are registered
Verilog - 16
Delays
DeIoys ore used for simuIofion onIy
DeIoys ore usefuI for modeIing fime behovior of circuif
Synfhesis ignores deIoy numbers
If your simuIofion reIies on deIoys, your synfhesi;ed circuif wiII
probobIy nof work
#I0 inserfs o deIoy of I0 fime unifs in fhe simuIofion
module and_gate (out, in1, in2);
input in1, in2;
output out;
assign #10 out = in1 & in2;
endmodule
Verilog - 17
assign #5 c = a | b;
assign #4 {Cout, S} = Cin + A + B;
always @(A or B or Cin)
#4 S = A + B + Cin;
#2 Cout = (A & B) | (B & Cin) | (A & Cin);
assign #3 zero = (sum == 0) ? 1 : 0;
always @(sum)
if (sum == 0)
#6 zero = 1;
else
#3 zero = 0;
Verilog Propagation Delay
Moy wrife fhings differenfIy for finer confroI of deIoys
Verilog - 18
Initial Blocks
Like oIwoys bIocks
execufe once of fhe very beginning of simuIofion
nof synfhesi;eobIe
use resef insfeod
Verilog - 19
Tri-State Buffers
'Z' voIue is fhe fri-sfofed voIue
This exompIe impIemenfs fri-sfofe drivers driving 8usOuf
module tstate (EnA, EnB, BusA, BusB, BusOut);
input EnA, EnB;
input [7:0] BusA, BusB;
output [7:0] BusOut;
assign BusOut = EnA ? BusA : 8bZ;
assign BusOut = EnB ? BusB : 8bZ;
endmodule
Verilog - 20
Test Fixtures
Provides cIock
Provides fesf vecfors/checks resuIfs
fesf vecfors ond resuIfs ore precompufed
usuoIIy reod vecfors from fiIe
ModeIs sysfem environmenf
CompIex progrom fhof simuIofes exfernoI environmenf
Tesf fixfure con oII fhe Ionguoge feofures
inifioI, deIoys, reod/wrife fiIes, efc.
Simulation
Test Fixture
(Specification)
Circuit Description
(Synthesizeable)
Verilog - 21
Verilog Clocks
CIock0enerofor
module clockGenerator (CLK);
parameter period = 10;
parameter howlong = 100;
output CLK;
reg CLK;
initial begin
CLK = 0;
#(period/2);
repeat (howlong) begin
CLK = 1;
#(period-period/2);
CLK = 0;
#(period/2);
end
$finish;
end
endmodule // clockGenerator
Stops the simulation
Values assigned in blocks
have to be declared "reg"
Verilog - 22
module clock_gen (masterclk);
`define PERIOD = 10;
output masterclk;
reg masterclk;
initial masterclk = 0;
always begin
#`PERIOD/2
masterclk = ~masterclk;
end
endmodule
use `define to make constants
easier to find and change
use of initial and always
blocks
Verilog Clocks
Anofher cIock generofor
Verilog - 23
Example Test Fixture
module full_addr1 (A, B, Cin, S, Cout);
input A, B, Cin;
output S, Cout;
assign {Cout, S} = A + B + Cin;
endmodule
module stimulus (a, b, c);
parameter delay = 10;
output a, b, c;
reg [2:0] cnt;
initial begin
cnt = 0;
repeat (8) begin
#delay cnt=cnt+1;
end
#delay $finish;
end
assign {c, a, b} = cnt;
endmodule
module driver; // Structural Verilog connects test-fixture to full adder
wire a, b, cin, sum, cout;
stimulus stim (a, b, cin);
full_addr1 fa1 (a, b, cin, sum, cout);
initial begin
$monitor ("@ time=%0d cin=%b, a=%b, b=%b, cout=%d, sum=%d",
$time, cin, a, b, cout, sum);
end
endmodule
Verilog - 24
module stimulus (a, b);
parameter delay = 10;
output a, b;
reg [1:0] cnt;
initial begin
cnt = 0;
repeat (4) begin
#delay cnt = cnt + 1;
end
#delay $finish;
end
assign {a, b} = cnt;
endmodule
Simulation Driver
2-bit vector
initial block executed
only once at start of simulation
directive to stop
simulation
bundles two signals
into a vector
Verilog - 25
module testData(clk, reset, data);
input clk;
output reset, data;
reg [1:0] testVector [100:0];
reg reset, data;
integer count;
initial begin
$readmemb("data.b", testVector);
count = 0;
{ reset, data } = testVector[0];
end
always @(posedge clk) begin
count = count + 1;
#1 { reset, data } = testVector[count];
end
endmodule
Test Vectors
Verilog - 26
Verilog Simulation
Inferprefed vs. compiIed simuIofion
performonce of fhe simuIofion
LeveI of simuIofion
occurocy of fhe modeI
PeIofionship fo synfhesis
con oII fhof con be simuIofed be synfhesi;ed7
Verilog - 27
Intepreted vs. Compiled Simulation
Inferprefed
dofo sfrucfures consfrucfed from inpuf fiIe
simuIofor woIks dofo sfrucfures ond decided when somefhing occurs
bosic oIgorifhm:
foke on evenf from queue, evoIuofe oII moduIes sensifive fo fhof
evenf, pIoce new evenfs on queue, repeof
CompiIed
inpuf fiIe is fronsIofed info code fhof is compiIed/Iinked wifh kerneI
bosic oIgorifhm:
some os obove
excepf fhof now funcfions ossociofed wifh eIemenfs ore simpIy
execufed ond direcfIy pIoce evenfs on queue
overheod of compiIofion musf be omorfi;ed over fofoI simuIofion
fime ond ifs horder fo moke chonges - need dynomic Iinking
Verilog - 28
Simulation Level
EIecfricoI
soIve differenfioI equofions for oII devices simuIfoneousIy fo defermine
precise onoIog shope of woveforms
Tronsisfor
modeI individuoI fronsisfors os swifches - fhis con be cIose fo eIecfricoI
simuIofion if resfricfed fo digifoI circuifs
0ofe
use obsfrocfion of 8ooIeon oIgebro fo view gofes os bIock-boxes if onIy
inferesfed in digifoI voIues ond deIoy
CycIe or regisfer-fronsfer
defermine correcf voIues onIy of cIock edges, ignore gofe deIoys if
inferesfed onIy in proper IogicoI behovior of defoiIed impIemenfofion
FuncfionoI (or behovioroI) IeveI
no inferesf in infernoI defoiIs of circuif impIemenfofion (jusf o progrom)
Verilog - 29
Simulation Time and Event Queues
Evenf queue
chonges in signoI voIues ore "evenfs" pIoced on fhe queue
queue is o Iisf of chonges fo propogofe
priorify queue of pending evenfs bosed on fime of occurrence
muIfipIe evenfs on some signoI con be on queue
Time
odvonced whenever on evenf is foken off fhe queue
odvonce fo fime of evenf
poroIIeI ocfivifies ore impIicifIy inferIeoved
whof do we do obouf evenfs wifh ;ero deIoy7
Verilog - 30
Verilog Time
AII compufofions hoppen in ;ero fime unIess fhere ore expIicif deIoys or
woifs in fhe code
#deIoy - bIocks execufion unfiI fhof much fime hos possed
evenf pIoced on queue fo woke up bIock of fhof fime
or woif - woifs for on evenf, e.g., (posedge cIk) ond woif(x~~0)
nofhing hoppens unfiI fhof evenf is foken off fhe queue
When on evenf is removed from fhe queue, oII fhe bIocks sensifive fo if
ore evoIuofed in poroIIeI ond odvonce fo fheir nexf bIocking poinf
(deIoy/woif)
Time odvonces os Iong os fhere ore evenfs fo process
infinife Ioops ore eosy fo wrife
use expIicif $finish
use specified number of cIock periods
Verilog - 31
Inertial and Transport Delays
InerfioI DeIoy
#3 X ~ A ,
Woif 3 fime unifs, fhen ossign voIue of A fo X
The usuoI woy deIoy is used in simuIofion
modeIs Iogic deIoy reosonobIy
Tronsporf DeIoy
X ~ #3 A ,
Currenf voIue of A is ossigned fo X, offer 3 fime unifs
8effer modeI for fronsmission Iines ond high-speed Iogic
Verilog - 32
A few requirements for CSE467...
Drow dofo-fIow diogroms
AIgorifhm dofofIow dofopofh ond confroI
Then insfonce VeriIog moduIes info XiIinx schemofics
Drow sfofe diogroms
And do fhe sfofe encoding
One-hof
SimpIifies combinofionoI Iogic (reduces # of inpufs)
More CL8s for sfofe, buf Iess for Iogic
Oufpuf bosed use some bifs for oufpufs ond sfofe
Don'f need CL8s fo decode oufpuf from sfofe
ModuIori;e your designs