A

Compal Confidential

Schematic Document

MCP79-MX
2009 / 02 / 19

Rev:1.0

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Cover Sheet
Size Document Number
Custom

Rev
1.0

LA-4631P

Date:

Sheet

Thursday, February 19, 2009

E

of

42

Braxton 14"

Compal confidential
Project Code: KCM00
File Name : LA-4631P

Intel Penryn

PCB

Fan Driver
RT9027BPS

ZZZ1

uFCPGA-478 CPU
P.4
P.4,5,6

X76

Thermal Sensor
EMC1402-1-ACZL-TR

P.4

FSB

H_A#(3..35)

667/800/1066MHz 1.05V

H_D#(0..63)

ZZZ2

Memory
Channel A

14" LED Panel

HD 1366 x 768
HD+ 1600 x 900

Dual Channel

LVDS

DDR3 800/1066 MHz +1.5V

P.20

HDMI Conn.
Display Port

Channel B

1:2 Switch
TI
SN75DP122A
P.21

P.21

BANK 0, 1, 2, 3

nVIDIA
MCP79-MX

SATA

PCI-E x1
PCIE2

PCIE3

USB2.0

SATA_A0

SATA HDD Conn

SATA_A1
B to B
USB2

USB/E-SATA Conn

USB1
B to B
USB0

On Right Side

USB Conn
On Right Side

USB Conn
On Left Side

Express Card
( 34mm )

RealTek
RTL8111DL

P.23

Mini Card-1
WLAN (Half)

P.22

P.19

FCBGA 1437
PCIE1

DDR3-SO-DIMM x1

HDMI / TMDS

P.21

PCIE0

DDR3 / 1GB on board

( 128Mx8) x8pcs P.17,18

JMicron
JMB380

P.24

USB3

Express Card
( 34mm )

P.20

P.29

P.29

P.27

P.23

P.26

HDA

B to B

USB7

Mini Card-1 (WLAN)

( Half )

P.24

P.7~16

RJ45 Conn.

USB6

IEEE1394

USB5

LPC

USB4

P.29

P.27

P.27

P.27

Audio Codec
IDT 92HD83

RTC CKT.

Tweeter (0.5W x2)

P.25, 29

P.25

Speaker (1W x2) P.25

P.14,15,32,33

Touch Pad Conn

P.29

Power Circuit DC/DC

Camera

BIOS(System/EC)

Int.KB

P.29

P.28

Power OK CKT.

P.32~40

Audio Jack x3

B to B
Compal Secret Data

Security Classification
2009/02/19

Issued Date

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

P.24

Digital Microphone
P.28

P.30

Blue Tooth

SIM Card

P.24

KBC
ENE KB926

Power On/Off CKT.

DC/DC Interface CKT.

Mini Card-2 (WWAN)

( Full )

P.29

P.22

Title

P.29

Compal Electronics, Inc.

Block Diagram

Size Document Number

Custom LA-4631P
Date:

Rev
1.0
Sheet

Thursday, February 19, 2009

E

of

42

Voltage Rails

O MEANS ON

X MEANS OFF

Symbol Note :
: means Digital Ground

: means Analog Ground

power
plane

+5VS
+3VS
+1.8VS
+B

+5VALW

+1.5V

+3VALW

+1.1VS
+VCCP

@ : means just reserve , no build

DEBUG@ : means just reserve for debug.

+1.0VS

+1.1VALW

+0.75VS

State

+CPU_CORE
+1.5VS

Board ID Table for AD channel

Vcc
Ra

3.3V +/- 5%
100K +/- 5%
Rb
0
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

Board ID

S0

S1

S3

S5 S4/ Battery only

S5 S4/AC & Battery

don't exist

S5 S4/AC

0
1
2
3
4
5
6
7

BOARD ID Table
V AD_BID min
0 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

Board ID
0
1
2
3
4
5
6
7

PCB Revision
0.1
0.2
0.3
0.4
0.5
1.0

SMBUS Control Table

1

SOURCE

INVERTER

BATT

SERIAL
EEPROM

THERMAL
SENSOR
(CPU)

SODIMM

EXP CARD

MINI CARD1 MINI CARD2

X
X

V
X

X
X

X
V

X
X

X
X

X
X

X
X

MCP79

MCP79

EC_SMB_CK1
EC_SMB_DA1

KB926

EC_SMB_CK2
EC_SMB_DA2

KB926

MEM_SMBCLK
MEM_SMBDATA
MCP_SMB_CLK
MCP_SMB_DATA

MINI CARD 1 RESERVED +3VALW TO PULL HIGH

Compal Secret Data

Security Classification
2009/02/19

Issued Date

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Notes List

Size Document Number

Custom LA-4631P
Date:

Thursday, February 19, 2009

Rev
1.0
Sheet

of

42

XDP Reserve

+VCCP

Place close to CPU within 500mil

H_A20M#
H_FERR#
H_IGNNE#

7
7
7
7

H_STPCLK#
H_INTR
H_NMI
H_SMI#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

H_A20M#
H_FERR#
H_IGNNE#

A6
A5
C4

H_STPCLK#
H_INTR
H_NMI
H_SMI#

D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D22
D3
F6

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#

H_DEFER#
H_DRD Y#
H_DBSY#

BR0#
BR1#
IERR#
INIT#

F1
AA7
D20
B3

H_BR0#
H_BR1#
H_IERR#
H_INIT#

LOCK#

H4

H_LOCK#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

C1
F3
F4
G3
G2

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

HIT#
HITM#

G6
E4

H_HIT#
H_HITM#

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_PREQ#
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7
H_BR0#
H_BR1#

7
7

H_INIT# 7
H_LOCK# 7
H_RESET# 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7

49.9_0402_1%

49.9_0402_1%

XDP_PREQ#

R515 2

49.9_0402_1%

XDP_TDI

R516 2

49.9_0402_1%

XDP_TDO

R517 2

49.9_0402_1%

XDP_TMS

R518 2

49.9_0402_1%

H_PROCHOT#

R519 2

68_0402_5%

H_BR0#

R520 1

62_0402_5%

H_FERR#

R521 1

62_0402_5%

H_INTR

R522 1

150_0402_1%

H_NMI

R523 1

150_0402_1%

H_RESET#

R524 1

200_0402_1%

H_BR1#

R1275 1

62_0402_5%

XDP_TCK

R525 2

49.9_0402_1%

XDP_TRST#

R526 2

649_0402_1%

PROCHOT#
THERMDA
THERMDC
THERMTRIP#

H_PROCHOT#
H_THERMDA_R
H_THERMDC_R

C7

H_THERMTRIP#

BCLK[0]
BCLK[1]

A22
A21

CLK_CPU_BCLK
CLK_CPU_BCLK#

+5VS

C3
10U_1206_16V4Z~N
2
1

T7

C4
1

1
1

2 100_0402_5%
2 100_0402_5%

U3
1
2
3
4

+3VS

H_THERMDA
H_THERMDC

28

EN_DFAN1

EN_DFAN1

R10
10K_0402_5%

H_THERMTRIP# 7

28 FAN_SPEED1

CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7

C6
0.01U_0402_16V7K

10U_1206_16V4Z~N

C5
1000P_0402_50V7K~N

H_PROCHOT# 7
R7
R8

H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil

H CLK

Fan Control circuit

D21
A24
B25

H_HIT# 7
H_HITM# 7
T1
T2
T3
T4
T5
T6

THERMAL

STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

H5
F21
E1

H_ADS# 7
H_BNR# 7
H_BPRI# 7

7
7
7

R514 2

VEN
VIN
VO
VSET

GND
GND
GND
GND

8
7
6
5

RT9027BPS SO 8P

40mil

JFAN1

FAN1_POWER

H_ADSTB#1

K3
H2
K2
J3
L1

DEFER#
DRDY#
DBSY#

ICH

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADS#
H_BNR#
H_BPRI#

1
2
3

1
2
3

4
5

GND
GND

MOLEX_53780-0370~D
CONN@

Thermal Sensor
+3VS
0.1U_0402_16V4Z

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#[17..35]

H1
E2
G5

ADS#
BNR#
BPRI#

CONTROL

7
7
7
7
7
7

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

XDP/ITP SIGNALS

H_ADSTB#0

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP_1

R513 2

H_THERMTRIP#

JCPU1A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

ADDR GROUP_0

H_A#[3..16]

RESERVED

H_IERR#

TYCO_2-1871873-3_Merom~D
CONN@

1
C2
+3VS

1
C1
2
U2
1

VDD

SCLK

EC_SMB_CK2

H_THERMDA

D+

SDATA

EC_SMB_DA2

H_THERMDC
2
2200P_0402_50V7K
R9
L_THERM#
1
2
10K_0402_5%

D-

ALERT#

THERM#

GND

EC_SMB_CK2 28
EC_SMB_DA2 28

EMC1402-1-ACZL-TR MSOP 8P

SMBus Address:100_1100

Compal Secret Data

Security Classification
2009/02/19

Issued Date

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

Size Document Number

Custom LA-4631P
Date:

Rev
1.0
Sheet

Tuesday, February 24, 2009

1

of

42

+CPU_CORE

7
7
7
@ R13
@ R14

1
1

AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21

@ C308 1

7
7
7

H_DSTBN#1
H_DSTBP#1
H_DINV#1

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

MISC

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

COMP0
COMP1
COMP2
COMP3

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PW RGOOD
H_CPUSLP#
H_PSI#

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_DPRSTP# 7,38
H_DPSLP# 7
H_DPWR# 7
H_PWRGOOD 7
H_CPUSLP# 7
H_PSI#
38

TYCO_2-1871873-3_Merom~D
CONN@

49.9

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

166
200

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0
1
0

R16

R17

R18

To IMVP

layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU

CPU_BSEL

R15

27.4_0402_1%
2
1

V_CPU_GTLREF
TEST1
2 1K_0402_5%
TEST2
2 1K_0402_5%
TEST3
T8
0.1U_0402_16V4Z
TEST4
2
TEST5
T10
TEST6
T11
TEST7
T12
CPU_BSEL0
CPU_BSEL0
CPU_BSEL1
CPU_BSEL1
CPU_BSEL2
CPU_BSEL2

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

+VCCP
H_PW RGOOD R527 1

2@ 150_0402_1%

H_CPUSLP#

R528 1

2@ 51_0402_1%

H_DPRSTP#

R529 1

2@ 220_0402_1%

+CPU_CORE
JCPU1C

47A

54.9_0402_1%
2
1

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

27.4_0402_1%
2
1

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

DATA GRP 2

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]

DATA GRP 1

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

DATA GRP 0

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

7
7
7
7

H_D#[32..47] 7

JCPU1B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

54.9_0402_1%
2
1

H_D#[0..15]

DATA GRP 3

25.5

29.9

25.5

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]

AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VCCSENSE 38

VSSSENSE

AE7

VSSSENSE

VSSSENSE 38

+VCCP

4.5A
C

1
+ C7
330U 2.5V Y D2 LESR15M CX H1.9
2

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

1
C8
2

+1.5VS

1
C9
2

Near pin B26

Layout Note:
Route VCCSENSE and VSSSENSE traces at
For 8 layer condition 27.4 Ohms with 50 mil spacing.

Length match within 25 mils.

The trace width/space/other is
20/7/25.

0
@ C649
0.01U 16V K X7R 0402

38
38
38
38
38
38
38

TYCO_2-1871873-3_Merom~D
CONN@
.

H_DPRSTP#

266

R1283
0_0805_5%
1
2

10mil

+1.5VS_VCCA

0.01U_0402_16V7K

10U_0805_6.3V6M

+CPU_CORE

+VCCP

For 6 layer
Z=27.4 ohm
VCCSENSE, VSSSENSE/ 14mils (MS),
16mils (SL) width, 7mils space, 25mils
space to other signals Mismatch =25mils.

V_CPU_GTLREF

R20
2K_0402_1%

Dual Core CPU

2

Close to CPU pin AD26

within 500mils.

2 100_0402_1%

VCCSENSE

R23

2 100_0402_1%

VSSSENSE

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Close to CPU pin

within 500mils.

Compal Secret Data

Security Classification
Issued Date

R21

R19
1K_0402_1%

Title

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

Size Document Number

Custom LA-4631P
Date:

Rev
1.0
Sheet

Tuesday, February 24, 2009

1

of

42

+CPU_CORE

C490
10U_0805_4V

C489
10U_0805_4V

C488
10U_0805_4V

C485
10U_0805_4V

C484
10U_0805_4V

C457
10U_0805_4V

C14
10U_0805_4V

C13
10U_0805_4V

C12
10U_0805_4V

C11
10U_0805_4V

Near CPU CORE regulator

ESR <= 1.5m ohm

Capacitor > 1980uF

JCPU1D

TYCO_2-1871873-3_Merom~D
CONN@
.

C580
10U_0805_4V

C579
10U_0805_4V

C578
10U_0805_4V

C577
10U_0805_4V

C493
10U_0805_4V

C492
10U_0805_4V

+CPU_CORE

16pcs on TOP side

C592
10U_0805_4V

C590
10U_0805_4V

C589
10U_0805_4V

C588
10U_0805_4V

C587
10U_0805_4V

2
C586
10U_0805_4V

C591
10U_0805_4V

2
C583
10U_0805_4V

C28
10U_0805_4V

2
C584
10U_0805_4V

C582
10U_0805_4V

C26
10U_0805_4V

C22
10U_0805_4V

C27
10U_0805_4V

+CPU_CORE

C585
10U_0805_4V

C581
10U_0805_4V

+CPU_CORE

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

16pcs on bottom side

+VCCP
B

C15
0.1U_0402_10V6K

C16
0.1U_0402_10V6K

+CPU_CORE

C17
0.1U_0402_10V6K

+CPU_CORE

+ C458
330U_D2E_2.5VM_R9
2

C18
0.1U_0402_10V6K

+CPU_CORE

+ C456
330U_D2E_2.5VM_R9

C19
0.1U_0402_10V6K

C20
0.1U_0402_10V6K

Place these caps inside the

socket cavity on Bottom side.
(North side Secondary)

+CPU_CORE

+ C576
330U_D2E_2.5VM_R9
2

+ C522
330U_D2E_2.5VM_R9
2

Compal Secret Data

Security Classification
2009/02/19

Issued Date

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

Size Document Number

Custom LA-4631P
Date:

Rev
1.0

Thursday, February 19, 2009

Sheet
1

of

42

H_D#[0..63]

U4A
5
5
5

H_DSTBP#0
H_DSTBN#0
H_DINV#0

5
5
5

H_DSTBP#1
H_DSTBN#1
H_DINV#1

5
5
5

H_DSTBP#2
H_DSTBN#2
H_DINV#2

5
5
5
4

H_DSTBP#3
H_DSTBN#3
H_DINV#3
H_A#[3..35]

2
1
1K_0402_5%

CPU_BSEL2

R560
@

5
5
5

R25
@

CPU_BSEL2
CPU_BSEL1
CPU_BSEL0

2
1
1K_0402_5%

2
1
1K_0402_5%

2
1
1K_0402_5%

+VCCP

R24
@

R26
@

4
4
4

1
B

L1

MBK1608221YZF 0603

C23

C24

H_ADS#
H_BNR#
H_BR0#
H_BR1#
H_DBSY#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

4 H_PROCHOT#
4 H_THERMTRIP#
4 H_FERR#
2.2U_0402_6.3VM

4.7U_0603_6.3V6K

+V_PLL_CPU

4
4
4
4
4
4
4
4
4
4

T40
U40
V41

CPU_DSTBP0#
CPU_DSTBN0#
CPU_DBI0#

H_DSTBP#1
H_DSTBN#1
H_DINV#1

W39
W37
V35

CPU_DSTBP1#
CPU_DSTBN1#
CPU_DBI1#

H_DSTBP#2
H_DSTBN#2
H_DINV#2

N37
L36
N35

CPU_DSTBP2#
CPU_DSTBN2#
CPU_DBI2#

H_DSTBP#3
H_DSTBN#3
H_DINV#3

M39
M41
J41

CPU_DSTBP3#
CPU_DSTBN3#
CPU_DBI3#

H_ADSTB#0
H_ADSTB#1

H_ADSTB#0
H_ADSTB#1
H_REQ#[0..4]

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

MRB(REV.E) 1.1VS
+VCCP

H_DSTBP#0
H_DSTBN#0
H_DINV#0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

4
4
4

AC34
AE38
AE34
AC37
AE37
AE35
AB35
AF35
AG35
AG39
AE33
AG37
AG38
AG34
AN38
AL39
AG33
AL33
AJ33
AN36
AJ35
AJ37
AJ36
AJ38
AL37
AL34
AN37
AJ34
AL38
AL35
AN34
AR39
AN35

CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#
CPU_A33#
CPU_A34#
CPU_A35#

AE36
AK35

CPU_ADSTB0#
CPU_ADSTB1#

AC38
AA33
AC39
AC33
AC35

CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#

H_ADS#
AD42
H_BNR#
AD43
H_BR0#
AE40
H_BR1#
AL32
H_DBSY#
AD39
H_DRD Y#
AD41
H_HIT#
AB42
H_HITM#
AD40
H_LOCK#
AC43
H_TRDY#
AE41
E41
T13
PAD
H_PROCHOT# 1R1281 0_0402_5%
AJ41
2
H_THERMTRIP# 1R1280 0_0402_5%
AG43
2
H_FERR#
AH40
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0

20 mA

H_RS#0
H_RS#1
H_RS#2

H_RS#0
H_RS#1
H_RS#2

+V_PLL_CPU
+1.05VS_PLL

1.1VS

F42
D42
F41

CPU_ADS#
CPU_BNR#
CPU_BR0#
CPU_BR1#
CPU_DBSY#
CPU_DRDY#
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_TRDY#
CPU_PECI
CPU_PROCHOT#
CPU_THERMTRIP#
CPU_FERR#
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0

AC41
AB41
AC42

CPU_RS0#
CPU_RS1#
CPU_RS2#

AH28
U28

+V_PLL_CPU
+V_PLL_DP

AM39
AM40

BCLK_VML_COMP_VDD
BCLK_VML_COMP_GND

AM43
AM42

CPU_COMP_VCC
CPU_COMP_GND

29 mA

+VCCP

C277
2.2U_0402_6.3VM

R29 2
R30 2

1 49.9_0402_1%
1 49.9_0402_1%

R31 1
R32 1

2 49.9_0402_1%
2 49.9_0402_1%

BCLK_VML_COMP_VCC
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_COMP_GND

FSB

CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#

Y43
W42
Y40
W41
Y39
V42
Y41
Y42
P42
U41
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
AA36
AA34
AA38
AA35
U38
U36
U35
U33
U34
W38
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
L37
L39
L38
N36
N38
J39
J38
J37
L42
M42
P41
N41
N40
M40
H40
K42
H41
L41
H43
H42
K41
J40
H39
M43

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

CPU_BPRI#
CPU_DEFER#

AA41
AA40

H_BPRI#
H_DEFER#

BCLK_OUT_CPU_P
BCLK_OUT_CPU_N

G42
G41

BCLK_OUT_ITP_P
BCLK_OUT_ITP_N

AL43
AL42

BCLK_OUT_NB_P
BCLK_OUT_NB_N

AL41
AK42

H_D#[0..63] 5

1
@
H_BPRI# 4
H_DEFER# 4

C21
15P_0402_50V8J

CLK_CPU_BCLK
CLK_CPU_BCLK#
PAD
PAD

T21
T24

BCLK_FEEDBACK_P
BCLK_FEEDBACK_N

@
2

BCLK_IN_N
BCLK_IN_P

AK41
AJ40

CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_SMI#

AF41
AH39
AH42
AF42
AG41
AH41

H_A20M#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_SMI#

H_A20M# 4
H_IGNNE# 4
H_INIT# 4
H_INTR 4
H_NMI 4
H_SMI# 4

CPU_PWRGD
CPU_RESET#

AH43
H38

H_PW RGOOD
H_RESET#

H_PWRGOOD 5
H_RESET# 4

CPU_SLP#
CPU_DPSLP#
CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#

AM33
AN33
AM32
AG42
AN32

H_CPUSLP#
H_DPSLP#
H_DPWR#
H_STPCLK#
H_DPRSTP#

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

C25
15P_0402_50V8J

H_CPUSLP# 5
H_DPSLP# 5
H_DPWR# 5
H_STPCLK# 4
H_DPRSTP# 5,38
To +CPU_CORE

MCP79MX-B2 PBGA 1437P

1

Close to AM39 Ball

Compal Secret Data

Security Classification
Issued Date

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

MCP79(1/10)-FRONT SIDE BUS

Size

Document Number

Rev
1.0

LA-4631P
Date:

Sheet

Tuesday, February 24, 2009

1

of

42

DDR_A_DQS#[0..7]

DDR_B_DQS#[0..7]

DDR_A_DQS#[0..7] 17,18

DDR_A_DQS[0..7]
D

DDR_B_DQS#[0..7] 19

DDR_B_DQS[0..7]

DDR_A_DQS[0..7] 17,18

U4B

DDR_B_DQS[0..7] 19
D

U4C
19 DDR_B_D[0..63]

17,18 DDR_A_D[0..63]

AN5
AU5
AR10
AN13
AN27
AW29
AV35
AR34

MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N

AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

MEMORY
PARTITION 0

MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0

MRAS0#
MCAS0#
MWE0#

AV17
AP17
AR17

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

MBA0_2
MBA0_1
MBA0_0

AP23
AP19
AW17

DDR_A_BS2
DDR_A_BS1
DDR_A_BS0

MA0_14
MA0_13
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0

AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19

DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

MCLK0A_2_P
MCLK0A_2_N

AW33
AV33

MCLK0A_1_P
MCLK0A_1_N

BA24
AY24

M_CLK_DDR1
M_CLK_DDR#1

MCLK0A_0_P
MCLK0A_0_N

BB20
BC20

M_CLK_DDR0
M_CLK_DDR#0

MCS0A_1#
MCS0A_0#

AT15
AR18

DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_A_RAS# 17,18
DDR_A_CAS# 17,18
DDR_A_WE# 17,18
DDR_A_BS[0..2] 17,18

DDR_A_MA[0..14] 17,18

T30
2
1
75_0402_1%

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

17,18 DDR_A_DM[0..7]

MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0

R40

MODT0A_1
MODT0A_0

AP15
AV15

M_ODT1
M_ODT0

MCKE0A_1
MCKE0A_0

AU23
AT23

DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

T31
M_CLK_DDR0 17,18
M_CLK_DDR#0 17,18
T34
DDR_CS0_DIMMA# 17,18
T35
M_ODT0

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

AT4
AT3
AV2
AV3
AR4
AR3
AU2
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
BA8
BC8
BB4
BC4
BA7
AY8
BA9
BB10
BB12
AW12
BB8
BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42

MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

AT5
BA2
AY7
BA11
BB34
BB38
AY43
AR42

MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0

19 DDR_B_DM[0..7]

17,18

T36
DDR_CKE0_DIMMA 17,18

MCP79MX-B2 PBGA 1437P

MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N

AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

MRAS1#
MCAS1#
MWE1#

AW16
BA15
BA16

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

MBA1_2
MBA1_1
MBA1_0

BB29
BB18
BB17

DDR_B_BS2
DDR_B_BS1
DDR_B_BS0

MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

BA29
BA14
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18

DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

MCLK1A_2_P
MCLK1A_2_N

BA42
BB42

MCLK1A_1_P
MCLK1A_1_N

BB22
BA22

M_CLK_DDR3
M_CLK_DDR#3

MCLK1A_0_P
MCLK1A_0_N

BA19
AY19

M_CLK_DDR2
M_CLK_DDR#2

MCS1A_1#
MCS1A_0#

BB14
BB16

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#

MODT1A_1
MODT1A_0

BB13
AY15

M_ODT3_DIMMB
M_ODT2_DIMMB

MCKE1A_1
MCKE1A_0

AY31
BB30

DDR_CKE3_DIMMB
DDR_CKE2_DIMMB

MEMORY
PARTITION 1
DDR_B_RAS# 19
DDR_B_CAS# 19
DDR_B_WE# 19
DDR_B_BS[0..2] 19
C

DDR_B_MA[0..14] 19

MEMORY CONTROL 1A

AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5
AN10
AR5
AU6
AV5
AU7
AU8
AW9
AP11
AW6
AY5
AU9
AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35

MEMORY CONTROL 0A

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

M_CLK_DDR3 19
M_CLK_DDR#3 19
B

M_CLK_DDR2 19
M_CLK_DDR#2 19
DDR_CS3_DIMMB# 19
DDR_CS2_DIMMB# 19
M_ODT3_DIMMB 19
M_ODT2_DIMMB 19
DDR_CKE3_DIMMB 19
DDR_CKE2_DIMMB 19

MCP79MX-B2 PBGA 1437P

Compal Secret Data

Security Classification
Issued Date

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

MCP79(2/10)-MEM PARTS 0 & 1

Size

Document Number

Rev
1.0

LA-4631P
Date:

Sheet

Tuesday, February 24, 2009

1

of

42

U4D
D

MCLK1B_2_P
MCLK1B_2_N

BA41
BB41

MCLK0B_1_P
MCLK0B_1_N

MCLK1B_1_P
MCLK1B_1_N

AY23
BA23

BA21
BB21

MCLK0B_0_P
MCLK0B_0_N

MCLK1B_0_P
MCLK1B_0_N

BA20
AY20

AU17
AR15

MCS0B_0#
MCS0B_1#

MCS1B_0#
MCS1B_1#

BC16
BA13

AN17
AN15

MODT0B_0
MODT0B_1

MODT1B_0
MODT1B_1

AY16
BC13

AV23
AN25

MCKE0B_0
MCKE0B_1

MCKE1B_0
MCKE1B_1

BA30
BA31

MEMORY CONTROL 1B

MCLK0B_2_P
MCLK0B_2_N

BB24
BC24

AH27
AG27
AG28

MRESET0#

AY32

GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64

+1.5V

4.77 A
C29

C30

C31

C32

C33

C34

+1.5V
B

C35

C36

C37

C38

C39

C40

C41

C349
0.1U_0402_16V7K

AM17
AM19
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31

0.1U_0402_16V7K

+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8
+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54

0.1U_0402_16V7K

AA22
AP12
G30
P10
T10
T6
V10
V34
W5
AA39
AB22
AB7
AD22
AE20
AF24
AG24
AH35
AK7
AM28
AT25
AP30
AR36
AU10
F28
BC21
AY9
BC9
D34
F24
G32
H31
K7
M38
M5
M6
M7
M9
N39
N8
P33
P34
P37
P4
P40
P7
R36
R40
R43
R5
T18
T20
AK11
T24
T26

0.1U_0402_16V7K

8mil

0.1U_0402_16V7K

0.1U_0402_16V7K

MEM_COMP_GND

C348
2.2U_0402_6.3VM

0.1U_0402_16V7K

MEM_COMP_GND AM41

0.1U_0402_16V7K

2 40.2_0402_1%

DDR_RST# 17,18,19

4.7U_0603_6.3V6K

1 R33

2 DDR_RST#
0_0402_5%

0.1U_0402_16V7K

MEM_COMP_VDD

R537
MRESET0#
+1.5V

4.7U_0603_6.3V6K

MEM_COMP_VDD AN41

0.1U_0402_16V7K

1 40.2_0402_1%

197 mA

10U_0805_10V4Z

+1.5V

2 R34

+V_PLL_CPU

+V_PLL_MCLK
+V_DLL_DLCELL_AVDD
+V_PLL_FSB

8mil

1.05V
This voltage powers the PLLs of DDR2 interfaces.

0.1U_0402_16V7K

MEMORY CONTROL 0B

AU33
AU34

T33
T34
T35
T37
T38
T7
T9
U18
U20
U22

MCP79MX-B2 PBGA 1437P

Compal Secret Data

Security Classification
Issued Date

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

MCP79(3/10)-MEM CNTL 0B&1B

Size

Document Number

Rev
1.0

LA-4631P
Date:

Sheet

Tuesday, February 24, 2009

1

of

42

U4E

F7
E7
D7
C7
E6
F6
E5
F5
E4
E3
C3
D3
G5
H5
J7
J6
J5
J4
L11
L10
L9
L8
L7
L6
N11
N10
N9
P9
N7
N6
N5
N4

Express Card

EXP_CLKREQ#
PEB_PRSNT#

23 EXP_CLKREQ#
23 PEB_PRSNT#

PCIE

C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1

MCP79_PCIE_RST#

C9

PE0_PRSNT_16#

PE0_REFCLK_P
PE0_REFCLK_N

E11
D11

D5
D9

PEB_CLKREQ/GPIO_49#
PEB_PRSNT#

PE1_REFCLK_P
PE1_REFCLK_N

G11
F11

CLK_PCIE_EXPR
CLK_PCIE_EXPR#

PEC_CLKREQ/GPIO_50#
PEC_PRSNT#

PE2_REFCLK_P
PE2_REFCLK_N

J11
J10

CLK_PCIE_LAN
CLK_PCIE_LAN#

WLAN

24 WLAN_CLKREQ#

W LAN_CLKREQ#
PED_PRSNT#

M15
B10

PED_CLKREQ/GPIO_51#
PED_PRSNT#

PE3_REFCLK_P
PE3_REFCLK_N

G13
F13

CLK_PCIE_WLAN
CLK_PCIE_WLAN#

PEE_PRSNT#

L16
L18

PEE_CLKREQ/GPIO_16#
PEE_PRSNT/GPIO_46#

PE4_REFCLK_P
PE4_REFCLK_N

J13
H13

CLK_PCIE_1394
CLK_PCIE_1394#

M16
M18

PEF_CLKREQ/GPIO_17#
PEF_PRSNT/GPIO_47#

PE5_REFCLK_P
PE5_REFCLK_N

L14
K14

M17
M19

PEG_CLKREQ/GPIO_18#
PEG_PRSNT/GPIO_48#

PE6_REFCLK_P
PE6_REFCLK_N

N14
M14

PCIE_WAKE#

F17

PE_WAKE#

PEX_RST0#

K11

MCP79_PCIE_RST#

PCIE_RX0_P
PCIE_RX0_N

K9
J9

PE1_RX0_P
PE1_RX0_N

PE1_TX0_P
PE1_TX0_N

D8
C8

PCIE_TX0_P
PCIE_TX0_N

24 PCIE_RX2_P
24 PCIE_RX2_N

IEEE1394

+VCCP

R52

26 PCIE_RX3_P
26 PCIE_RX3_N

1.1VS

PE1_TX1_P
PE1_TX1_N

B8
A8

F9
E9

PE1_RX2_P
PE1_RX2_N

PE1_TX2_P
PE1_TX2_N

A7
B7

PCIE_TX2_P
PCIE_TX2_N

PCIE_RX3_P
PCIE_RX3_N

H7
G7

PE1_TX3_P
PE1_TX3_N

B6
C6

PCIE_TX3_P
PCIE_TX3_N

C55

C56

C58

+V_PLL_PEX

PE1_RX3_P
PE1_RX3_N

T17
W19
U17
V19
W16
W17
W18
U16

+DVDD0_PEX1
+DVDD0_PEX2
+DVDD0_PEX3
+DVDD0_PEX4
+DVDD0_PEX5
+DVDD0_PEX6
+DVDD0_PEX7
+DVDD0_PEX8

T19
U19

+DVDD1_PEX1
+DVDD1_PEX2

T16

+V_PLL_PEX

161 mA
PE_COMP

2 C67

A11

+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8
+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13

Y12
AA12
AB12
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12

+AVDD1_PEX1
+AVDD1_PEX2
+AVDD1_PEX3

M13
N13
P13
2

PEX_CLK_COMP

LAN

PCIE_TX2_P 24
PCIE_TX2_N 24

WLAN

PCIE_TX3_P 26
PCIE_TX3_N 26

IEEE1394

C60

L11

C61

C62

C63

1
1

+VCCP

BLM21PG221SN1D_0805~D
C64
10U_0805_10V4Z

1.2A
2.2U_0402_6.3VM

IEEE1394

1U_0402_6.3V4Z

WLAN

CLK_PCIE_1394 26
CLK_PCIE_1394# 26

PCIE_TX1_P 22
PCIE_TX1_N 22

1U_0402_6.3V4Z

MCP79MX-B2 PBGA 1437P

LAN

CLK_PCIE_WLAN 24
CLK_PCIE_WLAN# 24

Express Card

0.1U_0402_16V7K

R53
2.37K_0402_1%
@

C59

Express Card

CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22

PCIE_TX0_P 23
PCIE_TX0_N 23

+AVDD_PEX

0.1U_0402_16V7K

2.2U_0402_6.3VM

4.7U_0603_6.3V6K

C57

2 10NH_LQG15HS10NJ02D_5%_0402~D
C66

+DVDD_PEX

1U_0402_6.3V4Z

1U_0402_6.3V4Z

L3 1

0.1U_0402_16V7K

+VCCP

0.1U_0402_16V7K

2.2U

C54
2.2U_0402_6.3VM

PE1_RX1_P
PE1_RX1_N

PCIE_RX2_P
PCIE_RX2_N

430 mA

2 0_0402_5%
2

H9
G9

PCIE_TX1_P
PCIE_TX1_N

22 PCIE_RX1_P
22 PCIE_RX1_N

WLAN

PCIE_RX1_P
PCIE_RX1_N

LAN

PCIE_RST# 22,23,24,26
C43
0.1U_0402_16V7K
@

CLK_PCIE_EXPR 23
CLK_PCIE_EXPR# 23

E8
C10

23 PCIE_RX0_P
23 PCIE_RX0_N

R35 2
0_0402_5%

LAN_CLKREQ#
PEC_PRSNT#

22,23,24,28 PCIE_WAKE#

22 LAN_CLKREQ#

Express Card

1.1VS

PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N

LAN

IEEE1394

PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N

1.1VS

Compal Secret Data

Security Classification
Issued Date

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

MCP79(4/10)-PCI EXPRESS

Size

Document Number

Rev
1.0

LA-4631P
Date:

Sheet

Tuesday, February 24, 2009

1

10

of

42

+3.3VALW_MAC

+3VALW
+1.05VALW_MAC

66 mA

+1.05VS_PLL

21 TI_PRIORITY
21 MCP_DP_CBL_DET
20 MCP79_LCD_PWM
28 MCP79_ENBKL
20,28 MCP79_ENVDD

+1.8VS

21
21

MCP79_DP3+
MCP79_DP3-

21
21
21
21
21
21

MCP79_DP2+
MCP79_DP2MCP79_DP1+
MCP79_DP1MCP79_DP0+
MCP79_DP0-

21
21

MCP79_AUX+
MCP79_AUX-

21 HDMI_HPD
21 MCP_DP_HPD

C83

1
@

R79

2
10U_0805_10V4Z
1 R80

B27

D21
C21

MII_COMP_VDD

RGMII_PWRDWN/GPIO_37

G23

MII_COMP_GND

BUF_25MHZ

E23

MII_RESET#

J23

+V_RGB_DAC
+V_TV_DAC

J32
K32

DDC_CLK0
DDC_DATA0

B31
A31

RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
RGB_DAC_HSYNC
RGB_DAC_VSYNC

B39
A39
B40
A40
A41

C39
B38

RGB_DAC_RSET
RGB_DAC_VREF

E36
A35

TV_DAC_RSET
TV_DAC_VREF

T28
U27

+V_VPLL
+V_PLL_CORE

C38
D38

XTALIN_TV
XTALOUT_TV

TI_PRIORITY
MCP_DP_CBL_DET

E16
B15

GPIO_6/FERR/IGPU_GPIO_6#
GPIO_7/NFERR/IGPU_GPIO_7#

MCP79_LCD_PWM
MCP79_ENBKL
MCP79_ENVDD

G39
E37
F40

LCD_BKL_CTL/GPIO_57
LCD_BKL_ON/GPIO_59
LCD_PANEL_PWR/GPIO_58

MCP79_DP3+
MCP79_DP3-

D35
E35

HDMI_TXC_P/ML0_LANE3_P
HDMI_TXC_N/ML0_LANE3_N

MCP79_DP2+
MCP79_DP2MCP79_DP1+
MCP79_DP1MCP79_DP0+
MCP79_DP0-

G35
F35
F33
G33
J33
H33

HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
HDMI_TXD1_P/ML0_LANE1_P
HDMI_TXD1_N/ML0_LANE1_N
HDMI_TXD2_P/ML0_LANE0_P
HDMI_TXD2_N/ML0_LANE0_N

MCP79_AUX+
MCP79_AUX-

D43
C43

DP_AUX_CH0_P
DP_AUX_CH0_N

C31
F31

HPLUG_DET2/GPIO_22
HPLUG_DET3

2
0_0402_5%

190 mA

+1.8VS_IFP

2.2U
+3VS
R81

16 mA
+VCCP

1
2
2.2U_0402_6.3VM
C84
2
1
0.1U_0402_16V4Z C85
0_0603_1%
+3VS_PLL_HDMI
2

1.1VS

95 mA
1
C89

R82

2
0.1U_0402_16V4Z

2
1

HDMI_RSET
HDMI_VPROBE

M27
M26

+VDD_IFPA
+VDD_IFPB

M28
M29

+V_PLL_IFPAB
+V_PLL_HDMI

T25

+VDD_HDMI

J31
J30

HDMI_RSET
HDMI_VPROBE

C90
@

R1262 1

10K_0402_5%

PHY_25MHZ_R

@R71

2
4.7U_0603_6.3V6K

10K_0402_5%

2 22_0402_5%

PHY_25MHZ 22

+3VS

LCD_DDC_CLK
LCD_DDC_DATA

R163

LCD_DDC_CLK 20
LCD_DDC_DATA 20

PHY_25MHZ
@ 1
C309
2

TV_DAC_RED
TV_DAC_GREEN
TV_DAC_BLUE
TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45

A36
B36
C36
D36
C37

+3VS

R186

LCD_DDC_CLK
LCD_DDC_DATA

1.1VS
C

+1.05VS_PLL
+VCCP

FLAT

IFPA_TXC_P
IFPA_TXC_N

B35
C35

LVDSAC+
LVDSAC-

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

B32
A32
D32
C32
D33
C33
B34
C34

LVDSA0+
LVDSA0LVDSA1+
LVDSA1LVDSA2+
LVDSA2-

IFPB_TXC_P
IFPB_TXC_N

L31
K31

LVDSBC+
LVDSBC-

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N

J29
H29
L29
K29
L30
K30
N30
M30

LVDSB0+
LVDSB0LVDSB1+
LVDSB1LVDSB2+
LVDSB2-

DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24

C30
B30

SCL_DP_MCP
SDA_DP_MCP

DDC_CLK3
DDC_DATA3

D31
E31

SCL_HDMI_MCP
SDA_HDMI_MCP

IFPAB_RSET
IFPAB_VPROBE

E32
G31

IFPAB_RSET @ R83
IFPAB_VPROBE@ C91

LVDSAC+ 20
LVDSAC- 20
LVDSA0+
LVDSA0LVDSA1+
LVDSA1LVDSA2+
LVDSA2-

C176

20
20
20
20
20
20

LVDSBC+ 20
LVDSBC- 20
LVDSB0+
LVDSB0LVDSB1+
LVDSB1LVDSB2+
LVDSB2-

C175

L13
2
10NH_LQG15HS10NJ02D_5%_0402~D

Signal : TXD0_R
Strap: Networking select
Strapped Value : 0: MII 1: RGMII
Description : Selects an MII interface or an RGMII interface for MAC.

20
20
20
20
20
20

SCL_DP_MCP 21
SDA_DP_MCP 21

+3VALW

1.1VALW_MAC

SCL_HDMI_MCP 21
SDA_HDMI_MCP 21
1
1

+1.05VALW

2 1K_0402_1%
0.1U_0402_16V4Z

R1307
20K_0402_1%

20 mil

MCP79MX-B2 PBGA 1437P

1

C86
1
1 C87
C448

1K_0402_1% 1

2.2U_0402_6.3VM

2.2U_0402_6.3VM

1
C88

4.7U_0603_6.3V6K
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

14 SLP_RMGT#

R1308
0_0402_5%

1 @
C656

@
1
R1311
0_0402_5%

28 SLP_MCP79_MAC#

+1.05VALW_MAC

S
+1.05VALW_MAC1

20 mil

+3VALW

1
R1309
10K_0402_5%

Issued Date

2009/02/19

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

2
1

Compal Secret Data

Security Classification

20 mil

R1310
0_0402_5%
1
2

2
G
3

1
R1269
2

10K_0402_5%

1
R1268
2

10K_0402_5%

10K_0402_5%

1
R1267
2

1
R1266
2

10K_0402_5%

10K_0402_5%

1
R1265
2

1
R1264
2

10K_0402_5%

10K_0402_5%

+3VALW

@ 1
Q69
C658
2N7002_SOT23

0.01U_0402_25V7K

R1263
2

C657
0.1U_0402_16V4Z

RGMII_INT
RXCTL
RXCLK
RXD3
RXD2
RXD1
RXD0

1.1VALW_MAC

AO3416_SOT23
Q67

2
G

0.01U_0402_25V7K

Q68
AO3413_SOT23

DACS

PANEL
2 0_0603_1%

1
RGMII_MDC
RGMII_MDIO

R67

R1279
22K_0402_5%

MCP79_ENVDD

+V_DUAL_MACPLL

R63
10K_0402_5%
TXCLK_R

2
1
2.7K_0402_5%

+1.05VS_PLL

RGMII_INTR/GPIO_35

C27

+3.3VALW_MAC_REF

2.2U_0402_6.3VM

+MII_COMP_VDD
2
49.9_0402_1%
1
2 MII_COMP_GND
R70
49.9_0402_1%

2
1
2.7K_0402_5%

E28
B24
C24
C25
D25
D24
C26

0_0603_1%
2
@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2.2U_0402_6.3VM

R69

+3.3VALW_MAC

J22
T23

MII_VREF
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
RGMII_TXC/MII_TXCLK
RGMII_TXCTL/MII_TXEN

C72

C76

+V_DUAL_MACPLL

MII_RXER/GPIO_36
MII_COL/GPIO_20/MSMB_DATA
MII_CRS/GPIO_21/MSMB_CLK

+V_DUAL_RMGT1
+V_DUAL_RMGT2

RGMII_INT

9 mA

LAN

U23
V23

C71

0.1U_0402_16V4Z

R61

L4

F23
B26
B22

RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
RGMII_RXC/MII_RXCLK
RGMII_RXCTL/MII_RXDV

R57
1

264 mA +1.05VALW_MAC_R

BLM18AG121SN1D_0603

+1.05VALW_MAC

C23
B23
E24
A24
A23
C22

J24
K24

0.1U_0402_16V4Z

RXD0
RXD1
RXD2
RXD3
RXCLK
RXCTL
47K_0402_5%
1
2

+3.3V_DUAL_RMGT1
+3.3V_DUAL_RMGT2

0.1U_0402_16V4Z

1.1VALW_MAC

1
C75

264 mA

U4F

R1306
0_0603_1%

2.2U

+3.3VALW_MAC_R
1
C69
C70

4.7U_0603_6.3V6K

@R55
1K_0402_5%
1
1

@ R54
1K_0402_5%

+1.05VALW

2
2

R1301
0_0603_1%

@
R1302
0_0603_1%

1.1VALW
MCP79_AUXMCP79_AUX+

+3.3VALW_MAC

20 mil

Compal Electronics, Inc.

MCP79(5/10)-LAN,RGB,TV,LVD

Size

Document Number

R ev
1.0

LA-4631P
Date:

Tuesday, February 24, 2009

1

Sheet

11

of

42

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
HB_PWR_EN
PCI_REQ#4

T2
V9
T3
U9
T4
AC3
AE10
AC4
AE11
AB3
AC6
AB2
AC7
AC8
AA2
AC9
AC10
AC11
AA1
AA5
Y5
W3
W6
W4
W7
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
T5
U7

+3VS

1
1
1
1

R99
R124
R138
R140

1 R147

2
2
2
2

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

2 8.2K_0402_5%

SERIRQ

P2
N3
N2
N1

PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#

PCI_TRDY#

Y3

PCI_TRDY#

SERIRQ

AE2
AE1
AE6
U24
U26
U39
U4
U8
V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37
V4
V40
V7
W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
Y24
Y25

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

AD11

28

PCI_REQ0#
PCI_REQ1/FANRPM2#
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_GNT0#
PCI_GNT1/FANCTL2#
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#

AA3
AA6
AA11
W10

PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_SERR#
PCI_STOP#

AA9
Y4
AA10
Y1
AB9
AA7
Y2

PCI

PCI_PME/GPIO_30#
PCI_RESET0#
PCI_RESET1#

PCI_DEVSEL# 8.2K_0402_5% 1 R148

PCI_FRAME# 8.2K_0402_5% 1 R150
PCI _IRDY#
8.2K_0402_5% 1 R158

2
2
2

PCI_PERR#
PCI_SERR#
PCI_STOP#

2
2
2

8.2K_0402_5% 1 R188
8.2K_0402_5% 1 R189
8.2K_0402_5% 1 R190

T1

R6
R7
R8

1
R96
PCI_CLK2

PCI_CLKIN

R9

PCI_CLKIN

2
0_0402_5%

AD4
AE12

R104 1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

AD3
AD2
AD1
AD5

R_LPC_AD0
R_LPC_AD1
R_LPC_AD2
R_LPC_AD3

LPC_CLK0

AE9

LPC_CLK0_R

GND

R_LPC_FRAME#

LPC_RESET0#

GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130

+3VS

Y26
Y27
AB18
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
AD28
AD33
AD34

1 R100
2
22_0402_5%

AE5

LPC_DRQ1/GPIO_19#
LPC_DRQ0#
LPC_SERIRQ

T9

C95

LPC

0
(R196)
0
(R196)

PCI_PME# HAS INTERNAL PULLUP

PCI_CLK0
PCI_CLK1
PCI_CLK2

LPC_FRAME#
LPC_PWRDWN#/GPIO_54/EXT_NMI#

53

0
(R194)
1
(R191)

R10
R11

PCI_CLKRUN/GPIO_42#

GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97

R3
U10
R4
U11
P3

Samsung 1G

41

1
(R192)
0
(R195)

1 R101
2
22_0402_5%

2
33_0402_5%
R105
R107
R108
R109

1
1
1
1

LPC_FRAME#

LPC_FRAME# 24,28

PLT_RST# 24,28
2
2
2
2

1 R110
2
22_0402_5%

22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%
LPC_CLK0

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

2
2
2
2
2

Hynix 1G

39

R106
10K_0402_5%

24,28
24,28
24,28
24,28

R94
R95
R92
R98
R97

10P_0402_50V8J

1
1
1
1
1

+3VS

GPIO

X76L01@X76L02@
R193
R196 2
1
1
2
8.2K_0402_5% 8.2K_0402_5%

U4G

X76L02@
X76L01@
R195 2
R192 2
1
1
8.2K_0402_5% 8.2K_0402_5%

X76L02@
X76L01@
R191
R194 2
1
1
2
8.2K_0402_5% 8.2K_0402_5%

+3VS

LPC_CLK0 24,28

1 @

HDA_SDATA_OUT (MSB)
LPC_FRAME# (LSB)

C96
10P_0402_50V8J

00: Boot ROM

01: Boot ROM
10: Boot ROM
(SPI_CS0)
11: Boot ROM
(SPI_CS1)

located on LPC bus

located on PCI bus
located on SPI bus

located on SPI bus

MCP79MX-B2 PBGA 1437P

Compal Secret Data

Security Classification
Issued Date

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

MCP79(6/10)-PCI & LPC

Size

Document Number

Rev
1.0

LA-4631P
Date:

Sheet

Tuesday, February 24, 2009

1

12

of

42

U4H
20 SATA_A0_TXP
20 SATA_A0_TXN

SATA HDD

20 SATA_A0_RXN
20 SATA_A0_RXP

29 SATA_A1_TXP
29 SATA_A1_TXN

ESATA

29 SATA_A1_RXN
29 SATA_A1_RXP

SATA_A0_TXP
SATA_A0_TXN

AJ7
AJ6

SATA_A0_RXN
SATA_A0_RXP

AJ5
AJ4

SATA_A0_TX_P
SATA_A0_TX_N
SATA_A0_RX_N
SATA_A0_RX_P

SATA_A1_TXP
SATA_A1_TXN

AJ11
AJ10

SATA_A1_TX_P
SATA_A1_TX_N

SATA_A1_RXN
SATA_A1_RXP

AJ9
AK9

SATA_A1_RX_N
SATA_A1_RX_P

AK2
AJ3

SATA_B0_TX_P
SATA_B0_TX_N

AJ2
AJ1

SATA_B0_RX_N
SATA_B0_RX_P

SATA
C

USB

USB0_P
USB0_N

C29
D29

USB20_P0
USB20_N0

USB1_P
USB1_N

C28
D28

USB20_P1
USB20_N1

USB2_P
USB2_N

A28
B28

USB20_P2
USB20_N2

USB3_P
USB3_N

F29
G29

USB20_P3
USB20_N3

USB4_P
USB4_N

K27
L27

USB20_P4
USB20_N4

USB5_P
USB5_N

J26
J27

USB20_P5
USB20_N5

USB6_P
USB6_N

F27
G27

USB20_P6
USB20_N6

USB7_P
USB7_N

D27
E27

USB20_P7
USB20_N7

USB8_P
USB8_N

K25
L25

USB20_P8
USB20_N8

USB9_P
USB9_N

H25
J25

AM4
AL3

SATA_B1_TX_P
SATA_B1_TX_N

USB10_P
USB10_N

F25
G25

AL4
AK3

SATA_B1_RX_N
SATA_B1_RX_P

USB11_P
USB11_N

K23
L23

AN1
AM1

SATA_C0_TX_P
SATA_C0_TX_N

AM2
AM3

SATA_C0_RX_N
SATA_C0_RX_P

USB20_P0 27
USB20_N0 27

USB0

USB20_P1 29
USB20_N1 29

USB1

USB20_P2 29
USB20_N2 29

USB2

USB20_P3 23
USB20_N3 23

Express Card

USB20_P4 27
USB20_N4 27

Camera

USB20_P5 27
USB20_N5 27

BlueTooth

USB20_P6 24
USB20_N6 24

WWAN

USB20_P7 24
USB20_N7 24

WLAN

T26
T27

+5VALW

1.1VS
+3VS

G26
H27
J28
K28

200 mA

SATA_C1_RX_N
SATA_C1_RX_P

E12

SATA_LED#

A27

2
R113
0_0603_1%

+3.3V_DUAL_USB

+DVDD_SATA

1
L9

BLM18AG121SN1D_0603

C107

136 mA

C111

C452
0.1U_0402_16V7K

C110

SATA_TERMP

+V_PLL_SATA

AF19
AG16
AG17
AG19

+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4

AH17
AH19

+DVDD1_SATA1
+DVDD1_SATA2

AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13

+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9

AN14
AL14
AM13
AM14

+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4

AE3

USB_RBIAS

SATA_TERMP

AD35
AD37
AD38
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24

R116
806_0402_1%

C104 C105

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

1
2

C98

C99

MCP79MX-B2 PBGA 1437P

0.1U_0402_16V7K

0.1U_0402_16V7K

2.2U_0402_6.3VM

+AVDD_SATA
1
2
C108
C109

0.1U_0402_16V7K

+VCCP

2.2U_0402_6.3VM

2
C106

AE16

GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160

2.2U_0402_6.3VM

53 mA

10U_0805_10V4Z

AN3
AN2

USB_RBIAS_GND

1.1VS

2
C97
1

R78 1
R103 1
R111 1

4.7U_0603_6.3V6K

+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4

SATA_C1_TX_P
SATA_C1_TX_N

2.2U_0402_6.3VM

4.7U_0603_6.3V6K

2
C101

R115
0_0603_1%
B

+V_PLL_USB

+V_PLL_SATA
C100

+VCCP

L28

+3VALW

AP3
AP2

USB_OC#0
USB_OC#2
USB_OC#1

L7
BLM18AG121SN1D_0603

18 mA

2.2U

81 mA

1.1VS

+V_PLL_USB

USB_OC#0 27
USB_OC#1 29
USB_OC#2 29
PM_EXTTS#0_1 19

0.1U_0402_16V7K

10NH_LQG15HS10NJ02D_5%_0402~D

L21
K21
J21
H21

2.2U_0402_6.3VM

L8

USB_OC#0
USB_OC#1
USB_OC#2
PM_EXTTS#0_1

USB_OC0/GPIO_25#
USB_OC1/GPIO_26#
USB_OC2/GPIO_27/MGPIO#
USB_OC3/GPIO_28/MGPIO#

4.7U_0603_6.3V6K

+VCCP

R117

2.49K_0402_1%
A

Compal Secret Data

Security Classification
Issued Date

2009/02/19

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

MCP79(7/10)-SATA & USB

Size

Document Number

R ev
1.0

LA-4631P
Date:

Tuesday, February 24, 2009

1

Sheet

13

of

42

+3VS

+3VS

U8 @

NC

SSON

NC

GND

SS

For Audio code use

ASM3P623S00BF-08TR_TSSOP8

+3VALW

@
R122
10K_0402_5%

HDA_SDOUT

R130
L10
HDA_RESET#

K15

HDA_RESET#

HDA_SYNC
HDA_DOCK_EN/GPIO_4/PS2_MS_CLK#
HDA_DOCK_RST/GPIO_5/PS2_MS_DATA#

L15
K17
L17

H DA_SYNC

1
2

G17
J17
H17

PWRBTN#
R152

+3VALW

R151 2 @

PWRBTN#
10K_0402_5%

RTC_RST#

1
2
49.9K_0402_1%

+RTCVCC

0_0402_5%
2

Close to RAM door

28 EC_RSMRST#
28 MCP_PWRGD

JCMOS1 @
1
2

28,38

NO SHORT PAD

VGATE

T25
T16
T28
R159 2
R160 2

C126 @
1
2
1U_0402_6.3V4Z

PAD
PAD
PAD

1 10K_0402_5%
1 10K_0402_5%

LID#
LLB#

M22

CPU_DPRSLPVR

C16
D16

PWRBTN#
RSTBTN#

C20

RTC_RST#

D20
E20

PWRGD_SB
PS_PWRGD

C17

CPU_VLD

E19
F19
J19
J18
G19

JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
JTAG_TCK

MISC

C13

SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT/GPIO_64#

L19
K19
G21
F21
M23

FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62

B12
A12
D12
C12

CPUVDD_EN

D17

SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9

C14
D13
C15
B14

MCP_SPKR

R142

MCP_SPKR 25

HD Audio Codec
MCP_SMB_CLK
MCP_SMB_DATA

R143

R144

+3VALW
EC_LID_OUT#
EC_LID_OUT# 28
R153
+3VALW
@10K_0402_5%
2 R156
1VR_ON
VR_ON 28,38
0_0402_5%
ENABLE +1.05V POWER
R_ACIN 2
1
ACIN
28,32,33
SDMK0340L-7-F
D4

XTALIN
XTALOUT

A19
B19

XTALIN_RTC
XTALOUT_RTC

1
C129

15P_0402_50V8J
X2
2

XTAOUT_RTC_R

NC

IN

AE7

TEST_MODE_EN
PKG_TEST

K22
L22

MCP79MX-B2 PBGA 1437P

3 NC
OUT 4
R549
0_0402_5%~D
32.768KHZ 1TJS125BJ4A421P
2
1XTAOUT_RTC 1
2

2 R296
1
0_0402_5%

T32 PAD

EC

BUF_SIO_CLK

SUS_CLK_R

R162

R164
1K_0402_1%

A20GATE,KBRDRSTIN*, RI* & EXTSMI*

HAVE INTERNAL PULLUPS

1
EC_KBRST#
1

220P_0402_50V7K 2

@
C453

SPKR
0 = User Mode Boot Init table
1 = Safe Mode Boot Init table
Suggest use user mode.

@ C131
2 0.1U_0402_16V4Z

U9
8
7
6
5

MCP_SMB_CLK
MCP_SMB_DATA
1

220P_0402_50V7K 2

+3VALW

@ R165
EC_GA20
1

@
D3
PJDLC05_SOT23

T33 PAD

12P_0402_50V8J
C130

@
C454

+3VALW

25MHZ 12PF 30PPM

C128
10P_0402_50V8J

10P_0402_50V8J

A16
B16

XTALIN_RTC

C127
1
2

MCP_SMB_CLK 24
MCP_SMB_DATA 24
MEM_SMBCLK 18,19
MEM_SMBDATA 18,19

XTALOUT
X1
1

B18

R146

R154
R155
332K_0402_1%
@

@ R161

SUS_CLK/GPIO_34

R145

MEM_SMBCLK
MEM_SMBDATA
SMB_ALERT#

XTALIN
2 XTALOUT_R
R534
0_0402_5%~D

R139
10K_0402_5%
2

SPKR

MCP_CORE_VID0 36
MCP_CORE_VID1 36
MCP_CORE_VID2 36

28

DPRSLPVR

INTRUDER#

L20
M20
M21

MCP_SPKR

+3VALW

R149
38

B20
M25
M24

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15

+3VS

R137
C
10K_0402_5%
@

10K_0402_5%

INTRUDER#

2
49.9K_0402_1%

+3VALW

10K_0402_5%

1
R141

LID_SW#

A20GATE
KBRDRSTIN#
SIO_PME#
EXT_SMI/GPIO_32#

+RTCVCC
28

GPIO_12/SUS_STAT/ACCLMTR_EXT_TRIG#

2
EC_SCI#
EC_SMI#

L26
K13
L13
C19
C18

1
2
2.2K_0402_5%

28
28

EC_GA20
EC_KBRST#

EC_GA20
EC_KBRST#

1
2
2.2K_0402_5%

28
28

B11
C11

THERM_DIODE_P
THERM_DIODE_N

+3VS

R136

GPIO_1/PWRDN_OK/SPI_CS1

R135

2
1
2.7K_0402_5%

L24

R134

22K_0402_5%

PM_SLP_S3# 28
SLP_RMGT# 11
PM_SLP_S5# 28

22K_0402_5%

SLP_S3#
SLP_RMGT#
SLP_S5#

PLACE 0.1UF NEAR AE18 and AE17 BALL

+V_PLL_NV_H
+V_PLL_XREF_XS
+V_PLL_SP_SPREF

AE18
T27
AE17

ACZ_SYNC 25

@
C121
10P_0402_50V8J

C125

R133

10K_0402_5%

ACZ_RST# 25

@ R166

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

@ AT24C16AN-10SI-2.7_SO8
10K_0402_5%

C124

2.2U_0402_6.3VM

C123

2.2U_0402_6.3VM

4.7U_0603_6.3V6K

C81

0.1U_0402_10V6K

0.1U_0402_10V6K

@ 1
C120

ACZ_BITCLK 25

1R132
2
22_0402_5%

+1.05VS_PLL

+V_PLL_NV
C82

HDA_PULLDN_COMP

A15

R129
R131
1
2
22_0402_5%

1
2
2.2K_0402_5%

92 mA

1
2
2.2K_0402_5%

49.9_0402_1%
10NH_LQG15HS10NJ02D_5%_0402~D

R128

ACZ_SDOUT 25

ACZ_BITCLK
+3VALW

HDA

EMI_HD_IN 2
1
0_0402_5%

ACZ_SDOUT

E15

C1191

10K_0402_5%

R127
HDA_BITCLK

1
2
R125 22_0402_5%
1
2
R126 22_0402_5%

HDA_BITCLK
C1181

F15

HDA_SDATA_OUT

22K_0402_5%

J16
K16

HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA

+3VALW

+V_DUAL_HDA1
+V_DUAL_HDA2

4.7U_0603_6.3V6K

HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK

J15

+VCCP

HDA_SDATA_IN0

J14

C114

2
1
10P_0402_50V8J @ C116
2
1
10P_0402_50V8J @ C117

1.1VS

G15

10P_0402_50V8J

ACZ_SDIN0
2
1
10P_0402_50V8J @ C115

25 ACZ_SDIN0

C113

10P_0402_50V8J

U4I

0.1U_0402_16V7K

C455

0.1U_0402_16V7K

20 mA
2

R119
@ 10K_0402_5%

CLKOUT

CLKIN

10K_0402_5%

VDD

10P_0402_50V8J

1
@
C112
0.1U_0402_16V4Z
2

@ R197
1 EMI_HD_IN_D 2
1EMI_HD_IN
0_0402_5%
2

22K_0402_5%

HDA_BITCLK

10K_0402_5%

@
R118
10K_0402_5%

HDCP 2-WIRE ROM

Compal Secret Data

Security Classification
Issued Date

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

MCP79(8/10)-HDA & MISC

Size

Document Number

R ev
1.0

LA-4631P
Date:

Sheet

Tuesday, February 24, 2009

1

14

of

42

0.75V ~ 1.05 V

0.1U_0402_16V7K

C165

RTC Battery

+COINCELL

RTCVREF

3 2

R536
1K_0402_5%~D

B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
G36
G37
G38
H35
H37
J34
J35
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32
AB32

+VTT_CPUCLK

AG32

+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8

AD10
AE8
AB10
AD9
Y10
AB11
AA8
Y9

POWER

+RTCVCC

C248

C177

A20

0.1U_0402_16V7K

C249

4.7U_0603_6.3V6K

C541
1U_0603_10V4Z~D

4.7U_0603_6.3V6K

3 mA

+RTCVCC

D17
BAT54CW_SOT323~D
1

+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3

T21
U21
V21

+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4

G18
H19
J20
K20

C149

C150

C151

R167
0_0603_1%

368 mA

+3.3V_MCP79

C166

C167

C168

C169

C170

139 mA

+VDD_AUXC
C171
0.1U_0402_16V7K

1.1VALW
+1.05VALW

1 R168
2
0_0402_5%

C172
0.1U_0402_16V7K

+3VALW
+3.3V_DUAL

33 mA
2

1 R170
2
0_0402_5%

C174
0.1U_0402_16V7K

MCP79MX-B2 PBGA 1437P

A

Issued Date

Compal Secret Data

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

+3VS

Security Classification

C148

10U_0805_10V4Z

C147

4.7U_0603_6.3V6K

0.1U_0402_16V7K

C146

C173
4.7U_0603_6.3V6K

+VBAT

C145
0.1U_0402_16V7K

C144
0.1U_0402_16V7K

C143
0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V4Z
2

+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52
+VTT_CPU53

+VCCP
2

4.7U_0603_6.3V6K

C164

C158

R32
AC32
E40
J36
N32
T32
U32
V32
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V4Z
0.1U_0402_16V7K

1U_0402_6.3V4Z
1

C163

C157

+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8
+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18

0.1U_0402_16V7K

+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81

0.1U_0402_16V7K

C162

C156

AA25
AC23
U25
AH12
AG10
AG5
Y21
Y23
AA16
AA26
AA27
AA28
AC16
AC17
AC18
AC19
AC20
AC21
AA17
AC24
AC25
AC26
AC27
AC28
AD21
AD23
W27
V25
AA18
AE19
AE21
AE23
AE25
AE26
AE27
AE28
AF10
AF11
AA19
AF2
AF21
AF23
AF25
AF3
AF4
AF7
AH23
AF9
AA20
AG11
AG12
AG21
AG23
AG25
AG3
AG4
AA21
AG6
AG7
AG8
AG9
AH1
AH10
AH11
W26
AH2
AA23
W28
AH25
AH21
AH3
AH4
AH5
AH6
AH7
AH9
AA24
W21
W23
W25
AF12

C142

0.1U_0402_16V7K

C141

0.1U_0402_16V7K

C161

0.1U_0402_16V7K

4.7U_0603_6.3V6K

C155

C140

0.1U_0402_16V7K

C154

0.1U_0402_16V7K

C139

1.25A

1U_0402_6.3V4Z

0.22U_0402_6.3V6K

C160

80mil

1U_0402_6.3V4Z

0.22U_0402_6.3V6K

C153

U4J

11.6 A

0.1U_0402_16V7K

C159
0.1U_0402_16V7K

2
C

C138

+
2

0.1U_0402_16V7K

C152

0.1U_0402_16V7K

0.1U_0402_16V7K

C137

0.1U_0402_16V7K

1
C136

10U_0805_10V4Z

0.1U_0402_16V7K

1
C135

0.1U_0402_16V7K

1
C134

330U_D2E_2.5VM_R9

1
C133

4.7U_0603_6.3V6K

1
C132
0.22U_0402_6.3V6K

+1.0VS

Title

Compal Electronics, Inc.

MCP79(9/10)-POWER&RTC Batt

Size

Document Number

Rev
1.0

LA-4631P
Date:

Sheet

Thursday, February 19, 2009

1

15

of

42

U4K
D

AH26
AH33
AH34
AH37
AH38
AJ39
AJ8
AK10
AK33
AK34
AK37
AK4
AK40
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
AP26
AN28
AN30
AN39
AN4
Y7
AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37
AP4
AP40
AP7
AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28
AP33
AU32
AR30
AU36
AU38
AU4
G28
F20
AV28
AV32
AV36
AV4
AV7
AW11
G20
AR43
AW43
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41

GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207
GND208
GND209
GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219
GND220
GND221
GND222
GND223
GND224
GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232
GND233
GND234
GND235
GND236
GND237
GND238
GND239
GND240
GND241
GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250
GND251
GND252

GND

GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301
GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341
GND342
GND343

AV40
BA1
BA4
AW31
AY6
L35
BC33
BC37
BC41
AY14
BC5
C2
D10
D14
D15
D18
D19
D22
D23
D26
D30
D37
D6
E13
E17
E21
E25
E29
E33
F12
F16
F32
F8
G10
G12
G14
G16
BC12
G22
G24
AW20
G34
G4
G43
G6
G8
H11
H15
AW35
H23
AN8
G40
J12
J8
K10
K12
K18
K26
K37
K4
K40
K8
AU1
L40
L43
L5
M10
M34
M35
M37
Y28
Y33
Y34
Y35
Y37
Y38
AB17
AB16
AN26
AD7
M11
AA4
AB19
AY13
P11
Y6
T11
V11
Y11
AH16
T22

MCP79MX-B2 PBGA 1437P

A

Compal Secret Data

Security Classification
Issued Date

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

MCP79(10/10)-GND

Size

Document Number

Rev
1.0

LA-4631P
Date:

Sheet

Thursday, February 19, 2009

1

16

of

42

+1.5V

U10
8 DDR_A_DQS0
8 DDR_A_DQS#0
8 DDR_A_D[0..7]

DDR_A_D1
DDR_A_D7
DDR_A_D0
DDR_A_D6
DDR_A_D4
DDR_A_D3
DDR_A_D5
DDR_A_D2

C4
D4

DQS
DQS#

B4
C8
C3
C9
E4
E9
D3
E8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A8
B8
H9
2
240_0402_5%~D
E2
+V_DDR_MCH_REF
J9

8 DDR_A_DM0
1
R171

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_MA14

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4

J8
F10
H2
F2
H10
A1
N8
A11
A4
N1
N11

NU/TDQS#
DM/TDQS
ZQ

VDDQ
VDDQ
VDDQ
VDDQ

B10
C2
E3
E10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A3
A10
D8
G3
G9
K2
K10
M2
M10

ODT
CK
CK#
CKE

VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

DDR_A_D21
DDR_A_D18
DDR_A_D17
DDR_A_D19
DDR_A_D22
DDR_A_D16
DDR_A_D20
DDR_A_D23

C4
D4

DQS
DQS#

B4
C8
C3
C9
E4
E9
D3
E8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A8
B8
8 DDR_A_DM2
H9
1
2
M_ODT0
R172
240_0402_5%~D
M_CLK_DDR0
E2
+V_DDR_MCH_REF
M_CLK_DDR#0
J9
DDR_CKE0_DIMMA
DDR_A_MA0
K4
DDR_A_BS0
DDR_A_MA1
J3
L8
DDR_A_BS1
DDR_A_MA2
K9
L4
DDR_A_BS2
DDR_A_MA3
J4
K3
DDR_A_MA4
L9
DDR_CS0_DIMMA#
DDR_A_MA5
H3
L3
DDR_A_RAS#
DDR_A_MA6
F4
M9
DDR_A_MA7
G4 DDR_A_CAS#
M3
DDR_A_WE#
DDR_A_MA8
H4
N9
DDR_RST#
DDR_A_MA9
N3
M4
DDR_A_MA10
H8
DDR_A_MA11
B3
M8
DDR_A_MA12
B9
K8
DDR_A_MA13
C10
N4
D2
D10
A2
A9
J8
B2
F10
F3
H2
F9
F2
D9
H10
J2
A1
DDR_A_MA14
J10
N8
L2
A11
L10
A4
N2
N1
N10
N11

VDDQ
VDDQ
VDDQ
VDDQ

B10
C2
E3
E10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A3
A10
D8
G3
G9
K2
K10
M2
M10

NU/TDQS#
DM/TDQS
ZQ

ODT
CK
CK#
CKE

VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

+1.5V

U12
8 DDR_A_DQS4
8 DDR_A_DQS#4
8 DDR_A_D[32..39]

DDR_A_D39
DDR_A_D34
DDR_A_D32
DDR_A_D35
DDR_A_D36
DDR_A_D33
DDR_A_D37
DDR_A_D38

C4
D4

DQS
DQS#

B4
C8
C3
C9
E4
E9
D3
E8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A8
B8
8 DDR_A_DM4
H9
1
2
M_ODT0
R173
240_0402_5%~D
M_CLK_DDR0
E2
+V_DDR_MCH_REF
M_CLK_DDR#0
J9
DDR_CKE0_DIMMA
DDR_A_MA0
K4
DDR_A_BS0
DDR_A_MA1
J3
L8
DDR_A_BS1
DDR_A_MA2
K9
L4
DDR_A_BS2
DDR_A_MA3
J4
K3
DDR_A_MA4
L9
DDR_CS0_DIMMA#
DDR_A_MA5
H3
L3
DDR_A_RAS#
DDR_A_MA6
F4
M9
DDR_A_MA7
G4 DDR_A_CAS#
M3
DDR_A_WE#
DDR_A_MA8
H4
N9
DDR_RST#
DDR_A_MA9
N3
M4
DDR_A_MA10
H8
DDR_A_MA11
B3
M8
DDR_A_MA12
B9
K8
DDR_A_MA13
C10
N4
D2
D10
A2
A9
J8
B2
F10
F3
H2
F9
F2
D9
H10
J2
A1
DDR_A_MA14
J10
N8
L2
A11
L10
A4
N2
N1
N10
N11

VDDQ
VDDQ
VDDQ
VDDQ

B10
C2
E3
E10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A3
A10
D8
G3
G9
K2
K10
M2
M10

ODT
CK
CK#
CKE

G2
F8
G8
G10

NU/TDQS#
DM/TDQS
ZQ

G2
F8
G8
G10

VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

+1.5V

U13
8 DDR_A_DQS6
8 DDR_A_DQS#6
8 DDR_A_D[48..55]

DDR_A_D54
DDR_A_D51
DDR_A_D49
DDR_A_D50
DDR_A_D52
DDR_A_D48
DDR_A_D53
DDR_A_D55

C4
D4

DQS
DQS#

B4
C8
C3
C9
E4
E9
D3
E8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A8
B8
8 DDR_A_DM6
H9
1
2
M_ODT0
R174
240_0402_5%~D
M_CLK_DDR0
E2
+V_DDR_MCH_REF
M_CLK_DDR#0
J9
DDR_CKE0_DIMMA
DDR_A_MA0
K4
DDR_A_BS0
DDR_A_MA1
J3
L8
DDR_A_BS1
DDR_A_MA2
K9
L4
DDR_A_BS2
DDR_A_MA3
J4
K3
DDR_A_MA4
L9
DDR_CS0_DIMMA#
DDR_A_MA5
H3
L3
DDR_A_RAS#
DDR_A_MA6
F4
M9
DDR_A_MA7
G4 DDR_A_CAS#
M3
DDR_A_WE#
DDR_A_MA8
H4
N9
DDR_RST#
DDR_A_MA9
N3
M4
DDR_A_MA10
H8
DDR_A_MA11
B3
M8
DDR_A_MA12
B9
K8
DDR_A_MA13
C10
N4
D2
D10
A2
A9
J8
B2
F10
F3
H2
F9
F2
D9
H10
J2
A1
DDR_A_MA14
J10
N8
L2
A11
L10
A4
N2
N1
N10
N11

VDDQ
VDDQ
VDDQ
VDDQ

B10
C2
E3
E10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A3
A10
D8
G3
G9
K2
K10
M2
M10

ODT
CK
CK#
CKE

G2
F8
G8
G10

M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

BA0
BA1
BA2

J3
K9
J4

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

CS#
RAS#
CAS#
WE#
RESET#

H3
F4
G4
H4
N3

DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_RST#

NU/TDQS#
DM/TDQS
ZQ
VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

H5TQ1G83AFP-G7C FBGA 78P

H5TQ1G83AFP-G7C FBGA 78P

H5TQ1G83AFP-G7C FBGA 78P

H5TQ1G83AFP-G7C FBGA 78P

X76@

X76@

X76@

X76@

+1.5V

B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10

+1.5V
+V_DDR_MCH_REF

M_ODT0

0.1U_0402_16V4Z~D

C204
0.1U_0402_16V4Z~D

C203
0.1U_0402_16V4Z~D

C202
0.1U_0402_16V4Z~D

C201
0.1U_0402_16V4Z~D

C200
0.1U_0402_16V4Z~D

C199
0.1U_0402_16V4Z~D

C198
0.1U_0402_16V4Z~D

C197
2.2U_0603_6.3V6K~D

C196
2.2U_0603_6.3V6K~D

C195

1U_0402_6.3V6K~D

C192
1U_0402_6.3V6K~D

C191
1U_0402_6.3V6K~D

C190
1U_0402_6.3V6K~D

C189
1U_0402_6.3V6K~D

C188
1U_0402_6.3V6K~D

C187
1U_0402_6.3V6K~D

C186
1U_0402_6.3V6K~D

C185

C184

10U_0603_6.3V6M~D

C182

DDR_A_BS1

8,18 DDR_A_BS1

C181

DDR_A_BS0

8,18 DDR_A_BS0

C180

C178

DDR_CKE0_DIMMA

8,18 DDR_CKE0_DIMMA

10U_0603_6.3V6M~D

M_CLK_DDR#0

8,18 M_CLK_DDR#0

10U_0603_6.3V6M~D

8,18 M_CLK_DDR0

10U_0603_6.3V6M~D

M_CLK_DDR0

330U_D2_2.5VY_R15M

8,18 M_ODT0

DDR_A_BS2

8,18 DDR_A_BS2

+1.5V

DDR_CS0_DIMMA#

8,18 DDR_CS0_DIMMA#

DDR_A_RAS#

8,18 DDR_A_RAS#

1U_0402_6.3V6K~D

C254
1U_0402_6.3V6K~D

C250
1U_0402_6.3V6K~D

C255
1U_0402_6.3V6K~D

C256
1U_0402_6.3V6K~D

C251
1U_0402_6.3V6K~D

C247

DDR_RST#

9,18,19 DDR_RST#

C599
1U_0402_6.3V6K~D

DDR_A_WE#

8,18 DDR_A_WE#

C253
1U_0402_6.3V6K~D

DDR_A_CAS#

8,18 DDR_A_CAS#

Place close to MEM

+1.5V

U11
8 DDR_A_DQS2
8 DDR_A_DQS#2
8 DDR_A_D[16..23]

G2
F8
G8
G10

8,18 DDR_A_MA[0..14]

Place the end of the DDR3

+0.75VS

2
1

1
C194

R176
30_0402_1%~D

Second
MAIN

0.1U_0402_10V7K~D

M_CLK_DDR#0

M_CLK_DDR0_TERM

3.3P_0402_50V8C~D

C193

1
C252

R175
30_0402_1%~D

0.1U_0402_10V7K~D

M_CLK_DDR0

Vendor

Package

Samsung

(9*11)

Samsung DDR3(1066): SA00002L60L (K4B1G0846D-HCF8 FBGA 82P)

Hynix

(8*11.5)

Hynix DDR3 (1066): SA00002PO0L (H5TQ1G83AFP-G7C FBGA 78P)

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

DDRIII-Memory Down (Top)

Size

Rev
1.0

LA-4631P
Date:

Document Number
Tuesday, February 24, 2009

Sheet
1

17

of

42

+1.5V

U14
8 DDR_A_DQS1
8 DDR_A_DQS#1
8 DDR_A_D[8..15]

DDR_A_D10
DDR_A_D13
DDR_A_D11
DDR_A_D8
DDR_A_D9
DDR_A_D14
DDR_A_D12
DDR_A_D15

C4
D4

DQS
DQS#

B4
C8
C3
C9
E4
E9
D3
E8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A8
B8
H9
2
240_0402_5%~D
E2
+V_DDR_MCH_REF
J9

8 DDR_A_DM1
1
R177

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4

J8
F10
H2
F2
H10
A1
N8
A11
A4
N1
N11

DDR_A_MA14

VDDQ
VDDQ
VDDQ
VDDQ

B10
C2
E3
E10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A3
A10
D8
G3
G9
K2
K10
M2
M10

NU/TDQS#
DM/TDQS
ZQ

ODT
CK
CK#
CKE

VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

+1.5V

U15
8 DDR_A_DQS3
8 DDR_A_DQS#3
8 DDR_A_D[24..31]

DDR_A_D27
DDR_A_D30
DDR_A_D26
DDR_A_D25
DDR_A_D31
DDR_A_D28
DDR_A_D24
DDR_A_D29

C4
D4

DQS
DQS#

B4
C8
C3
C9
E4
E9
D3
E8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A8
B8
8 DDR_A_DM3
H9
1
2
M_ODT0
R178
240_0402_5%~D
M_CLK_DDR0
E2
+V_DDR_MCH_REF
M_CLK_DDR#0
J9
DDR_CKE0_DIMMA
DDR_A_MA0
K4
DDR_A_BS0
DDR_A_MA1
J3
L8
DDR_A_BS1
DDR_A_MA2
K9
L4
DDR_A_BS2
DDR_A_MA3
J4
K3
DDR_A_MA4
L9
DDR_CS0_DIMMA#
DDR_A_MA5
H3
L3
DDR_A_RAS#
DDR_A_MA6
F4
M9
DDR_A_MA7
G4 DDR_A_CAS#
M3
DDR_A_WE#
DDR_A_MA8
H4
N9
DDR_RST#
DDR_A_MA9
N3
M4
DDR_A_MA10
H8
DDR_A_MA11
B3
M8
DDR_A_MA12
B9
K8
DDR_A_MA13
C10
N4
D2
D10
A2
A9
J8
B2
F10
F3
H2
F9
F2
D9
H10
J2
A1
DDR_A_MA14
J10
N8
L2
A11
L10
A4
N2
N1
N10
N11
G2
F8
G8
G10

H5TQ1G83AFP-G7C FBGA 78P

X76@

NU/TDQS#
DM/TDQS
ZQ

VDDQ
VDDQ
VDDQ
VDDQ

B10
C2
E3
E10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A3
A10
D8
G3
G9
K2
K10
M2
M10

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

C4
D4

DQS
DQS#

B4
C8
C3
C9
E4
E9
D3
E8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A8
B8
8 DDR_A_DM5
H9
1
2
M_ODT0
R179
240_0402_5%~D
M_CLK_DDR0
E2
+V_DDR_MCH_REF
M_CLK_DDR#0
J9
DDR_CKE0_DIMMA
DDR_A_MA0
K4
DDR_A_BS0
DDR_A_MA1
J3
L8
DDR_A_BS1
DDR_A_MA2
K9
L4
DDR_A_BS2
DDR_A_MA3
J4
K3
DDR_A_MA4
L9
DDR_CS0_DIMMA#
DDR_A_MA5
H3
L3
DDR_A_RAS#
DDR_A_MA6
F4
M9
DDR_A_MA7
G4 DDR_A_CAS#
M3
DDR_A_WE#
DDR_A_MA8
H4
N9
DDR_RST#
DDR_A_MA9
N3
M4
DDR_A_MA10
H8
DDR_A_MA11
B3
M8
DDR_A_MA12
B9
K8
DDR_A_MA13
C10
N4
D2
D10
A2
A9
J8
B2
F10
F3
H2
F9
F2
D9
H10
J2
A1
DDR_A_MA14
J10
N8
L2
A11
L10
A4
N2
N1
N10
N11

BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

DDR_A_D42
DDR_A_D41
DDR_A_D43
DDR_A_D47
DDR_A_D46
DDR_A_D40
DDR_A_D44
DDR_A_D45

G2
F8
G8
G10

ODT
CK
CK#
CKE

VREFDQ
VREFCA

+1.5V

U16
8 DDR_A_DQS5
8 DDR_A_DQS#5
8 DDR_A_D[40..47]

VDDQ
VDDQ
VDDQ
VDDQ

B10
C2
E3
E10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A3
A10
D8
G3
G9
K2
K10
M2
M10

ODT
CK
CK#
CKE

G2
F8
G8
G10

NU/TDQS#
DM/TDQS
ZQ
VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

BA0
BA1
BA2
CS#
RAS#
CAS#
WE#
RESET#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

+1.5V

U17
8 DDR_A_DQS7
8 DDR_A_DQS#7
8 DDR_A_D[56..63]

DDR_A_D58
DDR_A_D61
DDR_A_D59
DDR_A_D60
DDR_A_D63
DDR_A_D57
DDR_A_D62
DDR_A_D56

C4
D4

DQS
DQS#

B4
C8
C3
C9
E4
E9
D3
E8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A8
B8
8 DDR_A_DM7
H9
1
2
M_ODT0
R180
240_0402_5%~D
M_CLK_DDR0
E2
+V_DDR_MCH_REF
M_CLK_DDR#0
J9
DDR_CKE0_DIMMA
DDR_A_MA0
K4
DDR_A_BS0
DDR_A_MA1
J3
L8
DDR_A_BS1
DDR_A_MA2
K9
L4
DDR_A_BS2
DDR_A_MA3
J4
K3
DDR_A_MA4
L9
DDR_CS0_DIMMA#
DDR_A_MA5
H3
L3
DDR_A_RAS#
DDR_A_MA6
F4
M9
DDR_A_MA7
G4 DDR_A_CAS#
M3
DDR_A_WE#
DDR_A_MA8
H4
N9
DDR_RST#
DDR_A_MA9
N3
M4
DDR_A_MA10
H8
DDR_A_MA11
B3
M8
DDR_A_MA12
B9
K8
DDR_A_MA13
C10
N4
D2
D10
A2
A9
J8
B2
F10
F3
H2
F9
F2
D9
H10
J2
A1
DDR_A_MA14
J10
N8
L2
A11
L10
A4
N2
N1
N10
N11

VDDQ
VDDQ
VDDQ
VDDQ

B10
C2
E3
E10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A3
A10
D8
G3
G9
K2
K10
M2
M10

ODT
CK
CK#
CKE

G2
F8
G8
G10

M_ODT0
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

BA0
BA1
BA2

J3
K9
J4

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

CS#
RAS#
CAS#
WE#
RESET#

H3
F4
G4
H4
N3

DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_RST#

NU/TDQS#
DM/TDQS
ZQ
VREFDQ
VREFCA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

H5TQ1G83AFP-G7C FBGA 78P

H5TQ1G83AFP-G7C FBGA 78P

H5TQ1G83AFP-G7C FBGA 78P

X76@

X76@

X76@

B3
B9
C10
D2
D10
A2
A9
B2
F3
F9
D9
J2
J10
L2
L10
N2
N10

+V_DDR_MCH_REF

8,17 DDR_A_WE#
9,17,19 DDR_RST#

0.1U_0402_16V4Z~D

8,17 DDR_A_BS0
B

DDR_A_WE#

C214
0.1U_0402_16V4Z~D

DDR_A_BS0

DDR_A_CAS#

C213
0.1U_0402_16V4Z~D

8,17 DDR_A_CAS#

C212
0.1U_0402_16V4Z~D

8,17 DDR_A_RAS#

DDR_CKE0_DIMMA

DDR_A_RAS#

C211
0.1U_0402_16V4Z~D

8,17 M_CLK_DDR#0
8,17 DDR_CKE0_DIMMA

DDR_CS0_DIMMA#

C210
0.1U_0402_16V4Z~D

M_CLK_DDR#0

DDR_A_BS2
C205

8,17 DDR_CS0_DIMMA#

C209
0.1U_0402_16V4Z~D

8,17 DDR_A_BS2

M_CLK_DDR0

8,17 M_CLK_DDR0

C208
0.1U_0402_16V4Z~D

M_ODT0

8,17 M_ODT0

DDR_A_BS1
C207
2.2U_0603_6.3V6K~D

8,17 DDR_A_BS1

C206
2.2U_0603_6.3V6K~D

8,17 DDR_A_MA[0..14]

DDR3 Terminations
+0.75VS

DDR_RST#

RP5
DDR_A_CAS#
1
DDR_CKE0_DIMMA 2

4
3

36_0404_4P2R_5%~D
RP10
DDR_A_MA6
4
DDR_A_MA8
3

36_0404_4P2R_5%~D
RP11
DDR_A_MA10
1
4
DDR_A_BS2
2
3

36_0404_4P2R_5%~D
RP12
DDR_A_MA5
1
4
DDR_A_MA9
2
3

1
2

1
2

C215

0.1U_0402_16V4Z~D

C653
0.1U_0402_16V4Z~D

C652
0.1U_0402_16V4Z~D

C651
0.1U_0402_16V4Z~D

C608
0.1U_0402_16V4Z~D

C607
0.1U_0402_16V4Z~D

C606
0.1U_0402_16V4Z~D

MEM_SMBCLK 14,19
MEM_SMBDATA 14,19

AT24C02BN-SH-T_SO8~D

C605
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

MEM_SMBCLK
MEM_SMBDATA

C604
0.1U_0402_16V4Z~D

8
7
6
5

C603
0.1U 50V K X7R 0603

VCC
WP
SCL
SDA

C647

A0
A1
A2
GND

@ 1K_0402_5%~D

R182
@ 1K_0402_5%~D

R181

1
2
3
4

C648
0.1U 50V K X7R 0603

C221
1
2

@
U18

36_0404_4P2R_5%~D
RP13
1
4
2
3

+0.75VS

36_0404_4P2R_5%~D
RP14
DDR_A_MA11
4
DDR_A_MA14
3

DDR_A_BS0
DDR_A_MA0

1
2

36_0404_4P2R_5%~D
RP15
DDR_A_MA4
1
4
DDR_A_MA1
2
3

36_0404_4P2R_5%~D
RP16
DDR_A_MA7
1
4
DDR_A_MA13
2
3

36_0404_4P2R_5%~D

C220
1U_0402_6.3V6K~D

1
2

C219
1U_0402_6.3V6K~D

36_0404_4P2R_5%~D
RP9
1
4
2
3

C218
1U_0402_6.3V6K~D

DDR_A_MA12
DDR_A_BS1

C217
1U_0402_6.3V6K~D

36_0404_4P2R_5%~D
RP8
DDR_A_MA2
4
DDR_A_MA3
3

C216
1U_0402_6.3V6K~D

1
2

1U_0402_6.3V6K~D

4
3

36_0404_4P2R_5%~D
RP7

+0.75VS

DDR_A_RAS#
M_ODT0

1
2

DDR_CS0_DIMMA# 1
DDR_A_WE#
2

+3VS

RP6
4
3

36_0404_4P2R_5%~D
A

Place decaps close end termination resistors, one decap for 4 resistors

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

DDRIII-Memory Down (Bottom)

Size

Rev
1.0

LA-4631P
Date:

Document Number
Tuesday, February 24, 2009

Sheet
1

18

of

42

+1.5V

+1.5V

+V_DDR_MCH_REF

8 DDR_B_D[0..63]

+V_DDR_MCH_REF

+0.75VS

R185

DDR_B_D58
DDR_B_D59

10K_0402_5%~D

DDR_B_DM7

2.2U_0603_6.3V6K~D

C241

C242
0.1U_0402_16V4Z~D

2
1
2

M_CLK_DDR3 8
M_CLK_DDR#3 8

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 8
DDR_B_RAS# 8

DDR_CS2_DIMMB#
M_ODT2_DIMMB

DDR_CS2_DIMMB# 8
M_ODT2_DIMMB 8

M_ODT3_DIMMB

M_ODT3_DIMMB 8

+V_DDR_MCH_REF_R

R187
1
2
0_0402_5%~D

1
3

+0.75VS

+V_DDR_MCH_REF

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

+V_DDR_MCH_REF

DDR_B_DQS#5
DDR_B_DQS5
+1.5V

DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6

+3VALW
R27
1K_0402_1%

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
R169
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#_R
MEM_SMBDATA
MEM_SMBCLK

+V_DDR_MCH_REF

+V_DDR_MCH_REF

R183
0_0402_5%~D
1
2
MEM_SMBDATA 14,18
MEM_SMBCLK 14,18

R28
1K_0402_1%

PM_EXTTS#0_1 13

+0.75VS

DELL CONFIDENTIAL/PROPRIETARY

FOX_AS0A626-U4SN-7F~D

DDR3 SO-DIMM/Standard Type

Place close to JDIMM pin 203 and 204

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

DDRIII SO-DIMM SLOT

Size

Document Number

Rev
1.0

LA-4631P
Date:

206
208

M_CLK_DDR3
M_CLK_DDR#3

BOSS1
BOSS2

GND1
GND2

205
207

R184
2
1
10K_0402_5%~D

+3VS

DDR_B_D56
DDR_B_D57

+3VS

2.2U_0402_6.3VM

DDR_B_D50
DDR_B_D51

C230
2.2U_0402_6.3VM

DDR_B_DQS#6
DDR_B_DQS6

C229
1U_0402_6.3V6K~D

DDR_B_D48
DDR_B_D49

1U_0402_6.3V6K~D

DDR_B_D42
DDR_B_D43

0.1U_0402_16V4Z~D

DDR_B_DM5

C240
1U_0402_6.3V6K~D

DDR_B_D40
DDR_B_D41

DDR_B_MA2
DDR_B_MA0

2.2U_0603_6.3V6K~D

DDR_B_D34
DDR_B_D35

C235

DDR_B_DQS#4
DDR_B_DQS4
B

DDR_B_MA6
DDR_B_MA4

C236
0.1U_0402_16V4Z~D

DDR_B_D32
DDR_B_D33

DDR_B_MA11
DDR_B_MA7

C237

T18

DDR_CKE3_DIMMB 8

C239
1U_0402_6.3V6K~D

DDR_B_MA13
DDR_CS3_DIMMB#

8 DDR_CS3_DIMMB#

T17

DDR_B_MA14

C238
1U_0402_6.3V6K~D

8 DDR_B_WE#
8 DDR_B_CAS#

2
B

Q5
2N7002_SOT23

C228
1U_0402_6.3V6K~D

DDR_B_WE#
DDR_B_CAS#

DDR_CKE3_DIMMB

C234
0.1U_0402_16V4Z~D

8 DDR_B_BS0

DDR_B_D30
DDR_B_D31

Q38
MMBT3904_SOT23

C227
1U_0402_6.3V6K~D

DDR_B_MA10
DDR_B_BS0

DDR_B_DQS#3
DDR_B_DQS3

C233
0.1U_0402_16V4Z~D

M_CLK_DDR2
M_CLK_DDR#2

8 M_CLK_DDR2
8 M_CLK_DDR#2

DDR_B_D28
DDR_B_D29

2
G

C226
10U_0603_6.3V6M~D

DDR_B_MA3
DDR_B_MA1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D22
DDR_B_D23

+1.5V
R510
4.7K_0402_5%

C232
0.1U_0402_16V4Z~D

DDR_B_MA8
DDR_B_MA5

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

DDR_B_DM2

C225
330U_D2_2.5VY_R15M

DDR_B_MA12
DDR_B_MA9

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

Place close to SO-DIMM

+1.5V

DDR_B_D20
DDR_B_D21

C231

8 DDR_B_BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_RST# 9,17,18
+5VALW

@ C224

DDR_B_BS2

DDR_RST#
DDR_B_D14
DDR_B_D15

C347

DDR_CKE2_DIMMB

8 DDR_CKE2_DIMMB
C

DDR_B_DM1

R512

DDR_B_D26
DDR_B_D27

8 DDR_B_MA[0..14]
R509
1K_0402_5%

DDR_B_D12
DDR_B_D13

15.4K_0402_1%

DDR_B_DM3

8 DDR_B_DM[0..7]

0.1U_0402_16V4Z~D

DDR_B_D24
DDR_B_D25

8 DDR_B_DQS#[0..7]
+1.5V

R511

DDR_B_D18
DDR_B_D19

DDR_B_D6
DDR_B_D7

15.4K_0402_1%

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D16
DDR_B_D17

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D10
DDR_B_D11

DDR_B_D4
DDR_B_D5

DDR_B_DQS#1
DDR_B_DQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_B_D8
DDR_B_D9

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

2
1
2.7K_0402_5%

DDR_B_D2
DDR_B_D3

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

8 DDR_B_DQS[0..7]

2.2U_0603_6.3V6K~D

DDR_B_DM0
D

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C222

DDR_B_D0
DDR_B_D1

C223
0.1U_0402_16V4Z~D

JDIMM1

Tuesday, February 24, 2009

Sheet
1

19

of

42

LCD
JLVDS1

R556 1

+3VALW
+3VS
U21

W=60mils

C273
0.1U_0402_16V7K~N

+LCDVDD

1
3

EN

NC

GND

AOZ1320CI-04_SOT23-6
11,28 MCP79_ENVDD

LCD_VCC_TEST_EN 2 R211
1
0_0402_5%

R210
10K_0402_1%

C274

11 LCD_DDC_DATA

LCD_DET#
LCD_DDC_DATA

1 R289
2
0_0402_5%

LCD_TST
28

Change from 10K to 100k - 0102.

+LCDVDD

2 47K_0402_5%
LCD_DET#

C275

28 LCD_VCC_TEST_EN

@ D6
MCP79_ENVDD
2
CH751H-40PT_SOD323-2

28

W=60mils

0.1U_0402_16V7K~N

GND

OUT

4.7U_0805_6.3V6K~N

IN

50
48
46
44
42

28
11
11

LVDSA0+
LVDSA1-

11
11

LVDSA2+
LVDSAC-

11
11

LVDSB0+
LVDSB1-

11
11

LVDSB2+
LVDSBC-

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

LCD_TST
EDID_DATA_LCD
LVDSA0+
LVDSA1-

LCD_TST

LVDSA2+
LVDSACLVDSB0+
LVDSB1LVDSB2+
LVDSBC-

INVT_PWM

INVT_PWM

C600

G10
G8
G6
G4
G2

INVPW R_B+

G11
G9
G7
G5
G3
G1

51
49
47
45
43
41

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

+LCDVDD

+3VS

EDID_CLK_LCD
LVDSA0-

0_0402_5% 2
LVDSA0- 11

LVDSA1+
LVDSA2-

LCD_DDC_CLK

LCD_DDC_CLK 11

LVDSA1+ 11
LVDSA2- 11

LVDSAC+
LVDSB0-

LVDSAC+ 11
LVDSB0- 11

LVDSB1+
LVDSB2-

LVDSB1+ 11
LVDSB2- 11

LVDSBC+

LVDSBC+ 11

DISPOFF#
INVPW R_B+

1 R284

need swap DISPOFF# to pin 36 on Pannel side.

1
2
B+
L12
FBMA-L11-201209-121LMA50T

100P_0402_50V

W=60mils

I-PEX_20439-040E-02
D29

INVT_PWM

VN

CH1

VP

CH2

+3VALW

X01 change JLVDS connect signal (for layout)

DISPOFF#
+3VS

CM1213-02SR_SOT143-4

Place D29 close to JLVDS1

R212
4.7K_0402_5%

28

BKOFF#

BKOFF#

D7

DISPOFF#

SDMK0340L-7-F SOD-323
11 MCP79_LCD_PWM

MCP79_LCD_PWM

2 @ R215 1
10_0402_5%

INVT_PWM
1
C276
100P_0402_50V

SATA HDD

JSATA1
13 SATA_A0_TXP
13 SATA_A0_TXN
13 SATA_A0_RXN
13 SATA_A0_RXP

C569

C518

C568

C570

1 0.01U_0402_25V7K~N

1
2
3
4
5
6
7

SATA_A0_TXP_C
1 0.01U_0402_25V7K~N SATA_A0_TXN_C

1 0.01U_0402_25V7K~N SATA_A0_RXN_C
SATA_A0_RXP_C
1 0.01U_0402_25V7K~N

+3VS
3

+5VS

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

GND
A+
AGND
BB+
GND

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
GND
VCC12
GND

Close to JSATA1.
+5VS

23
24

SUYIN_127043FB022G345ZR_NR
CONN@

1
+ C394
150U_B2_6.3VM_R45M

C390
10U_0805_10V4Z~N

C392
0.1U_0402_16V7K~N

C391
0.1U_0402_16V7K~N

C393
1000P_0402_50V7K~N

Compal Secret Data

Security Classification
Issued Date

2009/02/19

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

LCD/SATA HDD

Size Document Number

Custom

R ev
1.0

LA-4631P

Date:

Tuesday, February 24, 2009

E

Sheet

20

of

42

HDMI Connector

+5VS_HDMI

2
D19

+5VS

@
2 R1282 1
0_0402_5%

1
2
BAT1000-7-F SOT23-3

F1
1A_6VDC_MINISMDC110

0.1U_0402_16V7K
C450

C449
0.1U_0402_16V7K

+5VS

1
100K_0402_5%
R396

JHDMI1

R399
2.2K_0402_5%

+5VS_HDMI

1
5
2

HDMI_HPD

HDMI_HPD

HDMI_DET_C

OE#
P

11

28

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMI_SDA
HDMI_SCL

HDMI_DET_C
+5VS_HDMI

DVI_TXC-

U36
SN74AHCT1G125GW_SOT353-5

DVI_TXC+
DVI_TXD0DVI_TXD0+
DVI_TXD1DVI_TXD1+
DVI_TXD2DVI_TXD2+
SCL_HDMI_MCP

11 SCL_HDMI_MCP

DVI_SCLK

1
2 R404
0_0402_5%
1
2 R405
0_0402_5%

SDA_HDMI_MCP

11 SDA_HDMI_MCP

C451
0.1U_0402_16V7K

+3VS

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND

20
21
22
23

FOX_QJ5119L-NVBT-7F
CONN@

DVI_SDATA

Close to JHDMI connector

+3VS
@ R406 1

2 0_0402_5%

@ R411 1

+3VS

+5VS_HDMI

2 0_0402_5%

DVI_TXD1-

VGA_DVI_TXC-

DVI_TXC-

DVI_TXD1+

VGA_DVI_TXC+

DVI_TXC+

R412

@ R416 1

2
0_0402_5%

R413

2 0_0402_5%

2
DVI_SCLK

4.7K_0402_5%

HDMI_SCL

1
D

2 0_0402_5%

@ R423 1

R415

4.7K_0402_5%
Q12

@ R417 1

R414

4.7K_0402_5%

4.7K_0402_5%

SUPERWORLD OCE2012120YZF

SUPERWORLD OCE2012120YZF

VGA_DVI_TXD1+

VGA_DVI_TXD1-

L24

L23

2N7002_SOT23

@ R418 1

2 0_0402_5%

L26
VGA_DVI_TXD0-

DVI_TXD0-

VGA_DVI_TXD0+

DVI_TXD0+

@ R426 1

DisplayPort Connector

+5VS +3VS

F3
MF-NSMF150-2 1.5A 6V
1
2
@F2
MF-NSMF150-2 1.5A 6V
1
2

U38

32

TMDS_HPD_SINK

40

DP_HPD_SINK

5
11
20
27
31
42
44
51
57

GND
GND
GND
GND
GND
GND
GND
GND

R120

DP_CBL_DET

HPD
DPVADJ
VSADJ

R435 1
2
@ 0_0402_5%

37

28

26
R440

R438

2
C479

10
8

NC
Line 4 GND
5

AZ1045-04QU_MSOP10

Line 3
4

6
NC

VDD
Line 1
3
1

10
8

AZ1045-04QU_MSOP10

NC
Line 4 GND
5

NC
Line 3

DP_TXD2+
DP_TXD2-

2
C481

DP_TXC+
DP_TXC-

2
C483
2 BLM18AG121SN1D_0603

DP_HPD

1 R437
2 1
1K_0402_5%

R441
@
100K_0402_5%

R121

1 C486
R443

2 BLM18AG121SN1D_0603
1

R444

C487
180P_0402_50V8J

21
22
23
24

LANE0_P
GND
LANE0_N
LANE1_P
GND
LANE1_N
LANE2_P
GND
LANE2_N
LANE3_P
GND
LANE3_N
CONFIG1

CONFIG2

A U X C H _P
GND
AUXCH_N
HPD
RETURN
DP_PWR

FOX_3V102P1-RB2BT-8F_20P

2 4.7K_0402_5%

+3VS

MCP_DP_CBL_DET 11

PIN 14
PULLED UP (26K)

INSIDE DONGLE

R454
2M_0402_5%

1
D

MCP79_AUX+

BSS138W-7-F_SOT323-3
MCP79_AUX3

Q16
2@ R477
1
0_0402_5%
1

11 MCP79_AUX-

BSS138W-7-F_SOT323-3
11 MCP79_AUX+

2 0_0402_5% DP_AUXP
2 0_0402_5% DP_AUXN

R458 1
R459 1

R460
100K_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

DP_TXD1+
DP_TXD1-

2
R457
100K_0402_5%

11 SCL_DP_MCP
11 SDA_DP_MCP

DP_TXD0+
DP_TXD0-

2
C477

R453
100K_0402_5%

U41

5
A

NC

P
1

R452
@
5.1M_0402_5%

R439 @

MCP_DP_CBL_DET
74LVC1G14GW_SOT353-5
CBL_DET 2 R449
1
Y 4
0_0402_5%

CBL_DET

DP_CBL_DET

@
R486
0_0402_5%

DP_HPD

100K_0402_5%

R447 1

Q45

JDP1

1
0.1U_0402_16V4Z

+3VS

AO3413_SOT23

1
0.1U_0402_16V7K

R434 1
2
1K_0402_5%

+3VS

2
C491

1
0.1U_0402_16V7K

DP_TX3+
DP_TX3-

2
C476
1
0.1U_0402_16V7K
2
C478
1
0.1U_0402_16V7K
2
C480
1
0.1U_0402_16V7K
2
C482
1
0.1U_0402_16V7K
1
L28

U40
@

+3VS_DP

L29

EXPOSED PAD
SN75DP122A_QFN56_8X8

DP_TX2+
DP_TX2-

28 DP_CBL_DET
MCP_DP_HPD 11
DP_AUXP
DP_AUXN

MCP_DP_HPD

R445

R433
@

100K_0402_5%

1
0.1U_0402_16V7K

DP_TX3+
DP_TX3-

1
0.1U_0402_16V7K

DP_TX1+
DP_TX1-

NC

NC

DP_TX2+
DP_TX2-

47
46

DP_TX0+
DP_TX0-

U39
@

Line 2

50
49

DP_SINK 3(P)
DP_SINK 3(N)

VDD
Line 1

DP_SINK 2(P)
DP_SINK 2(N)

+3VS

DP_TX1+
DP_TX1-

3
1

DP_TX0+
DP_TX0-

53
52

CAD

56
55

DP_SINK 1(P)
DP_SINK 1(N)

39

DP_SINK 0(P)
DP_SINK 0(N)

100K_0402_5%

CAD_SINK

PRIORITY

41

VGA_DVI_TXD2+
VGA_DVI_TXD2-

33

25
24

100K_0402_5%

1
0_0402_5%

LP

VGA_DVI_TXD1+
VGA_DVI_TXD1-

TMDS_SINK 2(P)
TMDS_SINK 2(N)

100P_0402_50V8J

MCP_DP_CBL_DET

2@ R456
1
0_0402_5%

DP_CBL_DET

MCP_DP_HPD

2 R451
1
0_0402_5%

1
4.7K_0402_5%

DP_HPD

30

VGA_DVI_TXD0+
VGA_DVI_TXD0-

22
21

100K_0402_5%
2
1

R436

I2C_SCL
I2C_SDA

19
18

TMDS_SINK 1(P)
TMDS_SINK 1(N)

2
1
100K_0402_5%

+3VS

29
28

TMDS_SINK 0(P)
TMDS_SINK 0(N)

MCK3225201YZF 1210
L27
1
2
2

1
2
R427 0_0402_5%
VGA_DVI_TXC+
16
VGA_DVI_TXC15

DP_HPD

AUX(P)_I2C(SCL)
AUX(N)_I2C(SDA)

HDMI_SDA
2N7002_SOT23

C468

11 MCP_DP_CBL_DET

36
35

VDD*1
TMDS_SINK_CLK(P)
TMDS_SINK_CLK(N)

+3V_DP

2100K_0402_5%

DP_CBL_DET
2
0_0402_5%
@
1
2MCP_DP_CBL_DET_TI
R475
0_0402_5%
HDMI_HPD

AUX_SINK (P)
AUX_SINK (N)

Close to JDP connector

R430 1

1
R431

11 TI_PRIORITY

2 0_0402_5%
2 0_0402_5%
2 4.7K_0402_5%
2 4.7K_0402_5%

ML_IN 3(P)
ML_IN 3(N)

45
43

38

@
@

ML_IN 2(P)
ML_IN 2(N)

12
13

2
8
34
48
54

1
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
0.1U_0402_16V4Z

+3VS

2 0_0402_5%
2 0_0402_5%

9
10

VDD
VDD
VDD
VDD
VDD

SCL_HDMI_MCP R407 1
SDA_HDMI_MCP R408 1
R428 1
R429 1

11 SCL_HDMI_MCP
11 SDA_HDMI_MCP

@
@

ML_IN 1(P)
ML_IN 1(N)

2
C459 2
C461 2
C463
2
C465 2
C467 2
C469 2
C471 2
C473

11 SCL_DP_MCP
11 SDA_DP_MCP

6
7

14
17
23

6.49K_0402_1%

11 MCP79_AUX+
11 MCP79_AUX-

ML_IN 0(P)
ML_IN 0(N)

VCC
VCC
VCC

R490 1
R489 1

MCP79_DP3+
MCP79_DP3-

11 MCP79_DP3+
11 MCP79_DP3-

3
4

SCL_DP_MCP
SDA_DP_MCP

MCP79_DP2+
MCP79_DP2-

11 MCP79_DP2+
11 MCP79_DP2-

MCP79_AUX+
MCP79_AUX-

MCP79_DP1+
MCP79_DP1-

11 MCP79_DP1+
11 MCP79_DP1-

SW_DP0+
1
SW_DP00.1U_0402_16V7K
1
0.1U_0402_16V7K
SW_DP1+
1
SW_DP10.1U_0402_16V7K
1
0.1U_0402_16V7K
SW_DP2+
1
SW_DP20.1U_0402_16V7K
1
0.1U_0402_16V7K
SW_DP3+
1
SW_DP30.1U_0402_16V7K
1
0.1U_0402_16V7K
2 0_0402_5% DP+
DP0_0402_5%
2

4.7K_0402_1%

11 MCP79_DP0+
11 MCP79_DP0-

2
C460 2
C462
2
C464 2
C466
2
C470 2
C472
2
C474 2
C475
R488 1
@
R487 1
@

Q13

2 0_0402_5%

NC

DisplayPort/TMDS 1:2 Switch/Translator

MCP79_DP0+
MCP79_DP0-

GR OUND

2 0_0402_5%

NC

@ R425 1

DVI_SDATA

SUPERWORLD OCE2012120YZF

0.1U_0402_16V7K

SUPERWORLD OCE2012120YZF

DVI_TXD2DVI_TXD2+

Line 2

VGA_DVI_TXD2+

L25
VGA_DVI_TXD2-

SCL_DP
1
0.1U_0402_16V4Z

2
C495

DP_AUXP

SDA_DP
1
0.1U_0402_16V4Z

2
C496

DP_AUXN

Issued Date

2009/02/19

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Q17
2@ R479
1
0_0402_5%
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

HDMI/Display Port Conn.

Size Document Number
Custom

R ev
1.0

LA-4631P

Date:

Tuesday, February 24, 2009

1

Sheet

21

of

42

CM1293A-04SO SOT23-6

W=60mils

LAN_MIDI0-

+3V_LAN

These caps close to U64: Pin 44, 45

C624

CH1

Vn

CH2

These caps close to U64: Pin 4

C625

+LAN_VDD

These caps close to U64: Pin 44,45

These caps close to U64: Pin 4,10,13, 30, 36,39

LAN_MIDI0+

0.01U_0402_16V7K
C630

0.1U_0402_10V7K
C629

0.1U_0402_10V7K~N

22U_1206_6.3V6M

0.1U_0402_10V7K~N C623

0.1U_0402_10V7K~N C622

0.1U_0402_10V7K~N

+3V_LAN_R

+LAN_VDD12

2
R1238
0_0603_5%

0.1U_0402_10V7K~N C621

C617

0.1U_0402_10V7K~N C620

C616
0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

1
1

0.1U_0402_10V7K~N C619

+3V_LAN
C615

0.1U_0402_10V7K~N C618

1.5A
1

CH4

Vp

CH3

+LAN_VDD
+3VALW

@ D25
CM1293A-04SO SOT23-6
D

LAN_MIDI1-

CH1

Vn

CH2

CH4

Vp

CH3

LAN_MIDI1+

( Should be place within 200 mils )

+3VALW

@ D26

CM1293A-04SO SOT23-6
LAN_MIDI3-

CM1293A-04SO SOT23-6
LAN_MIDI2-

U22

1
R1255

R1256
+3VS

10,23,24,28 PCIE_WAKE#
2

LAN_XTAL1
LAN_XTAL2_R

1K_0402_5%

2
2.49K_0402_1%
PCIE_WAKE#
ISOLATEB

REFCLK_P
REFCLK_M

25

CLKREQB

27

PERSTB

46

RSET

26
28

LANWAKEB
ISOLATEB

41
42

LAN_CABDT

28 LAN_CABDT

CKTAL1
CKTAL2

28 LAN_LOPWEN

0_0402_5%
ISOLATEB
2

LAN_LOPWEN 1
@ R1250

23
24

NC
NC

7
14
31
47

GND
GND
GND
GND

22

LED0

38

LAN_LED0

MDIP0
MDIN0
MDIP1
MDIN1
MDI P2
MDI N2
MDI P3
MDI N3

2
3
5
6
8
9
11
12

LAN_MIDI0+
LAN_MIDI0LAN_MIDI1+
LAN_MIDI1LAN_MIDI2+
LAN_MIDI2LAN_MIDI3+
LAN_MIDI3-

FB12

R1257
15K_0402_5%

RTL8111DL

17
18

EGND

1
2
4.7UH_1098AS-4R7M_1.3A
1
C632

+LAN_VDD12

SROUT12

48

+LAN_SROUT12

EVDD12
DVDD12
DVDD12
DVDD12
AVDD12

19
30
36
13
10

+LAN_EVDD12

W=60mils
+LAN_VDD12

+3V_LAN_R
1

39

VDDSR
VDDSR

44
45

VDD33
VDD33

29
37

AVDD33
AVDD33
ENSR

1
40
43

2 0_0402_5%

LAN_XTAL2 1
0_0402_5%~D

2
R550

1
C636
1
C637
1
C638
1
C639

+3V_LAN_R

LAN_XTAL2_R

These components close to U64: Pin 48

( Should be place within 200 mils )
R1259
0_0603_5%
2

W=30mils
1
C634
1
C635

+3V_LAN

W=30mils
1

+LAN_VDD

2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
LED1_LED3
LED2_LED3

These caps close to U64: Pin 19

LAN_LED0
R1258
1
2
0_0603_5%
2
0.1U_0402_16V7K~N
2
0.1U_0402_16V7K~N
2
0.1U_0402_16V7K~N
2
0.1U_0402_16V7K~N

+3V_LAN

+3V_LAN

D21
LAN_LED21

LAN_LED31

T19

C305

C306

C307

0.01U_0402_16V7K
LAN_MIDI3LAN_MIDI3+

C310

1
2
3

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

24
23
22

RJ45_MDI3RJ45_MDI3+

0.01U_0402_16V7K
LAN_MIDI2LAN_MIDI2+

4
5
6

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MDI2RJ45_MDI2+

0.01U_0402_16V7K
LAN_MIDI1LAN_MIDI1+

7
8
9

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_MDI1RJ45_MDI1+

0.01U_0402_16V7K
LAN_MIDI0LAN_MIDI0+

10
11
12

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

RJ45_MDI0RJ45_MDI0+

1 R236
2
75_0402_1%

CT

D23

LAN_LED11

1000P_1206_2KV7K
1 R239
2
75_0402_1%

TX3+

RJ45_MDI1-

TX1-

RJ45_MDI2-

TX2-

RJ45_MDI2+

TX2+

RJ45_MDI1+

TX1+

RJ45_MDI0-

TX0-

TX0+

LAN_LED31

+3V_LAN

LED2_LED3 1 R22
LED2_RXDLY_R
2
220_0402_5%
LED1_LED3 1 R12
LED1_AD1_R
2
220_0402_5%
1
2
R1274 0_0402_5%

Orange LED-

Green LED-

10

14
15
16
17
18
19

Green-Orange LED+
A

TYCO_2041633-1

1 R256
2
75_0402_1%

Issued Date

11

GND
GND
GND
GND
GND
GND

SDMK0340L-7-F

1 R254
2
75_0402_1%

Compal Secret Data

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

TX3-

LED1_LED3

D24

Security Classification
LFE9249-R LAN

Yellow LED+

RJ45_MDI0+

SDMK0340L-7-F

Yellow LED-

12

RJ45_MDI3+
LED2_LED3

D22

13

SDMK0340L-7-F

C299
27P_0402_50V8J

JLAN1
LED0_AD0_R
1 R5
2
220_0402_5%
1
2
R1272 0_0402_5%
RJ45_MDI3-

SDMK0340L-7-F

C304

C633

These caps close to U64: Pin 1, 29,37,40

1
1

CH3

+LAN_VDD

X5
25MHZ_20P

CH2

+3VALW

@ D28

LAN_LED0

2
1

+LAN_AVDD33

LAN_XTAL1

R234
0_0402_5%

C298
27P_0402_50V8J

1 R1276 2
0_0603_5%

@ D27

W=60mils

RTL8111DL-GR_LQFP48
R230 1

Vp

+3VALW

L111

11 PHY_25MHZ

CH3

Vn

AVDD12

LAN_MIDI2+

CH4

100P_0402_25V8K

PCIE_RST#

HSIN

CH2

CH1

100P_0402_25V8K
C642

10 LAN_CLKREQ#
10,23,24,26 PCIE_RST#

16

Vp

C640

10 CLK_PCIE_LAN
10 CLK_PCIE_LAN#

HSIP

Vn

100P_0402_25V8K
C641

C631 2

HSON

15

CH4

LAN_MIDI3+

3.6K_0402_5%
2

22U_1206_6.3V6M

PCIE_TX1_N

21

R1254
1

33
34
35
32

0.1U_0402_10V7K~N

C628 2

CH1

+3V_LAN
LAN_LED3
LAN_LED2
LAN_LED1

LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS

10U_0603_6.3V

10 PCIE_TX1_N

PCIE_TX1_P

HSOP

C644

10 PCIE_TX1_P

20

C643

C627 2

10 PCIE_RX1_N

PCIE_RX1_C_P
0.1U_0402_16V7K
PCIE_RX1_C_N
1
0.1U_0402_16V7K
PCIE_TX1_C_P
1
0.1U_0402_16V7K
PCIE_TX1_C_N
1
0.1U_0402_16V7K
1

0.1U_0402_10V7K

C626 2

10 PCIE_RX1_P

Title

Compal Electronics, Inc.

Gigabit LAN_RTL8111DL

Size Document Number

Custom

Rev
1.0

LA-4631P

Date:

Sheet

Tuesday, February 24, 2009

1

22

of

42

Express Card Power Switch

Express Card
JEXP1

+1.5VS_CARD

(1A)

3.3Vout
3.3Vout

3
5

17
6

AUX_IN
SYSRST#

AUX_OUT
OC#

19

20

SHDN#

PERST#

STBY#

NC

@ R498 1

2 100K_0402_5% PEB_PRSNT#

@ R499 1

2 100K_0402_5% CPUSB#

10

CPPE#

CPUSB#

18

RCLKEN

GND

PERST#

8
16

C533

28,30,35 SYSON
28,30,36,37 SUSP#

C532

+3VALW

PCIE_RST#

+3VS_CARD_AUX

0.1U_0402_16V7K~N

10,22,24,26 PCIE_RST#

15

C528

3.3Vin
3.3Vin

0.1U_0402_16V7K~N

2
4

0.1U_0402_16V7K~N

11
13

13
13

USB20_N3
USB20_P3

USB20_N3
USB20_P3

24
24

SMB_CLK
SMB_DATA

SMB_CLK
SMB_DATA

10,22,24,28 PCIE_WAKE#

R347 2
R348 2

1 0_0402_5%
1 0_0402_5%

R493 2
R494 2

1 0_0402_5%
1 0_0402_5%
+1.5VS_CARD

R495 1

2 0_0402_5%
+3VS_CARD_AUX

USB20_N3_R
USB20_P3_R
CPUSB#
SMB_CLK_R
SMB_DATA_R

PERST#

+3VS_CARD
10 EXP_CLKREQ#
10 PEB_PRSNT#
10 CLK_PCIE_EXPR#
10 CLK_PCIE_EXPR

EXP_CLKREQ# R496 1
PEB_PRSNT#
R497 1
CLK_PCIE_EXPR#
CLK_PCIE_EXPR

2 0_0402_5%
2 0_0402_5%

R501 1
R505 1

2 0_0402_5%
2 0_0402_5%

(0.5A)

10 PCIE_RX0_N
10 PCIE_RX0_P
10 PCIE_TX0_N

PCIE_TX0_N

C47

0.1U_0402_16V7K~N

1.5Vout
1.5Vout

C527

1.5Vin
1.5Vin

10U_0805_4VAM~D

12
14

C526

U28

C525

C524

C523

0.1U_0402_16V7K~N

C531

C530

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

C529

10U_0805_4VAM~D

+1.5VS

(1.5A)
0.1U_0402_16V7K~N

+3VS

0.1U_0402_16V7K~N

+3VALW

+3VS_CARD

10 PCIE_TX0_P

PCIE_TX0_P

C46

EXP_CLKREQ#_R
CPPE#

PCIE_RX0_C_N
PCIE_RX0_C_P

1 0.1U_0402_16V7K PCIE_TX0_C_N
PCIE_TX0_C_P
1 0.1U_0402_16V7K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

27
28
29
30

GND
GND
GND
GND

GND
GND

31
32
B

FOX_1CX422AU1-BT_26P_RT-T
CONN@

TPS2231MRGPR-1 QFN 20P

Compal Secret Data

Security Classification
2009/02/19

Issued Date

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Express Card

Size Document Number

Custom

Rev
1.0

LA-4631P

Date:

Tuesday, February 24, 2009

Sheet
1

23

of

42

W=60mils

WLAN

+3VS

+3VALW

+3V_WLAN

Q43
D

1 R308
2
0_0805_5%

S
4

C322

@
2

JMINI1

10 PCIE_TX2_N
10 PCIE_TX2_P

2 0_0402_5%
2 0_0402_5%

PCIE_RX2_C_N
PCIE_RX2_C_P
PCIE_TX2_C_N
PCIE_TX2_C_P

PCIE_TX2_N

C51

1 0.1U_0402_16V7K

PCIE_TX2_P

C50

1 0.1U_0402_16V7K
+3V_WLAN

GND2

2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

USB20_N7_R
USB20_P7_R

@
@

R273 1
R278 1

2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

C321
0.01U 16V K X7R 0402

LPC_FRAME# 12,28

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

+3VS
LPC_AD[0..3] 12,28
WL_RADIO_OFF# 28
PCIE_RST# 10,22,23,26
+3VALW

WL_RADIO_OFF#
R37 1
R270 1
SMB_CLK_WLAN R299 1
SMB_DATA_WLANR281 1
R1288 1
R1289 1

SMB_CLK
SMB_DATA
MCP_SMB_CLK
MCP_SMB_DATA

R1294
2.2K_0402_5%
Q56
SSM3K7002FU_SC70-3

2 0_0402_5% USB20_N7
2 0_0402_5% USB20_P7

USB20_N7 13
USB20_P7 13

MCP_SMB_CLK 1

14 MCP_SMB_CLK

R1295
2.2K_0402_5%

SMB_CLK

SMB_CLK 23
2

PCIE_RST_R#

TYCO_1775861-1~D
CONN@

@
C336 47P 50V J NPO 0402

GND1

54

1
1
1
1
1

PCIE_RST_R#

C337 47P 50V J NPO 0402

53

LPC_FRAME#_RR263
LPC_AD3_R
R264
LPC_AD2_R
R265
LPC_AD1_R
R266
LPC_AD0_R
R267

C320
0.01U 16V K X7R 0402

R102 1
R112 1

10 PCIE_RX2_N
10 PCIE_RX2_P

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

PLT_RST#_R
LPC_CLK0_R

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2 0_0402_5%
2 0_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

R268 1
R282 1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
G

PLT_RST#
LPC_CLK0

12,28 PLT_RST#
12,28 LPC_CLK0

WLAN_ACT_R
BT_PRI_R
WLAN_CLKREQ#_R

Q57
SSM3K7002FU_SC70-3

C45
0.1U_0402_16V7K
@
14 MCP_SMB_DATA

MCP_SMB_DATA

SMB_DATA

CLK_PCIE_WLAN#
CLK_PCIE_WLAN

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

+1.5VS

10 CLK_PCIE_WLAN#
10 CLK_PCIE_WLAN

R260 1
R261 1
R262 1

1
C535 +

SMB_DATA 23

2
G

10,22,23,28 PCIE_WAKE#
27
WLAN_ACT
27
BT_PRI
10 WLAN_CLKREQ#

PCIE_WAKE#
WLAN_ACT
BT_PRI
W LAN_CLKREQ#

1
C324

R368
1.5M_0402_5%
@
1

Q44
SSM3K7002FU_SC70-3
@

+3V_WLAN

2
G
3

+1.5VS

EN_WLAN#

28

EN_WLAN
2

R374
470K_0402_5%
@

C323

4.7U 10V Z Y5V 0805

2
B+_BIAS

0.1U 16V K X7R 0402

@
SI3456BDV-T1-E3 1N TSOP6

@ 330U_D2E_6.3VM_R25~D

6
5
2
1

0.01U 16V K X7R 0402

C521
1U_0603_10V6K

+5VS

R1296
2

2.2K_0402_5%

WWAN
+1.5VS

+3VS

JMINI2
3

+
2

1
C574 +
2

54

TYCO_1775861-1~D
CONN@

UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

+UIM_PWR

Vn

Vp

CH2 CH3

+UIM_PWR

+3VS

S DIO(BR) NUP4301MR6T1 TSOP-6

D9 @
WAN_RADIO_OFF#
PCIE_RST#
2 0_0402_5% +3VALW

R275 1
SMB_CLK_WWAN R276 1
SMB_DATA_WWAN R277 1
USB20_N6_R
USB20_P6_R

2 0_0402_5% SMB_CLK
2 0_0402_5% SMB_DATA

R279 1
R280 1

2 0_0402_5% USB20_N6
2 0_0402_5% USB20_P6

WAN_RADIO_OFF# 28
PCIE_RST# 10,22,23,26
28

UIM_DET

USB20_N6 13
USB20_P6 13

JSIM1
2
4
6
7
8

UIM_VPP
UIM_DATA
UIM_DET

C571
100P_0402_25V8K

GND
VPP
I/O
DET
DET

3
VCC
RST
CLK

1
3
5

GND
GND

9
10

2
DAN217_SC59-3

C573 C329

SUYIN_254070FB008H505ZL

@
1

UIM_RST
UIM_CLK

C571 & C573 as close as JSIM1

C330

+1.5VS

C334
0.01U 16V K X7R 0402

C335
0.01U 16V K X7R 0402

Compal Secret Data

Security Classification
2009/02/19

Issued Date

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

CH1 CH4

0.1U 16V K X7R 0402

GND2

U23
1

4.7U 6.3V K X5R 0805

C575

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

C351 47P 50V J NPO 0402

@ 330U_D2E_6.3VM_R25~D

C333

@ 330U_D2E_6.3VM_R25~D

4.7U 10V Z Y5V 0805

C332

0.1U 16V K X7R 0402

0.01U 16V K X7R 0402

C331
4

53

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

C350 47P 50V J NPO 0402

+3VS

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

100P_0402_25V8K

+3VS

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

Title

Compal Electronics, Inc.

Mini Card_WLAN/WWAN

Size Document Number

Custom

Rev
1.0

LA-4631P

Date:

Sheet

Tuesday, February 24, 2009

E

24

of

42

HP2_JD

29 HP2_JD

MIC_JD

29 MIC_JD

2
20K_0402_1%

SENSE B

14

2
R300
1
R301
1
R303

1
39.2K _0402_1%
2
20K_0402_1%
2
10K_0402_1%

SENSE A

13

SENSE_A

49
7
42
26
30
33

GPAD
DVSS
PVSS
AVSS
AVSS
AVSS

12
25

CAP2

22

VREFFILT

21

V-

34

VREG

37

14

1
R310

MCP_SPKR

C358
1U_0603_10V6K
2
1

2
20K_0402_1%
2
20K_0402_1%

1
3
3

1
3

3
3

1
3

S
D

@
Q62
2N7002_SOT23

2
G

@
Q65
2N7002_SOT23

2
G

@
Q66
2N7002_SOT23

HP_MUTE

Co-lay schematic
1

R393 1 0_0402_5%

PC_BEEP

R394 1 0_0402_5%

MONO_IN

+AVDD_AUDIO

+AVDD_AUDIO

R272
2.49K_0402_1%

+DVDD_AUDIO

R389
2.49K_0402_1%

R304
10K_0402_5%

R315
2.2K_0402_5%

SENSE A

SENSE B

EAPD
C313

C314
1000P_0402_50V7K~D

1000P_0402_50V7K~D

+5VALW

@
Q64
2N7002_SOT23

S
B

MCP Beep

1
R307

@ D
Q61
2N7002_SOT23
S

HP_MUTE

92HD83C1X5NLGXYBX8 QFN 48P CODEC C353

BEEP#

3
3

MONO_IN

PC_BEEP
MONO_OUT

4.7U_0603_6.3V

28

0.1U_0402_10V6K

PC_BEEP

EAPD shut down Extenal and Intenal AMP

EC Beep

1U_0603_10V6K
C346

10U_0603_6.3V
C345

0.1U_0402_10V6K
C344

39
45
PVDD
PVDD

27
38
AVDD
AVDD

17
18

@
Q60
2N7002_SOT23

SENSE_B

1
R298

PORT_F_L
PORT_F_R

CAP+

PORT_E_L
PORT_E_R

@
Q63
2N7002_SOT23

36

43
44
15
16

CAP-

1U_0603_10V6K
C343

C342

10U_0603_6.3V

C341
9

35

EC_MUTE#

EC_MUTE#

2
2.2U_0603_6.3V4Z

SPKER_R1
SPKER_R2

SPKR_PORT_D_RSPKR_PORT_D_R+

2
G

29 HP1_JD

EAPD

2
G

HP1_JD

SPDIF_OUT_0

47

@ D
Q59
2N7002_SOT23
S

1
C352

48
1 EAPD
0_0402_5%

100P_0402_50V
EC_MUTE# 2 R297

SPKR_PORT_D_L+
SPKR_PORT_D_L-

DMIC1/GPIO0/SPDIF_OUT_1

HP2_LEFT
HP2_RIGHT

DMIC0/GPIO2

HP1_LEFT
HP1_RIGHT

SPKER_L1
SPKER_L2

4
46

HP2_LEFT 29
HP2_RIGHT 29

100P_0402_50V

2 0_0402_5%

1
@ C594

DMIC_CLK/GPIO1

HP_MUTE

1 R295
1
@ C593

40
41

HDA_RST#

SSM3K131TU_SOT323-3

1U_0603_10V6K

C356

11

2 33_0402_5%

Q50

HP_MUTE

HP1_LEFT 29
HP1_RIGHT 29

MIC_LEFT 29
MIC_RIGHT 29
+MIC1_VREFO

10U_0603_6.3V

2 0_0402_5%

1 R294

19
20
24

C355

DMIC_DATA

1 R293

PORT_C_L
PORT_C_R
VREFOUT_C

2.2U_0603_6.3V4Z

27

ACZ_RST#

31
32

C354

DMIC_CLK

DVDD_CORE

3
DVDD_IO

DVDD

C340

0.1U_0402_10V6K

C339

1
10P_0402_50V8J

C602

1U_0603_10V6K

0.1U_0402_10V6K

C338

2
1
C572

10P_0402_50V8J

14
27

HP1_PORT_B_L
HP1_PORT_B_R

HDA_SYNC

56_0402_5%
HP1_LEFT
2
HP1_RIGHT
2
56_0402_5%
56_0402_5%
HP2_LEFT
2
HP2_RIGHT
2
56_0402_5%

10

R1290
1
1
R1291
R1292
HP2_LEFT_R
1
HP2_RIGHT_R 1
R1293
MIC_LEFT
MIC_RIGHT
HP1_LEFT_R
HP1_RIGHT_R

2 0_0402_5%

28
29
23

SSM3K131TU_SOT323-3

S
D

Q48
SSM3K131TU_SOT323-3

Q49
SSM3K131TU_SOT323-3

Q54

2
G

1 R291

ACZ_SYNC

2
G

HDA_SDO

14

HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_or_F

S
B

HDA_SDI

Q53
SSM3K131TU_SOT323-3

Q47
Q52
SSM3K131TU_SOT323-3
SSM3K131TU_SOT323-3

2 0_0402_5%

SSM3K131TU_SOT323-3

2
G

2 33_0402_5%

1 R290

2
G

1 R288

D
D
Q51

ACZ_SDIN0

HDA_BITCLK

2 0_0402_5%

1 R286

14 ACZ_SDOUT

14

R287 & C572 Close U25 pin6

14 ACZ_BITCLK

28

U25

HP2_LEFT
HP2_RIGHT

HP1_LEFT
HP1_RIGHT

+5VS

R229
1
2
0_0805_5%

+AVDD_AUDIO

R306
0_0402_5%

1 R271
2
0_0603_5%

R287
0_0402_5%

ACZ_SDOUT

+AVDD_AUDIO
ACZ_BITCLK

+3VS

+DVDD_AUDIO

R1287
10K_0402_1%

C243
TWSPK_L1
1

10U_0603_6.3V6M~D

HP_MUTE
TWSPK_L2
EC_MUTE#

10U_0603_6.3V6M~D
TWSPK_R1

PLACE CLOSE TO CODEC PIN 13

PLACE CLOSE TO CODEC PIN 13

If SENSE_A total length is greater

than 6 inches, change C313 to 0.1uF.

If SENSE_B total length is greater

than 6 inches, change C314 to 0.1uF.

Q55
SSM3K7002FU_SC70-3

2
G

C245

If ports E and F are unused,

simply pull-up SENSE_B to
AVDD with a 100K-ohm resistor.

TWSPK_R1 29
JSPK1

10U_0603_6.3V6M~D

TWSPK_R2 29

C595

PACDN042_SOT23-3~D
3
1
2

JTWL2

1
2
3
4
GND
GND

TWSPK_L1
TWSPK_L2

MOLEX_53780-0470
CONN@

D11

1
2

1
2

3
4

GND
GND

MOLEX_53780-0270~D
CONN@
4

ROW PESD5V0U2BT 3P C/C SOT23 ESD

1

PACDN042_SOT23-3~D
3
1
2

Issued Date

1
2
3
4
5
6

2 0_0805_5%

AGND

2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D

Compal Electronics, Inc.

Compal Secret Data

Security Classification

GND

100P_0402_50V

R320 1

100P_0402_50V

D10

100P_0402_50V

D5

Reserved for TEST

100P_0402_50V

10U_0603_6.3V6M~D

C598

TWSPK_R2

C597

SPKER_R2

C596

SPKER_L1
SPKER_L2
SPKER_R1
SPKER_R2

C246

SPKER_R1

SPKER_L2

C244

SPKER_L1

Title

Codec IDT 92HD83

Size Document Number
Custom

Rev
1.0

LA-4631P

Date:

Tuesday, February 24, 2009

G

Sheet

25
H

of

42

+1.8VS_CR

W=30 mil

These caps close to U26 pin5.

1

1
C368

C367

2
1000P_0402_50V7K

3
4

APCLKN
APCLKP

C375 1

2 0.1U_0402_16V7K

10 PCIE_TX3_P

C376 1

2 0.1U_0402_16V7K

PCIE_TX3_C_N
PCIE_TX3_C_P

9
8

APRXN
APRXP

10 PCIE_RX3_N

C395 1

2 0.1U_0402_16V7K

PCIE_RX3_C_N
PCIE_RX3_C_P

2 0.1U_0402_16V7K
2 8.2K_0402_5%

APTXN
APTXP

10 PCIE_RX3_P

C396 1
R337 1

11
12

APREXT

+3VS

W=12 mil

JMB_XIN
JMB_XOUT

1
2
C387 10U_0805_10V4Z
1
2
C379 0.1U_0402_16V4Z
10,22,23,24 PCIE_RST#

PCIE_RST#

R338 1

2 0_0402_5%

XRSTN

T22
T23

+3VS

R342 1
R343 1

2 4.7K_0402_5%
2 4.7K_0402_5%

TXIN
TXOUT

30

TAV33

1
2

XRSTN
XTEST

15
16
17

2
10U_0805_10V4Z

CR1_CD1N
CR1_CD0N

DV33
DV33
DV33
DV18
DV18

19
20
44
18
37

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

MDIO7

R325 1

2 10K_0402_5%

MDIO12

R329 1

2 200K_0402_5%

MDIO14

R327 1

2 200K_0402_5%

TPA1P
TPBIAS_1
TREXT

34
35
36

IEEE_TPA1P
TPBIAS
TREXT

R340 1

2 12K_0402_1%

R341 1

2 10K_0402_5%

APGND

TCPS
TPB1N
TPB1P
TPA1N

24
31
32
33

CR1_PCTLN

2
0.1U_0402_16V4Z

C386
10U_0805_10V4Z
@

CR1_LEDN

49

GPAD

2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

W>40 mil

C388
10U_0805_10V4Z
@

+1.8VS_CR

1
C377

1
C378

2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

C389
10U_0805_10V4Z
@

+3VS

Close to U26.
TCPS
IEEE_TPB1N
IEEE_TPB1P
IEEE_TPA1N

W=10 mil
IEEETP

21

C374

APVDD
APV18

JMB380

SEEDAT
SEECLK

1
C373

5
10

APREXT

38
39

13
14

1
C369

IEEE_TPB1N
IEEE_TPB1P
IEEE_TPA1N
IEEE_TPA1P

1
C383
0.33U_0603_10V7K

C372

22P_0402_50V8J

R539
56_0402_5%

2
2

R336
1M_0402_5%

X4
24.576MHz_16P_3XG-24576-43E1

29
29
29
29

R540
56_0402_5%

JMB_XIN

22P_0402_50V8J

IEEE_TPB1N
IEEE_TPB1P
IEEE_TPA1N
IEEE_TPA1P

W=7 mil

C370

R538
56_0402_5%

R344
4.99K_0402_1%

Close to U26 pin38, pin39. (L<500mil).

C382
220P_0402_50V7K

R345
56_0402_5%

JMB380-QGAZ0B_QFN48_7X7

10 CLK_PCIE_1394#
10 CLK_PCIE_1394
10 PCIE_TX3_N

2
0.1U_0402_16V4Z

1
C366

+3VS

U26
CLK_PCIE_1394#
CLK_PCIE_1394

These caps close to U26 pin10.

TPBIAS
R551
1
2
0_0402_5%~D

JMB_XOUT

W=10 mil

W=7 mil

Compal Secret Data

Security Classification
Issued Date

2009/02/19

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

IEEE1394_JMB380

Size Document Number

Custom

R ev
1.0

LA-4631P

Date:

Tuesday, February 24, 2009

1

Sheet

26

of

42

+5VALW

USB_EN#

USB_EN#

OC1#
OUT1
OUT2
OC2#

8
7
6
5

1
+ C443
1

TPS2062ADR_SO8~D
2
USB_OC#0

R385

1
1

USB_EN#

13

Q8

2
G

13

USB20_N0

13

USB20_P0

L19 WCM2012F2S-900T04_0805
1 1
2 2

USB20_N0
USB20_P0

JUSBP1
+USB_AS

USB_N0
USB_P0

C444
0.1U_0402_16V4Z

28,29

GND
IN
EN1#
EN2#

150U_B2_6.3VM_R45M

1
2
3
4

W=80mils Close to USB Connector.

30K_0402_5%

C445
0.1U_0402_16V4Z

W=80mils

+USB_AS
U32

W=80mils

1
2
3
4

VBUS
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4
SUYIN_020173MR004S52GZL

SSM3K7002FU_SC70-3

change JUSBP1 connect signal (for layout)

Bluetooth

R388
100K_0402_5%
@

+3VS

15

JCA1

DMIC_CLK

DMIC_CLK

USB_P4
USB_N4
1 MBK1608221YZF 0603
2 0_0603_1%

L21 2
R74 1

DMIC_DATA

1
2
3
4
5
6
7
8
9

L21, L22 AS CLOSE JCA1 AS POSSIBLE

1
C446

1
2
3
4
5
6
7

GNDGND

USB20_P5 13
USB20_N5 13

D20
ROW PESD5V0U2BT 3P C/C SOT23 ESD

16

HRS_CL537-0918-4-86
CONN@

GND
GND

USB20_P5_R
USB20_N5_R

C357
@

MOLEX_48227-0701

C447

AS CLOSE AS JCA1

C359
@

47P 50V J NPO 0402

DMIC_DATA

USB20_P4
USB20_N4

BT_PRI 24
10_0402_5%
10_0402_5%

47P 50V J NPO 0402

100P_0402_50V 100P_0402_50V

RTCVREF

RTCVREF

1
D33
SDMK0340L-7-F

CLOSE TO U48
@ C655
0.1U_0402_16V4Z
51ON#

51ON#

29,32

2.2U_10V_K X7R_0603
U48

1
1
2

NC
A

Q58
2N7002_SOT23

2
G

TC7SZ14FU_SSOP5~D

R1305
100K_0402_5%
2

USB_DETECT#

C654
29 USB_DETECT#

R1304
100K_0402_1%~D

R1303
10K_0402_1%

RTCVREF

RTCVREF

25

USB20_P4
USB20_N4

2
4
6
8
10
12
14

13
13
+3VS
25

1
3
5
7
9
11
13

2
4
6 USB20_P5_R 2 R398
8 USB20_N5_R 2 R400
10
12
14

28
BT_DET
24
WLAN_ACT
28
BT_OFF#
28 BT_RADIO_OFF#

1
3
BT_OFF#
5
BT_RADIO_OFF# 7
9
11
13

JBT1
BT_DET

USB_P0

USB_N0

Camera Conn
L30 WCM2012F2S-900T04_0805
1 1
2 2

USB_DET#_DELAY

USB_DET#_DELAY 28

D31
SDMK0340L-7-F

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/02/19

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

USB/BlueTooth/FP/Felcia
Size Document Number
Custom LA-4631P
Date:

Tuesday, February 24, 2009

Rev
1.0
Sheet

27

of

42

29

KSI[0..7]

29

KSO[0..16]

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

KSO[0..16]

+3VS
EC_SMB_DA2

R362 2

1 4.7K_0402_5%

EC_SMB_CK2

R363 2

1 4.7K_0402_5%
29

BT_RADIO_OFF#

R366 2

1 4.7K_0402_5%

WAN_RADIO_OFF# R402 2

1 4.7K_0402_5%

WL_RADIO_OFF#

1 4.7K_0402_5%

R403 2

39
39
4
4

PM_SLP_S3#
6
PM_SLP_S5#
14
EC_SMI#
15
LCD_TST
16
BT_RADIO_OFF#17
UIM_DET
18
PS_ID
19
KB_BL_PWM# 25
FAN_SPEED1 28
WL_RADIO_OFF# 29
E51_TXD
30
0_0402_5%2
1R555 31
DP_HPD
ON_OFF
32
29 ON_OFF
PWR_BTN_LED# 34
29 PWR_BTN_LED#
EN_KBL#
36
29 EN_KBL#

R376
4.7K_0402_5%
1
2
1
2
R377
4.7K_0402_5%
+3VALW

EC_MUTE#

R380 1

2 10K_0402_5%

EN_KBL#

R392 1

2 10K_0402_5%

LID_SW_D#

R397 1

2 10K_0402_5%

KSO1

R375 1

2 47K_0402_5%

KSO2

R401 1

2 47K_0402_5%

EC_SMB_DA1

R359 2

1 4.7K_0402_5%

EC_SMB_CK1

R360 2

EC_GA20

R1252 1

2 10K_0402_5%

EC_KBRST#

R1253 1

2 10K_0402_5%

PCIE_WAKE#

R1277 1

2 10K_0402_5%

BT_DET

R1284 1

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

14 PM_SLP_S3#
14 PM_SLP_S5#
14 EC_SMI#
20
LCD_TST
27 BT_RADIO_OFF#
24
UIM_DET
32
PS_ID
29 KB_BL_PWM#
4 FAN_SPEED1
24 WL_RADIO_OFF#

+5VS

TP_DATA
TP_CLK

DIAG_LOOP3

DIAG_LOOP3

21

XCLKO

XCLKI
2
R552
0_0402_5%~D

122
123

1 4.7K_0402_5%

2 10K_0402_5%

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

R1261 1
@
2 0_0402_5%~D
EN_DFAN1
EN_DFAN1 4
IR EF
IREF
33
CHGVADJ_R 1
2
R358 0_0402_5%

83
84
85
86
87
88

EC_MUTE#
USB_EN#
USBSW_EN2#
USB_EN2#
TP_CLK
TP_DATA

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

GPI

LAN_CABDT 22

LAN_LOPWEN 22
CHGVADJ 33

EC_MUTE# 25
USB_EN# 27,29
USBSW_EN2# 29
USB_EN2# 29
TP_CLK 29
TP_DATA 29

R361
0_0402_5%
97
2
1HDMI_DET_C
HDMI_DET_C 21
STB_LAN#
98
STB_LAN# 30
BT_OFF#
99
BT_OFF# 27
109 LID_SW_D# 1
2
LID_SW# 14
@ D2
SDMK0340L-7-F
119 FRD#SPI_SO
120 FWR#SPI_SI
126 SPI_CLK
128 FSEL#SPICS#
73
74
89
90
91
92
93
95
121
127

USB_DET#_DELAY
USBSW_EN#
FSTCHG
BATT_CHG_LED#
CAPSLED#
BATT_LOW_LED#
EN_WLAN#
SYSON
VR_ON
ACIN

USB_DET#_DELAY 27
USBSW_EN# 29
FSTCHG 33
BATT_CHG_LED# 29
CAPSLED#
BATT_LOW_LED# 29
EN_WLAN# 24
SYSON
23,30,35
VR_ON
14,38
ACIN
14,32,33

SPI Flash (16Mb*1)

@ C409
1
2SPI_CLK_R
0.1U_0402_16V4Z~N
+3VALW
C410
1
2
0.1U_0402_16V4Z~N

20mils
2 R365

1
10K_0402_5%
U30

FSEL#SPICS# 2
1SPI_CS#
R367
15_0402_5%
FRD#SPI_SO 1
2SPI_SO
15_0402_5% R369

1
2
3
4

110
112
114
115
116
117
118

VGATE
EC_ENBKL
MCP79_ENVDD
BT_DET
SUSP#
PWRBTN#
BKLT_KB_DET#

V18R

124

+V18R
C411

VGATE

@
C650
0.1U_0402_16V4Z

MCP79_ENVDD 11,20
BT_DET
27
SUSP#
23,30,36,37
PWRBTN# 14
BKLT_KB_DET# 29

Close to U30
SPI_CLK_R

EC_ENBKL

2 R213
1
0_0402_5%

@
C645
22P_0402_50V8J

@
C646
22P_0402_50V8J

R214
10K_0402_5%

4.7U_0603_6.3V6K

2
C412

1
0.1U_0402_16V4Z

BKOFF#

R198 1
2
22K_0402_5%

MCP_PWRGD

R1270
@
KSI4 1
R1271
KSI6 1
@
R553 @
1

0_0603_1%
2 KSI5
0_0603_1%
2 KSI7
0_0603_1%
2 E51_TXD

22P_0402_50V8J
2

1
4

1
1

C413

IN

For ENE Debug

LID_SW_D#

OUT

MOLEX_53780-0370~D

FWR#SPI_SI

EC_RSMRST#

NC

4
5

SPI_CLK

LCD_TST

NC

GND
GND

SPI_CLK_R1 R370
2
15_0402_5%
SPI_SI
1 R372
2
MX25L1605DM2I-12G SOP 8P ROM
15_0402_5%

1
11 MCP79_ENBKL

ECAGND

X3

C414
22P_0402_50V8J

1
2
3

8
7
6
5

Close to U29
SPI_CLK

+3VALW

1
2
3

VCC
HOLD#
SCLK
SI

14,38

XCLKO 1 R381
2 XCLKI
@ 20M_0603_5%

JHS1

CS#
SO
WP#
GND

EC_RSMRST# 14
100 EC_RSMRST#
101 EC_LID_OUT#
EC_LID_OUT# 14
@
102 EC_ON
EC_ON
29
D13 RB751V_SOD323
103 R1251
1
20_0402_5%
PCIE_WAKE# 10,22,23,24
MCP_PWRGD
104 MCP_PWRGD_EC
1
2
MCP_PWRGD 14
105 BKOFF#
BKOFF#
20
106 WAN_RADIO_OFF#
1
2
1
2
+3VS
WAN_RADIO_OFF# 24
R378 0_0402_5% R379 10K_0402_5%
107 LCD_VCC_TEST_EN
LCD_VCC_TEST_EN 20
@
108 PSID_DISABLE#
PSID_DISABLE# 32

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

XCLK1
XCLK0

KB926QFD3 LQFP 128P

68
70
71
72

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2
Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
SM Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

FAN_SPEED1
1

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

2 0_0402_5%~D
LCD_DET# 20

ECAGND

Issued Date
32.768KHZ_12.5P_1TJS125BJ2A251

0.5A perCompal
each pinElectronics,

Compal Secret Data

Security Classification
2009/02/19

Deciphered Date

R1286
2
1
1K_0402_1%

1 4.7K_0402_5%

2 0.01U_0402_16V7K
BATT_TEMP 39
BATT_OVP 39
ADP_I
33

63
64
65
66
75
76

C405
0.1U_0402_16V4Z

M/B rev:0.1; 0.2; 0.3; 0.4; 0.5; 1.0

Voltage:0.0; 0.4; 0.8; 1.2; 1.65; 2.2

R364 2
1
100K_0402_5%

1 4.7K_0402_5%

R502 2

Low Enable

C406 1
BATT_TEMP
BATT_OVP
ADP_I
AD_BID
R1260 1
@

INVT_PWM 20
BEEP#
25
SLP_MCP79_MAC# 11
ACOFF
33

R1285
2
1
22K_0402_5%

R500 2

USB_EN2#

AD

R559 0_0402_5%~D
1
2
BEEP#
SLP_MCP79_MAC#
ACOFF

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

21
23
26
27

PWM Output

KSI[0..7]

+3VALW

USB_EN#

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

0.1U_0402_16V4Z

12
13
37
20
38

Rb

AD_BID
1

C408

15P_0402_50V8J

EC_SCI#
DP_CBL_DET

100K_0402_5%

R352

AGND

47K_0402_5%

14
21

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

Page 3 Note List

R350

69

1
@ C407

1
2
3
4
5
7
8
10

GND
GND
GND
GND
GND

+3VALW

LPC_CLK0
PLT_RST#
EC_RST#
SDMK0340L-7-F 2
1 D1
DP_CBL_DET 1
2
R554
0_0402_5%

12,24 LPC_CLK0
12,24 PLT_RST#

R357

@ 10_0402_5%

+3VALW

Ra

VCC
VCC
VCC
VCC
VCC
VCC
1

LPC_CLK0
R356

EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

Board ID

C398
0.1U_0402_16V4Z~N

1
ECAGND2
2
1
MURATA BLM18AG601SN1D 0603 L18

11
24
35
94
113

14
14
12
12,24
12,24
12,24
12,24
12,24

L17
2
1
+3VALW
MURATA BLM18AG601SN1D 0603

200K_0402_5%

U29

67

AVCC

+EC_AVCC

C397
1000P_0402_50V7K~N

9
22
33
96
111
125

C404
1000P_0402_50V7K~N

C403
1000P_0402_50V7K~N

C402
0.1U_0402_16V4Z~N

C401
0.1U_0402_16V4Z~N

C400
0.1U_0402_16V4Z~N

C399
0.1U_0402_16V4Z~N

+EC_AVCC

+3VALW

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Inc.

Title

BIOS & EC I/O Port

Size Document Number
Custom LA-4631P
Date:

Tuesday, February 24, 2009

Rev
1.0
Sheet

28

of

42

INT_KB_Conn.1
+3VALW

R382

100K_0402_5%

Power Button
D14
2

PWR_ON-OFF_BTN#

28

28
28

51ON#

ON_OFF

28

51ON#

27,32

JKB1

DIAG_LOOP3

DIAG_LOOP3

KSO[0..16]

KSO[0..16]

ROW BAV70W-7-F 3P C/C SOT-323

@
D15
RLZ20A_LL34

1
EC_ON

1
R384
0_0402_5%

D
Q7
S SSM3K7002FU_SC70-3

2
G

28

EC_ON

C435
1U_0805_25V4Z~D

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

KSI[0..7]

KSI[0..7]

R383
10K_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GND
GND

31
32

KSI0

C542

100P_0402_25V8K

KSO6

C556

100P_0402_25V8K

KSI1

C543

100P_0402_25V8K

KSO7

C557

100P_0402_25V8K

KSI2

C544

100P_0402_25V8K

KSO8

C558

100P_0402_25V8K

KSI3

C545

100P_0402_25V8K

KSO9

C559

100P_0402_25V8K

KSI4

C546

100P_0402_25V8K

KSO10

C560

100P_0402_25V8K

KSI5

C547

100P_0402_25V8K

KSO11

C561

100P_0402_25V8K

KSI6

C548

100P_0402_25V8K

KSO12

C562

100P_0402_25V8K

KSI7

C549

100P_0402_25V8K

KSO13

C563

100P_0402_25V8K

KSO0

C550

100P_0402_25V8K

KSO14

C564

100P_0402_25V8K

KSO1

C551

100P_0402_25V8K

KSO15

C565

100P_0402_25V8K

KSO2

C552

100P_0402_25V8K

KSO16

C566

100P_0402_25V8K

KSO3

C553

100P_0402_25V8K

DIAG_LOOP3

C567

100P_0402_25V8K

KSO4

C554

100P_0402_25V8K

KSO5

C555

100P_0402_25V8K

For EMI

+3VS

TYCO_3-2041084-0

R157
10K_0402_5%

JBTB1

B to B Conn.

Q41
+5VS_KBL
SI3456BDV-T1-E3 1N TSOP6 W/D @
F4
0.75A_24V_1812L075-24DR
6
5
4
2
1
2
20mil
1
1
2
R305
0_0805_5%
BKLT_KB_DET

13
13

USB20_N1
USB20_P1

13
13

USB20_N2
USB20_P2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

USB20_N1
USB20_P1

+5VS

1
2

20mil
R395
100K_0402_5%

13 SATA_A1_TXP
13 SATA_A1_TXN

Q42
MMBF170-7-F NPN SOT-23
S

13
13

SATA_A1_RXN
SATA_A1_RXP

26
26

IEEE_TPB1N
IEEE_TPB1P

26
26

IEEE_TPA1N
IEEE_TPA1P

R371
470K_0402_5%

BKLT_KB_DET# 28

2
G
3

B+_BIAS

BKLT_KB_DET#

C415
1U_0603_10V6K

1
EN_KBL#

28

EN_KBL

2@ R373

1 1.5M_0402_5%
+5VS_KBL

Q39
SSM3K7002FU_SC70-3

2
G

BKLT_KB_DET
KB_BL_PWM

20mil

1
2
3 GND
4 GND

IEEE 1394 Port

5
6

TYCO_2041084-4
CONN@

28 USBSW_EN2#

SATA_A1_TXP
SATA_A1_TXN
SATA_A1_RXN
SATA_A1_RXP
IEEE_TPB1N
IEEE_TPB1P
IEEE_TPA1N
IEEE_TPA1P
USB_OC#1
USB_OC#2
USB_EN#
USBSW_EN#
USB_EN2#
USB_DETECT#
BATT_CHG_LED#
BATT_LOW_LED#
PWR_BTN_LED#
PWR_ON-OFF_BTN#
USBSW_EN2#

Q40
MMBF170-7-F NPN SOT-23

2
G
3

28 KB_BL_PWM#

13
USB_OC#1
13
USB_OC#2
27,28 USB_EN#
28 USBSW_EN#
28 USB_EN2#
27 USB_DETECT#
28 BATT_CHG_LED#
28 BATT_LOW_LED#
28 PWR_BTN_LED#

JKB2
1
2
3
4

USB20_N2
USB20_P2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

GND
GND

61
62

+5VALW

+3VALW
+MIC1_VREFO
MIC_JD
MIC_RIGHT
MIC_LEFT

MIC_JD 25
MIC_RIGHT 25
MIC_LEFT 25

HP2_JD
HP2_RIGHT
HP2_LEFT

HP2_JD 25
HP2_RIGHT 25
HP2_LEFT 25

HP1_JD
HP1_RIGHT
HP1_LEFT

HP1_JD 25
HP1_RIGHT 25
HP1_LEFT 25

TWSPK_R1
TWSPK_R2

TWSPK_R1 25
TWSPK_R2 25

Tweeter Channel R output

E-T_1001-F60E-03R
CONN@

20mil
3

Touch PAD/B Conn.

CONN@
TYCO_2041084-4

+5VS
28
28

4
3
2
1

TP_DATA
TP_CLK

TP_DATA
TP_CLK

2009/02/19

D16
PESD5V0U2BT 3P C/C SOT23 ESD

Compal Electronics, Inc.

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Secret Data

Security Classification
Issued Date

6
5

100P_0402_25V8K C442

100P_0402_25V8K C441

1
C440
0.01U_0402_16V7K

4 GND
3 GND
2
1
JTP1

Title

PWR_OK/BTN/TP
Size Document Number
Custom LA-4631P
Date:

Rev
1.0
Sheet

Tuesday, February 24, 2009

E

29

of

42

+3VALW to +3VS Transfer

+3VALW

+5VALW to +5VS Transfer

+1.05VALW to +VCCP Transfer

+3VS

B+_BIAS

+5VALW

+5VS

+1.05VALW

1
C497

RUNON

1
2
R463
1
100K_0402_5%

Q18
S SSM3K7002FU_SC70-3

2
G

C498

C499

C500

D
D
D
D

S
S
S
G

1
2
3
4

8
7
6
5

U44

AO4478L 1N SO8
2 10U_0805_10V4Z~N

C502

C503
10U_0805_10V4Z~N

2
2
0.1U_0402_16V4Z~N

3VS_GATE

RUNON 1
2 1 5VS_GATE
R464
C507
47K_0402_5%
0.01U_0402_25V7K~N
2

0.1U_0402_16V4Z~N
C506
0.01U_0402_25V7K~N

SUSP

S
S
S
G

AO4478L 1N SO8
2 10U_0805_10V4Z~N

D
D
D
D

U43

R461

10U_0805_10V4Z~N

1
2
3
4

SUSP

2
G

R462
47K_0402_5%

8
7
6
5

+VCCP

B+_BIAS

U42

330K_0402_5%

8
7
6
5

D
D
D
D

10U_0805_10V4Z~N

1
2
3
4

S
S
S
G

C501
AO4430L 1N SO8
2 10U_0805_10V4Z~N

C504

C505
1

0.1U_0402_16V4Z~N
2
2

1.05VS ON1
1.05VS_GATE
2
R465
1
100K_0402_5%
C508
D
0.01U_0402_25V7K~N
2
Q19
S SSM3K7002FU_SC70-3

+3VALW TO +3V_LAN
+3VALW

+1.5V to +1.5VS Transfer

+3V_LAN

+3VALW to +3V_DP Transfer

+3VS

R1278
0_0805_5%
1
2

U45

1
C509

2
G
2N7002_SOT23

SUSP

Q22
S SSM3K7002FU_SC70-3

2
G

0_0402_5%~D

C515

@
R557

330K_0402_5%

470P_0402_50V7K~D

SUSP

2
G
3

0.1U_0603_25V7K

2
+VCCP
0.1U_0402_16V4Z~N

8
7
6
5

@
C609

D
D
D
D

S
S
S
G

1
2
3
4

10U_0805_10V4Z~N
2

1 @
1 @
C610
C611

@ AO4478L 1N SO8
2 10U_0805_10V4Z~N

C516

AO4478L 1N SO8

+3V_DP

U47

1
2
3
4

S
S
S
G

1
2
1

R469
1

STB_LAN#

D
D
D
D

R466
100K_0402_5%~D

8
7
6
5

R467
470_0805_5%

Q21

B+_BIAS

U46

1
2

332K_0402_1%

Q23

2
1U_0603_10V4Z

+3VALW

+1.5VS

2
2
R UN_DP 1
3DP_GATE
2
@ R558
1
100K_0402_5%
0.1U_0402_16V4Z~N
@ C612
D
0.01U_0402_25V7K~N
2
@
Q46
S SSM3K7002FU_SC70-3

+1.8VS

Discharge Circuit

+VCCP

+1.5VS
1

+CPU_CORE

R472

10U_0805_10V4Z

10U_0805_10V4Z

2
G
2N7002_SOT23

R503
0_0402_5%~D
1
2
1

10U_0805_10V4Z

STB_LAN#

1
1
C510 C511

AO4478L 1N SO8

R476

+1.5V

R483

S Q35
SSM3K7002FU_SC70-3

2
SUSP

SUSP

S Q27
SSM3K7002FU_SC70-3

S Q28
SSM3K7002FU_SC70-3

2
G

2
G
3

2
G
3

1 2

1
SYSON

S Q33
SSM3K7002FU_SC70-3

Q24
SSM3K7002FU_SC70-3

2
G
3

SYSON

23,28,35

SUSP

SYSON# 2
G

2
1

SYSON#

470_0402_5%

470_0402_5%

100K_0402_5%

470_0402_5%
470_0402_5%

R531

R485

+3VALW

R471

28

2
1
R470
47K_0402_5%

+1.5V

20K_0402_5%~D

B+_BIAS

S
S
S
G

C514

1
C513

D
D
D
D

B+_BIAS

1
2
3
4

R468
10U_0805_10V4Z~D

1
C512

8
7
6
5

+0.75VS

+5VS

+3VS
1

1
1

R480
R484
470_0402_5%

R482
470_0402_5%

2
1
A

D
SUSP

2
G

D
SUSP

2
G

S Q30
SSM3K7002FU_SC70-3

S Q31
SSM3K7002FU_SC70-3

SUSP
Q34
SSM3K7002FU_SC70-3

1
SUSP#

23,28,36,37 SUSP#

100K_0402_5%
SUSP

SUSP

2
G

SUSP

R474
4

1
1

470_0402_5%

+5VALW

R481

470_0402_5%
2

+3V_WLAN
R473
10K_0402_5%

S Q32
SSM3K7002FU_SC70-3

2
G
4

Q25
SSM3K7002FU_SC70-3

2
G

2009/02/19

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R478
10K_0402_5%

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

DC/DC Circuits
Size Document Number
Custom LA-4631P
Date:

Rev
1.0
Sheet

Tuesday, February 24, 2009

E

30

of

42

FD2
FIDUCAL

FD3
FIDUCAL

FD4
FIDUCAL
@

@
1

FD1
FIDUCAL
@

H1
@ HOLEA

H_2P2

H2
@ HOLEA

H4
@ HOLEA

H5
@ HOLEA

H6
@ HOLEA

H7
@ HOLEA

H8
@ HOLEA

H10
@ HOLEA

H11
@ HOLEA

H12
@ HOLEA

H13
@ HOLEA

H_2P8
C

11pcs

H21
@ HOLEA

H16
@ HOLEA

H22
@ HOLEA

H14
@ HOLEA

H15
@ HOLEA

H_3P2

H20
@ HOLEA

H19
@ HOLEA

H_3P0

H17
@ HOLEA

H18
@ HOLEA

H_4P2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/02/19

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Screws
Size Document Number
Custom LA-4631P
Date:

Rev
1.0
Sheet

Thursday, February 19, 2009

1

31

of

42

PC1
2200P_0402_50V7K~D

PR1
@ 56K_0402_5%~D

@
ADPIN

VIN
1

VS

VIN

1
2

PC8
1
2
8

@
PR7
10K_0402_5%~D

@ PR9
10K_0402_5%~D
1

RTCVREF

3.3V

8
+

LM393DR_SO8

Vin Detector

VS

Max.
18.234
17.597

L-->H
H-->L

typ.
17.841
17.210

Min.
17.449
16.813

1
PC12
0.1U_0603_25V7K~D

51ON#_Gate

51ON#

14,28,33

32.8

PR12
22K_0402_5%~D
1
2

@
PD1
RLZ4.3B_LL34

@ PU1B

PQ1
S 1TR BSS84 1P SOT-23 W/D

ACIN

PR11
100K_0402_5%~D

0.22U_1206_25V7K

PC11
2
1

CHGRTCP

33_1206_5%~D
PR10

1
2

RLS4148_LL34-2
C

RLS4148_LL34-2

VinDe_Out

LM393DR_SO8

2
1

@
PC10
1000P_0402_50V7K~D

PJP1
@ JUMP_43X118
1 1
2 2

PD3
2

VinDe_Ref
2 -

PU1A

@
PR5
@ PR3
10K_0402_5%~D
1K_0402_5%~D
1
2

32.3

PD2

BATT+

VinDe_IN3

1
2

1
2

PR8
19.6K_0402_1%~D
2
1

PC9
0.1U_0402_16V7K~D

VIN

PR6
@ 22K_0402_1%~D
1
2

N41
@

PL2
BLM18BD102SN1D_0603~D
2
1 DOCK_PSID

PSID

@
PR4
82.5K_0402_1%~D

PC7
1000P_0402_50V7K~D
2
1

PC6
100P_0402_50V8J~D
2
1

1000P_0402_50V7K~D

PC5

1
2

1
2

PC4
100P_0402_50V8J~D

1000P_0402_50V7K~D

PC3

ACES_88299-0600

27,29

PR2
@ 1M_0402_1%~N
1
2

VIN

1
2
3
4
5
6
7
8

PC2
100P_0402_50V8J~D

1
2
3
4
5
6
GND
GND

PL1
FBMJ4516HS720NT_1806~D
1
2

PJPDC1

0.01U_0402_25V7K~D

PR13
200_0805_5%

+3VALW

1
2

GND

@
MAX1615_#SHDN 1
2
PR14 0_0402_5%~D

MAX1615EUK+_SOT23-5~D

PR15
1
2
0_0402_5%~D

PC14
1U_0805_25V4Z~D

DOCK_PSID

PR17
33_0402_5%~D
1
2

PR16
2.2K_0402_5%~D
1
2

#SHDN

MAX1615_IN

5/3+

IN

PD4
DA204U_SOT323~D

OUT

PC13
1
2

4.7U_0805_6.3V6K~D

PU3

+5VALW

RTCVREF

PS_ID

28

PQ2

+3VALWP

PJP6
@ JUMP_43X118
1 1
2 2

+3VALW

PJP8
@ JUMP_43X118
1 1
2 2

+1.5VP

PJP12
@ JUMP_43X118
1 1
2 2
PJP14
@ JUMP_43X118
1 1
2 2
5

2
G

PJP7
@ JUMP_43X118
1 1
2 2

+1.0VSP

@
PD5
SM24_SOT23

PD6
DA204U_SOT323~D

PQ3
MMST3904-7-F_SOT323~D
E

PR19
10K_0402_1%~D

1
C

2
B

PR21
1
@

PSID_DISABLE# 28

2
10K_0402_1%~D

+1.0VS

PJP9
@ JUMP_43X118
1 1
2 2

PJP10
@ JUMP_43X118
1 1
2 2

+1.05VALW

PJP2
@ JUMP_43X118
1 1
2 2

+5VALW

+1.05VALWP

PJP4
@ JUMP_43X118
1 1
2 2

+5VALW

+5VALW

PJP5
@ JUMP_43X118
1 1
2 2

PR20
PR18
15K_0402_1%~D 100K_0402_1%~D
1
2
1
2

PJP3
@ JUMP_43X118
1 1
2 2

+5VALWP

SSM3K7002FU_SC70-3

+0.75VSP

PJP11
@ JUMP_43X118
1 1
2 2

+1.8VSP

PJP13
@ JUMP_43X118
1 1
2 2

+1.5V

+0.75VS

Compal Secret Data

Security Classification
Issued Date

2006/10/1

2007/5/01

Deciphered Date

DCIN / Precharge

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

+1.8VS

Size Document Number

Custom
KCM00
Date:

Rev
1.0
Sheet

Tuesday, February 24, 2009

1

32

of

10

PC32
1U_0603_10V6K~D

PR33
100K_0402_1%~D

FDS6690AS_NL_SO8

2ACOP 7 ACOP
PC34
0.47U_0603_16V7K~N

LODRV

23

PGND

22

LEARN

21

CELLS

20

DL_CHG

4
3
2
1
G
S
S
S
D
D
D
D
5
6
7
8

PR29
0.02_2512_1%

3
1

BATT+
1

24

ACSET

PC23
4.7U_1206_25V6K~D

PR30
4.7_1206_5%~D

PQ7
FDS4435BZ_SO8

PC171
10U_1206_25V6M~D

RLS4148_LL34-2
PC28
0.1U_0603_25V7K~D

0.01U_0402_25V7K~D

PC20
2

/BATDRV

PC30
10U_1206_25V6M~D

PQ8
REGN

PC19

5
6
7
8

1
1

PL3
10UH_SIL1045RA-100PF_4.5A_30%
1
2

25

PH

ACDRV
ACDET

DH_CHG
LX_CHG
PD7
2
REGN

PR31
124K_0402_1%
1
2

CP setting

4.7U_1206_25V6K~D
2
1

26

5
6
7
8

HIDRV

PR27
FDS6690AS_NL_SO8
2.2_0603_5%~D
BTST 1
2
4

4
5

ACN
ACP

PQ6

PR23
100K_0402_1%~D

8
9

AGND

ACOFF 28

VREF
CELLS

PC36
0.1U_0603_25V7K~D

PC37
@0.1U_0603_25V7K~D

VDAC

11

SRP

19

SRP

SRN

18

SRN

BAT

17

TP

29

SRSET

16

IADAPT

15

VADJ
ACSET

12

VADJ

CELLS
13

2
3cell/4cell# 39
G
PQ10
2N7002 1N SOT-23

BATDRV

IREF

28

14

RTCVREF

PR38
2
1
60.4K_0402_1%~D

IADAPT
1

PR39
100K_0402_1%~D

PR42
10_0603_5%~D

PC41
@0.01U_0402_25V7K~D

PR40
100K_0402_1%~D

PR41
100K_0402_1%~D

ACIN

PJP16
28

IREF

PC42
100P_0402_50V8J~D
PR43
@ 0_0402_5%~D

MOLEX_53780-0370~D
@

CHGVADJ

PQ11
2N7002 1N SOT-23

2
G

Current

14,28,32

0V

0A

3.3V

3A

VADJ

28

PR44
210K_0402_1%~D
1
2

GND
GND

ACGOOD#

ADP_I
1

REGN

4
5

1
2
3

1
2
3

+COINCELL

VREF

BQ24751ARHDR_QFN28_5X5

Cells selector

/BATDRV

ICHG setting

ACGOOD

ACGOOD#

PC39
0.1U_0603_25V7K~D

PC40
0.1U_0603_25V7K~D

PR37
47K_0402_1%~D

PR36
100K_0402_1%~D
1
2GATE

4 Cell

3 Cell

VREF

GND

CELLS

VREF

VREF

PC38
1U_0603_10V6K~D

10

PQ9
SI2301BDS-T1-E3_SOT23-3

PR35
54.9K_0402_1%

Fsw : 300KHz

PC35
0.1U_0402_16V7K~D
1
2
1

Input UVP : 16.98V

OVPSET

OVPSET

Input OVP : 22.3V

Iadapter=(Vacset/Vvdac)*(0.1/PR217)=3.34A
2

27

PR34
340K_0402_1%~D

Icharge=(Vsrset/Vvdac)*(0.1/PR222)=3.3A

BTST

ACSET

90W adapter

PVCC

PC17
0.1U_0805_25V7K
1
2

PC33
680P_0603_50V8J~D

2
3

ACDET

PC31
0.01U_0402_25V7K~D
@

PC24

3
2
1

ACN
ACP

VREF

1000P_0402_50V7K~D
1

PC26
0.1U_0603_25V7K~D

ACDRV

PR32
54.9K_0402_1%

PVCC

CHGEN#

PC25
0.1U_0603_25V7K~D

PR28
340K_0402_1%~D

PC27
2.2U_0805_25V6K

CHGEN

28

PU4
1

PC29
10U_1206_25V6M~D

PL13
SUPPRE_TDK MPZ1608S300AT 0603
CHG_B+
1
2
PC18
2

PC22

PC16
0.1U_0402_16V7K~D
1
2

2
1

8
7
6
5

D
D
D
D

PR26
100K_0402_1%~D

1
3.3_1210_5%~D

S
S
S
G

1000P_0402_50V7K~D
1

1
2
3
4

B+
PR22
0.015_2512_1%

1
2
3
4
PC21
0.01U_0402_25V7K~D
2
1

S
S
S
G

PR24
3.3_1210_5%~D

1
1

D
D
D
D

PQ5
FDS4435BZ_SO8

PC15
0.01U_0603_50V7K~D

PR25

1 2

8
7
6
5

4.7U_1206_25V6K~D
2
1

PQ4
FDS4435BZ_SO8

VIN

3
2
1

GATE

3.3V

PC44
0.1U_0402_16V7K~D

3V

PQ15
2N7002 1N SOT-23

2
G

CHGEN#
D

PQ14
2N7002 1N SOT-23

2
G

28 FSTCHG

PR52
340K_0402_1%~D

4.2V

SSM3K7002FU_SC70-3

2006/10/1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/5/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

PQ13
2N7002 1N SOT-23

PR48
100K_0402_1%~D

ACOFF

2
G

0V

Battery Voltage/per cell

PR50
100K_0402_1%~D

CHGVADJ

PR47
200K_0402_1%~D

B+_BIAS

2
1
2
PQ16
2
G

220K_0402_5%

PR53

32.8

PC43

2
S DIO 1SS355
1

1
2

PD8

2
PR51
1
PC45
0.1U_0603_25V7K~D
2
1

220K_0402_5%

PR49

+5VALW

32.8

VREF

VREF
VREF

0.1U_0805_25V7M~N

100_0805_5%~D

470K_0402_5%~D

B+

PQ12
S 1TR BSS84 1P SOT-23 W/D

PR46

PR45
499K_0402_1%~D

Title
Size
B
Date:

Charger
Document Number

Rev
1.0

KCM00
Sheet

Tuesday, February 24, 2009

E

33

of

10

ISL6237_B+

ISL6237_B+

B+

25

PHASE2

PHASE1

16

PC57
0.1U_0603_25V7K~D
LX5

1
2
3

DL3

23

LGATE2

LGATE1

18

DL5

FB3

PGND

22

30

OUT2

VL

OUT1

10

32

REFIN2

FB1

11

BYP

SKIP

29

2VREF_ISL6237
1

PC51
2200P_0402_50V7K~D
2
1

BST5A 2
1
2.2_0603_5%~D

3
2
1

LX3

PC50
4.7U_0805_25V6K~D
2
1

5
6
7
8

FDS6690AS_NL_SO8

17

PR58

PC169
10U_1206_25V6M~D

BOOT1

PC56
0.1U_0603_25V7K~D

PQ19

DH5

PR60
61.9K_0402_1%~D
1
2

19
15

3
2
1

4.7U_0805_6.3V6K~D

PC59
2
1

1U_0603_10V6K~D

PVCC

UGATE1

+5VALWP

PL4
2
1
3.3UH +-20% FDVE1040-3R3M 11.3A

PC60

BOOT2

VCC

24

6
VIN

UGATE2

1 BST3A
2.2_0603_5%~D

TP

26

PR56
4.7_1206_5%~D
2
1

FDS6690AS_NL_SO8

33

PC54
1U_0603_10V6K~D
1
2

8
7
6
5

PR57

+ PC61
330U_D3L_6.3VM_R25M

PR62
9.76K_0402_1%~D
1
2

DH3
PQ20

680P_0603_50V8J~D
2
1

330U_D3L_6.3VM_R25M
2

PC58
PR55
680P_0603_50V8J~D 4.7_1206_5%~D
2
1
2
1

2
+

PR59
0_0402_5%~D

1
PC55

PR61
10K_0402_1%~D

1
2

PC168
10U_1206_25V6M~D

PU5

LDO

PC53
1
2

1
2
3

PC52
0.1U_0603_25V7K~D

PC49
4.7U_0805_25V6K~D
2
1

8
7
6
5

FDS8884_SO8

PL5
1
2
3.3UH +-20% FDVE1040-3R3M 11.3A

+3VALWP

PQ18

VL
PQ17
FDS8884_SO8

5
6
7
8

PC48
2200P_0402_50V7K~D
2
1

PC47
4.7U_0805_25V6K~D
2
1

PR54
0_0805_5%
1
2
PC46
4.7U_0805_25V6K~D
2
1

PJP17
@ JUMP_43X118
1 1
2 2

FB5

REF

PC62 0.22U_0603_10V7K~D

LDOREFIN

Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical)

@ PR63
6237_SKIP2
PR64
1

PC63
0.22U_0603_25V7-K

28

EN_LDO

POK1

13

EN1

6237_EN2 27

EN2

POK
PR67

ILIM1

12

ILM1

ILIM2

31

ILIM2

267K_0402_1%~D
1

GND
21

NC

TON
2

5
1

Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical)

PC64

2VREF_ISL6237
2

0.047U_0603_16V7K~D

1
2

PC65

1U_0603_10V6K~D

PR70
0_0402_5%~D

806K_0603_1%

2
PR71

PR73
@ 47K_0402_5%~D

1
309K_0402_1%

ISL6237IRZ-T_QFN32_5X5

6237_TON

PQ21
S TR BSS84 1P SOT-23 W/D

POK2

14

@ PR69
0_0402_5%~D

0_0402_5%~D

NC

6237_NC

PR72

VL

0_0402_5%~D
2

PR68

VL

39 MAINPWON

6237_EN1

2VREF_ISL6237 1

Fsw=300kHz

EN_LDO

Iocp=11A
B

20

PR65
100K_0402_1%~D
2

PC66
0.047U_0402_16V7K~N
2
1

Imax=8.5A

PD9
RLZ5.1B_LL34
1
2

VS

PR66
200K_0402_5%~D
1
2

3.3VALWP

0_0402_5%~D
1

5VALWP
PR74
@

Imax=7.5A

0_0402_5%~D

Iocp=9.8A
Fsw=400kHz

PD10

2
S DIO 1SS355

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/10/1

Issued Date

Deciphered Date

2007/05/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

+3VALWP, + 5VALWP

Size Document Number

Custom
KCM00
Date:

Tuesday, February 24, 2009

Rev
1.0
Sheet
1

34

of

10

PJP18
@ JUMP_43X118
1 1
2 2

SI4430BDY
Rds(on)=4.8mohm~6mohm
PHASE_1.5V

1.5VP

6269_1.5V

UG_1.5V
PR76

1
PR75
10K_0402_1%~D

2.2_0603_5%~D
+5VALW
BOOT_1.5V

Imax=13A

2
PC69

Iocp=16.9A

0.1U_0603_25V7K~D

1
2

PC68
10U_1206_25V6M~D

10U_1206_25V6M~D

PC67

6269_B+

B+

13

14
UG

BOOT

PHASE

GND
VIN

PGOOD

15

17

PU6

16

PVCC

PR78
1

5
6
7
8

PR77
0_0603_5%~D
4.7_0603_5%~D
2 6269_1.5V

PC70
1
2

12

Fsw=231kHz
PQ22
SI4172DY-T1-GE3 1N

4
C

VCC

FCCM

11

PGND

10

LG_1.5V

PL6
1.5UH +-20% FDVE1040-H-1R5M=P3 17.1A
1
2

+1.5VP
+1.5VP

5
6
7
8
PQ23
SI4430BDY_SO8

PR82
7.15K_0402_1%~D

2
PC74
680P_0603_50V8J~D

PR84

PR85
57.6K_0402_1%~D

PC77
0.01U_0402_25V7K~D
1

49.9K_0402_1%~D

PR86
1.33K_0402_1%~D
2

PC78
2200P_0402_50V7K~D

1
2

PC76

22P_0402_50V8J~D

ISL6269ACRZ-T_QFN16_4X4

3
2
1

0.1U_0402_16V7K~D

PC73
220U_D2_4VM~D

PR83
2K_0402_1%~D

+ PC72
+
220U_D2_4VM~D

ISEN_1.5V
1

VO

PC75

PR80
4.7_1206_5%~D
2 1

ISEN
FSET

EN
COMP

LG

FB

PR81
22K_0402_1%~D
1
2
1

23,28,30 SYSON

PR79
0_0402_5%~D
1
2

6269_1.5V
PC71
2.2U_0603_6.3V6K~D

3
2
1

2.2U_0603_6.3V6K~D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/10/1

Deciphered Date

2007/05/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

1.5VP
Size

Document Number

Rev
1.0

KCM00
Date:

Tuesday, February 24, 2009

Sheet
1

35

of

10

PC80
1U_0402_6.3V6K~D

PC79
1U_0402_6.3V6K~D

PGOOD1 PGOOD2 1K @

PR88
1

1
2

PC81
0.1U_0603_25V7K~D

+5VALWP

PR89

2 PR90

ISL6228_B+

1K_0402_1%~D
@

+5VALWP

PC82
0.1U_0603_25V7K~D
2 PR91

10_0603_1%

ISL6228_B+

10_0603_1%

PR96

FB1

GND_T

29

PGOOD2

28

FSET2

VIN2

VCC1

VIN1

FSET1

68K_0402_1%~D
PR97

VCC2

1
PGOOD1

2 PR98

ISL6228_B+

10

OCSET1

VO2

26

2
4

PQ26
FDS8884_SO8

UG_1.05VALWP
13 UGATE1

PHASE2

@ 0.01U_0402_25V7K~D
23
4

1
2

PC100
PR111

2.2_0603_5%~D
PC103
1U_0402_6.3V6K~D

0.1U_0402_16V7K~D
3
2
1

PC102
1U_0402_6.3V6K~D

SI4386DY_SO8
2

1
+5VALWPBST_1.0VSP
2

+1.05VALWP

PR110
4.7_1206_5%~D

0.75UH 20% FDVE0630-R75M=P3 13.4A

1

PQ27

DCR 10m ohm(max)

+5VALWP

(0.75V~1.05V)
PL8
1

5
6
7
8

BOOT2

LX_1.0VSP

PC96
2

PR107
11K_0402_1%~D

UG_1.0VP

22

21

PVCC2
20

LGATE2
19

PGND2
18

17

PGND1

LGATE1

PVCC1
15

1
2
3

UGATE2

3
2
1

14 BOOT1
1BST_1.05VALWP

1 2

16

PR108
PC98
0_0603_5%~D
0.1U_0402_16V7K~D

.015U_0402_16V7K~D

+
2

+1.0VSP

PC172
10U_1206_25V6M~D

8
7
6
5

1
PQ25
FDS6690AS_NL_SO8

23,28,30,37

SUSP#

PC93

PC167
10U_1206_25V6M~D
2
1

24

5
6
7
8

EN2

ISL6228_B+

PR105
0_0402_5%~D
1
2

ISL6228HRTZ-T_QFN28_4X4
PHASE1

PR189
0_0402_5%~D

25

PC99
220U_X_2VM_R7M~D

OCSET2

PU7

EN1

PC95
4.7U_1206_25V6K~D

11

1.05VALWP_EN

1
2
1
2

+1.0VS

11K_0402_1%~D

+
2

PR102
PQ24
FDS8884_SO8

LX_1.05VALWP12

PC97
680P_0603_50V8J~D

PC92

220U_X_2VM_R7M~D

PC123
10U_1206_25V6M~D

1
2

PC170
10U_1206_25V6M~D
2
1

68K_0402_1%~D

1UH_FDV0630-1R0M-P3_10.3A_20%
PR106
4.7_1206_5%~D

@ PR109
0_0402_5%~D
1
2

PR101
FB2_+1.0VSP

27

8
7
6
5

PC90
4.7U_1206_25V6K~D

FB2

PR99
681_0402_5%~D
1000P_0402_50V7K~D
86.6K_0402_1%~D PR100
PC88
2
1
1
2

+5VALWP

PC94
4.7U_1206_25V6K~D
2
1

PL7
1

+1.05VALWP

VO1

1
2
3

PR103
12.1K_0402_1%~D

PC89
4.7U_1206_25V6K~D
2
1

2
C

PC91
.01U_0402_16V7K~D
1
2

1K_0402_1%~D
@

12.1K_0402_1%~D

PC101
680P_0603_50V8J~D

2
2

2
PR95

PC87
2
1

PC86
1000P_0402_50V7K~D PR93
18.2K_0402_1%~D

PR92
PC85
22K_0402_1%~D
1000P_0402_50V7K~D

PR94
86.6K_0402_1%~D

1000P_0402_50V7K~D 681_0402_5%~D

2.2_0603_1%~D

1
2

ISL6228_B+

2200P_0402_50V7K~D
PC173

1
2

PR87
2

+5VALWP

2.2_0603_1%~D

PC84
680P_0402_50K X7R~D

B+

PC83
470P_0402_50V8J~D

PJP19
@ JUMP_43X118
1 1
2 2

DCR 6.2m ohm(max)

1.0VSP

Imax=7A
LG_1.05VALWP

Imax=9.3A

LG_1.0VSP

Iocp=9.1A
Iocp=12.1A

Fsw=303kHz
Fsw=366kHz
+1.0VSP

PR112
0_0402_5%~D
2
1

1
2

2
1

PR115
374K_0402_1%

PR114
200K_0402_1%~D

1
1

2
1

Issued Date

Compal Secret Data

2006/10/1

Deciphered Date

2007/5/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

PC107
0.1U_0402_16V7K~D

FB2_+1.0VSP

Security Classification

0.75

PR121
100K_0402_5%~D
1
2
14
MCP_CORE_VID0

2
G
2

@ PR118
10K_0402_1%~D

@ PR124
22K_0402_1%~D

+3VALW

0.77

PC106
0.1U_0402_16V7K~D

PQ30
SSM3K7002FU_SC70-3

PC105
0.1U_0402_16V7K~D

2
G

PR120
100K_0402_5%~D
1
2
14
MCP_CORE_VID1
@ PR123
22K_0402_1%~D

0.79

@ PR117
10K_0402_1%~D

0.80

+3VALW

2
G

PQ29
SSM3K7002FU_SC70-3

0.87

PR119
100K_0402_5%~D
1
2
14
MCP_CORE_VID2

0.90

@ PR116
10K_0402_1%~D

@ PR122
22K_0402_1%~D

+3VALW

PR113
54.9K_0402_1%

0.98

1.05

VID2 VID1 VID0 voltage

PQ28
SSM3K7002FU_SC70-3

PC104
0.01U_0402_25V7K~D

1.05VALWP_EN
1

+3VALWP

Title

1.05VALWP/+1.0VSP
Size

Document Number

Rev
1.0

KC M 00
Date:

Tuesday, February 24, 2009

Sheet
1

36

of

10

PJP20 JUMP_43X118

@
PU8

RT9025

EN

VDD

VOUT

ADJ

PGOOD

PC108
0.1U_0402_16V7K~D
@

GND

GND

PC109
10U_1206_25V6M~D

PC111
10U_1206_25V6M~D
PC112
1U_0402_6.3V6K~D

PR127
2.37K_0402_1%~D

GND

PC110
0.1U_0402_16V7K~D
@

+5VALW

GND

PR125 0_0402_5%~D

+1.8VSP

VIN

PR126
3.01K_0402_1%~D
2
1

23,28,30,36 SUSP#

NC

NC
1

+3VALW

+1.8VSP
Imax=0.3A

VTT

VTTSNS

GND
VTTREF

10

8
6

+3VALW
1

VIN

VLDOIN

PR128
2

1
0_0402_5%~D

PC119
0.1U_0402_16V7K~D
@

SUSP#

PC113
23,28,30,36
0.1U_0402_16V7K~D
2

S3

S5

PGND

VDDQSNS

1
2

10U_0805_10V6K~D
PC117

10U_0805_10V6K~D
PC116
2
1

+0.75VSP

PC118
1U_0603_10V6K~D

RT9026_MSOP10

GND

PU9

11

JUMP_43X118
@

4.7U_0805_6.3V6K~D

PC114
2
1

+1.5VP

PC115
2
1

PJP21

4.7U_0805_6.3V6K~D

+0.75VSP
Imax=1.5A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/10/1

2007/05/30

Deciphered Date

+0.75VSP/ 1.8VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size Document Number

Custom
KCM00
Date:

Rev
1.0

Tuesday, February 24, 2009

Sheet
1

37

of

10

+CPU_CORE

PR148
1_0402_5%~D

PR149 @ 0_0402_5%~D
1
2
PC135
1
2
ISEN1
VCC_PRM

PC139
10U_1206_25V6M~D

1
2

PC138
10U_1206_25V6M~D

PL11

+CPU_B+

0.36UH_PCMC104T-R36MN1R17_30A_20%

2
+5VS

VSUM

PR159
1_0402_5%~D

PR160 @ 0_0402_5%~D
1
2

PC144
680P_0603_50V8J~D

PR158
10K_0402_1%~D
2
1

G
S
S
S

PQ36

4
3
2
1

G
S
S
S

PQ35

PR155
4.7_1206_5%~D
PR157

2.2_0603_5%~D
0.22U_0603_10V7K~D

29.1
ISEN1
ISEN2
2

2200P_0402_50V7K~D
PC174

PC122
100U_25V_M~D

PC121
100U_25V_M~D

PR147
10K_0402_1%~D
2
1

3.65K_1206_1%

PR146
2

4.7_1206_5%~D
680P_0603_50V8J~D

PR145
PC134
2
1 2

UGATE_CPU2
PR154
PC141
BOOT_CPU2
1
2
1
2

PR161 1_0603_5%~D
PC146
1U_0603_10V6K~D

PC147
1
2
B

0.22U_0603_16V7K~D

SI4430BDY_SO8

SI4430BDY_SO8
VCC_PRM
ISEN2

PR165

+CPU_B+

PC150 10_0603_5%~D

Fsw=300kHz

1K_0402_1%~D

0.1U_0603_25V7K~D

PC151 0.022U_0603_25V7K
1
2

2
2

11K_0402_1%~D

PR170

1
2
PR168 0_0402_5%~D
PC154 180P_0402_50V8J~D
1
2

VSSSENSE

2.61K_0402_1%~D

VSUM
PC153
0.022U_0603_25V7K

PC152
@0.022U_0603_25V7K

PR169

PH2

PR171 1K_0402_1%~D PR172 3.57K_0402_1%~D

10KB_0603_ERTJ1VR103J
PC155 0.068U_0603_50V7K~N
1
2
PC156
0.22U_0603_16V7K~D

PC157 0.22U_0603_10V7K~D
2
1

Compal Secret Data

Security Classification
2007/1/15

Issued Date

Deciphered Date

2008/1/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PC130
10U_1206_25V6M~D
2
1

PC129
10U_1206_25V6M~D
2
1

5
3
2
1
5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1

4
3
2
1

PHASE_CPU2

4
3
2
1

ISEN1
24

ISEN2

VDD

PQ34
SI7686DP_POWERPAK

PU10

25

0.36UH_PCMC104T-R36MN1R17_30A_20%

0.22U_0603_16V7K~D

3.65K_1206_1%

NC

23

1VDD_CPU 22

GND
21

VIN
20

VSUM

VO
18

DROOP

DFB
17

19

Vin_CPU

VD IFF

16

FB2

DFB

12

VSUM

PC137
10U_1206_25V6M~D
2
1

26

BOOT2

LGATE_CPU2

1 2

UGATE2

27

FB

B+

3
2
1

29
28

PVCC_CPU

D
D
D
D

PGND2
PHASE2

SI4430BDY_SO8

5
6
7
8

VW

PQ33

D
D
D
D

OCSET

COMP

LGATE_CPU1

5
6
7
8

VW

G
S
S
S

D
D
D
D

OCSET

10

PC128
10U_1206_25V6M~D
2
1

1
1

PC127
1U_0603_10V6K~D

0.01U_0402_25V7K~D

PC126
2
1

PC125
1U_0603_10V6K~D
2
1

PC124
0.01U_0402_25V7K~D
2
1

30

ISL6262ACRZ-T_QFN48_7X7

2200P_0402_50V7K~D
2
1
PC175

37
VID0

31

LGATE2

PR163
1K_0402_1%~D

VCC_PRM

5
CPU_VID2
5
CPU_VID1
5
CPU_VID0
5

PVCC

SOFT

38

NTC

FB_CPU 11

2
5

VID1

SOFT

FB2_CPU

0_0402_5%~D

VID2

39

40
VID3

41

NTC

PC149 1000P_0402_50V7K~D
2
1
2
255_0402_1%~D
1
2

PR167

VID4

42
VID5

43
VID6

45

44
VR_ON

DPRSLPVR

46

CLK_EN#

DPRSTP#

32

VCCSENSE

48

LGATE1

PR166
5

47

49

VR_TT#

220P_0402_50V7K~D

PR164
1

3V3

GND

33

150K_0402_1%~D

PR190

1
PC148

PHASE_CPU1

34

PR162 97.6K_0402_1%~D PC145 470P_0402_50V7K~D

1
2
2
1

UGATE_CPU1

PGND1

PC143 1000P_0402_50V7K~D

35

PHASE1

DROOP

UGATE1

RBIAS

COMP

PC142
1
2
1000P_0402_50V7K~D
PR156 6.81K_0402_1%~D
1
2

PC132
2 1
2

PQ32
SI4430BDY_SO8

36

PMON

RTN

PR153 11.5K_0402_1%~D
1
2

BOOT1

VSEN

@ 100K_0603_1%_TH11-4H104FT
1
2
@ 0.015U_0402_16V7K
PC136
0.068U_0603_50V7K~N PC140
1
2

PL10
PR144
BOOT_CPU1

RBIAS

PH1

2 1

PSI#

15

PR151 147K_0402_1%~D
1
2

RTN

PR152

10K_0402_1%~D
2 PMON

14

VR_TT#
@ 4.22K_0402_1%
1

PR150
2
1

VSEN_CPU

PC133
1

1U_0603_10V6K~D

PGOOD

PQ31
SI7686DP_POWERPAK

5
6
7
8

H_PSI#
POW_MON

VDIFF

VGATE

PL9
FBMJ4516HS720NT_1806~D
1
2
@

2.2_0603_5%~D 0.22U_0603_10V7K~D

13

2
1
14,28

1
PR143

PR142

499_0402_1%~D

1.91K_0402_1%~D
PC131
1U_0603_10V6K~D

+3VS

0_0402_5%~D
2
3V3_CPU

PR134
1

+3VS

0_0402_5%~D
2
CLK_EN#_CPU

PR132
1

CLK_EN#

0_0402_5%~D
2

VID6
2
1
PR1350_0402_5%~D
VID5
2
1
PR1360_0402_5%~D
VID4
2
1
PR1370_0402_5%~D
VID3
2
1
PR1380_0402_5%~D
VID2
2
1
PR1390_0402_5%~D
VID1
2
1
PR1400_0402_5%~D
VID0
2
1
PR1410_0402_5%~D

PR131
1

5,7 H_DPRSTP#

+CPU_B+

PR129
1_0603_5%~D

499_0402_1%~D
2

DPRSLPVR_CPU
PR133
VR_ON_CPU
0_0402_5%~D
2
1

PR130
14 DPRSLPVR

14,28
CPU_VID3

5600P_0402_25V7K

DPRSTP#_CPU

CPU_VID4

CPU_VID5

VR_ON

PC120

CPU_VID6

+5VS

Title

Compal Electronics, Inc.

+CPU_CORE

Size Document Number

Custom

Rev
1.0

KCM00

Date:

Tuesday, February 24, 2009

Sheet
1

38

of

10

1 . B AT +
2 . B AT +
3.ID
4 .B/I
5. TS
6.SMD
7.S MC
8.GND
9.GND

1
2
3
4
5
6
7
8
9

PD14
DA204U_SOT323~D

3
1

1
3cell/4cell#

2 BATT_TEMP

BATT_TEMP 28

PR174
1K_0402_5%~D

PC162
0.1U_0402_16V7K~D
@

BATT_SMC

GND
GND

9
8
7
6
5
4
3
2
1

Place clsoe to EC pin

1

200275MR009G10PZR_9P-T
11
10

Battery Connect/OTP

2
PR173
47K_0402_5%~D

BATT_SMD

1
2

PC159
1000P_0402_50V7K~D

BATT_B/I

SMART
Batte ry:

+3VALWP

PC161
100P_0402_50V8J~D

1
PC160
0.01U_0402_25V7K~D

1
2

1
2

PC158
100P_0402_50V8J~D

BATT+

@
PL12
FBMA-L18-453215-900LMA90T_1812~D
BATT++
1
2

PJPB1 battery connector

3
1

BATT++

PD13
DA204U_SOT323~D

BATT+

PD12
DA204U_SOT323~D

PD11
DA204U_SOT323~D

+3VALWP

PR175
1K_0402_5%~D
2
1

3cell/4cell# 33

+3VALWP

PR176
6.49K_0402_1%~D
C

PJP22

EC_SMB_DA1 28

PR177
100_0402_5%~D

CPU
1

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

EC_SMB_CK1 28

PR178
100_0402_5%~D

VL

VS

BATT+

PR183
205K_0402_1%~D
1

8
+

PD15

OTP_OUT 1

MAINPWON 34

S DIO 1SS355
PU11A
LM358ADR_SO8

1
2

PR188
150K_0402_1%~D

OTP_IN-

PR186
150K_0402_1%~D
PH3
100K_0603_1%_TH11-4H104FT

1
PC165
1000P_0402_50V7K~D

PR187
86.6K_0402_1%~D

OTP_IN+
2

VL

PU11B

PR184
61.9K_0402_1%~D
1
2

LM358ADR_SO8
BATT_IN
5
1

VL
PR181
147K_0402_1%~D
1
2

1
2
8
P

BATT_OVP

28

BATT_OUT7

PC163
0.1U_0603_25V7K~D

PR180
10.7K_0402_1%~D

PR182
499K_0402_1%~D

PR185
10K_0402_1%~D
1
2

PC164
0.01U_0402_25V7K~D

CPU

VS

PR179
453K_0402_1%~D

PC166
1U_0603_10V6K~D

LI-3S :12.6V----BATT-OVP=1.1V
LI-4S :16.8V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+
A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/10/1

2007/05/30

Deciphered Date

BATTERY CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size Document Number

Custom
KCM00
Date:

Rev
1.0

Tuesday, February 24, 2009

Sheet
1

39

of

10

Version Change List ( P. I. R. List )

Item Page#
D

Title

Date

Request
Owner

Page 1/1

Issue Description

Solution Description

p37

+0.75VSP/1.8VSP

08/10/15

compal

source shortage

pu9

p33

charger

08/10/15

compal

design change

PQ6 PQ8

p32

DCIN / Precharge

08/10/15

compal

meet PSL

PQ2

p33

charger

08/10/15

compal

meet PSL

PQ16

p32

DCIN / Precharge

08/10/15

compal

meet PSL

PQ1

p33

charger

08/10/15

compal

meet PSL

PQ12

p34

+3VALWP/+5VALWP

08/10/15

compal

meet PSL

PQ21

p33

charger

08/10/15

compal

meet PSL

PR22 PR29

p37

+0.75VSP/1.8VSP

08/10/15

compal

adjust 1.8V output voltage

PR127 PR124

10

p33

charger

08/10/15

compal

adjust charge current to 3.1A

PR38

11

p33

charger

08/10/15

compal

adjust CP set for ICPP function

PR38

12

p34

+3VALWP/+5VALWP

08/10/15

compal

meet choke component current limit

PL4 PL5

13

p32

DCIN / Precharge

08/10/15

compal

meet PSL

PL1

14

p38

CPU_CORE

08/10/15

compal

meet PSL

PL9

15

p39

BATTERY CONN

08/10/15

compal

meet PSL

PL12

16

p33

charger

08/10/22

compal

design change

PQ6 PQ8

17

p35

+1.5VSP

08/10/22

compal

reduce L/S MOS Vds

PQ22

18

p36

+1.05VALWP/1.0VP

08/10/22

compal

Add remote sense function

PR189

19

p36

+1.05VALWP/1.0VP

08/10/22

compal

adjust output voltage

pr94

20

p36

+1.05VALWP/1.0VP

08/10/22

compal

design change

PL8

21

p35

+1.5VSP

08/10/22

compal

design change

PL6

22

p33

charger

08/10/22

compal

EMI request

PL13

23

ALL

every power

08/10/22

compal

reduce output ripple

PC123 PC167 PC168 PC169 PC170

24

ALL

every power

08/10/22

compal

sunbber for EMI request

PR30 PR106 PR55 PR56 PR80 PR110 PR105 PR155

Rev.
D

25

ALL

every power

08/10/22

compal

sunbber for EMI request

PC33 PC58 PC60 PC74 PC97 PC101 PC134 PC144

26

P34 P35

every power

08/10/22

compal

increase boost resistor value form 0 ohm to 2.2 ohm for EMI request

PR57 PR58 Pr76

27

p39

BATTERY CONN

08/12/03

compal

adjust OTP set

PR183

28

p33

charger

08/12/03

compal

DFX request

PQ10 PQ11 PQ13 PQ14 PQ15

29

p36

+1.05VALWP/1.0VP

08/12/03

compal

adjust +1.0VSP OCP set

PR102 PR107

30

p36

+1.05VALWP/1.0VP

08/12/03

compal

adjust +1.0VSP output voltage

PR99

31

p35

+1.5VSP

08/12/12

compal

design change(already trail run in PT phase)

PQ22

32

p39

BATTERY CONN

08/12/12

compal

adjust OTP set

PR183

33

p33

charger

08/12/31

compal

reduce AC-IN inrush current

PR24 PR25

34

p36

+1.05VALWP/1.0VP

08/12/31

compal

WWAN issue

PC173 PC174 PC175

34

p34

+3VALWP/+5VALWP

08/12/31

compal

adjust +5VALWP voltage

PR62 change frome 10k to 9.62k

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/1/15

Issued Date

2008/1/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PW PIR-1
Size Document Number
Custom
KCM00
Date:

Rev
1.0
Sheet

Tuesday, February 24, 2009

1

40

of

10

Braxton Power block

Battery OVP

CPU OTP

Page 39

Turn Off
Input
Switch Page 32

DC IN

Page 39

Turn Off
B+
+3VALWP: TDC:8.5A OCP:11A OVP:108%~114%
+5VALWP: TDC:7.5A OCP:9.8A OVP:108%~114%
(ISL6237)
Page 34

CHARGER
CC:0A~3A
CV:16.8V(4cell)
CV:12.6V(3cell)
(BQ24751) Page 33

+3VALW

+1.8VSP TDC:0.24A
(RT9025-25PSP)
Page 37

+1.5VP: TDC:13A OCP:16.9A OVP:113%~119%

(ISL6269A)

Battery

Always

SUSP#

+1.5VP:SYSON

Page 35

+1.5VP
CPU CORE
OCP:54A
OVP:2V
(ISL6262A)
VR_ON

+0.75VSP TDC:1.5A
(RT9026MSOP)
Page 37

SUSP#

Page 38

+1.05VALWP:TDC:7A OCP:9.1A OVP:113%~119%

+1.0VSP(0.75V~1.05V):TDC:9.3A OCP:12.1A OVP:113%~119%
(ISL6268)
Page 36

SUSP#
SUSP#

Title
<Title>
Size
Document Number
Custom<Doc>
Date:
A

Tuesday, February 24, 2009

Rev
1.0
Sheet

41

of

10

Version Change List ( P. I. R. List )

Item Page#
D

Title

Date

Request
Owner

Page 1/1

Issue Description

Solution Description

Rev.

19

P19-DDR3_SO-DIMM SLOT

2008/09/22 nVidia

can't use SO-DIMM

change SO-DIMM SA0 to pull high & SA1 to pull down

0.2

20

P20-LCD/SATA HDD

2008/09/25 Compal

can't read EDID for Panel

change JLVDS1 Pin 37 from +LCDVDD TO +3VS

0.2

21

P21-HDMI/Display Port

2008/10/07 Compal

Change DP122 to DP122A

12

P12-MCP79(6/10)_PCI/LPC 2008/10/13 Compal

28

P28-EC_KB926/BIOS/Reed SW2008/10/20 Compal

change R440 from 4.64K to 5.11K and R438 from 5.11K to 6.49K

can't select on board SPD data

0.2

ADD R191,R192,R193 TO SELECT ON BOARD MEMORY VENDOR

0.2

Change EC_SMB_DA1 and EC_SMB_CK1 from +5VALW to +3VALW

0.2

18

P18-1GB/2GB_DDR3_On Board2008/12/04 nVidia

On board Ram unstable

Add 0.1uF cap between Termination Resistor and +0.75VS

0.4

14

P14-MCP79(8/10)_HDA/MISC 2009/02/03 Dell

saving power consumption

change +3VALW to +3VS on MEM_SMBCLK & MEM_SMBDATA

1.0

24

P24-Mini Card_WLAN/WWAN

reserve SMBus from MCP79

1.0

2009/02/04 Dell

9
10
11
12
C

13
14
15
16
17
18
19
20
21
22

23
24
25
26
27
28
29
30
31
32

2009/02/19

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

EE PIR-1
Size Document Number
Custom LA-4631P
Date:

Rev
1.0
Sheet

Thursday, February 19, 2009

1

42

of

42