Digital Sweep Generator

The digital sweep generator is based on the Dig_TX board. The DSP and its memory, as well as the audio- and RF-ADCs remain unassembled. Signal synthesis is completely performed within the FPGA. A miniMAX-40 module with a little hand-made logic on a prototype board controls the sweep generator. The FPGA master clock frequency is 80 MHz. A seventh order reconstruction filter is implemented at the RF-DAC output. With a 40 MHz Nyquist frequency, the bandwidth design target for the sweep generator was 100 kHz ~ 30 MHz. The lower frequency is limited by a transformer between the DAC and the LP filter, while the upper frequency is limited by the filter roll-off. The maximum usable frequency is that frequency below the Nyquist frequency (fn = fclk/2; fclk=master clock frequency), at which the alias frequency fa = fclk-fo (fa=alias frequency, fo=desired output frequency) is still sufficiently attenuated. The term sufficiently is application dependent and means that the alias signal and its intermodulation products must not disturb the desired signal. Generally it is a good idea to attenuate the alias signal to below the required signal-to-noise ratio of the DDS signal generator. For the digital sweep generator, which shall be used for measurement applications, a minimum SNR of 60 dB seems adequate. While that is not extremely good if compared to commercially available sweep generators, it is sufficient for amateur measurements. In most cases, the SNR is actually better than 70 dB. In order to keep the passband ripple flat, so that a wide frequency range can be covered without introducing artifical ripple due to the anti-aliasing filter response, a seventh order Butterworth lowpass filter was initially considered and implemented. Its attenuation at 30 MHz was below 1 dB, but the attenuation at the alias of 50 MHz was less than 30 dB. The filter has been designed for 50 input and output impedance. The following table shows the calculated and the really selected capacitances and inductivities. Also the number of windings on an Epcos (Siemens) double hole core type B62152 A8X17 (AL=9nH/W 2) for the inductivities are listed. Fractions are estimated values. Seventh order Butterworth filter (-1dB at 30 MHz; -30dB at 58 MHz) component L1 L2 L3 C50 C51 C52 C53 Simulation results with real values: ideal value 300 nH 482 nH 300 nH 43 pF 174 pF 174 pF 43 pF real values 297 nH 410 nH 297 nH 44 pF 165 pF 165 pF 44 pF turns 5 3/4 6 3/4 5 3/4 -

AC Analysis Aplac 7.62 Student version FOR NON-COMMERCIAL USE ONLY 5.00 Mag -15.00

-35.00

-55.00

-75.00 10.0M MagdB(Vac(Outp

30.0M f/Hz

100.0M

It turned out, that the attenuation of the alias frequency was not satisfactory. Either a higher order Butterworth filter or a change of the filter topology to a much steeper Chebychev filter of the same seventh order was required. A higher order Butterworth filter will be considered for a future redesign, but for the existing board, it was more convenient to implement a Chebychev filter. The goal was to find a compromise between the passband ripple and a steep filter transition. The following table shows the calculated and the really chosen values for a 7th order Chebychev filter with 0.5 dB passband ripple up to 30 MHz and almost 60 dB attenuation at 50 MHz. Seventh order Chebychev filter (-0.5 dB at 30 MHz; -60 dB at 50 MHz) component ideal value real values 350 nH 375 nH 350 nH 183 pF (150//33) 288 pF (220//68) 288 pF (220//68) 183 pF (150//33) turns 7 7 1/4 7 -

L1 334 nH L2 357 nH L3 334 nH C50 184 pF C51 280 pF C52 280 pF C53 184 pF (real value means calculated, not measured!) Simulation results with real values:

AC Analysis Aplac 7.62 Student version FOR NON-COMMERCIAL USE ONLY 5.00 Mag -15.00

-35.00

-55.00

-75.00 10.0M MagdB(Vac(Outp

30.0M f/Hz

100.0M

Due to the unprecise realisation with the real values, the attenuation of 0.5 dB is already reached at about 29 MHz. The following diagram shows the passband ripple of the Chebychev filter.

AC Analysis Aplac 7.62 Student version FOR NON-COMMERCIAL USE ONLY 1.00 Mag 0.50 0.00 -0.50 -1.00 1.0M MagdB(Vac(Outp 3.0M f/Hz 10.0M 30.0M

miniMAX-40 LCA Pinout Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Description DOUT-I/O CCLK VCC GND A0--I/O A1-CS2-I/O I/O A2-I/O A3-I/O I/O I/O A15-I/O A4-I/O A14-I/O A5-I/O GND A13-I/O A6-I/O A12-I/O A7-I/O I/O I/O A11-I/O A8-I/O A10-I/O A9-I/O VCC GND TCLKIN-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O XC 3020 XC 3030 XC 3042 Signal DOUT CCLK VCC GND NIOWR CSLCA NIORD Taster U/D (In) Taster L/R (In) Drehgeber B (In) A15 IO24 A14 IO23 GND A13 SER_SPARE A12 SERADR (Out) BS0 SERDATA (Out) A11 SERCLK (Out) A10 -5V clock (Out) VCC GND VCC CLKOUT IO16 IO13 IO14 LCD_E (Out) IO12 LCD_RS (Out) LCD_R/W (Out) LCD_DB6 (I/O) LCD_DB7 (I/O) LCD_DB4 (I/O) VCC LCD_DB5 (I/O) LCD_DB2 (I/O) LCD_DB3 (I/O) LCD_DB0 (I/O) connector J1-59 J1-61 J1-1 63,64 J2-32 J2-31 J1-44 J1-43 J1-41 J2-18 J1-40 J2-17 J1-39 63,64 J2-16 J1-38 J2-15 J1-37 J2-52 J1-36 J2-14 J1-35 J2-13 J1-33 J1-1 63,64 J1-1 J2-47 J1-32 J1-29 J1-30 J1-27 J1-28 J1-25 J1-26 J1-23 J1-24 J1-21 J1-1 J1-22 J1-19 J1-20 J1-17

I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 M152 GND 53 M0-RT 54 VCC 55 M2-I/O 56 HDC-I/O 57 I/O 58 -I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 -I/O 65 GND 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 XTAL2-I/O 76 GND 77 78 VCC 79 DONE80 D7-I/O 81 82 BCLKIN-XTAL1I/O D6-I/O 83 I/O 84 I/O 85 I/O 86 D5-I/O 87 -I/O 88 D4-I/O 89 I/O 90 VCC 91 D3-I/O 92 -I/O 93

NMRD NMWR SELECT LCD_DB1 (I/O) TOUT1 STDP GND GND VCC VCC VCC IO15 LCD Backlight PWM (Out) SSN A16PS0 A17PS1 A18PS2 A19PS3 Drehgeber A (In) NINIT GND HLDAK HLDRQ INTP3 INTP2 INTP1 DMARQ0 NDMAAK0 DMARQ1 NDMAAK1 D6 (Wobbel-PA) GND NRESET VCC DONEPG AD7 BCLKIN AD6 D12 (Wobbel-PA) D24 (Wobbel-PA) ASTB AD5 A8 AD4 BUFRW VCC AD3 A9

J2-29 J2-30 J1-58 J1-18 J2-48 63,64 63,64 J1-1 J1-1 J1-1 J1-31 J1-34 J1-42 63,64 J2-46 J2-45 J2-58 J2-57 J2-56 J2-36 J2-37 J2-38 J2-39 J1-45 63,64 J1-57 J1-1 J1-62 J2-10 J1-56 J2-9 J1-46 J1-47 J2-28 J2-8 J2-11 J2-7 J2-34 J1-1 J2-6 J2-12

94 95 96 97 98 99 100

D2-I/O I/O I/O I/O D1-I/O -/RDY-I/O D0-DIN-I/O

AD2 D48 (Wobbel-PA) BS1 BS2 AD1 NBUSY AD0

J2-5 J1-48 J2-53 J2-54 J2-4 J2-3

Folgende Register sind im XC3030 FPGA auf dem MiniMax-40 Board definiert und an der jeweils angegebenen I/O-Adresse vom V40HL aus ansprechbar:

0x7000
7 LCD_DB7 R/W 6 LCD_DB6 R/W 5 LCD_DB5 R/W

LCD Data Register

4 LCD_DB4 R/W 3 LCD_DB3 R/W 2 LCD_DB2 R/W 1 LCD_DB1 R/W 0 LCD_DB0 R/W

Data to be written to or read from LCD. The direction is switched by LCD Data Direction Register.

0x7001
7 6 5 -

LCD Control Register

4 3 2 E W 1 R/W W 0 RS W

LCD control signals.

0x7002
7 6 5 -

LCD Backlight
4 3 B3 W 2 B2 W 1 B1 W 0 B0 W

Brightness of LCD backlight. B[3..0] = 0000: Backlight off; B[3..0] = 1111: Backlight max

0x7003
7 6 5 -

Keyboard Input
4 3 Taste U/D R 2 Taste L/R R 1 0 Drehgbr B Drehgbr A R R

Inputs the logical levels of the keys on the front panel. An interrupt is generated when these values change.

0x7004
7 6 5 -

LCD Data Direction Register

4 3 2 1 0 DIR W

DIR=0: LCD port is input; DIR=1: LCD port is output;

0x7005
7 SD7 W 6 SD6 W 5 SD5 W

Serial Output Buffer

4 SD4 W 3 SD3 W 2 SD2 W 1 SD1 W 0 SD0 W

Data to be sent via serial port

0x7006
7 TXBE R 6 -

Serial Control/Status Register

5 4 3 2 1 SPARE R/W 0 SERADR R/W

Data may be written to the serial output buffer, when TXBE is high. SERADR outputs the serial address. The receiver latches the data when SERADR changes its level. SPARE is currently unused.

0x7007
7 6 5 4 -

Port4
3 D48 W 2 D24 W 1 D12 W 0 D6 W

Port4 controls the attenuation of the resistor ladder inside the PA. This ladder consists of four resistor stages with 6, 12, 24 and 48dB attenuation. The attenuation is inserted by a relay, when the respective bit in the Port4 output register is set.

WOBBELTX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TCK CONF_DONE nCEO TDO VCCINT 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 GNDINT DSPCLK 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 DAC_D0 GNDINT DAC_D1 DAC_D2 DAC_D3 DAC_D4 DAC_D5 DAC_D6 DAC_D7 VCCINT DAC_D8 DAC_D9 DAC_D10 DAC_D11 DAC_D12 DAC_D13 DAC_CLK GNDINT P2 P3 VCCINT IN, RESETB 91 CLK, CLK_SPX 92 IN 93 GNDINT 94 95 96 VCCINT 97 98 99 100 101 102 103 104 GNDINT 105 106 ADC_CLK 107 108 ADC_D11 109 ADC_D10 110 ADC_D9 111 ADC_D8 112 VCCINT 113 ADC_D7 114 ADC_D6 115 ADC_D5 116 ADC_D4 117 ADC_D3 118 ADC_D2 119 ADC_D1 120 ADC_D0

VCCINT

GNDINT CLKUSR

GNDINT

VCCINT WAITB BSTBB RDB WRB GNDINT RDYnBSY

INIT_DONE VCCINT

SERCLK VCCINT SERDATA SERADR SER_SPARE GPIO11 GNDINT GPIO10 Trigger out Marker out GPIO7 VCCINT TMS TRST nSTATUS

WOBBELTX
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 nCONFIG VCCINT MSEL1 MSEL0 GNDINT 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 D4 D5 D6 D7 GNDINT D8 D9 D10 D11 VCCINT D12 D13 D14 D15 GNDINT 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 VCCINT DATA7 SPARE3 SPARE2 SPARE1 AA15 AA14 AA13 GNDINT A0 A1 A2 A3 A4 A5 A6 VCCINT A7 A8 A9 DEV_CLRn IN, P0 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 CLK, CLK IN, P1 DEV_OE A10 A11 GNDINT A12 A13 A14

VCCINT

GNDINT AUDCLK FSY VCCINT SCK AIDATA GNDINT D0 D1 D2 D3 VCCINT

VCCINT INTB1 INTB2 INTB3 INTB4

VCCINT

GNDINT

GNDINT TDI nCE DCLK DATA0

nRS nWS CS nCS

Schematics

WOBBELTX

A[13..0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A14 RDB WRB WAITB BSTBB 25 24 23 22 19 18 17 16 15 14 13 12 9 8 47 46 45 44 41 40 39 38 35 34 33 32 29 28 27 26 7 98 95 100 99 93 94 R9 VCC33 DSP Boot mode 10K DSPCLK 85 84 C VCC33 R20 WAITB 10K R11 33K U3 2 4 1 PB1 CPU RESET VCC PFI MR RESET RESET PFO GND 8 7 5 3 33K RESETB R10 VCC33 VCC33 97 86 69 56 43 37 31 21 11 P0 P1 P2 P3 65 64 63 62

U1 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 X/Y MRD MWR WAIT BSTB HOLDRQ HOLDAK P0 P1 P2 P3 X1 X2 VDD VDD VDD VDD VDD VDD VDD VDD VDD UPD77019 P0 and P1 select the boot mode. GND GND GND GND GND GND GND GND GND 10 20 30 36 42 55 68 83 96 P3 PIN VCC33 P5 PIN C1 0.1uF C2 0.1uF C3 0.1uF C4 0.1uF C5 0.1uF C6 0.1uF C7 0.1uF C8 0.1uF C9 0.1uF C10 0.1uF P6 PIN P4 PIN TMS TDI TCK TICE TDO CLKOUT INT1 INT2 INT3 INT4 RESET HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HA0 HA1 HCS HRD HWR HRE HWE SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 SI2 SIEN2 SCK2 SO2 SOEN2 77 76 75 74 73 72 71 70 82 81 78 79 80 66 67 TCK3 48 49 50 51 52 53 54 61 60 59 58 57 92 91 90 89 88 87 5 4 3 2 1 TMS3 TDI3 TCK3 TICE TDO CLK_SPX INTB1 INTB2 INTB3 INTB4 RESETB U7C 74LVC14 U7D 74LVC14 U7E 74LVC14 U7F 74LVC14 C P1 CLK_SPX 1 4 6 5 8 1 4 9 10 1 4 11 12 1 4 13 VCC33 TDI3 1 4 1 TMS3 3 U6A 2 VCC33 J1 TMS TDI TCK 74LVC32 6 U6B 1 4 4 5 R17 4K7 R18 4K7 TICE TDO 1 2 3 4 5 6 7 8 9 10 CON2X5 74LVC32 8 U6C 1 4 9 10 R19 4K7 DSP debug WRB JTAG connector for debugging U7A 74LVC14 2 74LVC32 SELB_BOOT 11 U6D 1 4 12 13 4 1 4 1 4 3 U7B 74LVC14 P2 1 A14 WAITB BSTBB INTB[4..1] SPARE[3..1] RESETB A[14..0] D[15..0] AA[15..13] P[3..0] CLK_SPX DSPCLK RDB FPGA A[14..0] D[15..0] AA[15..13] P[3..0] CLK_SPX DSPCLK RDB WRB WAITB BSTBB INTB[4..1] SPARE[3..1] RESETB FPGA.SCH DAC_D[13..0] DAC_CLK ADC_D[11..0] ADC_CLK DAC_D[13..0] DAC_CLK ADC_D[11..0] ADC_CLK D

74LVC32

VCC33 D 8 x 10K VCC33 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 AA13 AA14 AA15 1 1 1 1 1 1 1 S1 6 5 4 3 2 1 0 9 VCC33 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 41 43 U2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 WE CE OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC GND GND 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 44 12 34

Set Boot Mode

P0 P1 SPARE1 SPARE2 SPARE3

SELB_BOOT 3 22 RDB

AT29LV1024J BOOT ROM 1 2 3 4 5 6 7 8

MAX708T 200ms delay P2 indicates that DSP loads program from Boot ROM. P2 must be reset to 0V by software in order to indicate that the boot sequence has finished. VCC50 C21 0.1uF PIN P7 AVDD C22 0.1uF C23 0.1uF AVDD C20 0.1uF

CON1 +5V GND 2 1 Power B Place this text close to connector at the respective pin.

VCC50 F1 TR5-1.25AT C48 D3 ZY5.6 C46 0.1uF 470uF10 C47

U17 LT1117CST-3.3 3 2 I O 4 O G 1

2 x 10:10 Wdg auf Doppellochkern A7-X1 (AL=140nH) VCC33 R16 T3 270 C49 8 100uFT4 ADC_CLK 100 0.1uF DL-4 R15 C17 T2 3 4 9 DL-1 10 5 6 13 14 17 18 21 22 24 34 35 38 39 U5 7 AIN AIN D0 D1 D2 D3 D4 ENCODE D5 D6 ENCODE D7 D8 VREF D9 D10 C1 D11 GND GND GND GND GND GND GND GND GND GND GND GND GND AD6640 Grenzfrequenz: 36 MHz Note: R13 and R14 are usually not populated. C50 und C53: je 2x22pF parallel C51 und C52: je 2x330pF in Serie AVCC AVCC AVCC AVCC AVCC AVCC DVCC DVCC DVCC DVCC DVCC DVCC 25 26 27 28 29 30 31 32 33 42 43 44 11 12 15 16 19 20 1 2 36 37 40 41 ADC_D0 ADC_D1 ADC_D2 ADC_D3 ADC_D4 ADC_D5 ADC_D6 ADC_D7 ADC_D8 ADC_D9 ADC_D10 ADC_D11 AVDD

10uFT6.3

VCC50

VCC33 VCC50 C19

DR1

AVDD C18 L1~L3 auf Doppellochkern A8-X17 (AL=9nH) 5:5:10 Wdg auf Doppellochkern A7-X1 (AL=140nH) T1 JP1 JPCB2NC DL-CT-1 R14 51 5 3/4 Wdg L1 300nH C50 43p 6 3/4 Wdg L2 482nH C51 174p 5 3/4 Wdg L3 300nH C52 174p C53 0.1uF 43p 10nF 10nF C14 C15 C16

R41 430

R42 200

0.1uF

DR_CC_10

0.1uF

R13 D2 D1 U13 M3 U14 M3 U15 M3 U16 M3 DAC_D0 DAC_D1 DAC_D2 DAC_D3 DAC_D4 DAC_D5 DAC_D6 DAC_D7 DAC_D8 DAC_D9 DAC_D10 DAC_D11 DAC_D12 DAC_D13 DAC_CLK A 14 13 12 11 10 9 8 7 6 5 4 3 2 1 28 26 20 U4 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 CLOCK DCOM ACOM AD9764 IOUTA IOUTB FSADJ COMP1 COMP2 REFIO SLEEP AVDD DVDD REFLO 22 21 18 19 23 17 15 24 27 16 C13 0.1uF R12 2K 51

VCC33

1 5V 3.3V

C11 0.1uF

C12 0.1uF AVDD VCC50

Michael Kraemer Michael Kraemer Edenkobener Weg 24 D404229 Duesseldorf Germany Title Digital Transmitter Size A2 Date: 8 7 6 5 4 3 2 Document Number DIG_TX.SCH January 1, 2002 Sheet 1 1 of REV 1 2

A[14..0] D[15..0]

A[14..0] U12 D[15..0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RDB WRB BSTBB WAITB P2 U8 INTB1 INTB2 INTB3 INTB4 3 CLK_SPX DSPCLK 198 199 200 201 202 203 204 206 207 208 214 215 217 218 219 146 147 148 149 151 152 153 154 156 157 158 159 161 162 163 164 19 20 18 17 225 226 227 228 91 33 211 RESETB VCC33 R37 10K R34 1K R35 1K R36 1K RESETB 90 3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RDB WRB BSTBB WAITB INTB1 INTB2 INTB3 INTB4 CLK_SPX DSPCLK CLK RESETB CEO DAC_D0 DAC_D1 DAC_D2 DAC_D3 DAC_D4 DAC_D5 DAC_D6 DAC_D7 DAC_D8 DAC_D9 DAC_D10 DAC_D11 DAC_D12 DAC_D13 DAC_CLK ADC_D0 ADC_D1 ADC_D2 ADC_D3 ADC_D4 ADC_D5 ADC_D6 ADC_D7 ADC_D8 ADC_D9 ADC_D10 ADC_D11 ADC_CLK AA13 AA14 AA15 P0 P1 P2 P3 SPARE1 SPARE2 SPARE3 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 AIDATA SCK FSY AUDCLK TDI TCK TMS TDO TRST 68 70 71 72 73 74 75 76 78 79 80 81 82 83 84 120 119 118 117 116 115 114 113 111 110 109 108 106 196 195 194 210 212 87 88 193 192 191 67 66 65 64 63 62 61 56 55 54 53 51 50 49 48 46 143 142 138 137 177 1 58 4 59 AIDATA SCK FSY AUDCLK VCC33 DAC_D0 DAC_D1 DAC_D2 DAC_D3 DAC_D4 DAC_D5 DAC_D6 DAC_D7 DAC_D8 DAC_D9 DAC_D10 DAC_D11 DAC_D12 DAC_D13 DAC_CLK ADC_D0 ADC_D1 ADC_D2 ADC_D3 ADC_D4 ADC_D5 ADC_D6 ADC_D7 ADC_D8 ADC_D9 ADC_D10 ADC_D11

DAC_D[13..0] ADC_D[11..0]

DAC_D[13..0] ADC_D[11..0]

VCC33 D C24 DAC_CLK 0.1uF C25 0.1uF C26 0.1uF C27 0.1uF C28 0.1uF

AA[15..13] ADC_CLK AA13 AA14 AA15 P0 P1 P2 P3 SPARE1 SPARE2 SPARE3 ADC_CLK P[3..0]

AA[15..13]

P[3..0]

INTB[4..1]

INTB[4..1]

SPARE[3..1] VCC50 J8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CON2X10

SPARE[3..1]

VCC50 C32 0.1uF C

4 1 2

VCC OE GND

OUT

80.000 MHz

VCC33 U11 27 23 17 3 15 12 VCC VPP VPPSEL VCCSEL CASC GND EPC2 DATA DCLK OE CS INITC TDI TDO TMS TCK 31 2 7 10 16 13 28 25 32 TDI TDO TMS TCK JP2 R38 R39 R40 3 x 10k 124 123 178 J7 2 4 6 8 10 VCC33 TCK TDO TMS TDI 1 3 5 7 9 2 4 6 8 10 VCC33 MSEL0 MSEL1 CE DIGTX10K100 VCC33 FDAT0 DCLK STATUSB DONE CONFIGB 180 179 60 2 121 DATA0 DCLK STATUS CONF_DONE CONFIG

J6 DCLK DONE CONFIGB STATUSB FDAT0 1 3 5 7 9

CON2X5 FLEX Download Cable

CON2X5 EPC2 Programming Cable

AVDD R25 R24 220

C36 100p R27 68K

R28 68K

C39 100p R30 39K

4 5 Mikrofon 1K2 R23 R22 1K8 10k 4 3 2 R21 C33 0.1uF 10k 1 1 LM837 U10A 1 R26 3K9 C44 4.7uFT10 6 LM837 1 1 U10B 7 C37 C38 0.1uF 0.1uF R31 27K 10 9 LM837 1 1 4K7 4.7uFT10 4 U10C 8 R29 C45 12 13

4 U10D 14 LM837 1 1 J5 Spare Analog in 150 R33 R32 150 C42 0.47uF AVDD U9 8 5 7 6 AINL SDATA AINR SCLK VA+ LRCK MCLK AGND CS5331A A 1 2 3 4 AIDATA SCK FSY AUDCLK

C35 10uFT10

C34 0.1uF

J4

C43 0.47uF

C40 10n

C41 10n

NEC Electronics (Europe) GmbH Michael Kraemer Oberrather Strasse 4 D40472 Duesseldorf Germany Title PILO Audio 1 Size A2 Date: Document Number PILOAUD1.SCH January 1, 2002 Sheet 1 2 of REV 1 2

Schematics

Wobbel-FPGA

MAX+plus II 9.3 File: TOP.GDF Date: 01/01/2002 13:52:53 Page: 1

OUTPUT OUTPUT

serial-in
SERDATA SERADDR SERCLK
INPUT INPUT INPUT

phase_accu
DATA[31..0] SFRQ SWING MARK1 MARK2 TPS SPC TDEL TTIME MTS DATA[31..0] DATA[31..0] SFRQ SWING MARK1 MARK2 TPS SPC TDEL TTIME MTS SRESETB SRESETSB CLK CLKS

Blank Trigger

SRESETSB CLKS AMPLITUDE

SERDATA SERADDR SERCLK SRESETSB CLKS AMPLITUDE

p_to_a
PHASE[27..0] BLANK TRIGGER CLK PHASE[27..0] CLK SIN[13..0] SIN_N[13..0] DPHASE[17..0] CLK CLKS SRESETSB SRESETB SIN[13..0] AMPL[13..0] SIN_N[13..0] DAC_CLK DPHASE[17..0] CLK CLKS SRESETSB DATA[31..0] SRESETB AMPLITUDE
OUTPUT OUTPUT

DAC_D[13..0] DAC_CLK

DATA[31..0] AMPLITUDE

SRESETB SRESETSB CLK CLKS

RESETB
AND2 NOT AND3

INPUT

VCC

SRESETB
DFF

DFF PRN

XOR Q

DFF PRN D Q

XOR

DFF PRN D Q

TFF PRN T Q

DFF PRN D Q

PRN D Q

FREQUENCY=80MHz

SRESETSB

CLK

INPUT

CLRN

CLRN

CLRN

CLRN

CLRN

CLRN

GLOBAL

CLKS Slow Clock (currently CLK/16)

MAX+plus II 9.3 File: SERIAL-IN.GDF Date: 01/01/2002 13:53:27 Page: 1

A[0] A[1] A[2] A[3] A[4] RXD

NOT NOT NOT NOT NOT

AND6

Adr=0: Start Frequency Register SFRQ

OUTPUT

SFRQ

LPM_SHIFTREG
SRESETSB SERDATA
INPUT INPUT

AND6

SRESETSB
1

sset shiftin q[] DATA[31..0]

OUTPUT

Adr=1: Swing Frequency Register SWING DATA[31..0]

OUTPUT

SWING

NOT

OR2

enable
AND6

Adr=2: Marker 1 Frequency Register MARK1

VCC VCC VCC AND2 DFF DFF PRN D Q D PRN Q NOT AND2 DFF PRN D Q AND6 INPUT INPUT OUTPUT

MARK1

SERCLK CLKS

Adr=3: Marker 2 Frequency Register Rising edge on SERCLK MARK2

OUTPUT

CLRN

CLRN

CLRN

MARK2

AND6

Adr=4: Amplitude Register

VCC VCC VCC

AMPLITUDE
AND2 DFF DFF PRN D Q D PRN Q NOT AND2 DFF PRN D Q INPUT

OUTPUT

AMPLITUDE

SERADDR

NOT

Rising edge on SERADDR

CLRN

AND6

CLRN

CLRN

Adr=5: Time Per Sample Register TPS

VCC AND2 AND2 DFF D PRN Q OUTPUT

TPS

RXD

AND6

Adr=6: Samples Per Cycle Register Falling edge on SERADDR SPC

OUTPUT

CLRN

SPC

AND6

LPM_DFF

Adr=7: Trigger Delay Register TDEL

OUTPUT

TDEL

DATA[7..0]
OR2 NOT

data[] enable

q[]

A[7..0]
AND6

Adr=8: Trigger Time Register SRESETSB

1

sclr

TTIME

OUTPUT

TTIME

AND6

Adr=9: Marker Time Register MTS

OUTPUT

MTS

MAX+plus II 9.3 File: PHASE_ACCU.GDF Date: 01/01/2002 13:53:59 Page: 1

Marker Time

LPM_FF
sset DATA[7..0] MTS
INPUT OR2

data[] q[] enable MT[7..0]

Time Per Sample

LPM_FF
sset DATA[7..0]
OR2

data[] q[] enable

VTPS[7..0]

TPS

INPUT

Marker 1 Samples Per Cycle

LPM_FF LPM_COMPARE
sset DATA[31..0]
INPUT VCC AND2

LPM_FF
sset DATA[11..0]
OR2

DATA[31..0] DATA[27..0] data[] q[] enable

CLRN CLRN OR2

data[] q[] enable VSPC[11..0]

MARK1

INPUT

MARK1

dataa[] datab[]

DFF

DFF PRN PRN Q D Q NOT

NOR2

ageb

SPC

INPUT

8count
MT[0] MT[1] MT[2] MT[3] MT[4] MT[5] MT[6] MT[7]
OR2

Trigger Delay

Marker 2

LPM_FF
sset DATA[7..0] TDEL
INPUT OR2

LPM_FF LPM_COMPARE
sset DATA[27..0] data[] q[] enable CLKTM
CLRN CLRN VCC AND2

data[] q[] enable VTDEL[7..0] MARK2

INPUT

MARK2

OR2

dataa[] datab[]

DFF

DFF PRN Q D PRN NOT Q

ageb

LDN A B C D E F G H GN DNUP

NOR8

QA QB QC QD QE QF QG QH

Trigger Time

LPM_FF
sset DATA[7..0]
OR2

Start Frequency

CLKS
VCC NOT

LPM_FF
sset VTTIME[7..0] SFRQ
INPUT

CLK UP/DN COUNTER

OR2 OUTPUT

data[] q[] enable

DATA[27..0] SFRQ
OR2

data[] q[] enable

ACTIVE

NOT

BLANK

TTIME

INPUT

CLKS

INPUT

Sweep Frequency

LPM_FF LPM_ADD_SUB
sset DATA[27..0]
OR2

SFREQ[27..0]
INPUT

CLK

LPM_FF BUSMUX
dataa[]
0

LPM_FF LPM_FF LPM_ADD_SUB

data[] q[] enable

dataa[] result[] datab[] SUM[27..0]

SWING

INPUT

result[] sel

data[] q[] enable sclr

data[] q[] data[] q[] dataa[] result[] datab[] RESULT[27..0]

LPM_FF

datab[]

data[] q[] sclr PHASE[27..0]

OUTPUT

PHASE[27..0]

SRESETSB

INPUT

NOT 1

ACTIVE SRESETB
NOT AND2 OR2 NOT AND2 AND2 NOT NOT OR4 INPUT

CLKSDIV

OUTPUT

Trigger

VCC

CLKSDIV CLKTM Freq. steps per cycle

OR2 OR8

ACTIVE
VCC

DTIME
VCC

STTIME

deadtime after cycle

8count
LDN A B C D E F QA QB QC QD QE QF

78.125 kHz
OR6

Triggertime

8count
VTPS[0] VTPS[1] VTPS[2] VTPS[3] VTPS[4] VTPS[5] VTPS[6] VTPS[7] LDN A B C D E F G H GN DNUP QA QB QC QD QE QF QG QH

8count
VSPC[0] VSPC[1] VSPC[2] VSPC[3] VSPC[4] VSPC[5] VSPC[6] VSPC[7]
OR2

8count
OR12

8count
OR8

DNUP
VCC

CLKTM

LDN A B C D E F G H GN DNUP

QA QB QC QD QE QF QG QH COUT
1

VTDEL[0] VTDEL[1] VTDEL[2] VTDEL[3] VTDEL[4] VTDEL[5] VTDEL[6] VTDEL[7]

OR3

CLKSDIV

LDN A B C D E F G H GN DNUP

QA QB QC QD QE QF QG QH

VTTIME[0] VTTIME[1] VTTIME[2] VTTIME[3] VTTIME[4] VTTIME[5] VTTIME[6] VTTIME[7]

OR3

CLKSDIV

LDN A B C D E F G H GN DNUP

OR8

QA QB QC QD QE QF QG QH

NOT

NOT

CLKS

CLK UP/DN COUNTER

CLK UP/DN COUNTER

CLK UP/DN COUNTER

CLK UP/DN COUNTER

n = 2 ~ 256 tD = n * 12.8 us tD = 25.4 ~ 3276.8 us

NOT

CLK UP/DN COUNTER

n = 2 ~ 256 tT = n * 12.8 us tT = 25.4 ~ 3276.8 us

All frequencies assume an 80 MHz master clock CLKS assumed to be CLK/16

Time per freq.-step n = 2 ~ 256 tM = n * 12.8 us tM = 25.4 ~ 3276.8 us

4count
VSPC[8] VSPC[9] VSPC[10] VSPC[11]
1

OR3

LDN A B C D CIN DNUP

QA QB QC QD

CLK COUNTER
VCC

s = 2 ~ 4096

MAX+plus II 9.3 File: P_TO_A.GDF Date: 01/01/2002 13:54:33 Page: 1

LPM_DFF

data[] CLK CLK

q[]

HW[12..0]
VCC WIRE

LPM_ADD_SUB LPM_CONSTANT
(cvalue) result[] dataa[] result[] datab[]

LPM_ADD_SUB LPM_CONSTANT BUSMUX

dataa[]
0

HW13

LPM_DFF BUSMUX
HW[13..0] dataa[]
0

(cvalue)

result[]

LPM_CONSTANT BUSMUX
(cvalue) result[] dataa[] result[] R13,HW[12..0] datab[]

result[] sel CLK

result[] IP[7..0] sel

1

LPM_ROM
address[] inclock outclock q[] ROM[12..0]

dataa[] datab[]

datab[]

data[]

q[]

SIN[13..0]

0 1

datab[]

result[] sel

CLK

WIRE

R13

PPHASE[25..18] CLK
DFF PRN Q D GND

PPHASE26 PPHASE25 PPHASE24 PPHASE23 PPHASE22 PPHASE21 PPHASE20 PPHASE19 PPHASE18

NOR8 VCC

OUTPUT

SIN[13..0]

PHASE[27..0] CLK

INPUT INPUT

PHASE[27..0] CLK
CLRN

NAND2

DFF PRN D Q

DFF PRN D Q

DFF PRN D Q

DFF

DFF PRN PRN Q D Q

DFF PRN D Q

DFF PRN D Q

LPM_DFF

PPHASE27 CLK

CLK
CLRN CLRN CLRN CLRN CLRN CLRN CLRN

PHASE[27..0] CLK

data[]

q[]

PPHASE[27..0] Previous phase

PPHASE[17..0]
OUTPUT

DPHASE[17..0]

LPM_ADD_SUB LPM_CONSTANT
(cvalue) result[] dataa[] result[] PHASE[27..18] datab[]

LPM_DFF

CLK

Delayed Phase (sync. to SIN)

data[]

q[]

PPHASEI[27..18]

LPM_DFF

Previous phase + 1 data[] CLK q[] HWN[12..0]

VCC

LPM_ADD_SUB LPM_CONSTANT
(cvalue) result[] dataa[] result[] PPHASEI[25..18] datab[]

CLK

WIRE

LPM_ADD_SUB LPM_CONSTANT BUSMUX

dataa[] datab[]
0 1

HWN13

LPM_DFF BUSMUX
HWN[13..0] dataa[]
0

(cvalue)

result[]

LPM_CONSTANT BUSMUX
(cvalue) result[] dataa[] result[] RN13,HWN[12..0] datab[]

result[] sel CLK

data[]

result[] IPN[7..0] sel

1

LPM_ROM
address[] inclock outclock q[]

dataa[]
0

datab[]

q[]

SIN_N[13..0]

result[] sel

CLK

ROMN[12..0] datab[]

1 WIRE

RN13

CLK
PRN Q

DFF D

GND

PPHASEI26 PPHASEI25 PPHASEI24 PPHASEI23 PPHASEI22 PPHASEI21 PPHASE20 PPHASEI19 PPHASEI18

NOR8 VCC

OUTPUT

SIN_N[13..0]

CLRN

NAND2

DFF PRN D Q

DFF PRN D Q

DFF PRN D Q

DFF

DFF PRN PRN Q D Q

DFF PRN D Q

DFF PRN D Q

PPHASEI27 CLK

CLRN

CLRN

CLRN

CLRN

CLRN

CLRN

CLRN

CLK

MAX+plus II 9.3 File: OUTPUT_STAGE.GDF Date: 01/01/2002 13:55:06 Page: 1

LPM_ADD_SUB

SIN_N[13..0]

dataa[] result[] DSIN[13..0]

SIN[13..0]

datab[]

LPM_DFF
SIN_N-SIN does never exceed 6 bits plus sign for a 14-bit wide and 1024 word sine DSIN[6..0] data[] q[] DEX[6..0]

LPM_MULT
clock dataa[] result[] datab[]
1 1

LPM_DFF

DELTA[13..0]

DELTA[12..6] CLK

data[]

q[]

DA[6..0]

LOW,O_DP[5..0]

LPM_ADD_SUB LPM_DFF

LPM_DFF

always positive DA6,DA6,DA6,DA6,DA6,DA6,DA6,DA[6..0] CLK carry propagation data[] CLK q[] dataa[] clock datab[]

DPHASE[17..12] CLK

data[]

q[]

O_DP[5..0]

result[]

ISIN[13..0]

1 1

LPM_DFF

LPM_DFF

LPM_DFF

LPM_DFF
VCC

DATA[31..0] SIN[13..0] data[] data[] data[] data[] SIN[13..0] DPHASE[17..0] SIN_N[13..0]

INPUT WIRE INPUT WIRE INPUT

HIGH

q[]

q[]

q[]

q[]

LOW

INPUT GND

LPM_FF
SRESETSB
INPUT

LPM_DFF LPM_MULT
q[] data[] q[] clock dataa[] result[] ISIN[13..0] datab[] RES[23..0] RES[23..10] data[] q[]
OUTPUT

SRESETSB DATA[9..0]
OR2

NOT

sset data[] enable

LPM_DFF

AMPLITUDE

INPUT

AMPL[13..0]

CLKS

INPUT

CLKS

interpolated sine SRESETB

INPUT

sclr
1

CLK

INPUT

CLK

NOT OUTPUT

DAC_CLK

Schematics

MiniMAX-FPGA

4 U86 VCC

U85 U87 U26 AD0 P100,FAST U10 OBUFZ DI0 D A0 A4 BS[0..2] CPUCLK U11 INLAT U31 DO1 AD5 P87,FAST U23 INLAT U30 DO0 AD4 P89,FAST U22 OBUFZ DI4 DECODER DO4 DI[0..7] DO[0..7] DI[0..7] DO[0..7] NDE A[0..15] NIORD NIOWR A[0..15] OBUF NIORD NIOWR BS[0..2] CPUCLK U69 U73 NDE NOD DO5 SELECT DECODER.SCH DI1 DI5 U71 U70 IPAD XCLK IBUF OPAD P99 NBUSY NBUSY

A8

U1 IBUF

U43 A8 P88 U44 A9 P93 U45 A10 P25 U46 A11 P23 U47 A12 P19 U48 A13 P17 U49 A14 P14 U50 A15 P12 U53 P8 NIORD U54 P5 NIOWR C D

A9

U2 IBUF

A10

U3 IBUF

A11

U4 IBUF

U27 AD1 P98,FAST

U12 OBUFZ

U24 OBUFZ

A12

U5 IBUF

A13 A1 A5 U66 U13 U25 IPAD CPUCLK DO6 U65 IPAD STDP IBUF A14 INLAT GCLK U84 A15

U6 IBUF

U7 IBUF

INLAT U32 DO2 AD6 P83,FAST

U28 C AD2 P94,FAST

U14 OBUFZ

U20 OBUFZ

U8 IBUF

DI2

DI6

INV

NIORD U51 IBUF U67 NIOWR U52 IBUF ACLK Detect HALT mode This logic will keep CE of the Flash EEPROM high during HALT mode in order to reduce the power consumption. U81

A2

A6

U15

INLAT U33 DO3 AD7 P81,FAST

U21

INLAT

U29 AD3 P92,FAST

U16 OBUFZ

U18 OBUFZ

DO7

U59 U57 BS0 INLAT C U72 ASTB P21 BS0 DI7

DI3

A3 B U17 INLAT U19 INLAT

A7 D FD U77 HALT AND3B1 U75 IDLE BS1 INLAT P96 BS1 Q U60 U58 B

PS0 U39 A16 P60 U35 INLAT A16 U41 A18 P62 U37 INLAT

PS2 NAND2B2 U78 U79 AND3 BS2 AND2 OR2 U80 U76 D Q U63 VCC U62 PS3 U42 INLAT U61

A18

U56 P97 BS2

PS1 U40 A17 P61 A U36 INLAT A17 F1 C

U64 A19 AND2 C U38 INLAT U55 U68 U83 Michael Kraemer Michael Kraemer Edenkobener Weg 24 D40229 Duesseldorf Germany Document Number November 29, 1999 2 Sheet 1 1 of AND2B1 FD U82 OR2 OBUF NINIT OPAD P65 NINIT

A19 P63

U9 U34 ASTB P86 IBUF ASTB SELECT P48,FAST OBUFZ U74

SELECT AND2B1 Size |PARTTYPE=3030PQ100-70 A3 Date:

REV 1 7

5 Port0

DI[0..7] A[0..19] NIOWR NIORD D BS0 BS1

DI[0..7] A[0..19] NIOWR U91 NIORD U89 NAND2B1 XNOR2 A4 I/O access U90 A5 U94 700x A2 AND4B2 U108 A2 A1 A0 A8 A9 A10 AND5B5 A0 A2 A11 A15 A12 A1 A13 A14 AND5B2 A0 A2 AND4B2 U99 A0 x=3 U105 A1 AND4B1 U98 x=2 AND4B1 U107 x=5 x=6 NDE A0 A1 A2 AND4B3 U97 A0 A1 x=1 U96 x=0

DI[0..7] NIORD NIOWR SELPORT0 SELDDR0 PORT0.SCH Port1 DI[0..7] NIOWR SELPORT1 PORT1.SCH Port2 DI[0..7] NIOWR NIORD CLK_DB SELP23 SELP22 C SELP21 PORT2.SCH Port3 NIORD SELPORT3 DO[0..7] CPUCLK CLK_DB PORT3.SCH A1 Port4 A2 AND4B1 DI[0..7] U100 A2 A1 x=4 NIOWR SELPORT4 AND4B2 U251 A0 A1 A2 DI0 AND4 U101 D Q SSNO SSNI NIOWR C CE FDC A2 AND4 DO0 U102 NIORD XU1 TBUF U93 IBUF OPAD P59 SSN U92 OBUFT x=7 PORT4.SCH B DO[0..7] CPUCLK CPUCLK CPUCLK D DO[0..7] DO[0..7] DO[0..7]

BS2 NOR2 A6 A7 U95 AND5B2

SELECT

U103 INV

A0

U88

U104 A0 A1

A DI1

NAND2B1 U106 D Q NOD NOD XU2 C CE FDC 8 7 6 5 4 3 TBUF DO1 Title

Michael Kraemer Michael Kraemer Edenkobener Weg 24 D40229 Duesseldorf Germany Decoder Size A3 Date: Document Number DECODER.SCH December 31, 2001 2 Sheet 2 1 of REV 1 7

DI[0..7]

DI[0..7]

DO[0..7]

DO[0..7]

U109 D DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 NIOWR NIOWR D0 D1 D2 D3 D4 D5 D6 D7 C RD8C PI02 U110 SELPORT0 NIORD NIORD NAND2B1 U143 DI0 D Q DDIR PI04 C C SELDDR0 CE FDC PI05 XU8 TB05 DO5 PI01 INLAT PI05 INLAT XU7 TB04 C DO4 PI03 XU6 TB03 DO3 DDIR U136 INV PO01 U113 OBUFZ U112 DDIR U128 Q01 U141 INV PO05 U121 OBUFZ U131 Q05 U120 CPUCLK XU5 TB02 DO2 PI00 INLAT PI04 INLAT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CE PO00 PO01 PO02 PO03 PO04 PO05 PO06 PO07 PI00 XU3 TB00 DO0 DDIR U135 INV PO00 DO1 U111 OBUFZ DDIR U127 Q00 U142 INV PO04 U119 OBUFZ U132 Q04 D

PI01

XU4 TB01

PI06

XU9 TB06

DO6 DDIR U137 INV PO02

U114 DDIR U129 Q02 U140 INV PO06

U122

U115 OBUFZ

U123 OBUFZ

U130 Q06

PI07

XU10 DO7 TB07

INLAT PI02 PI06

INLAT

B U138 INV PO03

U116 DDIR DDIR U134 Q03 U139 INV PO07

U124

U117 OBUFZ

U125 OBUFZ

U133 Q07

INLAT PI03 PI07

INLAT

U118

U126

Michael Kraemer Michael Kraemer Edenkobener Weg 24 D40229 Duesseldorf Germany Title Port 0 Size A3 Date: 8 7 6 5 4 3 Document Number PORT0.SCH December 19, 1999 2 Sheet 3 1 of REV 1 7

DI[0..7]

DI[0..7] U145 U146 PO10 Q10 OBUF U144 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 D0 D1 D2 D3 D4 D5 D6 D7 C RD8C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CE PO10 PO11 PO12 U147 U153 PO11 OBUF U148 U154 PO12 OBUF U149 U155 Q13 OBUF U150 U156 OPAD ,SLOW Q12 OPAD ,SLOW Q11 OPAD ,SLOW OPAD ,SLOW D

NIOWR SELPORT1

NIOWR

C OBUF U151

Q14 OPAD ,SLOW U157 Q15 OBUF U152 U158 Q16 OBUF U159 GND OPAD ,SLOW OPAD ,SLOW

Michael Kraemer Michael Kraemer Edenkobener Weg 24 D40229 Duesseldorf Germany Title Port 1 (Output Port) Size A3 Date: 8 7 6 5 4 3 Document Number PORT1.SCH December 19, 1999 2 Sheet 4 1 of REV 1 7

DI[0..7]

DI[0..7] U168 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 D0 D1 D2 D3 D4 D5 D6 D7 C RD8C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CE BACK0 BACK1 BACK2 BACK3 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 U176 D0 D1 D2 D3 D4 D5 D6 D7 C RD8C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CE SERADR SPARE

CLK2 CLK4 CLK8 U204 CLK16 CLK32 CNT0 TX AND2 AND5B4 S U205 CPUCLK C R FRS CPUCLK XR3 PULLUP INLAT U161 Q26 OBUF SERDATA U160 U175 U162 Q27 CE C R SR8RLED OBUF SELP23 NIORD NIORD NAND2B1 SERADR XU11 TB20 DO0 U207 DO[0..7] DO[0..7] C SPARE SERADR OBUF U198 U202 Q25 ,SLOW Q SERCLK SERDATA OBUF U195 U201 Q24 ,SLOW OBUF U197 U200 Q23 ,SLOW D U206 SERCLK U196 U199 Q22 ,SLOW

D NIOWR SELP21 SELP23 SELP23 NIOWR

CPUCLK U180 U169 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 D0 D1 D2 D3 D4 D5 D6 D7 C RD8C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CE CESR CPUCLK U188 U179 SLI D0 D1 D2 D3 D4 D5 D6 D7 SRI L LEFT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

SELP22 C NIOWR AND2B1 U189 D Q U178 D Q AND2B1

U177 GND U190

U194 U191 S C C FD CPUCLK C R FD FRS S U192 U163 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CEO TC CLK2 CLK4 CLK8 CLK16 CLK32 CLK64 CLK128 CLK256 CLK2 CLK4 CLK8 CLK16 CLK32 U209 U170 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CEO TC BACK0 BACK1 BACK2 BACK3 A0 A1 A2 A3 EQ B0 B1 B2 B3 COMP4 CLK2 CLK4 CLK8 CLK16 CLK32 AND5 CPUCLK U182 U181 Q0 R CE C C8BCR U184 GND U171 U172 U173 U174 Q21 ,FAST INV FDRSE U165 GND 8 7 CLK_DB Size A3 Date: 6 5 4 3 March 18, 2000 2 OBUF CLK256 OBUF U166 U167 Q20 Title Port 2 (SIO, LCD Backlight/neg.V) Document Number PORT2.SCH Sheet 5 1 of REV 1 7 Q1 Q2 TC AND3 TXBE U211 XU17 TB26 DO6 AND5B5 U186 CNT0 U203 AND3B1 XU16 AND2B1 U185 OR2 TB25 DO5 AND2 OR2 U183 CESR CPUCLK C R FRS U210 START_TX B XU15 TB24 DO4 Q OR2 XU14 TB23 DO3 OR2 U193 START_TX U212 XU13 TB22 DO2 Q TXBE INV TX SPARE XU12 TB21 DO1

U164 VCC

CPUCLK

CE C R

CB8RE

CE C R

XU18 TB27

DO7

CB8RE

Michael Kraemer Michael Kraemer Edenkobener Weg 24 D40229 Duesseldorf Germany

DO[0..7]

DO[0..7] INLAT

XR4 PULLUP U221 Q30 CPUCLK U214 XR5 PULLUP U243 U244 Q0 Q1 Q2 Q3 CE PI130 PI131 PI132 PI133 D0 D1 D2 D3 C RD4C Q0 Q1 Q2 Q3 CE PI230 PI231 PI232 PI233 INLAT PI31 U222 Q31 PI30 PI31 PI32 PI33 D0 D1 D2 D3 C RD4C D CPUCLK

U213 SELPORT3 NIORD D NIORD NAND2B1 PI230 XU19 TB30 DO0 U228 VCC

PI30

PI231

XU20 TB31

DO1

CLK_DB PI232 XU21 TB32 DO2

CLK_DB

U215 XR6 PULLUP INLAT U223 Q32

PI233

XU22 TB33

PI32 DO3

U216 XU23 TB34 C PI33 XU24 TB35 DO5 U217 INLAT U224 Q33 C DO4 XR7 PULLUP

XU25 TB36

DO6

U235 XU26 U240 TB37 DO7 CPUCLK

U236 U237 INTP1 P71,FAST U238

OBUF FDRS U252 GND B INV U239 Q FD AND2B1 PI30 PI130 PI230 AND3B1 U229 OR4 AND3B2 U232 AND3B2 U248 U230 U233 PI32 PI132 PI232 AND3B1 U245 OR4 OR2 CLK_DB PI31 PI131 PI231 AND3B1 U231 A PI33 PI133 PI233 AND3B1 U247 C FD U246 U249 U250 U234 D

CPUCLK

Michael Kraemer Michael Kraemer Edenkobener Weg 24 D40229 Duesseldorf Germany Title Port 3 (Input Port) Size A3 Date: 8 7 6 5 4 3 Document Number PORT3.SCH December 31, 2001 2 Sheet 6 1 of REV 1 7

AND3B2

AND3B2

DI[0..7]

DI[0..7] U145 U146 D6 Q34 OBUF U144 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 D0 D1 D2 D3 D4 D5 D6 D7 C RD8C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CE D6 D12 D24 D48 U147 U153 D12 OBUF U148 U154 D24 OBUF U149 U155 D48 OBUF Q37 OPAD ,SLOW Q36 OPAD ,SLOW Q35 OPAD ,SLOW OPAD ,SLOW D

NIOWR SELPORT4

NIOWR

Michael Kraemer Michael Kraemer Edenkobener Weg 24 D40229 Duesseldorf Germany Title Port 4 (Output Port) Size A3 Date: 8 7 6 5 4 3 Document Number PORT4.SCH December 31, 2001 2 Sheet 7 1 of REV 1 7

Schematics

WOBBEL-PA

VCC P7 1 6 2 7 3 8 4 9 5 DSUB9HF U2 1 2 3 4 5 6 7 8 9 I1 I2 I3 I4 I5 I6 I7 I8 GND Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 COM 18 17 16 15 14 13 12 11 10 C9 0.1uF C R3 820 R17 51 P3 P4 C8 0.1uF 4 2 P1 P2 R4 200 3 R1 51 C7 0.1uF 7 AD811AN L2 FP5 VCC12P C VCC

RELAY-TQ2SA-5V U4

1 0

RELAY-TQ2SA-5V U5

1 0

RELAY-TQ2SA-5V U6

1 0

RELAY-TQ2SA-5V U7

1 0

ULN2803

8 P5

L1 FP5 VCC12M R7 39 R10 91 R6 150 R8 82 -12dB R9 82 R13 390 R11 56 -24dB R12 56 R14 6K2 R15 51 -48dB R16 51 P6

U3 6

R2 51

R5 150 -6dB

B VCC12P

VCC U1 1 C4 10uFT6.3 C1 0.1uF 2 GND NMA0512S DC/DC Converter VCC +V 0V -V 6 5 4

C2 0.1uF

C5 4.7uFT16

C3 0.1uF

C6 4.7uFT16

VCC12M A U8 M3 U9 M3 U10 M3 U11 M3 Michael Kraemer Michael Kraemer Edenkobener Weg 24 D40229 Duesseldorf Germany 1 1 1 1 Title Endstufe fuer Wobbelsender Size A3 Date: 8 7 6 5 4 3 Document Number WOBBELPA.SCH May 14, 2000 2 Sheet 1 1 of REV 1 1 A