Lec 09 DecoderEncoder MuxDemux

EC402 Digital Electronic Circuits
Combinational Circuit Design

Dr. Sushanta K. Mandal 1st Floor, Faculty Block -5 KIIT
Decoder
A decoder is a multiple-input, multiple output combinational circuit that converts binary information from n input lines to an 2n unique output lines. Applications:
Microprocessor memory system: selecting different banks of memory. Microprocessor I/O: Selecting different devices (printer) Microprocessor instruction decoding: Enabling different functional units. Memory: Decoding memory addresses (e.g. in ROM).
Sushanta K. Mandal EC402 Digital Electronic Circuits Spring 2011 2
General Structure of a Decoder Circuit
Sushanta K. Mandal
EC402 Digital Electronic Circuits Spring 2011
1-2-line Decoder
A 0 D0 1 D1 0 1 D0 1 0
D1
D0 = A D1 = A
2-to-4-Line Decoder
2-to-4 -line D1 A1 decoder D2

A0 D3
D0
A1 A0 D3 D2 D1 D0 0 0 1 1 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0
Sushanta K. Mandal
2-to-4-Line Decoder
A1
A1 A0 D0
A0 0 1 0 1
D3 0 0 0 1
D2 0 0 1 0
D1 0 1 0 0
D0 1 0 0 0
0 0 1 1
D1
D2
D 0 = A1 A 0 D1 = A1A 0 D 2 = A1 A 0 D 3 = A 1A 0
D3
Sushanta K. Mandal
2-to-4-Line Decoder w/ Enable

E n 0 1 1 1 1 A 1 X 0 0 1 1 A 0 X 0 1 0 1 D 3 0 0 0 0 1 D 2 0 0 0 1 0 D 1 0 0 1 0 0 D 0 0 1 0 0 0
2-to-4 -line D1 A1 decoder D2

A0 En D3
D0
D 0 = En A1 A 0 D1 = En A1A 0 D 2 = EnA1 A 0 D3 = EnA1A 0
Sushanta K. Mandal

En A1 A0 D0
En A1 A0 D3 D2 D1 D0 0 1 1
D1
X 0 0 1 1
X 0 1 0 1
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 1 0 0 0
1 1
D2
D 0 = En A1 A 0
D3
D1 = En A1A 0 D 2 = EnA1 A 0 D3 = EnA1A 0
Sushanta K. Mandal

Complemented outputs
D 0 = En A1 A 0 D1 = En A1A 0 D 2 = EnA1 A 0 D3 = EnA1A 0

The decoder is enabled when E = 0. The output whose value = 0 represents the minterm is selected by inputs A and B.
The decoder is disabled when E = 1 D0 D3 = 1

3-to-8-Line Decoder
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3-to-8-Line Decoder
Outputs D3 D4 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0
0 0 0 0 1 1 1 1
Binary Inputs 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
D0 1 0 0 0 0 0 0 0
D1 0 1 0 0 0 0 0 0
D2 0 0 1 0 0 0 0 0
D5 0 0 0 0 0 1 0 0
D6 0 0 0 0 0 0 1 0
D7 0 0 0 0 0 0 0 1
If the input corresponds to minterm mi then the decoder ouputi will be the single asserted output.
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3-to-8-Line Decoder using 2-to4-line Decoder

Truth Table A0 A1 A2 D0 A0 2-to-4 D 1 -line A1 decoder D2 D3 En D0 D1 D2 D3
A2 0 0 0 0 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 D7 0 0 0 0 0 0 0 1 D6 0 0 0 0 0 0 1 0 D5 0 0 0 0 0 1 0 0 D4 0 0 0 0 1 0 0 0 D3 0 0 0 1 0 0 0 0 D2 0 0 1 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D0 1 0 0 0 0 0 0 0
D0 A0 2-to-4 D 1 -line A1 decoder D2 D3 En
D4 D5 D6 D7
1 1 1
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4-to-16-Line Decoder
When w = 0, the top decoder is enabled and the bottom is disabled. Top decoder generates 8 minterms 0000 to 0111, while the bottom decoder outputs are 0s.
When w = 1, the top decoder is disabled and the bottom is enabled. Bottom decoder generates 8 minterms 1000 to 1111, while the top decoder outputs are 0s.
Implementing Logic w/ Decoder

F1(X, Y, Z) = m(1, 2, 6, 7) F2(X, Y, Z) = m( 4, 6 )
D0 D1 D3 D4 D5 D6 D7
Z Y X
A0 3-to-8 A1 A2
F1
-line D2 decoder
F2
Combinational Logic (Full-Adder) using Decoder

Ci 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C 0 0 0 1 0 1 1 1
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MSI 74x138
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MSI 74x138
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MSI 74x138
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MSI 74x138 Logic Diagram
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Position encoding for a 3-bit mechanical encoding disk
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Using a 3-to-8 decoder to decode a Gray code.
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4-to-16 decoder using 74X138
N3
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5-to-32 decoder from 74X138 chips

Chip select goes to input G2B
Global enable goes to inputs G1 and G2A

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Complete 74x139 Decoder
All Inputs buffered to minimise loading

M-to-N-Line Encoder (M2 )
2-to-4 -line D1 A1 Decoder D2

A0 En D3
D0
D0 D1 D2 D3
4-to-2 A0 -line Encoder A 1

Ac
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M-to-N-Line Encoder
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4-to-2 Encoder
D1 D0 For A0 00 01 11 10 D3 D2
00 D3 0 0 0 1 D2 0 0 1 0 D1 0 1 0 0 D0 1 0 0 0 A1 0 0 1 1 1 0 1 A0 01 11 10 X 0 X 1 0 X X X X X X X 1 X X X
A0 = D1 + D3 or D2D0
D1 D0 For A1 00 01 11 10 D3 D2
00 01 11 10 X 1 X 1 0 X X X X X X X 0 X X X
Since Dx=1 only in one column at a time A0 = D1 + D3 A1 = D2 + D3
A1 = D2 + D3 or D1D0
8-to-3 Encoder (Octal-to-binary)

D7 0 0 0 0 0 0 0 1 D6 0 0 0 0 0 0 1 0 D5 0 0 0 0 0 1 0 0 D4 0 0 0 0 1 0 0 0 D3 0 0 0 1 0 0 0 0 D2 0 0 1 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D0 1 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
Since Dx=1 only in one column at a time A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7

Example 1 of an Encoder
Only point to one single reading at a Sushanta K. Mandal EC402 Digital Electronic Circuits time. Spring 2011
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Priority Encoder
The encoder defined in the last slide has the limitation that only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination. Example: if D3 and D6 are 1, the output of the encoder will be 111. z = D1+ D3+ D5+ D7 y = D2+ D3+ D6+ D7 x = D4+ D5+D6+ D7
Priority Encoder
This does not represent either binary 3 or binary 6. To resolve this ambiguity, encoder circuit must establish an input priority to ensure that only one input is encoded.
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Priority Encoder
A priority encoder is an encoder circuit that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.
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Priority Encoder
Valid bit indicator (V) is set to 1 when one or more inputs are equal to 1. If all inputs are 0, there is no valid inputs and V is equal to 0. Timing analysis
Priority Encoder
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Map for a Priority Encoder
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Implementation of Priority Encoder
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Design Problem
Design a 4-input priority encoder in which D0 having the highest priority and input D3 the lowest priority.
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Design Problem
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Design Problem
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Multiplexers (Mux)
A multiplexer is a combinational circuit that selects binary information from one of 2 n input lines and directs it to a single line. There are n selection lines.
Multiplexers (Mux)
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4-to-1-line Mux w/o Enable

S1 S0 0 1 0 1 0 1 0 1 A3 X X X 0 X X X 1 A2 X X 0 X X X 1 X A1 X 0 X X X 1 X X A0 0 X X X 1 X X X F 0 0 0 0 1 1 1 1
A0 A1 A2 A3
0 0
4-to-1 Mux
S1 S0
1 1 0 0 1 1
S1 0 0 1 1
Sushanta K. Mandal
S0 0 1 0 1
F A0 A1 A2 A3
EC402 Digital Electronic Circuits Spring 2011 42
F = S1S0A0 + S1S0A1 + S1S0A2 + S1S0A3
4-to-1-line Mux using 2X1 mux

I0 I1 0 1 Y0 I0 I1 Y1 0 1 F
2-to-1 Mux
S0
2-to-1 Mux
S1
I2 I3
0 1
2-to-1 Mux
S0
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4-to-1-line Mux
F = S1S0A0 + S1S0A1 + S1S0A2 + S1S0A3
S1 S0 A0 F
A1
A2
A3
4-to-1-line Mux with Enable

A0 A1 A2 A3 En
En 0 1 1 1 1 S1 X 0 0 1 1 S0 X 0 1 0 1 F 0 A0 A1 A2 A3
4-to-1 Mux
S1 S0
F = En (S1S0A0 + S1S0A1 + S1S0A2 + S1S0A3) = EnS1S0A0 + EnS1S0A1 + EnS1S0A2 + EnS1S0A3
Functionality: Selection of a particular input Route 1 of N inputs (A) to the output F N log Require 2 Selection bits (S) En(able) bit can disable the route and set F to 0
4-to-1-line Mux with Enable

F = En (S1S0A0 + S1S0A1 + S1S0A2 + S1S0A3)
S1 S0 A0 F
A1
A2
A3 En
Quadruple 2-to-1-Line Multiplexer
A[3:0]
En A3-0
B[3:0]
B3-0
2-to-1 Mux (4-bit bus)

SEL
F[3:0]
En 0 1 1
SEL X 0 1
F[3:0] 0000 A[3:0] B[3:0]
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Quadruple 2-to-1-Line Multiplexer
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Quadruple 2-to-1-Line Multiplexer with Enable

A0 A1 A2 A3 F0 F1 F2 F3 En 0 1 1 SE L X 0 1 F[3:0] 0000 A[3:0] B[3:0] Fx=AxEnSEL+BxEnSEL
SEL B0 B1 B2 B3 En
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Design Canonical Form w/ MUX

F(A, B, C) = A BC + ABC + ABC + ABC
F(A, B, C) = m(1, 2, 6, 7)
0 1 1 0 0 0 1 1 A0 A1 A2 A3 A4 A5 A6 A7
Each input in a MUX is a minterm OR gates are included
8-to-1 Mux
S 2 S 1 S0 A B C
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F = m(1, 2, 6, 7)
F = A BC + ABC + ABC + ABC

En
Each input in a MUX is a minterm OR gates are included
C C 0 1
Vdd
A0 A1 A2 A3
A
F
B 0 1 0 1
F C C 0 1
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4-to-1 Mux
S1 A S0 B
0 0 1 1
Sushanta K. Mandal

F = m(1, 2, 6, 7)
F = A BC + ABC + ABC + ABC

B
A0 A A
Vdd
C 0 1 0 1
F 0 A 1 A
En
0
F
A1 A2 A3
4-to-1 Mux
S1 B S0 C
0 1 1
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Full Adder using MUX

S = Cin A B + Cin AB + Cin AB + Cin AB
A 0
Ci Ci Ci A0 A1 A2 A3
B 0 0 1 1 0 0 1 1
Ci 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1 Ci Ci Ci Ci Ci Ci Ci Ci
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0 4-to-1 Mux
S1 A S0 B Sum
0 0 1 1 1 1
Sushanta K. Mandal
Full Adder using MUX

A
A0 Ci
Vdd
B 0 0 1 1 0 0 1 1
Ci 0 1 0 1 0 1 0 1
Co 0 0 0 1 0 1 1 1 0 0 Ci Ci Ci Ci 1 1
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0 4-to-1 Mux
S1 A S0 B Carry
A1 A2 A3
0 0 0 1 1 1 1
Sushanta K. Mandal
Function Implementation using 8x1Multiplexer

F ( A, B, C , D) = (1, 3, 4,11,12,13,14,15)
1. Complete the truth table from the SOP. 2. The first n 1 variables in the table are applied to the selection inputs of the multiplexer. 3. For each combination of the selection variables, we evaluate the output as a function of the last variable. 4. Apply these values to the data input in proper order.
Function Implementation using 8x1MUX

F ( A, B, C , D) = (1, 3, 4,11,12,13,14,15)
note the order of input lines
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MSI 74x157
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MSI 74x157
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MSI 74x157
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MSI 74x151
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Demultiplexers (DeMux)
A0 A1 A2 A3
D0
4-to-1 Mux
S1 S0
1-to-4 DeMux D2
S1 S0 D3
D1
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Demultiplexer Operation
S1 0 0 D0 A 1-to-4 DeMux D2 S1 S0 D3 D1 1 1 S0 0 1 0 1 D3 0 0 0 A D2 0 0 A 0 D1 0 A 0 0 D0 A 0 0 0
D 0 = S1 S0 A D1 = S1S0 A D 2 = S1 S0 A D 3 = S1S0 A
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Demultiplexer Operation
S1 D0 S0 D1
S1 0 0 1 1
S0 0 1 0 1
D3 0 0 0 A
D2 0 0 A 0
D1 0 A 0 0
D0 A 0 0 0
D2
D 0 = S1 S0 A D1 = S1S0 A D 2 = S1 S0 A D 3 = S1S0 A
D3
A
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Demultiplexer with Enable

S1 D0 S0 D1 En 0 D2 1 1 D3 1 1 S1 X 0 0 1 1 S0 X 0 1 0 1 D3 D2 D1 0 0 0 0 A 0 0 0 A 0 0 0 A 0 0 D0 0 A 0 0 0
En
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A
EC402 Digital Electronic Circuits Spring 2011 64
BCD-to-Decimal Decoder (74LS42)

Does not have an enable input Can be used as a 3-to-8 decoder with the D input used as an enable input (a) Logic diagram for the 7442 BCD-to-decimal decoder (b) logic symbol (c) truth table
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BCD-to-7-Segment Decoder
Another kind of decoder
A B C D
BCD-to-7Segment Decoder
a b c d e f g
a b c d e f g
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Another kind of decoder
A B C D
a b c d e f g
a b c d e f g e f
a b
g c
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Decode 2 and show
0 0 1 0
A B C D
a b c d e f g
1 1 0 1 1 0 1
a b c d e f g e f
a b
g c
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Decode 4 and show
0 1 0 0
A B C D
a b c d e f g
0 1 1 0 0 1 1
a b c d e f g e f
a b
g c
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BCD-to-7-segment decoder/driver driving a commonanode 7-segment LED display
Notice the current limiting resistors, required to prevent overdriving the LED display
Segment patterns for all possible input codes
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Common-anode: All the anode connections of the LEDs are joined together to Vcc, LED ON when input signal (Output) is LOW Common-cathode : All the cathode connections of the LEDs are joined together to GND. NO VCC , LED ON when input (Output) is HIGH
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TTL and CMOS devices are normally not used to drive the common-cathode display directly because of current (mA) requirement. A buffer circuit is used between the decoder chips and common-cathode display
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BCD-to-7-Segment Decoder Truth Table

A 0 1 2 3 4 5 6 7 8 9 >10 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 a 1 0 1 1 0 1 0 1 1 1 0 b 1 1 1 1 1 0 0 1 1 1 0 c 1 1 0 1 1 1 1 1 1 1 0 d 1 0 1 1 0 1 1 0 1 0 0 e 1 0 1 0 0 0 1 0 1 0 0 f 1 0 0 0 1 1 1 0 1 1 0 g 0 0 1 1 1 1 1 0 1 1 0
All other inputs
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Design Each Output Individually a

A 0 1 2 3 4 5 6 7 8 9 >10 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 a 1 0 1 1 0 1 0 1 1 1 0
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AB
CD
00 1 0 0 1
01 0 1 0 1
11 1 1 0 0
10 1 0 0 0
00 01 11 10
a = A BD + ACD + ABD + A BC
All other inputs
Sushanta K. Mandal
Design Each Output Individually b

A 0 1 2 3 4 5 6 7 8 9 >10 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 b 1 1 1 1 1 0 0 1 1 1 0
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AB
CD
00 1 1 0 1
01 1 0 0 1
11 1 1 0 0
10 1 0 0 0
00 01 11 10
b = BC + A B + ACD + ACD
All other inputs
Sushanta K. Mandal

Lec 09 DecoderEncoder MuxDemux

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Lec 09 DecoderEncoder MuxDemux

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EC402 Digital Electronic Circuits

Combinational Circuit Design

General Structure of a Decoder Circuit

EC402 Digital Electronic Circuits Spring 2011

2-to-4 -line D1 A1 decoder D2

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

2-to-4-Line Decoder w/ Enable

2-to-4 -line D1 A1 decoder D2

D 0 = En A1 A 0 D1 = En A1A 0 D 2 = EnA1 A 0 D3 = EnA1A 0

EC402 Digital Electronic Circuits Spring 2011

2-to-4-Line Decoder w/ Enable

D1 = En A1A 0 D 2 = EnA1 A 0 D3 = EnA1A 0

EC402 Digital Electronic Circuits Spring 2011

2-to-4-Line Decoder w/ Enable

D 0 = En A1 A 0 D1 = En A1A 0 D 2 = EnA1 A 0 D3 = EnA1A 0

The decoder is disabled when E = 1 D0 D3 = 1

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

3-to-8-Line Decoder using 2-to4-line Decoder

D0 A0 2-to-4 D 1 -line A1 decoder D2 D3 En

EC402 Digital Electronic Circuits Spring 2011

Implementing Logic w/ Decoder

Combinational Logic (Full-Adder) using Decoder

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

MSI 74x138 Logic Diagram

EC402 Digital Electronic Circuits Spring 2011

Position encoding for a 3-bit mechanical encoding disk

EC402 Digital Electronic Circuits Spring 2011

Using a 3-to-8 decoder to decode a Gray code.

EC402 Digital Electronic Circuits Spring 2011

4-to-16 decoder using 74X138

5-to-32 decoder from 74X138 chips

Global enable goes to inputs G1 and G2A

Complete 74x139 Decoder

All Inputs buffered to minimise loading

M-to-N-Line Encoder (M2 )

2-to-4 -line D1 A1 Decoder D2

4-to-2 A0 -line Encoder A 1

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

Since Dx=1 only in one column at a time A0 = D1 + D3 A1 = D2 + D3

8-to-3 Encoder (Octal-to-binary)

Since Dx=1 only in one column at a time A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

Map for a Priority Encoder

EC402 Digital Electronic Circuits Spring 2011

Implementation of Priority Encoder

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

EC402 Digital Electronic Circuits Spring 2011

4-to-1-line Mux w/o Enable

F = S1S0A0 + S1S0A1 + S1S0A2 + S1S0A3

4-to-1-line Mux using 2X1 mux

EC402 Digital Electronic Circuits Spring 2011

4-to-1-line Mux with Enable

F = En (S1S0A0 + S1S0A1 + S1S0A2 + S1S0A3) = EnS1S0A0 + EnS1S0A1 + EnS1S0A2 + EnS1S0A3