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U2 7 1 2 6 3 5 4 A B C D O A O B O C O D 13 12 11 10 9 15 14

O E LT O F RB I O G B I/RB O 74 47N

CHAPTER 9: ASYNCHRONOUS COUNTERS

D.Wilcher

CHAPTER 9: OBJECTIVES Describe the difference between Asynchronous and Synchronous counters. Analyze counter circuits and diagrams. Explain how propagation delay affect the operation of counter. Determine the modulus of a given counter Modify the modulus of a counter. Discriminate the difference between a 4 Bit Binary and Decade counter.
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CHAPTER 9: OBJECTIVES continue Design a counter that will have any specified sequence of states. Explain the operation of cascaded counters. Use logic gates to decode counters. Eliminate glitches in a counter circuit. Explain how a digital clock operates. Troubleshoot counter circuits Use counters in specified applications.
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CHAPTER 9: Digital ICs used in this chapter discussion 74LS93A (4 Bit Asynchronous Binary Counter) 74LS160 (Synchronous BCD Decade Counter w/Asynchronous Clear) 74HC161 (4Bit Synchronous Binary Counter w/Asynchronous Clear) 74HC163 (Synchronous 4 Bit Binary Counter w/Synchronous Clear) 74HC190 (Synchronous [BCD] Decade Up/Down Counter) 74LS47 (Dual D Flip-Flop)
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2-Bit Asynchronous Counter The clock input of an asynchronous counter is always connected only to the LSB (Least Significant Bit) flip-flops. Asynchronous Counter is a digital circuit in which flip-flops (FF) within the counter do not change states at exactly the same time because they do not have a common clock pulse. Clock signal is applied to the clock input C of LSB flip-flop. Asynchronous counters are also known as ripple counters
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Figure 9--1

A 2-bit asynchronous binary counter. Open file F09-01 to verify operation.

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

ASYNCHRONOUS Events that do not have fixed time relationship with each other and generally, do not occur at the same time.

D.Wilcher

Timing Diagram for a 2-Bit Asynchronous Counter By applying 4 clock pulses to FF0 and observing Q output of each FF, the changes in the state of the digital IC output response can be validated. Positive going edges of the CLK causes the QO outputs to toggle, i.e, Hi to Lo. The Timing Diagram is a graphical tool for observing the input CLK events and the FFs corresponding output (states) responses.

D.Wilcher

Figure 9--2

Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

3-Bit Asynchronous Counter Operation is the same as that of a 2-Bit Counter. The counter has 8 states instead of 4. An additional FF is wired to the dual FFs of a 2Bit Counter. Just like a 2 Bit Counter a Timing Diagram is used to analyze the counting sequence of the digital circuit.

D.Wilcher

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Figure 9--3

Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F09-03 to verify operation.

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Propagation Delay Due to the rippling effect of toggling sequential FFs, there is a small delay associated with this trggering event. The rippling effect is due to the input clock pulse triggering the first FF and then each additional FF triggering its adjacent neighbor. Therefore, the switching of each FF is not instananeous. This propagation delay is a disadvantage to using Asynchronous Binary Counters
D.Wilcher
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Figure 9--4

Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

PROPAGATION DELAY The time required for a logic-level change to be transmitted through one or more digital elements.

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4-Bit Asynchronous Counter Operation is the same as that of a 2 & 3-Bit Counters. The counter has 16 states instead of 4 & 8. An additional FF is wired to the dual FFs of a 3Bit Counter. Just like a 2 & 3 Bit Asynchronous Counters a Timing Diagram is used to analyze the counting sequence of the digital circuit.

D.Wilcher

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Figure 9--5

Four-bit asynchronous binary counter and its timing diagram. Open file F09-05 and verify the operation.

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Calculating Total Propagation Delay (tp(tot)) To calculate the tp(tot) of an Asynchronous Binary Counter multiply the number FFs by the Propagation Delay (PD) of one digital device.

EQ1) tp(tot) = nFF x PD

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Calculating The Maximum Clock Frequency To calculate the maximum clock frequency (fmax) of digital counter.

EQ2) fmax = 1/tp(tot)

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Determining the Number of States for an Asynchronous Binary Counter To calculate number of states or count value for an Asynchronous Binary Counter:

EQ3) #States = 2n n is the number of FFs

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Calculating tp(tot) and fmax a 4-Bit Binary Counter

CALCULATOR TRY OUT!!! TO SEE HOW THESE EQUATIONS WORK DO EXAMPLE/SOLUTION EXERCISE ON PAGE 463 IN TEXTBOOK! ALSO CALCULATE THE #STATES FOR THE BINARY COUNTER.

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Asynchronous Decade Counters An Asynchronous Decade Counter has an unique number states. The modulus is another way of describing an Asynchronous Decade Counters unique number of states. Counters can be designed to have a number of states in their counting sequence that is less than the maximum of 2n. The resulting sequence is called a truncated sequence.
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Asynchronous Decade Counters continued One common modulus for counters with truncated sequences is ten (called MOD 10). Counters with ten states in their sequence are called decade counters. The count sequence of zero (0000) through nine (1001) is a BCD (Binary Coded Decimal) decade counter. This counter is useful in display applications in which BCD is required for conversion to a decimal readout.
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Partial Decoding Technique By wiring a NAND gate to Q1 and Q3 partial decoding is accomplished. Resets the counter to zero (0000) when the 10th clock pulse is reached. Other counting sequences can be achieved using the Partial Decoding Technique.

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Figure 9--6

An asynchronously clocked decade counter with asynchronous recycling.

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

A 4Bit Asynchronous Binary Counter Example The 74LS93A Digital IC An Application Specific Integrated Circuit (ASIC) dedicated for 4 Bit Asynchronous Binary Counting. It has 4 internal JK FFs. A 2 Input NAND Gate for clearing all FFs. The 2 Input NAND Gate can be wired to the Q1 and Q3 to form a Modulus 12 counter.

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Figure 9--8 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--7

Asynchronously clocked modulus-12 counter with asynchronous recycling.

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--9 states.)

Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--10

74LS93A connected as a modulus-12 counter.

Thomas L. Floyd Digital Fundamentals, 8e

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Copyright 2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.