COUNTERS WITH INPUTS

Inputs Mealy Outputs Mealy vs. Moore

ECEn/CS 224

14 COUNTERSI Page 1

Counters With Inputs

What if you dont want counter to increment every single cycle?

ECEn/CS 224

14 COUNTERSI Page 2

An Incrementable Counter
State Memory Current State

Inputs

Input Forming Logic

Next State

DD QQ
INC Q1 Q0 N1 N0

Note that the next state is a function of the input INC as well as the current state.

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 1 1 0 1 0

ECEn/CS 224

14 COUNTERSI Page 3

Incrementable Counter Derivation

INC Q1 Q0 N1 N0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 0

Doing the KMaps for this results in: N1 = (INCQ1Q0) + (INCQ1) + (Q1Q0) N0 = (INCQ0) + (INCQ0) = INCQ0

ECEn/CS 224

14 COUNTERSI Page 4

Incrementable Counter Behavior

CLK

INC Current State 00 01 10

The counter increments on the clock edge only when INC is asserted

ECEn/CS 224

14 COUNTERSI Page 5

Counters With More Inputs

CLR INC Q1 Q0 N1 N0

CLR = INC = 0 No state transition CLR = 0 INC = 1 Counter Increments CLR = 1 INC = 0 Counter resets to 00 CLR = 1 INC = 1 What should it do?

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 1 1 0 1 1 0 0 0 0 0 ? ? ? ?

0 1 0 1 1 0 1 0 0 0 0 0 ? ? ? ?

ECEn/CS 224

14 COUNTERSI Page 6

Precedence of INC vs. CLR?

1. 2. 3. 4. Could do nothing Could give INC precedence Could give CLR precedence Assume INC=CLR=1 will never occur You decide when you draw the transition table

ECEn/CS 224

14 COUNTERSI Page 7

Case 1 Do Nothing
CLR INC Q1 Q0 N1 N0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 1

N1 =

CLRINCQ1Q0 + CLRINCQ1 + CLRINCQ1 + INCQ1Q0 CLRINCQ0 + CLRINCQ0 + CLRINCQ0

N0 =

ECEn/CS 224

14 COUNTERSI Page 8

Case 2 Give INC Precedence

CLR INC Q1 Q0 N1 N0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 0 0 0 1 0 1 0

N1 =

INCQ1Q0 + CLRINCQ1 + INCQ1Q0 CLRINCQ0 + INCQ0

N0 =

ECEn/CS 224

14 COUNTERSI Page 9

Case 3 Give CLR Precedence

CLR INC Q1 Q0 N1 N0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0

N1 =

CLRINCQ1Q0 + CLRINCQ1 + CLRQ1Q0 CLRINCQ0 + CLRINCQ0

N0 =

ECEn/CS 224

14 COUNTERSI Page 10

Case 4 Assume INC=CLR=1 Will Never Occur

CLR INC Q1 Q0 N1 N0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 X X X X 0 1 0 1 1 0 1 0 0 0 0 0 X X X X

N1 =

CLRINCQ1 + INCQ1Q0 + CLRQ1Q0 CLRINCQ0 + INCQ0

N0 =

What happens in the real circuit when INC=CLR=1? It depends on the final equations

ECEn/CS 224

14 COUNTERSI Page 11

Case 4 When INC=CLR=1 What Happens?

CLR INC Q1 Q0 N1 N0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 0 1 0

N1 =

CLRINCQ1 + INCQ1Q0 + CLRQ1Q0 CLRINCQ0 + INCQ0

N0 =

In the end, Xs in TTs result in some predictable behavior, you just dont care what that is

ECEn/CS 224

14 COUNTERSI Page 12

Moore vs. Mealy Sequential Machines

ECEn/CS 224

14 COUNTERSI Page 13

Moore Sequential Machine (static)

Outputs are a function of current state only

Inputs

Input Forming Logic

Next State

State Memory

Current State

DD QQ

Output Forming Logic

Outputs

ECEn/CS 224

14 COUNTERSI Page 14

Mealy Sequential Machine (dynamic)

Outputs are a function of current state and inputs

Inputs

Input Forming Logic

Next State

State Memory

Current State

DD QQ

Output Forming Logic

Outputs

ECEn/CS 224

14 COUNTERSI Page 15

Example: 2 Bit Counter

Moore output (Z) on count=3 Mealy output (Y) when count=3 and INC=1
Incrementing from 3 back to 0
INC Q1 Q0 N1 N0 Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 1 Y 0 0 0 0 0 0 0 1

Moore outputs usually require multiple entries in TT. Mealy outputs often require only one.

ECEn/CS 224

14 COUNTERSI Page 16

Mealy vs. Moore Timing

CLK
Z output is TRUE whenever count=3 (it is static function of current state) Y output is TRUE whenever count=3 AND INC=1 (it is dynamic function of current state and input)
ECEn/CS 224
14 COUNTERSI Page 17

INC Current State Z

10

11

00