Script started on Tue 05 Mar 2013 10:49:31 AM CST [root@localhost 32]# cd /simplesim-3.0/ anagram_result.log eventq.h mysim_anagram.exp redir.bash s im-profile.

c ANNOUNCE-3.0 FAQ mysim.exp redir.sh s im-profile.o benchmarks go_result.log mysim_gcc.exp regress.sh s im-safe bitmap.h hack_guide.pdf mysim_go.exp regs.c s im-safe.c bpred.c hack_guide.ps mysim_perl.exp regs.h s im-safe.o bpred.h has mysim_v2.exp regs.o s tats.c bpred.o host.h mysim_v3.exp resource.c s tats.h cache.c instruct-progs.tar.gz mysim_v4.exp resource.h s tats.o cache.h libexo mysim_v6.exp resource.o s ymbol.c cache.o LICENSE mysim_v7.exp sim-bpred s ymbol.h config loader.c options.c sim-bpred.c s ymbol.o config.h loader.h options.h sim-bpred.o s yscall.c CONTRIBUTORS loader.o options.o sim-cache s yscall.h dlite.c machine.c pipeview.pl sim-cache.c s yscall.o dlite.h machine.def PROJECTS sim-cache.o s ysprobe dlite.o machine.h ptrace.c sim-eio s ysprobe.c eio.c machine.o ptrace.h sim-eio.c t arget-alpha eio.h main.c ptrace.o sim-eio.o t arget-pisa eio.o main.o range.c sim-fast t ests endian.c Makefile range.h sim-fast.c t ests-alpha endian.h memory.c range.o sim-fast.o t ests-pisa endian.o memory.h README sim.h t extprof.pl eval.c memory.o README.eio sim-outorder v ersion.h eval.h misc.c README.retarget sim-outorder.c W ARRANTY eval.o misc.h README.sim-inorder sim-outorder.o eventq.c misc.o README.windows sim-profile ct mysim_perl.exp <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.

All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache

hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref)

dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none}

-cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> |dl2|none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits

il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb

:dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1):

-cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres

s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

ivalents # -pcstat k)

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing

information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call...

sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 il1.accesses 14918 il1.hits 14199 il1.misses 719 il1.replacements 94 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0482 il1.repl_rate 0.0063 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 719 il2.hits 32 il2.misses 687 il2.replacements 0 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 0.9555 il2.repl_rate 0.0000 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 5173 dl1.hits 4705 dl1.misses 468 dl1.replacements 6 dl1.writebacks 3 dl1.invalidations 0 dl1.miss_rate 0.0905 dl1.repl_rate 0.0012 dl1.wb_rate 0.0006 dl1.inv_rate 0.0000 dl2.accesses 471 dl2.hits 4 dl2.misses 467 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9915 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 82 mem.page_mem 656k

# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #

total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if

# total number of pages allocated # total size of memory pages allocated

mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl>

<name> <nsets> <bsize> <assoc> <repl> Examples:

name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref)

dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger

false false false false

-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits

il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./

benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1):

-cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 il1.accesses 14918 il1.hits 14199 il1.misses 719 il1.replacements 94 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0482 il1.repl_rate 0.0063 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 5173 dl1.hits 4705 dl1.misses 468 dl1.replacements 6 dl1.writebacks 3 dl1.invalidations 0 dl1.miss_rate 0.0905 dl1.repl_rate 0.0012 dl1.wb_rate 0.0006 dl1.inv_rate 0.0000 dl2.accesses 1190 dl2.hits 36 dl2.misses 1154 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9697 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 82 mem.page_mem 656k mem.ptab_misses 146 mem.ptab_accesses 1245031 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total number of pages allocated size of memory pages allocated first level page table misses page table accesses

mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> - name of the cache being defined <nsets> - number of sets in the cache

<bsize> - block size of the cache <assoc> - associativity of the cache <repl> - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random Examples: -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2

-cache:il2 |none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

dl2 # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements

dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file

# -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed

sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).

warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2):

-cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 il1.accesses 14918 il1.hits 14199 il1.misses 719 il1.replacements 94 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0482 il1.repl_rate 0.0063 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 5173 dl1.hits 4705 dl1.misses 468 dl1.replacements 6 dl1.writebacks 3 dl1.invalidations 0 dl1.miss_rate 0.0905 dl1.repl_rate 0.0012 dl1.wb_rate 0.0006 dl1.inv_rate 0.0000 dl2.accesses 1190 dl2.hits 36 dl2.misses 1154 dl2.replacements 2 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9697 dl2.repl_rate 0.0017 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if

mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format:

<name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations

dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # -config -dumpconfig -h -v # # false # false # load configuration from a file dump configuration to a file print help message verbose operation

# -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

false false 1 false <null> <null>

# # # # # #

enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec)

il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc

hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random

Examples:

-cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements

dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

-nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref)

il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).

warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2):

-cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes

ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>|

-tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

none none false false

# # # #

instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations

il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow:

sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a

lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random

Examples:

-cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs

s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}

-flush -cache:icompress ivalents # -pcstat k)

false # flush caches on system calls false # convert 64-bit inst addresses to 32-bit inst equ <null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref)

dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger

false false false false

-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits

il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./

benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1):

-cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 il1.accesses 14918 il1.hits 14199 il1.misses 719 il1.replacements 94 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0482 il1.repl_rate 0.0063 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 5173 dl1.hits 4705 dl1.misses 468 dl1.replacements 6 dl1.writebacks 3 dl1.invalidations 0 dl1.miss_rate 0.0905 dl1.repl_rate 0.0012 dl1.wb_rate 0.0006 dl1.inv_rate 0.0000 dl2.accesses 1190 dl2.hits 36 dl2.misses 1154 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9697 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 82 mem.page_mem 656k mem.ptab_misses 146 mem.ptab_accesses 1245031 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total number of pages allocated size of memory pages allocated first level page table misses page table accesses

mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> - name of the cache being defined <nsets> - number of sets in the cache

<bsize> - block size of the cache <assoc> - associativity of the cache <repl> - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random Examples: -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0017 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2

-cache:il2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> |dl2|none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements

il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i

sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size

ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits

dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.

# -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

false false false false 1 false <null> <null>

# # # # # # # # # #

load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics **

sim_num_insn sim_num_refs sim_elapsed_time sim_inst_rate il1.accesses il1.hits il1.misses il1.replacements il1.writebacks il1.invalidations il1.miss_rate il1.repl_rate il1.wb_rate il1.inv_rate il2.accesses il2.hits il2.misses il2.replacements il2.writebacks il2.invalidations il2.miss_rate il2.repl_rate il2.wb_rate il2.inv_rate dl1.accesses dl1.hits dl1.misses dl1.replacements dl1.writebacks dl1.invalidations dl1.miss_rate dl1.repl_rate dl1.wb_rate dl1.inv_rate dl2.accesses dl2.hits dl2.misses dl2.replacements dl2.writebacks dl2.invalidations dl2.miss_rate dl2.repl_rate dl2.wb_rate dl2.inv_rate ld_text_base ld_text_size ld_data_base ld_data_size s' size in bytes ld_stack_base s in stack) ld_stack_size ld_prog_entry ld_environ_base ld_target_big_endian big endian mem.page_count mem.page_mem mem.ptab_misses mem.ptab_accesses

14918 5148 1 14918.0000 14918 14199 719 94 0 0 0.0482 0.0063 0.0000 0.0000 719 32 687 0 0 0 0.9555 0.0000 0.0000 0.0000 5173 4705 468 6 3 0 0.0905 0.0012 0.0006 0.0000 471 4 467 0 0 0 0.9915 0.0000 0.0000 0.0000 0x0120000000 532480 0x0140000000 119648

# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #

total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

0x011ff9b000 # program stack segment base (highest addres 16384 0x0120012c80 0x011ff97000 0 82 656k 146 1245031 # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total number of pages allocated size of memory pages allocated first level page table misses page table accesses

mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> - name of the cache being defined <nsets> - number of sets in the cache

<bsize> - block size of the cache <assoc> - associativity of the cache <repl> - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random Examples: -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately

false false false false 1 false

# -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

<null> # restore EIO trace execution from <fname> <null> # redirect simulator output to file (non-interacti <null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements

il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 719 # total number of accesses il2.hits 32 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9555 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 471 # total number of accesses dl2.hits 4 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9915 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.

All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache

hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size

ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o

k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits

dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations

il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow:

sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a

lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random

Examples:

-cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs

s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}

-flush -cache:icompress ivalents # -pcstat k)

false # flush caches on system calls false # convert 64-bit inst addresses to 32-bit inst equ <null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14199 # total number of hits il1.misses 719 # total number of misses il1.replacements 94 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0482 # miss rate (i.e., misses/ref) il1.repl_rate 0.0063 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4705 # total number of hits dl1.misses 468 # total number of misses dl1.replacements 6 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0905 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0012 # replacement rate (i.e., repls/ref)

dl1.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger

false false false false

-seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

1 false <null> <null>

# # # #

random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits

il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>>

Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations

dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute

-cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...

sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:37 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs

s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}

-flush -cache:icompress ivalents # -pcstat k)

false # flush caches on system calls false # convert 64-bit inst addresses to 32-bit inst equ <null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref)

il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration,

which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches **

Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 il1.accesses 14918 il1.hits 14224 il1.misses 694 il1.replacements 20 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0465 il1.repl_rate 0.0013 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 694 il2.hits 7 il2.misses 687 il2.replacements 0 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 0.9899 il2.repl_rate 0.0000 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 5173 dl1.hits 4706 dl1.misses 467 dl1.replacements 2 dl1.writebacks 0 dl1.invalidations 0 dl1.miss_rate 0.0903 dl1.repl_rate 0.0004 dl1.wb_rate 0.0000 dl1.inv_rate 0.0000 dl2.accesses 467 dl2.hits 0 dl2.misses 467 dl2.replacements 2 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 1.0000 dl2.repl_rate 0.0043 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if

mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:

<name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations

dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute

-cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing

information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call...

sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.

All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache

hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size

ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o

k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits

dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations

il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0017 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow:

sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address

ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements

dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file

# -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

false false false false 1 false <null> <null>

# # # # # # # #

print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed

sim_elapsed_time sim_inst_rate il1.accesses il1.hits il1.misses il1.replacements il1.writebacks il1.invalidations il1.miss_rate il1.repl_rate il1.wb_rate il1.inv_rate il2.accesses il2.hits il2.misses il2.replacements il2.writebacks il2.invalidations il2.miss_rate il2.repl_rate il2.wb_rate il2.inv_rate dl1.accesses dl1.hits dl1.misses dl1.replacements dl1.writebacks dl1.invalidations dl1.miss_rate dl1.repl_rate dl1.wb_rate dl1.inv_rate dl2.accesses dl2.hits dl2.misses dl2.replacements dl2.writebacks dl2.invalidations dl2.miss_rate dl2.repl_rate dl2.wb_rate dl2.inv_rate ld_text_base ld_text_size ld_data_base ld_data_size s' size in bytes ld_stack_base s in stack) ld_stack_size ld_prog_entry ld_environ_base ld_target_big_endian big endian mem.page_count mem.page_mem mem.ptab_misses mem.ptab_accesses mem.ptab_miss_rate >>>

1 14918.0000 14918 14224 694 20 0 0 0.0465 0.0013 0.0000 0.0000 694 7 687 0 0 0 0.9899 0.0000 0.0000 0.0000 5173 4706 467 2 0 0 0.0903 0.0004 0.0000 0.0000 467 0 467 2 0 0 1.0000 0.0043 0.0000 0.0000 0x0120000000 532480 0x0140000000 119648

# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #

total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

0x011ff9b000 # program stack segment base (highest addres 16384 0x0120012c80 0x011ff97000 0 82 656k 146 1245031 0.0001 # # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total first number of pages allocated size of memory pages allocated first level page table misses page table accesses level page table miss rate

<<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache

<repl> Examples:

- block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits

dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations

il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial

entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g.,

A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 694 # total number of accesses il2.hits 7 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9899 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 467 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2

-cache:il2 |none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

dl2 # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements

dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file

# -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed

sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).

warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2):

-cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 il1.accesses 14918 il1.hits 14224 il1.misses 694 il1.replacements 20 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0465 il1.repl_rate 0.0013 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 5173 dl1.hits 4706 dl1.misses 467 dl1.replacements 2 dl1.writebacks 0 dl1.invalidations 0 dl1.miss_rate 0.0903 dl1.repl_rate 0.0004 dl1.wb_rate 0.0000 dl1.inv_rate 0.0000 dl2.accesses 1161 dl2.hits 7 dl2.misses 1154 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9940 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if

mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:

<name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations

dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute

-cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing

information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call...

sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14224 # total number of hits il1.misses 694 # total number of misses il1.replacements 20 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0465 # miss rate (i.e., misses/ref) il1.repl_rate 0.0013 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4706 # total number of hits dl1.misses 467 # total number of misses dl1.replacements 2 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0903 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1161 # total number of accesses dl2.hits 7 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9940 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0017 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.

All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache

hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14211 # total number of hits il1.misses 707 # total number of misses il1.replacements 83 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0474 # miss rate (i.e., misses/ref) il1.repl_rate 0.0056 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 707 # total number of accesses il2.hits 20 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9717 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4702 # total number of hits dl1.misses 471 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 11 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0910 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0021 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 482 # total number of accesses dl2.hits 15 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9689 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0041 # replacement rate (i.e., repls/ref)

dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none}

-cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> |dl2|none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14211 # total number of hits il1.misses 707 # total number of misses il1.replacements 83 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0474 # miss rate (i.e., misses/ref) il1.repl_rate 0.0056 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 707 # total number of accesses il2.hits 20 # total number of hits

il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9717 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4702 # total number of hits dl1.misses 471 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 11 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0910 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0021 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 482 # total number of accesses dl2.hits 15 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9689 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0041 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb

:dtlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1):

-cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14196 # total number of hits il1.misses 722 # total number of misses il1.replacements 106 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0484 # miss rate (i.e., misses/ref) il1.repl_rate 0.0071 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 722 # total number of accesses il2.hits 35 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9515 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4700 # total number of hits dl1.misses 473 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 6 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0914 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0012 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 479 # total number of accesses dl2.hits 12 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9749 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres

s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

ivalents # -pcstat k)

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14211 # total number of hits il1.misses 707 # total number of misses il1.replacements 83 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0474 # miss rate (i.e., misses/ref) il1.repl_rate 0.0056 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 707 # total number of accesses il2.hits 20 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9717 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

dl1.accesses 5173 # total number of accesses dl1.hits 4702 # total number of hits dl1.misses 471 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 11 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0910 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0021 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 482 # total number of accesses dl2.hits 15 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9689 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing

information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call...

sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 il1.accesses 14918 il1.hits 14211 il1.misses 707 il1.replacements 83 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0474 il1.repl_rate 0.0056 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 707 il2.hits 20 il2.misses 687 il2.replacements 0 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 0.9717 il2.repl_rate 0.0000 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 5173 dl1.hits 4702 dl1.misses 471 dl1.replacements 22 dl1.writebacks 11 dl1.invalidations 0 dl1.miss_rate 0.0910 dl1.repl_rate 0.0043 dl1.wb_rate 0.0021 dl1.inv_rate 0.0000 dl2.accesses 482 dl2.hits 15 dl2.misses 467 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9689 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 82 mem.page_mem 656k

# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #

total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if

# total number of pages allocated # total size of memory pages allocated

mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/perl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl>

<name> <nsets> <bsize> <assoc> <repl> Examples:

name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14196 # total number of hits il1.misses 722 # total number of misses il1.replacements 106 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0484 # miss rate (i.e., misses/ref) il1.repl_rate 0.0071 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 722 # total number of accesses il2.hits 35 # total number of hits il2.misses 687 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9515 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4700 # total number of hits dl1.misses 473 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 6 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0914 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0043 # replacement rate (i.e., repls/ref)

dl1.wb_rate 0.0012 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 479 # total number of accesses dl2.hits 12 # total number of hits dl2.misses 467 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9749 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0042 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger

false false false false

-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14211 # total number of hits

il1.misses 707 # total number of misses il1.replacements 83 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0474 # miss rate (i.e., misses/ref) il1.repl_rate 0.0056 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4702 # total number of hits dl1.misses 471 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 11 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0910 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0021 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1189 # total number of accesses dl2.hits 35 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9706 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./

benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1):

-cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 il1.accesses 14918 il1.hits 14211 il1.misses 707 il1.replacements 83 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0474 il1.repl_rate 0.0056 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 5173 dl1.hits 4702 dl1.misses 471 dl1.replacements 22 dl1.writebacks 11 dl1.invalidations 0 dl1.miss_rate 0.0910 dl1.repl_rate 0.0043 dl1.wb_rate 0.0021 dl1.inv_rate 0.0000 dl2.accesses 1189 dl2.hits 35 dl2.misses 1154 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9706 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 82 mem.page_mem 656k mem.ptab_misses 146 mem.ptab_accesses 1245031 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total number of pages allocated size of memory pages allocated first level page table misses page table accesses

mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> - name of the cache being defined <nsets> - number of sets in the cache

<bsize> - block size of the cache <assoc> - associativity of the cache <repl> - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random Examples: -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14196 # total number of hits il1.misses 722 # total number of misses il1.replacements 106 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0484 # miss rate (i.e., misses/ref) il1.repl_rate 0.0071 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4700 # total number of hits dl1.misses 473 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 6 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0914 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0012 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1201 # total number of accesses dl2.hits 47 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9609 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2

-cache:il2 |none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

dl2 # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14211 # total number of hits il1.misses 707 # total number of misses il1.replacements 83 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0474 # miss rate (i.e., misses/ref) il1.repl_rate 0.0056 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4702 # total number of hits dl1.misses 471 # total number of misses dl1.replacements 22 # total number of replacements

dl1.writebacks 11 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0910 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0021 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1189 # total number of accesses dl2.hits 35 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9706 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file

# -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed

sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) il1.accesses 14918 # total number of accesses il1.hits 14211 # total number of hits il1.misses 707 # total number of misses il1.replacements 83 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0474 # miss rate (i.e., misses/ref) il1.repl_rate 0.0056 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 5173 # total number of accesses dl1.hits 4702 # total number of hits dl1.misses 471 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 11 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0910 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0043 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0021 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1189 # total number of accesses dl2.hits 35 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9706 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/perl.a lpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).

warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2):

-cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 il1.accesses 14918 il1.hits 14196 il1.misses 722 il1.replacements 106 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0484 il1.repl_rate 0.0071 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 5173 dl1.hits 4700 dl1.misses 473 dl1.replacements 22 dl1.writebacks 6 dl1.invalidations 0 dl1.miss_rate 0.0914 dl1.repl_rate 0.0043 dl1.wb_rate 0.0012 dl1.inv_rate 0.0000 dl2.accesses 1201 dl2.hits 47 dl2.misses 1154 dl2.replacements 2 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9609 dl2.repl_rate 0.0017 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if

mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:

<name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres

s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ

ivalents # -pcstat k)

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no

-cache:il2 |none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

none # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements

dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref)

dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger

false false false false

-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits

dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.

# -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics **

sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0017 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow:

sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...

sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.

All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache

hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 dl1.accesses 20091 dl1.hits 18921 dl1.misses 1170 dl1.replacements 88 dl1.writebacks 20 dl1.invalidations 0 dl1.miss_rate 0.0582 dl1.repl_rate 0.0044 dl1.wb_rate 0.0010 dl1.inv_rate 0.0000 dl2.accesses 1190 dl2.hits 36 dl2.misses 1154 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9697 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 82 mem.page_mem 656k mem.ptab_misses 146 mem.ptab_accesses 1245031 mem.ptab_miss_rate 0.0001 >>> # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total first number of pages allocated size of memory pages allocated first level page table misses page table accesses level page table miss rate

<<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache

<repl> Examples:

- block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 dl1.accesses 20091 dl1.hits 18921 dl1.misses 1170 dl1.replacements 88 dl1.writebacks 20 dl1.invalidations 0 dl1.miss_rate 0.0582 dl1.repl_rate 0.0044 dl1.wb_rate 0.0010 dl1.inv_rate 0.0000 dl2.accesses 1190 dl2.hits 36 dl2.misses 1154 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9697 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if

mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:

<name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres

s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ

ivalents # -pcstat k)

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0017 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no

-cache:il2 |none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

none # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements

dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref)

dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:38 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger

false false false false

-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits

dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.

# -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics **

sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow:

sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...

sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18921 # total number of hits dl1.misses 1170 # total number of misses dl1.replacements 88 # total number of replacements dl1.writebacks 20 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0582 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0044 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0010 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1190 # total number of accesses dl2.hits 36 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9697 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.

All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache

hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 dl1.accesses 20091 dl1.hits 18931 dl1.misses 1160 dl1.replacements 22 dl1.writebacks 2 dl1.invalidations 0 dl1.miss_rate 0.0577 dl1.repl_rate 0.0011 dl1.wb_rate 0.0001 dl1.inv_rate 0.0000 dl2.accesses 1162 dl2.hits 8 dl2.misses 1154 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9931 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 82 mem.page_mem 656k mem.ptab_misses 146 mem.ptab_accesses 1245031 mem.ptab_miss_rate 0.0001 >>> # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total first number of pages allocated size of memory pages allocated first level page table misses page table accesses level page table miss rate

<<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache

<repl> Examples:

- block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 dl1.accesses 20091 dl1.hits 18931 dl1.misses 1160 dl1.replacements 22 dl1.writebacks 2 dl1.invalidations 0 dl1.miss_rate 0.0577 dl1.repl_rate 0.0011 dl1.wb_rate 0.0001 dl1.inv_rate 0.0000 dl2.accesses 1162 dl2.hits 8 dl2.misses 1154 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9931 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if

mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:

<name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18931 # total number of hits dl1.misses 1160 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 2 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0577 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0011 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0001 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1162 # total number of accesses dl2.hits 8 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9931 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres

s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ

ivalents # -pcstat k)

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18931 # total number of hits dl1.misses 1160 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 2 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0577 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0011 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0001 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1162 # total number of accesses dl2.hits 8 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9931 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no

-cache:il2 |none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

none # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18931 # total number of hits dl1.misses 1160 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 2 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0577 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0011 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0001 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1162 # total number of accesses dl2.hits 8 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements

dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9931 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18931 # total number of hits dl1.misses 1160 # total number of misses dl1.replacements 22 # total number of replacements dl1.writebacks 2 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0577 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0011 # replacement rate (i.e., repls/ref)

dl1.wb_rate 0.0001 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1162 # total number of accesses dl2.hits 8 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 2 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9931 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0017 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger

false false false false

-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18930 # total number of hits

dl1.misses 1161 # total number of misses dl1.replacements 23 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0578 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0011 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0001 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1164 # total number of accesses dl2.hits 10 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9914 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.

# -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics **

sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18930 # total number of hits dl1.misses 1161 # total number of misses dl1.replacements 23 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0578 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0011 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0001 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1164 # total number of accesses dl2.hits 10 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9914 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow:

sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18930 # total number of hits dl1.misses 1161 # total number of misses dl1.replacements 23 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0578 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0011 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0001 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1164 # total number of accesses dl2.hits 10 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9914 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...

sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18930 # total number of hits dl1.misses 1161 # total number of misses dl1.replacements 23 # total number of replacements dl1.writebacks 3 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0578 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0011 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0001 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1164 # total number of accesses dl2.hits 10 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9914 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.

All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache

hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 dl1.accesses 20091 dl1.hits 18930 dl1.misses 1161 dl1.replacements 23 dl1.writebacks 3 dl1.invalidations 0 dl1.miss_rate 0.0578 dl1.repl_rate 0.0011 dl1.wb_rate 0.0001 dl1.inv_rate 0.0000 dl2.accesses 1164 dl2.hits 10 dl2.misses 1154 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9914 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 82 mem.page_mem 656k mem.ptab_misses 146 mem.ptab_accesses 1245031 mem.ptab_miss_rate 0.0001 >>> # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total first number of pages allocated size of memory pages allocated first level page table misses page table accesses level page table miss rate

<<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache

<repl> Examples:

- block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 sim_num_refs 5148 sim_elapsed_time 1 sim_inst_rate 14918.0000 dl1.accesses 20091 dl1.hits 18930 dl1.misses 1161 dl1.replacements 23 dl1.writebacks 3 dl1.invalidations 0 dl1.miss_rate 0.0578 dl1.repl_rate 0.0011 dl1.wb_rate 0.0001 dl1.inv_rate 0.0000 dl2.accesses 1164 dl2.hits 10 dl2.misses 1154 dl2.replacements 2 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9914 dl2.repl_rate 0.0017 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 532480 ld_data_base 0x0140000000 ld_data_size 119648 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120012c80 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if

mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:

<name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18906 # total number of hits dl1.misses 1185 # total number of misses dl1.replacements 103 # total number of replacements dl1.writebacks 19 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0590 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0051 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0009 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1204 # total number of accesses dl2.hits 50 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9585 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres

s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ

ivalents # -pcstat k)

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18906 # total number of hits dl1.misses 1185 # total number of misses dl1.replacements 103 # total number of replacements dl1.writebacks 19 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0590 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0051 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0009 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1204 # total number of accesses dl2.hits 50 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9585 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref)

ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no

-cache:il2 |none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

none # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18905 # total number of hits dl1.misses 1186 # total number of misses dl1.replacements 104 # total number of replacements dl1.writebacks 26 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0590 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0052 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0013 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1212 # total number of accesses dl2.hits 58 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements

dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9521 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18906 # total number of hits dl1.misses 1185 # total number of misses dl1.replacements 103 # total number of replacements dl1.writebacks 19 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0590 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0051 # replacement rate (i.e., repls/ref)

dl1.wb_rate 0.0009 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1204 # total number of accesses dl2.hits 50 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9585 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger

false false false false

-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 14918 # total number of instructions executed sim_num_refs 5148 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 14918.0000 # simulation speed (in insts/sec) dl1.accesses 20091 # total number of accesses dl1.hits 18906 # total number of hits

dl1.misses 1185 # total number of misses dl1.replacements 103 # total number of replacements dl1.writebacks 19 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0590 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0051 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0009 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1204 # total number of accesses dl2.hits 50 # total number of hits dl2.misses 1154 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9585 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 532480 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 119648 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120012c80 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 82 # total number of pages allocated mem.page_mem 656k # total size of memory pages allocated mem.ptab_misses 146 # total first level page table misses mem.ptab_accesses 1245031 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/pe rl.alpha -O ./benchmarks/1stmt.i>> Error is: <<<sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/perl.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:49:39 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.

# -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

sim: ** starting functional simulation w/ caches ** Unrecognized switch: -O. warning: partially supported sigprocmask() call... sim: ** simulation statistics **

sim_num_insn sim_num_refs sim_elapsed_time sim_inst_rate dl1.accesses dl1.hits dl1.misses dl1.replacements dl1.writebacks dl1.invalidations dl1.miss_rate dl1.repl_rate dl1.wb_rate dl1.inv_rate dl2.accesses dl2.hits dl2.misses dl2.replacements dl2.writebacks dl2.invalidations dl2.miss_rate dl2.repl_rate dl2.wb_rate dl2.inv_rate ld_text_base ld_text_size ld_data_base ld_data_size s' size in bytes ld_stack_base s in stack) ld_stack_size ld_prog_entry ld_environ_base ld_target_big_endian big endian mem.page_count mem.page_mem mem.ptab_misses mem.ptab_accesses mem.ptab_miss_rate >>> exit exit

14918 5148 1 14918.0000 20091 18905 1186 104 26 0 0.0590 0.0052 0.0013 0.0000 1212 58 1154 1 0 0 0.9521 0.0008 0.0000 0.0000 0x0120000000 532480 0x0140000000 119648

# # # # # # # # # # # # # # # # # # # # # # # # # # # #

total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs

0x011ff9b000 # program stack segment base (highest addres 16384 0x0120012c80 0x011ff97000 0 82 656k 146 1245031 0.0001 # # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total first number of pages allocated size of memory pages allocated first level page table misses page table accesses level page table miss rate

Script done on Tue 05 Mar 2013 10:51:26 AM CST