Introduction to CMOS VLSI Design

Design for Low Power

Outline
Power and Energy Dynamic Power Static Power Low Power Design

Design for Low Power

CMOS VLSI Design

Slide 2

Power and Energy

Power is drawn from a voltage source attached to the VDD pin(s) of a chip. Instantaneous Power: P(t ) = iDD (t )VDD Energy: Average Power:

E = P (t )dt = iDD (t )VDD dt

0 0

Pavg

E 1 = = iDD (t )VDD dt T T 0

Design for Low Power

CMOS VLSI Design

Slide 3

Dynamic Power
Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND VDD This repeats Tfsw times over an interval of T
fsw iDD(t)

Design for Low Power

CMOS VLSI Design

Slide 4

Dynamic Power Cont.

Pdynamic =

VDD iDD(t)

fsw

Design for Low Power

CMOS VLSI Design

Slide 5

Dynamic Power Cont.

Pdynamic 1 = iDD (t )VDD dt T 0 VDD = iDD (t )dt T 0 VDD = [ TfswCVDD ] T = CVDD 2 f sw
fsw VDD iDD(t)
T T

Design for Low Power

CMOS VLSI Design

Slide 6

Activity Factor
Suppose the system clock frequency = f Let fsw = f, where = activity factor If the signal is a clock, = 1 If the signal switches once per cycle, = Dynamic gates: Switch either 0 or 2 times per cycle, = Static gates: Depends on design, but typically = 0.1 Dynamic power: Design for Low Power

Pdynamic = CVDD 2 f
CMOS VLSI Design

Slide 7

Short Circuit Current

When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of short circuit current. < 10% of dynamic power if rise/fall times are comparable for input and output

Design for Low Power

CMOS VLSI Design

Slide 8

Example
200 Mtransistor chip 20M logic transistors Average width: 12 180M memory transistors Average width: 4 1.2 V 100 nm process Cg = 2 fF/m

Design for Low Power

CMOS VLSI Design

Slide 9

Dynamic Example
Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current.

Design for Low Power

CMOS VLSI Design

Slide 10

Dynamic Example
Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance.
Clogic = ( 20 106 ) ( 12 ) ( 0.05m / ) ( 2 fF / m ) = 24nF Pdynamic = 0.1Clogic + 0.05Cmem ( 1.2 ) f = 8.6 mW/MHz
2

Cmem = ( 180 106 ) ( 4 ) ( 0.05m / ) ( 2 fF / m ) = 72nF

Design for Low Power

CMOS VLSI Design

Slide 11

Static Power
Static power is consumed even when chip is quiescent. Ratioed circuits burn power in fight between ON transistors Leakage draws power from nominally OFF devices
Vgs Vt

I ds = I ds 0e

nvT

Vds vT 1 e

Vt = Vt 0 Vds +
Design for Low Power

s + Vsb s

)
Slide 12

CMOS VLSI Design

Ratio Example
The chip contains a 32 word x 48 bit ROM Uses pseudo-nMOS decoder and bitline pullups On average, one wordline and 24 bitlines are high Find static power drawn by the ROM = 75 A/V2 Vtp = -0.4V

Design for Low Power

CMOS VLSI Design

Slide 13

Ratio Example
The chip contains a 32 word x 48 bit ROM Uses pseudo-nMOS decoder and bitline pullups On average, one wordline and 24 bitlines are high Find static power drawn by the ROM = 75 A/V2 Vtp = -0.4V Solution:
I pull-up V ( =
DD

Vtp 2

= 24A

Ppull-up = VDD I pull-up = 29W Pstatic = (31 + 24) Ppull-up = 1.6 mW

Design for Low Power

CMOS VLSI Design

Slide 14

Leakage Example
The process has two threshold voltages and two oxide thicknesses. Subthreshold leakage: 20 nA/m for low Vt 0.02 nA/m for high Vt Gate leakage: 3 nA/m for thin oxide 0.002 nA/m for thick oxide Memories use low-leakage transistors everywhere Gates use low-leakage transistors on 80% of logic Design for Low Power
CMOS VLSI Design

Slide 15

Leakage Example Cont.

Estimate static power:

Design for Low Power

CMOS VLSI Design

Slide 16

Leakage Example Cont.

Estimate static power: High leakage: ( 20 106 ) ( 0.2 ) ( 12 ) ( 0.05m / ) = 2.4 106 m Low leakage: ( 20 106 ) ( 0.8) ( 12 ) ( 0.05m / ) + ( 180 106 ) ( 4 ) ( 0.05m / ) = 45.6 106 m
I static = ( 2.4 106 m ) ( 20nA / m ) / 2 + ( 3nA / m ) +
6

( 45.6 10 m ) ( 0.02nA / m ) / 2 + ( 0.002nA / m )

= 32mA Pstatic = I staticVDD = 38mW

Design for Low Power

CMOS VLSI Design

Slide 17

Leakage Example Cont.

Estimate static power: High leakage: ( 20 106 ) ( 0.2 ) ( 12 ) ( 0.05m / ) = 2.4 106 m Low leakage: ( 20 106 ) ( 0.8) ( 12 ) ( 0.05m / ) + ( 180 106 ) ( 4 ) ( 0.05m / ) = 45.6 106 m
I static = ( 2.4 106 m ) ( 20nA / m ) / 2 + ( 3nA / m ) +
6

( 45.6 10 m ) ( 0.02nA / m ) / 2 + ( 0.002nA / m )

= 32mA Pstatic = I staticVDD = 38mW

If no low leakage devices, Pstatic = 749 mW (!) Design for Low Power
CMOS VLSI Design

Slide 18

Low Power Design

Reduce dynamic power : C: VDD: f: Reduce static power

Design for Low Power

CMOS VLSI Design

Slide 19

Low Power Design

Reduce dynamic power : clock gating, sleep mode C: VDD: f: Reduce static power

Design for Low Power

CMOS VLSI Design

Slide 20

Low Power Design

Reduce dynamic power : clock gating, sleep mode C: small transistors (esp. on clock), short wires VDD: f: Reduce static power

Design for Low Power

CMOS VLSI Design

Slide 21

Low Power Design

Reduce dynamic power : clock gating, sleep mode C: small transistors (esp. on clock), short wires VDD: lowest suitable voltage f: Reduce static power

Design for Low Power

CMOS VLSI Design

Slide 22

Low Power Design

Reduce dynamic power : clock gating, sleep mode C: small transistors (esp. on clock), short wires VDD: lowest suitable voltage f: lowest suitable frequency Reduce static power

Design for Low Power

CMOS VLSI Design

Slide 23

Low Power Design

Reduce dynamic power : clock gating, sleep mode C: small transistors (esp. on clock), short wires VDD: lowest suitable voltage f: lowest suitable frequency Reduce static power Selectively use ratioed circuits Selectively use low Vt devices Leakage reduction: stacked devices, body bias, low temperature Design for Low Power
CMOS VLSI Design

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