Schematic Diagrams for Laptop Motherboard

Schematic Diagrams
Appendix B: Schematic Diagrams

This appendix has circuit diagrams of the W243HUQ/W244HUQ notebooks PCBs. The fo llowing table indicates
where to find the appropriate schematic diagram.
Diagram - Page
Diagram - Page
Diagram - Page
CougarPoint - M 6/9 - Page B - 19
Power 0.85VS - Page B - 36
CPU 1/7 (DMI, PEG, FDI) - Page B - 3
Power V-Core1 - Page B - 37
CPU 2/7 (CLK, MISC, JTAG) - Page B - 4
Power V-Core2 - Page B - 38
CPU 3/7 (DDR3) - Page B - 5
Charger, DC In - Page B - 39
CPU 4/7 (Power) - Page B - 6
New Card, Mini PCIE - Page B - 23
Click Board - Page B - 40
CPU 5/7 (Graphics Power) - Page B - 7
CCD, 3G, TPM - Page B - 24
Audio Board/USB - Page B - 41
CPU 6/7 (GND) - Page B - 8
Card Reader/LAN JMC251C - Page B - 25
Power Switch & LID Board - Page B - 42
CPU 7/7 (RESERVED) - Page B - 9
LAN (JMC251C), SATA HDD, ODD - Page B - 26
DDR3 SO-DIMM_0 - Page B - 10
USB 2.0 Connector - Page B - 27
DDR3 SO-DIMM_1 - Page B - 11
KBC-ITE IT8518 - Page B - 28
LVDS, Inverter - Page B - 12
LED, MDC, BT - Page B - 29
HDMI, CRT - Page B - 13
Audio Codec ALC269 - Page B - 30
USB, Fan, TP, Multi-Conn - Page B - 31
5VS, 3VS, 1.05VS, 1.5VS_CPU - Page B - 32
VDD3, VDD5 - Page B - 33
Power 1.5V/0.75V/1.8VS - Page B - 34
Power 1.05VS - Page B - 35
Table B - 1
SCHEMATIC
DIAGRAMS
Version Note
The schematic diagrams in this chapter
are based upon version 6-7P-W24H5-002.
If your mainboard (or
other boards) are a later version, please
check with the Service
Center for updated diagrams (if required).
B - 1
HTTP://MYCOMP.SU/ - Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook
. . , , .
. . -, .(812)951-37-99, .8-921-951-37-99,ICQ:573812745, service@it-lux.ru
B.Schematic Diagrams
System Block Diagram - Page B - 2
Schematic Diagrams
System Block Diagram

CLICK BOARD
6 -7 1- W2 40 2-D 01
Huron River System Block Diagram
AUDIO BOARD
VDD3,VDD5
U SB +E AR PH ONE +E XT .M IC
6 -7 1- C4 50 8-D 03
POWER SWITCH BOARD
Sandy Bridge
P OW ER S WI TCH +H OT KE Y X 3
6 -7 1- E5 1Q S-D 02
37.5*37.5 mm
EXTERNAL ODD BOARD
PROCESSOR
E XT . OD D
6 -7 1- E5 1Q N-D 01
rPGA989/988
FDI
HD MI
Sheet 1 of 43
System Block
Diagram
0. 5" ~6 .5 "
Memory Termination
800/1067 MHz
DDR3 / 1.5V
DDRIII
SO-DIMM0
SYSTEM SMBUS
0 .1 "~1 3
DDRIII
SO-DIMM1
CR T CO NN EC TO R
T OU CH P AD
INTERNAL
GRAPHICS
S yn ap ti c
810602-1703
<8 "
INTERNAL
L VD S S WI TC H
GRAPHICS
S PI
CougarPoint
Platform
Controller
Hub (PCH)
MIC
IN
RJ-11
HP
OUT
INT SPK R
AZALIA
MDC
MODULE
25x25x0.6 mm
989 Balls FCBGA
128pins LQFP
14 *14*1 .6 mm
VCORE, 0.85VS
VGFX_CORE
<= 8"
32.768 KHz
EC
IT E 85 18 E
1.05VS, 1.05VS_VTT
AU DI O BO AR D
CR T S WI TC H
L CD C ON NE CT OR ,
1.5V,0.75VS(VTT_MEM)
1.8VS
DMI*4
<1 5"
CLICK BOARD
5V,3V,5VS,3VS,1.5VS,
1.5VS_CPU
Az al ia C od ec
VIA VT1802
INT SPK L
MD C CO N
33 MHz
INT MIC
LPC
0. 5" ~1 1"
I NT . K/ B
EC SMBUS
B IO S
S PI
AZALIA LINK
PCIE
TH ER MA L
SE NS OR
W 83 L7 71 AW G
S MA RT
F AN
S MA RT
B AT TE RY
SATA I/II 3.0Gb/s
100 MHz
24 MHz
<1 2"
32.768KHz
< 12 "
USB2.0
480 Mbps
Mi ni P CI E
S OC KE T
3 G CA RD
( US B9 )
1" ~1 6"
(Optional)
Mi ni P CI E
S OC KE T
WL AN
( US B2 )
JMICRO
JMC251 C
LAN
MH z
RJ-45
S AT A HD D
SA TA O DD
USB P OR T
(U SB 0)
U SB P OR T
(U SB 1)
US B PO RT
( US B9 )
C CD
(U SB 5)
CARD READER 25
7I N1
S OC KE T
A UD IO
B OA RD
B - 2 System Block Diagram

. . , , .
Schematic Diagrams
CPU 1/7 (DMI, PEG, FDI)

Sandy Bridge Processor 1/7
( DMI,PEG,FDI )
1 .0 5V S _V TT
U 3 4A
D
D
D
D
MI_ T X P 0
MI_ T X P 1
MI_ T X P 2
MI_ T X P 3
[
[
[
[
15 ]
15 ]
15 ]
15 ]
D
D
D
D
MI_ R
MI_ R
MI_ R
MI_ R
XN
XN
XN
XN
0
1
2
3
[
[
[
[
15 ]
15 ]
15 ]
15 ]
D
D
D
D
MI_ R
MI_ R
MI_ R
MI_ R
XP
XP
XP
XP
0
1
2
3
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
FD
FD
FD
FD
FD
FD
FD
FD
I_T X N
I_T X N
I_T X N
I_T X N
I_T X N
I_T X N
I_T X N
I_T X N
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
[1 5 ]
FD
FD
FD
FD
FD
FD
FD
FD
I_T X P 0
I_T X P 1
I_T X P 2
I_T X P 3
I_T X P 4
I_T X P 5
I_T X P 6
I_T X P 7
B2 8
B2 6
A2 4
B2 3
G2 1
E2 2
F21
D2 1
G2 2
D2 2
F20
C2 1
A2 1
H1 9
E1 9
F18
B2 1
C2 0
D1 8
E1 7
0
1
2
3
4
5
6
7
A2 2
G1 9
E2 0
G1 8
B2 0
C1 9
D1 9
F17
J18
J17
[1 5 ] F D I_ F S Y NC 0
[1 5 ] F D I_ F S Y NC 1
H2 0
[ 1 5 ] F DI _IN T
R 3 89
1 K_ 0 4
J19
H1 7
[1 5 ] F D I_ L S Y NC 0
[1 5 ] F D I_ L S Y NC 1
R3 9 0
24 .9 _ 1 %_ 0 4
MI_ RX # [0 ]
MI_ RX # [1 ]
MI_ RX # [2 ]
MI_ RX # [3 ]
D
D
D
D
MI_ RX [0 ]
MI_ RX [1 ]
MI_ RX [2 ]
MI_ RX [3 ]
D
D
D
D
MI_ T X# [0 ]
MI_ T X# [1 ]
MI_ T X# [2 ]
MI_ T X# [3 ]
P E G_ IC OM P I
P E G_ I CO MP O
P E G _R CO MP O
D MI_ T X[ 0]
D MI_ T X[ 1]
D MI_ T X[ 2]
D MI_ T X[ 3]
FD
FD
FD
FD
FD
FD
FD
FD
I0 _T X # [0 ]
I0 _T X # [1 ]
I0 _T X # [2 ]
I0 _T X # [3 ]
I1 _T X # [0 ]
I1 _T X # [1 ]
I1 _T X # [2 ]
I1 _T X # [3 ]
FD
FD
FD
FD
FD
FD
FD
FD
I0 _T X [0 ]
I0 _T X [1 ]
I0 _T X [2 ]
I0 _T X [3 ]
I1 _T X [0 ]
I1 _T X [1 ]
I1 _T X [2 ]
I1 _T X [3 ]
F D I0 _F S Y N C
F D I1 _F S Y N C
F D I_ INT
F D I0 _L S Y N C
F D I1 _L S Y N C
EDP Function Disable

EDP_HPD: Pull-up10K- DISABLED
E DP _ C OM P A 1 8
A1 7
E DP _ H P D # B 1 6
DP Compensation Signal
PQ 4 7
* MT N7 0 0 2 Z H S 3
G
S
[1 1] DP _ A U XP
[1 1] DP _ A U XN
C3 2 5
C3 2 4
*0 . 1 u _1 0 V _ X 7R _ 04
*0 . 1 u _1 0 V _ X 7R _ 04
D P _ A U X_ P C 1 5
D P _ A U X_ N D 1 5
e D P _ C OM P IO
e D P _ IC OM P O
e D P _ H P D#
e DP_ AU X
e DP_ AU X#
R3 8 8
*1 0 0 K _ 04
[1 1]
[1 1]
[1 1]
[1 1]
[1 1]
[1 1]
[1 1]
[1 1]
11/03
DP _ T X P 0
DP _ T X P 1
DP _ T X P 2
DP _ T X P 3
DP _ T X N0
DP _ T X N1
DP _ T X N2
DP _ T X N3
C3 3 0
C3 2 9
C3 2 7
C5 4 0
*0 . 1 u _1 0 V _ X 7R
*0 . 1 u _1 0 V _ X 7R
*0 . 1 u _1 0 V _ X 7R
*0 . 1 u _1 0 V _ X 7R
_ 04
_ 04
_ 04
_ 04
D
D
D
D
P _ T XP
P _ T XP
P _ T XP
P _ T XP
_0
_1
_2
_3
C1 7
F16
C1 6
G1 5
C3 3 1
C3 2 8
C3 2 6
C5 4 1
*0 . 1 u _1 0 V _ X 7R
*0 . 1 u _1 0 V _ X 7R
*0 . 1 u _1 0 V _ X 7R
*0 . 1 u _1 0 V _ X 7R
_ 04
_ 04
_ 04
_ 04
D
D
D
D
P _ T XN
P _ T XN
P _ T XN
P _ T XN
_0
_1
_2
_3
C1 8
E1 6
D1 6
F15
e D P _ T X [0 ]
e D P _ T X [1 ]
e D P _ T X [2 ]
e D P _ T X [3 ]
e D P _ T X # [0]
e D P _ T X # [1]
e D P _ T X # [2]
e D P _ T X # [3]
eDP
[1 1] E MB _ H P D
P E G_ R X # [ 0 ]
P E G_ R X # [ 1 ]
P E G_ R X # [ 2 ]
P E G_ R X # [ 3 ]
P E G_ R X # [ 4 ]
P E G_ R X # [ 5 ]
P E G_ R X # [ 6 ]
P E G_ R X # [ 7 ]
P E G_ R X # [ 8 ]
P E G_ R X # [ 9 ]
P E G_ R X# [1 0 ]
P E G_ R X# [1 1 ]
P E G_ R X# [1 2 ]
P E G_ R X# [1 3 ]
P E G_ R X# [1 4 ]
P E G_ R X# [1 5 ]
P E G_ RX [ 0 ]
P E G_ RX [ 1 ]
P E G_ RX [ 2 ]
P E G_ RX [ 3 ]
P E G_ RX [ 4 ]
P E G_ RX [ 5 ]
P E G_ RX [ 6 ]
P E G_ RX [ 7 ]
P E G_ RX [ 8 ]
P E G_ RX [ 9 ]
P E G_ R X [1 0 ]
P E G_ R X [1 1 ]
P E G_ R X [1 2 ]
P E G_ R X [1 3 ]
P E G_ R X [1 4 ]
P E G_ R X [1 5 ]
P E G _ TX # [ 0 ]
P E G _ TX # [ 1 ]
P E G _ TX # [ 2 ]
P E G _ TX # [ 3 ]
P E G _ TX # [ 4 ]
P E G _ TX # [ 5 ]
P E G _ TX # [ 6 ]
P E G _ TX # [ 7 ]
P E G _ TX # [ 8 ]
P E G _ TX # [ 9 ]
P E G_ T X# [1 0 ]
P E G_ T X# [1 1 ]
P E G_ T X# [1 2 ]
P E G_ T X# [1 3 ]
P E G_ T X# [1 4 ]
P E G_ T X# [1 5 ]
P E G _T X [ 0 ]
P E G _T X [ 1 ]
P E G _T X [ 2 ]
P E G _T X [ 3 ]
P E G _T X [ 4 ]
P E G _T X [ 5 ]
P E G _T X [ 6 ]
P E G _T X [ 7 ]
P E G _T X [ 8 ]
P E G _T X [ 9 ]
P E G _ TX [1 0 ]
P E G _ TX [1 1 ]
P E G _ TX [1 2 ]
P E G _ TX [1 3 ]
P E G _ TX [1 4 ]
P E G _ TX [1 5 ]
R6 3
2 4 .9_ 1 % _ 04
K3 3
M 35
L34
J35
J32
H 34
H 31
G 33
G 30
F35
E3 4
E3 2
D 33
D 31
B3 3
C 32
SC70-5 & SC70-3 Co-lay
Q1 7
5
G ND
NC
GN D
VC C
V O
1
2
3
*T MP 2 0
3 .3 V
J33
L35
K3 4
H 35
H 32
G 34
G 31
F33
F30
E3 5
E3 3
F32
D 34
E3 1
C 33
B3 2
M 29
M 32
M 31
L32
L29
K3 1
K2 8
J30
J28
H 29
G 27
E2 9
F27
D 28
F26
E2 5
M 28
M 33
M 30
L31
L28
K3 0
K2 7
J29
J27
H 28
G 28
E2 8
F28
D 27
E2 6
D 25
Q1 6
2
1
VC C
O UT
1: 2 (4 mi ls :8 mi ls )
T H E RM _ V OL T [2 7 ]
C9 9
C 10 0
3
0 .1 u_ 1 0 V _ X7 R _0 4
G ND
G 71 1 S T 9 U
0 .1 u _1 0 V _ X 7R _ 04
Sheet 2 of 43
CPU 1/7
(DMI, PEG, FDI)
3
9/20
EVT
PLACE NEAR U3
On Board CPU Thermal Sensor

3.3 V
Analog Thermal Sensor

C9 7
*0 .1 u_ 1 6 V _ Y 5 V _ 0 4
D +_ C P U
1
2
15 ]
15 ]
15 ]
15 ]
D
D
D
D
P E G_ C OM P
U 11
VD D
D+
TH E R M
AL ERT
DG ND
SD AT A
S CL K
4
6
R1 2 2
*1 0 m i _l 0 4
C RIT _ T E MP _ R E P # [1 8 ]
TS # _ D IMM 0_ 1 [9 ,1 0 ]
Q1 8
* 2N 3 9 04
D -_C P U
E
[
[
[
[
B2 7
B2 5
A2 5
B2 4
DMI
MI_ T X N 0
MI_ T X N 1
MI_ T X N 2
MI_ T X N 3
PCI EXPRESS* - GRAPHICS
1 . 0 5V S _ V TT
D
D
D
D
Intel(R) FDI
1 .05 V S _ V T T
15 ]
15 ]
15 ]
15 ]
20 mil
3
5
7
8
S M D _ C P U _ T HE R M [1 4 , 2 7 ]
S M C _ C P U _ T HE R M [1 4 , 2 7 ]
* W 8 3L 7 7 1 A W G
P Z 98 8 2 7- 36 4 B -0 1 F
[3 ,8 , 11 ,1 3 , 1 4, 15 , 1 7 ,1 8, 1 9 ,2 0 ,22 ,2 3 ,2 6 ,28 ,3 0 ,3 1,3 3 ,3 4 ,3 5] 3.3 V

[3 ,5, 18 , 1 9 ,2 0, 3 4 ,3 6 ] 1 .05 V S _V T T
CPU 1/7 (DMI, PEG, FDI) B - 3

. . , , .
CAD NOTE: DP_COMPIO and ICOMPO signals

should be shorted near balls and routed with
- typical impedance < 25 mohms
[
[
[
[
J22
J21
H 22
Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)

Processor Pullups/Pull downs
1 . 05 V S _ V T T

( CLK,MISC,JTAG )
PU/PD for JTAG signals

1. 0 5 V S _ V T T
P _ TM S
P _ TD I _ R
P _ P RE Q #
P _ TD O_ R
P _ TC L K
P _ TR S T #
H_ S N B _ IV B #
C 26
P RO C_ S E L E CT #
S K T OC C #
XD P _ D B R _R
AL 3 3
H _ C A TE R R #
H_ P E C I_ R
AN 3 3
P E CI
R4 1 7
[ 1 8 ] H _ T H R MT R I P #
5 6 _1 % _ 04
H _ P R OC H O T# _ D A L 3 2
P R O C H OT #
*1 0 mi l _ 04
AN 3 2
TH E R M T R I P #
[ 1 8] H _ C P U P W R G D
P M S Y S _ P W R GD _ B U F
R 60
*1 0 mi l _ 04
1 3 0_ 1 % _0 4
Buffered reset to CPU
P M_ S Y N C _R
AM 3 4
P M_ S Y N C
S M _ R C OMP [ 0]
S M _ R C OMP [ 1]
S M _ R C OMP [ 2]
H _ C P U P W R GD _ R A P 3 3
V D D P W R GO OD _ R
U N C OR E P W R GO OD
V8
S M_ D R A MP W R O K
B U F _C P U _ R S T# A R 3 3
RESE T #
7 5_ 1 % _0 4
R 1 04
11/ 04
43 _ 1 %_ 0 4
6
D
3 .3 VS
R5 3 0
1 0K _ 0 4
Q3 6 A
MT D N 7 0 02 Z H S 6 R
2 G
T CK
T MS
TR S T #
JTAG & BPM
R4 1 8
*1 0 mi l _ 04
C L K _ E XP _P
C L K _ E XP _N
A 16
A 15
DDR3 Compensation Signals
[ 14 ]
[ 1 4]
CL K _ DP _ P [1 4 ]
C L K _ D P _ N [ 14 ]
R8
C P U D R A MR S T #
AK1
A5
A4
S M_ R C O MP _ 0
S M_ R C O MP _ 1
S M_ R C O MP _ 2
AP2 9
AP2 7
X DP _ P R DY #
X D P _ P R E Q#
AR2 6
AR2 7
AP3 0
X DP _ T CL K
X D P _ T MS
X DP _ T RS T #
AR2 8
AP2 6
X DP _ T DI_ R
X D P _ T D O _R
S M _ R C OMP _0
R 41 3
1 4 0_ 1 % _ 04
S M _ R C OMP _1
R 38 2
2 5 . 5 _1 % _ 04
S M _ R C OMP _2
R 38 1
2 0 0_ 1 % _ 04
S3 circuit:- DRAM PWR GOOD logic
H _ T H R MT R I P #_ R
PWR MANAGEMENT
R4 1 9
[ 1 5 ] H _ P M _S Y N C
A 28
A 27
S M_ D R A MR S T #
P R DY #
PREQ #
R1 0 5
* 0. 1 u _ 10 V _ X 7 R _ 0 4
T DI
T DO
3 . 3V
R7 3
R 57
*2 0 0_ 1 % _0 4
A L3 5
X DP _ DB R_ R
[ 1 5]
P M_ D R A M_ P W R GD
A T2 8
AR2 9
AR3 0
A T3 0
AP3 2
AR3 1
A T3 1
AR3 2
XDP_ B PM
XDP_ B PM
XDP_ B PM
XDP_ B PM
XDP_ B PM
XDP_ B PM
XDP_ B PM
XDP_ B PM
A
C 3
P MS Y S _P W R G D _ B U F
*B A T5 4 A W G H
DBR #
# [ 0]
# [ 1]
# [ 2]
# [ 3]
# [ 4]
# [ 5]
# [ 6]
# [ 7]
1 0 K _ 04
D2 0
[ 1 5, 3 3 ] 1 . 8 V S _ P W R G D
BPM
BPM
BPM
BPM
BPM
BPM
BPM
BPM
1 .5 V _ CP U
10/28
R 58
0_ R
1_ R
2_ R
3_ R
4_ R
5_ R
6_ R
7_ R
* 39 _ 0 4
R5 9
0 _ 04
D
R4 0 5
H _ P R O C H OT #
If P RO CH OT # i s no t us ed, t he n it m ust
be t er mi na ted w it h a 68- O +- 5% p ul l-u p
re si st or t o 1 .0 5V S_ VT T .
D P L L _R E F _ S S C LK
DP L L _ RE F _ S S C L K #
DDR3
MISC
[ 3 6]
*1 0 mi l _ 04
THERMAL
R4 1 1
[ 1 8 , 27 ] H _ P E C I
B C LK
BC L K#
Q 10
[ 6 , 3 1, 3 3 , 3 4 ] S U S B
* MT N 7 0 0 2Z H S 3
S
3
P Z 98 8 2 7-3 6 4 B -0 1F
D
5 G
S
10/29
Q3 6 B
MT D N 7 0 02 Z H S 6 R
D
R 1 12
[ 17 , 2 3 ] P L T_ R S T #
C9 6
1 00 K _ 0 4
*6 8 p _5 0 V _ N P O _ 04
Q1 4
1 . 5V
*1 . 5K _1 % _ 04
G
[ 2 7 ] H _ P R OC H O T_ E C
R5 3 1
S3 circuit:- DRAM_RST# to memory

should be high during S3
H _ P R OC H OT #
MT N 70 0 2 Z H S 3
C 51 5
R 10 6
R4 7
*0 _0 4
R4 5
4 7 p_ 5 0 V _ N P O _0 4
*7 5 0_ 1 % _0 4
10/1
CAD Note: Capacitor
need to be placed
close to buffer output pin
R9 1
R9 0
1K _ 0 4
1 0 0 K _ 04
C P UD RA M RS T #
* 0 _0 4
Q8
MT N 70 0 2 Z H S 3
S
D
R 48
1K _0 4
D D R 3_ D R A M R S T # [ 9 , 10 ]
R4 6
[ 2 , 5 , 1 8, 1 9 , 2 0 , 34 , 3 6 ]
[6 ,3 1 ]
[ 6 , 8 , 9, 1 0 , 2 0, 2 6 , 2 8 , 31 , 3 3 ]
[ 2, 8 , 1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 6, 2 8 , 3 0, 3 1 , 3 3 , 34 , 3 5 ]
[ 9, 1 0 , 1 1 , 12 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8, 19 , 2 0 , 23 , 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0 , 31 , 3 6 ]
D R A M R S T _ C N TR L [ 8 , 14 ]
4 . 9 9K _ 1 % _0 4
CA T E RR #
1 .0 5 VS_ VT T
10 K _ 0 4
C 58 5
11/0 3
AN 3 4
Sheet 3 of 43
CPU 2/7
(CLK, MISC, JTAG)
R 41 2
TRA CE W ID TH 1 0MI L, L EN GT H < 50 0M IL S
[ 18 ] H _S N B _ I V B #
1 K_ 0 4
H _C P U P W R G D _ R
62 _ 0 4
U3 4 B
3 . 3V S
R 40 7
R 41 0
XD
XD
XD
XD
XD
XD
5 1 _ 04
5 1 _ 04
* 51 _ 0 4
5 1 _ 04
5 1 _ 04
5 1 _ 04
CLOCKS
41 6
10 8
10 9
41 5
41 4
95
MISC
R
R
R
R
R
R
H _P R O C H O T #
C2 2
0 . 0 47 u _ 10 V _ X 7R _ 04
1 . 05 V S _ V T T
1 . 5V _C P U
1 . 5V
3 . 3V
3 . 3V S
B - 4 CPU 2/7 (CLK, MISC, JTAG)

. . , , .
Schematic Diagrams
CPU 3/7 (DDR3)

Sandy Bridge Processor 3/7 ( DDR3 )
U34C
U34D
[9] M
_A_BS0
[9] M
_A_BS1
[9] M
_A_BS2
[9] M_A_CAS#
[9] M_A_RAS#
[ 9] M_A_WE#
AE10
AF10
V6
AE8
AD9
AF9
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]
SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
DDR SYSTEM MEMORY A
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
PZ98827-364B- 01F
AB6
AA6
V9
M_A_CLK_DDR0 [9]
M_A_CLK_DDR#0 [9]
M_A_CKE0 [9]
AA5
AB5
V10
[10] M
_B_DQ[63:0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_A_CLK_DDR1 [9]
M_A_CLK_DDR#1 [9]
M_A_CKE1 [9]
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
M_A_CS#0 [9]
M_A_CS#1 [9]
AH3
AG3
AG2
AH2
M_A_ODT0 [9]
M_A_ODT1 [9]
C4
G6
J3
M
6
AL6
AM8
AR12
AM15
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS#[7:0] [ 9]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS[7:0] [ 9]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A[15:0] [9]
[10] M_B_BS0
[10] M_B_BS1
[10] M_B_BS2
[ 10] M
_B_CAS#
[ 10] M
_B_RAS#
[10] M_B_WE#
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M
5
N4
N2
N1
M
4
N5
M
2
M
1
AM
5
AM
6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT
5
AT
6
AP6
AN8
AR6
AR5
AR9
AJ11
AT
8
AT
9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
R6
AA10
AB8
AB9
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CLK[2]
SB_CLK#[2]
SB_CKE[2]
SB_CLK[3]
SB_CLK#[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_M
A[0]
SB_M
A[1]
SB_M
A[2]
SB_M
A[3]
SB_M
A[4]
SB_M
A[5]
SB_M
A[6]
SB_M
A[7]
SB_M
A[8]
SB_M
A[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
AE2
AD2
R9
M
_B_CLK_DDR0 [10]
M
_B_CLK_DDR#0 [ 10]
M
_B_CKE0 [10]
AE1
AD1
R10
M
_B_CLK_DDR1 [10]
M
_B_CLK_DDR#1 [ 10]
M
_B_CKE1 [10]
AB2
AA2
T
9
AA1
AB1
T
10
AD3
AE3
AD6
AE6
Sheet 4 of 43
CPU 3/7
(DDR3)
M
_B_CS#0 [10]
M
_B_CS#1 [10]
AE4
AD4
AD5
AE5
M
_B_ODT0 [10]
M
_B_ODT1 [10]
D7
F3
K6
N3
AN5
AP9
AK12
AP15
M
_B_DQS#0
M
_B_DQS#1
M
_B_DQS#2
M
_B_DQS#3
M
_B_DQS#4
M
_B_DQS#5
M
_B_DQS#6
M
_B_DQS#7
M_B_DQS#[7:0] [10]
C7
G3
J6
M
3
AN6
AP8
AK11
AP14
M
_B_DQS0
M
_B_DQS1
M
_B_DQS2
M
_B_DQS3
M
_B_DQS4
M
_B_DQS5
M
_B_DQS6
M
_B_DQS7
M_B_DQS[7:0] [10]
AA8
T
7
R7
T
6
T
2
T
4
T
3
R2
T
5
R3
AB7
R1
T
1
AB10
R5
R4
M
_B_B0
M
_B_B1
M
_B_B2
M
_B_B3
M
_B_B4
M
_B_B5
M
_B_B6
M
_B_B7
M
_B_B8
M
_B_B9
M
_B_B10
M
_B_B11
M
_B_B12
M
_B_B13
M
_B_B14
M
_B_B15
M_B_B[ 15:0] [10]
PZ98827-364B-01F
CPU 3/7 (DDR3) B - 5

. . , , .
M
_A_DQ0
M
_A_DQ1
M
_A_DQ2
M
_A_DQ3
M
_A_DQ4
M
_A_DQ5
M
_A_DQ6
M
_A_DQ7
M
_A_DQ8
M
_A_DQ9
M
_A_DQ10
M
_A_DQ11
M
_A_DQ12
M
_A_DQ13
M
_A_DQ14
M
_A_DQ15
M
_A_DQ16
M
_A_DQ17
M
_A_DQ18
M
_A_DQ19
M
_A_DQ20
M
_A_DQ21
M
_A_DQ22
M
_A_DQ23
M
_A_DQ24
M
_A_DQ25
M
_A_DQ26
M
_A_DQ27
M
_A_DQ28
M
_A_DQ29
M
_A_DQ30
M
_A_DQ31
M
_A_DQ32
M
_A_DQ33
M
_A_DQ34
M
_A_DQ35
M
_A_DQ36
M
_A_DQ37
M
_A_DQ38
M
_A_DQ39
M
_A_DQ40
M
_A_DQ41
M
_A_DQ42
M
_A_DQ43
M
_A_DQ44
M
_A_DQ45
M
_A_DQ46
M
_A_DQ47
M
_A_DQ48
M
_A_DQ49
M
_A_DQ50
M
_A_DQ51
M
_A_DQ52
M
_A_DQ53
M
_A_DQ54
M
_A_DQ55
M
_A_DQ56
M
_A_DQ57
M
_A_DQ58
M
_A_DQ59
M
_A_DQ60
M
_A_DQ61
M
_A_DQ62
M
_A_DQ63
DDR SYSTEM MEMORY B
[ 9] M_A_DQ[63:0]
Schematic Diagrams
CPU 4/7 (Power)

POWER
U 34F
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 371
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 366
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 354
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 359
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 363
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 337
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 332
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 351
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 336
2 2u _ 6 . 3 V _ X 5 R _ 0 8
C 69
1 0u _ 6 . 3 V _ X 5 R _ 0 6
C 33
1 0u _ 6 . 3 V _ X 5 R _ 0 6
C 74
1 0u _ 6 . 3 V _ X 5 R _ 0 6
C 56
1 0u _ 6 . 3 V _ X 5 R _ 0 6
C 34
1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C OR E
C 53
1 0u _ 6 . 3 V _ X 5 R _ 0 6
C 362
*2 2 u _ 6. 3V _X 5 R _ 08
C 360
*2 2 u _ 6. 3V _X 5 R _ 08
C 334
*2 2 u _ 6. 3V _X 5 R _ 08
C 333
*2 2 u _ 6. 3V _X 5 R _ 08
C 356
*2 2 u _ 6. 3V _X 5 R _ 08
C 62
*1 0 u _ 6. 3V _X 5 R _ 06
C 72
*1 0 u _ 6. 3V _X 5 R _ 06
C 59
*1 0 u _ 6. 3V _X 5 R _ 06
C 66
*1 0 u _ 6. 3V _X 5 R _ 06
V C OR E
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
1 00
PEG AND DDR
Sheet 5 of 43
CPU 4/7
(Power)
C 353
1 .0 5 V S _ V T T
PROCESSOR UNCORE POWER

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V CC IO 1
V CC IO 2
V CC IO 3
V CC IO 4
V CC IO 5
V CC IO 6
V CC IO 7
V CC IO 8
V CC IO 9
V CC IO 1 0
V CC IO 1 1
V CC IO 1 2
V CC IO 1 3
V CC IO 1 4
V CC IO 1 5
V CC IO 1 6
V CC IO 1 7
V CC IO 1 8
V CC IO 1 9
V CC IO 2 0
V CC IO 2 1
V CC IO 2 2
V CC IO 2 3
V CC IO 2 4
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
8.5A
A H 13
A H 10
A G 10
A C 10
Y1 0
U1 0
P1 0
L10
J14
J13
J12
J11
H1 4
H1 2
H1 1
G1 4
G1 3
G1 2
F1 4
F1 3
F1 2
F1 1
E1 4
E1 2
V CC IO 4 0
C3 6 1
C3 5 7
C 365
C 398
C 350
22 u _ 6 . 3 V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X 5R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
C4 0 2
+
22 0 u _ 6 . 3 V _ 6 . 3 *6 . 3 *4 . 2
C3 5 5
C3 4 4
C 364
C 358
C 346
*2 2 u _6 . 3 V _ X 5 R _0 8
*2 2 u _6 . 3 V _ X 5 R _0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
2 2 u _ 6 . 3 V _ X5 R _ 0 8
C4 1 7
C3 9 6
C4 1 9
C 406
C 397
C 384
*2 2 u _6 . 3 V _ X 5 R _0 8
*2 2 u _6 . 3 V _ X 5 R _0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
2 2 u _ 6 . 3 V _ X5 R _ 0 8
C3 2 1
C4 1 8
C 375
C 383
C 382
*2 2 u _6 . 3 V _ X 5 R _0 8
*2 2 u _6 . 3 V _ X 5 R _0 8
2 2 u _ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X 5R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
C4 0 7
C3 7 2
C 352
C 367
C 385
*2 2 u _6 . 3 V _ X 5 R _0 8
22 u _ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X5 R _ 0 8
C3 8 1
C3 9 4
C 420
C 368
*2 2 u _6 . 3 V _ X 5 R _0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
+
22 0 u _ 6 . 3 V _ 6 . 3 *6 . 3 *4 . 2
E1 1
D1 4
D1 3
D1 2
D1 1
C1 4
C1 3
C1 2
C1 1
B1 4
B1 2
A1 4
A1 3
A1 2
A1 1
J23
*2 2 u _6 . 3 V _ X 5 R _0 8
+ V 1 .0 5 S _ V C CP _ F
R 62
* 2 0m i l _ 0 4
1 .0 5 V S _ V T T
CAD Note: H_CPU_SVIDALRT#_R,H_CPU_SVIDDAT_R

Place the PU resistors close to CPU
SVID Signals
1 .0 5 V S_ VT T
SVID
SV 48
V C OR E
A G3 5
A G3 4
A G3 3
A G3 2
A G3 1
A G3 0
A G2 9
A G2 8
A G2 7
A G2 6
AF3 5
AF3 4
AF3 3
AF3 2
AF3 1
AF3 0
AF2 9
AF2 8
AF2 7
AF2 6
A D3 5
A D3 4
A D3 3
A D3 2
A D3 1
A D3 0
A D2 9
A D2 8
A D2 7
A D2 6
A C3 5
A C3 4
A C3 3
A C3 2
A C3 1
A C3 0
A C2 9
A C2 8
A C2 7
A C2 6
AA3 5
AA3 4
AA3 3
AA3 2
AA3 1
AA3 0
AA2 9
AA2 8
AA2 7
AA2 6
Y3 5
Y3 4
Y3 3
Y3 2
Y3 1
Y3 0
Y2 9
Y2 8
Y2 7
Y2 6
V3 5
V3 4
V3 3
V3 2
V3 1
V3 0
V2 9
V2 8
V2 7
V2 6
U3 5
U3 4
U3 3
U3 2
U3 1
U3 0
U2 9
U2 8
U2 7
U2 6
R3 5
R3 4
R3 3
R3 2
R3 1
R3 0
R2 9
R2 8
R2 7
R2 6
P3 5
P3 4
P3 3
P3 2
P3 1
P3 0
P2 9
P2 8
P2 7
P2 6
VID AL ER T #
V ID S CL K
VI DSO U T
AJ 2 9
AJ 3 0
AJ 2 8
H _ C P U _ S V I D A L R T # _R
H _ CP U_ S V IDC L K _ R
H _ CP U_ S V IDD A T _ R
R 40 6
R 88
R 85
4 3 _ 1 % _0 4
0_04
0_04
H _C P U _ S V I D A L R T # [ 3 6 ]
H _C P U _ S V I D C L K [ 3 6]
H _C P U _ S V I D D A T [ 3 6]
H _ C P U _S V I D A L R T #
H _ C P U _S V I D C L K
H _ C P U _S V I D D A T _ R
R4 0 8
R8 9
R8 6
CAD Note: H_CPU_SVIDCLK_R

Place the PU
resistors close to VR
V C OR E _ V C C _ S E N S E [ 3 6 ]
V C OR E _ V S S _ S E N S E [ 3 6 ]
1 .0 5 V S _ V T T
SENSE LINES
ICCMAX Maximum Proces sor
48A
CORE SUPPLY
V CO RE
PROCES SOR CORE POWER
V C C_ S E N S E
V SS_ SEN SE
AJ 3 5
AJ 3 4
R 3 79
10_04
V C C I O_ S E N S E
V S S I O_ S E N S E
B1 0
A1 0
V C CIO _ S E N S E _ R
V S S I O_ S E N S E
R 3 84
*0 _ 0 4
V C CIO _ S E N S E
[ 34 ]
[ 3 6 , 37 ]
[ 2, 3 , 1 8 , 1 9 , 2 0 , 3 4 , 36 ]
V CO R E
1. 05 V S _ V T T
R 3 83
10_04
P Z 9 88 2 7 -3 6 4 B -0 1 F
B - 6 CPU 4/7 (Power)

. . , , .
7 5_ 1 % _ 0 4
*5 4 . 9 _ 1 % _0 4
1 30 _ 1 % _ 0 4
Schematic Diagrams
CPU 5/7 (Graphics Power)

( GRAPHICS POWER )
POWER
1 .5 V
U 3 4G
V G F X _ CO RE
2 2 u _6 . 3 V _ X 5R _ 0 8
2 2u _ 6 . 3 V _X 5 R _0 8
C 37 6
C3 7 4
C 3 17
C3 7 7
2 2 u _ 6. 3 V _ X 5 R _ 0 8
2 2 u_ 6 . 3 V _ X5 R _ 08
22 u _ 6 . 3V _X 5 R _ 0 8
2 2 u _6 . 3 V _ X 5R _ 0 8
2 2u _ 6 . 3 V _X 5 R _0 8
C 3 89
C 39 0
C3 2 2
C 3 18
C3 7 3
2 2 u _ 6. 3 V _ X 5 R _ 0 8
2 2 u_ 6 . 3 V _ X5 R _ 08
22 u _ 6 . 3V _X 5 R _ 0 8
* 22 u _ 6 . 3V _X 5 R _ 0 8
2 2u _ 6 . 3 V _X 5 R _0 8
C 3 15
+
C 31 4
+
* 3 30 U _2 . 5 V _ D 2_ D
5 6 0u _ 2 . 5 V _6 . 6 * 6. 6 * 5. 9
1 .8 V S
All VCCPLL = 1.2A

C 4 58
+
3 3 0 uF _2 . 5 V _ 9 m_ 6 . 3 *6
C3 1 6
C3 1 9
C 32 0
1 0 u_ 6 . 3 V _ X5 R _0 6
1u _ 6 . 3 V _X 5 R _0 4
1 u _ 6. 3 V _ X 5 R _ 0 4
B6
A6
A2
V C CP L L 1
V C CP L L 2
V C CP L L 3
AK3 5
AK3 4
V C C _ GT _ S E N S E [ 3 6]
V S S _ GT _ S E N S E [ 3 6 ]
Q1 5
*A O3 4 02 L
S
D
V _ S M _V R E F
1 K _ 1 % _0 4
V _ S M _ V RE F _ C NT
R1 1 4
*1 0 0K _1 % _ 04
11/03
C5 8 6
AL 1
SM _ VREF
R 11 7
V_ SM _ VREF R1 1 6
0 _0 4
1 K _ 1 % _0 4
1 1/03
*0 . 1 u _1 0 V _ X 7R _ 04
S U S B # [ 3, 3 1 , 3 3 , 34 ]
V _ S M _V R E F _ C N T
CAD Note: +V_SM_VREF should

have 10 mil trace width
1. 5 V _ C P U
VD DQ 1
VD DQ 2
VD DQ 3
VD DQ 4
VD DQ 5
VD DQ 6
VD DQ 7
VD DQ 8
VD DQ 9
V D D Q1 0
V D D Q1 1
V D D Q1 2
V D D Q1 3
V D D Q1 4
V D D Q1 5
AF7
AF4
AF1
A C7
A C4
A C1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
Sheet 6 of 43
CPU 5/7
(Graphics Power)
All VDDQ = 12A

+C 4 00
C6 3
C 65
C5 8
10 u _ 6 . 3V _X 5 R _ 0 6
1 0 u _6 . 3 V _ X 5R _ 0 6
1 0u _ 6 . 3 V _X 5 R _0 6
C7 1
C 60
C6 7
10 u _ 6 . 3V _X 5 R _ 0 6
1 0 u _6 . 3 V _ X 5R _ 0 6
1 0u _ 6 . 3 V _X 5 R _0 6
2 2 0 u _6 . 3 V _ 6 . 3* 6 . 3 *4 . 2
11/29
0. 8 5 V S
P Z 98 8 2 7-3 6 4 B -0 1 F
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
M2 7
M2 6
L 26
J 26
J 25
J 24
H2 6
H2 5
All VDDQ = 6A
C3 2 3
C 3 45
C2 8
P C1 6 7
+
10 u _ 6 . 3V _X 5 R _ 0 8
1 0 u _6 . 3 V _ X 5R _ 0 8
1 0u _ 6 . 3 V _X 5 R _0 6
* 3 30 u _ 2 . 5V _9 m _ 6. 3* 6
1 .5 V _ CP U
H2 3
V CCS A _ S E NS E
V C C S A _S E N S E
R5 3 2
F C _ C2 2
V C CS A _ V ID 1
C2 2
C2 4
V CC S A _ S E NS E [3 5 ]
* 0 _0 4
R3 9 3
V CC S A _ V ID0 [3 5 ]
*1 0 K _ 0 4
R 56
1 0K _0 4
V C C S A _ V I D 1 [ 35 ]
R3 8 6
1 0 K _0 4
[ 3 5]
[ 19 , 2 9 , 3 1]
[ 18 , 1 9 , 3 3]
[ 3 , 8 , 9 , 10 , 2 0 , 2 6, 28 , 3 1 , 3 3]
[ 3 , 3 1]
[ 3 7]
[ 3 , 9 , 1 0, 1 1 , 1 2 , 1 3, 1 4 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0 , 2 3, 2 4 , 2 5 , 27 , 2 8 , 2 9, 30 , 3 1 , 3 6]
0. 8 5 V S
1. 5 V S
1. 8 V S
1. 5 V
1. 5 V _ C P U
V GF X _ C O R E
3. 3 V S
CPU 5/7 (Graphics Power) B - 7

. . , , .
C 3 86
VA XG _ SENSE
V SSA XG _ SENSE
*2 2 u_ 6 . 3 V _ X 5R _ 08
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
VREF
2 2 u_ 6 . 3 V _ X5 R _ 08
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
DDR3 -1.5V RAILS
2 2 u _ 6. 3 V _ X 5 R _ 0 8
AT2 4
AT2 3
AT2 1
AT2 0
AT1 8
AT1 7
A R2 4
A R2 3
A R2 1
A R2 0
A R1 8
A R1 7
AP2 4
AP2 3
AP2 1
AP2 0
AP1 8
AP1 7
A N2 4
A N2 3
A N2 1
A N2 0
A N1 8
A N1 7
A M2 4
A M2 3
A M2 1
A M2 0
A M1 8
A M1 7
AL 2 4
AL 2 3
AL 2 1
AL 2 0
AL 1 8
AL 1 7
AK2 4
AK2 3
AK2 1
AK2 0
AK1 8
AK1 7
AJ 2 4
AJ 2 3
AJ 2 1
AJ 2 0
AJ 1 8
AJ 1 7
A H2 4
A H2 3
A H2 1
A H2 0
A H1 8
A H1 7
SA RAIL
C3 8 7
MISC
C 3 88
GRAPHICS
C3 6 9
1.8V RAIL
C 39 2
SENSE
LINES
R 11 9
All VAXG = 33A

C 3 91
Schematic Diagrams
CPU 6/7 (GND)

Sandy Bridge Processor 6/7 ( GND )
U34H
CAD Note: 0 ohm resistor

should be placed close
to CPU
Sheet 7 of 43
CPU 6/7 (GND)
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
PZ9882 7-364 B- 01F
U3 4I
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS1 00
VSS1 01
VSS1 02
VSS1 03
VSS1 04
VSS1 05
VSS1 06
VSS1 07
VSS1 08
VSS1 09
VSS1 10
VSS1 11
VSS1 12
VSS1 13
VSS1 14
VSS1 15
VSS1 16
VSS1 17
VSS1 18
VSS1 19
VSS1 20
VSS1 21
VSS1 22
VSS1 23
VSS1 24
VSS1 25
VSS1 26
VSS1 27
VSS1 28
VSS1 29
VSS1 30
VSS1 31
VSS1 32
VSS1 33
VSS1 34
VSS1 35
VSS1 36
VSS1 37
VSS1 38
VSS1 39
VSS1 40
VSS1 41
VSS1 42
VSS1 43
VSS1 44
VSS1 45
VSS1 46
VSS1 47
VSS1 48
VSS1 49
VSS1 50
VSS1 51
VSS1 52
VSS1 53
VSS1 54
VSS1 55
VSS1 56
VSS1 57
VSS1 58
VSS1 59
VSS1 60
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE3 5
AE3 4
AE3 3
AE3 2
AE3 1
AE3 0
AE2 9
AE2 8
AE2 7
AE2 6
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB3 5
AB3 4
AB3 3
AB3 2
AB3 1
AB3 0
AB2 9
AB2 8
AB2 7
AB2 6
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
VSS1 61
VSS1 62
VSS1 63
VSS1 64
VSS1 65
VSS1 66
VSS1 67
VSS1 68
VSS1 69
VSS1 70
VSS1 71
VSS1 72
VSS1 73
VSS1 74
VSS1 75
VSS1 76
VSS1 77
VSS1 78
VSS1 79
VSS1 80
VSS1 81
VSS1 82
VSS1 83
VSS1 84
VSS1 85
VSS1 86
VSS1 87
VSS1 88
VSS1 89
VSS1 90
VSS1 91
VSS1 92
VSS1 93
VSS1 94
VSS1 95
VSS1 96
VSS1 97
VSS1 98
VSS1 99
VSS2 00
VSS2 01
VSS2 02
VSS2 03
VSS2 04
VSS2 05
VSS2 06
VSS2 07
VSS2 08
VSS2 09
VSS2 10
VSS2 11
VSS2 12
VSS2 13
VSS2 14
VSS2 15
VSS2 16
VSS2 17
VSS2 18
VSS2 19
VSS2 20
VSS2 21
VSS2 22
VSS2 23
VSS2 24
VSS2 25
VSS2 26
VSS2 27
VSS2 28
VSS2 29
VSS2 30
VSS2 31
VSS2 32
VSS2 33
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
PZ98827- 364B-01 F
B - 8 CPU 6/7 (GND)

. . , , .
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
Schematic Diagrams
CPU 7/7 (RESERVED)

( RESERVED )
CFG Straps for Processor
U 34 E
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
CF G 2
1:(Default) Normal Operation; Lane #

definition matches socket pin map definition
0:Lane Reversed
R 11 1
CF G 0
CF G 2
CF G
CF G
CF G
CF G
*1 K _ 0 4
4
5
6
7
CF G 4
R 11 0
H_ CPU
H_ CPU
H_ CPU
H_ CPU
*1 K _ 0 4
_ RSV D
_ RSV D
_ RSV D
_ RSV D
1 AJ 3 1
2 AH3 1
3 AJ 3 3
4 AH3 3
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
CF G
R
R
R
R
R
[0 ]
[1 ]
[2 ]
[3 ]
[4 ]
[5 ]
[6 ]
[7 ]
[8 ]
[9 ]
[ 1 0]
[ 1 1]
[ 1 2]
[ 1 3]
[ 1 4]
[ 1 5]
[ 1 6]
[ 1 7]
SVD
SVD
SVD
SVD
SVD
28
29
30
31
32
R S V D 33
R S V D 34
R S V D 35
V A X G_ V A L _ S E N S E
V S S A X G_ V A L _ S E N S E
V C C _ V A L _S E N S E
VS S _ V AL _ S ENSE
R
R
R
R
SVD
SVD
SVD
SVD
37
38
39
40
R
R
R
R
R
SVD
SVD
SVD
SVD
SVD
41
42
43
44
45
R
R
R
R
R
SVD
SVD
SVD
SVD
SVD
46
47
48
49
50
L7
AG 7
AE7
AK2
W8
AT2 6
AM 3 3
AJ 2 7
T8
J16
H 16
G 16
Sheet 8 of 43
CPU 7/7
(RESERVED)
AR 3 5
AT3 4
AT3 3
AP3 5
AR 3 4
AJ 2 6
CF G 5
CF G 6
R 99
R 92
11:
10:
01:
00:
(Default) x16 - Device 1 functions 1 and 2 disabled

x8, x8 - Device 1 function 1 enabled ; function 2 disabled
Reserved - (Device 1 function 1 disabled ; function 2 enabled)
x8,x4,x4 - Device 1 functions 1 and 2 enabled
*1 K _ 0 4
*1 K _ 0 4
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
F25
F24
F23
D2 4
G2 5
G2 4
E2 3
D2 3
C3 0
A3 1
B3 0
B2 9
D3 0
B3 1
A3 0
C2 9
J20
B1 8
A1 9
CFG7
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
B3 4
A3 3
A3 4
B3 5
C 35
1 .5 V
R 40
R S V D 51
R S V D 52
AH 2 7
V C C_ DIE_ SE N S E
R3 8
V R E F _ C H _ A _ D I MM
R S V D 54
R S V D 55
RS V D 2 4
RS V D 2 5
V C C I O_ S E L
AN 3 5
AM 3 5
1K _ 1 % _ 04
MV R E F _ D Q _ D I M 0
D R A M R S T _ C N TR L
R S V D 56
R S V D 57
R S V D 58
[ 9]
10/29
1K _ 1 % _ 04
AT2
AT1
AR 1
D R A M R S T _ C N TR L [ 3, 14 ]
1 .5 V
R 44
* 0 _0 4
B1
*1 K _ 0 4
M V R E F _D Q_ D I MMA
R3 1
*1 K _ 0 4
RS V D 2 7
R 93
Q7
* A O3 4 0 2L
S
D
R3 9
J15
CF G 7
* 0 _0 4
AJ 3 2
AK3 2
R 28
KE Y
V R E F _ C H _ B _ D I MM
Q6
* A O3 4 0 2L
S
D M V R E F _ D Q_ D I M 1
1 K _ 1% _ 0 4
M V R E F _D Q_ D I MMB
[ 10 ]
10/29
R4 9
P Z 9 8 8 27 -3 6 4B - 01 F
10/29
3 .3 V
R 39 2
10 K _ 0 4
R 29
G
CFG[6:5]
RS V D 6
RS V D 7
PCIE Port Bifurcation Straps
RESERVED
RS V D 5
V R E F _ C H _A _ D IMM B 4
V R E F _ C H _B _ D IMM D 1
*1 K _ 0 4
R3 9 1
* 10 m i _l 0 4
1 K _ 1% _ 0 4
H _S N B _ I V B # _P W R C TR L
D R A M R S T _ C N TR L
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
[ 3 , 6 , 9, 1 0 , 2 0, 2 6 ,2 8 ,31 ,3 3 ] 1 . 5V
[ 2, 3 ,1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 6, 2 8 , 3 0, 3 1 ,3 3 ,34 ,3 5 ] 3 . 3V
CPU 7/7 (RESERVED) B - 9

. . , , .
Display Port Presence Strap

1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
AK2 8
AK2 9
AL 2 6
AL 2 7
AK2 6
AL 2 9
AL 3 0
A M3 1
A M3 2
A M3 0
A M2 8
A M2 6
AN2 8
AN3 1
AN2 6
A M2 7
AK3 1
AN2 9
Schematic Diagrams
DDR3 SO-DIMM_0
SO-DIMM A
[ 4]
J D I M M2 A
M_ A _ A [ 1 5 : 0]
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
[4 ] M _ A_ BS0
[4 ] M _ A_ BS1
[4 ] M _ A_ BS2
[4 ] M _ A_ CS # 0
[4 ] M _ A_ CS # 1
[ 4 ] M_ A _ C L K _ D D R 0
[ 4 ] M_ A _ C L K _ D D R #0
[ 4 ] M_ A _ C L K _ D D R 1
[ 4 ] M_ A _ C L K _ D D R #1
[4 ] M _ A_ CK E0
[4 ] M _ A_ CK E1
[ 4 ] M_ A _ C A S #
[ 4 ] M_ A _ R A S #
[ 4 ] M_ A _ W E #
Sheet 9 of 43
DDR3 SO-DIMM_0
CHANGE TO STANDARD
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
_ A_ A0
_ A_ A1
_ A_ A2
_ A_ A3
_ A_ A4
_ A_ A5
_ A_ A6
_ A_ A7
_ A_ A8
_ A_ A9
_ A _ A 10
_ A _ A 11
_ A _ A 12
_ A _ A 13
_ A _ A 14
_ A _ A 15
S A 0_ D I M0
S A 1_ D I M0
[ 10 , 1 4 ] S MB _C L K
[ 1 0 , 1 4 ] S MB _ D A T A
3 .3 V S
R N2
1 0 K _ 8P 4 R _0 4
1
8
S A 1 _D I M1
2
7
S A 0 _D I M1
3
6
S A 1 _D I M0
4
5
S A 0 _D I M0
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120
[ 4 ] M _ A _ OD T 0
[ 4 ] M _ A _ OD T 1
11
28
46
63
136
153
170
187
S A 1 _ D I M 1 [ 10 ]
S A 0 _ D I M 1 [ 10 ]
[ 4 ] M_ A _ D Q S [ 7 : 0 ]
[ 4 ] M _A _ D QS # [ 7 : 0 ]
M
M
M
M
M
M
M
M
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
S0
S1
S2
S3
S4
S5
S6
S7
12
29
47
64
137
154
171
188
M
M
M
M
M
M
M
M
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
_ A _ DQ
S #0
S #1
S #2
S #3
S #4
S #5
S #6
S #7
10
27
45
62
135
152
169
186
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1 0 /AP
A1 1
A 1 2 /B C#
A1 3
A1 4
A1 5
BA0
BA1
BA2
S0 #
S1 #
CK 0
CK 0 #
CK 1
CK 1 #
CK E 0
CK E 1
CA S #
RA S #
W E#
SA0
SA1
S CL
S DA
OD T 0
OD T 1
DM
DM
DM
DM
DM
DM
DM
DM
0
1
2
3
4
5
6
7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0
S1
S2
S3
S4
S5
S6
S7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0 #
S1 #
S2 #
S3 #
S4 #
S5 #
S6 #
S7 #
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
DQ 1 0
DQ 1 1
DQ 1 2
DQ 1 3
DQ 1 4
DQ 1 5
DQ 1 6
DQ 1 7
DQ 1 8
DQ 1 9
DQ 2 0
DQ 2 1
DQ 2 2
DQ 2 3
DQ 2 4
DQ 2 5
DQ 2 6
DQ 2 7
DQ 2 8
DQ 2 9
DQ 3 0
DQ 3 1
DQ 3 2
DQ 3 3
DQ 3 4
DQ 3 5
DQ 3 6
DQ 3 7
DQ 3 8
DQ 3 9
DQ 4 0
DQ 4 1
DQ 4 2
DQ 4 3
DQ 4 4
DQ 4 5
DQ 4 6
DQ 4 7
DQ 4 8
DQ 4 9
DQ 5 0
DQ 5 1
DQ 5 2
DQ 5 3
DQ 5 4
DQ 5 5
DQ 5 6
DQ 5 7
DQ 5 8
DQ 5 9
DQ 6 0
DQ 6 1
DQ 6 2
DQ 6 3
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
12 9
13 1
14 1
14 3
13 0
13 2
14 0
14 2
14 7
14 9
15 7
15 9
14 6
14 8
15 8
16 0
16 3
16 5
17 5
17 7
16 4
16 6
17 4
17 6
18 1
18 3
19 1
19 3
18 0
18 2
19 2
19 4
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
_ A_ DQ
M _ A _ D Q [ 63 : 0 ] [ 4 ]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
J D I MM 2B
1. 5V
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
3 .3 VS
20 mi ls
C 10 1
C1 0 2
1 u _6 . 3 V _ Y 5 V _ 0 4
0 . 1 u_ 1 6 V _ Y 5 V _ 04
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1 0
D1 1
D1 2
D1 3
D1 4
D1 5
D1 6
D1 7
D1 8
199
V D DS PD
3 .3 V S
R1 2 4
77
122
125
*1 0K _0 4
198
30
[ 2 , 1 0 ] T S # _D I MM 0 _1
[ 3 , 1 0 ] D D R 3 _ D R A MR S T #
C 24
C 23
1 u _6 . 3 V _ X 5R _ 04
0 . 1 u_ 1 0 V _ X5 R _0 4
[ 8 ] M V R E F _D Q_ D I MM A
R4 1
MV R E F _ D I M 0
C 92
C 91
CLOSE TO S O- DIMM _0
1. 5 V
R 94
1 K _ 1 %_ 0 4
MV R E F _ D I M 0
R1 0 3
1
126
N C1
N C2
N CT E ST
EVEN T#
R ESET#
V R E F _ DQ
V R E F _ CA
* 0_ 0 4
1 u _6 . 3 V _ X 5R _ 04
0 . 1 u_ 1 0 V _ X5 R _0 4
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS1 6
SS1 7
SS1 8
SS1 9
SS2 0
SS2 1
SS2 2
SS2 3
SS2 4
SS2 5
SS2 6
SS2 7
SS2 8
SS2 9
SS3 0
SS3 1
SS3 2
SS3 3
SS3 4
SS3 5
SS3 6
SS3 7
SS3 8
SS3 9
SS4 0
SS4 1
SS4 2
SS4 3
SS4 4
SS4 5
SS4 6
SS4 7
SS4 8
SS4 9
SS5 0
SS5 1
SS5 2
44
48
49
54
55
60
61
65
66
71
72
12 7
12 8
13 3
13 4
13 8
13 9
14 4
14 5
15 0
15 1
15 5
15 6
16 1
16 2
16 7
16 8
17 2
17 3
17 8
17 9
18 4
18 5
18 9
19 0
19 5
19 6
V T T _ ME M
VTT1
VTT2
G1
G2
20 3
20 4
GN D 1
GN D 2
D D R S K -2 0 40 1 -T R 5 B
1K _ 1 % _ 04
D D R S K -2 04 0 1 -T R 5 B
V T T _ ME M
C1 0 3
C1 0 5
C1 0 4
C 1 06
C 1 11
1 u_ 6 . 3 V _ X 5R _ 04
1 u_ 6 . 3 V _ X5 R _0 4
1u _ 6 . 3 V _X 5 R _ 0 4
1 u _ 6 . 3V _ X 5 R _ 0 4
1 0 u _6 . 3 V _ X 5R _ 06
1 .5 V
+ C3 4 7
C3 7 0
C 64
C5 7
C5 5
C6 1
C 40
C 70
C 84
C4 6
*2 2 0 u_ 4 V _ V _ A
1 0 u_ 1 0 V _ Y 5 V _ 08
1 0u _ 1 0 V _Y 5 V _ 08
1 0u _ 6 . 3V _X 5 R _ 0 6
1u _ 6 . 3V _X 5 R _ 0 4
1 u _ 6 . 3V _ X 5 R _ 0 4
1 u _ 6. 3 V _ X 5 R _ 0 4
1 u _6 . 3 V _ X 5R _ 04
1 u_ 6 . 3 V _ X5 R _ 04
5 6 0 u_ 2 . 5 V _ 6 . 6* 6 . 6* 5 . 9
[ 3 , 6, 8 , 1 0 , 2 0, 26 , 2 8 , 31 , 3 3 ] 1 . 5 V
[ 10 , 3 3 ] V T T _M E M
[ 3 , 1 0, 11 , 1 2 , 13 , 1 4 , 1 5, 16 , 1 7 , 18 , 1 9 , 2 0, 23 , 2 4 , 25 , 2 7 , 2 8, 29 , 3 0 , 31 , 3 6 ] 3 . 3 V S
[ 1 9 , 29 , 3 1 ] 1 . 5 V S
1 . 5V
C3 7
C8 6
C6 8
C 82
C 48
C 49
C5 1
C5 0
C5 2
C 47
0 . 1 u_ 1 0 V _ X5 R _0 4
0 . 1u _ 1 0V _X 5 R _ 0 4
0. 1 u _ 1 0V _ X 5 R _ 0 4
0 . 1 u _ 10 V _ X 5 R _ 0 4
0 . 1 u _1 0 V _ X 5R _ 04
0 . 1 u_ 1 0 V _ X5 R _0 4
0 . 1 u_ 1 0 V _ X5 R _0 4
0 . 1u _ 1 0V _X 5 R _ 0 4
0. 1 u _ 1 0V _ X 5 R _ 0 4
0 . 1 u _ 10 V _ X 5 R _ 0 4
B - 10 DDR3 SO-DIMM_0
. . , , .
Schematic Diagrams
DDR3 SO-DIMM_1
CHANGE TO STANDARD
SO-DIMM B
[ 4 ] M _ B _B [ 15 : 0 ]
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
_ B_ B0
_ B_ B1
_ B_ B2
_ B_ B3
_ B_ B4
_ B_ B5
_ B_ B6
_ B_ B7
_ B_ B8
_ B_ B9
_ B _ B 10
_ B _ B 11
_ B _ B 12
_ B _ B 13
_ B _ B 14
_ B _ B 15
R0
R# 0
R1
R# 1
SA 0 _ DIM 1
SA 1 _ DIM 1
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120
[ 4 ] M _B _ O D T 0
[ 4 ] M _B _ O D T 1
11
28
46
63
136
153
170
187
[ 4 ] M_ B _ D QS [ 7 : 0 ]
[ 4 ] M _B _D QS # [ 7 : 0 ]
M
M
M
M
M
M
M
M
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
0
1
2
3
4
5
6
7
12
29
47
64
137
154
171
188
M
M
M
M
M
M
M
M
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
_ B _ D QS
#0
#1
#2
#3
#4
#5
#6
#7
10
27
45
62
135
152
169
186
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 1 0/ A P
A1 1
A 1 2/ B C #
A1 3
A1 4
A1 5
BA0
BA1
BA2
S0 #
S1 #
CK0
CK0 #
CK1
CK1 #
CKE 0
CKE 1
CAS #
RAS #
W E#
SA0
SA1
S CL
S DA
OD T0
OD T1
DM
DM
DM
DM
DM
DM
DM
DM
0
1
2
3
4
5
6
7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0
S1
S2
S3
S4
S5
S6
S7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S 0#
S 1#
S 2#
S 3#
S 4#
S 5#
S 6#
S 7#
D Q0
D Q1
D Q2
D Q3
D Q4
D Q5
D Q6
D Q7
D Q8
D Q9
D Q1 0
D Q1 1
D Q1 2
D Q1 3
D Q1 4
D Q1 5
D Q1 6
D Q1 7
D Q1 8
D Q1 9
D Q2 0
D Q2 1
D Q2 2
D Q2 3
D Q2 4
D Q2 5
D Q2 6
D Q2 7
D Q2 8
D Q2 9
D Q3 0
D Q3 1
D Q3 2
D Q3 3
D Q3 4
D Q3 5
D Q3 6
D Q3 7
D Q3 8
D Q3 9
D Q4 0
D Q4 1
D Q4 2
D Q4 3
D Q4 4
D Q4 5
D Q4 6
D Q4 7
D Q4 8
D Q4 9
D Q5 0
D Q5 1
D Q5 2
D Q5 3
D Q5 4
D Q5 5
D Q5 6
D Q5 7
D Q5 8
D Q5 9
D Q6 0
D Q6 1
D Q6 2
D Q6 3
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
M_ B _ D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q1 0
Q1 1
Q1 2
Q1 3
Q1 4
Q1 5
Q1 6
Q1 7
Q1 8
Q1 9
Q2 0
Q2 1
Q2 2
Q2 3
Q2 4
Q2 5
Q2 6
Q2 7
Q2 8
Q2 9
Q3 0
Q3 1
Q3 2
Q3 3
Q3 4
Q3 5
Q3 6
Q3 7
Q3 8
Q3 9
Q4 0
Q4 1
Q4 2
Q4 3
Q4 4
Q4 5
Q4 6
Q4 7
Q4 8
Q4 9
Q5 0
Q5 1
Q5 2
Q5 3
Q5 4
Q5 5
Q5 6
Q5 7
Q5 8
Q5 9
Q6 0
Q6 1
Q6 2
Q6 3
M_ B _ D Q [ 6 3: 0 ] [ 4 ]
J D I M M1 B
1 . 5V
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
3. 3 V S
2 0 mil s
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
199
V DD S P D
C4 1 6
C4 1 5
1u _ 6 . 3V _Y 5 V _0 4
0 . 1u _ 1 6V _Y 5 V _0 4
[ 2 , 9 ] T S # _D I MM 0 _1
[ 3 , 9 ] D D R 3 _ D R A MR S T #
C2 6
C2 5
[ 8]
1 u _ 6. 3 V _ X 5 R _ 0 4
0 . 1 u _1 0 V _ X 5R _ 04
MV R E F _ D Q_ D I MM B
R 42
C LO SE TO SO -DI MM_ 1
R 97
1 .5 V
1 K _ 1% _ 0 4
MV R E F _ D I M 1
198
30
1
126
NC1
NC2
NCT E S T
E V E NT #
RES ET #
V RE F _ D Q
V RE F _ C A
* 0 _0 4
MV R E F _ D I M 1
C 89
C 88
77
122
125
1 u_ 6 . 3 V _ X5 R _0 4
0 . 1u _ 1 0V _X 5 R _ 0 4
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
VSS1 6
VSS1 7
VSS1 8
VSS1 9
VSS2 0
VSS2 1
VSS2 2
VSS2 3
VSS2 4
VSS2 5
VSS2 6
VSS2 7
VSS2 8
VSS2 9
VSS3 0
VSS3 1
VSS3 2
VSS3 3
VSS3 4
VSS3 5
VSS3 6
VSS3 7
VSS3 8
VSS3 9
VSS4 0
VSS4 1
VSS4 2
VSS4 3
VSS4 4
VSS4 5
VSS4 6
VSS4 7
VSS4 8
VSS4 9
VSS5 0
VSS5 1
VSS5 2
44
48
49
54
55
60
61
65
66
71
72
1 27
1 28
1 33
1 34
1 38
1 39
1 44
1 45
1 50
1 51
1 55
1 56
1 61
1 62
1 67
1 68
1 72
1 73
1 78
1 79
1 84
1 85
1 89
1 90
1 95
1 96
Sheet 10 of 43
DDR3 SO-DIMM_1
V TT _ ME M
VTT1
VTT2
G1
G2
2 03
2 04
GN D 1
GN D 2
D D R S K -2 0 4 01 -T R 9D
R 98
1 K _ 1% _ 0 4
D D R S K -20 4 0 1-T R 9D
La y out Note :
S O- DIMM_1 i s pla c ed fa rthe r from the G MC H t ha n S O- DIMM_0
V T T _ ME M
C1 1 0
C1 0 9
C 1 07
C1 0 8
C1 1 2
1 u_ 6 . 3 V _ X5 R _0 4
1u _ 6 . 3V _X 5 R _ 0 4
1 u _ 6. 3 V _ X 5 R _ 0 4
1 u _6 . 3 V _ X 5R _0 4
10 u _ 6 . 3V _ X 5 R _ 0 6
C3 7 9
C7 8
C 3 80
C4 4
C8 3
C 76
C 39
C7 3
1 0u _ 1 0V _Y 5 V _0 8
10 u _ 10 V _ Y 5V _ 0 8
1 0 u _1 0 V _ Y 5 V _ 0 8
1 u _6 . 3 V _ X 5R _0 4
1u _ 6 . 3 V _X 5 R _ 0 4
1 u _ 6. 3V _ X 5 R _ 0 4
1 u _6 . 3 V _ X 5R _ 04
1 u_ 6 . 3 V _ X5 R _0 4
C4 5
C4 2
C 41
C8 1
C3 6
C 85
C 35
C3 8
C7 5
C 43
0 . 1u _ 1 0 V _X 5 R _ 0 4
0. 1 u _ 10 V _ X 5 R _ 0 4
0 . 1 u _1 0 V _ X 5R _ 04
0 . 1 u_ 1 0 V _ X5 R _ 0 4
0. 1u _ 1 0V _ X 5 R _ 0 4
0 . 1 u _ 10 V _ X 5R _ 04
0 . 1 u_ 1 0 V _ X5 R _0 4
0 . 1u _ 1 0V _X 5 R _ 0 4
0. 1 u _ 10 V _ X 5 R _ 0 4
0 . 1 u _1 0 V _ X5 R _0 4
1 .5 V
[ 1 9 , 29 , 3 1 ]
[ 3, 6 , 8 , 9 , 2 0, 2 6 , 2 8 , 31 , 3 3 ]
[9 ,3 3 ]
[ 3 , 9 , 1 1, 1 2 , 1 3, 1 4 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0, 23 , 2 4 , 25 , 2 7 , 2 8, 2 9 , 3 0 , 31 , 3 6 ]
1 . 5V S
1 . 5V
V T T_ M E M
3 . 3V S
1 . 5V
DDR3 SO-DIMM_1 B - 11
. . , , .
[ 4 ] M _B _ B S 0
[ 4 ] M _B _ B S 1
[ 4 ] M _B _ B S 2
[ 4 ] M _B _ C S # 0
[ 4 ] M _B _ C S # 1
[ 4] M_ B _ C L K _ D D
[ 4] M_ B _ C L K _ D D
[ 4] M_ B _ C L K _ D D
[ 4] M_ B _ C L K _ D D
[ 4 ] M _B _ C K E 0
[ 4 ] M _B _ C K E 1
[ 4 ] M _ B _C A S #
[ 4 ] M _ B _R A S #
[ 4 ] M _ B _W E #
[ 9 ] S A 0_ D I M1
[ 9 ] S A 1_ D I M1
[ 9 , 1 4] S MB _ C L K
[ 9 , 14 ] S MB _ D A T A
J D I M M1 A
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
Schematic Diagrams
LVDS, Inverter
3 .3 V S
PANEL CONNECTOR
30Pin
J _L C D 2
L V D S -L1 N
L V D S -L1 P
L V D S -L0 N
L V D S -L0 P
G N B _E N A V D D
P _ DD C_ DA T A
P _ DD C_ CL K
PLVDD
HI LVDS:3.3V 3A
B R I GH T N E S S
HI eDP:3.3V 3A
LOW eDP;5V 3A
I N V _B L O N
PLVDD_SEL
HI ? 5V 3A
LOW ? 3.3V 3A
L V D S -L 2 N
L V D S -L 2 P
E M B _H P D
1A
3. 3 V S
3 .3 VS
3A
R5 7 9
3 .3 VS
Q 43
*A O 34 1 5
S
D
R5 8 0
C5 1 8
C 5 19
C 52 0
*1 0 0 K _0 4
R5 8 1
3A
Q 41
A O 34 1 5
S
D
>100 mil
C5 4 4
0 . 1 u _1 6 V _ Y 5 V _ 04
D
S
Q 45
*A O 34 1 5
S
D
3 3 0 K _0 4
Q 42
M T N 7 00 2 Z H S 3
L V D S -L 0 N
L V D S -L 0 P
[ 1 6] LV D S -L 0N
[ 1 6 ] L V D S -L 0 P
M U X _ 1N
M U X _ 1P
C5 4 5
S
P _ D D C _ D A TA [ 16 ]
P _ D D C _ C LK [ 1 6 ]
R 37 0
B R I GH TN E S S
Q4 9
*M TN 7 00 2 Z H S 3
1 0 0K _ 0 4
B R I G H T N E S S [ 27 ]
G
S
I N V _B L O N
L V D S -L 2 N
L V D S -L 2 P
L V D S -L2 N [ 16 ]
L V D S -L2 P [ 1 6 ]
E M B _H P D
1A
E MB _ H P D
11/0 3
[ 2]
3 .3 VS
3A
[ 16 ]
[1 6 ]
[1 6 ]
[1 6 ]
[ 16 ]
[1 6 ]
PL VD D
MU X _2 N
MU X _2 P
MU X _0 N
MU X _0 P
[2 ]
[2 ]
[2 ]
[2 ]
[2 ]
[2 ]
RN1 2 8
7
6
5
RN1 3 8
7
6
5
RN1 4 8
7
6
5
RN1 5 8
7
6
5
L V D S -U 2 N
LV D S -U 2 P
LV D S -U 1 N
LV D S -U 1 P
L V D S -U 0 N
LV D S -U 0 P
D P _ T XN 1
D P _ TX P 1
D P _ T XN 0
D P _ TX P 0
DP _ A UX N
D P _ A UXP
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
0 _ 8P 4 R _0 4
0 _ 8P 4 R _0 4
M
M
M
M
M
M
U X _ 2N
U X _ 2P
U X _ 1N
U X _ 1P
U X _ 0N
U X _ 0P
* 0_ 8 P 4 R _ 04
D P _ TX P 2 [ 2 ]
D P _ T XN 2 [ 2]
* 0_ 8 P 4 R _ 04
D P _ TX P 3 [ 2 ]
D P _ T XN 3 [ 2]
INVERTER CONNECTOR
3 .3 V
3. 3 V
3. 3 V
* 10 0 K _ 04
B K L _E N
B LO N
[ 2 7 ] B K L_ E N
U1 6 A
7 4L V C 08 P W
3
[ 1 6 ] B L ON
14
14
R2 6 8
U1 6 B
7 4L V C 08 P W
C 2 14
* 0 . 1u _ 10 V _ Y 5 V _ 0 4
4
6
14
1 0 0K _0 4
5
R2 6 7
R 6 08
[ 1 6 , 2 7] N B _ E N A V D D
P _ DD C_ DA T A
P _ DD C_ CL K
G2
G 1
[ 1 6 ] L V D S -U C L K N
[ 1 6 ] L V D S -U C L K P
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
G2
L V D S -L 1 N
L V D S -L 1 P
G1
L V D S -L C L K N
L V D S -L C L K P
[ 1 6 ] L V D S -L 1 N
[ 1 6 ] L V D S -L 1 P
1 00 K _ 0 4
R5 7 8
>100 mil
J _ L CD1
* 8 72 1 6-4 0 0 6
P L V D D _S E L
[ 1 6] L V D S -L C L K N
[ 1 6] L V D S -L C L K P
R2 4 4
5V S
VL ED
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
C5 4 3
R 5 77
Q4 4
*M T N 7 00 2 Z H S 3
40Pin
2A
P L V DD
>100mil
*1 0 0K _0 4
P L V D D _S E L
Sheet 11 of 43
LVDS, Inverter
3A
>100 mil
C 54 2
4 . 7 u _1 0 V _ Y 5 V _ 08
0. 1 u _ 16 V _ Y 5 V _ 0 4
0 . 1 u_ 1 6 V _Y 5V _0 4
11/3
0 _ 06
5 VS
PL VDD
8 7 21 6 -3 00 6
* 0. 1 u _ 50 V _ Y 5 V _ 0 6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
*1 00 K _ 0 4
Q4 8
MT N 7 0 02 Z H S 3
L V D S -LC LK N
L V D S -LC LK P
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
* 2 00 _ 1% _ 0 4
C5 1 7
0. 1 u _ 50 V _ Y 5 V _ 06
C 58 7
8
7
6
5
P 20 0 3 E V G
1 M_ 0 4
Q4 7
3
2
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2 . 2K _ 0 4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
PL VD D_ S EL
8
3. 3 V
I N V _ B LO N
10
U1 6 D
7 4L V C 08 P W
12
*1 0 0K _0 4
14
R 2 66
[ 2 7, 3 0 ] L I D _ S W #
U 1 6C
74 L V C 0 8 P W
[ 1 8] S B _B L O N
R2 8 0
C2 1 3
*1 M_ 0 4
0 . 1 u_ 1 6V _Y 5V _ 0 4
[ 1 2, 1 9 , 2 0, 2 5 , 2 9, 3 0 , 3 1, 3 6 , 3 7]
[ 3 0, 3 1 , 3 2, 3 3 , 3 4, 3 5 , 3 6, 3 7 , 3 8]
[ 2 , 3 , 8 , 13 , 1 4, 15 , 1 7, 1 8 , 1 9, 2 0 , 2 2, 2 3 , 2 6, 2 8 , 3 0, 3 1 , 3 3, 3 4 , 3 5]
[ 3, 9 , 1 0 , 12 , 1 3 , 14 , 1 5, 16 , 1 7, 1 8 , 1 9, 2 0 , 2 3, 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0, 3 1 , 3 6]
[ 3 1, 3 2 , 3 4]
11
13
[ 1 5, 2 7 , 3 6] A L L _ S Y S _ P W R GD
7
30Pin & 40 Pin Co-layout--LED

PANEL.
R9
1 0u _ 10 V _ Y 5 V _ 08
2A
2 . 2 K _0 4
0 . 1u _ 1 6V _ Y 5 V _ 0 4
2A
R 60 7
R1 0
VL ED
L2
* H C B 16 0 8 K F -1 21 T 25
0 . 1 u_ 1 6 V _Y 5 V _ 0 4
V IN
V IN
B - 12 LVDS, Inverter
. . , , .
5 VS
VI N
3 .3 V
3 .3 VS
S Y S 1 5V
Schematic Diagrams
HDMI, CRT
OE#
D C C _E N #
P C0
P C1
D C C _E N #
R T_E N#
3
4
6
4. 02 K _1% _0 4
R5 3
R5 1
32
10
PC 0
PC 1
R EX T
34
35
*4. 7 K_ 04
*4. 7 K_ 04
OE_ 1
QE_ 2
49
GN D
R 4 00
H D MI B _C L OC K P
H D MI B _C L OC K N
4. 7 K_ 04
D C C _E N #
4. 7 K_ 04
P C0
*4. 7 K_ 04
P C1
1 0u _1 0V _Y 5 V_ 08
10u _1 0V _Y 5 V _0 8
18
R 55
AC
RD1
HOT P LU G D E TE C T
D D C/ C E C GN D
S DA
14
C 3 39
0. 1 u_ 16V _ Y 5V _0 4
0. 1 u_ 16 V_ Y 5V _ 04
12
T MD S _C LO C K#
T MD S _C LO C K
10
8
C 31
C 3 40
0. 1 u_ 16V _ Y 5V _0 4
0. 1 u_ 16 V_ Y 5V _ 04
T MD S _D A TA 1#
T MD S _D A TA 1
HD MI _H PD -C
19
17
15
HD MI B _E XT 1_ S C L
13
HD MI _C EC
S CL
R E SE R V E D
3. 3V S
C 33 8
H D MI _ H PD-C
+5 V
16
10 0K _ 04
CE C
TMD S C LO C K-
CLK S H IE L D
TMD S C LO C K+
T MDS D A T A0 S H I EL D 0
TMD S D A TA 0+
TMD S D A TA 1S H I E LD 1
TMD S D A TA 1+
11
R 70
TM D S_ DA TA 0#
TM D S_ DA TA 0
TM D S_ DA TA 2#
TM D S_ DA TA 2
TMD S D A TA 2+
*0_ 04
4
3
L1 0
1
2
*W CM20 12 F2 S -SH OR T
R 69
*0_ 04
R 72
*0_ 04
4
3
L1 2
1
2
*W CM20 12 F2 S -SH OR T
R 71
*0_ 04
T MDS D A T A2 S H I EL D 2
C 30
0. 1 u_ 16V _ Y 5V _0 4
R 64
HD MI B_ D A TA 1N
*0_ 04
4
3
L9
1
2
*W C M20 12 F 2S -SH OR T
R 65
*0_ 04
R 66
*0_ 04
T MD S _C L OC K
4
3
L 11
1
2
*W C M20 12 F 2S -SH OR T
T MD S _D A TA 1
R 67
3. 3 V S
C 349
H D MI B _E X T1 _S D A
H D MI _ H PD -C
HD MI B_ D A TA 1P
CRT PORT
C 3 48
H D MI B _E X T1_ S C L
H D MI B _E X T1_ S D A
HD MI B_ C LOC K N
R 395
? ? ?
RD2
H D MI B _E X T1_ S D A
J_H D MI1
PS8101 (6-03-08101-032) PIN TO PIN
R 52
1 _0 4
H D MI B _D A T A0 P
H D MI B _D A T A0 N
HD MI B_ C LOC K P
R 54
5 VS _ H D MI _I N R 40 1
S N 75 D P 139
P I N 4 9= GN D
H D MI B _D A TA 0 N
H D MI B _D A TA 2 N
Sheet 12 of 43
HDMI, CRT
C 12 81 7-11 9A 5 -L
T MD S _C L OC K #
T MD S _D A TA 1 #
*0_ 04
5 VS
6-20-14X30-015
J_ C R T1
10 8A H 15 F ST 04 A 1C C
1
2
3
4
6-19-31001-264
RE D
10/29
1
9
V ID E O_ 3
0 . 22u _1 0V _Y 5 V_ 04
C 31 2
0. 22 u_ 10 V_ Y 5V _0 4
C 3 11
C 3 13
0. 2 2u _1 0V _Y 5V _ 04
BYP
TP D 7S 0 19
GN D
B LU E
GR N
RE D
10 p_5 0V _ N PO _ 04
10 p_ 50 V_ N P O _0 4
11
12
DDCDAT A
13
HS Y NC
14
V S Y NC
15
DDCL K
5
6
7
C 19
8
C 18
1 0p _50 V _N P O _0 4
C1 4
22p _5 0V _ N PO _ 04
22 p_ 50 V_ N P O _0 4
15 0_ 1% _04
1 50 _1 %_0 4
2 2p _5 0V _N P O _0 4
C2 0
C 16
VS Y NC
*10 p_ 50 V_ N P O _0 4
3 3_0 4
10
C 7 10 00 p_ 50 V_ X 7R _0 4
V ID E O_ 2
V CC_ DDC
R 37 3
24 mil
C 9 2 20 p_ 50 V_ N PO _04
V ID E O_ 1
V C C _ VI D E O
C R T_ V SY N C
2
GR N
B LU E
C 11 22 0p _50 V _N P O _0 4
16
FC M1 00 5MF -60 0T 01
FC M1 00 5MF -60 0T 01
FC M1 00 5MF -60 0T 01
C 1 5 1 000 p_ 50 V_ X 7R _ 04
V C C _ SY N C
2
3. 3V S
HS Y N C
L8
L5
L3
GN D1
GN D2
5V S
3 . 3V S
3 3_0 4
0_ 04
0_ 04
0_ 04
C 12
S Y N C _OU T 2
R 37 2
C 2 1 *1 0p _5 0V _N P O _ 04
S Y N C _ IN 2
S Y N C _OU T 1
C R T_ H S Y N C
C 1 7 * 10 p_5 0V _ N PO _ 04
[ 16 ] D A C _ VS Y N C
S Y N C _ IN 1
14
C 13
15
DD C L K
12
R 13
[ 16 ] D A C _HS Y N C
D D C _OU T 2
R1 4
13
DDC_ IN2
R 15
11
[ 16 ] D A C _D D C AC L K
D D C _OU T 1
DD C D A TA
150 _1 %_ 04
8
7
6
5
[ 16 ] D A C _D D C AD A TA
U 33
DDC_ IN1
.
.
.
10
L7
L6
L4
[ 16 ] D AC _ R E D
[ 16 ] D AC _ GR E EN
[ 16 ] D AC _ BL UE
RN1
2. 2 K _8P 4 R _0 4
.
.
.
3. 3V S
1_ 04
RD3
*B A V9 9 R E C TI F I E R
*B AV 9 9 R E C TI F I ER
*B A V 99 R EC T I FI E R
H D MI B _E X T1_ S C L
G ND
GND
GND
GND
3. 3 VS
H PD
25
*4. 7 K_ 04
*0_ 04
R 3 96
SC L
SD A
5V S _H D MI
[ 3, 9 ,1 0, 1 1, 13 , 14 , 15, 1 6, 1 7, 18 , 19 ,2 0, 2 3, 24 , 25 , 27, 2 8, 2 9, 30 , 31 ,3 6] 3. 3 VS
[ 1 1, 19 , 20 , 25, 2 9, 3 0, 31 , 36 ,3 7] 5V S
HDMI, CRT B - 13
. . , , .
10/28
9
8
M_P OR TB _ H PD # _R 7
* 10 mil _0 4
R6 1
R6 8
3 . 3V S
IN _ D 4+
IN _ D 4-
5V S
GND1
GND2
GND3
GND4
H D MI _C T RLC L K
H D MI _C T RLD A TA
[1 6] H D MI _C T R LC L K
[ 1 6] H D MI _C T R LD A TA
R 39 8
NI _ D 3+
IN _ D 3-
48
47
[ 1 6] H D MI B_ C LK B P
[ 1 6] H D MI B_ C LK B N
[ 16 ] POR T C _H P D
NI _ D 2+
IN _ D 2-
45
44
[ 1 6] H D MI B_ D 0B P
[ 1 6] H D MI B_ D 0B N
2. 2 K _04
42
41
[ 1 6] H D MI B_ D 1B P
[ 1 6] H D MI B_ D 1B N
22
OU T_D 1+ 23
OU T _D 1 19
OU T_D 2+ 20
OU T _D 2 16
OU T_D 3+ 17
OU T _D 3 13
OU T_D 4+ 14
OU T _D 4 28
S C L _S I N K 29
S D A _S I N K
30
H P D _S I N K
2
V C C [ 1 ] 11
V C C [ 2 ] 15
V C C [ 3 ] 21
V C C [ 4 ] 26
V C C [ 5 ] 33
V C C [ 6 ] 40
V C C [ 7 ] 46
V CC[8 ]
1
GN D [ 1 ] 5
GN D [ 2 ] 12
GN D [ 3 ] 18
GN D [ 4 ] 24
GN D [ 5 ] 27
GN D [ 6 ] 31
GN D [ 7 ] 36
GN D [ 8 ] 37
GN D [ 9 ] 43
GN D [ 10 ]
NI _ D 1+
IN _ D 1-
2. 2K _ 04
39
38
[ 1 6] H D MI B_ D 2B P
[ 1 6] H D MI B_ D 2B N
R 404
For ESD
R 4 03
U5
AC
FOR INTEL GRAPHIC
5 VS _ H D MI
AC
HDMI PORT
Schematic Diagrams
CougarPoint - M 1/9
RT C V CC
C4 6 8
1 8 p_ 5 0 V _ N P O _0 4
C4 6 5
J _R T C 1
1 u _6 . 3 V _ X5 R _0 6
JO P E N 1
C4 6 3
1 8 p_ 5 0 V _ N P O _0 4
*OP E N _ 1 0m i l -1M M
R T C_ V B A T 1
2
10mil
J_RTC1
R 4 78
C2 0 6
1 M _0 4
1 u _6 . 3 V _ X5 R _0 6
R2 3 5
R T CVC C
A2 0
RT C_ X 1
C2 0
R TC _ X2
3 3 0 K _0 4
R T C _ R S T#
D2 0
S R T C _ R S T#
G2 2
S M_ I N T R U D E R #
K2 2
P C H _I N T V R M E N
C1 7
RT CX 1
RT CX 2
RT CR S T #
INT RU DE R #
I N T V R ME N
1 K_ 0 4
H DA _ B IT CL K _ R
N3 4
H DA _ S Y N C_ R
L34
H DA _ RS T # _ R
K3 4
HD A _ RS T #
N O REB OO T ST RA P: HD A_ SP KR Hi gh E na bl e
HD A _ S DIN 0
C3 4
SPI_ SI
R2 6 9
3. 3 A _ 1 . 5 A _H D A _ I O
10/29
*1 K _ 04
A3 4
T PM FU NC TI ON :S PI_ SI H ig h Ena bl e
R 46 8
[ 2 7 ] M E _W E
* 28 m i l_ 0 6
11/05
R B 7 5 1S - 40 C 2
A
3. 3 V
Flash Descriptor Security Overide
D1 2
H DA _ S DO UT _ R
3. 3 V S
NC 1
HIGH = Enable
LOW = Disable
C3 6
R5 3 9
0_04
N3 2
3 .3 VS_ SPI
P C H _ J T A G_ T MS
H 7
P C H _ J T A G_ T D I
K5
R2 9 1
*3 . 3 K _ 1% _ 0 4
S P I _H OL D # 7
W P#
SPI_ SI
SPI_ SO
P C H _ J T A G_ T D O
S P I_ S CL K _ R
S P I_ S I_ R
S P I _ S O_ R
S P I_ CS 0 # _ R
R N 16
0_ 8 P 4 R _ 0 4
8
1
7
2
6
3
5
4
H S P I _ S C L K [ 2 7]
H S P I _ M S I [ 2 7]
HS P I_ M S O [2 7 ]
H S P I _ C E # [ 27 ]
R4 4 4
* 0 _0 4
S P I_ S CL K _ R T 3
S P I _ C S 0#
R1 7 6
* 0 _0 4
S P I _ C S 0 # _R Y 1 4
R1 7 8
* 0 _0 4
S A TA I C OM P O
R 2 30
LP C _ F R A M E # [ 23 , 2 7 ]
1 0 K_ 0 4
R2 2 9
*1 0 K _ 04
S E R I R Q [ 2 3 , 2 7]
A M3
A M1
AP7
AP5
S A TA
S A TA
S A TA
S A TA
RX N0
RX P 0
TX N 0
TX P 0
[2 5 ]
[ 2 5]
[2 5 ]
[2 5 ]
SATA HDD
A M1 0
A M8
AP1 1
AP1 0
A D7
A D5
A H5
A H4
S A T A RX N2 [2 5 ]
S A T A R X P 2 [ 2 5]
S A T A TX N 2 [ 2 5 ]
S A T A TX P 2 [ 2 5 ]
SATA ODD
AB8
AB1 0
AF3
AF1
Y7
Y5
A D3
A D1
Y3
Y1
AB3
AB1
Y1 1
S A T A I C OMP
R1 7 2
3 7. 4 _ 1 % _0 4
S A T A 3 C O MP
R1 7 1
4 9. 9 _ 1 % _0 4
R4 3 2
7 50 _ 1 %_ 0 4
1. 0 5 V S
Y1 0
S A T A I C O MP I
AB1 2
S P I_ CL K
1. 0 5 V S
S P I_ CS 1 #
T1
S P I_ S I_ R
V4
S P I _ S O_ R
U 3
S P I_ CS 0 #
R 4 41
*3 3 _ 04
A H1
R B IA S _ S A T A 3
P3
S A TA _L E D #
V1 4
G P I O 21
S A T A 3 RB IA S
S P I_ CS 0 #
S P I_ CS 1 #
S P I_ S O
S CK
SPI_ SCL K
4
H OL D #
J TA G _ TM S
H 1
S P I _ S C LK
S P I_ S I
CE #
J TA G _ TC K
J TA G _ TD I
LP C _ A D 0 [ 2 3 , 27 ]
LP C _ A D 1 [ 2 3 , 27 ]
LP C _ A D 2 [ 2 3 , 27 ]
LP C _ A D 3 [ 2 3 , 27 ]
AB1 3
SI
1 0K _0 4
S A T A 3 C O MP I
SO
3
1 0K _0 4
R 1 83
3 . 3V S
S A T A 3 R C OM P O
32Mbit
S AT A4 RXN
S A TA 4 R XP
S A T A 4T X N
S A T A 4 T XP
S AT A5 RXN
S A TA 5 R XP
S A T A 5T X N
S A T A 5 T XP
J3
J TA G _ TD O
SPI_* = 1.5"~6.5"
VD D
R2 9 4
*3 . 3 K _ 1% _ 0 4
S P I _W P #
H D A _ D OC K _ E N # / G P I O3 3
H D A _ D OC K _ R S T # / GP I O1 3
P C H _ J T A G_ T C K _ B U F
BIOS ROM
U 17
S AT A3 RXN
S A TA 3 R XP
S A T A 3T X N
S A T A 3 T XP
HD A _ S DO
* 1 0K _ 0 4
10/28
Flash Descriptor
Security Overide
Low = Disabled-(Default)
High = Enabled
*N C _ 0 4
C 22 1
* 0. 1 u _ 16 V _ Y 5V _ 0 4
HD A _ S DIN 3
A3 6
R5 3 8
[ 26 ] U S B 3 0_ S M I #
HDA_SDOUT
HD A _ S DIN 2
SATA
*1 K _ 0 4
HD A _ S DIN 1
IHDA
[ 28 ] H D A _ S D I N 1
iTPM ENABLE/DISABLE
R 16 7
S AT A1 RXN
S A TA 1 R XP
S A T A 1T X N
S A T A 1 T XP
S AT A2 RXN
S A TA 2 R XP
S A T A 2T X N
S A T A 2 T XP
G3 4
3. 3 V S
S AT A0 RXN
S A TA 0 R XP
S A T A 0T X N
S A T A 0 T XP
E3 4
[ 29 ] H D A _ S D I N 0
JTAG
Sheet 13 of 43
CougarPoint - M 1/9
SPKR
HD A _ S P K R
*1 K _ 0 4
R 1 68
G P I O2 1
B o a rd I D
V5
T10
H DA _ S P K R
E3 6
K3 6
S E RI RQ
HD A _ SYN C
[2 9 ] HD A _ S P K R
R 19 5
S E R IRQ
D3 6
L DRQ 0 #
L D R Q1 # / GP I O 2 3
SATA 6G
R2 2 4
3 . 3A _ 1 . 5 A _ H D A _I O
C3 8
A3 8
B3 7
C3 7
F W H 4 / LF R A M E #
HD A _ B CL K
NO REBOOT STRAP
3. 3 V S
F W H0 / L A D 0
F W H1 / L A D 1
F W H2 / L A D 2
F W H3 / L A D 3
S RT C RS T #
SPI
R 2 36
*1 0 K _ 0 4
U 3 7A
8 52 0 5 -02 7 0 1
1 2
S A T A _ L E D # R 4 45
1 0 M_ 0 4
Zo= 5 0O? 5%
R2 3 7
2 0K _1 % _ 04
3 .3 VS
X 12
X1 3
MC -30 6 _ 32 . 7 6 8K H z
LPC
R TC CL EA R
3
4
R4 7 7
2 0K _1 % _ 04
11 /05
1 K_ 0 4
2
1
1 u_ 6 . 3 V _ X5 R _0 6
*3 2 . 7 68 K H z
R 47 6
CougarPoint - M
(HDA,JTAG,SATA)
20mil
C 4 66
2
1
R T C_ V B A T _ 1
3
4
V DD 3
RTC
D 17
B A T5 4 C S 3
1 A
C 3
2 A
20mil
S P I _ MO S I
S A TA L E D #
S A TA 0 G P / GP I O 2 1
S P I _ MI S O
S A TA 1 G P / GP I O 1 9
P1
S A T A _ L E D# [2 8 ]
B B S _ B I T 0 [ 1 7]
C o u g ar P oi n t _ R e v _ 1p 0
VSS
* P C T 2 5 V F 0 32 B
P C B F oo t p ri nt = M -S OP 8B
10/29
3. 3 V
R 23 8
R 21 8
R 22 3
2 1 0_ 1 % _0 6
2 1 0_ 1 % _0 6
2 1 0_ 1 % _ 06
P C H _ J T A G_ T MS
P C H _ J T A G_ T D I
P C H _ J T A G_ T D O
R 45 9
10 0 _ 1% _ 0 4
R4 5 8
R 21 1
1 0 0_ 1 % _0 4
5 1 _0 4
R 20 9
R N1 7
* 3 3_ 8 P 4 R _ 0 4
8
1
7
2
6
3
5
4
[ 2 8 ] H D A _ S D O _M D C
[ 2 8 ] H D A _ S Y N C _ MD C
[ 2 8] H D A _R S T #_ M D C
[ 2 8 ] H D A _ B I T C L K _ MD C
11/04
H
H
H
H
D A _ S D OU T _ R
DA _ S Y NC_ R
D A _ R S T# _ R
DA _ B IT CL K _ R
4
3
2
1
5
6
7
8
H D A _ S D O U T [ 2 9]
H D A _ S Y N C [ 2 9]
H DA _ RS T # [2 9 ]
H D A _ B I TC L K [ 2 9]
33 _ 8 P 4R _ 04
R N1 8
[ 11 , 1 2 , 1 9, 2 0 , 2 5,
[ 2 2,
[ 2 , 3, 8, 1 1 , 1 4, 1 5 , 1 7 , 18 , 1 9 , 20 , 2 2 , 2 3, 2 6 , 2 8,
[ 3 , 9 , 10 , 1 1 , 1 2, 1 4 , 1 5, 1 6 , 1 7 , 18 , 1 9 , 20 , 2 3 , 2 4, 2 5 , 2 7,
[
[ 20 ] 3 . 3 A _ 1. 5 A _ H D A _ I O
[ 15 , 2 0 ] R T C V C C
29 , 3 0 , 31 , 3 6 , 3 7] 5 V S
24 , 2 7 , 31 , 3 2 , 3 8] V D D 3
30 , 3 1 , 33 , 3 4 , 3 5] 3 . 3 V
28 , 2 9 , 30 , 3 1 , 3 6] 3 . 3 V S
14 , 1 5 , 19 , 2 0 , 3 4] 1 . 0 5 V S
1 0 0_ 1 % _ 04
P C H _ J T A G_ T C K _ B U F
B - 14 CougarPoint - M 1/9
. . , , .
Schematic Diagrams
CougarPoint - M 2/9
3 .3 V
CougarPoint - M (PCI-E,SMBUS,CLK)
U 3 7B
B F 36
B E 36
A Y 34
B B 34
BG
BH
AY
BB
B J 38
B G 38
A U 36
A V 36
10 /2 9
PCI-E x1
1
2
3
4
5
6
7
8
B G 40
B J 40
A Y 40
B B 40
Usage
X
USB3.0
WLAN
GLAN / CARD READER
NEW CARD
X
X
X
BE
BC
AW
AY
P C I E C L K R Q0 #
P
P
P
P
E RN 6
E RP 6
E T N6
ETP6
P
P
P
P
D R A MR S T _ C N T R L
C 8
S ML 0 _ C L K
G 12
S ML 0 _ D A T A
SMBUS
S M L 0A LE R T # / GP I O6 0
M1
A A 48
A A 47
1 00 MHz
P E RN 8
P E RP 8
P E T N8
P ETP8
[ 2 2 ] C L K _P C I E _ M I N I #
[ 2 2] C L K _ P C I E _ MI N I
C 13
L P D_ S P I_ IN T R#
E1 4
S MC _ C P U _ T H E R M
M 16
S MD _ C P U _ T H E R M
M7
CL _ CL K 1
T11
C L _ D A TA 1
P1 0
C L _ R S T# 1
C L _D A T A 1
P E G _A _C L K R Q # / GP I O4 7
C L K O U T _ P E G_ A _ N
CL K O UT _ P E G _ A _ P
C L K OU T _D MI _ N
CL K O UT _ DM I_ P
P C I E C L K R Q 1 # / GP I O1 8
CL K O UT _ DP _ N
C LK O U T_ D P _ P
C L K OU T _ P C I E 2N
C L K OU T _ P C I E 2P
C L K I N _D MI _ N
CL KIN _ DM I_ P
P C I E C L K R Q 2 # / GP I O2 0
Y 43
Y 45
L A N _ C LK R E Q #
L 12
V 45
V 46
1 0/ 29
C L K I N _ G N D 1_ N
C L K I N _G N D 1 _ P
C LK I N _ D OT _ 96 N
C L K I N _D OT _ 9 6 P
C L K IN_ S A T A _ N
CL K IN _ S A T A _ P
P C I E C L K R Q 4 # / GP I O2 6
R 2 19
R 2 62
*1 0 K _ 04
*1 0 K _ 04
D G P U _ P R S N T#
R 5 43
R 4 63
R 1 69
*1 0 K _ 04
*1 0 K _ 04
*1 0 K _ 04
CL K _ B U
CL K _ B U
CL K _ B U
CL K _ B U
CL _ CL K1 [2 2 ]
P E G_ C L K R E Q #
CL K _ B U F _ RE F 1 4
LA N _ C L K R E Q #
10 0M Hz
C LK _E XP _N
C LK _E XP _P
AM 1 2
AM 1 3
C L K _ D P _ N _R
C L K _ DP _ P _ R
BF1 8
BE1 8
C L K _ P C I E _I C H #
C L K _ P C I E _I C H
BJ 3 0
BG 3 0
C L K _ BUF _ C PY C L K_ N
C L K _ BUF _ C PY C L K_ P
G 24
E2 4
C L K _ B U F _ D OT 9 6 _N
C L K _ B U F _ D OT 9 6 _P
R 154
R 150
1 0K _ 0 4
1 0K _ 0 4
1 0K _ 0 4
1 0K _ 0 4
R N1 9
1 0 K _ 8P 4R _ 0 4
8
1
7
2
6
3
5
4
R
R
R
R
2 12
1 75
2 08
2 39
Sheet 14 of 43
CougarPoint - M 2/9
*1 0 K _ 04
10 K _ 0 4
10 K _ 0 4
*1 0 K _ 04
[3 ]
[3 ]
1 20 M Hz
*1 0 m i _l 0 4
*1 0 m i _l 0 4
C L K _ D P _N
C L K _ D P _P
[3 ]
[3 ]
10 0M Hz
96 M Hz
1 00 M Hz
AK7
AK5
C L K_ SATA#
C L K_ SATA
K4 5
C L K _ BUF _ R EF 1 4
*X 8 A 0 25 0 0 0 F G1 H _2 5 M H z
C4 4 7
1 4.3 1 8M Hz
R 43 8
3 3M Hz
X1
C LK _P C I _ F B [ 17 ]
X T A L 2 5_ I N
X T A L 2 5_ O U T
Y 47
X C LK _R C O MP
V4 7
V4 9
22 p _ 5 0 V _N P O _0 4
X 11
X 8A 02 5 0 0 0F G1 H _ 2 5 MH z
2
X T A L 2 5_ I N
X T A L 25 _ OU T
R1 3 2
R1 3 4
R2 3 2
R2 4 0
CL K _ P C IE _ ICH
CL K _ P C IE _ ICH #
CL K _ S A T A #
CL K _ S A T A
C L _ R S T# 1 [ 2 2 ]
AV2 2
AU 2 2
C LK I N _ P C I L OO P B A C K
C L K OU T _ P E G_ B _ N
C L K OU T _ P E G_ B _ P
F _ CP Y CL K _ N
F _ CP Y CL K _ P
F _ D O T9 6 _ N
F _ D O T9 6 _ P
C L _ D A TA 1 [ 22 ]
H 45
P C I E C L K R Q 5 # / GP I O4 4
P E G _B _C L K R Q #
3G _ B _ C L K R Q#
AB3 7
AB3 8
R E F C LK 14 I N
L 14
A B 42
A B 40
10 K _ 0 4
10 K _ 0 4
*1 0 K _ 04
*1 0 K _ 04
*1 0 K _ 04
S M D _ C P U _ T H E R M [ 2 , 27 ]
CL _ RS T 1 #
P C I E C L K R Q 3 # / GP I O2 5
1 00 MHz
[ 2 4 ] C L K _ P C I E _ GL A N #
[ 2 4 ] C L K _ P C I E _G L A N
2 48
2 50
4 81
5 40
5 41
S M C _ C P U _ T H E R M [ 2 , 27 ]
A8
[ 2 2 ] W LA N _ C L K R E Q #
R
R
R
R
R
3 .3 V S
1 0/ 29
C L _C L K 1
DR A M RS T _ CN T RL [3 ,8 ]
S ML 1 D A TA / GP I O7 5
V 10
Y 37
Y 36
S M B _ DA T A [9 ,1 0 ]
B T _S B D #
LP D _ S P I _ I N T R #
P E G_ B _ C L K R Q #
S M L0 C L K
S M L1 C LK / GP I O5 8
E RN 7
E RP 7
E T N7
ETP7
J2
A B 49
A B 47
B T _ S B D # [ 2 2]
S M B _ CL K [9 ,1 0 ]
S M L0 D A T A
S M L1 A L E R T # / P C H H OT # / GP I O7 4
P C I E C L K R Q 0 # / GP I O7 3
[ 2 6 ] C LK _P C I E _ U S B 3 0 #
[2 6 ] CL K _ P C IE _ US B 3 0
O nly PC IECLKRQ [ 2:1 ]# on PCH a re core w e l l pow e re d.

Al l othe r PC IECLKRQ x # a re suspe nd w e ll pow e re d.
E RN 5
E RP 5
E T N5
ETP5
A1 2
M 10
Y 40
Y 39
[ 2 6 ] P C I E C LK R Q 2#
38
38
38
38
E RN 4
E RP 4
E T N4
ETP4
P
P
P
P
S MB _D A T A
SM BD ATA
1 M _ 04
C4 4 4
22 p _ 5 0 V _N P O _0 4
E6
P E G_ B _ C LK R Q # / GP I O 5 6
V 40
V 42
3 G_ B _ C L K R Q#
T 13
V 38
V 37
X C L K _ R C OM P
P C I E C L K R Q 6 # / GP I O4 5
9 0 . 9 _1 % _ 0 4
1 . 0 5V S
[ 2 , 3, 8, 1 1 , 1 3 , 1 5, 1 7 , 1 8 , 1 9, 20 , 2 2 , 2 3 , 26 , 2 8 , 3 0 , 31 , 3 3 , 3 4 , 35 ]
[ 3, 9, 1 0 , 1 1 , 1 2, 1 3 , 1 5 , 1 6, 1 7 , 1 8 , 1 9, 20 , 2 3 , 2 4 , 25 , 2 7 , 2 8 , 29 , 3 0 , 3 1 , 36 ]
[ 1 3 , 15 , 1 9 , 2 0 , 34 ]
3. 3 V
3. 3 V S
1. 0 5 V S
K4 3
K 12
P C I E C L K R Q 7 # / GP I O4 6
A K 14
A K 13
R4 3 7
90.9-O ? % pullup to +VccIO

(1.05V, S0 rail)close to
PCH
C L K OU T _ I T P XD P _ N
C L K OU T _ I T P XD P _ P
FLEX CLOCKS
Lane
Lane
Lane
Lane
Lane
Lane
Lane
Lane
37
37
36
36
E RN 2
E RP 2
E T N2
ETP2
P E RN 3
P E RP 3
P E T N3
P ETP3
P
P
P
P
S MB _C L K
C 9
2. 2 K _ 0 4
2. 2 K _ 0 4
1K _ 0 4
P C I E _ TX N 4_ C
P C I E _ TX P 4 _ C
H 14
S MB C L K
S MC _ C P U _ TH E R M R 2 49
S MD _ C P U _ TH E R M R 2 56
D R A MR S T _ C N TR L R 4 82
0 . 1 u _1 0 V _ X 7R _ 0 4
0 . 1 u _1 0 V _ X 7R _ 0 4
B T _S B D #
C 13 0
C 12 9
P C I E _ TX N 3_ C
B G 36
B J 36
A V 34
A U 34
P
P
P
P
S MB A LE R T # / GP I O1 1
E1 2
P C I E _ R X N 4_ G L A N
P C I E _ R X P 4 _ GL A N
P C I E _ T XN 4 _G L A N
P C I E _T X P 4 _ GL A N
0 . 1 u _1 0 V _ X 7R _ 0 4
0 . 1 u _1 0 V _ X 7R _ 0 4
34
34
32
32
E RN 1
E RP 1
E T N1
ETP1
_ 04
1
2
3
4
C L K O U T F L E X 0 / GP I O6 4
F47
H 47
K4 9
D GP U _ P R S N T #
C o u g arP oi n t _ R e v _ 1 p 0
CougarPoint - M 2/9 B - 15
. . , , .
[2 4 ]
[2 4 ]
[2 4 ]
[2 4 ]
C 14 2
C 14 3
P C I E _ TX N 2_ C
BE
BF
BB
AY
P
P
P
P
Link
[ 22 ] P C I E _ R XN 3 _ W L A N
[ 22 ] P C I E _ R XP 3_ W L A N
[ 22 ] P C I E _ T X N 3 _ W L A N
[ 2 2 ] P C I E _ T XP 3_ W L A N
0 . 1 u _1 0 V _ X 7R _ 0 4
0 . 1 u _1 0 V _ X 7R _ 0 4
B G 34
B J 34
A V 32
A U 32
Controller
C 13 1
C 13 2
E _ RX N1
E _ RX P 1
E _ TX N 1
E _ TX P 1
PCI-E*
[ 26 ] P C I E _ R XN 2 _ U S B 3 0
[ 26 ] P C I E _ R XP 2_ U S B 3 0
[ 2 6 ] P C I E _ T XN 2 _ U S B 3 0
[ 2 6 ] P C I E _ T XP 2_ U S B 3 0
PCI
PCI
PCI
PCI
CLOCKS
T 71
T 72
T 12
T 13
R N9
2 . 2 K _ 8P 4R
8
7
6
5
S MB _ C L K
S MB _ D A T A
S ML 0 _ D A T A
S ML 0 _ C L K
Schematic Diagrams
CougarPoint - M 3/9
CougarPoint -M (DMI,FDI,GPIO)
3. 3V
A C _ P RE S E NT
R 54 4
1 0K _0 4
P C IE _ W A K E #
R 48 6
1 0K _0 4
P M _ S L P _ LA N #
R 24 7
*1 0 K _ 0 4
S W I#
R 48 5
1 0K _0 4
P W R_ B T N#
R 25 2
*1 0 K _ 0 4
P M _ B A T L OW #
R 24 6
8 . 2 K _0 4
S U S _ P W R _A C K
R 48 3
1 0K _0 4
P M _ CL K R UN #
R 44 7
8 . 2 K _0 4
U3 7 C
[ 2]
[ 2]
[ 2]
[ 2]
2]
2]
2]
2]
_R
_R
_R
_R
BC 2 4
BE2 0
BG 1 8
BG 2 0
XN0
XN1
XN2
XN3
BE2 4
BC 2 0
BJ 1 8
BJ 2 0
D MI _R X P 0
D MI _R X P 1
D MI _R X P 2
D MI _R X P 3
D MI
D MI
D MI
D MI
DM
DM
DM
DM
AY
AY
AY
AU
[ 2 ] D MI _ T X P 0
[ 2 ] D MI _ T X P 1
[ 2 ] D MI _ T X P 2
[ 2 ] D MI _ T X P 3
F
F
F
F
F
F
F
F
DM I0 RX P
DM I1 RX P
DM I2 RX P
DM I3 RX P
AW 2 4
AW 2 0
BB1 8
AV1 8
_T X N 0
_T X N 1
_T X N 2
_T X N 3
I0 RX N
I1 RX N
I2 RX N
I3 RX N
DM
DM
DM
DM
24
20
18
18
I 0 TX N
I 1 TX N
I 2 TX N
I 3 TX N
D M I 0 TX P
D M I 1 TX P
D M I 2 TX P
D M I 3 TX P
DI_ RX N
DI_ RX N
DI_ RX N
DI_ RX N
DI_ RX N
DI_ RX N
DI_ RX N
DI_ RX N
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
XP
XP
XP
XP
XP
XP
XP
XP
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
B J 14
AY1 4
BE1 4
B H1 3
B C1 2
B J 12
B G1 0
B G9
B G1 4
BB1 4
BF1 4
B G1 3
BE1 2
B G1 2
B J 10
B H9
49 . 9 _ 1% _ 0 4
D M I _C OM P _ R
BJ 2 4
D M I _2 R B I A S
0
1
2
3
4
5
6
7
FD
FD
FD
FD
FD
FD
FD
FD
I _ TX P 0
I _ TX P 1
I _ TX P 2
I _ TX P 3
I _ TX P 4
I _ TX P 5
I _ TX P 6
I _ TX P 7
[
[
[
[
[
[
[
[
2]
2]
2]
2]
2]
2]
2]
2]
[2 ]
[2 ]
[2 ]
[2 ]
[2 ]
[2 ]
[2 ]
[2 ]
3. 3V S
F D I_ INT [2 ]
F DI_ F S Y NC 0
F D I_ F S Y N C0 [2 ]
R TC V C C
B C1 0
D M I _ I R C OM P
75 0 _ 1% _ 0 4
I _ TX N
I _ TX N
I _ TX N
I _ TX N
I _ TX N
I _ TX N
I _ TX N
I _ TX N
AV1 2
D M I _ Z C O MP
BG 2 5
R4 2 2
FD
FD
FD
FD
FD
FD
FD
FD
AW 1 6
F DI_ IN T
R4 2 3
1 . 0 5V S
BH 2 1
F DI_ F S Y NC 1
DM I2 RB IAS
F DI_ L S Y NC 0
F D I_ F S Y N C1 [2 ]
AV1 4
D S W O DV R E N
F D I _ LS Y N C 0 [ 2 ]
BB1 0
Sheet 15 of 43
CougarPoint - M 3/9
F D I _ LS Y N C 1 [ 2 ]
F DI_ L S Y NC 1
A1 8
D S W OD V R E N
E2 2
D P W RO K
B9
P C IE _ W A K E #
N3
P M _ CL K RU N#
R4 7 2
3 30 K _ 0 4
R4 7 9
*3 3 0 K _ 04
C 5 89
[ 27 ] P M_ P C H _ P W R OK
S USA CK #
1 0 K_ 0 4
S Y S _ RE S E T #
K3
S Y S _ P W RO K
P1 2
SYS_ R ESET #
S Y S_ P W RO K
*0 . 1 u _ 16 V _ Y 5V _0 4
R2 7 0
1 0 K _ 04
R2 1 3
*1 0 mi l _ 04
P M_ P C H _ P W R OK _ R
L22
P M_ MP W R O K
L10
P W R OK
A P W R OK
11/03
B1 3
[ 3 ] P M_ D R A M_ P W R G D
D R A MP W R O K
[ 27 ] R S MR S T #
[ 2 7]
C 12
System Power Management
DS W V RM E N
S U S _ P W R_ A C K
R 45 3
3. 3 V S
R 26 1
C 21
R S MR S T #
1 0K _0 4
S US _ P W R _ A CK
[2 7 ] P W R_ B T N#
S US _ P W R _ A CK
K1 6
P W R _ B T N#
E2 0
RS M RS T #
D P W R OK
W AKE #
A C_ PR E S ENT
H 20
P M_ B A T L OW #
E1 0
* 1 0m i l _0 4
DSWODVREN - On Die DSW VR Enable
R S MR S T #
HI Enabled (DEFAULT)
P C I E _W A K E # [ 2 2 , 24 , 2 6 ]
LOW Disabled
P M _ C L K R U N # [ 23 ]
S 4 _ S T A T E # [ 2 3]
N1 4
S U S CL K
D1 0
SL P_ S5 #
S L P _ S 5 # / GP I O 6 3
SL P_ S4 #
H4
S U S C # [ 27 , 3 3 ]
F4
SL P_ S3 #
S U S B # [ 2 6 , 2 7, 3 1 ]
G1 0
SL P_ A#
G1 6
SL P_ SU S#
S L P _A #
A C P R E S E N T / GP I O 3 1
S L P_ S US #
B A T L OW # / G P I O7 2
P MS Y N C H
AP1 4
A1 0
SW I#
[2 7 ] S W I#
G8
S U S C LK / GP I O 6 2
P W R B TN #
[ 17 , 2 7 ] A C _P R E S E N T
R2 5 7
C L K R U N # / GP I O 3 2
S U S _ S T A T # / GP I O 6 1
S U S W A R N # / S U S P W R D N A C K / GP I O3 0
H _ P M_ S Y N C
K1 4
RI#
[3 ]
P M _ S LP _L A N #
S LP _L A N # / GP I O 2 9
C o u g a rP oi n t _ R e v _ 1 p 0
3 .3 V
14
U 1 5D
7 4 L V C0 8 PW
12
[ 3 6] D E L A Y _P W R G D
1 1 S Y S _ P W R _O K
13
R 23 4
* 1 0m i l _0 4
S Y S _ P W R OK
[ 27 ] P M_ P C H _ P W R O K
3 .3 V
[ 35 ] 0 . 8 5 V S _ P W R GD
4
[ 3, 33 ] 1 . 8 V S _ P W R GD
3 DD R_ 1 .0 5 V S _ P W RG D
[ 1 1 , 27 , 3 6 ]
R 54 5
1 0 K _ 04
1 . 0 5 V S _ V T T _E N
R 27 8
ON
A L L _S Y S _ P W R GD
10
1 . 0 5 V S _ V T T_ E N
2
7
1. 0 5 V S _ P W R GD
DD R1 .5 V _ P W RG D
[ 3 4]
1 0 K _0 4
14
14
14
1
[ 3 3]
U 15 C
7 4 L V C0 8 P W
U 1 5B
7 4 L VC0 8 P W
U 15 A
7 4 LV C 0 8 P W
R2 5 3
7
3 .3 V
3 .3 V
[
[
[
[
D MI
D MI
D MI
D MI
FDI
2]
2]
2]
2]
DMI
[
[
[
[
*1 0 K _ 0 4
[3 4 ]
P M_ M P W R O K
[ 9 , 1 0 , 3 3]
[ 1 3 , 2 0]
[ 1 3 , 1 4, 19 , 2 0 , 3 4]
[ 2 , 3 , 8, 11 , 1 3 , 1 4, 1 7 , 1 8 , 19 , 2 0 , 2 2, 2 3 , 2 6 , 28 , 3 0 , 3 1, 33 , 3 4 , 3 5]
[ 3 , 9 , 10 , 1 1 , 1 2, 13 , 1 4 , 1 6, 1 7 , 1 8 , 19 , 2 0 , 2 3, 2 4 , 2 5 , 27 , 2 8 , 2 9, 30 , 3 1 , 3 6]
V TT _ ME M
RT CV C C
1. 0 5 V S
3. 3 V
3. 3 V S
. . , , .
Schematic Diagrams
CougarPoint - M 4/9
CougarPoint -M
(LVDS,DDI,CRT)
U3 7 D
L _ B K LT E N
L _ V D D_ E N
S D V O _ T V CL K I NN
S D V O_ T V C L K I N P
L _ B K LT C T L
S D V O_ S T A L L N
SD VO _ ST AL L P
P4 5
2 . 3 7K _ 1% _ 0 4
L V D S _ IB G
AF3 7
AF3 6
AE4 8
AE4 7
AK3 9
AK4 0
[ 1 1 ] LV D S - LC L K N
[ 1 1 ] L V D S -L C L K P
[ 1 1 ] L V D S -L 0 N
[ 1 1 ] L V D S -L 1 N
[ 1 1 ] L V D S -L 2 N
A N4 8
A M4 7
AK4 7
AJ 4 8
[ 1 1 ] L V D S -L 0 P
[ 1 1 ] L V D S -L 1 P
[ 1 1 ] L V D S -L 2 P
A N4 7
A M4 9
AK4 9
AJ 4 7
AF4 0
AF3 9
[ 1 1 ] L V D S -U C L K N
[ 1 1 ] L V D S -U C L K P
[ 12 ]
DAC _ B L U E
[ 12 ]
D A C _ GR E E N
[ 12 ]
DAC _ RE D
DA C_ B L U E
DA C_ G RE E N
* 3 3p _ 5 0 V _ N P O_ 0 4
DA C_ R E D
A H4 5
A H4 7
AF4 9
AF4 5
[ 1 1 ] L V D S -U 0 P
[ 1 1 ] L V D S -U 1 P
[ 1 1 ] L V D S -U 2 P
A H4 3
A H4 9
AF4 7
AF4 3
R2 0 0
R1 8 7
R1 9 2
C 196
* 3 3p _ 5 0 V _ N P O_ 0 4
[ 1 1 ] L V D S -U 0 N
[ 1 1 ] L V D S -U 1 N
[ 1 1 ] L V D S -U 2 N
1 5 0_ 1 % _ 0 4
1 5 0_ 1 % _ 0 4
1 5 0_ 1 % _ 0 4
DA C_ B L U E
DA C_ G RE E N
DA C_ R E D
N4 8
P4 9
T49
C 188
C 169
* 3 3p _ 5 0 V _ N P O_ 0 4
EMI
NEAR PCH
[ 12 ]
[ 12 ]
R1 6 5
T39
M4 0
[ 1 2 ] D A C _D D C A C L K
[1 2 ] D A C _ DD CA DA T A
M4 7
M4 9
DAC _ H S YN C
DAC _ V SY N C
1K _1 % _ 0 4
Connect to GND
DA C_ IR E F
T43
T42
S D V O _ INT N
S D V O_ I N T P
AP 3 9
AP 4 0
L _ C T RL _ CL K
L _ C T RL _ DA T A
L V D _ IBG
L VD _ VBG
S D V O_ C T R L C L K
S D V O _ C TR L D A T A
L VD _ VR EFH
L VD _ VR EFL
L VD SA_ C L K#
L VD SA_ C L K
L VD
L VD
L VD
L VD
SA_ D
SA_ D
SA_ D
SA_ D
ATA# 0
ATA# 1
ATA# 2
ATA# 3
L VD
L VD
L VD
L VD
SA_ D
SA_ D
SA_ D
SA_ D
ATA0
ATA1
ATA2
ATA3
D D P B _A U X N
D D PB_ AU XP
DD PB_ H PD
L VD SB_ C L K#
L VD SB_ C L K
L VD SB_ D ATA# 0
L VD SB_ D ATA# 1
L VD SB_ D ATA# 2
L VD SB_ D ATA# 3
L VD SB_ D ATA0
L VD SB_ D ATA1
L VD SB_ D ATA2
L VD SB_ D ATA3
C R T_ B L U E
C R T_ G R E E N
C R T_ R E D
C R T_ D D C _ C LK
C R T_ D D C _ D A T A
DD PB_ 0 N
D DP B_ 0 P
DD PB_ 1 N
D DP B_ 1 P
DD PB_ 2 N
D DP B_ 2 P
DD PB_ 3 N
D DP B_ 3 P
D DP C_ C T RL C L K
D D P C _ C TR L D A T A
D D P C _A U X N
D DP C _ A U X P
D D P C_ H P D
D D
DD
D D
DD
D D
DD
D D
DD
P C_ 0 N
PC _ 0 P
P C_ 1 N
PC _ 1 P
P C_ 2 N
PC _ 2 P
P C_ 3 N
PC _ 3 P
D DP D_ C T RL C L K
D D P D _ C TR L D A T A
C R T_ H S Y N C
C R T_ V S Y N C
D A C _ IRE F
C R T_ I R T N
D D P D _A U X N
D DP D _ A U X P
D D P D_ H P D
D D
DD
D D
DD
D D
DD
D D
DD
P D_ 0 N
PD _ 0 P
P D_ 1 N
PD _ 1 P
P D_ 2 N
PD _ 2 P
P D_ 3 N
PD _ 3 P
P3 8
M 39
AT4 9
AT4 7
AT4 0
AV
AV
AV
AV
AU
AU
AV
AV
42
40
45
46
48
47
47
49
R 271
R 272
2 . 2 K _0 4
2 . 2 K _0 4
3 .3 VS
P4 6
P4 2
Sheet 16 of 43
CougarPoint - M 4/9
H D M I _ C TR L C L K [ 1 2 ]
H D M I _ C TR L D A T A [ 1 2 ]
AP 4 7
AP 4 9
AT3 8
P C H_ D DP C_ H P D
AY
AY
AY
AY
BA
BA
BB
BB
H
H
H
H
H
H
H
H
47
49
43
45
47
48
47
49
SDVO
R1 7 0
T45
P3 9
Display Port B
L _ C T RL _ CL K
L _ C T RL _ DA T A
AM 4 2
AM 4 0
DM
DM
DM
DM
DM
DM
DM
DM
IB_ D
IB_ D
IB_ D
IB_ D
IB_ D
IB_ D
IB_ C
IB_ C
2B
2B
1B
1B
0B
0B
LK
LK
N_ C
P_ C
N_ C
P_ C
N_ C
P_ C
B N_ C
BP_ C
R1 5 3
C
C
C
C
C
C
C
C
140
141
124
125
126
127
137
138
*1 0 m i l _0 4
0 . 1 u _1 0 V _ X 7 R
0 . 1 u _1 0 V _ X 7 R
0 . 1 u _1 0 V _ X 7 R
0 . 1 u _1 0 V _ X 7 R
0 . 1 u _1 0 V _ X 7 R
0 . 1 u _1 0 V _ X 7 R
0 . 1 u _1 0 V _ X 7 R
0 . 1 u _1 0 V _ X 7 R
P O RT C _ HP D [1 2 ]
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
H
H
H
H
H
H
H
H
DM
DM
DM
DM
DM
DM
DM
DM
IB _ D
IB _ D
IB _ D
IB _ D
IB _ D
IB _ D
IB _ C
IB _ C
2 B N [1 2 ]
2 B P [1 2 ]
1 B N [1 2 ]
1 B P [1 2 ]
0 B N [1 2 ]
0 B P [1 2 ]
L K BN [1 2 ]
L K B P [ 1 2]
Display Port C
1 0 K _ 04
1 0 K _ 04
LVDS
R1 6 3
R2 1 5
L _ D DC _ CL K
L _ D D C _ D A TA
M 43
M 36
AT4 5
AT4 3
BH 4 1
BB 4 3
BB 4 5
BF 4 4
BE 4 4
BF 4 2
BE 4 2
BJ 4 2
BG 4 2
C o u g a rP o ni t _ R e v _ 1 p 0
[ 11 , 1 2 , 1 9 , 2 0 , 2 5 , 2 9, 30 , 3 1 , 3 6 , 3 7 ] 5 V S
[ 3 , 9 , 1 0 , 1 1 , 1 2, 13 , 1 4 , 1 5 , 1 7 , 1 8 , 1 9, 20 , 2 3 , 2 4 , 2 5 , 2 7 , 2 8, 29 , 3 0 , 3 1 , 3 6 ] 3 . 3 V S
. . , , .
3 .3 VS
T40
K4 7
[ 1 1 ] P _D D C _ C L K
[1 1 ] P _ D DC _ D A T A
Digital Display Interface
pull up 2.2K
CRT
Ver:1.0
AP 4 3
AP 4 5
Display Port D
[ 1 1, 27 ]
J47
M4 5
[ 1 1 ] B L ON
NB _ E NA V DD
Schematic Diagrams
CougarPoint - M 5/9
Boot BIOS Strap
LPC
Reserved
PCI
SPI
* 1 K _ 04
R4 4 6
* 1 K _ 04
CougarPoint -M (PCI,USB,NVRAM)
U 37 E
(NAND)
BG 2 6
BJ 2 6
BH 2 5
BJ 1 6
BG 1 6
AH 3 8
AH 3 7
A K4 3
A K4 5
C 18
N 30
H 3
AH 1 2
AM 4
AM 5
Y 13
K2 4
L24
A B4 6
A B4 5
B B S _ B I T1
B B S _ B I T0 [ 1 3 ]
Flash Descriptor security override strap

LOW = PCI_GNT#3 swap override
HIGH = Default
PCI_GNT#3
Sheet 17 of 43
CougarPoint - M 5/9
R2 2 5
* 1K _0 4
B E2 8
BC 3 0
B E3 2
BJ 3 2
BC 2 8
B E3 0
B F32
BG 3 2
A V2 6
B B2 6
AU 2 8
AY 3 0
AU 2 6
AY 2 6
A V2 8
A W30
IN T _ P IRQ E #
*1 K _ 0 4
MPC Switch Control

MPC ON -- 0
MPC OFF -- 1 DEFAULT
3 .3 V
P L T _R S T #
I N T _P I R Q A #
I N T _P I R Q B #
I N T _P I R Q C #
I N T _P I R Q D #
U1 3
74 A H C 1 G 0 8G W
1
4
B U F _ P L T _ R S T # [ 2 2 , 2 4 , 26 , 2 7 ]
K4 0
K3 8
H 38
G 38
D GP U _ H O L D _ R S T # C 4 6
C 44
D GP U _ S E L E C T#
E4 0
D _G P U _ P W R _E N #
R2 4 5
D 47
B B S _B I T 1
D G P U _ P W M_ S E L E C T # E 4 2
F46
P C I _ GN T #3
1 00 K _ 0 4
[ 2 5 ] S A TA _O D D _ D A #
I N T _P I R Q E #
S A T A _ O DD _ DA #
I N T _P I R Q G#
I N T _P I R Q H #
G
G
C
D
42
40
42
44
1
2
3
4
R SVD 7
R SVD 8
R SVD 9
R SVD 1 0
R SVD 1 1
R SVD 1 2
R SVD 1 3
R SVD 1 4
R SVD 1 5
R SVD 1 6
R SVD 1 7
R SVD 1 8
R SVD 1 9
R SVD 2 0
R SVD 2 1
R SVD 2 2
TP2 1
TP2 2
TP2 3
TP2 4
R SVD 2 3
R SVD 2 4
FOR LAYOUT SWAP
I N T _ P I R QD #
D_ G P U_ P W R_ E N #
S A T A _ OD D _D A #
I N T _ P I R QG #
AT1 0
BC 8
AU 2
AT4
AT3
AT1
AY 3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD 4
BF6
TP2 5
TP2 6
TP2 7
TP2 8
TP2 9
TP3 0
TP3 1
TP3 2
TP3 3
TP3 4
TP3 5
TP3 6
TP3 7
TP3 8
TP3 9
TP4 0
R SVD 2 8
R SVD 2 9
U SBP0 N
U SBP0 P
U SBP1 N
U SBP1 P
U SBP2 N
U SBP2 P
U SBP3 N
U SBP3 P
U SBP4 N
U SBP4 P
U SBP5 N
U SBP5 P
U SBP6 N
U SBP6 P
U SBP7 N
U SBP7 P
U SBP8 N
U SBP8 P
U SBP9 N
U SBP9 P
U SBP1 0 N
U S B P 10 P
U SBP1 1 N
U S B P 11 P
U SBP1 2 N
U S B P 12 P
U SBP1 3 N
U S B P 13 P
QA #
QB #
QC #
QD #
R E Q1 # / G P I O5 0
R E Q2 # / G P I O5 2
R E Q3 # / G P I O5 4
GN T 1 # / GP I O 5 1
GN T 2 # / GP I O 5 3
GN T 3 # / GP I O 5 5
P I R QE # / G P I O 2
P I R QF # / G P I O 3
P I R QG # / GP I O4
P I R QH # / GP I O5
R N4
1 0K _8 P 4 R _ 04
4
5
IN T _ P IRQ A#
D GP U _ H OL D _ R S T # 3
6
D GP U _ S E L E C T #
2
7
1
8
IN T _ P IRQ E#
I N T _ P I R QB #
I N T _P I R Q C #
I N T _P I R Q H #
D G P U _P W M_ S E LE C T #
AT1 2
BF3
C2 4
A2 4
C2 5
B2 5
C2 6
A2 6
K2 8
H2 8
E2 8
D2 8
C2 8
A2 8
C2 9
B2 9
N2 8
M2 8
L 30
K3 0
G3 0
E3 0
C3 0
A3 0
L 32
K3 2
G3 2
E3 2
C3 2
A3 2
US
US
US
US
US
US
B _ PN0
B_ PP0
B _ PN1
B_ PP1
B _ PN2
B_ PP2
[2 6 ]
[2 6 ]
[3 0 ]
[3 0 ]
[2 2 ]
[2 2 ]
10/29
US
US
US
US
B _ PN4
B_ PP4
B _ PN5
B_ PP5
[2 3 ]
[2 3 ]
[2 3 ]
[2 3 ]
US B _ P N9 [3 0 ]
US B _ P P 9 [3 0 ]
U S B _P N 1 1 [ 2 8 ]
U S B _ P P 1 1 [2 8 ]
C3 3
U S B _ B IA S
R 4 67
USB PORT0 (J_USB_1)

USB PORT1 (J_USB3_1; USB3.0)
WLAN
NEW CARD
3G
CCD
USB PORT2 (AJ_USB1)

BT
PORT11
[ 2 3]
[ 1 4]
PCL K_ T P M
CL K _ P C I_ F B
[ 2 7 ] P C LK _K B C
U SB R B IA S
R2 1 4
R2 2 7
*2 2 _ 0 4
2 2 _0 4
P C L K _ TP M_ P C H
C LK _P C I _ F B _ R
R2 6 0
2 2 _0 4
C LK _P C I _ K B C _ R
H 49
H 43
J48
K4 2
H 40
P L T RS T #
CL KO
CL KO
CL KO
CL KO
CL KO
UT _ P C
UT _ P C
UT _ P C
UT _ P C
UT _ P C
I0
I1
I2
I3
I4
O
O
O
O
O
C 0# /
C 1# /
C 2# /
C 3# /
C 4# /
O C5 #
O C 6# /
O C 7# /
G P IO 5 9
G P IO 4 0
G P IO 4 1
G P IO 4 2
G P IO 4 3
/ G P IO 9
G P IO 1 0
G P IO 1 4
A1 4
K2 0
B1 7
C1 6
L 16
A1 6
D1 4
C1 4
U
U
U
U
U
U
U
U
S B _ OC
S B _ OC
S B _ OC
S B _ OC
S B _ OC
S B _ OC
S B _ OC
S B _ OC
#01
#23
#45
#67
#89
# 1 01 1
# 1 21 3
#14
SB_ O
SB_ O
SB_ O
SB_ O
C# 4 5
C # 1 0 11
C# 6 7
C # 1 2 13
R N6
1 0K _8 P 4 R
5
6
7
8
_ 04
4
3
2
1
U
U
U
U
SB_ O
SB_ O
SB_ O
SB_ O
C# 0 1
C# 1 4
C# 2 3
C# 8 9
R N7
1 0K _8 P 4 R
5
6
7
8
_ 04
4
3
2
1
U S B _ O C# 0 1 [3 0 ]
10/29
R2 3 3
* 0 _0 4
C ou g a rP o i nt _R e v _ 1 p0
3 .3 V
U
U
U
U
2 2 . 6 _1 % _ 0 4
B3 3
C 6
R2 2 8
R2 6 5
R2 5 1
R2 4 1
AY 5
BA2
PM E#
P L T _ RST #
10 K _ 0 4
10 K _ 0 4
10 K _ 0 4
*1 0 K _ 0 4
AV5
AV1 0
US BR B IA S #
K1 0
[ 27 ] P ME #
[ 3 , 2 3 ] P L T _ R S T#
3 .3 V S
R N5
1 0K _8 P 4 R _ 04
4
5
3
6
2
7
1
8
AT8
R SVD 2 6
R SVD 2 7
P IR
P IR
P IR
P IR
AY 7
AV7
AU 3
BG 4
R SVD 2 5
PI N P LT_R ST# to B uff er
* 0 . 1u _ 1 6 V _ Y 5 V _ 0 4
5
C2 0 7
SVD
SVD
SVD
SVD
R SVD 5
R SVD 6
P C I _ GN T #3
B2 1
M 20
AY 1 6
BG 4 6
R 2 43
R
R
R
R
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP1 0
TP1 1
TP1 2
TP1 3
TP1 4
TP1 5
TP1 6
TP1 7
TP1 8
TP1 9
TP2 0
USB
R2 2 6
Boot BIOS Location
0
1
0
1
RSVD
BBS_BIT0
0
0
1
1
PCI
BBS_BIT1
A C _ P R E S E N T [ 1 5 , 27 ]
[ 2 , 3 , 8 , 1 1, 13 , 1 4 , 1 5 , 1 8, 1 9 , 2 0 , 2 2 , 23 , 2 6 , 2 8 , 3 0, 31 , 3 3 , 3 4 , 3 5] 3. 3V
[ 3, 9, 1 0 , 1 1 , 1 2 , 13 , 1 4 , 1 5 , 1 6, 18 , 1 9 , 2 0 , 2 3, 2 4 , 2 5 , 2 7 , 28 , 2 9 , 3 0 , 3 1, 36 ] 3 . 3 V S
. . , , .
Schematic Diagrams
CougarPoint - M 6/9
3 .3V S
R1 8 0
1 0K _0 4
R1 8 4
*0 _ 0 4
B IO S _ RE C
CougarPoint - M (GPIO,VSS_NCTF,RSVD)
BIOS RECOVERY
DISABLE----R349 NO STUFF (DEFAULT)
ENABLE-----R349 STUFF
U 3 7F
S _G P IO
[2 7 ] S M I #
3 .3V S
R4 5 1
*1 0 K _ 04
R4 5 0
10 0 K _ 0 4
T7
S MI#
A4 2
D GP U _ H P D _ IN T R #
H3 6
S C I#
E3 8
IC C_ E N #
C1 0
G P IO 12
C4
H OS T_ A L E R T #1
G2
GF X _ C R B _ D E T
[2 7 ] S C I #
10/28
B M B U S Y # / GP I O0
T A C H 4 / GP I O 6 8
T A C H 1 / GP IO1
T A C H 5 / GP I O 6 9
T A C H 2 / GP IO6
T A C H 6 / GP I O 7 0
T A C H 3 / GP IO7
T A C H 7 / GP I O 7 1
C4 0
S A TA _O D D _ P W R GT
B4 1
P C H _ G P IO 57
R4 6 9
1 . 5K _1 % _ 0 4
C4 1
G P I O 70
R4 7 4
1 . 5K _1 % _ 0 4
A4 0
G P I O 71
R4 7 1
1 . 5K _1 % _ 0 4
S A T A _ OD D _ P W R GT [2 5 ]
3 .3 VS
3 .3 VS
G P I O8
L A N _ P H Y _ P W R _ C T R L / GP I O 1 2
R3 1 4
[ 27 ] O C P P E #
*0 _ 04
P4
G P I O1 5
S A TA _D E T # 4
A 2 0 GA TE
U2
S A T A 4 G P / GP IO1 6
T5
S C LO C K / GP I O2 2
H OS T_ A L E R T #2
E8
G P I O2 4 / M E M_ L E D
R4 6 5
1 K _ 04
K B C _ R S T#
E1 6
[ 1 1] S B _ B L ON
G P I O2 7
IC C _ E N #
P LL _ OD V R _E N
P8
G P IO 34
K1
P C H _M U T E #
K4
S A TA _O D D _ P R S N T #
V8
[2 5 ] S A T A _ OD D _ P R S N T #
F D I_ OV R V L T G
M5
M F G _M OD E
N2
G F X _ CR B _ DE T
M3
V1 3
GA 2 0 [2 7 ]
1 .0 5 VS_ VT T
H _ P E C I [3 , 2 7]
K B C _ R S T # [ 27 ]
G P I O2 8
H _ C P U P W R GD [ 3 ]
AY1 0
H T H R MT R I P #_ R
T 14
IN IT 3 _3 V #
AY1
N V _ CL E
T H R MT R I P #
R1 2 5
3 90 _ 1 % _0 6
H _ T H R MT R I P # [3]
R4 3 0
I N IT 3 _ 3 V #
D F _T V S
TS _ V S S 1
S T P _ P C I# / GP IO 3 4
TS _ V S S 2
TS _ V S S 3
TS _ V S S 4
R4 2 9
1 K_ 0 4
10/28
A H 8 R 54 7
*1 0 mi l _ 04
A K 1 1 R 54 8
*1 0 mi l _ 04
A H 1 0 R 54 9
*1 0 mi l _ 04
A K 1 0 R 55 0
*1 0 mi l _ 04
2 . 2K _0 4
1 .8 VS
H _ S N B _ IV B # [ 3 ]
Sheet 18 of 43
CougarPoint - M 6/9
DMI & FDI Termination Voltage

NV_CLE
Set to Vss when LOW

Set to Vcc when HIGH
3 .3 V S
3 .3 V S
[ 2 ] C R I T _ T E MP _ R E P #
3.3 V
* 1 0K _ 0 4
*0 _ 0 4
P R OC P W R G D
G P I O3 5
INTEGRATE CLOCK
DISABLE----R465 NO STUFF (DEFAULT)
ENABLE-----R465 STUFF
R1 3 7
R1 3 8
AY1 1
CPU/MISC
B IOS _ R E C
3 .3V
GPIO
D4 0
T A C H 0 / GP IO1 7
*1 0 K _ 0 4
H P E C I_R
P5
R CIN #
D GP U _ P W R OK
R4 8 4
A U1 6
P E CI
R4 4 9
10 K _ 0 4
R1 8 1
10 K _ 0 4
T E S T _ S E T _ UP
R4 3 5
*0 _ 04
C R IT _ T E M P _R E P # _ R
R2 2 2
10 0 K _ 0 4
T E S T _ DE T
P3 7
S L OA D / G P IO 38
NC _ 1
S D A T A OU T 0 / GP IO 3 9
B G2
S D A T A OU T 1 / GP IO 4 8
V S S _ N CT F _ 1 5
V S S _ N CT F _ 1 6
G P I O5 7
V S S _ N CT F _ 1 7
V3
B G4 8
D6
B H3
B H4 7
1 K_ 0 4
1 K_ 0 4
* 10 K _ 0 4
V S S _ N CT F _ 1 8
H OS T _ A L E R T# 1
H OS T _ A L E R T# 2
G P IO 12
A4
10/28
3 .3 V S
A4 4
BJ 4
V S S _ N CT F _ 1
V S S _ N CT F _ 1 9
V S S _ N CT F _ 2
V S S _ N CT F _ 2 0
V S S _ N CT F _ 3
V S S _ N CT F _ 2 1
A4 5
R N8
1 0 K _ 8 P 4R _ 0 4
1
8
2
7
3
6
4
5
S C I#
S M I#
G A2 0
K B C _ R S T#
V S S _ N CT F _ 4
A5
V S S _ N CT F _ 5
A6
R
R
R
R
R
R
R
R
17 9
16 6
26 4
47 0
45 5
43 6
48 0
44 2
1 0 K _ 04
2 0 0K _0 4
1 0 K _ 04
1 K_ 0 4
* 1K _ 0 4
1 0 K _ 04
* 10 K _ 0 4
1 0 K _ 04
S _ GP IO
S A T A _ OD D _ P R S N T #
D G P U _ H P D _ IN T R #
S A T A _ OD D _ P W R GT
GP IO 3 4
C R I T _T E M P _ R E P #_ R
DG P U_ P W RO K
S A T A _ DE T # 4
B3
BJ 4 6
V S S _ N CT F _ 2 2
BJ 5
V S S _ N CT F _ 2 3
BJ 6
V S S _ N CT F _ 6
V S S _ N CT F _ 2 4
V S S _ N CT F _ 7
V S S _ N CT F _ 2 5
V S S _ N CT F _ 8
V S S _ N CT F _ 2 6
V S S _ N CT F _ 9
V S S _ N CT F _ 2 7
V S S _ N CT F _ 1 0
V S S _ N CT F _ 2 8
V S S _ N CT F _ 1 1
V S S _ N CT F _ 2 9
V S S _ N CT F _ 1 2
V S S _ N CT F _ 3 0
V S S _ N CT F _ 1 3
V S S _ N CT F _ 3 1
V S S _ N CT F _ 1 4
V S S _ N CT F _ 3 2
B4 7
D1
B D4 9
D4 9
BE1
* 1K _ 0 4
P L L _ OD V R _ E N
BE4 9
R 20 1
1 0 0K _0 4
F D I_ OV R V L T G
BF1
C2
C4 8
BD 1
R 19 4
BJ 4 4
BJ 4 5
A4 6
NCTF
R 46 2
R 25 4
R 46 1
E1
E4 9
F1
BF4 9
F49
C o ug a rP o i nt_ R e v _1 p 0
[ 2, 3,5 , 1 9 ,2 0 , 34 ,3 6 ] 1 .0 5 V S _ V T T
[ 6 , 1 9, 3 3 ] 1 . 8 V S
[2 , 3 ,8 ,11 ,1 3 , 1 4, 15 ,1 7 , 1 9, 20 ,2 2 ,2 3,2 6 , 2 8 ,3 0,3 1 , 3 3 , 3 4, 3 5 ] 3 . 3 V
[ 3 ,9 , 10 , 1 1 ,1 2 , 13 ,1 4 , 1 5, 16 ,1 7 , 1 9, 20 ,2 3 ,2 4,2 5 , 2 7 ,2 8,2 9 , 3 0 , 3 1, 3 6 ] 3 . 3 V S
. . , , .
Internal GFX: Low (Default)

External GFX: High
Schematic Diagrams
CougarPoint - M 7/9
CougarPoint -M (POWER)
1 .0 5 VS
5 VS
POWER
U3 7 G
V C CA _ D A C_ 3 . 3 V S
All VCCORE = 1.3A
1 u _ 6. 3V _ Y 5 V _0 4
1. 0 5 V S
1 u _6 . 3 V _ Y 5 V _ 0 4
1 . 0 5V S _V CC A P L L_ E X P
R1 5 2
AA2 3
AC 2 3
AD 2 1
AD 2 3
AF2 1
AF2 3
AG 2 1
AG 2 3
AG 2 4
AG 2 6
AG 2 7
AG 2 9
AJ 2 3
AJ 2 6
AJ 2 7
AJ 2 9
AJ 3 1
*2 0 m li _ 0 4
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
R E [1 ]
R E [2 ]
R E [3 ]
R E [4 ]
R E [5 ]
R E [6 ]
R E [7 ]
R E [8 ]
R E [9 ]
R E [1 0 ]
R E [1 1 ]
R E [1 2 ]
R E [1 3 ]
R E [1 4 ]
R E [1 5 ]
R E [1 6 ]
R E [1 7 ]
V C CA D A C
C 4 51
U4 7
C4 5 2
0 .0 1 u_ 1 6 V _ X7 R _ 04
VSSAD AC
C4 5 3
0 .1 u_ 1 0 V _ X5 R _0 4
C5 3 9
1 0u _ 6 .3 V _ X5 R _0 6
OU T
*0 .1 u _ 10 V _ X 5 R_ 0 4
C4 5 9
*2 2 u _ 6.3 V _ X 5 R _ 0 8
R 45 7
* 23 . 7 K _ 1 %_ 0 4
4
S H DN #
R 1 59
* 20 m i l_ 0 4
3. 3 V S
R 46 0
C1 5 6
V SS AL VDS
* 10 K _ 1 % _0 4
1 .8 V S _ V C C T X_ L V D
0 . 1u _ 1 0 V _X 5 R _0 4
V CC T X_ L V DS [1]
G ND
* A P L 5 6 03 -3 3 B
V CC A L V D S
AK3 7
* 1 u_ 6 . 3 V _ X5 R _0 4
2
SET
AK3 6
IN
C 45 7
3 .3 V S _ V C CA _ L V D
1mA
A M3 7
L 34
HC B 1 60 8 K F -1 2 1 T2 5
60mA
A M3 8
C 1 53
C1 5 0
C4 3 9
0 .0 1 u_ 1 6 V _ X7 R _ 04
0 .0 1u _ 1 6V _X 7 R _ 0 4
2 2u _ 6 .3 V _ X5 R _0 8
APL5603-33B 6-02-56033-4C0
G9091-330T11UF 6-02-90913-4C0
1 . 8V S
AP3 6
Sheet 19 of 43
CougarPoint - M 7/9
U4 8
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
V CC
CRT
1 u_ 6 .3 V _ Y 5 V _ 0 4
C1 7 4
AP3 7
AN 1 9
1 .05 V S _ V C CA P LL _ E X P
V CC I O[ 2 8 ]
L3 1
*HC B 1 0 05 K F -12 1 T 20
3. 3V S
V C C A _P L L _ E X P
BJ 2 2
266mA
V CC A P L L E X P
C 4 24
AN 1 6
* 1 0u _ 6 . 3V _X 5 R_ 0 6
AN 1 7
HV CMOS
V3 3
V CC I O[ 1 5 ]
V CC I O[ 1 6 ]
AN 2 1
1 .0 5 V S
V CC I O[ 1 7 ]
V C C3 _ 3 [ 6]
C1 7 9
0 .1 u_ 1 0 V _ X5 R _0 4
V C C3 _ 3 [ 7]
V3 4
1. 5V S _1 . 8 V S
AN 2 6
All VCCIO = 2.92A
V CC I O[ 1 8 ]
AN 2 7
V CC I O[ 1 9 ]
C 14 7
C 1 71
C 1 49
C 1 51
C 1 52
1 0 u _6 . 3 V _ X 5R _ 06
1 u _ 6.3 V _ Y 5V _0 4
1 u _ 6. 3V _ Y 5V _0 4
1 u _ 6. 3V _ Y 5 V _0 4
1 u _ 6 . 3V _Y 5 V _ 04
AT1 6
160mA
AT2 0
42mA
V CC V RM [3]
AP2 1
V CC I O[ 2 0 ]
AP2 3
AP2 6
V CC I O[ 2 3 ]
AT2 4
V CC I O[ 2 4 ]
1 .0 5 V S_ VT T
V CC DM I [ 1]
VCC I O
V CC I O[ 2 2 ]
DM I
V CC I O[ 2 1 ]
AP2 4
C 14 6
2mA
AB3 6
V C CC LK D MI
V C CC L K DM I
R1 6 4
* 2 0m i l _0 4
C1 2 8
1u _ 6 .3 V _Y 5 V _ 04
1 . 05 V S
10 u _ 6 .3V _ X 5 R_ 0 6
AN 3 3
V CC I O[ 2 5 ]
AN 3 4
266mA
Z2501
C 14 4
A G1 6
V CC I O[ 2 6 ]
V C CD F T E RM [1]
V CC 3 _3 [ 3 ]
V C CD F T E RM [2]
BH 2 9
1 .5 V S _ 1 . 8V S
0 .1 u _1 0 V _ X 5R _ 0 4
160mA
AP1 6
1 . 0 5V S _V CC A P L L_ F D I
R 42 1
1.0 5 V S
*0 _ 0 4
11/ 01
V CC V R M [2 ]
BG 6
42mA
1 .0 5 V S _ V TT
V c cA F DI P L L
1. 0 5 V S
1 .5 V S
AU 2 0
* 20 m i l _0 4
1 .8 V S
R1 4 0
AJ 1 6
3 .3 VS
CougarPoint power supply range
* 20 m i _l 0 4
* 0_ 0 4
C1 6 0
V C CD F T E RM [3]
AJ 1 7
0 . 1u _ 1 0 V _X 5 R _0 4
V C CD F T E RM [4]
V CC ME 3 .3 V
AP1 7
V CC DM I [ 2 ]
R 1 49
V _ N V RA M _ V CC Q
R 1 41
V CC I O[ 2 7 ]
1. 0 5 S _ V CC _ DM I
190mA
A G1 7
DF T / S PI
3 .3 V S
F DI
1 0u _ 6 . 3 V _ X5 R _0 6
C1 7 8
LVDS
C 1 58
U 39
1mA
V CC CORE
C1 6 8
3 . 3V S
L17
HC B 1 00 5 K F -1 2 1 T2 0
V1
V C CSPI
20mA
3 .3 V S
R 43 9
*0 _ 0 4
R 44 0
0 _ 04
C4 4 6
3. 3V
Min
1.00V
1.43V
1.71V
3.14V
Voltage
1.05V
1.5V
1.8V
3.3V
Max
1.10V
1.58V
1.89V
3.47V
4.75V
5V
5.25V
11/03
1 u _6 . 3 V _ Y 5 V _ 0 4
Co u g ar P oi n t _ Re v _ 1 p 0
1 .8V S
1.5 V S _1 . 8 V S
R 14 3
*0 _ 0 4
R 14 8
*2 0 m li _ 0 4
R 14 7
*0 _ 0 4
[2 0]
[1 1, 1 2 , 2 0 , 2 5, 2 9 , 3 0 , 31 ,3 6 ,3 7]
[2 ,3 , 8,1 1 ,1 3 ,14 , 1 5 , 1 7 , 18 ,2 0 ,2 2, 2 3 , 2 6 , 2 8, 3 0 , 3 1 , 33 ,3 4 ,3 5]
[ 3 ,9, 10 , 1 1 , 1 2,1 3 ,1 4 ,15 , 1 6 , 1 7 , 18 ,2 0 ,2 3, 2 4 , 2 5 , 2 7, 2 8 , 2 9 , 30 ,3 1 ,3 6]
[6 ,1 8 ,3 3]
[2 9 ,3 1]
[ 2 , 3 , 5 , 1 8 , 20 ,3 4 ,3 6]
[ 1 3 , 1 4 , 15 ,2 0 ,3 4]
. . , , .
1. 5V S _1 . 8 V S
5V S
3. 3V
3. 3V S
1. 8V S
1. 5V S
1. 05 V S _ V T T
1. 05 V S
Schematic Diagrams
CougarPoint - M 8/9
CougarPoint - M (POWER)
CougarPoint power supply range

Voltage
1.05V
1.5V
1.8V
3.3V
5V
1 . 0 5V S _V C C A _C LK
L 36
* H C B 1 00 5 K F -1 2 1T 2 0
Max
1.10V
1.58V
1.89V
3.47V
5.25V
1 . 05 V S
U3 7 J
3 . 3V
PO WE R
AD 4 9
C1 9 4
V CC A CL K
0 . 1u _ 1 0V _X 5 R _ 0 4
3mA
C 19 2
P2 8
1 u _ 6. 3 V _ Y 5 V _ 0 4
1 .0 5 V S
V C C I O[ 31 ]
C 1 90
L 16
H C B 1 0 0 5K F -12 1 T 20
*0 . 1 u _1 0 V _ X5 R _0 4
P C H_ V CC DS W
V C C3 _ 3
2 66 mA
11/01
T27
DC P S US B Y P
V C C I O[ 32 ]
T29
V C C I O[ 33 ]
T38
3 .3 V
C 1 87
1 0u _ 6 . 3V _X 5 R _ 0 6
1 u _ 6. 3 V _ Y 5 V _ 0 4
BH 2 3
AL 2 9
V C C S U S 3 _3 [ 7 ]
V C C A P L LD MI 2
AL 2 4
*1 u _ 6. 3 V _ X 5R _ 04
DC P S US [3 ]
DCP S US
A ll V CC ASW =1 .0 1A
C1 7 3
V C C S U S 3 _ 3[ 10 ]
P2 4
V C C S U S 3 _3 [ 6 ]
V C C I O[ 34 ]
C 1 83
V CC A S W [3 ]
1 u _ 6. 3 V _ Y 5 V _ 0 4
AA2 6
* 20 m i _l 0 4
1 .0 5 V S
V CC A S W [4 ]
AA2 7
V CC A S W [5 ]
AA2 9
V CC A S W [6 ]
AA3 1
V CC A S W [7 ]
AC 2 6
Note: C1289- STUFFED ONLY FOR CPT INTERPOSER;

UNSTUFF FOR CPT
V CC A S W [8 ]
AC 2 7
V CC A S W [9 ]
AC 2 9
V CC A S W [1 0 ]
AC 3 1
V CC A S W [1 1 ]
AD 2 9
V CC A S W [1 2 ]
AD 3 1
V CC A S W [1 3 ]
W21
V CC A S W [1 4 ]
W23
+ V 5 A _P C H _ V C C 5 R E F S U S
1mA
V 5 R E F _S U S
Clock and Miscellaneous
1 u_ 6 . 3 V _ Y 5 V _ 04
M 26
V CC A S W [1 5 ]
W24
DCP S US [4 ]
V C C S U S 3 _3 [ 1 ]
A N 2 3 + V C C A _ U S B S U S C 15 4
R B 7 5 1 S -40 C 2
A
3 . 3V
R2 4 2
1 0 _0 4
C2 0 3
0 . 1 u _1 0 V _ X5 R _0 4
5V
*1 u _6 . 3 V _ X 5R _ 04
AN 2 4
1mA
P3 4
+ 5 V _P C H _ V C C 5 R E F S U S
D 11
C
V CC A S W [1 6 ]
V C C S U S 3 _3 [ 3 ]
V C C S U S 3 _3 [ 4 ]
V C C S U S 3 _3 [ 5 ]
Vc cD MI
Vc cI O
Vc cA SW
Vc cS PI
1. 1
1. 05
1. 05
3. 3
0. 04 2
2. 92 5
1. 01
0. 02 0
Vc cD SW3 _3
Vc cD FTE RM
Vc cS us3 _3
Vc cS usH DA
Vc cV RM
Vc cC lKD MI
Vc cS SC
Vc cD IFF CL KN
Vc cA LVD S
Vc cT X_L VD S
3. 3
1. 8
3. 3
3. 3
1. 5
1. 05
1. 05
1. 05
3. 3
1. 8
2 (m A)
0. 19
0. 09 7
1 (m A)
0. 16
0. 02
0. 09 5
0. 05 5
1 (m A)
0. 06
Sheet 20 of 43
CougarPoint - M 8/9
R B 7 5 1 S -40 C 2
A
3 . 3V S
R2 6 3
V C C S U S 3 _3 [ 2 ]
S0 I cc ma x Cur re nt ( A)
1 (m A)
1 (m A)
1 (m A)
0. 26 6
1 (m A)
0. 08
0. 08
1. 3
3 .3 V
V 5R E F
PC I/ GP IO /L PC
1 u _ 6. 3 V _ Y 5V _ 0 4
D 10
C
R1 9 6
T26
V CC A S W [2 ]
AA2 4
2 2u _ 6 . 3V _X 5 R _ 0 8
0 . 1u _ 1 0V _ X 5 R _ 0 4
AA1 9
AA2 1
C 2 00
C1 9 7
0 . 1 u _1 0 V _ X5 R _0 4
V2 4
V CC A S W [1 ]
C4 3 8
C 18 4
V2 3
V C C S U S 3 _3 [ 9 ]
Vo lt age R ai l Vol ta ge
V_ CP U_I O
1. 05
V5 RE F
5
V5 RE F_S us
5
Vc c3 _3
3. 3
Vc cA DAC 3
1. 05
Vc cA DPL LA
1. 05
Vc cA DPL LB
1. 05
Vc cC ore
1. 05
1 0 _0 4
5 VS
N 20
C2 0 2
97mA
N 22
1u _ 6 . 3 V _X 5 R _ 0 4
3 .3 V
11/03
P2 0
3. 3 V S
P2 2
C 18 6
1 u _6 . 3 V _ Y 5 V _ 0 4
266mA
AA1 6
V C C 3 _3 [ 1 ]
W16
V C C 3 _3 [ 8 ]
T34
C 1 81
0 . 1 u _1 0 V _ X 5R _0 4
V C C 3 _3 [ 4 ]
W26
C1 9 3
0 . 1u _ 1 0V _ X 5 R _ 0 4
C 1 80
0 . 1 u _1 0 V _ X5 R _0 4
V CC A S W [1 7 ]
W29
V CC A S W [1 8 ]
C2 0 1
W31
0 . 1 u _1 0 V _ X 5R _0 4
AJ 2
V CC A S W [1 9 ]
V C C 3 _3 [ 2 ]
+ V 1 . 0 5S _S A T A 3
W33
1 . 0 5 V S L3 2
H C B 1 0 0 5K F -12 1 T 20
V CC A S W [2 0 ]
1 . 0 5V S _V C C A _A _ D P L
1. 5 V S _ 1 . 8 V S
V C C I O[ 5 ]
+V C C R T C E X T
+C 4 36
C 4 23
C4 2 7
2 2 u _6 . 3 V _ X 5R _ 08
1 u_ 6 . 3 V _ Y 5 V _ 04
16mA
R 4 24
* 2 20 u _ 6. 3 V _ 6 . 3 *4 . 2
N 16
DC P RT C
AF1 3
L1 5
H C B 16 0 8 K F -1 21 T 2 5
All VCCIO=2.92A
C 16 6
C1 5 9
1 u _ 6. 3 V _ Y 5 V _ 0 4
*1 0 u_ 6 . 3 V _ X5 R _ 0 6
1 .0 5 V S
AH 1 3
V C C I O[ 12 ]
Y 49
AH 1 4
V C C V R M [ 4]
V C C I O[ 13 ]
* 0 _0 4
L3 5
H C B 1 0 0 5K F -12 1 T 20
V C C I O[ 6 ]
BD 4 7
V CC A DP L L A
SA TA
80mA
80mA
1. 1 V S _ V C C A _ B _ D P L
BF4 7
V CC A DP L L B
C 4 22
1. 05 V S
C4 2 6
55mA
AF1 7
AF3 3
1 u _ 6. 3 V _ Y 5 V _ 0 4 A F 3 4
AG 3 4
C 1 64
2 2 u _6 . 3 V _ X 5R _ 08
1 u_ 6 . 3 V _ Y 5 V _ 04
1 u _ 6. 3 V _ Y 5V _ 0 4
11/03
V C C I O[ 7 ]
V CC DIF F C L K N[1 ]
C 4 03
4 . 7 u _6 . 3 V _ X 5R _ 06
C1 9 1
C1 8 2
C4 1 2
*0 . 1 u _1 0 V _ X5 R _0 4
V C CS S T
0 . 1 u _1 0 V _ X 5R _0 4
+ V 1 . 05 M _V C C S U S
* 1 u_ 6 . 3 V _X 5 R _ 0 4
C4 1 3
1mA
C4 6 2
C4 6 1
DC P S US [1 ]
DC P S US [2 ]
BJ 8
V _P R OC _ I O
V CC RT C
V C C A S W [ 22 ]
C o u g arP o i n t _R e v _1 p 0
1 u _ 6. 3 V _ Y 5V _ 0 4
0 . 1u _ 1 0V _X 5 R _ 0 4
AC 1 6
1. 5V
1 . 05 V S
R 25 8
*0 _ 06
R 25 9
0_ 0 6
AC 1 7
C 16 7
AD 1 7
1 u _ 6. 3 V _ Y 5 V _ 0 4
DC P S S T
T17
V1 9
A2 2
C 4 60
3. 3V
1 . 5 V S _ 1 . 8V S
V1 6
*0 . 1 u _1 0 V _ X5 R _0 4
RT CV CC
1 . 05 V S
3 . 3 A _ 1. 5 A _ H D A _ I O
V C C I O[ 4 ]
MI SC
1 . 0 5 V S _ V TT
1 u_ 6 . 3 V _ Y 5V _0 4
C1 5 5
V CC S S C
L 33
*H C B 1 0 05 K F -1 2 1 T2 0
1 . 0 5 V S _ V C C A P L L_ S A T A 3
AF1 1
V C C I O[ 2 ]
CP U
1 .0 5 V S
AK1
V C C V R M[ 1 ]
V C C I O[ 3 ]
AG 3 3
RT C
* 2 2u _ 6 . 3V _X 5 R _ 0 8
C 1 63
T21
1. 01 A
1 .0 5 VS
V2 1
V C C A S W [ 23 ]
V C C A S W [ 21 ]
HD A
C 4 49
V C C A P LL S A T A
AF1 4
V CCS US H DA
T19
P3 2
[ 13 ] 3 . 3 A _ 1. 5 A _ H D A _ I O
[ 19 ] 1 . 5 V S _ 1 . 8V S
[ 1 3 , 15 ] R T C V C C
[ 2 3 , 2 6, 30 , 3 1 , 33 , 3 4 , 35 ] 5 V
[ 1 1 , 1 2, 1 9 , 2 5, 29 , 3 0 , 31 , 3 6 , 37 ] 5 V S
[ 2 , 3 , 8, 11 , 1 3 , 14 , 1 5 , 17 , 1 8 , 1 9, 2 2 , 2 3, 2 6 , 2 8, 30 , 3 1 , 33 , 3 4 , 35 ] 3 . 3 V
[ 3 , 9 , 1 0, 1 1 , 1 2, 13 , 1 4 , 15 , 1 6 , 17 , 1 8 , 1 9, 2 3 , 2 4, 2 5 , 2 7, 28 , 2 9 , 30 , 3 1 , 36 ] 3 . 3 V S
[ 3 , 6 , 8 , 9, 10 , 2 6 , 28 , 3 1 , 33 ] 1 . 5 V
[ 13 , 1 4 , 15 , 1 9 , 34 ] 1 . 0 5 V S
[ 2, 3 , 5 , 1 8 , 19 , 3 4 , 36 ] 1 . 0 5 V S _ V TT
16mA
3 . 3A _ 1 . 5 A _ H D A _I O
11/ 01
C2 0 4
0 . 1u _ 1 0V _X 5 R _ 0 4
0 . 1u _ 1 0V _ X 5 R _ 0 4
. . , , .
C 1 61
T24
V C C S U S 3 _3 [ 8 ]
V C C I O[ 1 4 ]
+ V C C A P L L _C P Y _ P C H
1 1/01
97mA
T23
C1 7 6
1 . 05 V S
1 .0 5 VS
V1 2
V C C 3_ 3 [ 5 ]
L 30
* H C B 1 00 5 K F -1 2 1T 2 0
2 2 u _6 . 3 V _ X 5R _ 08
All VCCIO=2.92A
P2 6
V C C I O[ 30 ]
V CC DS W 3 _ 3
3. 3 V S
C 4 41
N 26
V C C I O[ 29 ]
T16
US B
Min
1.00V
1.43V
1.71V
3.14V
4.75V
Schematic Diagrams
CougarPoint - M 9/9
CougarPoint
-M
(GND)
U37I
Sheet 21 of 43
CougarPoint - M 9/9
AY 4
AY 42
AY 46
AY 8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
B B4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
B F8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS [159]
VSS [160]
VSS [161]
VSS [162]
VSS [163]
VSS [164]
VSS [165]
VSS [166]
VSS [167]
VSS [168]
VSS [169]
VSS [170]
VSS [171]
VSS [172]
VSS [173]
VSS [174]
VSS [175]
VSS [176]
VSS [177]
VSS [178]
VSS [179]
VSS [180]
VSS [181]
VSS [182]
VSS [183]
VSS [184]
VSS [185]
VSS [186]
VSS [187]
VSS [188]
VSS [189]
VSS [190]
VSS [191]
VSS [192]
VSS [193]
VSS [194]
VSS [195]
VSS [196]
VSS [197]
VSS [198]
VSS [199]
VSS [200]
VSS [201]
VSS [202]
VSS [203]
VSS [204]
VSS [205]
VSS [206]
VSS [207]
VSS [208]
VSS [209]
VSS [210]
VSS [211]
VSS [212]
VSS [213]
VSS [214]
VSS [215]
VSS [216]
VSS [217]
VSS [218]
VSS [219]
VSS [220]
VSS [221]
VSS [222]
VSS [223]
VSS [224]
VSS [225]
VSS [226]
VSS [227]
VSS [228]
VSS [229]
VSS [230]
VSS [231]
VSS [232]
VSS [233]
VSS [234]
VSS [235]
VSS [236]
VSS [237]
VSS [238]
VSS [239]
VSS [240]
VSS [241]
VSS [242]
VSS [243]
VSS [244]
VSS [245]
VSS [246]
VSS [247]
VSS [248]
VSS [249]
VSS [250]
VSS [251]
VSS [252]
VSS [253]
VSS [254]
VSS [255]
VSS [256]
VSS [257]
VSS [258]
VS S[259]
VS S[260]
VS S[261]
VS S[262]
VS S[263]
VS S[264]
VS S[265]
VS S[266]
VS S[267]
VS S[268]
VS S[269]
VS S[270]
VS S[271]
VS S[272]
VS S[273]
VS S[274]
VS S[275]
VS S[276]
VS S[277]
VS S[278]
VS S[279]
VS S[280]
VS S[281]
VS S[282]
VS S[283]
VS S[284]
VS S[285]
VS S[286]
VS S[287]
VS S[288]
VS S[289]
VS S[290]
VS S[291]
VS S[292]
VS S[293]
VS S[294]
VS S[295]
VS S[296]
VS S[297]
VS S[298]
VS S[299]
VS S[300]
VS S[301]
VS S[302]
VS S[303]
VS S[304]
VS S[305]
VS S[306]
VS S[307]
VS S[308]
VS S[309]
VS S[310]
VS S[311]
VS S[312]
VS S[313]
VS S[314]
VS S[315]
VS S[316]
VS S[317]
VS S[318]
VS S[319]
VS S[320]
VS S[321]
VS S[322]
VS S[323]
VS S[324]
VS S[325]
VS S[328]
VS S[329]
VS S[330]
VS S[331]
VS S[333]
VS S[334]
VS S[335]
VS S[337]
VS S[338]
VS S[340]
VS S[342]
VS S[343]
VS S[344]
VS S[345]
VS S[346]
VS S[347]
VS S[348]
VS S[349]
VS S[350]
VS S[351]
VS S[352]
H46
K 18
K 26
K 39
K 46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P 16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P 30
N47
P 11
P 18
T33
P 40
P 43
P 47
P7
R2
R48
T12
T31
T37
T4
W 34
T46
T47
T8
V 11
V 17
V 26
V 27
V 29
V 31
V 36
V 39
V 43
V7
W 17
W 19
W2
W 27
W 48
Y 12
Y 38
Y4
Y 42
Y 46
Y8
B G29
N24
A J3
A D47
B 43
B E10
B G41
G14
H16
T36
B G22
B G24
C22
A P13
M14
A P3
A P1
B E16
B C16
B G28
B J28
H5
AA 17
A A2
A A3
AA 33
AA 34
AB 11
AB 14
AB 39
A B4
AB 43
A B5
A B7
AC 19
AC2
AC 21
AC 24
AC 33
AC 34
AC 48
AD 10
AD 11
AD 12
AD 13
AD 19
AD 24
AD 26
AD 27
AD 33
AD 34
AD 36
AD 37
AD 38
AD 39
AD4
AD 40
AD 42
AD 43
AD 45
AD 46
AD8
A E2
A E3
AF 10
AF 12
AD 14
AD 16
AF 16
AF 19
AF 24
AF 26
AF 27
AF 29
AF 31
AF 38
A F4
AF 42
AF 46
A F5
A F7
A F8
AG 19
AG2
AG 31
AG 48
AH 11
AH3
AH 36
AH 39
AH 40
AH 42
AH 46
AH7
AJ 19
AJ 21
AJ 24
AJ 33
AJ 34
AK 12
A K3
U37H
VS S[0]
VS S[1]
VS S[2]
VS S[3]
VS S[4]
VS S[5]
VS S[6]
VS S[7]
VS S[8]
VS S[9]
VS S[10]
VS S[11]
VS S[12]
VS S[13]
VS S[14]
VS S[15]
VS S[16]
VS S[17]
VS S[18]
VS S[19]
VS S[20]
VS S[21]
VS S[22]
VS S[23]
VS S[24]
VS S[25]
VS S[26]
VS S[27]
VS S[28]
VS S[29]
VS S[30]
VS S[31]
VS S[32]
VS S[33]
VS S[34]
VS S[35]
VS S[36]
VS S[37]
VS S[38]
VS S[39]
VS S[40]
VS S[41]
VS S[42]
VS S[43]
VS S[44]
VS S[45]
VS S[46]
VS S[47]
VS S[48]
VS S[49]
VS S[50]
VS S[51]
VS S[52]
VS S[53]
VS S[54]
VS S[55]
VS S[56]
VS S[57]
VS S[58]
VS S[59]
VS S[60]
VS S[61]
VS S[62]
VS S[63]
VS S[64]
VS S[65]
VS S[66]
VS S[67]
VS S[68]
VS S[69]
VS S[70]
VS S[71]
VS S[72]
VS S[73]
VS S[74]
VS S[75]
VS S[76]
VS S[77]
VS S[78]
VS S[79]
VSS [80]
VSS [81]
VSS [82]
VSS [83]
VSS [84]
VSS [85]
VSS [86]
VSS [87]
VSS [88]
VSS [89]
VSS [90]
VSS [91]
VSS [92]
VSS [93]
VSS [94]
VSS [95]
VSS [96]
VSS [97]
VSS [98]
VSS [99]
VS S[100]
VS S[101]
VS S[102]
VS S[103]
VS S[104]
VS S[105]
VS S[106]
VS S[107]
VS S[108]
VS S[109]
VS S[110]
VS S[111]
VS S[112]
VS S[113]
VS S[114]
VS S[115]
VS S[116]
VS S[117]
VS S[118]
VS S[119]
VS S[120]
VS S[121]
VS S[122]
VS S[123]
VS S[124]
VS S[125]
VS S[126]
VS S[127]
VS S[128]
VS S[129]
VS S[130]
VS S[131]
VS S[132]
VS S[133]
VS S[134]
VS S[135]
VS S[136]
VS S[137]
VS S[138]
VS S[139]
VS S[140]
VS S[141]
VS S[142]
VS S[143]
VS S[144]
VS S[145]
VS S[146]
VS S[147]
VS S[148]
VS S[149]
VS S[150]
VS S[151]
VS S[152]
VS S[153]
VS S[154]
VS S[155]
VS S[156]
VS S[157]
VS S[158]
CougarPoi nt_Rev _1p0
CougarPoint_Rev _1p0
. . , , .
A K38
A K4
A K42
A K46
A K8
A L16
A L17
A L19
A L2
A L21
A L23
A L26
A L27
A L31
A L33
A L34
A L48
A M11
A M14
A M36
A M39
A M43
A M45
A M46
A M7
A N2
A N29
A N3
A N31
A P12
A P19
A P28
A P30
A P32
A P38
A P4
A P42
A P46
A P8
A R2
A R48
A T11
A T13
A T18
A T22
A T26
A T28
A T30
A T32
A T34
A T39
A T42
A T46
A T7
A U24
A U30
A V16
A V20
A V24
A V30
A V38
A V4
A V43
A V8
A W14
A W18
A W2
A W22
A W26
A W28
A W32
A W34
A W36
A W40
A W48
A V11
A Y 12
A Y 22
A Y 28
Schematic Diagrams
New Card, Mini PCIE

NEW CARD(Port 3)
10 /29
MINI CARD WLAN
3 .3 V
20 mil
C4 7 2
0 . 1 u_ 1 6V _Y 5 V _0 4
11/01
J _M I N I 1
R6 0 5
[ 15 , 2 4 , 26 ] P C I E _ W A K E #
R 4 90
3 .3 V
*0 _ 04
1 0 K _ 04
1
3
5
7
11
13
9
15
[ 1 4 ] W L A N _ C L K R E Q#
[1 4 ] CL K_ PCIE _ M INI#
[ 1 4 ] C L K _ P C I E _M I N I
W AKE#
C O E X1
C O E X2
C L K R E Q#
REF C L KREF C L K+
GN D 0
GN D 1
3. 3 V A U X_ 0
1 . 5V _ 0
U I M _P W R
UIM _ DA T A
U I M_ C L K
UIM _ RE S E T
U I M_ V P P
GN D 5
2
6
8
10
12
14
16
R5 5 2
R4 9 1
*0 _ 0 4
B T_ S B D #
VD D3
8 0C LK
*1 0 m li _ 04
[ 27 ]
3 I N 1 [ 2 7]
KEY
21
27
29
35
23
25
31
33
[ 2 7 ] W L A N _ D E T#
[ 14 ] P C I E _ R X N 3 _ W L A N
[ 1 4 ] P C I E _R XP 3_ W L A N
[ 1 4 ] P C I E _T X N 3 _ W L A N
[ 1 4] P C I E _ T XP 3_ W L A N
R4 9 4
[ 27 , 2 8 ] B T _E N
*0 _ 04
3. 3 V
[ 1 4]
[ 1 4]
[ 1 4]
C L _C L K 1
C L _D A T A 1
C L _R S T #1
3 . 3V
[ 27 , 2 8 ] B T _E N
B T _S B D #
[ 1 4 ] B T _S B D #
R 1 99
R 2 04
R 4 98
R4 9 9
*
*
*
*
0_ 0 4
CL _ CL K _ 1
0_ 0 4
CL _ DA T A _ 1
0_ 0 4
CL _ RS T # _ 1
10 K _ 0 4
R5 0 1
0 _0 4
R5 5 3
*0 _ 04
17
19
37
39
41
43
45
47
49
51
GN D 2
GN D 3
GN D 4
GN D 1 1
P E T n0
P E T p0
P ERn 0
P ERp 0
R e s erv ed 0
R e s erv ed 1
GN D 1 2
3. 3V A U X _3
3. 3V A U X _4
GN D 1 3
R e s erv ed 2
R e s erv ed 3
R e s erv ed 4
R e s erv ed 5
GN D 6
GN D 7
GN D 8
GN D 9
G ND1 0
W _ DIS A B L E #
P ERSE T #
SM B _ CL K
S M B _ DA T A
U S B _D U S B_ D+
3. 3 V A U X_ 1
1 . 5V _ 1
1 . 5V _ 2
3. 3 V A U X_ 2
L E D _W W A N #
L E D_ W L A N#
L E D _W P A N #
18
26
34
40
50
20
22
30
32
36
38
24
28
48
52
42
44
46
W L A N _ E N [ 27 , 2 8 ]
B U F _ P L T _R S T # [ 17 , 2 4 , 26 , 2 7 ]
US B _ D #
US B _ D
R3 5 7
R3 5 6
B T _D E T # [ 2 7 , 2 8]
U S B _ P N 2 [ 17 ]
USB _ P P 2 [1 7 ]
* 1 0m i _l 0 4
* 1 0m i _l 0 4
R4 8 9
0 _ 04
3 . 3V
3 . 3V
W L A N _ L E D # [ 2 7 , 28 ]
MP C E C - S 00 F 1 -T P 0 0
1 0/ 29
[ 3 , 6, 8, 9 , 1 0 , 20 , 2 6 , 28 , 3 1 , 33 ] 1 . 5 V
[ 19 , 2 9 , 31 ] 1 . 5 V S
[ 2 , 3, 8 , 1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 1 9 , 2 0, 2 3 , 2 6, 2 8 , 3 0, 31 , 3 3 , 34 , 3 5 ] 3. 3 V
[ 3, 9 , 1 0 , 11 , 1 2 , 13 , 1 4 , 15 , 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 3, 2 4 , 2 5, 2 7 , 2 8, 29 , 3 0 , 31 , 3 6 ] 3. 3 V S
[ 1 3 , 2 4, 27 , 3 1 , 32 , 3 8 ] V D D 3
New Card, Mini PCIE B - 23

. . , , .
Sheet 22 of 43
New Card, Mini
PCIE
Schematic Diagrams
CCD, 3G, TPM

MINI CARD 3G(Port 6)
3G POWER
R5 0 9
3 .3 V
3 G_ 3 . 3V
LK R E Q#
E F CL K E F CL K +
ND0
ND1
C 50 0
U I M_ P W R
U I M_ D A TA
U I M_ C L K
U I M_ R S T
U I M_ V P P
C2 0 9
C5 0 7
0. 1 u _ 16 V _ Y 5 V _ 04
0. 1 u _1 6 V _ Y 5 V _ 04
0 . 1 u _1 6 V _ Y 5 V _0 4
0. 1 u _ 16 V _ Y 5 V _ 04
1 0 0K _ 0 4
R5 1 9
35
23
25
31
33
[ 2 7 ] 3 G_ D E T #
17
19
37
39
41
43
45
47
49
51
3 G_ 3 . 3 V
Sheet 23 of 43
CCD, 3G, TPM
C2 4 2
C2 6 7
0 . 1u _ 1 6V _ Y 5 V _ 0 4
1 0u _ 10 V _ Y 5 V _ 0 8
G ND1 1
PETn 0
PETp 0
P E R n0
P E R p0
W _ DIS A B L E #
P E RS E T #
S MB _ C L K
S M B _ DA T A
U S B _D US B _ D+
R es e rv e d0
R es e rv e d1
G ND1 2
3 .3 V A UX _ 3
3 .3 V A UX _ 4
G ND1 3
R es e rv e d2
R es e rv e d3
R es e rv e d4
R es e rv e d5
3. 3V A U X_ 1
1 . 5V _ 1
1 . 5V _ 2
3. 3V A U X_ 2
LE D _ W W A N #
L E D_ W L A N#
LE D _ W P A N #
Q3 5
MT N 70 0 2Z H S 3
18
26
34
40
50
Q 33
M TN 7 00 2 Z H S 3
3 30 K _ 04
[ 2 7 ] 3 G_ P W R _ E N
GN D 6
GN D 7
GN D 8
GN D 9
G ND1 0
1 0 _0 6
R5 2 0
22 0 u_ 6 . 3 V _6 . 3 *6 . 3 *4 . 2
GN D 5
G ND2
G ND3
G ND4
C 4 83
R 51 5
1 0 u_ 1 0V _Y 5V _ 0 8
C 2 87
+
C2 1 2
KEY
21
27
29
3G _3 . 3 V
>48 mil
C
R
R
G
G
3. 3V A U X_ 0
1 . 5V _ 0
U I M _P W R
U I M_ D A T A
U I M_ C L K
UIM _ RE S E T
U I M_ V P P
>48 mil
60m ils
G
W AKE #
C OE X 1
C OE X 2
2
6
8
10
12
14
16
7
11
13
9
15
J_ 3 G1
1
3
5
*0 _ 06
Q3 0
A O 34 1 5
S
D
From H8 default HI
20
22
30
32
36
38
3 G _E N
[ 2 7]
SIM CONN
U S B _P N 4 [ 17 ]
U S B _P P 4 [ 1 7 ]
24
28
48
52
42
44
46
3 G_ 3 . 3 V
U I M_ P W R
R5 0 3
*4 . 7K _ 0 4
U I M_ D A T A
C2 3 5
3G _3 . 3 V
0. 1 u _ 16 V _ Y 5 V _ 04
C2 8 6
J_ S I M 1
88 9 10 -5 2 04 M-0 1
2 20 u _4 V _ V _ A
LOCK
(TOP VIEW)
R 5 04
*1 0m i l _0 4
U I M _C LK
U I M _R S T
U I M _P W R
U I M _C
C 3
C 2
C 1
U I M_ C L K
U I M_ R S T
U I M_ P W R
R 48 8
* 1 0m i _l 0 4
U I M_ D A T A
U I M_ V P P
U I M_ GN D
C 7 U I M_ D
C 6
C 5
OPEN
C 4 89
C 1 7 70 6 61 -1
S I M LO C K
U I M_ D A T A
U I M_ V P P
C 4 70
C 46 9
C4 7 1
* 2 2p _ 50 V _ N P O _0 4
* 22 p _ 50 V _ N P O _0 4
*2 2 p_ 5 0V _ N P O_ 0 4
* 22 p _ 50 V _ N P O _0 4
3. 3 V S
TPM 1.2
A sse rted bef ore en te ring S3

C5 0 8
C2 8 5
C2 9 4
C 3 00
*0 . 1 u_ 1 6 V _Y 5V _ 0 4
*0 . 1 u_ 1 6V _Y 5V _ 0 4
*0 . 1 u_ 1 6V _ Y 5V _ 0 4
*1 u_ 1 6 V _X 5 R _ 0 6
CCD
L PC r es et timing:
L PCPD# inact ive to LRST# inact ive 3 2~96us
5V
U 28
[ 1 3 , 27 ]
[ 1 3 , 27 ]
[ 1 3 , 27 ]
[ 1 3 , 27 ]
L P C_ A D
L P C_ A D
L P C_ A D
L P C_ A D
26
23
20
17
0
1
2
3
21
[ 17 ] P C LK _ T P M
[ 1 3 , 27 ]
[ 3 , 17 ]
[ 1 3 , 27 ]
[ 15 ]
L A D0
L A D1
L A D2
L A D3
L CL K
22
16
27
15
L P C _ F R A ME #
P L T _R S T #
S E R IRQ
P M _C L K R U N #
V D D1
V D D2
V D D3
L F RA M E #
L RE S E T #
S E R IRQ
C LK R U N #
G ND
GP I O
G P I O2
XTAL O
TESTI
C5
C4
0 . 1 u_ 1 6V _Y 5V _ 0 4
1 u_ 6 . 3 V _Y 5 V _0 4
1 u_ 6 . 3 V _Y 5 V _0 4
6
2
J _ CC D1
T P M3 0 0 4
T P M3 0 0 5
13
XTALI
14
XTALO
[ 27 ] C C D _ E N
[ 17 ] U S B _P N 5
[ 1 7] U S B _ P P 5
[2 7 ] CC D_ DE T #
PP
C 6
*1 00 K _ 0 4
*0 . 1 u_ 1 6V _Y 5V _ 0 4
XT A L I
N C_ 1
N C_ 2
N C_ 3
MJ_CCD1
R1 1
2
C2 8 2
T P M 30 0 1 1
T P M 30 0 2 3
T P M 30 0 3 12
HI: ACCESS
L OW: NORMAL ( Int ernal PD)
HI: 4E/ 4F H
T PM _BADD L OW: 2E/ 2F H
T PM _PP
EN
G 5 24 3 A
VSB
T E S T B I/B A DD
TP M _P P
V OU T
3
*1 u _6 . 3 V _ Y 5 V _ 04
48 mil
1
VIN
VIN
C2
3 . 3V S
5
L P CP D #
T P M_ B A D D
4
5
TPM
28
[ 15 ] S 4 _ S TA TE #
5 V _C C D
U 41
10
19
24
G
G
G
G
ND_ 1
ND_ 2
ND_ 3
ND_ 4
4
11
18
25
4
3
C C D _D E T #
X7
* MC -1 4 6 _3 2 . 7 68 K H z
1
2
C 3 05
C 30 2
* 18 p _ 50 V _ N P O _0 4
6-22-32R76-0B4
From H8 default HI
* 18 p _5 0 V _ N P O _0 4
* S L B 96 3 5T T
R3 4 9
P C LK _ T P M
X TA L O
C 2 92
P C LK _ T P M1
X TA L I
*3 3 _0 4
Co-layout X7, X8
*1 0 p_ 5 0V _ N P O_ 06
3 . 3V S
1
2
4
3
[ 2 , 3, 8, 1 1 , 13 , 1 4 , 15 , 1 7 , 18 , 1 9, 20 , 2 2, 2 6 , 2 8, 3 0 , 3 1, 3 3 , 3 4, 3 5 ] 3 . 3V
[ 3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 14 , 1 5 , 16 , 1 7 , 18 , 1 9, 20 , 2 4, 2 5 , 2 7, 2 8 , 2 9, 3 0 , 3 1, 3 6 ] 3 . 3V S
[ 2 0 , 2 6, 3 0 , 3 1, 3 3 , 3 4, 3 5 ] 5 V
X8
*1 T JS 12 5 D J 4 A 42 0 P _ 32 . 7 68 K H z
T P M _P P
R 3 41
*1 0 K _0 4
T P M _B A D D
R 3 48
*1 0 K _1 % _0 4
R 3 52
*1 0 K _1 % _0 4
6-22-32R76-0B2
6-22-32R76-0BG
B - 24 CCD, 3G, TPM

. . , , .
1
2
3
4
5
8 5 2 05 -0 50 0 1
Schematic Diagrams
Card Reader/LAN JMC251C

S D _C L K
*1 0p _5 0V _N P O_0 6
SD _ C LK
R 4 48
*2 0mi l _0 4
11 /0 2
(>20 mil)
R E GLX
S D X C _P OWE R
MS _I N S #
1 K_ 04
S D _W P
C 17 0
0. 1 u_ 16 V_ Y 5V _0 4 2. 2 u_ 6. 3V _ Y 5V _0 6
U 36
Ca rd Rea der Pu ll High /Lo w

Re sis tor s
D VD D
R 162
*2 0mi l _04
R 156
[2 5] LA N _ MD I P0
*2 0mi l _04 [2 5] LA N _ MD I N 0
2[ 5] LA N _ MD I P1
[2 5] LA N _ MD I N 1
D VD D
R 144
*2 0mi l _04
49
50
51
52
53
54
A V D D 12 _55 55
56
57
58
59
LA N _ MD I P2 60
LA N _ MD I N 2 61
A V D D 12 _62 62
LA N _ MD I P3 63
LA N _ MD I N 3 64
MD I O10
MD I O9
MD I O8
A V D D 12 _52
3. 3 V_ LA N
[2 5] LA N _ MD I P2
2[ 5] LA N _ MD I N 2
2[ 5] LA N _ MD I P3
[2 5] LA N _ MD I N 3
MD I O1 0
MD I O9
MD I O8
V DD
V I P _1
V I N _1
A V D D 12
V I P _2
V I N _2
GN D
A V D D 33
V I P _3
V I N _3
A V D D 12
V I P _4
V I N _4
JMC251 C
(LQFP 64)
LA N _ SC L R 42 6
* 4. 7K _ 04
U 35
8
VCC
(>20mil)
C 17 7
C 44 8
10 u_ 6. 3 V_ X5 R _0 6
Pi n#3 3
0. 1 u_ 16 V_ Y 5V _0 4
Pi n# 33
6
5
JMC251/261 only
WP
SCL
SDA
A0
A1
GN D
A2
*A T2 4C 0 2B N
7
MP D
1
2
3
R 21 6
1 0K _0 4
R 21 7
* 4. 7K _0 4
C 44 0
0 . 1u _16 V _Y 5 V_ 04
J MC 25 1-LGB Z 0C
R 14 2
3 . 3V S
V C C _ C AR D
3. 3 V S
(>20mi l)
(>20mil)
(>20mil)
MPD
LA N _P C I E _W A KE #
LA N _S C L
LA N _S D A
C 1 99
C 198
C 44 3
C 44 2
1 0u _6 . 3V _X 5R _ 06
P in# 32
0 . 1u _1 6V _Y 5 V _04
P in #3 2
*10 u_ 6. 3V _ Y 5V _0 6
P in #3 1
0. 1u _1 6V _ Y 5V _0 4
Pi n# 31
3 . 3V _L A N
*0_ 06
V DD3
3 . 3V _L AN
SD _ WP
MD I O12
MD I O14
SD _ C D #
V DD3
R 43 1
BU F _ PL T_ R ST # [ 17 , 22 ,2 6, 2 7]
C PP E N
I S ON _2 51 CR 1 91
11 /0 2
*20 mi _l 04
R 1 90
*10 0K _0 4
3. 3 V_ LA N
R 434
1 0K _0 4
P C I E_ WA K E #
[ 15 , 22, 2 6] P C I E_ WA K E #
PCIe D ifferential
Pairs = 100 Ohm
LA N _ PC I E _W A K E#
Sheet 24 of 43
Card Reader/LAN
JMC251C
AV D D 1 2_ 13
DVDD
3. 3 V_ LA N
C 43 5
C 13 9
0. 1u _1 6V _Y 5 V _0 4
Pi n#7
0. 1u _1 6V _Y 5V _0 4
Pi n#1 3
DV DD R 1 46
*2 0m li _0 4
R 14 5
12 K_ 1% _0 4
AV D D 1 2_ 7
4 IN 1 SO CKET SD/MM C/MS/ MS Pr o

R 13 6
*0 _0 4
R 42 7
*2 0m li _0 4
P C I E_ R XP _4 _GL A N
P C I E_ R XN _ 4_ GLA N
C 4 33
C 4 34
MS _I N S #
S D _C D #
S D _D 2
S D _D 3
S D _B S
11 /0 2
0. 1 u_ 10 V_ X7 R _0 4
0. 1 u_ 10 V_ X7 R _0 4
Card Reader
Power
P C I E _R X P 4_GL A N [ 1 4]
PC I E _ R XN 4 _GLA N [ 14 ]
V CC_ CA RD
V C C _C A R D
S D _C L K
C 48 2
AV D D 1 2_ 52
AV D D 1 2_ 55
A VD D 1 2_ 62
A VD D 12_ 7
C 44 5
C 15 7
C 14 5
C 13 6
0. 1u _1 6V _Y 5 V _0 4
Pi n#5 2
0. 1u _1 6V _Y 5V _0 4
Pi n#5 5
0. 1 u_1 6V _ Y 5V _0 4
Pi n# 62
*1 0u_ 6. 3 V_ X5 R _0 6
Pi n# 7
Re se rv ed
P C I E _TX N 4_ GLA N [ 14 ]
P C I E_ TX P4 _GL A N [ 1 4]
C L K_ P C I E_ GLA N [ 14 ]
C LK _ PC I E _GL A N # [ 14 ]
L AN X OU T
R 428
*1 M_04
0. 1u _1 6V _Y 5 V _0 4
R 49 6
*7 5_ 04
V CC_ CA RD
C 47 9
LA N X IN
0. 1u _1 6V _Y 5 V _0 4
X 10
2
For
JMC251 C
FS X 5L_ 25 MH Z
X9
3. 3 V_ LA N
3
C 13 4
C 14 8
0. 1u _1 6V _Y 5 V _0 4
Pi n#4 3
0. 1u _1 6V _Y 5V _0 4
Pi n#4 3
C 43 1
S D _D 0
S D _D 1
S D _W P
S D _C L K
S D _D 3
MS _I N S #
S D _D 2
S D _D 0
S D _D 1
S D _B S
3. 3 V_ LA N
4
C 45 0
2
1
* FS X5 L_ 25 MH z
2 2p _50 V _N P O_0 4
C 432
22p _5 0V _N PO_ 04
0 . 1u _16 V _Y 5 V_ 04
P in #2
LA N _P C I E _W AK E # [ 27 ]
R B 7 51 S-4 0C 2
LA N X I N
LA N X OUT
R E X T_C
V D D R EG
(>20mil)
VD D R EG
D1 6
1
2
3
4
5
6
7
AV D D1 2_ 7
*20 mi _l 04 8
9
10
11
12
A V DD 12 _13 13
MD I O1 3
14
MD I O7
15
16
CR _CD 1 N
10/2 9
R 2 07
* 28m li _0 6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V DDRE G
V C C 3V
P W RCR
TE S T
MP D
W AK E N
LA N _L ED 2
C R _ LE D
R ST N
C PP E N
GN D
V DDIO
MD IO 6
MD I O1 2
MD I O1 4
C R _C D 0 N
P1
P2
P3
P4
P5
P6
P7
P8
P9
P 10
P 11
P 12
P 13
P 14
P 15
P 16
P 17
P 18
P 19
P 20
P 21
J_ C AR D -R E V 1
C D _ SD
D A T2 _S D
C D / D A T3 _S D
C MD _ SD
V S S_ S D
V D D _S D
C L K_ S D
V S S_ S D
D A T0 _S D
D A T1 _S D
W P _S D
V S S_ MS
V C C _MS
S C LK _ MS
D A T3 _MS
I N S _MS
D A T2 _MS
S D I O/ D A T0_ MS
D A T1 _MS
B S _MS
GN D
V S S_ MS
GN D
MD R 01 9-C 0 -1 04 2
P2 2
P2 3
C 19 5
* 10u _6 . 3V _X 5R _ 06
P in #2
3. 3 V_ LA N
6-22-25R00-1B4
6-22-25R00-1B5
C 13 3
C 13 5
C 18 9
*10 u_ 6. 3V _ X5R _06

Pi n#5 9
Re ser ve d
*0. 1 u_ 16V _ Y 5V _0 4
Pi n#5 9
*0. 1 u_ 16 V_ Y 5V _0 4 0. 1 u_ 16 V_ Y 5V _0 4
Pi n# 2
Pi n# 21
P lac e a ll c a pac ito rs c lo se d to c h ip .

T h e s u b sc rip t in e ac h CA P in c ic ate s th e p in
n u mb er o f J M C 25 1 /JM C2 6 1 th at sh o u ld b e
c ol s e d to .
V C C _C A R D
VC C _C A R D
C 43 7
C 4 78
C 4 81
C 4 80
* 0. 1u _1 6V _Y 5 V _0 4
*0 . 1u _1 6V _Y 5 V_ 04
*0 . 1u _1 6V _Y 5 V_ 04
Near Ca rdr ead er CON N
VD D 3
1.2V
V DD3
2A
P C 1 02
*0 .1 u_ 16 V_ Y 5V _0 4
P C 99
P R 1 15
*0 _0 4
5
9
7
8
1
U 20
VIN
VIN
P OK
1A
V C N TL
V OU T
V OU T
VFB
D VD D
3
P R 1 16
* 1. 27 K _1 %_0 4
EN
GN D
*1 u_ 10 V_ Y 5V _ 06
2
PC9 8
*A X 6 6 1 0
* 82 p_5 0V _ N PO_ 04
GS 711 3
6- 02- 071 13- 320
AX 661 0
6- 02- 066 10- 320
PR 1 14
*2. 4 9K _1 %_ 04
10/29
[ 13, 2 2, 2 7, 31 , 32 ,3 8] V D D 3
[ 25 ] D VD D
[ 3, 9 , 10 1, 1, 1 2, 13 , 14 , 15, 1 6, 1 7, 18 , 19 ,2 0, 2 3, 25 , 27 , 28, 2 9, 3 0, 31 , 36 ] 3 . 3V S
[3 , 6, 8 9, , 10 , 20, 2 6, 2 8, 31 , 33 ] 1 . 5V
[ 2 0, 23 , 26 , 30, 3 1, 3 3, 34 , 35 ] 5 V
Card Reader/LAN JMC251C B - 25

. . , , .
REXT
A V DD 33
X IN
X OUT
C LK N
C LK P
AV DD 1 2
R XP
RXN
GND
T XN
T XP
A V DD 12
MDI O1 3
MDI O7
C R_C D1 N
D VD D
DV DD
V DD3
MDI O1 1
LA N _ LE D0
LA N _ LE D1
I SON
GND
VD DI O
VD DO
M DI O5
M DI O4
M DIO 3
MD IO 2
MD I O1
MD I O0
F B1 2
GND
LX
R 15 8
* 4. 7K _ 04
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V C C _ C AR D
R 42 5
10/29
LA N _ SD A
For
REGL X
S D _C D #
1 0K _0 4
3. 3V _ LA N
SD X C _ POW E R
S D _ C LK _C
S D _ BS
S D _D3
S D _D2
S D _D1
S D _D0
DV DD
MD I O1 1
LA N _ LE D0
LA N _ LE D1
I SON_ 25 1C
C 16 5
*4 . 7K _0 4
R 49 3
3 .3 V S V D D 3
D VD D
L3 7
S WF 25 20 C F -4R 7M-M
3 .3 V S
R 49 7
3. 3V _ LA N
Switch ing Regulator

close to PIN33
C 4 54 ne ar P in# 41
JMC251C
Schematic Diagrams
LAN (JMC251C), SATA HDD, ODD

R3 7 4
1L 25
GIGA LAN (JMC251C)
* 0_ 0 4
2
4
3
* W CM 20 1 2 F 2 S -S H O R T
R3 7 5
* 0_ 0 4
R3 7 6
DV D D
[2 4 ]
[2 4 ]
[2 4 ]
[2 4 ]
L A N_ M
L A N_ M
L A N_ M
L A N_ M
D IP 0
D IN 0
D IP 1
D IN 1
[2 4 ]
[2 4 ]
[2 4 ]
[2 4 ]
L A N_ M
L A N_ M
L A N_ M
L A N_ M
D IP 2
D IN 2
D IP 3
D IN 3
L A N_ MD
L A N_ MD
L A N_ MD
L A N_ MD
IP 0
IN 0
IP 1
IN 1
L A N_ MD
L A N_ MD
L A N_ MD
L A N_ MD
IP 2
IN 2
IP 3
IN 3
6
5
3
2
* 0 _0 4
1L 26
L29
12
11
9
8
T D4 +
T D4 T D3 +
T D3 -
M X4 +
M X4 M X3 +
MX 3 -
T D2 +
T D2 T D1 +
T D1 -
MX 2 +
M X2 MX 1 +
MX 1 -
T CT 4
T CT 3
T CT 2
T CT 1
MC T 4
MC T 3
MC T 2
MC T 1
13
14
16
17
L MX 1+
L MX 1L MX 2+
L MX 2-
19
20
22
23
L MX 3+
L MX 3L MX 4+
L MX 4-
R3 7 8
1L 27
2
J _R J 1
4
3
*W C M 2 01 2 F 2 S -S H O R T
R3 7 7
* 0 _0 4
*0 _ 04
D L MX 1 +
D L MX 1 D L MX 2 +
D L MX 2 -
1
2
3
6
D L MX 3 +
D L MX 3 D L MX 4 +
D L MX 4 -
4
5
7
8
DA +
DA DB +
DB -
s h ei l d
s h ei l d
GN D 1
GN D 2
G ND
R 75
* 0_ 0 4
C 54
C3 4 3
0 .0 1u _ 1 6V _ X 7 R _ 0 4
*0 . 0 1u _ 1 6V _ X 7 R _ 0 4
*0 .0 1 u_ 1 6 V _X 7 R _ 0 4
*0 .0 1u _ 16 V _ X 7 R _ 04
C3 4 2
C3 4 1
R3 8 5
* 0 _0 4
1L 28
15
18
21
24
DC+
DCDD+
DDP J S -0 8S L 3 B
4
3
*W C M 2 01 2 F 2 S -S H O R T
R3 8 7
* 0 _0 4
W240HU PJS-08SL3B
W250HU PJS-08SO1B-1
G S T 50 0 9 LF
N
N
N
N
MC
MC
MC
MC
T_ 1
T_ 2
T_ 3
T_ 4
R4 0 2
R3 9 9
R3 9 7
R3 9 4
75 _ 1 %_ 0 4
75 _ 1 %_ 0 4
75 _ 1 %_ 0 4
75 _ 1 %_ 0 4
N M C T _R
C 3 35
1 0 0 0p _ 2 K V _ X7 R _ 1 2
Sheet 25 of 43
LAN(JMC251C),
SATA HDD, ODD
SATA HDD
SATA ODD
Zero Power ODD
J _ HD D1
S1
S2
S3
S4
S5
S6
S7
C4 8 7
C4 8 6
0 .0 1 u_ 1 6 V _X 7 R _ 0 4
0 .0 1 u_ 1 6 V _X 7 R _ 0 4
S A TA _ R XN 0
S A TA _ R XP 0
C4 8 5
C4 8 4
0 .0 1 u_ 1 6 V _X 7 R _ 0 4
0 .0 1 u_ 1 6 V _X 7 R _ 0 4
S A TA T X P 0 [1 3]
S A TA T X N 0 [1 3 ]
S A TA R X N 0 [ 1 3]
S A TA R X P 0 [ 13 ]
3 . 3V S
1.5A
G ND 1
A+
AG ND 2
BB+
G ND 3
DP
V_ 5 0
V _5 0 _ 1
MD
G ND 4
G ND 5
5V S
1A
S1
S2
S3
S4
S5
S6
S7
C4 3 0
C4 2 8
0 .0 1u _ 1 6V _ X 7 R _ 0 4
0 .0 1u _ 1 6V _ X 7 R _ 0 4
C4 2 5
C4 2 1
0 .0 1u _ 1 6V _ X 7 R _ 0 4
0 .0 1u _ 1 6V _ X 7 R _ 0 4
S A T A T X P 2 [13 ]
S A T A T X N 2 [1 3]
S A T A R XN 2 [ 13 ]
S A T A R XP 2 [1 3 ]
C 5 21
P1
P2
P3
P4
P5
P6
S A T A _ OD D_ P R S N T # [1 8 ]
S A T A _ OD D_ D A # [1 7 ]
W240HU ALLTOP-C166N5-12205-L
W250HU 1-162-100561
1u _ 6 . 3V _Y 5 V _ 0 4
10 u _ 10 V _ Y 5 V _ 08
C2 1 0
C4 7 5
0 . 1u _ 1 6V _ Y 5 V _ 0 4
0 . 1u _ 1 6V _ Y 5 V _ 0 4
C4 7 4
A LL T OP -C 16 6 N 5 -1 2 20 5 -L
P IN G N D1 ~ 2 = G N D
C4 7 3
H D D _N C 1
H D D _N C 2
H D D _N C 3
C 5 22
0 . 1 u _1 6 V _ Y 5 V _ 04
* 0 .01 u _ 16 V _ X 7R _ 04
5 V S _ OD D
U 42
1
C4 1 1
C 4 10
C4 0 8
C4 0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
0. 1 u _ 16 V _ Y 5 V _ 0 4
1 u_ 6 .3 V _Y 5 V _0 4
10 u _ 10 V _ Y 5 V _ 0 8
V O UT
VIN
VIN
GN D
EN
4
5
+C 3 9 3
2
C 18 5 5 3-1 1 3 05 -L
H D D _N C 0
*0 . 1 u _1 6 V _ Y 5 V _0 4
P1
P2
P3
P4
P5
P6
P7
P8
P9
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5
5 VS
J _ OD D 1
S A TA _ T X P 0
S A TA _ T X N 0
C4 7 6
10
7
4
1
4
3
* W CM 20 1 2 F 2 S -S H O R T
R3 8 0
*0 _ 04
*1 0 0 u_ 6 . 3 V _B 2
S A T A _ OD D_ P W R GT [1 8]
G5 2 43 A
R 5 55
1 0 0K _ 0 4
+ C 2 08
*1 00 u _ 6. 3 V _ B _ A
5 V S [1 1 ,12 ,1 9 ,2 0,2 9 ,3 0,3 1 ,3 6,3 7 ]
D V D D [ 24 ]
3 .3 V [2 , 3, 8 ,1 1 ,1 3,1 4 ,1 5,1 7 ,1 8,1 9 ,2 0,2 2 ,2 3,2 6 ,2 8, 30 ,3 1 , 33 ,3 4 , 35 ]
1 .5 V [3 , 6, 8 ,9 ,1 0 , 20 ,2 6 , 28 ,3 1 , 33 ]
3 .3 V S [3 , 9 ,10 , 1 1 ,12 , 1 3 ,14 , 1 5 ,16 , 1 7 ,18 , 1 9 ,2 0, 2 3 ,2 4, 2 7 ,2 8, 2 9 ,3 0,3 1 ,3 6]
B - 26 LAN (JMC251C), SATA HDD, ODD

. . , , .
Schematic Diagrams
USB 2.0 Connector
PCH USB 2.0 Coonnector
R 558
U S BV C C
0_06
C 495
0. 1u_16V _Y 5V _04
+
C 162
Sheet 26 of 43
USB 2.0 Connector
100u_6. 3V_B _B
J _U SB 3_1
1
U S B_P P0
R 197
0_04
U SB _PN 0_A
R 203
0_04
U SB _PP 0_A
Diff. trace 90ohm
L64
U S B_PN 0_A _R
U S B_PP 0_A_R
* W C M2012F2S -S H OR T
V+
D A TA _L
D A TA _H
GN D
GND1
GND2
GN D3
GND4
17
U S B_P N 0
317D E04PS A7A 2C

GND1
GND2
GND3
GND4
17
W240HU: 6-21-B4A10-009
/2nd: 6-21-B4A00-009
W250HUQ: 6-21-B4A20-009
30
U S BV C C
USB 2.0 Connector B - 27

. . , , .
U S B30V C C
Schematic Diagrams
KBC-ITE IT8518
K B C_ A V DD
C2 6 6
0 . 1 u _1 6 V _ Y 5 V _ 04
C2 1 1
10 u _ 10 V _ Y 5 V _ 0 8
C 26 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
C 2 56
0 . 1 u_ 1 6 V _Y 5 V _0 4
V D D3
V D D3
C 2 22
VD D3
L1 9
H C B 1 0 0 5K F -12 1 T 20
V D D3
C2 3 4
C 23 3
C2 3 2
R 29 9
0 . 1u _ 1 6V _ Y 5V _ 0 4
*0 . 1 u _1 6 V _ Y 5 V _ 04
*0 . 1 u_ 1 6 V _Y 5 V _0 4
1 0 0K _ 0 4
S MC _ B A T
S MD _ B A T
0 . 1 u _1 6 V _ Y 5 V _ 04
K B C_ W R E S E T #
E C_ V C C
HC B 10 0 5K F -12 1 T 20
P C LK _ K B C
[ 1 8 ] GA 2 0
[ 26 , 3 8 ] A C _ I N #
[ 28 ] L E D _ A C I N
[ 15 , 1 7 ] A C _ P R E S E NT
[ 1 5 ] P M_ P C H _ P W R O K
[ 18 ] S M I #
[ 18 ] S C I #
*0 _ 0 4
*0 _ 0 4
R 30 0
R 30 3
[ 3 8 ] B A T _ DE T
[ 3 8] B A T_ V O LT
[3 0 ] AP_ KEY #
[ 2 ] T H E R M_ V OL T
[ 3 8 ] T OT A L _C U R
[ 2 3 ] 3 G_ D E T #
[ 2 3] C C D _ D E T #
S M C_ B A T
S M D_ B A T
[ 38 ] S M C _ B A T
[ 38 ] S M D _ B A T
[ 2 , 1 4]
[ 2 , 1 4]
[ 3 , 18 ] H _P E C I
S MC _ C P U _ T H E R M
S MD _ C P U _ T H E R M
66
67
68
69
70
71
72
73
3 G_ D E T#
C C D _ D E T#
M OD E L_ I D
R 6 06
11/ 03
0 _0 4
R 3 28
*0 _ 0 4
L C D _B R I GH T N E S S
[ 2 9] K B C _ B E E P
LOW ACTIVE
HIGH ACTIVE
[ 2 8 ] LE D _ S C R OL L #
[ 2 8 ] L E D _ N U M#
[2 8 ] L E D_ CA P #
[ 28 ] L E D _B A T _ C H G
[ 2 8] LE D _ B A T_ F U LL
[ 2 8] LE D _ P W R
80 C L K
[ 22 ] 8 0 C L K
[ 22 , 2 8 ] B T _D E T #
[ 2 2 ] 3I N 1
[ 3 0 ] W E B _ E MA I L #
[ 30 ] T P _ C L K
[ 30 ] T P _ D A T A
R 32 0
0 _0 4
8 0 P OR T _ D E T #
1 10
1 11
1 15
1 16
1 17
1 18
24
25
28
29
30
31
32
34
85
86
87
88
89
90
1 25
[ 2 3 ] 3G _ E N
18
21
[ 3 1] P W R _ S W #
[ 1 1 , 30 ] L I D _ S W #
33
[1 5 ] P W R_ B T N#
74
VBAT
AVCC
11
LPC K/B MATRIX
W R ST#
76
77
78
79
80
81
B A T _ DE T
B A T _ V OL T
AP_ KEY #
K S I0 /S T B #
K S I1 /A F D #
K S I2 /INIT #
K S I 3/ S LI N #
KSI4
KSI5
KSI6
KSI7
K S O 0/ P D 0
K S O 1/ P D 1
K S O 2/ P D 2
K S O 3/ P D 3
K S O 4/ P D 4
K S O 5/ P D 5
K S O 6/ P D 6
K S O 7/ P D 7
K S O8 / A C K #
K S O 9/ B U S Y
K S O 1 0/ P E
K S O1 1 / E R R #
K S O1 2 / S LC T
K S O1 3
K S O1 4
K S O1 5
G A 2 0/ G P B 5
K B R S T #/ GP B 6 ( P U )
P W U R E Q # / GP C 7( P U )
L 8 0 LL A T / GP E 7 ( P U )
E C S CI# /G P D3 ( P U )
E C S MI # / G P D 4 ( P U )
DAC
G
G
D
D
D
D
PJ 0
PJ 1
A C 2 / GP
A C 3 / GP
A C 4 / GP
A C 5 / GP
J2
J3
J4
J5
IT8518
ADC
AD
AD
AD
AD
AD
AD
AD
AD
I0
I1
I2
I3
I4
I5
I6
I7
( P D )K S O1 6 / GP C 3
( P D )K S O1 7 / GP C 5
(
(
(
(
(
(
(
(
PWM
PW
PW
PW
PW
PW
PW
PW
PW
M0 / GP A 0 (
M1 / GP A 1 (
M2 / GP A 2 (
M3 / GP A 3 (
M4 / GP A 4 (
M5 / GP A 5 (
M6 / GP A 6 (
M7 / GP A 7 (
PU
PU
PU
PU
PU
PU
PU
PU
)
)
)
)
)
)
)
)
2C
2D
2C
2D
2C
2D
LK 0 / G
A T0 / G
LK 1 / G
A T1 / G
LK 2 / G
A T2 / G
PF0 (
PF1 (
PF2 (
PF3 (
PF4 (
PF5 (
PD
PD
PD
PD
PD
PD
PD
PD
)GP H
)GP H
)GP H
)GP H
)GP H
)GP H
)GP H
)GP G
0/ I D
1/ I D
2/ I D
3/ I D
4/ I D
5/ I D
6/ I D
1/ I D
0
1
2
3
4
5
6
7
EXT GPIO
( P D )E G A D / G P E 1
( P D )E GC S # / G P E 2
( P D )E GC L K / G P E 3
WAKE UP
PS/2
PS
PS
PS
PS
PS
PS
PU
PU
PU
PU
PU
PU
( P D )W U I 5 / G P E 5
( P D )L P C P D# / W U I 6 / G P E 6
)
)
)
)
)
)
PWM/COUNTER
( P D )T A C H 0 / GP D 6
( P D )T A C H 1 / GP D 7
( P D )T MR I 0/ W U I 2 / GP C 4
( P D )T MR I 1/ W U I 3 / GP C 6
WAKE UP
P W RS W /G P E 4 ( P U )
CIR
R I 1 #/ W U I 0 / GP D 0( P U )
R I 2 #/ W U I 1 / GP D 1( P U )
( P D )C R X / GP C 0
( P D )C TX / G P B 2
LPC/WAKE UP
GP INTERRUPT
G I NT / GP D 5 ( P U )
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
J _ KB1
*8 5 20 1 -2 40 5 1
W25 0H U
4
5
6
8
11
12
14
15
K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7
4
5
6
8
11
12
14
15
1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24
K B -S O0
K B -S O1
K B -S O2
K B -S O3
K B -S O4
K B -S O5
K B -S O6
K B -S O7
K B -S O8
K B -S O9
K B -S O 10
K B -S O 11
K B -S O 12
K B -S O 13
K B -S O 14
K B -S O 15
1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24
RN1 0
1 0 K _8 P 4 R _ 0 4
4
5
3
6
2
7
1
8
RA
RB
1 0K
W 24 0H U
10K
W 25 0H UQ
W 27 0H UQ
V D D3
V D D3
RA
M OD E L_ I D
R 29 2
R 29 3
RB
11/02
P CL K _ K B C
C2 4 6
*1 0 p _5 0 V _ N P O _0 6
B A T_ V O LT
R3 1 2
C2 1 7
1 u _6 . 3 V _ Y 5 V _ 04
A C_ IN#
C2 5 8
0 . 1 u_ 1 6V _Y 5V _0 4
V DD 3
*1 0_ 0 4
P C LK _ K B C _R
Co-lay SPI ROM

U 31
8
VD D
K B C_ S P I_ S I_ R
K B C _ S P I _ S O_ R
K B C_ S P I_ CE # _ R
SI
SO
K B C_ F L A S H
3
W P#
CE #
6
10 0
10 1
10 2
10 3
10 4
10 5
10 6
K B C_ S P I_ S CL K _ R
4
H OL D #
K B C_ S P I_ C E #
K B C_ S P I_ S I
K B C_ S P I_ S O
3 G_ P W R _E N
K B C _ S P I _ S C LK
V C H G-S E L [ 3 8 ]
CC D_ E N
[ 2 3]
VSS
M X 25 L 3 20 6 E
P C B F o ot p ri nt = A C A -S P I -0 0 4-T 0 3
11/0 1
[ 23 ]
( P D )L 80 H LA T / G P E 0
56
57
S U S B # [ 15 , 2 6 , 31 ]
S U S C # [ 1 5, 3 3 ]
93
94
95
96
97
98
99
10 7
82
83
84
C 2 88
0 . 1u _ 1 6V _ Y 5V _ 0 4
S U S _P W R _ A C K [ 1 5 ]
B T _ E N [ 2 2 , 28 ]
B K L _ E N [1 1 ]
H S P I _C E # [ 1 3]
H S P I _S C L K [ 1 3]
H S P I _M S O [ 1 3 ]
H S P I _M S I [ 1 3 ]
D D _ ON [ 26 , 3 1 , 32 ]
R 3 06
R 3 15
VD D
R3 6 0 1 K _ 0 4
K B C_ F L A S H
R 3 4 6 4 . 7 K _ 04
K B C _ H O LD #
SI
SO
CE #
S CK
OC P P E # [ 1 8]
4
VSS
* S S T 2 5V F 0 8 0 B S O8
10/29
35
17
5
2
1
6
K B C_ S P I_ S I_ R
K B C _ S P I _ S O_ R
K B C_ S P I_ CE # _ R
K B C_ S P I_ S CL K _ R
R 3 66
R 3 55
R 3 42
R 3 59
47 _ 0 4
15 _ 1 %_ 0 4
15 _ 1 %_ 0 4
47 _ 0 4
K B C_ S P I_ S I
K B C_ S P I_ S O
K B C_ S P I_ CE #
K B C_ S P I_ S CL K
C
C
C
C
30 3
29 0
28 4
29 7
R S MR S T # [ 1 5 ]
K B C _R S T # [ 1 8 ]
47
48
12 0
12 4
C P U _ F A N S E N [ 3 0]
H _ P R O C H OT _ E C [ 3 ]
R3 3 0
0_ 0 4
R3 3 6
*0 _ 0 4
P MP C H _ P W R OK _ R
P M _P C H _ P W R OK [ 1 5 ]
V C OR E _ O N [ 3 6 ]
A L L _S Y S _ P W R G D [ 1 1 , 1 5, 3 6 ]
11 9
12 3
P ME # _ R
R 3 29
R 3 35
R 3 31
0 _0 4
*0 _ 04
0 _0 4
19
C E L L _C ON TR OL [ 3 8 ]
P M E # [ 17 ]
L A N _ P C I E _W A K E # [ 24 ]
S W I# [1 5 ]
I T8 5 1 8E
C 2 50
0 . 1 u _1 6 V _ Y 5 V _ 04
AVSS
CLOCK
C K 3 2K E
C K 3 2K
C H G_ E N
2
12 8
R 33 3
NC 2
[1 1 ] B RIG HT NE S S
R2 8 8
*1 0 m li _ 0 4
* NC_ 0 4
0 _ 04
R3 2 6
*1 0 M_ 0 6
[ 1 1, 1 6 ]
V DD 3
J _8 0 D E B U G1
*M C -1 4 6_ 3 2 . 76 8 K H z
4
3
X5
1
2
N B _E N A V D D
* C M -20 0 S _ 32 . 7 6 8K H z
4
3
C 26 2
C2 6 5
*1 5 p _5 0 V _ N P O _0 4
*1 5 p _5 0 V _ N P O_ 0 4
1
2
3
4
5
*8 8 26 6 -0 50 0 1
3 IN1
8 0C LK
8 0D E T #
R3 5 3
1 00 K _ 0 4
11/29
L C D _B R I GH T N E S S
K B C _A G N D
C2 1 9
*0 _ 04
X4
1
2
E C _V S S
[ 38 ]
CK 3 2 K E
CK 3 2 K
R3 2 7
75
R X D / GP B 0( P U )
T X D/ G P B 1 ( P U )
( P D ) R I N G # / P W R F A I L # / L P C R S T# / G P B 7
VSS
VS S
VSS
VSS
VSS
VSS
VSS
[ 2 2, 2 8 ] W L A N _ L E D #
[ 2 2 ] W L A N _ D E T#
UART
*0 . 1u _ 1 0V _ X 5 R _ 0 4
MC-146 & CM200S

Co-layout
K B C_ S P I _ S I
K B C_ S P I _ S O
K B C_ S P I _ C E #
K B C_ S P I _ S C LK
W P#
H OL D #
*0 _ 0 4
*0 _ 0 4
11/04
KBC_SPI_*_R = 0.1"~0.5"
8 Mb it
U 30
8
11 2
1 08
1 09
1 0K _0 4
*1 0 K _ 04
V DD 3
GPIO
C L K 0 / GP B 3
D A T 0 / GP B 4
C L K 1 / GP C 1
D A T 1 / GP C 2
C L K 2 / GP F 6 ( P U )
D A T 2 / GP F 7 ( P U )
J _K B 2
8 5 2 01 -2 4 05 1
V 1. 0
K B C _ H O LD #
F L F R A ME # / GP G 2
F L A D0 /S C E #
F L A D 1/ S I
F L A D2 /S O
F L A D 3 / GP G 6
F L CL K /S CK
( P D )F LR S T #/ W U I 7 / GP G 0/ T M
SMBUS
SM
SM
SM
SM
SM
SM
K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7
0 . 1 u_ 1 6 V _Y 5 V _0 4
MO DE L_I D
S CK
FLASH
C 0 / GP
C 1 / GP
C 2 / GP
C 3 / GP
C 4 / GP
C 5 / GP
C 6 / GP
C 7 / GP
58
59
60
61
62
63
64
65
24
J_KB1
W 24 0HU /W 27 0HU
14
1 26
4
16
20
23
15
[ 2 2, 2 8 ] W L A N _ E N
[ 29 ] K B C _M U T E #
[ 1 3 ] ME _W E
[ 3 0] C P U _F A N
[3 0 ] W E B _ W W W #
L AD 0
L AD 1
L AD 2
L AD 3
L P C CL K
L F R A ME #
S E RIRQ
L P C R S T # / W U I 4 / GP D 2 ( P U )
1
12
27
49
91
113
1 22
K B C _W RE S E T #
VCC
[ 1 3 , 23 ] L P C _A D 0
[ 1 3 , 23 ] L P C _A D 1
[ 1 3 , 23 ] L P C _A D 2
[ 1 3 , 23 ] L P C _A D 3
[ 1 7] P C L K _ K B C
[ 1 3, 2 3 ] L P C _ F R A ME #
[ 13 , 2 3 ] S E R I R Q
[ 1 7 , 2 2, 2 4 , 2 6] B U F _ P L T_ R S T#
26
50
92
11 4
1 21
127
U2 3
10
9
8
7
13
6
5
22
B A T _ DE T
AP_ KEY#
3 G_ D E T #
CC D_ DE T #
C 23 8
1
0 . 1u _ 1 6V _ Y 5V _ 0 4
Sheet 27 of 43
KBC-ITE IT8518
K B C _ A GN D
C2 5 2
VSTBY
VS TBY
VSTBY
VST BY
VSTBY
VST BY
L 21
3. 3 V S
RN1 1
2 . 2 K _8 P 4 R _ 0 4
4
5
3
6
2
7
1
8
[ 13 , 2 2 , 24 , 3 1 , 32 , 3 8 ] V D D 3
[ 3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 19 , 2 0, 23 , 2 4 , 25 , 2 8 , 29 , 3 0 , 31 , 3 6 ] 3. 3 V S
B - 28 KBC-ITE IT8518
. . , , .
*3 3p _ 5 0V
*3 3p _ 5 0V
*3 3p _ 5 0V
*3 3p _ 5 0V
_N
_N
_N
_N
P O_ 0 4
P O_ 0 4
P O_ 0 4
P O_ 0 4
Schematic Diagrams
LED, MDC, BT
Bluetooth(Port8)
MJ_MDC1
20 MIL
12
11
1 .5 V
3V _B T
R 51 3
* 0 _0 4
J _ BT1
3. 3V
1
3
5
7
9
11
[ 1 3 ] H D A _ S DO _M D C
[ 1 3 ] H D A _ S Y N C_ MD C
[ 1 3 ] H D A _ S DI N 1
[ 1 3 ] H D A _ R S T # _M D C
R3 2 2
*3 3 _ 04 H D A _ S D I N 1_ R
J _M D C 1
2
4
6
8
10
12
GN D
RES E R V E D
A za l ai _ S DO
RES E R V E D
GN D
3 . 3V M a ni / a u x
A za l ai _ S Y N C
GN D
A za l ai _ S DI
GN D
A za l ai _ R S T #
A za l ai _ B C L K
*8 8 0 18 -1 2 0G
R 51 2
3. 3 V
* 0 _0 4
10mil L 4 1
MD C_ 3 . 3 V
P or t 11
3. 3 V
[ 1 7 ] U S B _ P N 11
[1 7 ] US B _ P P 1 1
[ 2 2, 2 7 ] B T _D E T #
*2 8 m li _ 06
1
2
3
4
5
6
*8 7 2 12 -0 6 G0
B T _ E N#
R 32 3
H D A _ B I T C L K _ MD C
C 2 37
C 2 55
* 0 . 1u _ 1 6V _ Y 5 V _ 0 4
*2 2p _ 5 0V _ N P O_ 0 4
[ 1 3]
*1 0 K _ 04
B T _E N #
Q 24
*M T N 7 0 02 Z H S 3
BT_ EN G
C2 5 9
3 . 3V
1 0/ 29
3 V_ BT
R 4 73
50 mil
50 mi l
*2 8 m li _ 0 6
C 4 64
*1 0u _ 6 . 3V _ X 5 R _ 0 6
L E D _A C I N [ 2 7 ]
S A TA _ L E D# [ 1 3 ]
6-52-52001-027
K P B -3 0 2 5Y S GC
3
D 15
K P B -30 2 5 Y S GC
K P B -30 2 5 Y S G C
R 1
C
W L A N _ L E D # [ 2 2 , 27 ]
*1 0 mi l _0 4
B
W LA N _ E N [ 2 2 , 2 7]
R 36 2
R3 6 1
R 36 3
R3 6 4
2 2 0_ 0 4
2 20 _ 0 4
2 2 0_ 0 4
2 20 _ 0 4
Q3
*D TC 11 4 E UA
L E D _C A P # [ 2 7]
L E D _ S C R OL L # [ 2 7 ]
6-52-52001-027
6-5 2-5 20 01-02 7
B T_ E N
B T_ E N
[ 2 2, 2 7 ]
Q1
DT C1 1 4 E UA
[ 3 , 6, 8 , 9 , 1 0, 2 0 , 2 6, 3 1 , 3 3]
[ 2 , 3 , 8 , 11 , 1 3, 14 , 1 5, 17 , 1 8, 19 , 2 0, 22 , 2 3, 2 6 , 3 0, 3 1 , 3 3, 3 4 , 3 5]
6 -52 -5 2001-027
[ 3, 9 , 1 0 , 11 , 1 2 , 13 , 1 4, 15 , 1 6, 17 , 1 8, 19 , 2 0, 23 , 2 4, 2 5 , 2 7, 2 9 , 3 0, 3 1 , 3 6]
M2
M-M A RK 1
M7
M -MA R K 1
M6
M-MA R K 1
M1
M-M A R K 1
M8
M -MA R K 1
H1 2
H 10
H 6 _ 3 D 4 _4 H 6_ 3 D 4 _ 4
2
3
4
5
H1 5
1
9
8
7
6
2
3
4
5
9
8
7
6
2
3
4
5
MT H 3 1 5 D1 11
H2 4
1
9
8
7
6
2
3
4
5
9
8
7
6
2
3
4
5
MT H 3 1 5 D 1 1 1
Sheet 28 of 43
LED, MDC, BT
BAT LED
D 14
SG
POWER ON
LED
L E D _ B A T _ F U L L [ 27 ]
D 1
L E D _B A T_ C H G [ 2 7 ]
[ 27 ]
WLAN
LED
A
D5
LE D _ N U M # [ 27 ]
SCROLL
LOCK
LED
R Y - S P 17 0 Y G 3 4 - 5M
C
C
R Y -S P 17 0 Y G 3 4 - 5 M
R Y - S P 1 7 0 Y G 3 4- 5M
A
D2
D4
D3
22 0 _0 4
R Y - S P 17 0 Y G 3 4 - 5 M
R2
CAPS
LOCK
LED
22 0 _ 04
SG
2 2 0 _0 4
22 0 _0 4
R7
2 20 _ 04
2 2 0_ 0 4
R6
R 5
NUM
LOCK
LED
L E D_ P W R
R4
R 3
BT
LED
HDD/ODD
LED
3 .3 V S
3. 3V S
Y
SG
3 . 3V S
3. 3 V S
3 . 3V S
3 .3 V S
LED
H1 1
1
1. 5 V
3. 3 V
3. 3 V S
9
8
7
6
MT H 31 5 D 1 1 1
H3
H4
C 1 11 D 11 1 N C 1 1 1D 1 11 N
M5
M-MA R K 1
M4
M-M A R K 1
M3
M -MA R K 1
H5
2
3
4
5
H6
1
MT H 3 1 5 D1 11
H9
2
3
4
5
S 2
S MD 8 0 X 80
MT H 3 1 5 D 1 1 1
H8
C 6 7 D6 7
J _ TP 1
6
MT H 31 5 D 1 1 1
H7
1
9
8
7
6
MT H 3 1 5 D1 11
H2 3
C6 7 D6 7
9
1
H 20
H 18
H 14
H 4_ 7 B 6 _0 D 3_ 7 H 4 _7 B 6 _ 0D 3_ 7H 6_ 3 D 4 _ 4
S1
S MD 80 X 8 0
1
H1 7
H 6 _ 0 D3 _7
H1 3
1
H 1
H2
C 1 11 D 11 1 N C 1 1 1D 1 11 N
H2 1
H 19
H 4 _ 0 B 7_ 0 D 3 _ 7 H 4_ 0 B 7 _0 D 3 _ 7
2
3
4
5
H2 5
1
9
8
7
6
2
3
4
5
MT H 3 1 5 D 1 1 1
9
8
7
6
LE D
LE D
LE D
LE D
_ PW R
_ A CIN
_ B A T _F U LL
_ B A T _C HG
*8 5 20 1 -06 0 5 1
G ND
MT H 31 5 D 1 1 1
H2 2
2
3
4
5
1
2
3
4
5
6
H1 6
1
MT H 3 1 5 D1 11
9
8
7
6
2
3
4
5
9
8
7
6
MT H 31 5 D 1 1 1
LED, MDC, BT B - 29
. . , , .
*1 8 0p _ 5 0V _ N P O _ 04
GN D
Schematic Diagrams
AUDIO CODEC
ALC269 VB
VT1802P
1 . 5V S
R5 2 7
* 0_ 0 4
R5 2 9
0 _ 04
.
t
n
e
n
o
p
m
o
C
5
7
Audio Codec ALC269

DV D D_ IO
3 .3 V S _ A UD
5 VS
R5 1 0
C 51 3
10 u _ 10 V _ Y 5 V _ 0 8
3 . 3V S
P V DD1 _ 2
C 29 9
0 . 1 u _1 6 V _ Y 5 V _ 04
C4 9 8
10 u _ 10 V _ Y 5 V _ 0 8
La yo ut N ot e:
*2 8 mi l _0 6
Ve ry cl os e t o Au di o C od ec
C2 7 1
0 . 1 u_ 1 6 V _Y 5 V _0 4
3 .3 V S _ A UD
R 5 67
0 _0 4
C 4 99
*1 0 u_ 1 0V _Y 5V _0 8
C2 8 1
C 28 0
C 2 83
0 . 1u _ 1 6V _ Y 5V _ 0 4
1 0 u_ 1 0 V _Y 5 V _0 8
0 . 1 u _1 6 V _ Y 5 V _ 04
C2 7 0
0 . 1u _ 1 6V _Y 5V _0 4
5 VS_ AU D
5 VS
L 40
H C B 1 0 0 5K F -12 1 T 20
1
2
C 4 97
C4 9 6
C 51 0
C 5 09
C4 9 4
0. 1 u _ 16 V _ Y 5 V _ 0 4
1 0u _ 1 0V _ Y 5V _ 0 8
0 . 1 u_ 1 6 V _Y 5 V _0 4
1 0 u _1 0 V _ Y 5 V _ 0 8
1u _ 6 . 3V _ Y 5V _ 0 4
5 VS
PD#
40
41
S P K OU T L+
S P K OU T L-
R 51 4
5 VS
47
48
E A P D _ M OD E
S P DIF O
Q 27
*B S S 1 3 8_ N L
D M I C -D A T
D M I C -C LK
HD A _ RS T #
44
45
Sheet 29 of 43
Audio Codec
ALC269
Q 32
[ 30 ] S P K O U T R * MT N 7 0 0 2Z H S 3
[ 3 0] S P K OU TR +
*1 0 0K _ 0 4
2
3
25
38
U2 9
4
P D#
L I N E 2 -L
L I N E 2 -R
M I C 2 -L
MI C 2 -R
S P K -R S P K -R +
C2 9 1
S P DIF C 2 /E A P D
S P DIF O
J DRE F
M ON O-OU T
GP I O 0
GP I O 1
M I C 1 -L
MI C 1 -R
ANALOG
MT N 7 0 0 2Z H S 3
S
[ 13 ] H D A _ S D I N 0
B I T -C L K
R 35 4
33 _ 0 4
S D A T A -I N
A Z _ S Y N C _R
10
H D A _ R S T#
11
B E E P _R
12
LD O_ C A P
M I C 1 -V R E F O-R
MI C 2- V R E F O
SYN C
MI C 1 - V R E F O - L
RE S E T #
[ 13 ] H D A _ S P K R
B E E P _C
AVSS1
AVSS 2
GN D
D VSS2
H P -O U T -L
H P -OU T -R
CB N
CB P
OP V E E
2 0 K _1 % _ 04
M IC_ S E NS E
14
15
LI N E 2 -L
LI N E 2 -R
R 36 8
3 9 . 2K _ 1 % _0 4
H P _S E N S E
16
17
MI C 2 _ L
MI C 2 _ R
18
S E N S E -B
19
20
JD R E F
MON O-O U T
21
22
MI C 1 -L _ R C 30 6
MI C 1 -R _R C 30 7
23
24
LI N E 1 -L
LI N E 1 -R
27
V R E F -A L C 26 9
MI C _ S E N S E [ 3 0 ]
R3 6 5
C 3 08
4. 7 K _ 0 4
10 0 p _5 0 V _ N P O _0 4
0 . 1 u_ 1 6 V _Y 5 V _0 4
C 50 2
0 . 1 u_ 1 6 V _Y 5 V _0 4
A U DG
ALC269
VT1802
P
R 52 3
20K_1%_04
5.
1K_1%_04
20 K _ 1 %_ 0 4
C5 1 2
EMI Require
*1 0 0 p_ 5 0 V _N P O_ 0 4
4 . 7 u_ 6 . 3 V _ X5 R _ 0 6
4 . 7 u_ 6 . 3 V _ X5 R _ 0 6
MI C 1 _ L
MI C 1 _ R
C3 0 1
28
30
29
LD O_ C A P
MI C 1 -V R E F O-R
MI C 2 -V R E F O
32
33
H E A D P H O N E -L
H E A D P H O N E -R
35
C B N - A L2 6 9
36
34
C B P -A L C 2 6 9
OP V E E -A L C 26 9
0 . 1 u _1 6 V _ Y 5 V _ 04
C3 0 4
2 . 2 u _6 . 3 V _ X5 R _0 6
ALC269 2.2u;
VT1802P 10u
C2 9 8
H E A D P H ON E -L [ 30 ]
H E A D P H ON E -R [ 3 0 ]
C2 7 2
A UD G
2 . 2 u _6 . 3 V _ X5 R _0 6
ALC269 2.2u
VT1802P NC
A U DG
2 . 2 u_ 6 . 3 V _X 5 R _ 0 6
S P K O U T L+
L2 4
F C M 10 0 5 K F -12 1 T 03
1
2
A LC 26 9 Q-V B 5-G R
J _ SPKL 1
S P K OU TL + _ L
C2 9 5
* 1 u_ 6 . 3 V _Y 5 V _0 4
85 2 0 4-0 2 0 01
*1 8 0p _ 5 0V _ N P O_ 0 4
MI C 1-V R E F O -L
S P K O U T L-
A UD G
17/16
S P K OU TL -_ L
A U DG
MI C 2 -V R E F O R 13 0
4. 7 K _ 0 4
J _ I N T MI C 1
I N T _ MI C
R 12 8
1K _ 0 4
Headphone Anti-Pop Circuit
R130
C2 8 9
8 8 2 66 -0 2 00 1
J_INTMIC1
2 1
6 8 0 p_ 5 0 V _X 7 R _ 0 4
3 .3 VS
F C M1 0 05 K F -1 2 1T 0 3
L23
C118
R 5 68
AL269
VT1802P
D
Q4 0
*2 N 70 0 2 W
R 5 69
* 4 . 7K _ 0 4
AZ_RST#
PD#
Spe a ke r w ire le ngth l e ss tha n 8 00 0mi ls , I t don't ne e d LC Fi lte r.
SPKO UTR+ ,R- ,L+ ,L- Tra ce wi dth
Spe a ke r 4 ohm- -- --- > 40 mil s
Spe a ke r 8 ohm- -- --- > 20 mil s
R5 7 0
R5 7 1
*1 0 K _0 4
*1 0 K _ 04
AUD G
C 53 8
* 10 u _ 6. 3 V _ X 5R _ 06
AUD G
MI C 1 _L
R3 4 3
1K _ 0 4
MI C 1 _R
R3 5 1
1K _ 0 4
AL269
VT1802P
680p
330p
MI C 1 -L [ 3 0 ]
MI C 1 -R
MI C 1 -V R E F O -R R 3 5 0
2. 2 K _ 0 4
MI C 1 -V R E F O -L R 3 4 5
2. 2 K _ 0 4
[ 3 0]
20 ms
4.7K_04
2.2K_04
Q 39
*2 N 7 0 02 W
Q 38
* A O3 4 1 5
G
E A P D _ MO D E
5V S
H E A D P H ON E - L
H E A D P H ON E - R
* 2 20 K _ 0 4
G
R343 & R351
R345 & R350
AL269
VT1802P
AL269
VT1802P
I N T _M I C
1K_04
75_04
C5 1 1
C5 1 4
4 . 7 u_ 6 . 3 V _X 5 R _ 0 6
4 . 7 u_ 6 . 3 V _X 5 R _ 0 6
J_SPKL1
2
1
*1 8 0p _ 5 0V _ N P O_ 0 4
1
2
C 1 18
3.3 VS_ AUD
1
2
C 2 93
2 . 2 u_ 6 . 3 V _X 5 R _ 0 6
FOR VOLUMN
ADJUST
C 50 3
HP _ S E N S E [3 0 ]
C2 7 9
31
4 7K _ 0 4
26
37
R3 6 7
49
[ 27 ] K B C _B E E P
1u _ 6 . 3V _ Y 5V _ 0 4
C 3 09
42
43
D 13
B A T 5 4 CW G H
A
C 3 BEEP
2 A
P VSS1
PVSS2
PCBEEP
R 36 9
V RE F
A Z _ S D IN0 _ R
[1 3 ] HD A _ S Y N C
3 . 3V S
L I N E 1 -L
L I N E 1 -R
S D A T A -O U T
2 2 p_ 5 0 V _N P O_ 0 4
[ 1 3 ] H D A _B I TC L K
S E NS E _ A
S en s e -B
5
[ 1 3 ] H D A _S D OU T
Q2 5
D
AU DG
13
S en s e A
S P K -L +
S P K -L -
DIGITAL
Closed to SB.
A UD G
AVD D1
AVDD 2
1 0 K _0 4
A
R B 7 51 S -4 0 C 2
39
46
R B 7 51 S -4 0 C 2
C
D1 9
PVD D1
PVDD 2
D1 8
[ 13 ] H D A _ R S T #
[ 27 ] K B C _ MU TE #
R 51 8
D VDD 1
HD A _ RS T #
L39
H C B 1 6 08 K F -1 2 1 T2 5
A
* R B 7 5 1 S -40 C 2
D V D D -I O
E A P D _M OD E C
D2 1
2.2K_04
4.7K_04
M I C 2 _L
M I C 2 _R
1 . 5 V S [ 1 9 , 3 1]
3 . 3 V S [ 3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 17 , 1 8 , 19 , 2 0 , 23 , 2 4 , 25 , 2 7 , 28 , 3 0 , 3 1, 3 6 ]
5 V S [ 11 , 1 2 , 19 , 2 0 , 25 , 3 0 , 31 , 3 6 , 37 ]
B - 30 Audio Codec ALC269

. . , , .
Schematic Diagrams
USB, Fan, TP, Multi-Conn

USB 2.0
FAN CONTROL
U3 8
F O N#
5 VS
5V S _F A N
[2 7 ] CP U _ F AN
1
2
3
4
80 mil
F ON
VIN
V OU T
VSET
A X 99 5 S A
G ND
G ND
G ND
G ND
8
7
6
5
U SBVC C
C 48 8
+
Port 1
C 94
0 . 1 u _1 6 V _Y 5 V _0 4
1 0 0u _ 6 . 3V _ B _ B
5 VS
5V S _ F A N
J_ F A N 1
J _ US B _ 1
R1 0 7
*0 _ 0 4
C 45 6
V+
1
2
*W C M2 0 12 F 2 S -S H O R T
R1 1 3
*0 _ 0 4
L13
A U S B _ P P 1_ R
0 . 1u _ 16 V _ Y 5 V _ 0 4
1 0 u_ 6 . 3 V _X 5 R _ 0 6
DA T A _ L
GN D
3 1 7 D E 0 4P S A 7A 2 C
[ 2 7] C P U _ F A N S E N
3. 3 V S
W24 0HU
31 7DE0 4PSA 7A 2C
W25 0HU
1- 284- 8002 81 -1
R 20 2
0 . 1 u_ 1 6 V _Y 5V _0 4
3
4
[ 3 1 , 3 3] D D _ ON #
V IN1
V O UT 2
V IN2
V O UT 3
E N#
G ND
*2 8 mi l _ 06
C 1 13
R 12 9
R 12 7
1 0 K _ 04
1 0 K _ 04
C 11 4
C 11 5
4 7 p_ 5 0 V _N P O_ 0 4
4 7 p _5 0 V _N P O_ 0 4
1 u _ 6. 3 V _ Y 5 V _ 0 4
100 MIL
J _ TP2
F LG # V O U T 1
5V
C5 0 1
R 13 1
L62
H C B 1 6 08 K F -1 2 1T 2 5
G_ U S B V C C
U4 0
F L G#
Sheet 30 of 43
USB, Fan, TP,
Multi-Conn
5 V S _ TP
5 VS
*0 _0 4
4 . 7K _0 4
CLICK B'd CONN
US B V CC
R5 2 4
C 49 2
C 4 93
C 49 1
0 . 1 u_ 1 6 V _Y 5V _0 4
*0 . 1u _ 1 6V _ Y 5V _ 0 4
1 0 u_ 6 . 3V _X 5 R _ 0 6
1
2
3
4
TP _ D A TA [ 2 7 ]
TP _ C L K [ 2 7 ]
8 5 2 01 -0 4 05 1
R T 9 7 15 B GS
If system has AP ON function, uses J_SW1

If system has no AP ON function, uses J_SW2
POWER SWITCH B'd CONN
0 . 0 1 u_ 1 6V _ X 7 R _ 0 4
3. 3 V S
C2 9
C 27
J _ SW 1
J _ A U D I O1
[ 2 9 ] H E A D P H O N E -R
[ 2 9 ] H E A D P H O N E -L
R 33 9
R 34 0
2 2 0_ 0 4
2 2 0_ 0 4
[ 29 ] M I C _ S E N S E
[2 9 ] HP _ S E NS E
[1 7 ] US B _ P N 9
[ 17 ] U S B _P P 9
[ 2 9 ] S P K OU TR +
[ 2 9 ] S P K OU TR -
H E A D P H ON E -R R
H E A D P H ON E -LL
M I C _ S E NS E
SPK_ H P#
H P _S E N S E
S P K O UT R+
S P K O UT R-
A UD G
A P _K E Y #
A P _ K E Y # [ 2 7]
0. 0 1 u _1 6 V _ X7 R _ 0 4
D
0 . 0 1u _ 1 6V _ X 7 R _ 04
J _ SW 2
1
2
3
4
5
6
7
8
9
10
20 mi l
Q9
* MT N 7 0 02 Z H S 3
M_ B T N #
W EB_ W W W #
W E B _ E MA I L#
L ID_ S W #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
8 72 1 3-1 4 0 0G
[ 2 9] M I C 1 -R
[ 2 9] M I C 1 -L
3 .3 V
3 .3 V
M_ B TN # [ 31 ]
W E B _ W W W # [ 27 ]
W E B _ E MA I L # [ 27 ]
LI D _S W # [ 1 1 , 2 7]
20 mi l
M_ B T N #
W EB_ W W W #
W E B _ E MA I L #
LI D _ S W #
AP_ KEY#
8 8 48 6 -0 80 1
C 5 4 6 C 5 47
A P _ ON
A P _ ON [ 3 1 ]
VIN
* 50 5 0 0-0 1 0 41 -0 01 L
[ 2 , 3 , 8 , 11 , 1 3 , 14 , 1 5, 17 , 1 8, 1 9 , 2 0, 2 2 , 2 3, 2 6 , 2 8, 3 1 , 3 3, 3 4 , 3 5]
[ 1 1, 1 2 , 1 9, 2 0 , 2 5, 2 9 , 3 1, 3 6 , 3 7]
[ 2 0, 2 3 , 2 6, 3 1 , 3 3, 3 4 , 3 5]
[ 2 6]
[ 1 1, 3 1 , 3 2, 3 3 , 3 4, 3 5 , 3 6, 3 7 , 3 8]
[ 3, 9 , 1 0 , 11 , 1 2 , 13 , 1 4 , 15 , 1 6, 17 , 1 8, 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 7, 2 8 , 2 9, 3 1 , 3 6]
1
2
3
4
5
6
7
8
* 0. 1u _ 16 V _ Y 5 V _ 04
5V
3 . 3V S
CLOSE TO J_SW1
1.1A 60mils
C2 2 3
*0 . 1 u _1 6 V _ Y 5V _ 0 4
Audio B'd CONN
3 .3 V
5 VS
5V
U S B V CC
VIN
3 .3 VS
USB, Fan, TP, Multi-Conn B - 31

. . , , .
CO-LAY USB 3.0 J_USB2
[ 1 7 ] U S B _ OC # 01
JFAN
3
DA T A _ H
GN D 1
G ND 2
GN D 3
G ND 4
[ 1 7] U S B _ P P 1
A U S B _ PN1 _ R 2
G ND1
GN D 2
G ND3
GN D 4
[ 1 7] U S B _ P N1
1
2
3
8 5 20 5 -03 7 0 1
C2 0 5
Schematic Diagrams
5VS, 3VS, 1.05VS, 1.5VS_CPU

SYS5 V
VIN
V A
SYS5 V
V IN 1
P R 22 4
PC2
P C 1 10
P C 1 11
0 . 1u _ 5 0V _Y 5V _0 6
0 . 1 u _5 0 V _ Y 5 V _ 0 6
0 . 1 u _5 0 V _ Y 5 V _ 0 6
P R 22 2
1 0 K _ 04
ON
DD_ON"L" T O
"H" FROM EC
1 0 K _0 4
D D _ ON #
1
V IN 1
7
V IN
[ 30 ] A P _ O N
P R2 2 6
1 K_ 0 4
P R2 2 7
1 K_ 0 4
R3 7 1
D D _ O N _ L A TC H
6
M_ B T N #
1 K _0 4
*1 0 K _ 0 4
P Q6 7 A
M TD N7 0 0 2Z H S 6 R
D D_ O N
R 60 4
P W R _S W #
1 K_ 0 4
5
I N S T A N T- ON
P W R_ S W # [2 7 ]
P R1 2 3
1 0K _ 0 4
11/02
V IN
[ 26 , 2 7 , 32 ] D D_ O N
D D _ ON
P Q6 7 B
MT D N7 0 02 Z H S 6 R
2 G
S
4
P R 22 1
VD D3
5 G
[ 1 5 , 2 6 , 27 ] S U S B #
S
1
10/28
GN D
P 2 8 08 B 0
P R2 3 4
S U S B [ 3 , 6, 3 3 , 3 4]
8
VA
[ 3 0 ] M_ B T N #
S US B
D D _ ON # [ 3 0 , 3 3 ]
PU 7
P R 22 0
ON
1 0 0K _ 0 4
ON
1 00 K _ 0 4
10/29
5V
ON
ON
3 .3 V S
C 5 04
C 5 05
C5 0 6
C2 4 7
C 22 4
C 2 25
0 . 0 1 u_ 1 6 V _ X7 R _0 4
0 . 0 1 u _1 6 V _ X7 R _0 4
0. 0 1 u _1 6 V _ X7 R _0 4
0. 0 1 u _1 6 V _ X 7R _ 04
0 . 0 1 u_ 1 6 V _X 7 R_ 0 4
0 . 0 1 u_ 1 6 V _ X7 R _0 4
1.5VS
S Y S 15 V
5V
5VS
P R2 1 8
P R2 2 5
S Y S 1 5 V V D D5
3A
Power Plane
P Q 6 6A
M T N N2 0 N 0 3 Q8
8
2
7
1
5 VS
4
1 M_ 0 4
P C 2 19
P R 23 2
0 . 1 u _1 6 V _ Y 5 V _ 0 4
*1 0 0 K _ 04
P R 23 1
5 V _ EN1
P Q6 4 B
MT N N 20 N 03 Q 8
5
S US B
P Q 63
MT N 70 0 2 Z H S 3
P C2 2 1
DD _O N #
P C 2 22
P Q6 6 B
M TN N 2 0 N 0 3 Q8
5
4 70 p _ 50 V _ X 7 R _ 04
1
1 0 0_ 0 4
47 0 p _5 0 V _ X 7R _ 04
P Q 6 5B
M TN N 2 0 N 0 3 Q8
S U S B [ 3 , 6, 33 , 3 4 ]
4 7 0p _ 5 0 V _X 7 R _ 0 4
6
PJ 2 0
P R 21 9
1 0 u _6 . 3 V _ X 5R _ 06
P C2 1 2
5 VS_ EN 1
1 0 0K _ 0 4
P C 2 16
0 . 1u _ 1 6V _Y 5V _0 4
1 .5 VS_ EN
P R 2 23
1 M_ 0 4
P C2 1 7
1. 5 V S _ L O
3A
5V
M T NN 20 N 03 Q8
2
1
8
7
P Q6 4 A
MT N N 2 0N 0 3Q 8
8
2
7
1
NMO S
P Q6 5 A
V DD 5
1 .5 VS
NM OS
1M _ 04
NMO S
S Y S 1 5V
1 .5 V
Sheet 31 of 43
5VS, 3VS, 1.05VS,
1.5VS_CPU
*4 0m i l
2
PJ 1 9
ON
1.5VS_CPU
* 4 0m i l
ON
11/03
3.3VS
S Y S 1 5V
8
7
P R2 3 3
3 .3 VS
P Q 20 A
M TN N 2 0 N 0 3 Q8
2
1
1 M_ 0 4
*1 00 K _ 0 4
4
3 . 3 V _E N 1
P Q 2 1B
M TN N 2 0 N 0 3 Q8
PC 9 4
P R 10 2
P R7 1
0 . 1u _ 1 6V _ Y 5V _0 4
1 0 u _6 . 3 V _ X 5R _ 06
1 00 _ 0 4
*1 M_ 0 4
3 .3 V S_ E N1
P Q 20 B
MT N N2 0 N 0 3 Q8
P C 89
D D _O N #
2 20 0 p _5 0 V _ X7 R _0 4
4 7 0p _ 5 0V _ X 7 R _ 0 4
S US B
8
7
P Q4 8 A
*M TN N 2 0 N 0 3 Q8
2
1
1 .5 VS _ CP U E N
P Q 16
MT N 70 0 2 Z H S 3
* 2 20 _ 0 4
P C1 8 0
P C 1 79
*0 . 1 u_ 1 0 V _ X7 R _0 4
* 10 u _ 6. 3V _ X 5 R _ 0 6
P Q4 8 B
* MT N N2 0N 0 3Q 8
P C4 6
5
SU SB
P Q1 1
* MT N7 0 0 2Z H S 3
*2 20 0 p _5 0 V _ X 7R _ 04
S
P R7 2
NMO S
P C9 6
PC9 5
5
10A
PJ15 MUST SHORT
SYS1 5 V
P R 10 9
Power Plane
1 M_ 0 4
V DD 3
1 . 5 V S _ C P U _L O
PR1 1 1
3 . 3V
3A
P Q2 1A
M T N N 20 N 0 3 Q8
2
1
8
7
1 .5 V _ CP U
PJ 1 5
* OP E N _5 A
2
1
3A
3. 3 V S _ L O
V DD 3
S Y S 15 V
NM O S
NMO S
1 .5 V
3.3V
3 . 3 V [ 2 , 3 , 8, 1 1 , 1 3 , 14 , 1 5 , 17 , 1 8 , 1 9, 2 0 , 2 2, 23 , 2 6 , 28 , 3 0 , 3 3, 3 4 , 3 5]
1 . 5 V S [ 1 9 , 29 ]
5 V S [ 1 1 , 1 2, 1 9 , 2 0 , 25 , 2 9 , 30 , 3 6 , 3 7]
V I N [ 1 1, 30 , 3 2 , 33 , 3 4 , 3 5, 3 6 , 3 7, 3 8 ]
S Y S 1 5V [ 32 , 3 4 ]
3. 3 V
ON
ON
V A [3 8 ]
1 . 5V _ C P U [ 3 , 6 ]
1 . 5V [ 3, 6 , 8 , 9 , 1 0, 2 0 , 2 6, 28 , 3 3 ]
5 V [ 2 0, 2 3 , 2 6, 30 , 3 3 , 34 , 3 5 ]
V IN1 [3 2 ]
3 . 3V S [ 3, 9, 1 0 , 1 1, 1 2 , 1 3 , 14 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0, 23 , 2 4 , 25 , 2 7 , 2 8, 2 9 , 3 0, 3 6 ]
V D D 3 [ 13 , 2 2 , 2 4, 2 7 , 3 2, 38 ]
V D D 5 [ 26 , 3 2 ]
B - 32 5VS, 3VS, 1.05VS, 1.5VS_CPU

. . , , .
Schematic Diagrams
VDD3, VDD5
V RE F
P R1 95
* 0 _0 4
P R7 7
0_04
P C1 9 5
1 u _ 10 V _ Y 5 V _ 0 6
P R 19 8
P R1 9 7
E N_ 3 V
E N_ 5 V
P C2 0 1
1 00 K _ 0 4
1 00 K _ 0 4
P C1 9 8
1 00 0 p _5 0 V _ X7 R _0 4
P U1 1
EN1
VFB1
V IN
24
V O1
P C1 9 9
8
10
uP6182
* RB 0 5 4 0S 2 P R2 0 9
1
2
3
18
17
16
25
15
VR EF
V R E G5
P R2 1 5
* 0 _0 4
P R2 12
* 0 _0 4
P R 2 1 3 P R2 10
P R2 11
2 .2_ 0 6 * 0 _0 4
0_04
V R E G5
M990125
E N _3 V 5 V
P R9 0
S
MT N7 0 02 Z H S 3
* 0 _0 4 E N_ 3 V
P R 82
0_04
10 0 K _ 0 4
PR8 4
M T N 70 0 2 Z H S 3
[2 6 ,2 7, 3 1 ] DD _ ON
PJ 1 1
*4 0 m il
0. 1u _ 1 0V _ X 5 R _ 0 4
PC7 1
P Q1 8
DD _O N_ E N _V D D
V IN
P C2 0 7
P D2 3
A
R B 0 54 0 S 2
C
1 0 0 0p _ 5 0V _ X 7 R_ 0 4
Rb
P R 2 28
P R1 9 6
* 0 _0 4
1 9. 1 K _ 1 % _0 6
Sheet 32 of 43
VDD3, VDD5
PC 6 3
PC5 8
+
2 2 0 u_ 6 .3 V _6 . 3 *6 .3 *4 . 20 . 1u _ 1 6V _ Y 5V _0 4
S Y S 5V
S Y S 10 V
P C6 9
P C2 0 8
P D1 9 R B 0 54 0 S 2
2 20 0 p _5 0 V _ X7 R _0 4
4 .7 u _2 5 V _ X 5R _ 08
R B 0 5 40 S 2
1 u_ 1 0 V _ Y 5 V _ 06
P C2 10
E N_ 5 V
0 .0 1 u_ 5 0 V _ X7 R_ 0 4
10 K _ 0 4
P R 86
R B 0 54 0 S 2
A
V R E G5
P D2 4
P Q7 3
*5 m m
P C6 1
0_04
0 .0 1 u_ 5 0 V _ X7 R_ 0 4
P D2 2
C
P C2 09
V R E G5
P R7 5
P D2 1
P 1 2 0 3B V
A
*R B 0 54 0 S 2
P R2 1 4
P J 10
1
3 0K _ 1 % _0 6
11/05
V IN 1
[3 8 ] US B _A C _ IN
C
P Q1 2 P D 9
E N_ A L L
* 6 80 K _ 1 % _0 4
VDD5
5A
V D D5
PL 9
4 . 7 UH _ 6.8 * 7. 3 *3 .5
2
VCL K
EN 0
13
A
* SK34SA
C S O D 1 40 S H
A
4 . 7 u _2 5 V _ X5 R _0 8
Ra
19
PD 7
PC 7 4
4 .7u _ 2 5V _X 5 R_ 0 8
S Y S 5V
1
PD 8
V R E G5
P C2 0 5
P Q 13
P 1 2 03 B V
4
1
2
3
L GA TE 1
3
2
1
20 K _ 1 %_ 0 4
21
5
6
7
8
L GA T E 2
L DO 5
P HA S E 1
V IN
12
PH ASE2
S K IP S E L
P Q 60
P 1 2 03 B V
C
P D5
0 .1 u _5 0 V _ Y 5 V _ 0 6
20
P R1 9 4
P C2 0 6
3
2
1
8
7
6
5
13 K _ 1 %_ 0 6
10 0 p _5 0 V _ N P O _0 4
2 2 0u _ 6 . 3 V _6 . 3 *6 . 3 * 4 . 2
0 . 1 u _1 6 V _ Y 5V _0 4
P C6 5
P C6 2 P D 6
UGA TE 1
11
PC7 2
P R7 6
S Y S 5V
B OO T1
U GA T E 2
14
0 .1u _ 1 0V _X 7 R_ 0 4
22
B O OT 2
0 .1 u_ 1 0 V _X 7 R_ 0 4
P L1 0
4 .7 UH_ 6 .8 *7 .3 *3 . 5
2
1
P C2 0 4
23
*S K 3 4 S A
A
8
7
6
5
P C 20 3
SY S3 V
PJ 8
*5 m m
P OK
P D2 0
A
R B 0 54 0 S 2
C
S Y S 15 V
PQ 1 4
P C6 8
MT N7 0 02 Z H S 3
2 20 0 p _5 0 V _ X7 R _0 4
V IN [ 1 1,3 0 ,3 1,3 3 ,3 4, 35 , 3 6 , 37 ,3 8 ]
V IN 1 [ 31 ]
S Y S 15 V [3 1 ,3 4]
V D D 5 [2 6, 3 1 ]
V D D3 [1 3, 2 2 , 2 4 , 27 ,3 1 ,38 ]
VDD3, VDD5 B - 33
. . , , .
5A
V D D3
2
L DO 3
1 u _ 10 V _ Y 5V _ 0 6
P Q 56
P 1 2 03 B V
*1 0 K _ 04
5
6
7
8
4 .7 u_ 2 5 V _X 5 R_ 0 8
GND P A D
GN D
4.7 u _ 25 V _ X 5R _ 08
VDD3
P R2 0 1
C S O D 1 40 S H
VO 2
P C 64
7
P C2 0 0
VREF
V IN
TO NSEL
EN 2
V RE G 3
VFB2
1 0 0 0p _ 5 0V _X 7 R_ 0 4
Schematic Diagrams
Power 1.5V/0.75V/1.8VS
V IN
P D4
PU 4
1
2
3
P R 1 92
21
VTT
DR VH
1
P C1 9 4
P C5 5
PC 5 4
20
V T T GN D
P R8 0
0_ 0 6
* OP E N _ 1 2A
P G OO D
S 3
* 10 K _ 1 % _ 04
GN D
NC
NC
5
6
7
8
0_06
P R9 2
1 0 0 K_ 0 4
D D R 1 . 5 V _ P W R GD
P R1 1 8
5V
1 0K _ 1 % _ 0 6
[1 5 ]
4 7 K _ 04
PR 9 8
[ 1 5 , 27 ] S U S C #
MT N 7 0 0 2 Z H S 3
S
P C8 2
PQ 1 9
* 0 . 1u _ 1 6 V _ Y 5 V _ 0 4
PQ 2 4
S
* MT N 70 0 2 Z H S 3
P J 12
*4 0 m i l
[ 3 0 , 3 1 ] D D _ ON #
P Q2 2
0. 1 u _ 1 6V _ Y 5 V _0 4
G
S
S US B
P Q2 3
MT N 7 0 0 2 Z H S 3
G
10 0 K _ 0 4
V T TE N
1 0 K _ 1 % _0 6
P C8 4
1 0 0K _ 0 4
P R1 0 3
P R1 1 7
5V
P R9 1
25
12
P R7 3
PR 9 9
* 10 0 0 p _5 0 V _ X 7 R _ 0 4
P R1 0 1
5V
PC 4 9
P C 1 69
3 .3 V
10
VD DQ SET
V D DQ S E T
P C7 9
S 5
P C8 0
P GO OD _ 61 6 3
11
V D DQ S NS
*M D U 26 5 4
2 .2 _ 0 4
1u _ 1 0 V _ Y 5V _0 6
*M T N 7 0 0 2Z H S 3
*1 0 _0 6
13
1 u _ 1 0V _ Y 5 V _ 0 6
* 2 2_ 0 4
P Q5 7
SU SB
P R2 0 8
Sheet 33 of 43
Power 1.5V/0.75V/
1.8VS
P R1 9 3
0_06
1
2
3
1
2
3
P R8 9
PC 7 6
P R2 0 6
5V
PQ 5 0
M D U 26 5 44
C S O D 14 0 S H
C O MP
15
14
P D 17
5
6
7
8
P V CC 5
V CC 5
5V
6 . 1 9K _ 1 % _ 0 6
*5 . 1 _0 6
V T T RE F
PC7 5
*1 0 0 0 p_ 5 0 V _ X 7 R _ 0 4
M T N 7 0 0 2Z H S 3
1. 5V _CTRL1
1. 5_ CTRL0
V olta ge
1
1
0
1
0
1
1 .55 V
1 .60 V
1 .65 V
1 .70 V
3 .3 V
3 .3 V
5V
10 K _ 0 4
1 u_ 1 0 V _ Y 5 V _ 0 6
PU 5
3A
V C NT L
4
P R1 0 5
1 0 0K _0 4
E N1 .8 V S
V O UT
2
GN D
P C6 6
PC 8 5
PC 8 3
0 . 1 u _1 6 V _ Y 5 V _ 0 4
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
M TN 7 00 2 Z H S 3
0 . 1u _ 1 6 V _Y 5V _0 4
[ 3 , 6 , 3 1, 34 ] S U S B
V FB
P C9 0
P Q 15
SU SB
P R7 8
1 . 27 K _ 1 % _ 04
EN
AX6 615ESA
11/0 9
GS7113
6-02-07113-320
AX6610
6-02-06610-320
0 . 1 u_ 1 6 V _ Y 5 V _ 04
3
5V
1 .8 V S
PJ 7
1
V O UT
1 0 u _6 . 3 V _ X 5 R _ 0 6
V IN
V IN
P OK
V1 .8
P C 57
1 . 8 V S _ P W R GD
PC 5 9
5
9
7
10 u _ 6. 3V _ X 5 R _0 6
2A
[ 3 , 1 5 ] 1 . 8 V S _ P W R GD
1.8VS
P C 91
PC6 7
P R1 1 0
CS
0 . 1 u _ 10 V _ X 7 R _ 0 4
0_06
P R 83
P C4 8
8 2p _ 5 0V _N P O _0 4
P R7 9
1K _ 1 % _ 0 4
* OP E N _ 3A
[ 6 , 1 8, 1 9 ]
[ 1 1 , 3 0, 3 1 , 3 2 , 3 4, 3 5 , 3 6 , 3 7, 3 8 ]
[ 2 0 , 2 3 , 2 6, 3 0 , 3 1 , 3 4, 3 5 ]
[ 2 , 3 , 8 , 11 , 1 3 , 1 4, 15 , 1 7 , 1 8, 19 , 2 0 , 2 2, 2 3 , 2 6 , 2 8, 3 0 , 3 1 , 3 4, 3 5 ]
[ 3 , 6 , 8 , 9 , 1 0, 2 0 , 2 6 , 2 8, 3 1 ]
[ 9, 1 0 ]
B - 34 Power 1.5V/0.75V/1.8VS
. . , , .
1 .8 VS
VIN
5V
3 .3 V
1 .5 V
V T T _ ME M
* 5 60 u _ 2 . 5V _6 . 3 *6
MO D E
P C 70
P R8 1
16
P C 1 84
0. 1 u _ 1 6V _ Y 5 V _ 0 4
*0 _ 0 6
P GN D
C S _ GN D
P C 52
0 . 1 u_ 1 6 V _ Y 5 V _ 04
P R 2 02
GN D
4
P Q5 1
18
17
56 0 u _ 2. 5 V _ 6 . 6 *6 . 6 *5 . 9
*0 _ 0 6
D RV L
* 1 00 0 p _X 7R _ 06
5V
0 _0 6
P R 2 03
1 .5 V
PJ 6
19
V T T S NS
3
P R 2 05
30A
V D DQ
LL
1 0 u_ 1 0 V _ Y 5 V _ 0 8 10 u _ 1 0V _Y 5 V _ 08 * 1 0u _ 1 0V _Y 5 V _ 08
V DD Q
1.5V
PL 7
1 . 0 U H _ 11 . 5 *1 0 . 2 *3 . 0
1
2
3 . 3 _ 06
*OP E N _ 2 A
V T T_ M E M
* 1 5u _ 2 5 V _ 6. 3 * 4. 4 _ C
0 . 1 u _1 0 V _ X 7 R _ 0 4
22
VBS T
24
P C 1 86
0 . 1 u _5 0 V _ Y 5 V _ 0 6
PJ 1 8
P C1 8 8
4 . 7u _ 2 5 V _ X 5R _ 0 8
P C 60
23
V L DO IN
P C1 9 1
4 . 7 u _ 2 5V _ X 5 R _0 8
V DD Q
V T T _ ME M
P C 1 92
+
P Q5 2
MD U 2 6 57
R B 0 5 4 0S 2
0 . 1 u _5 0 V _ Y 5 V _ 0 6
P C5 6
1 0 u _ 10 V _ Y 5V _0 8
VTT_MEM
P C 51
5
6
7
8
5V
u P 6 1 63
Schematic Diagrams
Power 1.05VS
5V
PC73
PR74
1u_10V_Y5V_06
V1. 05
PC1890.1u_16V_Y5V_04
ME4626-G
560u_2.5V_6.6*6.6*5.9
PD3
CSOD140SH
*ME4626-G
PC182
C
PD18
C
5
6
7
8
PAD
PQ54
4
A
*SK34SA
A
RTN
17
PQ55
11/03
16A
PJ17
*OPEN-12mm
1
2
1.05VS
R182
*28mil_0 6
PJ9
1
PR95
PR88
0_04
5V
PR104
Sheet 34 of 43
Power 1.05VS
PC81
40 .2K_1%_04
*40mil
4 7p_50V_NPO_04
*9 0.9K_0 4
PR87 0_04
VCCIO_SENSE [5]
PC87
PC86
PR96
0.01u_1 6V_X7R_04
20p_ 50V_NPO_04 10 0K_1%_04
PR85 0_04
1.05VS_VTT
5V
PJ16
*OPEN_ 5A
2
1
3.3V
MTDN7 002ZHS6R
PQ68
MTN7002ZHS3
PC31
S
PJ3
*1mm
2
100K_04
PQ10
2N3904
E
R123
*100_04
0. 1u_16V_Y5V_04
C
B
Q19
MTN7002ZHS3
G
S
R573
C405
PQ75B
G
PR229
[2,3 ,5,18,1 9,20,36] 1.05 VS_ VTT
*10u_10V_Y5V_08
0.1u_16V_Y5V_04
C399
5
S
0.8 5V_ON [ 35]
10 /1
C414
2200p_50V_X7R_04
D
100K_04
1M_04
PR56
100K_04
1 0A
PQ74
P12 03BV
8
7
3
6
2
5
1
R420
PR55
10/1
NM OS
SYS1 5V
5V
1.05VS_VTT
1. 05VS
10K_ 04
6
D
PQ75A
MTDN70 02ZHS6R
G
S
1. 05VS_VTT_EN [ 15]
ON
[13,14, 15,19,2 0]
[6,3 5]
[ 3,9,10, 11,12,13 ,14,15, 16,17,18, 19,20,2 3,24,25, 27,28,29, 30,31,3 6]
[2,3,8 ,11,13, 14,15,17, 18,19,2 0,22,23, 26,28,30, 31,33,3 5]
[20, 23,26,30, 31,33,3 5]
[1 1,30,31, 32,33,35, 36,37,3 8]
[31,3 2]
1. 05VS
0. 85VS
3. 3VS
3. 3V
5V
VIN
SYS15V
Power 1.05VS B - 35
. . , , .
DL
3
4
PC53
*5.1_06
FB
GND
VCC
5
6
7
8
11/05
BST
VOUT
N.C
1
2
3
PGD
10
PL8
1. 0UH_ 11.5*10.2*3.0
1
2
1
2
1
2
3
15
16
LX
11
*1000p_X7R_06
[ 15] 1.05VS_PWRGD
EN
1.05VS
0. 1u_16V_Y5V_04
DH
12
N. C
13
10K_04
ILIM
PR107
1.0 5VS_PWRGD
N.C
3. 3V
N.C
14
PC77
560u_2. 5V_6. 6*6. 6*5. 9
1
2
3
*0. 1u_16V_Y5V_04
11/03
PC183
PQ53
ME4894-G
PC45
PU6
SC412A / uP6127
PC88
MTN70 02ZHS3
4.7u_25V_X5R_08
5
6
7
8
[3,6, 31,33] SUSB
0. 1u_50V_Y5V_06
8.2K_1%_04
PC50
RB0540S2
PR94
PQ17
PC190
1.05VS_EN
4.7u_25V_X5R_08
PD10
PR1 08
100K_04
PC187
0.1u_50V_Y5V_06
VI N
5V
Schematic Diagrams
Power 0.85VS
3. 3V
PC129
PR159
10K_04
0.022u_16V_X7R_04
0.725V 0.675V
0.85VS_PWRGD [15]
VIN
PR146
PD1
100_04
RB0540S2
C
FOR EMI
PL4
1. 0UH_6.8*7.3*3.5
1
2
PR62
0_04
11
12
13
14
15
PC25
*0_04
PR158
[ 6] VCCSA_VI D0
[ 6] VCCSA_VI D1
PR157
100_04
PQ36B
PD1503YVS
PR63
12K_1%_04
1 1/0 5
PC41
V0.85
PC168
PC40
PJ5
*OPEN-5mm
1
2
0.85VS
PC42
0. 1u_25V_X7R_06
CSP
0.85V_ON [34]
CSN
PR65
1. 3K_1%_04
*0.1u_16V_Y5V_04
100K_1%_04
0.01u_50V_X7R_04
47p_50V_NPO_04
6A
PR64
0_04
3
33K_1%_04
0.01u_16V_X7R_04
PR155
PR173
PC124
CSN
22_04
1u_10V_Y5V_06
PR150
21
20
19
18
17
16
PC27
CSP
1K_1%_04
GND
PHASE
LG
VCC
RT
CSP
0.1u_16V_Y5V_04
PR151
SET3
SET2
SET1
SET0
FB
220u_6. 3V_6.3*6.3*4.2
6
7
8
9
10
PQ36A
PD1503YVS
0. 1u_16V_Y5V_04
5
6
10K_1%_04
PC140
15K_1%_04
PU9
uP6122
5
4
3
2
1
PR144
EAP
SS
POK
UG
BOOT
PR36
1
2
POK
PR145
10K_1%_04
COMP
VID0
VID1
EN/PSM
CSN
PR35
10K_1%_04
Sheet 35 of 43
Power 0.85VS
PR148
10K_1%_04
PC131
12K_1%_04
PC34
PR34
0. 1u_50V_Y5V_06
9.3K_1%_04
A
9.3K_1%_04
1 1/0 4
0.1u_50V_Y5V_06
PR147
0. 1u_50V_Y5V_06
5V
PR33
PC173
VIN
0_04
PC47
PR137
PC197
0. 1u_50V_Y5V_06
4. 7u_25V_X5R_08
PC154
PC153
VCCSA_VID1
0. 1u_50V_Y5V_06
4. 7u_25V_X5R_08
0.8V
PC155
0.9V
VCCSA_VID0
PR149
VCCSA_SENSE [6]
0_ 04
5V [20,23,26, 30,31,33,34]
0. 85VS [6]
VI N [11,30,31, 32,33,34,36,37, 38]
3.3V [2,3, 8,11,13,14,15, 17,18,19,20,22, 23,26,28,30,31, 33,34]
B - 36 Power 0.85VS
. . , , .
Schematic Diagrams
Power V-Core1
P R2 2
PC 1 1
1.05VS_VTT
1 0 _ 04
6 80 p _ 5 0V _ X 7 R _ 0 4
1 3 0 _1 % _ 0 4
PR 1 2
P R 1 9 1 . 2 1 K _ 1 %_ 0 4
PC 7
* 7 5_ 0 4
PUT COLSE
TO VCORE
Phase 1
Inductor
RT 4
1
5 6 0 0 p_ 5 0 V _ X 7R _ 04
A_G ND
H_ CP U_ S V ID DA T
H_ CP U_ S V ID CL K
H_ CP U_ S V ID A L RT #
[ 5 ] H _ C P U_ S V I D D A T
[ 5 ] H _ C P U_ S V I D C L K
[ 5 ] H _ C P U_ S V I D A L R T #
B~ 4 35 0
2 4. 9K _ 1 % _ 04
2
1 00 K _ N T C _ 0 6_ B
P R1 3 1
DIFFO UT
P R1 0
T RBST
PR 1 5
5 4 . 9 _ 1% _ 0 4
P R2 0
TS ENSE
P C1 1 3
1 0 0p _ 5 0V _N P O _0 4
1 0 0 _1 % _ 0 4
P R1 3 0
FB
VCORE_1
1 K_ 0 4
PC 1 2
22 p _ 50 V _ N P O_ 0 4
P R 1 41
P R2 7
P R2 1
C S P 1 [ 3 7]
P R 1 33
1 6 5 K _ 1 %_ 0 6
PR 3 1
10/29
P R 18 9
10 0 _ 04
P R 28
P R 12 8
[ 5 ] V C OR E _ V S S _ S E N S E
0 _0 4
1 2 . 1K _1 % _ 0 4
V S S _ S E N S E _ 6 1 31
13 7 K _ 1 % _0 6
C S P 3 [ 3 7]
P C 15
1 20 0 P
P C 14
2 70 p _ 5 0V _X 7 R _ 0 4
CSS UM
17
A_GN D
1 K _ 1 % _ 04
TSEN SEA
PC 3
PC 6
P R1 8
1
2
R T1
P R 1 69
8 . 2 5 K _1 % _ 0 4
A_GN D
CS N2
C SP2
CS N3
C SP3
CS N1
C SP1
D R ON
P W M1 / A D D R
P W M 3 / V B O OT
P W M 2/ I S H E D
IM A X
PW M A /IM AX A
V B OO T A
39
38
37
36
35
34
33
32
31
30
29
28
27
C S N 2 _5 V S
I MO NA
D R ON
P R 39
P R3 7
IC C_M AX _2 1h
= R*10 uA*25 6A/ 2V
A _G ND
C SNA
P R1 3 5
27 0 P _ 5 0V _X 7 R _0 4
1 13 K _ 1 % _ 04
20100805
A_GN D
P C 19
0 . 0 2 2 u_ 1 6 V _ X 7R _ 04
C S NA
[ 3 7]
C S P A [ 37 ]
1 1 5 K _ 1 %_ 0 6
PR 2 6
7 5 K _ 1 % _0 4
P R1 3 9
C S PA [3 7 ]
1 6 5K _1 % _ 0 6
RT 2
1
CO M P
IL IM
1 K_ 0 4
FBA
PC1 1 5
P C9
10 0 0 p _5 0 V _ X 7 R _ 0 4
10 0 K _ N T C _ 06 _ B
B~ 4 35 0
1 0 0p _ 5 0 V _ N P O _ 04
P R 1 29
3 . 0 1 K _ 1 %_ 0 4
P C 11 6
3 3 00 p _ 5 0V _X 7 R _ 0 4
P R 1 90 1 0 0_ 0 4
PUT COLSE
TO V_GT
Inductor
Q ua d VCC AXG
V ID1 = 1. 15 V
I cc Ma x =2 6A
R _LL= 3. 9m ohm
O CP~ 3 1A
V R _ ON
P R3
PJ 2
*6 m i l
* 1 00 K _ 0 4
P Q6 9 A
3
PR 5
G
1
* 10 K _ 0 4
* MT D N 7 00 2 Z H S 6 R
P R7
*1 0 m il _ 0 4
V R _O N
1
P Q6 9 B
PJ 1
[ 1 1 , 1 5, 27 ] A LL _ S Y S _P W R G D
*6 m i l
*M T D N 7 00 2 Z H S 6R
PC 1
PC 1 7
P R2 4
V_GT
*0 . 1 u _ 16 V _ Y 5V _0 4
47 0 p _ 50 V _ X 7 R _ 0 4
P C1 0
P R 25
6 8 P _ 5 0V _N P O_ 0 4
1 0 _0 4
P R 12 6 0 _0 4
PC 1 6
P R1 4 3
DIF FOU TA
A_GN D
A _G ND
[ 6 ] V C C _ G T _S E N S E
A_GN D
PJ 1 3
*6 m i l
7 . 5 K _ 1 %_ 0 4
[ 6 ] V S S _ GT _ S E N S E
A_GN D
A_GN D
P R1 3 2
P R 12 7 0 _0 4
1 0K _0 4
1 0K _0 4
2 0 . 5 K _ 1% _ 1 / 1 6W _0 4
OPTION:
DISALBE
V_GT
CSC OM PA
P R2 3
* 1 0K _0 4
P R1 5 2
1 5K _ 1 % _ 0 4
A_G ND
P R1 5 6
PR 3 8
11 3 K _ 1 % _0 4
P C2 1
A_GN D
1 0 00 p _ 50 V _ X 7 R _ 0 4
P C1 1 8
P R 1 91 1 0 0_ 0 4
PR 6
[3 7 ]
V R 1 _ P W M 3 [ 3 7]
5VS
P R 1 54
CO MPA
3 . 3V S
0_04
V R 1_ P W MA [ 3 7 ]
5VS
10 K _ 0 4
*6 m li
0 . 1 u _1 0 V _ X 5 R _ 0 4
A _G ND
Sheet 36 of 43
Power V-Core1
V R 1 _ P W M 1 [ 3 7]
V R1 _ P W M 3
P W M 2_ 6 1 3 1
I MA X _ 6 1 31
VR1_PWM A
V B O OT A
P R 41
* 0 _0 4
P R4 0
C SPPA
P R1 3 4
2 4 . 3 K _ 1% _ 0 4
5. 49 K _ 1 % _ 04
C SP1 [3 7 ]
I MO N
P C1 1 7
0 . 0 4 7u _ 1 0 V _X 7 R _0 4
4 1 . 2 K _ 1% _ 0 4
P J1 4
0. 1 u _ 1 0V _X 5 R _ 0 4
PUT COLSE
TO V_GT
HOT SPOT
P C2 3
P R4 3
CSS UM A
P R 1 40
2 4 K _ 1 %_ 0 4
C SP3 [3 7 ]
C S N1 [3 7 ]
5VS
CSN 3
CSP P3
CSN 1
CSP P1
DR ON
14
15
16
17
18
19
20
21
22
23
24
25
26
A_GN D
A_GN D
B ~3 9 64
1 0 0 K _ N T C _ 06 _ B
0 . 1 u _1 0 V _ X 7 R _ 0 4
P C 1 14
0 . 0 1u _ 5 0 V _ X7 R _0 4
V SNA_ 6 1 3 1
V S P A _6 1 3 1
1 u_ 6 . 3 V _ X 5R _ 0 4
*1 4 K _ 1 % _0 4
5. 49 K _ 1 % _ 04
VIN P R
0 . 0 4 7u _ 1 0 V _X 7 R _0 4
0_ 0 4
2 . 2 _0 6
P R1 5 3
0 _ 04
6131_VCC
P R 1 25
P C2 2
A_GN D
PR 8
V R_ ON
5VS
N C P 6 13 1 S
C S N3 [3 7 ]
CS N3 [3 7 ]
PU 1
IM ON A
[1 5 ] D E L AY _ P W RG D
VSP
T S E NS E
V R H OT #
SDI O
SCL K
AL E RT #
VR_ R DY
VR_ R DY A
ENA B L E
VCC
RO S C
VRM P
T S E NS E A
1 0 _ 04
PR 4 2
53
52
51
50
49
48
47
46
45
44
43
42
41
40
1
2
3
H_C PU_SVID DA T
4
5
H_C PU_SVID CLK
6
H_C PU_SVID ALRT#
VR_R DY
7
8
VR_R DY A
V R _ O N_ E N A B L E _ 61 3 1 9
10
P R1 4
1 0K _0 4 R O S C 1 1
V RM P _ VIN 1 2
TS E NS E A 1 3
1 0 K _0 4
0_04
PR 3 2
PC 2 0
1 0 0 0p _ 5 0V _X 7 R _0 4
A_G ND
A _G ND
TSEN SE
P R 2 30
[ 3 ] H _ P RO CH OT #
1 0 _ 04
CS N1 [3 7 ]
IL IM A
1 0 K _ 04
PR 1 1
* 1 5m i l _ 06
P R 1 42
VR 1_C SRE F
EP AD
D I F F OU T
VSN
TR BST
FB
C OM P
IL IM
D R O OP
C SCO M P
CSSU M
IO UT
CS R E F
N C2
NC 1
P R 16
T RBS T
PR 9
3.3 VS
PUT COLSE
TO VCORE
HOT SPOT
A_GN D
1 0 0_ 0 4
V C C _ S E N S E _6 1 3 1
P R1 8 8
VCORE
0 _0 4
VSN A
VSPA
FBA
D IF F OU T A
TR BSTA
CO M PA
IL IM A
D R O OP A
C S C OM P A
IO UT A
CSS UM A
C SPA
CS NA
P R 12 4
[ 5 ] V C OR E _ V C C _ S E N S E
1 0 0K _N T C _0 6 _ B
8 . 25 K _ 1 % _ 04
B~ 3 96 4
C SC OM P
1 0 00 p _ 5 0V _X 7 R _ 0 4
IM ON
PC 8
[ 1 1 , 12 , 1 9 , 2 0 , 25 , 2 9 , 3 0 , 31 , 3 7 ] 5 V S
[ 3 , 9 , 1 0, 1 1 , 1 2 , 1 3, 1 4 , 1 5 , 1 6, 1 7 , 1 8 , 1 9, 2 0 , 2 3 , 2 4, 2 5 , 2 7 , 28 , 2 9 , 3 0 , 31 ] 3 . 3 V S
[ 3 7 ] V _ GT
[ 5 , 37 ] V CO RE
[ 1 3 , 1 4 , 15 , 1 9 , 2 0 , 34 ] 1 . 0 5 V S
[ 1 1 , 3 0 , 3 1, 3 2 , 3 3 , 34 , 3 5 , 3 7 , 38 ] V I N
[ 2, 3 , 5 , 1 8 , 1 9, 2 0 , 3 4 ] 1 . 0 5V S _V TT
Power V-Core1 B - 37
. . , , .
0 . 1u _ 1 0 V _ X 7 R _ 0 4
PR1 8 7
R T3
P C5
[ 27 ] V C O R E _ ON
Qua d 4 5W C PU
VID 1= 0. 9V
Ic cMa x = 94 A
R_LL= 1 .9m ohm
OC P~ 12 0A
13 7 K _ 1 % _0 6
7 5 K _ 1 %_ 0 4
P C 13
4 . 0 2K _1 % _ 0 4 33 0 0 P _ 50 V _ X 7 R _ 0 4
Schematic Diagrams
Power V-Core2
EN
GN D 6
PQ 4 6
M D U 26 5 4
P Q2 8
*M D U 26 5 4
G
S
S
G
0 . 1 u _5 0 V _ Y 5 V _0 6
*1 5 m il _ 06
PR 6 8
*1 5 m il _ 06
CS N 3 [3 6 ]
G
G
VR EG_SWA_H G
VR EG_SWA
PW M
SW
EN
GN D 6
VCC
LG
11/04
P Q4 4
*M D U 2 6 5 4
PQ 4 3
M D U 26 5 4
VR EG_SWA_LG
11/0 9
C
PD 2
HG
BS T
N C P 5 91 1
V_GT
P R6 0
A
CS OD1 4 0 S H
*1 5 m il _ 0 6
25A
VGFX_CO RE
P C 37
+P C 1 47
*1 0 0 0p _ X 7R _ 06
G
S
VGFX_CORE
VGFX_CORE
PL 3
0 . 3 6u H _1 0 *1 0 *3 . 5
1
2
P AD
9
P C1 2 6
PR5 9
* 15 m i l_ 0 6
CS NA [3 6 ]
PR5 8
* 15 m i l_ 0 6
C S P A [ 3 6]
P R 61
*5 . 1 _ 06
+P C 16 4
3 30 u F _ 2 . 5V _9 m _ 6. 3 * 6
PQ 3 2
M D U 26 5 7
P C 12 8
CS P 3 [3 6 ]
* 3 30 u _ 2. 5 V _ 9 m _6 . 3 *6
0 . 2 2 u_ 1 0 V _ X7 R _0 6
P C 12 7
*4 . 7 u_ 2 5 V _ X 5R _ 08
2 . 2 _ 06
15 u _ 25 V _ 6 . 3 *4 . 4
VIN
P C3 0
0. 1u _ 5 0V _ Y 5 V _ 0 6
* 5. 1 _ 0 6
V C OR E [ 5 , 36 ]
V _ GT [ 3 6 ]
V G F X_ C OR E [ 6 ]
[ 1 1, 3 0 , 3 1, 3 2 , 3 3 , 34 , 3 5 , 36 , 3 8 ] V I N
[ 1 1, 1 2 , 1 9, 2 0 , 2 5 , 29 , 3 0 , 31 , 3 6 ] 5 V S
B - 38 Power V-Core2
. . , , .
* 3 30 U _ 2 . 5 V _ D 2
* 33 0 U _ 2 . 5 V _ D 2
* 33 0 U _ 2 . 5 V _ D 2
* 4. 7 u _ 25 V _ X 5 R _ 0 8
PR 7 0
P R 66
V C OR E
SK3 4 SA
P Q3 3
*M D U 2 6 5 7
3
4 9. 9 _ 1 %_ 0 4
4
25A
* 10 0 0 p_ X 7 R_ 0 6
P D1 1
VC ORE
P C 43
VR EG_SW3_LG
P AD
+P C 17 6 +P C 17 2 +P C 17 8 +P C 1 74 +P C 1 75 +P C 1 70 +P C 1 77 +P C 1 71
5 6 0u _ 2 . 5 V _6 . 6 *6 . 6 *5 . 9
P Q3 1
*M D U 26 5 4
P C 12 3
+
P U3
1 5 u_ 2 5 V _ 6. 3 * 4. 4
S
PQ 4 1
M D U 26 5 4
50A
[5 ,3 6 ] VCO RE
5 6 0u _ 2 . 5 V _6 . 6 *6 . 6 *5 . 9
LG 5
P Q4 5
MD U 2 6 54
P C 1 22
5 6 0u _ 2 . 5V _6 . 6 *6 . 6 *5 . 9
V CC
PL 5
0 . 3 6u H _1 2 . 9 *1 4 *3 . 8
1
2
VR EG_SW3_OU T
C S P 1 [ 36 ]
5 6 0u _ 2 . 5V _6 . 6 *6 . 6 *5 . 9
GN D 6
PR 5 2
P C3 8
C SN1 [3 6 ]
5 6 0u _ 2 . 5V _ 6 . 6 *6 . 6 *5 . 9
EN
V R E G_ S W 3 _ H G
SW
HG 8
PW M
* 4. 7 u _ 25 V _ X 5 R _ 0 8
D
G
BS T
P C1 2 1
*4 . 7 u_ 2 5 V _X 5R _ 08
PC 2 4
5VS
2 . 2u _ 6 . 3 V _X 5 R _0 6
3
4 9. 9 _ 1 %_ 0 4
4
0 . 2 2 u _1 0 V _ X7 R _0 6
N C P 5 91 1
PR 3 0
PR 5 4
*1 5 m il _ 06
P C1 2 0
P Q3 0
*M D U 26 5 7
5VS
PR 6 7
PC1 3 0
+
VIN
P C 18
1
[ 3 6 ] V R 1_ P W M 3
[ 3 6 ] D R ON
*1 5 m il _ 06
A
P C 1 25
* 5. 1 _ 0 6
P U2
[ 3 6 ] V R 1_ P W M A
PR 6 9
S K 34 S A
P R 57
2 . 2 _ 06
[ 3 6 ] D R ON
V CO RE
* 10 0 0 p_ X 7 R_ 0 6
P D 15
P AD
P Q4 0
MD U 2 6 57
Sheet 37 of 43
Power V-Core2
25A
VC ORE
P C 36
V R E G_ S W 1 _ L G
0 . 1 u _5 0 V _ Y 5 V _0 6
D
S
S
PQ 3 8
M D U 26 5 4
PC1 6 1
PL 6
0 . 3 6u H _1 2 . 9 *1 4 *3 . 8
1
2
V R E G_ S W 1 _ OU T
LG 5
V CC
11/03
SW
P R2 9
2 . 2 u _6 . 3 V _ X 5 R _ 0 6
2 . 2 u _6 . 3 V _ X 5 R _ 0 6
5VS
PW M
V R E G_ S W 1 _ H G
P C1 4 9
3
4 9. 9 _ 1 %_ 0 4
4
P R 1 38
[ 3 6 ] D R ON
HG 8
[ 3 6 ] V R 1_ P W M 1
N C P 5 91 1
BS T
P U8
P Q3 9
*M D U 26 5 7
D
PQ 2 9
M D U 26 5 7
0 . 2 2 u _1 0 V _ X7 R _0 6
P C 15 2
*4 . 7 u_ 2 5 V _ X 5R _ 08
P C 11 9
2 . 2 _ 06
*3 3 0 u F _2 5 V
P R1 36
P C1 3 3
+
1 5 u_ 2 5 V _ 6. 3 *4 . 4
P C2 2 3
+
* 4. 7 u _ 25 V _ X 5 R _ 0 8
VIN
VCORE_2
Schematic Diagrams
Charger, DC In
CHARGER
# Cha rge Current 3.0A

VA
# Cha rge Volt age 12.6V
VIN
1
2
3
0 . 1 u _5 0 V _ Y 5 V _ 06
0 . 1 u _5 0 V _ Y 5 V _ 06
P C 16 6
V IN
P C3 9
PC2 8
P C 44
P C 1 34
4 . 7 u_ 2 5 V _X 5 R _0 8
P C 15 1
4 . 7u _ 2 5V _ X 5 R _ 0 8
4 . 7 u_ 2 5V _X 5 R _0 8
P C1 5 7
4 . 7 u_ 2 5 V _X 5 R _0 8
P C 15 9
4 . 7 u_ 2 5 V _X 5R _0 8
P C 1 58
P C 13 9
*1 00 0 p _5 0 V _ X7 R _0 4
P C 13 8
4 . 7 u _2 5 V _ X 5R _ 08
5
6
8
0 . 1 u_ 5 0 V _Y 5 V _ 0 6
0 . 1 u_ 5 0V _Y 5 V _ 0 6
PC 4
P C 18 1
4. 7u _ 25 V _ X 5 R _ 0 8
0_04
4 . 7 u _2 5 V _ X 5R _ 08
PC3 3
PR 2
P Q 35 B
C 5 88
A P 6 9 0 1G S M
0 _0 4
P C 16 0
0 . 1 u_ 5 0V _Y 5V _0 6
P C 1 43
1 u _ 25 V _ 0 8
P D1 2
C
*0 _0 4
0 . 1 u_ 5 0 V _Y 5 V _0 6
11/03
*5 . 1_ 1 % _0 6
P R1 8 0
V_ BAT
P R 1 75
0 . 0 2 _1 % _ 32
R 6 09
PR1 6 4
PIN 25th
FOR2S CONNECT TO GND
FOR3S CONNECT N.C.
FOR4S CONNECT TO VREF PIN
0_ 0 4
R B 05 4 0 S 2
C E L LS
VA
P C1 5 6
PR1 7 2
PC1 4 6
PR1 2 2
P C 1 41
P L2
4. 7 U H _ 6. 8 * 7. 3 *3 . 5
11/05
P R4 7
V DD 3
* 0_ 0 4
AC
S M C_ B A T
A
32
31
30
29
28
27
26
25
V DD 3
P R1 8 2
10 K _ 0 4
VA
PC1 6 3
D T C1 1 4E U A
*0 . 1 u _5 0 V _ Y 5 V _ 06
P Q8
A O3 4 0 9
D
P R1 8 3
2 0 K _1 % _ 04
0 . 0 1u _ 50 V _ X 7 R _ 04
V _B A T
PR 5 1
3 0 0K _1 % _ 04
V O L T_ S E L
P R1 7 1
P R 17 6
S G ND 6
4 9 . 9K _1 % _ 04
P C1 4 5
* 22 p _5 0 V _ N P O _0 4
PC1 4 4
1 0 0 0p _ 50 V _ X 7 R_ 04 P R 1 7 4
2 2 K _1 % _ 04
PC1 4 8
1 0 0 0p _ 50 V _ X 7 R_ 04 P R 1 7 7
S GN D 6
S GN D 6
B A T _ V OL T _ R
S G ND6
S GN D 6
C
AC
A
D 8
B A V 99 R E C T I F I E R
B A T_ V O LT
CHARGE
CURRENT
ADJ
P R 17 0
1 K _ 1% _ 0 4
P C 16 2
D 7
C
AC
A
D 9
B A T_ D E T
1 K _ 1% _ 0 4
PD1 3
UD Z 1 6 B
T OTAL
POWER
ADJ
P Q4 2
PC1 4 2
1 0 0 p_ 5 0V _N P O_ 0 4
CT L 1
PR1 6 2
1 0K _1 % _ 04
VI N
C TL 1
GN D
VR EF
RT
C S
A DJ 3
BAT T
S GN D
S M D_ B A T
0 . 1u _ 5 0V _Y 5V _0 6
P C 1 36
S GN D 6
TRERMAL PAD
P C1 3 2
P C 13 5
A C _ I N # [ 2 6 , 2 7]
C
MB 3 9 A 13 2
P R 18 1
PR1 8 4
1 0 K _1 % _ 04
[ 32 ] U S B _ A C _ I N
VC C
-I N C 1
+ INC 1
A C IN
A C OK
-I N E 3
AD J 1
C OM P 1
D 6
C
AC
A
VA
24
23
22
21
20
19
18
17
33
3 9. 2 K _ 1 %_ 0 4
1
2
3
4
5
6
7
8
0 . 1 u _5 0 V _ Y 5 V _0 6
P U1 0
0 . 1 u_ 5 0V _Y 5 V _ 0 6
0 . 1u _ 5 0V _Y 5V _0 6
C T L2
CB
OU T -1
LX
VB
O U T -2
P GN D
C E L LS
0 . 1 u_ 5 0 V _Y 5 V _0 6
-I N E 1
OUT C 1
OU T C 2
+ IN C2
-I N C 2
A DJ 2
CO M P 2
C OM P 3
0 . 1u _ 5 0V _ Y 5V _ 0 6
9
10
11
12
13
14
15
16
0 . 1 u _5 0 V _ Y 5 V _ 06
P R 16 7
S GN D 6
2 2 K _1 % _ 04
Sheet 38 of 43
Charger, DC In
V _B A T
S G ND 6
10 K _ 1 %_ 0 4
P C1 5 0
PR4 9
PR5 3
P C3 2
60 . 4 K _ 1% _ 0 4
2 0 0K _ 0 4
0.5V/1AT O TA L _ C U R
[ 2 7 ] T OT A L _C U R
0 . 1u _ 5 0V _Y 5V _0 6
PR 4 8
0. 1 u _ 50 V _ Y 5 V _ 0 6
11/05
P R2 3 5
PI N17t h CONNECT
TO BAT CONN.
4 7 0K _ 0 4
0.5V/1A
C UR _ SE NS E
W250HU
0_04
P R 16 8
1 0 2K _ 1 % _0 4
E
P R1 6 1
[2 7 ]
[2 7 ]
[ 2 7]
[2 7 ]
V O LT _ S E L
VDD 3
V D D3
PQ 4
D T A 1 14 E U A
6
D
2
P R5 0
P R1 6 0
10 0 K _ 04
1 0K _ 0 4
2M _1 % _ 0 4
PR1 7 8
M T N 7 00 2 Z H S 3
P R4 4
P Q7 1 A
MT D N 7 00 2 Z H S106 R0 K _ 04
AT
AT
ET
OL T
2 PL 1 1
2 PL 1 2
2 PL 1 3
2 PL 1 4
S M C_ BA T _ R
S M D_ BA T _ R
B A T_ D E T_ R
B A T_ V O LT _ R
G
7 6 . 8K _1 % _ 04
W240HU
V C H G -S E L [ 2 7]
P Q2 6
MT N7 0 0 2Z H S 3
P Q 7 0B
6
5
S
1
1
P J4
*O P E N -1 m m
P Q 7 0A
M TD N7 0 0 2Z H S 6 R
[ 2 7] C E L L_ C ON TR OL
P R4 5
P C2 6
P R4 6
1M _ 04
S P Q 7 1B
M T D N7 0 0 2Z H S 6 R
1M _0 4
P Q3 4
M T N7 0 02 Z H S 3
G
D
[ 2 7 ] C H G_ E N
0 . 0 1u _ 5 0V _X 7 R _0 4
C T L1
M T D N 7 0 0 2Z H S 6 R
P R 1 79
4
3
2
1
J BATTA1
*B T D -05 T C 1 B
11/0 4
P R 16 3
1 7. 4 K _ 1 % _0 4
S MC _B
S MD _B
B A T_ D
B A T _V
PQ 6
G
V DD 3
C E L LS
F CM 10 0 5K F -12 1 T 03 1
F CM 10 0 5K F -12 1 T 03 1
F CM 10 0 5K F -12 1 T 03 1
F CM 10 0 5K F -12 1 T 03 1
*2 8 mi l _ 06
6-21-D34B0-105
4
3
2
1
J BATTA2
B T D-0 5 TI 1 G
S G ND 6
S GN D 6
V D D3 [ 1 3, 2 2 , 2 4, 2 7 , 3 1, 3 2 ]
VA [3 1 ]
V I N [ 11 , 3 0 , 3 1, 3 2 , 3 3, 3 4 , 3 5, 3 6 , 3 7]
S GN D 6
Charger, DC In B - 39
. . , , .
P C 13 7
# Tot al Power 60W
11/05
10 0 K _ 1 %_ 0 4
V_ BAT
PC 3 5
1 0K _ 1 % _0 4
2
1
* 0 . 1u _ 5 0V _ Y 5 V _ 0 6
P R1 8 5
0 _ 04
1 30 K _ 1 %_ 0 4
1 0 K _ 1 %_ 0 4
P C 1 65
0 . 1 u_ 5 0 V _Y 5V _ 0 6
P R1 8 6
P R 1 20
P Q3 5 A
A P 6 9 01 G S M
P R4
0 . 0 2 _1 % _ 32
3
2
1
*0 . 3 3 u_ 5 0 V _ 08
P C 10 9
PQ 2 5
M E P 4 43 5 Q8
PR 1
P C1 0 7
0 . 1u _ 5 0V _ Y 5 V _ 06
0 . 1 u _5 0 V _ Y 5 V _0 6
P C1 08
8
7
6
5
H C B 45 3 2 K -80 0 _ 18
P C 11 2
11/0 4
PL 1
1
2
G ND 1
G ND 2
*0 . 1 u _5 0 V _ Y 5 V _0 6
VA
4
P R 12 1
20 0 K _ 1% _ 0 4
JA C K 1
50 9 3 2-0 0 3 01 -0 0 1
0 . 1 u _5 0 V _ Y 5 V _0 6
P Q3 7
ME P 4 4 3 5Q 8
5
6
7
8
Schematic Diagrams
Click Board
CLICK BOARD
Sheet 39 of 43
Click Board
CGND
6-20-94A50-104
6-20-94AA0-104
6-20-94A70-104
CGND
1
CLED_PWR
2
CLED_ACIN
3
CLED_BAT_FULL
4
CLED_BAT_CHG
5
6
*85201-06051
6-21-91A00-106
6-21-91A20-106
11/ 04
SG
*KPB-3025YSGC
CGND CGND
CGND
BAT LED
CD26
*KPB-3025YSGC
CGND
CJ_TP3
1
CTP_CLK
2
CTP_DATA
3
CTPBUTTON_L
4
CTPBUTTON_R
5
6
85201-06051
CD27
Y
CGND
CJ_TP2
11/04
CGND CGND
6-52-55002-042
6-52-55002-04E
6-52-55002-042
6-52-55002-04E
6-21-91A00-106
6-21-91A20-106
CSW1~4
4
3
LIF T
KEY
RIG HT
KE Y
CSW1
TJG-533-S-T/R
CSW2
TJG-533-S-T/R
1
3
CTPBUTTON_L
CGND
CH3
1
9
8
7
6
2
3
4
5
MTH237D91
CGND
CSW3
*TJG-533-S-T/ R
2
4
CH1
1
9
8
7
6
2
3
4
5
CGND
CH4
1
9
8
7
6
2
3
4
5
MTH237D91
CGND
CGND
1
3
CTPBUTTON_L
CGND
6-53-3050B-042
MTH237D91
CGND
1
3
CTPBUTTON_R
CGND
6-53-3050B-042
2
3
4
5
2
4
RIGH T
KEY
5
6
2
4
5
6
1
3
LIFT
KEY
9
8
7
6
CH5
C95D95
6-53-3050B-042
CH6
HO-165X94_5NP
MTH237D91
CGND
CGND
CTPBUTTON_R
CGND
6-53-3050B-042
CH2
CSW4
*TJG-533-S-T/ R
2
4
5
6
2
1
5
6
CGND
CJ_TP1
1
CTP_DATA
2
CTP_CLK
3
4
85201-04051
CR4
*220_04 *220_04
3
CR3
P OWER ON
L ED
CVDD3
C5VS
CR2
*220 _04 *220_04
3
CR1
CC3
*0.1u_16V_Y5V_04
1
C5VS
CLED_BAT_FULL
SG
CC2
*0. 1u_16V_Y5V_04
CLED_BAT_CHG
CLED_PWR
CC1
0.1u_16V_Y5V_04
CLED_ACI N
CGND
B - 40 Click Board
. . , , .
Schematic Diagrams
Audio Board/USB
USB PORT
A _ U S B V CC
A _U S B V C C 2
A L5
H C B 1 6 08 K F -1 2 1T 2 5
60 mil
A _U S B V C C
AU 1
5
5 0mi ls
F L G# V O UT 1
A C9
1 0u _ 1 0V _ Y 5V _ 0 8
V I N 1 V O UT 2
V I N 2 V O UT 3
E N#
G ND
+A C 1
50 mils
A C5
0. 1 u _ 16 V _ Y 5 V _ 04
A C6
A J _ US B 1
8
0. 1 u _ 16 V _ Y 5 V _ 04
0. 1 u _ 16 V _ Y 5 V _ 04
A U S B _ P N2
R T9 7 1 5B G S
A GN D
A C7
1 00 u _ 6. 3 V _ B _ A
7
A G ND
AU SB_ PP2
A GN D A G N D
A R 10
A L 61
4
*1 0m i l _0 4
1
A GN D
A U S B _ P N2 _ R
6-02-09715-920
A R 11
DA T A _ L
DA T A _ H
*A W C M2 0 12 F 2 S -1 61 T 0 3
A G ND
V+
A U S B _ P P 2 _R
GN D1
G ND 2
GN D3
G ND 4
A_ 5 V
GN D
*1 0m i l _0 4
U S 04 0 3 6B C A 0 81
G ND1
GN D2
G ND3
GND 4
PIN SWAP
6-21-B49C0-104
6-21-B49B0-104
A GN D
AUDIO JACK
A MI C 1 -R
A MI C 1 -L
A_ 5 V
AL 6
F C M1 0 05 K F -1 2 1T 0 3
2
6
1
Sheet 40 of 43
Audio Board/USB
A J_ M I C 1
R
AC 1 0
A C4
2 S J -T3 5 1 -S 2 3
1 0 0p _ 5 0V _ N P O_ 0 4
1 00 p _ 50 V _ N P O _0 4
MIC IN
A J _ A U D I O1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A M I C 1 -R
A M I C 1 -L
AH
AH
AM
AS
AH
AU
AU
5
4
3
A MI C _S E N S E
AL 4
F C M1 0 05 K F -1 2 1T 0 3
E A D P H ON E -R
E A D P H ON E -L
IC_ S E N S E
P K _H P #
P _ S E NS E
S B _ P N2
SB_ PP2
A S P K OU TR +
A S P K OU TR -
6-20-B2800-106
BLACK
A H P _ S E NSE
A _A U D G
A S P K _H P #
A H E A D P H O N E -R
A R3
68 _ 0 4
A L2
F C M1 0 05 K F -1 2 1 T0 3
A H E A D P H O N E -L
A R5
68 _ 0 4
A L3
F C M1 0 05 K F -1 2 1 T0 3
8 72 1 3 -14 0 0 G
5
4
3
A J_ H P 1
R
2
6
L
1
2 S J -T3 5 1 -S 2 3
A R9
AR8
A C3
AC 2
*1 K _ 1% _ 0 4
*1 K _ 1 %_ 0 4
10 0 p _5 0 V _ N P O_ 0 4
10 0 p_ 5 0 V _N P O_ 0 4
HEA DPHONE
A _A U D G A G N D
6-20-53A00-114
BLACK 6-20-B2800-106
A _A U D G
A C1 4
0 . 1 u_ 1 6V _Y 5V _ 0 4
A C1 5
0 . 1 u_ 1 6V _Y 5V _ 0 4
A C1 3
0 . 1 u_ 1 6V _Y 5V _ 0 4
A C1 6
0 . 1 u_ 1 6V _Y 5V _ 0 4
A GN D
A _A U D G
AS P K O UT R+
AL 7
F C M 1 00 5 K F -1 21 T 0 3
1
2
A S P K OU TR -
AL 8
F C M 1 00 5 K F -1 21 T 0 3
1
2
A C1 1
1 00 0 p _5 0 V _ X7 R _0 4
A S P K OU T R+ _R
A S P K OU T R-_ R
A C8
18 0 p_ 5 0 V _N P O_ 0 4
A _A UD G
AH 1
C 5 9D 59
A H3
C5 9 D5 9
2
3
4
5
AH 2
1
9
8
7
6
2
3
4
5
M TH 2 76 D 1 1 1
A GN D
AH4
1
A C1 7
18 0 p _5 0 V _ N P O_ 0 4
A J_ S P K R 1
J_SPK1
2 1
1
2
8 5 20 4 -0 20 0 1
P C B F o o t p rin t = 8 52 0 4 -02 R
6-20-43150-102
6-20-43110-102
9
8
7
6
MT H 2 7 6 D 1 11
A GN D A G ND
A G ND
Audio Board/USB B - 41
. . , , .
TO M/B
Schematic Diagrams
Power Switch & LID Board

POWER SW & LED & HOT KEY
S _3 . 3 V S
S _ 3 . 3V
SR 2
S _ 3. 3 V S
SR 1
SJ _ SW 2
1
2
3
4
5
6
7
8
S M GN D
S _ V IN
* 50 5 0 0-0 1 0 41 -0 0 1L
8 8 48 6 -0 80 1
1 0 pin & 8 pi n co- la y
6-52-56001-023
6-52-56001-028
6-52-56000-020
6-52-56001-022
6-20-94K10-108
2
V CC
S C2
0.1 u _ 16 V _ Y 5 V _ 0 4
SD 1
S L I D _S W #
OU T
G ND
S D3
* HT -1 50 NB -DT
S M GN D
S A P _ ON
AC
SU 1
S C6
SAP_ O N
2 0m il
1 00 K _ 1 %_ 0 4
1
S M _B T N#
SW EB_ W W W #
S W E B _ E M A IL#
S L I D_ S W #
SC 1
MH 2 48 -A L F A -E S O
0 .1u _ 1 0V _ X 7 R_ 04
* 10 0 p_ 5 0 V _N P O_ 0 4
S M GN D
HT -1 50 N B -DT
S MG ND
S M GND
S M GN D
20 mil
20 mi l
S M _B T N #
S W E B _W W W #
S W E B _E M A I L #
S L ID_ S W #
S MGN D
S M GN D
S M GND
6-52-56001-023
6-52-56001-028
6-52-56000-020
6-52-56001-022
S M GND
SU1, SU2
6-02-00248-LC2
6-02-00268-LC1
3
1
6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
POWER BUTTON
HOT KEY
SPW R _ SW 1
T J G-5 33 -S -T / R
SW W W _ SW 1
T JG -5 33 -S -T / R
S M_ B T N#
1
3
2
4
5
6
2
4
5
6
1
3
S_ VIN
6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
WEB_EMAIL#
6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
WEB_WWW#
SW EB_ W W W #
11/04
2
4
6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
AP_KEY#
S R3
*1 0 0 K _1 % _ 04
S M A I L _S W 1
T J G-5 3 3-S -T/ R
1
3
SC 4
FOR E4120Q/E5120Q
SAP_ SW 1
T J G-5 33 -S -T /R
SW EB_ EM AIL #
1
3
2
4
SC 3
S R4
0_ 0 4
PSW1~8
0 .1 u_ 1 6V _Y 5V _ 0 4
0 .1 u _1 6 V _ Y 5 V _0 4
SAP_ O N
SC 5
5
6
FOR E5128Q
5
6
Sheet 41 of 43
Power Switch & LID
Board
*B A V 9 9 RE C TIF I E R
2 2 0 _0 4
2 0mi l
1
2
3
4
5
6
7
8
9
10
S D2
S _ 3. 3V
S _ 3 .3V
S R5
*4 7 K _ 04
0 . 1 u_ 1 6 V _Y 5 V _0 4
1
2
3
4
S MGN D
S M GN D
S M GND
S MGN D
S M GN D
S M GN D
S M GN D
S MG ND
S MGN D
FOR E4120Q/E5120Q
POWER BUTTON
SPW R _ SW 2
* TJ G-5 3 3 -S -T/ R
1
3
S M H1
2
4
S M_ B T N#
S MH 2
S M H5
H7 _ 0 D2 _3 H 7_ 0 D2 _ 3
2
3
4
5
S M H3
9
8
7
6
2
3
4
5
S M H4
9
8
7
6
2
3
4
5
9
8
7
6
5
6
SJ _ SW 1
LID SWITCH IC
C
S _ 3. 3V S
S _ 3 .3V
POWER
SWITCH
LED
MT H 23 7 D8 7
PSW1~8
3
4
S MGN D
6-53-3150B-245
6-53-3050B-240
6-53-3050B-241
S MGN D
1
2
S M GND
M TH 23 7 D8 7
S MG ND
M TH 2 37 D1 1 8
S MG ND
S MG ND
S M GN D
FOR E5128Q
B - 42 Power Switch & LID Board

. . , , .

Schematic Diagrams for Laptop Motherboard

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Schematic Diagrams for Laptop Motherboard

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Schematic Diagrams

Appendix B: Schematic Diagrams

CougarPoint - M 6/9 - Page B - 19

Power 0.85VS - Page B - 36

CPU 1/7 (DMI, PEG, FDI) - Page B - 3

CougarPoint - M 7/9 - Page B - 20

Power V-Core1 - Page B - 37

CPU 2/7 (CLK, MISC, JTAG) - Page B - 4

CougarPoint - M 8/9 - Page B - 21

Power V-Core2 - Page B - 38

CPU 3/7 (DDR3) - Page B - 5

CougarPoint - M 9/9 - Page B - 22

CPU 4/7 (Power) - Page B - 6

New Card, Mini PCIE - Page B - 23

Click Board - Page B - 40

CPU 5/7 (Graphics Power) - Page B - 7

CCD, 3G, TPM - Page B - 24

Audio Board/USB - Page B - 41

CPU 6/7 (GND) - Page B - 8

Card Reader/LAN JMC251C - Page B - 25

Power Switch & LID Board - Page B - 42

CPU 7/7 (RESERVED) - Page B - 9

LAN (JMC251C), SATA HDD, ODD - Page B - 26

DDR3 SO-DIMM_0 - Page B - 10

USB 2.0 Connector - Page B - 27

DDR3 SO-DIMM_1 - Page B - 11

KBC-ITE IT8518 - Page B - 28

LVDS, Inverter - Page B - 12

LED, MDC, BT - Page B - 29

HDMI, CRT - Page B - 13

Audio Codec ALC269 - Page B - 30

CougarPoint - M 1/9 - Page B - 14

USB, Fan, TP, Multi-Conn - Page B - 31

CougarPoint - M 2/9 - Page B - 15

5VS, 3VS, 1.05VS, 1.5VS_CPU - Page B - 32

CougarPoint - M 3/9 - Page B - 16

VDD3, VDD5 - Page B - 33

CougarPoint - M 4/9 - Page B - 17

Power 1.5V/0.75V/1.8VS - Page B - 34

CougarPoint - M 5/9 - Page B - 18

Power 1.05VS - Page B - 35

System Block Diagram - Page B - 2

System Block Diagram

Huron River System Block Diagram

POWER SWITCH BOARD

EXTERNAL ODD BOARD

SATA I/II 3.0Gb/s

B - 2 System Block Diagram

CPU 1/7 (DMI, PEG, FDI)

EDP Function Disable

SC70-5 & SC70-3 Co-lay

On Board CPU Thermal Sensor

Analog Thermal Sensor

PCI EXPRESS* - GRAPHICS

[3 ,8 , 11 ,1 3 , 1 4, 15 , 1 7 ,1 8, 1 9 ,2 0 ,22 ,2 3 ,2 6 ,28 ,3 0 ,3 1,3 3 ,3 4 ,3 5] 3.3 V

CPU 1/7 (DMI, PEG, FDI) B - 3

CAD NOTE: DP_COMPIO and ICOMPO signals

CPU 2/7 (CLK, MISC, JTAG)

Sandy Bridge Processor 2/7

PU/PD for JTAG signals

Buffered reset to CPU

JTAG & BPM