Chucng 4

CAC FL|P FL0P, 1HANH CH|, 80 EM

1k0NC VHDL

C|0| 1H|EU
1H|E1 KE CAC L0A| FL|P FL0P
}
/
1H|E1 KE 1HANH CH| D[CH
/ 3 , -
/ 3 , `
\/ \ } `
\/ \ .3 `
\/ ` /3 / / /
1H|E1 KE MACH EM
\/ \ , / - \
\/ \
\/ \ ./ 3/ \/ , 7 /
\/ \ 3 , 7 /
\/ \ 333 , 7 /
CAU H0| 0N 1AP VA 8A| 1AP

+++ - , :+~++ +, : - :+ . .y-+ ++ +.
142 y :+.~: .~ /
H|nh 4-. 5c dc khc| FL|P FL|P JK.
H|nh 4-2. 5c dc khc| FL|P FL|P D cc enob|e.
H|nh 4-3. 5c dc khc| thonh gh| 4 b|t.
H|nh 4-4. 5c dc khc| thonh gh| 4 b|t, nop scng scng.
H|nh 4-5. 5c dc khc| thonh gh| 8 b|t.
H|nh 4-6. 5c dc khc| moch dem vcng Jchnscn 8 b|t.
H|nh 4-7. 5c dc khc| moch dem vcng 8 b|t.
H|nh 4-8. 5c dc khc| moch d|eu kh|en 8 |ed song tot don.
H|nh 4-. 5c dc khc| moch dem nh| phon 4 b|t.
H|nh 4-0. 5c dc khc| moch dem 8CD.
H|nh 4-. 5c dc khc| moch dem 8CD cc g|o| mo 7 dcon oncde chung.
H|nh 4-2. 5c dc khc| moch dem tu 00 den 5 cc h|en th|.
H|nh 4-3. 5c dc khc| moch dem tu 000 den .


8ong 4-. 811 FL|P FL|P JK.
8ong 4-2. 811 FL|P FL|P D cc enob|e.
8ong 4-3. 811 moch thonh gh| d|ch 4 b|t.
8ong 4-4. 811 moch thonh gh| d|ch 4 b|t, nop scng scng.
8ong 4-5. 811 thonh gh| d|ch 8 b|t.
8ong 4-6. 811 moch dem J0HN50N 8 b|t.
8ong 4-7. 811 moch moch dem vcng 8b|t.
8ong 4-8. 811 moch d|eu kh|en 8 |ed song tot don.
8ong 4-. 811 moch dem nh| phon 4 b|t.
8ong 4-0. 811 moch dem 8CD.
8ong 4-. 811 moch dem 8CD cc g|o| mo 7 dcon.

+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 143

|. C|0| 1H|EU:
Trong phan nay se thiet ke cac mach flip flop, thanh ghi va mach em dung ngon ng VHDL
va s dung thiet b lap trnh.
Cac mach flip flop bao gom flip flop JK, flip flop T, flip flop D.
Thanh ghi dch bao gom thanh ghi dch noi tiep sang noi tiep, noi tiep sang song song, mach
em vong, mach em JohnSon.
Mach em nh phan, mach em len em xuong, mach em BCD, mach em at trc so
em, mach em co giai ma sang led 7 oan, mach em giay, em phut giay,
Cac thiet b lap trnh co the dung CPLD XC9572, XC 95144, Coolrunner XC2C256.
||. 1H|E1 KE CAC L0A| FL|P FL0P
' }
Bai 4-1: Thiet ke flip flop JK gom co cac ngo vao J, K, CLK, PRE, CLR va cac ngo ra gom Q
va Q:
8ucc : Ve s o khoi cua mach:

H|nh 4-. 5c dc khc| FF JK.
8ucc 2: Bang trang thai:

NC0 VA0 NC0 kA
Hong PkE CLk CLK J K Q QD
0 0 X X X
2 0 X X X 0
3 0 X X X 0
4 0 X X Q
0
QD
0

5

0 0 Q
0
QD
0

6

0 0
7

0 0
8

N01 Q
0
N01 QD
0

8ong 4-. 811 FF JK.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
144 y :+.~: .~ /
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ffjk is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
CLK : in STD_LOGIC;
PRE : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC;
QD : out STD_LOGIC);
end ffjk;
architecture Behav_ffjk of ffjk is
SIGNAL QT,QDT: STD_LOGIC;
SIGNAL JK : STD_LOGIC_VECTOR(1 DOWNTO 0);
begin
PROCESS(J,K,CLK,PRE,CLR)
BEGIN
IF (PRE='0') AND (CLR='0') THEN QT <='1'; QDT <='1'; -- hang 1 btt
ELSIF (PRE='0') AND (CLR='1') THEN QT <='1'; QDT <='0'; -- hang 2 btt
ELSIF (PRE='1') AND (CLR='0') THEN QT <='0'; QDT <='1'; -- hang 3 btt
ELSIF (PRE='1') AND (CLR='1') THEN
IF CLK='0' AND CLK'EVENT THEN
JK <=J & K;
CASE JK IS
WHEN "11" => QT <=NOT QT; QDT <=NOT QDT;
WHEN "10" => QT <='1'; QDT <='0';
WHEN "01" => QT <='0'; QDT <='1';
WHEN OTHERS => NULL; -- khong doi TT
END CASE;
END IF; -- cua lenh kiem tra xung clock
END IF;
END PROCESS;
Q <= QT;
QD <= QDT;
end Behav_ffjk;
/
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 145
Bai 4-2: Thiet ke flip flop D gom co cac ngo vao D, CLK, Enable va ngo ra gom Q va Q:
8ucc : Ve s o khoi cua mach:
D
E
CLK
Q
Q

H|nh 4-2. 5c dc khc| FF D cc enob|e.
8ucc 2: Bang trang thai:
NC0 VA0 NC0 kA
E c|k D Q QD
0 x x Q
0
QD
0

0 0 Q
0
QD
0



0 0


0
8ong 4-2. 811 FF D cc enob|e.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ff_de is
Port ( D : in STD_LOGIC;
E : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC;
QD : out STD_LOGIC);
end ff_de;
architecture Behavioral of ff_de is
SIGNAL QT: STD_LOGIC;
begin
PROCESS(D,E,CLK)
BEGIN
IF E='1' THEN
IF CLK='0' AND CLK'EVENT THEN QT <= D;
END IF;
END IF;
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
146 y :+.~: .~ /
END PROCESS;
Q <= QT;
QD <= NOT QT;
end Behavioral;
|||. 1H|E1 KE 1HANH CH| D[CH
' / 3 , -
Bai 4-3: Thiet ke thanh ghi dch 4 bit vao noi tiep ra noi tiep.
8ucc : Ve s o khoi cua mach:
D
CLK
CLR
Q0
Q1
Q2
Q3

H|nh 4-3. 5c dc khc| thonh gh| 4 b|t.
8ucc 2: Lap bang trang thai:
NC0 VA0 NC0 kA Ch| chu
c|r c|k D Q3 Q2 Q Q0
0 x x 0 0 0 0 keset
0 x Q3
0
Q2
0
Q
0
Q0
0
Khcng cc xung c|k


d Q2
0
Q
0
Q0
0
d D|ch du ||eu voc
8ong 4-3. 811 thonh gh| 4 b|t.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg4b is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end reg4b;
architecture Behavioral of reg4b is
begin
process(D,CLK,CLR)
variable QT: std_logic_vector(3 downto 0);
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 147
begin
if CLR ='0' then QT :="0000";
elsif CLK='1' and CLK'event then
QT(3 downto 0) := QT(2 downto 0) & D;
end if;
Q <= QT;
end process;
end Behavioral;
Bai 4-4: Thiet ke thanh ghi dch 4 bit vao noi tiep, song song, ra noi tiep song song.
8ucc : Ve s o khoi cua mach:
Q0
Q1
Q2
Q3
P0
P1
P2
P3
PL
CLR
CLK
D

H|nh 4-4. 5c dc khc| thonh gh| 4 b|t, nop scng scng, nc| t|ep.
8ucc 2: Lap bang trang thai:
NC0 VA0 NC0 kA Ch| chu
CLk CLK D PL P3 P2 P P0 Q3 Q2 Q Q0
0 x x x x x x x 0 0 0 0 keset
x x 0 P3 P2 P P0 P3 P2 P P0 Lcod
0 x x x x x Q3
0
Q2
0
Q
0
Q0
0
Khcng cc xung c|k


d x x x X Q2
0
Q
0
Q0
0
d D|ch du ||eu voc
8ong 4-4. 811 moch thonh gh| d|ch 4 b|t, nop scng scng, nc| t|ep.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tghi4b_ntss is
Port ( D : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
148 y :+.~: .~ /
P : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0);
PL : in STD_LOGIC);
end tghi4b_ntss;
architecture Behavioral of tghi4b_ntss is
begin
PROCESS(D,CLR,CLK,P,LOAD)
VARIABLE QT: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR='0' THEN QT:= "0000";
ELSIF PL='0' THEN QT:= P;
ELSIF CLK='1' AND CLK'EVENT THEN QT:= QT(2 DOWNTO 0) & D;
END IF;
Q <= QT;
END PROCESS;
end Behavioral;
/ 3 , `
Bai 4-5: Thiet ke thanh ghi dch 8 bit vao noi tiep, ra noi tiep song song.
8ucc : Ve s o khoi cua mach:
CLK
CLR
Q0
Q1
Q2
Q3
D
Q4
Q5
Q6
Q7

H|nh 4-5. 5c dc khc| thonh gh| 8 b|t.
8ucc 2: Lap bang trang thai:
NC0 VA0 NC0 kA Ch| chu
c|r c|k D Q7 Q6 Q5 Q4 Q3 Q2 Q Q0
0 x x 0 0 0 0 0 0 0 0 keset
0 x Q7
0
Q6
0
Q5
0
Q4
0
Q3
0
Q2
0
Q
0
Q0
0
Khcng cc xung c|k


d Q6
0
Q5
0
Q4
0
Q3
0
Q2
0
Q
0
Q0
0
d D|ch du ||eu voc
8ong 4-5. 811 thonh gh| d|ch 8 b|t.
8ucc 3: Viet chng trnh:
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 149
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TGHI8BIT is
Port ( CLK : in STD_LOGIC;
CLR,D : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end TGHI8BIT;
architecture Behavioral of TGHI8BIT is
SIGNAL QT: STD_LOGIC_VECTOR (7 downto 0);
begin
PROCESS (CLK,CLR)
BEGIN
IF CLR = '0' THEN QT <= "00000000";
ELSIF CLK='1' AND CLK'EVENT THEN
QT <= QT(6 DOWNTO 0) & D;
END IF;
END PROCESS;
Q <= QT;
end Behavioral;
\/ \ } `
Bai 4-6: Thiet ke mach em vong JONHSON 8 bit.
8ucc : Ve s o khoi cua mach:
CLK
CLR
Q0
Q1
Q2
Q3
8 BIT JOHNSON COUNTER
D
Q4
Q5
Q6
Q7

H|nh 4-6. 5c dc khc| moch dem vcng Jchnscn 8 b|t.
Chu y: D a c ket noi vi ngo ra 7 Q va nam ben trong mach ien.
8ucc 2: Lap bang trang thai:
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
150 y :+.~: .~ /
NC0 VA0 NC0 kA
c|r c|k Q7 Q6 Q5 Q4 Q3 Q2 Q Q0
0 X 0 0 0 0 0 0 0 0


0 0 0 0 0 0 0


0 0 0 0 0 0


0 0 0 0 0


0 0 0 0


0 0 0


0 0


0





0


0 0


0 0 0


0 0 0 0


0 0 0 0 0


0 0 0 0 0 0


0 0 0 0 0 0 0


0 0 0 0 0 0 0 0
8ong 4-6. 811 moch dem J0HN50N 8 b|t.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity johnson8bit is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end johnson8bit;
architecture Behavioral of johnson8bit is
begin
PROCESS (CLK,CLR)
VARIABLE QT: STD_LOGIC_VECTOR (7 downto 0);
VARIABLE D : STD_LOGIC;
BEGIN
IF CLR = '0' THEN QT <= "00000000";
ELSIF CLK='1' AND CLK'EVENT THEN
D <= NOT QT(7);
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 151
QT <= QT(6 DOWNTO 0) & D;
END IF;
Q <= QT;
END PROCESS;
end Behavioral;
- \/ \ .3 `
Bai 4-7: Thiet ke mach em vong 8 bit.
8ucc : Ve s o khoi cua mach:
CLK
CLR
Q0
Q1
Q2
Q3
8 BIT RING COUNTER
D
Q4
Q5
Q6
Q7

H|nh 4-7. 5c dc khc| moch dem vcng 8 b|t.
8ucc 2: Lap bang trang thai:
NC0 VA0 NC0 kA
c|r c|k Q7 Q6 Q5 Q4 Q3 Q2 Q Q0
0 X 0 0 0 0 0 0 0


0 0 0 0 0 0 0


0 0 0 0 0 0 0


0 0 0 0 0 0 0


0 0 0 0 0 0 0


0 0 0 0 0 0 0


0 0 0 0 0 0 0


0 0 0 0 0 0 0
8ong 4-7. 811 moch dem vcng 8b|t.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ringcounter8 is
Port ( CLK : in STD_LOGIC;
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
152 y :+.~: .~ /
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(7 downto 0));
end ringcounter8;
architecture Behavioral of ringcounter8 is
SIGNAL QT: STD_LOGIC_VECTOR(7 downto 0):=00000001;
begin
PROCESS (CLK,CLR)
BEGIN
IF CLR = '0' THEN QT <="00000001";
ELSIF CLK='1' AND CLK'EVENT THEN
QT <= QT(6 DOWNTO 0) & QT(7);
END IF;
END PROCESS;
Q <= QT;
end Behavioral;
Chu y: Chng trnh sau s dung bien thay v tn hieu nh cac chng trnh tren:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ringcounter8 is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end ringcounter8;
architecture Behavioral of ringcounter8 is
begin
PROCESS (CLK,CLR)
VARIABLE QT: STD_LOGIC_VECTOR (7 downto 0);
BEGIN
IF CLR = '0' THEN QT:="00000001";
ELSIF CLK='0' AND CLK'EVENT THEN
QT := QT(6 DOWNTO 0) & QT(7);
END IF;
Q <= QT;
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 153
END PROCESS;
end Behavioral;
\/ ` /3 / / /
Bai 4-8: Thiet ke mach ieu khien 8 led sang dan, tat dan t trai sang phai va t phai sang
trai theo xung clock.
8ucc : Ve s o khoi cua mach:
CLK
CLR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

H|nh 4-8. 5c dc khc| moch d|eu kh|en 8 |ed song tot don.
8ucc 2: Lap bang trang thai:
NC0 VA0 NC0 kA
c|r c|k Q7 Q6 Q5 Q4 Q3 Q2 Q Q0 1HAP PHAN
0 X 0 0 0 0 0 0 0 0 0


0 0 0 0 0 0 0


0 0 0 0 0 0 2


0 0 0 0 0 3


0 0 0 0 4


0 0 0 5


0 0 6


0 7


8


0


0 0 0


0 0 0


0 0 0 0 2


0 0 0 0 0 3


0 0 0 0 0 0 4


0 0 0 0 0 0 0 5


0 0 0 0 0 0 0 0 6


0 0 0 0 0 0 0 7


0 0 0 0 0 0 8


0 0 0 0 0


0 0 0 0 20


0 0 0 2


0 0 22


0 23


24


0 25


0 0 26
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
154 y :+.~: .~ /


0 0 0 27


0 0 0 0 28


0 0 0 0 0 2


0 0 0 0 0 0 30


0 0 0 0 0 0 0 3


0 0 0 0 0 0 0 0 32
8ong 4-8. 811 moch d|eu kh|en 8 |ed song tot don.
Cac trang thai sang dan tat dan t phai sang trai can 16 xung clock va trang thai ngc lai
cung can 16 xung clock.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sangtatdan_tppt is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end sangtatdan_tppt;
architecture Behavioral of sangtatdan_tppt is
SIGNAL QT: STD_LOGIC_VECTOR (7 downto 0);
begin
PROCESS(CLK,CLR)
VARIABLE DEM: INTEGER RANGE 0 TO 32;
BEGIN
IF CLR ='0' THEN QT <= "00000000";
ELSIF CLK='1' AND CLK'EVENT THEN
IF DEM <16 THEN QT <= QT(6 DOWNTO 0) & NOT QT(7);
ELSE QT <= NOT QT(0) & QT(7 DOWNTO 1);
END IF;
DEM:= DEM +1;
IF DEM = 32 THEN DEM:=0; END IF;
END IF;
END PROCESS;
Q <= QT;
end Behavioral;
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 155
Trong chng trnh bien DEM co chc nang lam bien em e thc hien lan lt cac trang
thai.
|V. 1H|E1 KE MACH EM
' \/ \ , / - \
Bai 4-9: Thiet ke mach em nh phan 4 bit.
8ucc : Ve s o khoi cua mach:
CLK
CLR
Q0
Q1
Q2
Q3

H|nh 4-. 5c dc khc| moch dem nh| phon 4 b|t.
8ucc 2: Lap bang trang thai:
NC0 VA0 NC0 kA Ch| chu
c|r c|k Q3 Q2 Q Q0
0 x 0 0 0 0 keset


0 0 0


0 0 0


0 0


. .. ..





0 0 0 0
8ong 4-. 811 moch dem nh| phon 4 b|t.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cout_4bit is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end cout_4bit;
architecture Behavioral of cout_4bit is
begin
PROCESS(CLK,CLR)
VARIABLE QT: STD_LOGIC_VECTOR(3 DOWNTO 0);
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
156 y :+.~: .~ /
BEGIN
IF CLR ='0' THEN QT:= "0000";
ELSIF CLK='1' AND CLK'EVENT THEN QT:= QT +1;
END IF;
Q <= QT;
END PROCESS;
end Behavioral;
\/ \ \
Bai 4-10: Thiet ke mach em bcd.
8ucc : Ve s o khoi cua mach:
CLK
CLR
Q0
Q1
Q2
Q3

H|nh 4-0. 5c dc khc| moch dem 8CD.
8ucc 2: Lap bang trang thai:
NC0 VA0 NC0 kA Ch| chu
c|r c|k Q3 Q2 Q Q0
0 x 0 0 0 0


0 0 0


0 0 0


0 0


0 0 0


0 0


0 0


0


0 0 0


0 0


0 0 0 0
8ong 4-0. 811 moch dem 8CD.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcdcounter is
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 157
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end bcdcounter;
architecture Behavioral of bcdcounter is
begin
PROCESS(CLK,CLR)
VARIABLE QT: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR ='0' THEN QT:= "0000";
ELSIF CLK='1' AND CLK'EVENT THEN QT:= QT +1;
IF QT = "1010" THEN QT := 0000 ;
END IF;
END IF;
Q <= QT;
END PROCESS;
end Behavioral;
\/ \ ./ 3/ \/ , 7 /
Bai 4-11: Thiet ke mach em bcd hien th tren led 7 oan.
8ucc : Ve s o khoi cua mach:
I0
I1
DECODE
a
b
c
d
e
f
g
I2
I3
SEGMENT
CLK
CLR
Q0
COUNTER
Q1
Q2
Q3
BCD LED

H|nh 4-. 5c dc khc| moch dem 8CD cc g|o| mo 7 dcon oncde chung.
8ucc 2: Lap bang trang thai:
NC0 VA0 NGO RA
tp c|r c|k Q3 Q2 Q Q0
dp g f e d c b a
hex
0 0 x 0 0 0 0
1 1 0 0 0 0 0 0
C0


0 0 0
1 1 1 1 1 0 0 1
F
2

0 0 0
1 0 1 0 0 1 0 0
A4
3

0 0
1 0 1 1 0 0 0 0
80
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
158 y :+.~: .~ /
4

0 0 0
1 0 0 1 1 0 0 1

5

0 0
1 0 0 1 0 0 1 0
2
6

0 0
1 0 0 0 0 0 1 0
82
7

0
1 1 1 1 1 0 0 0
F8
8

0 0 0
1 0 0 0 0 0 0 0
80


0 0
1 0 0 1 0 0 0 0
0
8ong 4-. 811 moch dem 8CD cc g|o| mo 7 dcon.
8ucc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count_bcd_gma is
Port ( CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0);
L7D : out STD_LOGIC_VECTOR (6 downto 0));
end count_bcd_gma;
architecture Behavioral of count_bcd_gma is
begin
PROCESS (CLR,CLK)
VARIABLE QTAM: STD_LOGIC_VECTOR (3 downto 0);
VARIABLE YTAM: STD_LOGIC_VECTOR (6 downto 0);
BEGIN
IF CLR='0' THEN QTAM :="0000";
ELSIF CLK='1' AND CLK'EVENT THEN QTAM:= QTAM +1;
IF QTAM = "1010" THEN QTAM:="0000";
END IF;
END IF;
CASE QTAM IS
when "0000" => YTAM := x"C0"; -- so 0
when "0001" => YTAM := x"F9"; -- so 1
when "0010" => YTAM := x"A4"; -- so 2
when "0011" => YTAM := x"B0"; -- so 3
when "0100" => YTAM := x"99"; -- so 4
when "0101" => YTAM := x"92"; -- so 5
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 159
when "0110" => YTAM := x"82"; -- so 6
when "0111" => YTAM := x"F8"; -- so 7
when "1000" => YTAM := x"80"; -- so 8
when "1001" => YTAM := x"90"; -- so 9
when others => YTAM := x"FF"; -- tat
END CASE;
Q <= QTAM;
L7D <= YTAM;
END PROCESS;
end Behavioral;
- \/ \ 3 , 7 /
Bai 4-12: Thiet ke mach em bcd t 00 en 59 hien th tren 2 led 7 oan ket noi theo phng
phap quet. S dung nguon xung clock co tan so 1,8432MHz tren bo th nghiem dung e quet va
lam xung tang gia tr em.
8ucc : Ve s o khoi cua mach:
CLK
CLR
OSC
1,8432MHz
a
b
c
d
e
f
g
anod0
anod1
Vcc

H|nh 4-2. 5c dc khc| moch dem tu 00 den 5 cc h|en th|.
8ucc 2: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEM0099 is
Port ( CLR : in std_logic;
CLK : in std_logic;
anod : out std_logic_vector(3 downto 0);
ma7d : out std_logic_vector( 7 downto 0));
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
160 y :+.~: .~ /
end DEM0099;

architecture Behavioral of DEM0099 is
signal F: std_logic_vector(18 downto 0);
signal mabl: std_logic_vector(7 downto 0);
signal mabh: std_logic_vector(7 downto 0);

function giai_ma(x1: in std_logic_vector(3 downto 0)) return std_logic_vector is
variable z1: std_logic_vector(7 downto 0);
begin
case x1 is
when "0000" => z1 := "11000000"; -- so 0
when "0001" => z1 := "11111001"; -- so 1
when "0010" => z1 := "10100100"; -- so 2
when "0011" => z1 := "10110000"; -- so 3

when "0100" => z1 := "10011001"; -- so 4
when "0101" => z1 := "10010010"; -- so 5
when "0110" => z1 := "10000010"; -- so 6
when "0111" => z1 := "11111000"; -- so 7

when "1000" => z1 := "10000000"; -- so 8
when "1001" => z1 := "10010000"; -- so 9
when others =>z1 := "11111111"; -- so
end case;
return z1;
end giai_ma;
begin
process (CLR,CLK,F,mabl,mabh)
variable bcd1: std_logic_vector(3 downto 0);
variable bcd2: std_logic_vector(3 downto 0);
begin
if CLR = '1' then bcd1:="0000"; bcd2:="0000";
F <= "0000000000000000000";
elsif RISING_EDGE(CLK) then F <= F + 1;
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 161
if F = "1111111111111111111" then bcd1:=bcd1+1;
if bcd1 = "1010" then bcd1:="0000";
bcd2:= bcd2+1;
if bcd2 = "0110" then bcd2:="0000";
end if;
end if;
end if;
end if;
QB <= bcd2 & bcd1 ; -- hien thi 8 led don
mabh <= giai_ma(bcd2);
mabl <= giai_ma(bcd1);
case F (10 downto 9) is
when "00" => ma7d <= mabh;
anod <="0010";
when "10" => ma7d <= mabl;
anod <="0001";
when others => null;
end case;
END PROCESS;
end Behavioral;
\/ \ 333 , 7 /
Bai 4-13: Thiet ke mach em bcd t 000 en 999 hien th tren 3 led 7 oan ket noi theo
phng phap bnh thng. S dung nguon xung clock tuy y.
8ucc : Ve s o khoi cua mach:
CLOCK
CLR
TRM CHC N V
a b c d e
f
g
a b c d e
f
g
a b c d e
f
g

H|nh 4-3. 5c dc khc| moch dem tu 000 den .
8ucc 2: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
162 y :+.~: .~ /
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEM_999000 is
Port ( CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
QDVI : out STD_LOGIC_VECTOR (6 downto 0);
QCHU : out STD_LOGIC_VECTOR (6 downto 0);
QTRA : out STD_LOGIC_VECTOR (6 downto 0));
end DEM_999000;

architecture Behavioral of DEM_999000 is
function giai_ma(x1: in std_logic_vector(3 downto 0)) return std_logic_vector is
variable z1: std_logic_vector(6 downto 0);
begin
case x1 is
when "0000" => z1 := "1000000"; -- so 0
when "0001" => z1 := "1111001"; -- so 1
when "0010" => z1 := "0100100"; -- so 2
when "0011" => z1 := "0110000"; -- so 3
when "0100" => z1 := "0011001"; -- so 4
when "0101" => z1 := "0010010"; -- so 5
when "0110" => z1 := "0000010"; -- so 6
when "0111" => z1 := "1111000"; -- so 7
when "1000" => z1 := "0000000"; -- so 8
when "1001" => z1 := "0010000"; -- so 9
when others =>z1 := "1111111"; -- TATLED
end case;
return z1;
end giai_ma;
begin
process (CLR,CLK)
variable BCD_DVI: std_logic_vector(3 downto 0);
variable BCD_CHU: std_logic_vector(3 downto 0);
variable BCD_TRA: std_logic_vector(3 downto 0);
begin
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 163
if CLR = '1' then BCD_DVI:="0000";
BCD_CHU:="0000";
BCD_TRA:="0000";

Elsif CLK= '1' and CLK'event then
BCD_DVI:=BCD_DVI+1;
if BCD_DVI= "1010" then
BCD_DVI:="0000";
BCD_CHU:= BCD_CHU+1;
if BCD_CHU= "1010" then
BCD_CHU:="0000";
BCD_TRA:= BCD_TRA+1;
if BCD_TRA= "1010" then
BCD_TRA:="0000";
end if;
end if;
end if;
end if;
QDVI <= giai_ma(BCD_DVI);
QCHU <= giai_ma(BCD_CHU);
QTRA <= giai_ma(BCD_TRA);
END PROCESS;
end Behavioral;
V. CAU H0| 0N 1AP VA 8A| 1AP
Bai tap 4-1: Thiet ke flip flop RS.
Bai tap 4-2: Thiet ke mach chot D.
Bai tap 4-3: Thiet ke flip flop D.
Bai tap 4-4: Thiet ke flip flop T.
Bai tap 4-5: Thiet ke 4 flip flop D gom 4 ngo vao D, 4 ngo ra Q va 4 ngo ra QD, dung chung
1 CLK.
Bai tap 4-6: Thiet ke 8 flip flop T gom 8 ngo vao T, 8 ngo ra Q va 8 ngo ra QD, dung chung
CLK.
Bai tap 4-7: Thiet ke thanh ghi dch giong nh IC 74164.
Bai tap 4-8: Thiet ke thanh ghi dch giong nh IC 74194.
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
164 y :+.~: .~ /
Bai tap 4-9: Thiet ke mach ieu khien en giao thong vi xanh_1, vang_1, o_1, xanh_2,
vang_2, o_2. Cho xanh sang 15 giay, vang sang 5 giay va o sang 20 giay.
Bai tap 4-10: Thiet ke mach ieu khien en 8 led n vi yeu cau nh sau: iem sang chay
t phai sang trai va t trai sang phai theo xung clock va co 1 chan cho phep E tch cc mc 0.
Bai tap 4-11: Thiet ke mach co chc nang giong nh IC 4017.
Bai tap 4-12: Thiet ke mach co chc nang giong nh IC 4017 nhng gom co 20 ngo ra.
Bai tap 4-13: Thiet ke mach co chc nang giong nh IC 4017 nhng gom 2 con: mot con em
hang n v va mot con em hang chuc.
Bai tap 4-14: Thiet ke mach em nh phan 4 bit em xuong.
Bai tap 4-15: Thiet ke mach em nh phan 4 bit em len, em xuong c ieu khien bang
tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu CLR.
Bai tap 4-16: Thiet ke mach em nh phan 4 bit em len, em xuong c ieu khien bang
tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu CLR.
Co them chc nang at trc so em nh IC 74193.
Bai tap 4-17: Thiet ke mach em nh phan 4 bit em len, em xuong c ieu khien bang
tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu CLR,
co giai ma hien th ra 1 led 7 oan t 0 en F tng ng vi so thap luc phan.
Bai tap 4-18: Thiet ke mach em BCD em len, em xuong c ieu khien bang tn hieu
UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu CLR, co giai
ma hien th ra 1 led 7 oan.
Bai tap 4-19: Thiet ke mach em BCD t 00 en 99 em len, em xuong c ieu khien
bang tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu
CLR, co giai ma hien th ra 2 led 7 oan khong dung quet.
Bai tap 4-20: Thiet ke mach em BCD t 000 en 999 em len, em xuong c ieu
khien bang tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn
hieu CLR, co giai ma hien th ra 3 led 7 oan dung quet.
Bai tap 4-21: Thiet ke mach gom co 3 led 7 oan, ban phm gom 10 phm so t 0 en 9.
Ban au th 3 led hien th so 000, khi nhan phm nao th phm o c dch vao t ben phai.
(giong nh may tnh calculator).
Bai tap 4-22: Thiet ke mach nh thi: gom co 2 led 7 oan e hien th so giay t 00 en 99,
ban phm gom 10 phm so t 0 en 0 va phm chc nang nh clear, enter, test, mot ngo
ra ieu khien relay. Ban au th 2 led hien th so 00, khi nhan phm nao th phm o c dch
vao t ben phai. Sau khi nhan xong th nhan enter qua trnh em xuong se bat au cho en khi
gia tr em bang 00 th relay se tac ong. He thong ngng.

Bai tap 4-23: Dung PLD ket noi vi IC em BCD 74LS90, hay viet chng trnh ieu khien
IC 74LS90 em vi trnh t nh sau:
em t 0 en 9, sau o em t 0 en 8, tng t em t 0 en 7 roi lap lai.
+++ - , :+~++ +, : - :+ . .y-+ ++ +.
y :+.~: .~ / 165
Bai tap 4-24: Mo ta mach em nh phan 4 bit co the em vi 4 cap tan so f ,
2
f
,
4
f
,
8
f
,
cac cap tan so co the chon bang 2 switch S0 va S1, cho tan so cung cap cho mach la f .
Bai tap 4-25: Mo ta mach co the tao ra dang song vi yeu cau nh sau:
Mach tao ra 5 xung co tan so 1Hz roi ngng 5 xung co tan so 1 hz, cho xung vao co tan so
10hz. Co 1 ngo vao reset
Bai tap 4-26: Mo ta mach co 3 nut nhan A, B va C: khi nhan nut A th ma ch tao ra 5 xung roi
ngng, khi nhan nut B th mach tao ra 10 xung roi ngng, khi nhan nut C th mach tao ra 15 xung
roi ngng. Cho xung clock ngo vao co tan so bang 1Hz.
Bai tap 4-27: Thiet ke mach so sanh 2 so nh phan 3 bit A va B va 1 mach em nh 4 bit: neu
so nh phan A ln hn B th mach em len, neu A bang B th mach em xuong, neu A nho hn B
th mach em.
Bai tap 4-28: Thiet ke 1 mach em nh phan 4 bit va 1 mach em Johnson 4 bit co cung clr
va enable nhng xung clock khac nhau .
Bai tap 4-29: Thiet ke 1 mach em nh phan 4 bit co clr, clk co the la chon em nh phan
chan hoac le.
Bai tap 4-30: Thiet ke 1 mach em nh phan 5 bit co clr, clk, enable, vi trnh t em: em
len t cc tieu len cc ai theo so theo so thap phan chan roi quay lai theo so thap phan le, c the
lap lai.
Bai tap 4-31: Thiet ke 1 mach co 8 ngo ra va cac ngo vao gom: 1 clk, 1 clr, 1 ngo vao S: S=0
th mach em Johnson, S=1 th mach em vong, 1 ngo vao pause bnh thng mc 1: khi nut
pause th mach ang em se ngng em va sau 5 xung th mach se em tiep.


v.


end