TP1. Adder_4bits.VHDL Library ieee; Library work; use ieee.std_logic_1164.all; use work.

all; ENTITY Adder_4bits is PORT (A,B : in std_logic_vector(3 downto 0); Cin : std_logic; Cout : out std_logic; S : out std_logic_vector (3 downto 0) ); END Entity Adder_4bits; ARCHITECTURE description of Adder_4bits is signal I0,I1,I2 : std_logic; begin ADD0 : TP1 port map (A(0),B(0),Cin,I0,S(0)); ADD1 : TP1 port map (A(1),B(1),I0,I1,S(1)); ADD2 : TP1 port map (A(2),B(2),I1,I2,S(2)); ADD3 : TP1 port map (A(3),B(3),I2,Cout,S(3)); END Architecture description; TP1.VHDL Library ieee; use ieee.std_logic_1164.all; ENTITY TP1 is PORT (A,B,Cin: in std_logic; Cout,S : out std_logic ); END ENTITY TP1; ARCHITECTURE description of TP1 is begin S<=A XOR B XOR Cin; Cout<=(A AND B) OR (A AND Cin) OR (B AND Cin); END Architecture description; TP2. TP2.VHDL Library ieee; use ieee.std_logic_1164.all; Entity TP2 is port ( clk, clk2, input : in std_logic; output : out std_logic ); end Entity TP2; Architecture Comportement of TP2 is signal bascule : std_logic_vector(0 to 2);

signal resetout : std_logic; begin bascule(0)<=clk; output<=bascule(2) and input and resetout; Process (bascule) is begin for i in 1 to 2 loop if(bascule(i-1)'event and bascule(i-1)='1') then bascule(i)<=not bascule(i); end if; end loop; end process; process (clk2) is variable a : integer range 0 to 3; begin if(clk2 'event and clk2='1') then a:=a+1; end if; case a is when 1 =>resetout<='0'; when others =>resetout<='1'; end case; end process; end architecture Comportement; TP3. Counter.VHDL Library ieee; Use ieee.std_logic_1164.all; Entity counter is Port( clk : in std_logic; output : out std_logic_vector (3 downto 0) ); End Entity counter; Architecture Comportement of counter is begin Process (clk) is variable cumul : std_logic_vector(3 downto 0):=(others=>'0');--sur 4 bits initialise a zero variable carry : std_logic_vector(4 downto 1);--sur 4 bits begin if rising_edge(clk) then carry(1):=cumul(0); cumul(0):=not cumul(0); for i in 1 to 3 loop carry(i+1):=cumul(i) and carry(i); cumul(i):= cumul(i) xor carry(i);

end loop; end if; output<=cumul; end Process; end architecture Comportement; Decoder_hex7seg.VHDL Library ieee; Use ieee.std_logic_1164.all; Entity decoder_hex7seg is Port( code_hex : in std_logic_vector(3 downto 0); display : out std_logic_vector (0 to 6) ); End Entity decoder_hex7seg; Architecture Beh of decoder_hex7seg is Begin Process (code_hex) is Begin case code_hex is when "0000" => display <= "0000001"; when "0001" => display <= "1001111"; when "0010" => display <= "0010010"; when "0011" => display <= "0000110"; when "0100" => display <= "1001100"; when "0101" => display <= "0100100"; when "0110" => display <= "1100000"; when "0111" => display <= "0001111"; when "1000" => display <= "0000000"; when "1001" => display <= "0001100"; when "1010" => display <= "0001000"; when "1011" => display <= "1100000"; when "1100" => display <= "0110001"; when "1101" => display <= "1000010"; when "1110" => display <= "0110000"; when others => display <= "0111000"; end case; end process; end architecture Beh; Freq_div.VHDL Library ieee; Use ieee.std_logic_1164.all; Entity freq_div is port ( c1 : in std_logic; c2: out std_logic ); End Entity freq_div; Architecture Comportement of freq_div is signal bascule : std_logic_vector(0 to 25);

begin c2 <= bascule(25); bascule(0)<=c1; process (bascule) is begin for i in 1 to 25 loop if(bascule(i-1)'event and bascule(i-1)='1') then bascule(i)<=not bascule(i); end if; end loop; end process; end architecture Comportement; TP3.VHDL Library ieee; Use ieee.std_logic_1164.all; Library work; use work.all; Entity TP3 is Port( CLOCK_50: in std_logic; HEX0 : out std_logic_vector(0 to 6); LEDG : out std_logic_vector(0 downto 0) ); End Entity TP3; Architecture Comportement of TP3 is signal clk : std_logic; signal x : std_logic_vector(3 downto 0); begin LEDG(0)<=clk; Inst_0: freq_div port map (CLOCK_50,clk); Inst_1: counter port map ( clk=>clk , output=>x); Inst_2: decoder_hex7seg port map (x,HEX0); end architecture Comportement; TP4. Decoder_hex7seg.VHDL Library ieee; Use ieee.std_logic_1164.all; Entity decoder_hex7seg is Port( code_hex : in std_logic_vector(3 downto 0); display : out std_logic_vector (0 to 6) ); End Entity decoder_hex7seg; Architecture Beh of decoder_hex7seg is Begin Process (code_hex) is Begin case code_hex is when "0000" => display <= "0000001";

when "0001" => display <= "1001111"; when "0010" => display <= "0010010"; when "0011" => display <= "0000110"; when "0100" => display <= "1001100"; when "0101" => display <= "0100100"; when "0110" => display <= "1100000"; when "0111" => display <= "0001111"; when "1000" => display <= "0000000"; when "1001" => display <= "0001100"; when "1010" => display <= "0001000"; when "1011" => display <= "1100000"; when "1100" => display <= "0110001"; when "1101" => display <= "1000010"; when "1110" => display <= "0110000"; when others => display <= "0111000"; end case; end process; end architecture Beh; Freq_div.VHDL Library ieee; Use ieee.std_logic_1164.all; Entity freq_div is port ( c1 : in std_logic; c2: out std_logic); end Entity freq_div; Architecture Comportement of freq_div is signal bascule : std_logic_vector(0 to 19);--25 begin c2 <= bascule(19);--25 bascule(0)<=c1; process (bascule) is begin for i in 1 to 19 loop--25 if(bascule(i-1)'event and bascule(i-1)='1') then bascule(i)<=not bascule(i); end if; end loop; end process; end architecture Comportement; HM.VHDL LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE ieee.std_logic_unsigned.all; ENTITY HM IS generic (X,Y,Z : integer);

PORT ( clk,reset,ss12: in std_logic; ds12,ests3: out std_logic; output: out std_logic_vector(3 downto 0) ); END HM; ARCHITECTURE Description OF HM IS BEGIN PROCESS(clk,reset) variable value: integer:=0;--contenu de l'etat du compteur variable seuil : integer;--select entre seuil1 et seuil2 c.a.d X ou Y Begin if(reset='1')then value:=0; ds12<='0'; ests3<='0'; elsif (rising_edge(clk))Then if ss12='0' Then seuil:=X; else seuil:=Y; end if; value:=value+1; if value=seuil then value:=0; ds12<='1'; else ds12<='0'; end if; if value=Z then ests3<='1'; else ests3<='0'; end if; end if; output<=std_logic_vector(to_unsigned(value,4)); END PROCESS; END Description; TP4.VHDL LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE ieee.std_logic_unsigned.all; USE work.all; ENTITY TP4 IS PORT( CLOCK_50: in std_logic;

LEDG : out std_logic_vector(0 downto 0); KEY : in std_logic_vector(1 downto 0); HEX0: out std_logic_vector(0 to 6); HEX1: out std_logic_vector(0 to 6); HEX2: out std_logic_vector(0 to 6); HEX3: out std_logic_vector(0 to 6) ); END TP4; ARCHITECTURE Desc OF TP4 IS signal clkin : std_logic; signal c,u : std_logic_vector(6 downto 1); signal s1,s2,s3,s4,s5,s6 : std_logic_vector(3 downto 0); signal mux1,mux2,mux3,mux4 : std_logic_vector(3 downto 0); BEGIN LEDG(0)<=clkin; I0:freq_div port map (CLOCK_50, clkin); I1: HM generic map(10,10,10) port map (clkin,not KEY(0), '0', c(1), u(1),s1); I2: HM generic map(6,10,10) port map (c(1), not KEY(0), '0', c(2), u(2), s2); I3: HM generic map(10,10,10) port map (c(2), not KEY(0), '0', c(3), u(3), s3); I4: HM generic map(6,10,10) port map (c(3), not KEY(0), '0', c(4), u(4), s4); I5: HM generic map(10,4,10) port map (c(4), not KEY(0), '0', c(5), u(5), s5); I6: HM generic map(10,10,2) port map (c(5), not KEY(0)or (c(5) and u(6)), '0', c(6), u(6), s6); I7: Decoder_hex7seg port map(mux1,HEX0); I8: Decoder_hex7seg port map(mux2,HEX1); I9: Decoder_hex7seg port map(mux3,HEX2); I10: Decoder_hex7seg port map(mux4,HEX3); mux1<= s1 when KEY(1)='1' else s3; mux2<= s2 when KEY(1)='1' else s4; mux3<= s3 when KEY(1)='1' else s5; mux4<= s4 when KEY(1)='1' else s6; END Desc;