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74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Dynamic characteristics type 74HCT193 continued Parameter recovery time Conditions Min PL to CPU, CPD; see Figure 11 VCC = 4.5 V MR to CPU, CPD; see Figure 12 VCC = 4.5 V 10 0 13 15 ns 10 2 13 15 ns 25 C Typ Max 40 C to +85 C 40 C to +125 C Unit Min Max Min Max
tsu
set-up time
Dn to PL; see Figure 13; note: CPU = CPD = HIGH VCC = 4.5 V 16 8 20 24 ns Dn to PL; see Figure 13 VCC = 4.5 V CPU to CPD, CPD to CPU; see Figure 15 VCC = 4.5 V 16 7 20 24 ns 0 6 0 0 ns
th
hold time
fmax
43 26
16 -
13 -
MHz pF
CPD
[1] [2]
tpd is the same as tPHL and tPLH. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs.
74HC_HCT193
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NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
11. Waveforms
1/fmax VI CPU, CPD input GND tW t PHL VOH Qn output VOL VM
001aag413
VM
t PLH
Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock pulse frequency
VI CPU, CPD input GND tPHL VOH TCU, TCD output VOL VM
001aag414
VM
tPLH
Measurement points are given in Table 10. tPLH and tPHL are the same as tpd. Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays
74HC_HCT193
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