VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

VHDL to Silicon
Design Flow

Victor L Dunn October 2003

October 2003 (VLD)

VHDL to Silicon Design Flow

VHDL to Silicon - Design Flow

October 2003 (VLD)

Xilinx WebPack Project Navigator...

VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

VHDL to Silicon

Design Flow..... Create Project and Select Target Device Create VHDL Source File Enter VHDL code & Syntax Check Create Test Bench & Simulate Synthesis Define Pins Translate, Map & Place and Route device Generate Programming File / Programme device
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VHDL to Silicon Design Flow

Synthesis What is it ?
Model Translate Circuit

Sy nt he sis
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Place & Route / Fit

Chip

VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Synthesis Design Flow.....

Enter VHDL Model Check Syntax Synthesize Define Pins Translate & Fit (CPLD) or Translate, Map, Place & Route (FPGA) Generate Programming File
October 2003 (VLD)

VHDL to Silicon Design Flow

VHDL to Silicon

Design Flow..... Create Project and Select Target Device Create VHDL Source File Enter VHDL code & Syntax Check Create Test Bench & Simulate Synthesis Define Pins Translate, Map & Place and Route device Generate Programming File / Programme device
October 2003 (VLD)

VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Create Project.... and Select Target Device....

October 2003 (VLD)

VHDL to Silicon Design Flow

Create VHDL Source File.....

October 2003 (VLD)

VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

VHDL to Silicon

Design Flow..... Create Project and Select Target Device 4 Create VHDL Source File 4 Enter VHDL code & Syntax Check Create Test Bench & Simulate Synthesis Define Pins Translate, Map & Place and Route device Generate Programming File / Programme device
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VHDL to Silicon Design Flow

Enter VHDL code.... Check Syntax

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity count9 is Port ( clk : in std_logic; reset : in std_logic; count_ext : out std_logic_vector(3 downto 0); count_carry : out std_logic); end count9; architecture Behavioural of count9 is signal count9 : std_logic_vector(3 downto 0); signal carry9 : std_logic; begin process (reset, clk) begin if reset = '1' then

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

library IEEE; - - declare libraries use IEEE.STD_LOGIC_1164.ALL; - - allows use of std_logic use IEEE.STD_LOGIC_ARITH.ALL; - - allows one to do sums use IEEE.STD_LOGIC_UNSIGNED.ALL; - - (sometimes needed) entity count9 is - - entity declaration Port ( clk : in std_logic; - - port statement reset : in std_logic; count_ext : out std_logic_vector(3 downto 0); count_carry : out std_logic); end count9; architecture Behavioural of count9 is - - architecture body

signal count9 : std_logic_vector(3 downto 0); - - 'internal wires' signal carry9 : std_logic; begin process (reset, clk) begin if reset = '1' then count9 <= "0000"; October 2003 (VLD)

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VHDL to Silicon Design Flow

VHDL to Silicon

Design Flow..... Create Project and Select Target Device 4 Create VHDL Source File 4 Enter VHDL code & Syntax Check 4 Create Test Bench & Simulate Synthesis Define Pins Translate, Map & Place and Route device Generate Programming File / Programme device
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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Testing your VHDL code

The Test Bench.....
Input Signal Waveforms

Reset

Clock

Unit Under Test count9 Output Waveforms Entity Test_Bench

Other inputs

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VHDL to Silicon Design Flow

Create Test Bench....

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Create Test Bench....

ARCHITECTURE behaviour OF testbench IS COMPONENT count9 PORT( clk : IN std_logic; reset : IN std_logic; count_enable : IN std_logic; count_ext : OUT std_logic_vector(3 downto 0); count_carry : OUT std_logic ); END COMPONENT; SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL clk : std_logic; reset : std_logic; count_enable : std_logic; count_ext : std_logic_vector(3 downto 0); count_carry : std_logic;

BEGIN uut: count9 PORT MAP( clk => clk, reset => reset, count_enable => count_enable, count_ext => count_ext, count_carry => count_carry);

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VHDL to Silicon Design Flow

Test Bench....

ARCHITECTURE behaviour OF testbench IS COMPONENT count9 - - Declare Entity to be PORT( - - Tested as a Component clk : IN std_logic; reset : IN std_logic; count_enable : IN std_logic; count_ext : OUT std_logic_vector(3 downto 0); count_carry : OUT std_logic ); END COMPONENT; SIGNAL clk : std_logic; - - Define Local Signals SIGNAL reset : std_logic; SIGNAL count_enable : std_logic; SIGNAL count_ext : std_logic_vector(3 downto 0); SIGNAL count_carry : std_logic;
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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Test Bench....
SIGNAL clk : std_logic; SIGNAL reset : std_logic; SIGNAL count_enable : std_logic; SIGNAL count_ext : std_logic_vector(3 downto 0); SIGNAL count_carry : std_logic;

BEGIN - - Instantiate Component uut: count9 PORT MAP( clk => clk, reset => reset, count_enable => count_enable, count_ext => count_ext, count_carry => count_carry);

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VHDL to Silicon Design Flow

Stimulus Waveforms....
setup : PROCESS BEGIN reset <= '0'; wait for 3 ns; reset <= '1'; wait for 3 ns; reset <= '0'; wait; end PROCESS; count_enable <= '1'; -- tie i/p high clock : PROCESS BEGIN for index in 1 to 100 loop clk <= '0'; wait for 20 ns; clk <= '1'; wait for 20 ns; clk <= '0'; end loop; wait; -- will wait forever END PROCESS;

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Stimulus Waveforms....
- - Define a reset pulse
3 ns Stay low .....

setup : PROCESS BEGIN reset <= '0'; wait for 3 ns; reset <= '1'; wait for 3 ns; reset <= '0'; wait; end PROCESS; count_enable <= '1';

3 ns

- - tie i/p high

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VHDL to Silicon Design Flow

Stimulus Waveforms....
clock : PROCESS - - Define a clock BEGIN for index in 1 to 100 loop clk <= '0'; 20 ns wait for 20 ns; Repeat .... clk <= '1'; wait for 20 ns; clk <= '0'; end loop; 20 ns wait; -- will wait forever END PROCESS;

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

VHDL to Silicon

Design Flow..... Create Project and Select Target Device 4 Create VHDL Source File 4 Enter VHDL code & Syntax Check 4 Create Test Bench & Simulate Synthesis Define Pins Translate, Map & Place and Route device Generate Programming File / Programme device
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VHDL to Silicon Design Flow

Simulate....

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

VHDL to Silicon

Design Flow..... Create Project and Select Target Device 4 Create VHDL Source File 4 Enter VHDL code & Syntax Check 4 Create Test Bench & Simulate 4 Synthesis Define Pins Translate, Map & Place and Route device Generate Programming File / Programme device
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VHDL to Silicon Design Flow

Real devices come in packages ....

....

6 6 F F F F F F
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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Packages go on Boards ....

On Board Clock Generator Programming Port

5 Volt power supply Connection

- +

Push Switches

3x 6 Block of LEDs

CPLD Pin Numbers

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VHDL to Silicon Design Flow

Link signal names to Pins

NET count_out<0> LOC=P16; NET count_out<1> LOC=P17; NET count_out<2> LOC=P18; NET count_out<3> LOC=P19; NET count_pulse LOC=P21; NET clk LOC=P43; NET reset LOC=P14;
"UCF" file

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

VHDL to Silicon

Design Flow..... Create Project and Select Target Device 4 Create VHDL Source File 4 Enter VHDL code & Syntax Check 4 Create Test Bench & Simulate 4 Synthesis 4 Define Pins 4 Translate, Map & Place and Route device Generate Programming File / Programme device
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VHDL to Silicon Design Flow

Translate, Map and Place and Route device....

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

VHDL to Silicon

Design Flow..... Create Project and Select Target Device 4 Create VHDL Source File 4 Enter VHDL code & Syntax Check 4 Create Test Bench & Simulate 4 Synthesis 4 Define Pins 4 Translate, Map & Place and Route device 4 Generate Programming File / Programme device
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VHDL to Silicon Design Flow

Programme device....

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Example Design Wave_Gen...

Clk Reset

Counter

Count
4

Wave_Out

Wave
Count_P ulse

Mode

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VHDL to Silicon Design Flow

Design Entity Wave_Gen

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Architecture Counter....

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VHDL to Silicon Design Flow

Architecture ....& wave_out

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Wave_Gen ... Synthesis

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VHDL to Silicon Design Flow

Synthesis Top Level Schematic

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Synthesis Top Level Schematic a closer look....

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VHDL to Silicon Design Flow

Synthesis Top Level Schematic a closer look....

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Synthesis Top Level Schematic an even closer look....

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VHDL to Silicon Design Flow

Synthesis Top Level Schematic inside block Wave_out

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

VHDL to Silicon
2. Select Device & Package

1. Define what you want

3. write VHDL

4. Simulate

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VHDL to Silicon Design Flow

VHDL to Silicon
5. Synthesis 6. Define Pin-outs

7. Translate & Fit to Device

8. Program Device

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Synthesis Syntax to Hardware

Examples of Logic inferred from VHDL

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VHDL to Silicon Design Flow

Synthesis Syntax to Hardware

Synthesis is the process of Translating a VHDL model into Logic Functions The Logic is "Inferred" from the VHDL. The VHDL Constructs and Syntax used to describe the required behaviour effects the resulting Logic that is generated. The Architecture of the Target Device effects how the Logic is mapped onto the actual gates on the Target Device.
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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

If Then Else

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VHDL to Silicon Design Flow

If Then Else

Multiplexor
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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Xor Conditional Selected

Assignment

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VHDL to Silicon Design Flow

Xor Conditional Selected

Assignment

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Xor - Process

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VHDL to Silicon Design Flow

Xor - Function

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Full Adder

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VHDL to Silicon Design Flow

Full Adder

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Decoder

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VHDL to Silicon Design Flow

Decoder

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Up Counter

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VHDL to Silicon Design Flow

Up Counter

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

Up Down Counter

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VHDL to Silicon Design Flow

Up Down Counter

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VHDL to Silicon...

October 2003

VHDL to Silicon Design Flow

4 bit Ripple Carry Adder

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VHDL to Silicon Design Flow

4 bit Ripple Carry Adder

Results depend on Target Device...

CPLD

FPGA

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