TEAC-LCDV1501M SERVICE MANUAL

CONTENT z PART 1Brief Introduction Of The TEAC-LCDV1501M

Specification Schematic Diagram Printed Circuit

z PART 2Key Ics And Assemblies z PART 3: Detailed Circuit

Main Board DVD Board HI-voltage Board

z PART 4 : Disassemble/Assemble Procedure z PART 5 : Parts List z PART6 : Debug Procedure

Part 1 Brief Introduction Of The TEAC-LCDV1501M

hank you for buying Polaroid LCD-TV Product. As a high-resolution LCD-TV with a 15-inch screen, the TEAC-LCDV1501M incorporates DVD player, LCD display and TV receiver in one system. It adopts an MPEG2 decoding format to achieve horizontal resolution more than 500 lines. Designed with USB and SD/MS/MMC card port, it can be connected to USB device or SD/MS/MMC Card. It has several special functions such as sleep time setting, MTS support, auto TV searching and the picture enlargement. The product can not only be connected to external audio and video signal source and PC, but also features an AV output to extern audio and video device. Specifications
Brand TV Type Dimension Depth Height Width Weight General Exterior Color Screen Size Number of Discs Video Inputs Video Outputs Audio Inputs Laser wavelength Video system Frequency Response Audio signal-to noise rate Audio distortion + noise Dynamic range Channel separation Audio Out Video Out Power Supply Power Consummation Black and Silver 15 in. 1 AV, S-Video, Component, VGA Composite L/R audio input(AV audio inputs share with S-Video and Component), PC audio input 780/650 nm NTSC 20Hz-20KHz + 2.5dB 85 dB -70dB (1KHz) 80Db (1KHz) 70Db (1KHz) Analog audio out Digital audio out:
Out Level: 2V0.2 1.0 , Load: 10k Load: 75 Out Level: 0.5VP-P, Out level: 1VP-P+0.2 load:75 Unbalanced negative AC 100-240V 50/60 Hz DC 12V 4A 48W

Polaroid TEAC-LCDV1501M TV With LCD Screen 176mm 374mm 388mm About 5.8 kg

POWER SUPPLY

Panel 15 TFT LCD

AT49F040B
FLASH

FLI8125
Decoder & Scaler

RGB

PC

IN

LR

Hsync Vsync CVBS

YPbPr 24LC01B/02B

EEPROM

AV IN

LR

YC

SVIDEO IN TUNER AN5832SA

SIF demodulation

LR

SIF

PT2314
audio processor

DVD

MXX29LV160BT
FLASH

TDA1517
audio power amplify

K4S641632H
SDRAM

MT1389HD
Decoder

AT24C16
EEPROM

BA5494
Motor Driver

BA6208F
reversible motor driver

LOARDER

Main Board 3227C (Top View)

Main Board 3227C Bottom view

HI-voltage Board 2872C

POWER Board 2956C (top view)

POWER Board 2956C (bottom view)

VGA Board 3230C(top view)

VGA Board 3230C(bottom view)

DVD Board 2805C(top view)

DVD Board 2805C(bottom view)

Remote Control Board 3229C

Key pad Board

3228C

Card Board 3307C(top view)

Card Board 3307C(bottom view)

USB and Headphone Board 3308C

Part 2 Key ICs And Assemblies

On Main Board
Serial No 1 2 3 4 5 6 7 8 9 10 11 1 2 Position 1U1,1U2 1U3 1U4,1U5 2U1 2U2 2U3 3U1 3U2 3U3 3U4 3U5 U1 Q2,Q6 Type AP1513 LM1117 FDS9435A AT49F040B 24LC01B/02B FLI8125 CD4052B AN5832SA LM7809 PT2314 TDA1517P BIT3193 AP4511M Serial no 1 2 3 4 5 6 7 8 9 10

On DVD board
Position 1U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 Type AP1513 LM1117 MT1389HD BA5954 BA6208F K4S641632H MX29LV160BT AT24C16 NJM4558 WM8714

On HI-voltage Board

ICS ON MAIN BOARD

1.AP1513

Block Diagram

2.LM1117

Single P-Channel Enhancement Mode Field Effect Transistor SO-8 P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
Features

3.FDS9435A

-5.3 A, -30 V, RDS(ON) = 0.045 @ VGS = -10 V, RDS(ON) = 0.075 @ VGS = - 4.5 V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package.

4.AT49F040B
Description
The AT49F040B is a 5-volt-only in-system reprogrammable Flash Memory.Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology,the device offers access times to 55ns with power dissipation of just 110 mW over the commercial temperature range.

Block Diagram

5.24LC01B/02B

1K/2K 2.5V I2CTM Serial EEPROM

6FLI8125

The FLI8125 is a cost-effective, highly-integrated, mixed signal solution for TV and Digital Video applications. It incorporates a multi-standard video decoder, high-speed triple 8-bit Analog-to-Digital Converter(ADC),and front end switching. An integrated VBI Slicer adds Closed Captioning(CC) and Teletext service support, and the built-in microprocessor enables full system control without external devices. Features

Pinout

Pin List I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground

Table 1: Analog Input Port
Pin Name No. I/O VDD18_A B NC GND18_C VDD18_C ADC_TES T AVDD_AD C AGND AGND SV1P GNDS Description 158 AP 159 160 161 162 163 164 165 166 167 Analog Power (1.8V) for A & B Channels. Must be bypassed with 0.1uF capacitor to the analog system ground plane. No Connection. Leave this pin open for normal operation. Analog Ground (1.8V Return) for C channel. Must be directly connected to the analog system ground plane on board. Analog Power (1.8V) for C Channel. Must be bypassed with 0.1uF capacitor to the analog system ground plane. Analog Front End Test O/P. Leave this Pin open. Used for factory testing purpose only. Analog Power (3.3V) for ADC. Must be bypassed with 0.1uF capacitor to the analog system ground plane. Analog Ground. Must be directly connected to the analog system ground plane on board. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog sync input for channel 1. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board.

AG AP O AP AG AG AI AG

A1P GNDS B1P GNDS C1P AVDD_A AN

168 169 170 171 172 173 174

AI AG AI AG AI AP AI

Positive analog input A for channel 1. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input B for channel 1. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input C for channel 1. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Power (3.3V) for ADC of Channel-A. Must be bypassed with 0.1uF capacitor to the analog system ground plane. Negative analog input A for channels 1 through 4. This acts as the return Path for the Sources connected to Channel-A Inputs. This has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog sync input for channel 2. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input A for channel 2. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input B for channel 2. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input C for channel 2. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Power (3.3V) for ADC of Channel-B. Must be bypassed with 0.1uF capacitor to the analog system ground plane. Negative analog input B for channels 1 through 4. This acts as the return Path for the Sources connected to Channel-B Inputs. This has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog sync input for channel 3. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Power (1.8V) for A & B Channels. Must be bypassed with 0.1uF capacitor to the analog system ground plane. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input A for channel 3. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input B for channel 3. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input C for channel 3. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Power (3.3V) for ADC of Channel-C. Must be bypassed with 0.1uF capacitor to the analog system ground plane. Negative analog input C for channels 1 through 4. This acts as the return Path for the Sources connected to Channel-C Inputs. This has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog sync input for channel 4. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input A for channel 4. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input B for channel 4. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Ground. Must be directly connected to the analog system ground plane on board. Positive analog input C for channel 4. The input has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network. Analog Power (3.3V) for ADC of SYNC Channel. Must be bypassed with 0.1uF capacitor to the analog system ground plane. Negative analog sync input for channels 1 through 4. This acts as the return Path for the Sources connected to SV Channel Inputs. This has to be AC coupled using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board. Analog Ground. Must be directly connected to the analog system ground plane on board.

AGND SV2P GNDS A2P GNDS B2P GNDS C2P AVDD_B BN

175 176 177 178 179 180 181 182 183 184

AG AI AG AI AG AI AG AI AP AI

AGND SV3P VDD18_AB GNDS A3P GNDS B3P GNDS C3P AVDD_C CN

185 186 158 187 188 189 190 191 192 193 194

AG AI AP AG AI AG AI AG AI AP AI

AGND SV4P GNDS A4P GNDS B4P GNDS C4P AVDD_SC SVN

195 196 197 198 199 200 201 202 203 204

AG AI AG AI AG AI AG AI AP AI

VO_GND

205

AG

VOUT2

206

AO

VDD18_SC GND18_SC

207 208

AP AG

Analog VOUT signal This is the Analog Video Output from the Decoder in the Composite Video format. This can be amplified and be fed to any video display device. Analog Power (1.8V) for SYNC Channel. Must be bypassed with 0.1uF capacitor to the analog system ground plane. Analog Ground (1.8V Return) for SYNC channel. Must be directly connected to the analog system ground plane on board.

Table 2: Low Bandwidth ADC Input Port

Pin Name VDDA33_LBADC LBADC_IN1 LBADC_IN2 LBADC_IN3 LBADC_IN4 LBADC_IN5 LBADC_IN6 LBADC_RTN VSSA33_LBADC No 1 2 3 4 5 6 7 8 9 I/O AP AI AI AI AI AI AI AG AG Description Analog Power (3.3V) for Low Bandwidth ADC Block. Must be bypassed with 0.1uF capacitor. Low Bandwidth Analog Input-1. The Input signal connected to this Pin, must be bypassed with a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak). Low Bandwidth Analog Input-2. The Input signal connected to this Pin, must be bypassed with a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak). Low Bandwidth Analog Input-3. The Input signal connected to this Pin, must be bypassed with a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak). Low Bandwidth Analog Input-4. The Input signal connected to this Pin, must be bypassed with a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak). Low Bandwidth Analog Input-5. The Input signal connected to this Pin, must be bypassed with a 0.1uF capacitor and could be in the range of 0V to 3.3V (peak to peak). Low Bandwidth Analog Input-6. The Input signal connected to this Pin, must be bypassed with This Pin provides the Return Path for LBADC inputs. Must be directly connected to the analog system ground plane on board. Analog Ground for Low Bandwidth ADC Block. Must be directly connected to the analog system ground plane on board.

Table 3: RCLK PLL Pins

Pin Name GND_RPLL VDD_RPLL_18 VBUFC_RPLL AGND_RPLL XTAL TCLK AVDD_RPLL_33 No 11 12 13 14 15 16 17 I/O DG DP O AG AO AI AP Description Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground plane. Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to Ground Plane. Test Output. Leave this Pin Open. This is reserved for Factory Testing Purpose. Analog ground for the Reference DDS PLL. Must be directly connected to the analog system ground plane. Crystal oscillator output. Reference clock (TCLK) from the 14.3MHz crystal oscillator. Analog Power (3.3V) for RCLK PLL. Must be bypassed with 0.1uF capacitor.

Table 4: Digital Video Input Port

Pin Name VID_CLK_1 VIDIN_HS No 153 122 I/O I I Description Video port data clock input meant for Video Input 1. Up to 75Mhz [Input, 5V-tolerant] When Video Input 1 is in BT656 Mode, this Pin acts as Horizontal Sync Input for Video Input 2. OR when Video Input 1 is in 16 Bit Mode this Pin acts as Horizontal Sync Input for Video Input 1. OR this Pin acts as Horizontal Sync Input for 24 Bit Video Input

VIDIN_VS

121

When Video Input 1 is in BT656 Mode, this Pin acts as Vertical Sync Input for Video Input 2. OR when Video Input 1 is in 16 Bit Mode this Pin acts as Vertical Sync Input for Video Input 1. OR this Pin acts as Vertical Sync Input for 24 Bit Video Input

VID_DATA_IN_0 VID_DATA_IN_1 VID_DATA_IN_2 VID_DATA_IN_3 VID_DATA_IN_4 VID_DATA_IN_5 VID_DATA_IN_6 VID_DATA_IN_7 Pin Name

135 136 137 138 139 140 141 142 No

IO

Input YUV data in 8-bit BT656 of Video Input 1 [Bi-Directional, 5V-tolerant] OR Input Y Data in case of 16 Bit Video Input (CCIR601) of Video Input 1 OR Input Red Data in case of 24 Bit Video Input

I/O

Description

VID_DATA_IN_8 VID_DATA_IN_9 VID_DATA_IN_10 VID_DATA_IN_11 VID_DATA_IN_12 VID_DATA_IN_13 VID_DATA_IN_14 VID_DATA_IN_15 VID_DATA_IN_16 VID_DATA_IN_17 VID_DATA_IN_18 VID_DATA_IN_19 VID_DATA_IN_20 VID_DATA_IN_21 VID_DATA_IN_22 VID_DATA_IN_23 VID_CLK2 VID_DE/FLD

145 146 147 148 149 150 151 152 123 124 125 128 129 130 131 132 118 115

IO

Input Pr / Pb Data in case of 16 Bit Video Input (CCIR601) of Video Input 1 OR Input Green Data in case of 24 Bit Video Input

IO

Input Blue Data in case of 24 Bit Video Input OR Video Input 2 in 8-bit with Embedded Sync / Separate Sync Sync in which case VID_DATA_IN_16 acts as the LSB of the 8-bit Video input and VID_DATA_IN_23 acts as the MSB of the 8-bit Video input.

I I

Video port data clock input meant for Video Input 2. Up to 75Mhz [Input, 5V-tolerant] Video Active Signal Input or the Field Signal Input from external Digital Video Source.

Note: In case of Multiple Digital Video Input Sources, only one source could be in 8-Bit with embedded Sync (BT656 mode) format.
Table 5: System Interface
Pin Name RESETn TEST GPIO15 No 10 20 21 I/O I I IO Description Hardware Reset (active low) [Schmitt trigger, 5v-tolerant] Connect to ground with 0.01uF (or larger) capacitor. For normal mode of operation connect this Pin to Ground. This pin is available as a general-purpose input/output port. Also it is optionally programmable to give out the external chip select signal meant for external SRAM. Refer to note below. Horizontal Sync signal Input-2. Used when Analog RGB component signal carries separate HSYNC signal. Vertical Sync signal Input-2. Used when Analog RGB component signal carries separate VSYNC signal. Host input clock or 186 UART Data In or JTAG clock signal. [Input, Schmitt trigger, 5V-tolerant] Host input data or 186 UART Data Out or JTAG mode signal. [Bi-directional, Schmitt trigger, slew rate limited, 5V-tolerant] DDC2Bi clock for VGA Port [internal 10K pull-up resistor] DDC2Bi data for VGA Port [internal 10K pull-up resistor] Clock signal from Master Serial 2 Wire Interface Controller Data signal meant for Master Serial 2 Wire interface Controller This Pin accepts the Input Clock signal in case of Boundary Scan Mode. This Pin accepts the Input Data signal in case of Boundary Scan Mode. This Pin accepts the Input Test Mode Select signal in case of Boundary Scan Mode. This Pin accepts the Boundary Scan Reset signal in case of Boundary Scan Mode. Input from Infra Red Decoder can be connected to this Pin. When not used, this pin is available as General Purpose Input/output Port. Input Interrupt Request signal can be connected to this Pin. When not used, this pin is available as General Purpose Input/output Port. This Pin will give out the Interrupt Signal to interrupt external Micro. When not used, this pin is available as General Purpose Input/output Port. This Pin accepts the Clock signal from External Serial 2 Wire interface Bus if FLI8125 is programmed to be in Slave mode. When not used, this pin is available as General Purpose Input/output Port. This Pin acts as the Data I/O signal when used with External Serial 2 Wire interface Bus if FLI8125 is programmed to be in Slave mode. Or this Pin is programmable to give out Address # 18 from the Internal Micro when used with 512K External Memory. When not used, this pin is available as General Purpose Input/output Port. This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use. When not used, this pin is available as General Purpose Input/output Port. This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use. When not used, this pin is available as General Purpose Input/output Port. This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use. When not used, this pin is available as General Purpose Input/output Port. Description

HSYNC2 VSYNC2 HOST_SCLK HOST_SDATA DDC_SCLK DDC_SDATA MSTR_SCLK MSTR_SDATA TCK TDI TMS TRST GPIO6/IRin GPIO7/IRQin GPIO8/IRQout GPIO9/SIPC_SCLK

22 23 24 25 26 27 30 31 34 35 36 37 38 41 42 43

I I IO IO IO IO O IO IO IO IO IO IO IO IO IO

GPIO10/SIPC_SDATA/ A18

44

IO

GPIO11/PWM0 GPIO12/PWM1 GPIO13/PWM2 Pin Name

47 48 51 No

IO IO IO I/O

GPIO14/PWM3/ SCART16

52

IO

This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use. Or it can be programmed to sense the Fast Blank Input signal from a SCART I/P source. When not used, this pin is available as General Purpose Input/output Port. This Pin provides the Output Data in case of Boundary Scan Mode. Horizontal Sync signal Input-1. Used when Analog RGB component signal carries separate HSYNC signal. Vertical Sync signal Input-1. Used when Analog RGB component signal carries separate VSYNC signal. Clock Output meant for External OSD Controller Horizontal Sync Output meant for External OSD Controller Vertical Sync Output meant for External OSD Controller Field Signal Output meant for External OSD Controller These Pins provide the Panel Data as shown in the TTL Display Interface Table below. These are available as General Purpose Input / Output Pins when not used as Panel Data.

TDO HSYNC1 VSYNC1 101 102 XOSD_CLK XOSD_HS PD20/B4/GPIO0 PD21/B5/GPIO1 PD22/B6/GPIO2 PD23/B7/GPIO3

55 156 157

O I I O O O O IO

103 104 86 87 88 89

Table 6: LVDS Display Interface

Pin Name PBIAS PPWR AVDD_LV_33 VCO_LV AVSS_LV AVDD_OUT_LV_33 CH3P_LV_E CH3N_LV_E CLKP_LV_E CLKN_LV_E CH2P_LV_E CH2N_LV_E CH1P_LV_E CH1N_LV_E CH0P_LV_E CH0N_LV_E AVSS_OUT_LV AVDD_OUT_LV_33 CH3P_LV_O CH3N_LV_O CLKP_LV_O CLKN_LV_O CH2P_LV_O CH2N_LV_O CH1P_LV_O CH1N_LV_O CH0P_LV_O CH0N_LV_O AVSS_OUT_LV AVDD_OUT_LV_33 No 53 54 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 I/O O O DP O G DP O O O O O O O O O O G DP O O O O O O O O O O G DP Description Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant] Panel Power Control [Tri-state output, 5V- tolerant] Digital Power for LVDS Block. Connect to digital 3.3V supply. Reserved. Output for Testing Purpose only at Factory. Ground for LVDS outputs. Digital Power for LVDS outputs. Connect to digital 3.3V supply. These form the Differential Data Output for Channel 3 (Even). These form the Differential Clock Output Even Channel. These form the Differential Data Output for Channel 2 (Even). These form the Differential Data Output for Channel 1 (Even). These form the Differential Data Output for Channel 0 (Even). Ground for LVDS outputs. Digital Power for LVDS outputs. Connect to digital 3.3V supply. These form the Differential Data Output for Channel 3 (Odd). These form the Differential Clock Output Odd Channel. These form the Differential Data Output for Channel 2 (Odd). These form the Differential Data Output for Channel 1 (Odd). These form the Differential Data Output for Channel 0 (Odd). Ground for LVDS outputs. Digital Power for LVDS outputs. Connect to digital 3.3V supply.

Table 7: TTL Display Interface

Pin Name No I/O Description For 8-bit panels PBIAS PPWR AVDD_LV_33 VCO_LV AVSS_LV AVDD_OUT_LV_33 R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 AVSS_OUT_LV AVDD_OUT_LV_33 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 AVSS_OUT_LV AVDD_OUT_LV_33 PD20/B4 PD21/B5 PD22/B6 PD23/B7 DEN DHS DVS DCLK PD24 53 54 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 86 87 88 89 90 91 92 93 115 O O DP O G DP O O O O O O O O O O G DP O O O O O O O O O O G DP O O O O O O O O O For 6-bit panels

Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant] Panel Power Control [Tri-state output, 5V- tolerant] Digital Power for TTL Block. Connect to digital 3.3V supply. Reserved. Output for Testing Purpose only at Factory. Ground for TTL outputs. Digital Power for TTL outputs. Connect to digital 3.3V supply. Red channel bit 0 (Even) Red channel bit 1 (Even) Red channel bit 2 (Even) Red channel bit 3 (Even) Red channel bit 4 (Even) Red channel bit 5 (Even) Red channel bit 6 (Even) Red channel bit 7 (Even) Green channel bit 0 (Even) Green channel bit 1 (Even) Ground for TTL outputs. Digital Power for TTL outputs. Connect to digital 3.3V supply. Green channel bit 2 (Even) Green channel bit 3 (Even) Green channel bit 4 (Even) Green channel bit 5 (Even) Green channel bit 6 (Even) Green channel bit 7 (Even) Blue channel bit 0 (Even) Blue channel bit 1 (Even) Blue channel bit 2 (Even) Blue channel bit 3 (Even) Ground for TTL outputs. Digital Power for TTL outputs. Connect to digital 3.3V supply. Blue channel bit 4 (Even) Blue channel bit 5 (Even) Blue channel bit 6 (Even) Blue channel bit 7 (Even) Display Data Enable Display Horizontal Sync. Display Vertical Sync. Display Pixel Clock Red channel bit 0 (Odd) Not used. Blue channel bit 2 (Even) Blue channel bit 3 (Even) Blue channel bit 4 (Even) Blue channel bit 5 (Even) Green channel bit 0 (Even) Green channel bit 1 (Even) Green channel bit 2 (Even) Green channel bit 3 (Even) Green channel bit 4 (Even) Green channel bit 5 (Even) Not used. Not used. Blue channel bit 0 (Even) Blue channel bit 1 (Even) Not used. Not used. Red channel bit 0 (Even) Red channel bit 1 (Even) Red channel bit 2 (Even) Red channel bit 3 (Even) Red channel bit 4 (Even) Red channel bit 5 (Even) Not used. Not used.

27

Pin Name

No

I/O

Description For 8-bit panels For 6-bit panels Not used. Red channel bit 0 (Odd) Red channel bit 1 (Odd) Red channel bit 2 (Odd) Red channel bit 3 (Odd) Red channel bit 4 (Odd) Red channel bit 5 (Odd) Not used. Not used. Green channel bit 0 (Odd) Green channel bit 1 (Odd) Green channel bit 2 (Odd) Green channel bit 3 (Odd) Green channel bit 4 (Odd) Green channel bit 5 (Odd) Not used. Not used. Blue channel bit 0 (Odd) Blue channel bit 1 (Odd) Blue channel bit 2 (Odd) Blue channel bit 3 (Odd) Blue channel bit 4 (Odd) Blue channel bit 5 (Odd)

PD25 PD26 PD27 PD28 PD29 PD30 PD31 PD32 PD33 PD34 PD35 PD36 PD37 PD38 PD39 PD40 PD41 PD42 PD43 PD44 PD45 PD46 PD47

114 113 112 111 110 109 108 107 106 105 104 103 102 101 123 124 125 128 129 130 131 132 118

O O O O O O O O O O O O O O O O O O O O O O O

Red channel bit 1 (Odd) Red channel bit 2 (Odd) Red channel bit 3 (Odd) Red channel bit 4 (Odd) Red channel bit 5 (Odd) Red channel bit 6 (Odd) Red channel bit 7 (Odd) Green channel bit 0 (Odd) Green channel bit 1 (Odd) Green channel bit 2 (Odd) Green channel bit 3 (Odd) Green channel bit 4 (Odd) Green channel bit 5 (Odd) Green channel bit 6 (Odd) Green channel bit 7 (Odd) Blue channel bit 0 (Odd) Blue channel bit 1 (Odd) Blue channel bit 2 (Odd) Blue channel bit 3 (Odd) Blue channel bit 4 (Odd) Blue channel bit 5 (Odd) Blue channel bit 6 (Odd) Blue channel bit 7 (Odd)

Note: In case of 24 Bit TTL Panels the RGB Odd Channel Outputs will not be used. In that case they can be made available for other purposes as Address & Data from On-Chip Micro or Digital Video Input Data.

Table 8: Parallel/Serial ROM Interface

Pin Name A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 No 95 96 100 101 102 103 104 105 106 107 108 I/O O Description 256K x8 PROM Address. These pins also have bootstrap functionality. For serial SPI ROM interface: - ROM_ADDR17 will be Serial Clock (ROM_SCLK) - ROM_ADDR16 will be Serial Data Output (ROM_SDO) For 512K X 8 PROM, Address Signal A18 is available thru Pin # 44 which is GPIO10.

28

A6 A5 A4 A3 A2 A1 A0

109 110 111 112 113 114 115

D7 D6 D5 D4 D3 D2 D1 D0 ROM_OEN ROM_SDI/ ROM_WEN

132 131 130 129 128 125 124 123 118 97

IO

External PROM data input.

O O

External PROM data Output Enable. External PROM data Write Enable (for In-System-Programming of FLASH) or Serial Data Input (SDI) for SPI ROM interface.

ROM_SCSN/ ROM_CSN

94

External PROM data Chip Select or Serial PROM Chip Select (ROM_SCSN) for SPI ROM interface.

Table 9: Digital Power and Ground

Pin Name RVDD_3.3 CVDD_1.8 CRVSS No 32 49 98 116 154 18 28 39 45 84 119 126 133 143 19 29 33 40 46 50 85 99 117 120 127 134 144 155 I/O P P G Description Ring VDD. Connect to digital 3.3V. Core VDD. Connect to digital 1.8V. Chip ground for core and ring.

Table 10: JTAG Boundary Scan

Pin Name TCK TDO TDI TMS TRST No 34 55 35 36 37 I/O I O I I I Description JTAG Boundary Scan TCK signal JTAG Boundary Scan TDO signal JTAG Boundary Scan TDI signal. Pad has internal 50K pull-up resistor. JTAG Boundary Scan RST signal. Pad has internal 50K pull-up resistor. JTAG Boundary Scan TMS signal. Pad has internal 50K pull-up resistor.

29

7.CD4052B
The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs.

Pinouts .

30

8.AN5832SA
Silicon Monolithic Bipolar IC DIL 32-Pin Plastic Package (S0 Type) Demodulation of US TV sound multiplex input Function SIF demodulation Zenith TV sound multiplex decoder dbx TV noise reduction AGC (Automatic Gain Control) Description of Test Circuit and Test Method

31

Pin Description

32

9.LM7809

33

10.PT2314
Description PT2314 is a four-channel input digital audio processor utilizing CMOS Technology. Volume, Bass, Treble and Balance are incorporated into a single chip. Loudness Function and Selectable Input Gain are also provided to build a highly effective electronic audio processor having the highest performance and reliability with the least external components. All functions are programmable using the I2C Bus. The pin assignments and application circuit are optimized for easy PCB layout and cost saving advantage for audio application. Features CMOS Technolog Least External Components Treble and Bass Control Loudness Function 4 Stereo Inputs with Selectable Input Gain Input/Output for External Noise Reduction System/Equalizer 2 Independent Speaker Controls for Balance Control Independent Mute Function Volume Control in 1.25 dB/step Low Distortion Low Noise and DC Stepping Controlled by I2C Bus Micro-Processor Interface Available in 28 Pins, DIP/SO Package Applications Car Stereo (Audio) Hi-Fi Audio System Pin Configuration

34

Pin Description

35

11.TDA1517P

2 x 6 W stereo power amplifier

The TDA1517 is an integrated class-B dual output amplifier in a plastic single in-line medium power package with fin (SIL9MPF), a plastic rectangular-bent single in-line medium power package with fin (RBS9MPF) or a plastic heat-dissipating dual in-line package (HDIP18). The device is primarily developed for multi-media applications. Features Requires very few external components High output power Fixed gain Good ripple rejection Mute/standby switch AC and DC short-circuit safe to ground and VP Thermally protected Reverse polarity safe Capability to handle high energy on outputs (VP = 0 V) No switch-on/switch-off plop Electrostatic discharge protection Pin Description Pin Configuration
SYMBOL
-INV1 SGND SVRR OUT1 PGND OUT2 VP M/SS -INV2

PIN
1 2 3 4 5 6 7 8 9

DESCRIPTION
non-inverting input 1 signal ground supply voltage ripple rejection output output 1 power ground output 2 supply voltage mute/standby switch input non-inverting input 2

DC Characteristics
VP = 14.4 V; Tamb = 25 C; measured in Fig.6; unless otherwise specified.

Note
The circuit is DC adjusted at VP = 6 to 18 V and AC operating at VP = 8.5 to 18 V. 36

ICS ON DVD BOARD

1.AP1513 (See Page 13) 2.LM1117 (See Page 14) 3.MT1389HD

Abbr. : SR : Slew Rate PU : Pull Up PD : Pull Down SMT : Schmitt Trigger 2MA~16MA : Output buffer driving strength.
Pin Main Alt. Type Description

RF Interface ( 26 ) 231 232 252 253 254 RFGND18 RFVDD18 OSP OSN RFGC Ground Power Analog output Analog output Analog output Analog ground Analog power 1.8V RF Offset cancellation capacitor connecting RF Offset cancellation capacitor connecting RF AGC loop capacitor connecting for DVD-ROM Current reference input. It generates reference current for 255 IREF Analog Input RF path. Connect an external 15K resistor to this pin and AVSS. 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 AVDD3 AGND DVDA DVDB DVDC DVDD DVDRFIP DVDRFIN MA MB MC MD SA SB SC SD CDFON CDFOP TNI TPI Power Ground Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog power 3.3V Analog ground AC coupled input path A AC coupled input path B AC coupled input path C AC coupled input path D AC coupled DVD RF signal input RFIP AC coupled DVD RF signal input RFIN DC coupled main-beam RF signal input A DC coupled main-beam RF signal input B DC coupled main-beam RF signal input C DC coupled main-beam RF signal input D DC coupled sub-beam RF signal input A DC coupled sub-beam RF signal input B DC coupled sub-beam RF signal input C DC coupled sub-beam RF signal input D CD focusing error negative input CD focusing error positive input 3 beam satellite PD signal negative input 3 beam satellite PD signal positive input

37

ALPC ( 4 ) Pin 20 21 22 23 Main MDI1 MDI2 LDO2 LDO1 Alt. Type Analog Input Analog Input Analog Output Analog Output Description Laser power monitor input Laser power monitor input Laser driver output Laser driver output

ADC Power ( 2 ) 244 245 ADCVDD3 ADCVSS Power Ground Analog 3.3V Power for ADC Analog ground for ADC VPLL (3) 43 44 45 VPLLVSS CAPPAD VPLLVDD3 Ground Analog Inout Power Analog ground for VPLL VPLL External Capacitance connection Analog 3.3V Power for VPLL

Reference Voltage ( 3 ) 28 29 30 V2REFO V20 VREFO Analog output Analog output Analog output Reference voltage 2.8V Reference voltage 2.0V Reference voltage 1.4V

Analog Monitor Output ( 7 ) 24 25 SVDD3 CSO RFOP Power Analog output Analog power 3.3V 1) 2) 1) 2) RFRP low pass, or Negative main beam summing output Central servo Positive main beam summing output

26 27 31 32 33

RFLVL SGND FEO TEO TEZISLV

RFON

Analog output Ground Analog output Analog output Analog output

Analog ground Focus error monitor output Tracking error monitor output TE Slicing Level

Analog Servo Interface ( 6 ) 246 247 248 249 250 251 RFVDD3 RFRPDC RFRPAC HRFZC CRTPLP RFGND Power Analog output Analog Input Analog Input Analog output Ground Analog Power RF ripple detect output RF ripple detect input(through AC-coupling) High frequency RF ripple zero crossing Defect level filter capacitor connecting Analog Power

38

RF Data PLL Interface ( 9 ) Pin 235 236 237 238 239 240 241 242 243 Main JITFO JITFN PLLVSS IDACEXLP PLLVDD3 LPFON LPFIP LPFIN LPFOP Alt. Type Analog output Analog Input Ground Analog output Power Analog Output Analog Input Analog Input Analog Output Description The output terminal of RF jitter meter. The input terminal of RF jitter meter. Ground pin for data PLL and related analog circuitry. Data PLL DAC Low-pass filter Power pin for data PLL and related analog circuitry. The negative output of loop filter amplifier The positive input terminal of loop filter amplifier. The negative input terminal of loop filter amplifier. The positive output of loop filter amplifier

Motor and Actuator Driver Interface ( 10 ) 34 35 36 37 38 39 OP_OUT OP_INN OP_INP DMO FMO TROPENP WM PWMOUT 1 TRO V_ADIN9 Analog output Analog input Analog input Analog Output Analog Output Analog Output Op amp output. Op amp negative input Op amp positive input Disk motor control output. PWM output. Feed motor control. PWM output. Tray PWM output / Tray open output. 1) 2) 1st General PWM output, or Version AD input 9

40

Analog Output

41

Analog Output

Tracking servo output. PDM output of tracking servo compensator. Focus servo output. PDM output of focus servo compensator

42

FOO

Analog Output LVTTL 3.3V Input,

FG 50 (Diogital pin) V_ADIN8

Schmitt Input, pull up , with analog input path for V_ADIN8

1) 2)

Motor Hall sensor input, or Version AD input 8

General Power/Ground ( 18 ) 55,93, 142,160, 174, 213 81,178 65,96,11 8, 131,145, 156, 170, 208 90, 148 DVSS Ground 3.3V Ground pin for internal digital circuitry DVDD3 Power 3.3V power pin for internal digital circuitry DVSS Ground 1.8V Ground pin for internal digital circuitry DVDD18 Power 1.8V power pin for internal digital circuitry

39

Micro Controller and Flash Interface (48) Pin Main Alt. Type Inout 62 HIGHA0 2~16MA, SR PU Inout 74 HIGHA1 2~16MA, SR PU Inout 73 HIGHA2 2~16MA, SR PU Inout 72 HIGHA3 2~16MA, SR PU Inout 71 HIGHA4 2~16MA, SR PU Inout 70 HIGHA5 2~16MA, SR PU Inout 69 HIGHA6 2~16MA, SR PU Inout 68 HIGHA7 2~16MA, SR PU 89 86 85 84 83 82 80 79 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Inout 2~16MA, SR Inout 2~16MA, SR Inout 2~16MA, SR Inout 2~16MA, SR Inout 2~16MA, SR Inout 2~16MA, SR Inout 2~16MA, SR Inout 2~16MA, SR Inout 92 IOA0 2~16MA, SR PU Microcontroller address 0 / IO Microcontroller address/data 7 Microcontroller address/data 6 Microcontroller address/data 5 Microcontroller address/data 4 Microcontroller address/data 3 Microcontroller address/data 2 Microcontroller address/data 1 Microcontroller address/data 0 Microcontroller address 15 Microcontroller address 14 Microcontroller address 13 Microcontroller address 12 Microcontroller address 11 Microcontroller address 10 Microcontroller address 9 Microcontroller address 8 Description

40

Pin

Main IOA1

Alt.

Type Inout 2~16MA, SR PU Inout

Description

77

Microcontroller address 1 / IO

56

IOA2

2~16MA, SR PU Inout

Microcontroller address 2 / IO

57

IOA3

2~16MA, SR PU Inout

Microcontroller address 3 / IO

58

IOA4

2~16MA, SR PU Inout

Microcontroller address 4 / IO

59

IOA5

2~16MA, SR PU Inout

Microcontroller address 5 / IO

60

IOA6

2~16MA, SR PU Inout

Microcontroller address 6 / IO

61

IOA7

2~16MA, SR PU

Microcontroller address 7 / IO

67

A16

Output 2~16MA, SR Output 2~16MA, SR Inout

Flash address 16

91

A17

Flash address 17

63

IOA18

2~16MA, SR SMT Inout

Flash address 18 / IO

64

IOA19

2~16MA, SR SMT Inout

Flash address 19 / IO

75

IOA20

2~16MA, SR SMT Inout

Flash address 20 / IO

1) Flash address 21 / IO 2) While External FLASH size <= 2MB: I) GPIO

87

IOA21

2~16MA, SR SMT Inout

88

ALE

2~16MA, SR PU, SMT

Microcontroller address latch enable

41

Pin 78

Main IOOE#

Alt.

Type Inout 2~16MA, SR SMT

Description

Flash output enable, active low / IO

66

IOWR#

Inout 2~16MA, SR SMT Flash write enable, active low / IO

76

IOCS#

Inout 2~16MA, SR PU, SMT Flash chip select, active low / IO

94

UWR#

Inout 2~16MA, SR PU, SMT Microcontroller write strobe, active low

95

URD#

Inout 2~16MA, SR PU, SMT Microcontroller read strobe, active low

97

UP1_2

Inout 4MA, SR PU, SMT Microcontroller port 1-2

98

UP1_3

Inout 4MA, SR PU, SMT Microcontroller port 1-3

99

UP1_4

Inout 4MA, SR PU, SMT Microcontroller port 1-4

100

UP1_5

Inout 4MA, SR PU, SMT Inout 1) Microcontroller port 1-6 2) I2C clock pin Microcontroller port 1-5

101

UP1_6

SCL

4MA, SR PU, SMT Inout

1) Microcontroller port 1-7 2) I2C data pin

102

UP1_7

SDA

4MA, SR PU, SMT Inout

1) Microcontroller port 3-0 2) 8032 RS232 RXD

103

UP3_0

RXD

4MA, SR PU, SMT Inout

1) Microcontroller port 3-1 2) 8032 RS232 TXD

104

UP3_1

TXD

4MA, SR PU, SMT Inout

1) Microcontroller port 3-4 2) Hardwired RD232 RXD 3) I2C clock pin

105

UP3_4

RXD SCL

4MA, SR PU, SMT

42

Inout 106 UP3_5 TXD SDA 4MA, SR PU, SMT Input SMT Inout 110 INTO# 4MA, SR PU, SMT

1) Microcontroller port 3-5 2) Hardwired RD232 TXD

3) I2C data pin

IR control signal input

109

IR

Microcontroller external interrupt 0, active low

Audio interface ( 28 ) Pin Main Alt. Type Description 1) 204 SPMCLK SCLK0 Inout Non-pull 2) Audio DAC master clock of SPDIF input While SPDIF input is not used: I) Serial interface port 0 clock pin II) GPIO 1) 205 SPDATA SDIN0 Inout Non-pull 2) Audio data of SPDIF input While SPDIF input is not used: I) Serial interface port 0 data-in II) GPIO 1) 206 SPLRCK SDO0 Inout Non-pull 2) Audio left/right channel clock of SPDIF input While SPDIF input is not used: I) Serial interface port 0 data-out II) GPIO 1) 2) 207 SPBCK SDCS0 ASDATA5 Inout Non-pull Audio bit clock of SPDIF input While SPDIF input is not used: I) Serial interface port 0 chip select II) Audio serial data 5 part I : DSD data sub-woofer channel or Microphone output III) GPIO 1) 209 ALRCK Inout 4MA, PD, SMT Output 210 ABCK Fs64 4MA Non-pull Inout 211 ACLK 4MA Non-pull Audio DAC master clock 2) Audio left/right channel clock Trap value in power-on reset: I) 1 : use external 373 II) 0: use internal 373

1) 2)

Audio bit clock Phase de-modulation

43

1) 2) Inout 197 ASDATA0 4MA PD SMT 4) 3)

Audio serial data 0 (Front-Left/Front-Right) DSD data left channel Trap value in power-on reset : I) 1 : manufactory test mode II) 0 : normal operation While using external channels: I) GPO_2

1) 2) Inout 202 ASDATA1 4MA PD SMT 4) 3)

Audio serial data 1 (Left-Surround/Right-Surround) DSD data right channel Trap value in power-on reset : I) 1 : manufactory test mode II) 0 : normal operation While using external channels: I) GPO_1

1) 2) 203 ASDATA2 Inout 4MA PD SMT 3) 4)

Audio serial data 2 (Center/LFE) DSD data left surround channel Trap value in power-on reset : I) 1 : manufactory test mode II) 0 : normal operation While using external channels: I) GPO_0

1)

Audio serial data 3 (Center-back/ Center-left-back/Center-right-back, in 6.1 or 7.1 mode)

Inout 212 ASDATA3 4MA PD SMT

2) 3)

DSD data right surround channel Trap value in power-on reset : I) 1 : manufactory test mode II) 0 : normal operation

4)

While only 2 channels output: I) GPO_0

1) 2) Inout 214 ASDATA4 INT1# 4MA PD SMT 4) 3)

Audio serial data 4 (Down-mixed Left/Right) DSD data center channel Trap value in power-on reset : I) 1 : manufactory test mode II) 0 : normal operation While only 2 channels output: I) Microcontroller external interrupt 1 II) GPO_0

1) 215 MC_DATA INT2# Inout PD SMT 2)

Microphone serial input While not support Microphone: I) Microcontroller external interrupt 2 II) GPO_0

Output 216 SPDIF 2~16MA, SR : ON/OFF Non-pull SPDIF output

44

217 218 219 220 221 222

APLLVDD3 APLLCAP APLLVSS ADACVSS2 ADACVSS1 ARF GPIO

Power Analog Inout Ground Ground Ground Output

3.3V Power pin for audio clock circuitry APLL External Capacitance connection Ground pin for audio clock circuitry Ground pin for AUDIO DAC circuitry Ground pin for AUDIO DAC circuitry 1) 2) 1) AUDIO DAC Sub-woofer channel output While internal AUDIO DAC not used: GPIO AUDIO DAC Right Surround channel output While internal AUDIO DAC not used: a. SDATA3 b. GPIO 1) AUDIO DAC Right channel output While internal AUDIO DAC not used: a. SDATA1 b. GPIO

223

ARS

GPIO

Output

2)

224

AR

GPIO

Output

2)

225

AVCM

Analog

AUDIO DAC reference voltage 1) AUDIO DAC Left Surround channel output While internal AUDIO DAC not used: a. SDATA2 b. GPIO 1) AUDIO DAC Left Surround channel output While internal AUDIO DAC not used: a. SDATA0 b. GPIO

226

AL

GPIO

Output

2)

227

ALS

GPIO

Output

2)

228 229 230

ALF ADACVDD1 ADACVDD2

GPIO

Output Power Power

1) 2)

AUDIO DAC Center channel output While internal AUDIO DAC not used:GPIO

3.3V power pin for AUDIO DAC circuitry 3.3V power pin for AUDIO DAC circuitry

Video Interface ( 18 ) 196 195 194 193 192 191 190 189 188 187 DACVDDC VREF FS YUV0 DACVSSC YUV1 DACVDDB YUV2 DACVSSB YUV3 CVBS C Y CIN Power Analog Analog Output 4MA, SR Ground Output 4MA, SR Power Output 4MA, SR Ground Output 4MA, SR 3.3V power pin for VIDEO DAC circuitry Bandgap reference voltage Full scale adjustment 1) 2) Video data output bit 0 Compensation capacitor

Ground pin for VIDEO DAC circuitry 1) 2) Video data output bit 1 Analog Y output

3.3V power pin for VIDEO DAC circuitry 1) 2) Video data output bit 2 Analog chroma output

Ground pin for VIDEO DAC circuitry 1) 2) Video data output bit 3 Analog composite output

45

186 185 184 183

DACVDDA YUV4 DACVSSA YUV5 B/Cb/Pb Y/G

Power Output 4MA, SR Ground Output 4MA, SR Output 4MA, SR Inout

3.3V power pin for VIDEO DAC circuitry 1) 2) Video data output bit 4 Green or Y

Ground pin for VIDEO DAC circuitry 1) 2) 1) 2) 1) 2) Video data output bit 5 Blue or CB Video data output bit 6 Red or CR Vertical sync input/output While no External TV-encoder: I) Vertical sync for video-input II) Version AD input port 1 III) GPIO 1) Video data output bit 7 While no External TV-encoder: I) Microcontroller external interrupt 3 II) Audio serial data 5 part II : DSD data sub-woofer channel or Microphone output III) GPIO 1) Horizontal sync input/output While no External TV-encoder: I) Horizontal sync for video-input II) Microcontroller external interrupt 4 III) Version AD input port 2 IV) GPIO MISC ( 12 )

182

YUV6

R/Cr/Pr

181

VSYN

V_ADIN1

4MA, SR SMT Non-pull

Inout 180 YUV7 INT3# ASDATA5 4MA, SR SMT Non-pull

2)

Inout 179 HSYN INT4# V_ADIN2 4MA, SR SMT Non-pull

2)

46 47 48 49 108

USB_VSS USBP USBM USB_VDD3 PRST#

USB Ground Analog Inout Analog Inout USB Power Input PU, SMT Input PD, SMT Output Input Inout Pull-Down Inout Pull-Down GPIO_5 Inout Pull-Up Inout Pull-Up

USB ground pin USB port DPLUS analog pin USB port DMINUS analog pin USB Power pin 3.3V Power on reset input, active low

107 233 234 201

ICE XTALO XTALI GPIO_3

Microcontroller ICE mode enable 27M crystal out 27M crystal in GPIO

200

GPIO_4

GPIO

199

RCLKB

GPIO

198

RVREF

GPIO_6

GPIO

46

Dram Interface ( 58 ) ( Sorted by position ) 176 C_0 IO_0 (RD16) IO_1 (RD17) IO_2 (RD18) IO_3 (RD19) IO_4 (RD20) IO_5 (RD21) IO_6 (RD22) IO_7 (RD23) Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) Digital Video output C bit 0 GPIO Digital Video output C bit 1 GPIO Digital Video output C bit 2 GPIO Digital Video output C bit 3 GPIO Digital Video output C bit 4 GPIO Digital Video output C bit 5 GPIO Digital Video output C bit 6 GPIO Digital Video output C bit 7 GPIO

175

C_1

173

C_2

172

C_3

171

C_4

169

C_5

168

C_6

167

C_7

177

IO_17

(DQM2) IO_8 (DQM3) IO_9 (RD24) IO_10 (RD25) IO_11 (RD26) IO_12 (RD27) IO_13 (RD28) IO_14 (RD29) IO_15 (RD30) IO_16 (RD31)

Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull Inout Non-pull

GPIO 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) Digital Video output Clock GPIO Digital Video output Y bit 0 GPIO Digital Video output Y bit 1 GPIO Digital Video output Y bit 2 GPIO Digital Video output Y bit 3 GPIO Digital Video output Y bit 4 GPIO Digital Video output Y bit 5 GPIO Digital Video output Y bit 6 GPIO Digital Video output Y bit 7 GPIO

166

YUVCLK

165

Y_0

164

Y_1

163

Y_2

162

Y_3

161

Y_4

159

Y_5

158

Y_6

157

Y_7

155 154 153 152

RA4 RA5 RA6 RA7

Inout Inout Inout Inout

DRAM address 4 DRAM address 5 DRAM address 6 DRAM address 7

47

151 150 149 147 146 144 143 141 140 139 138 137 136 135 134 133 132 130 129 128

RA8 RA9 RA11 CKE RCLK RA3 RA2 RA1 RA0 RA10 BA1 BA0 RCS# RAS# CAS# RWE# DQM1 IO_18 RD8 RD9 (DQS1)

Inout Inout Inout Pull-Down output Inout Inout Inout Inout Inout Inout Inout Inout output output output output Inout Inout Non-pull Inout Inout

DRAM address 8 DRAM address 9 DRAM address bit 11 DRAM clock enable Dram clock DRAM address 3 DRAM address 2 DRAM address 1 DRAM address 0 DRAM address 10 DRAM bank address 1 DRAM bank address 0 DRAM chip select, active low DRAM row address strobe, active low DRAM column address strobe, active low DRAM Write enable, active low Data mask 1 GPIO DRAM data 8 DRAM data 9

127 126 125 124 123 122 121 120 119 117 116 115 114 113 112 111

RD10 RD11 RD12 RD13 RD14 RD15 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 IO_19 DQM0 (DQS0)

Inout Inout Inout Inout Inout Inout Inout Inout Inout Inout Inout Inout Inout Inout Inout Non-pull Inout

DRAM data 10 DRAM data 11 DRAM data 12 DRAM data 13 DRAM data 14 DRAM data 15 DRAM data 0 DRAM data 1 DRAM data 2 DRAM data 3 DRAM data 4 DRAM data 5 DRAM data 6 DRAM data 7 GPIO Data mask 0

48

JTAG Interface( 4 ) 1) 51 TDI V_ADIN4 Inout Non-pull 2) 3) 1) 52 TMS V_ADIN5 Inout Non-pull 2) 3) 1) 53 TCK V_ADIN6 Inout Non-pull 2) 3) 1) 54 TDO V_ADIN7 Inout Non-pull 2) 3) Serial interface port 3 data-out Version AD input port 4 GPIO Serial interface port 3 data-in Version AD input port 5 GPIO Serial interface port 3 clock pin Version AD input port 6 GPIO Serial interface port 3 chip-select Version AD input port 7 GPO

Note: 1. The Main column is the main function, Alt. Means alternative function. 2. The multi-function GPIO pins are set to green characters. 3. The video input port and external TV encoder mode can not both use CCIR-601 mode, at least one of them should be in CCIR-656 mode. 4. Following is a summary of modified pins. (a) Pin 48, 49, 50, 51 are no longer for JTAG functions. (b) V_ADIN0 and V_ADIN3 is not available.

49

4.BA5494

50

51

5.BA6208F
The BA6208F is monolithic ICs used for driving reversible motors. It allows control of reversible motors in cassette players and other electrical equipment by using TTL-level logic signals. The IC contains a logic section, which controls forward and reverse rotations as well as forced stop, and an output power section, which can supply an output current of up to 100mA (typical) according to the logic control.

52

6.K4S641632H-TC60

SDRAM 64Mb H-die(x16)

The K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4x 1,048,576 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Information
Part No. K4S641632H-TC(L)60 K4S641632H-TC(L)60 Organization 4Mb x 16 4Mb x 16 Max Freq 166MHz(CL=3) 166MHz(CL=3) Interface LVTTL LVTTL Package 54 pin TSOP(II) 54 pin TSOP(II)

Row Address
A0A11

Column Address
A0A9

53

Pin Configuration (top view)

54

7. MX29LV160BT
16M-BIT[2Mx8/1Mx16]CMOS SINGLE VOLTAGE 3V ONLY FLASHMEMORY

55

56

57

8.AT24C16
2-Wire Serial CMOS E2PROM 16k ( 2048 x 8 ) The AT24C16 provides 16384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C16 is available in space saving 8-pin PDIP, 8-pin and 14-pin SOIC packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V(4.5V to 5.5V), 2.7V(2.7V to 5.5V) and 1.8V(1.8V to 5.5V) versions.

58

59

60

9.NJM4558

DUAL OPERATIONAL AMPLIFIER

61

10.WM8714

24-bit, 96kHz Stereo DAC

The WM8714 is a high performance stereo DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8714 supports data input word lengths from 16 to 24-bits and sampling rates up to 96kHz. The WM8714 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo DAC in a 14-pin SOIC package. The WM8714 has a hardware control interface for selection of audio data interface format, mute and de-emphasis. The WM8714 supports I2S, and right Justified audio data interfaces. The WM8714 is an ideal device to interface to AC-3TM, DTS TM , and MPEG audio decoders for surround sound applications, or for use in DVD players. FEATURES APPLICATIONS Stereo DAC DVD Players Audio Performance Digital TV - 95dB SNR (A weighted @ 48kHz) DAC Digital Set Top Boxes - -90dB THD DAC Sampling Frequency: 8kHz 96kHz Pin Selectable Audio Data Interface Format - I2S, Right Justified or DSP 3-5V Supply Operation 14-pin SOIC Package Pin Compatible with WM8725 Pin Configuration
LRCIN DIN BCKIN NC CAP VOUTR GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 MCLK FORMAT DEEMPH NC MUTE VOUTL VDD

Pin Description
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 DIN BCKIN NC CAP VOUTR GND VDD VOUTL MUTE NC DEEMPH FORMAT MCLK

NAME
LRCIN

TYPE
Digital input Digital input Digital input No connect Analogue output Analogue output Supply Supply Analogue output Digital input No connect Digital input Digital input Digital input Sample rate clock input Serial audio data input Bit clock input No internal connection

DESCRIPTION

Analogue internal reference Right channel DAC output Negative supply Positive supply Left channel DAC output Soft mute control, Internal pull down High = Mute ON Low = Mute OFF No internal connection De-emphasis select, Internal pull up High = de-emphasis ON Low = 16-bit right justified System clock input Low = de-emphasis OFF High = 16-24-bit I2S Data input format select, Internal pull up

62

ICS ON HI-VOLTAGE BOARD

1.BIT3193

High Performance PWM Controller

BIT3193 integrated circuit provides the essential features for general purpose PWM controller in a small low cost 16-pin package. BIT3193 has built-in a low frequency PWM generator for any specified application. BIT3193 includes latched off protection feature may make the system more reliable while compare to other similar products. Features 4.5V 8V operation Fixed High Frequency, Voltage Mode PWM Control Latched Off Protection Build-In Low Frequency PWM Generator Build-in UVLO Low Power CMOS Process Totem Pole Output 16 Pin Package Applications DC/DC Converters LCD TV LCD Monitor Notebook Computer Tablet PC Personal Digital Assistants Navigation Phone/ Door Phone Portable consumer product Recommended Operating Condition: Supply Voltage Operating Ambient Temperature Operating Frequency Pin Layout:
1 INN CMP LOAD CTOSC TIMER ONOFF GND NOUT2 8 9 16 MODSEL ISEN CLAMP PWMDC CTPWM PWMOUT VDD NOUT1

4.58V 070 C 50K400K Hz

63

Pin Description Pin No. 1 2 3 Symbol INN CMP LOAD I/O I/O O I/O Descriptions The inverting input of the error amplifier. Output of the error amplifier. A switch that connected to the high frequency triangle wave generator. This switch is open while ISEN pin <1.3V. An external resistor connected here may change the operation frequency of CTOSC in open load situation. An external capacitor connected here can set the frequency of high frequency PWM controller. With internal reference current and an external capacitor connected here can set the required period of starting and the timing of initialization. The controller is forced to reset mode while TIMER<0.3V. During reset mode, a60uA current will flow into the INN pin to reduce the output level of the error amplifier CMP to turn off the controller. The latched off protection function will be enable after this node is charged to>2.5V. System is latched off if any abnormal operation is detected if pin TIMER>2.5V. The output current of this pin is 20uA when TIMER<0.3V. The output current becomes to 1uA when TIMER>0.3V. The control pin of turning on or off the IC.1V threshold with an internal 80K 15% ohm pull-low resistor. The ground pin of the device. The number 2 output driver for driving the NMOSFET switch. The number 1 output driver for driving the NMOSFET switch. The power supplies pin of the device. The output pin of low frequency PWM generator. A 2.5V or floating two state output is provided through this pin. The internal circuit limits the max. Duty-cycle to 92%. With the internal reference current and an external capacitor connected here can set the operation frequency of low frequency PWM generator with 1.0V2.5V triangle wave output. Low frequency PWM controlling input. A PWM output comes out by comparing this DC input and the 1.02.5V triangle wave that is generated by CTPWM. Over voltage clamping. If a>2.0V voltage is detected. A60uA current will flow into the INN pin to reduce the output of the error amplifier pin CMP to regulate the output voltage. Load current detection pin, the open load situation is detected if a less than 1.3V input is sensed. To set the output polarity of the low frequency PWM controller.

4 5

CTOSC TIMER

I/O I/O

6 7 8 9 10 11

ONOFF GND NOUT2 NOUT1 VDD PWMOUT

I I/O O O I O

12

CTPWM

I/O

13

PWMDC

14

CLAMP

15 16

ISEN MODSEL

I O

64

2.AP4511M

N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET

65

Part 3
MAIN BOARD
Interface Hudson Audio Power

Detailed Circuit

DVD BOARD
Index MT1389 Audio out Video out and AV connector SDRAM and FLASH

HI-VOLTAGE BOAD
HI-voltage Board

66

+5V 8125IR VCC5 0 1R52 0 1R50 0 1R34 R1 G1 B1 L0603 2EC23 220uF/16V 16 + 3C39 IR 100nF R G B GND OE 15 VCC5_STB 1L1 1U6 FSAV330 TSSOP16 8 +5V 3EC1 100uF/16V DVD-IR 2 2Q1 2N3904 2R4 100 3 2R5 4.7K 2R6 10K 1 8125IR 2 2Q2 2N3904 IR-SW
D

2R1 100 3

2R2 4.7K 2R3 10K 1 +5V LED_G

2L20 1DVD-PR

FB

1DVD-Y 1DVD-PB

14 11 5 2 13 10 6 3 1

4B1 3B1 2B1 1B1 4B2 3B2 2B2 1B2 S

VCC

4A 3A 2A 1A

12 9 7 4

2R7 0 NC IR 3C1 100nF 2R8 100R 5CON1 1 2 SP_LOUT 1CON2 1 2 3 4 5 1 2 3 4 5 OUT_L SP_LOUT OUT_R SP_ROUT 3EC2 100uF/16V 3C2 100nF GND VCC5 VCC5 3EC3 100uF/16V 1L3 +5V +5V +5V

VCC9 VCC9V 1R46 10k 3 L 1Q7 2N3904 R 2 5CON2 1 2 SP_ROUT 1L2

SW

10k

1R45 1

GND

3C3 100nF

4R1 470 4R2 10k 3 4R3 1k 1 2 4Q1 2N3906 4Q2 2N3904 2 1CON4 3

SW DVD-Y DVD-PB DVD-PR 1CON1 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 GND GND GND H_SYNC1 V_SYNC1 GND VGA_SCL VGA_SDA 1R38 1C25 20 1 1R39 20 1C26 1 1R40 20 1C27 1

SW DVD-Y DVD-PB DVD-PR 4052-R 4052-L 4052-R 4052-L

LED_R

1k 4R4

SVH-Y SVH-C

SVH-Y SVH-C AUDIO-SEL0 AUDIO-SEL1 DVD_CHECK VCC5 DISC_CHECK DVD_LOCK VCC9 GND DVD_LOCK 1 DVD_CHECK DISC_CHECK DVD_LOCK 4Q4 2N3904 2 LED_G 4R6 10k 4R7 1k 3

+5V 4R5 470 2 1 3 4Q3 2N3906

RIN1 2 100n GIN1 2 100n BIN1 2 100n 1CON3 1 2 3 4 1 2 3 4 VGA-L VGA-R

1 2 3 4 5
C

AUDIO-SEL0 TV_MENU RIN1 GIN1 BIN1 H_SYNC1 V_SYNC1 VGA_SDA VGA_SCL CVBS1 TV_MENU RIN1 GIN1 BIN1 H_SYNC1 V_SYNC1 VGA_SDA VGA_SCL CVBS1 AV_R AV_L YPbPr_R YPbPr_L OUT_R OUT_L AV_R AV_L YPbPr_R YPbPr_L OUT_R OUT_L AUDIO-SEL1

4R8 1k

VCC5

VCC VCC5_STB IR-SW

VCC VCC5_STB IR-SW LED_R LED_G IR IR-SW

5U1 1 3 4 5 6 2 PESD5V0L5 VCC5 RIN2 GIN2 BIN2 1 2 5C1 100n 1CN1A Y-AL Y-AR V-AL V-AR GND GND AUX 1R5 47k 1R6 47k 1R7 47k 1R8 47k 1 3 2 4 5 6 YPbPr_L YPbPr_R AV_L AV_R

VCC9 GND

DVD_LOCK LED_R LED_R LED_G

RIN2 GIN2 BIN2

LOUT ROUT

LOUT ROUT VCC16

LED_G

LED_R LED_G IR IR-SW

1CON5

DVD
1R1 1R2 1R3 1R4 2.7k 2.7k 2.7k 2.7k

1EC1 1EC3 1EC2 1EC4 2.2uF/16V

2R55 75

2R53 75 2R51

1 2 3 4 5 6 7 8 9 10

1 2 3 4 5 6 7 8 9 10

TV_MENU GND DVD_L GND DVD_R DVD-IR VCC GND GND

DVD

VCC16

VCC5 9
B

CON7-2.1 GND 1 1 1DVD-Y 2 2 GND 3 3 1DVD-PB 4 4 GND 5 5 1DVD-PR 6 6 GND 7 7 DVD_CHECK 8 8 DISC_CHECK 9 9 DVD_LOCK 10 10 GND 11 11 12 12 VCC9 1L5

1L4 1 1 1 Value = 20 2R50 2R52 2R54 Value = 20 2C62 2C63 2C64 470 47 2 1K 27K
B

+ + + +

2 2 2

DVD-Y DVD-PB DVD-PR 3EC44 100uF/16V

CVBS-OUT IR

CVBS-OUT IR 8125IR 8125IR

3EC4 220uF/16V

3C4 100nF 3R1 3R2 3R3 3R4

1CN2A

7 1R10 75 6 AUX2 1CN2B 5 1R9

1 1C1

CVBS1

VCC5 VCC16 1 5C2 100n 3C6 3C7 VCC16 3EC5 3C5 100uF/16V 100nF 3U1 HEF4052 SO16NB 3EC43 3 4052-L + 2R56 CVBSOUT 75 470uF/25V 2 1Q3 3906 3 3EC6 1Q1 3906

1 3 3EC7 22u/10V 1 3R5 1 300 3R6 470 3R7 220 3R8 6.8K 1Q2 2N3904 2 CVBS-OUT 3

3 5D1 BAV99 1 2

100pF 100pF 16

1 AUX2

1 Value = 20 1R11 1R13 75 1R14 1R12 1C2 1C3

SVH-C

VGA-L DVD_R VGA-R

0Y 1Y 2Y 3Y 0X 1X 2X 3X INH

3EC10 10uF 3EC11 10uF

VCC Y_OUT

SVH-Y

DVD_L

3EC8 10uF 3EC9 10uF

1 5 2 4 12 14 15 11 6 3R9 100K 3R10 3R11 3R12 100K 100K 100K 3R13 10K

X_OUT A B

13 10 9

5U2 PACDN045

1 3 4 5 6 2

3C8 100pF

3C9 100pF

1CN3A PR PB Y GND GND GND CVBS LOUT ROUT AUX 5U3 1 3 4 5 6 2 PESD5V0L5 5 3 1 8 9 7 2 4 6 R1 G1 B1

3R14 0 0 0 1R51 1R49 1R48 75 1R15 1R16 CVBSOUT LOUT ROUT VCC5 2 VCC5 1 R G B 5C3 100n AUDIO-SEL0 3R20 100R 75 1R17 75 R G B 10K

7 8

VEE GND

+ + +

10uF 4052-R 1C4 10uF 3EC42 22p

3R16 10K

1R18 1C5 2 1 1C6 2 1 1R19 1C7 2 1 1R20 100n RIN2 BIN2 GIN2

1 3Q2 2N3904 3R18 10K 2

3 5D2 BAV99 1 2 5C4 100n 1 2

Title meeeeekta Size C Date:

4 3 2

Document Number <Doc> Wednesday, March 15, 2006

1

Rev v1.0 Sheet 2 of 5

SW VCC5 1 2C1 100n 2U2 SCL SDA 2R17 100 DVD_LOCK DISC_CHECK MUTE TV_MENU DVD_CHECK AUDIO-SEL1 AUDIO-SEL0 1 2 3 4 A0 A1 A2 VSS VCC WP SCK SI 8 7 6 5 2R15 100 2 2R9 2.7k 2R10 2.7k DVD_CHECK DISC_CHECK DVD_LOCK DVD_CHECK DISC_CHECK DVD_LOCK D0 D1 D2 D3 D4 D5 D6 D7 SW ROM_OEN A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

SW VCC5

A11 A9 A8 A13 A14 29 28 27 26 25 24 23 22 21

ROM_OEN A10 ROM_CSN D7

+ 2EC1 47u 16V

A12 A17 2R13 A15 A16 A14 A13 A11 A10 A9 A8

2R11 2R12 2R14 2R16 2R18 2R19 2R20 2R21 2R22 2R23

24LC32SN

4.7k 10k 10k 10k 10k 10k 10k 10k

2EC2 47u 16V 1

VCC5

VCC3.3 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

2EC3 47u 16V

2C3 2C4 100n100n

+ 2 SVH-Y RIN1 2

GIN1 BIN1 100n

C

2EC5 100uF 16V

100n

2R25 56 SVH-C BIN2

2EC6 47u 16V

2C16 100n 2

2R24 22 VCC3.3_PANEL

2L2

+ 2C17 2C18 2 2 2L3 GIN2 2C202C21 100n100n 1 1 RIN2 2R26 56 2R27 20

2EC11 47u + 16V 2L4

1 1

2C19 100n 2 2C29 100n 2

DVD-PR 2C30 100n2C32 100n 1 1 DVD-Y DVD-PB 2R28 2C31 56 100n 1 2 2R33 2C33 20 100n 1 2

VDDA33_LBADC LBADC_IN1 LBADC_IN2 LBADC_IN3 LBADC_IN4 LBADC_IN5 LBADC_IN6 LBADC_RTN VSSA33_LBADC RESETn GND_RPLL VDD_RPLL_18 VBUFC_RPLL AGND_RPLL XTAL TCLK AVDD_RPLL_33 CVDD_18 RVSS STI_TM2 GPIO15/STI_TM1/EXT_CS SYNC2 VSYNC2 HOST_SCL/UART_DI/JTAG_CLK HOST_SDA/UART_DO/JTAG_MODE DDC_SCL DDC_SDA CVDD_18 RVSS I2CM_SCL I2CM_SDA RVDD_33 RVSS GPIO0/LED1/TCK GPIO1/LED2/TDI GPIO2/PWR_CTRL/TMS GPIO3/SCART16_1 GPIO6/IRin CVDD_18 RVSS GPIO7/IRQin GPIO8/IRQout GPIO9/SIPC_SCL GPIO10/SIPC_SDA/A18 CVDD_18 RVSS GPIO11/PWM0 GPIO12/PWM1 RVDD_33 RVSS GPIO13/PWM2/VBI_VALID GPIO14/PWM3/SCART16_2

2EC12 + 47u 16V 2L5 2EC16 + 47u 16V

CVBS0 CVBS1 2R34 20

2C422C43 100n100n

1 1

CVBS-OUT

56

2R35

2C41 2 100n 2 2C44 100n

VSYNC1 VDD18_AB NC GND18_C VDD18_C ADC_TEST AVDD_ADC AGND AGND SV1P GNDS A1P GNDS B1P GNDS C1P AVDD_A AN AGND SV2P GNDS A2P GNDS B2P GNDS C2P AVDD_B BN AGND SV3P GNDS A3P GNDS B3P GNDS C3P AVDD_C CN AGND SV4P GNDS A4P GNDS B4P GNDS C4P AVDD_SC SVN VO_GND VOUT VDD18_SC GND18_SC

HSYNC1 RVSS RVDD_33 VID_CLK_1/VID1_CLK VID_D15/VID1_15/GP23 VID_D14/VID1_14/GP22 VID_D13/VID1_13/GP21 VID_D12/VID1_12/GP20 VID_D11/VID1_11/GP19 VID_D10/JTAG_TDI/VID1_10/GP18 VID_D9/JTAG_TDO/VID1_D9/GP17 VID_D8/JTRST/VID1_D8/GP16 RVSS CVDD_18 VID_D7/VID1_D7 VID_D6/VID1_D6 VID_D5/VID1_D5 VID_D4/VID1_D4 VID_D3/VID1_D3 VID_D2/VID1_D2 VID_D1/VID1_D1 VID_D0/VID1_D0 RVSS CVDD_18 VID_DIN23/D7/PD46/VID2_7 VID_DIN22/D6/PD45/VID2_6 VID_DIN21/D5/PD44/VID2_5 VID_DIN20/D4/PD43/VID2_4 VID_DIN19/D3/PD42/VID2_3 RVSS CVDD_18 VID_DIN18/D2/PD41/VID2_2 VID_DIN17/D1/PD40/VID2_1 VID_DIN16/D0/PD39/VID2_0 GPIO4/VID_HS/VID2_HS/VID1_HS GPIO5/VID_VS/VID2_VS/VID1_VS RVSS CVDD_18 VID_CLK2/ROM_OEN/PD47/VID2_CLK RVSS RVDD_33 VID_DE/FLD/A0/GPIO16/PD24 VBI_CLK/A1/GPIO17/PD25 VBI_VALID/A2/GPIO18/PD26 VBI_D0/A3/GPIO19/PD27 VBI_D1/A4/GPIO20/PD28 VBI_D2/A5/GPIO21/PD29 VBI_D3/A6/GPIO22/PD30 VBI_D4/A7/GPIO23/PD31 VBI_D5/A8/PD32/BT0 VBI_D6/A9/PD33/BT1 VBI_D7/A10/PD34/BT2

2L1

V_SYNC1

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

2U3 FLI8125

XOSD_FLD/A11/PD35/ROM512K XOSD_VS/A12/PD36/JT_BSCAN XOSD_HS/A13/PD37/OP_MD0 XOSD_CLK/A14/PD38/OP_MD1 EXT_ADC_CLMP/A15/SPI_EN RVSS RVDD_33 ROM_SDI/ROM_WEN ROM_SDO/A16/OCM_ROM ROM_SCLK/A17/OSC_SEL ROM_SCSN/ROMCSN DCLK/VOP_CLK DVS/VOP_VS DHS/VOP_HS DEN/VOP_FLD PD23/B7 PD22/B6 PD21/B5 PD20/B4 RVSS CVDD_18 AVDD_OUT_LV_33 AVSS_OUT_LV CH0N_LV_O/B3 CH0P_LV_O_B2 CH1N_LV_O_B1 CH1P_LV_O_B0 CH2N_LV_O_G7 CH2P_LV_O_G6 CLKN_LV_O_G5 CLKP_LV_O_G4 CH3N_LV_O_G3 CH3P_LV_O_G2 AVDD_OUT_LV_33 AVSS_OUT_LV CH0N_LV_E/G1 CH0P_LV_E/G0 CH1N_LV_E/R7 CH1P_LV_E/R6 CH2N_LV_E/R5 CH2P_LV_E/R4 CLKN_LV_E/R3 CLKP_LV_E/R2 CH3N_LV_E/R1 CH3P_LV_E/R0 AVDD_OUT_LV_33 AVSS_LV VCO_LV AVDD_LV_33 BSCAN_TDO PPWR PBIAS

104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

A11 A12 A13 A14 A15 ROM_WEN A16 A17 ROM_CSN 8 7 6 5

A7 A6 A5 A4 A3

5 6 7 8 9 10 11 12 13

H_SYNC1

A7 A6 A5 A4 A3 A2 A1 A0 DQ0

2 2C2 100n

A17 30 ROM_WEN 31 32 A18 1 A16 2 A15 3 A12 4

A14 A13 A8 A9 A11 OE# A10 CE# DQ7

10k 10k 4.7k NC

A17 WE# VCC 2U1 A18 AT29F040B A16 A15 A12

DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1

20 19 18 17 16 15 14

D6 D5 D4 D3 D2 D1
D

D0 A0 A1 A2

GND

GND

VCC3.3_PANEL 2EC4 + 47u 16V 2C5 100n +1.8V_CORE 2C6 100n 2C7 100n 2C8 100n 2C9 100n 2C10 2C11 2C12 2C13 2C14 2C15 100n 100n 100n 100n 100n 100n 2

1 2 3 4

VCC3.3_PANEL NC 0NC NC 2R29 2R30 2R31 2R32 0 VCC5 2R36 10k 2R38 0 NC 1 2R39 4.7k 2Q3 2N3904

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

+1.8V_RPLL 2C222C23 +1.8V_ADC 100n100n

2C24 2C25 2C26 2C27 +3.3V_RPLL 2C28 100n 100n 100n 100n 100n 1 1 1 1 2EC10 + 47u 16V 1 1 2 +3.3V_LBADC 2EC15 + 100uF 16V 1 2C39 100n 2 2
B A

TOP

2EC7 100uF 16V

2EC8 47u 16V

1 2

2EC9 + 100UF 16V

VCC3.3 2C34 100n 2CON1 LVDS20 2EC13 220uF 16V + 1

2C40 100n

NC

2R37 NC 10k BACK_EN NC 2C45+3.3V_LVDS 2C46 2C47 2C48 2C49 100n 100n 100n 100n 100n 1 1 1 1 1 2EC17 + 100UF 16V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

+3.3V_I/O_HUDSON 2C50 2C51 2C52 2C53 2C54 2C55 100n 100n 100n 100n 100n 100n 1 1 1 1 1 2 GND 2EC18 + 47u 16V 1 2 Rev V1.0 Sheet
1

PANEL_ON SLEEP 1POWER_ON ADC_IN1 ADC_IN2 ADC_IN3 2R41 1 1 1 2C562C572C58 100n100n100n 2R40 0 2 2 2 2L7 2L8 VCC3.3 2L9
A

2 GND

VCC5 POWER_ON 4R31 LED_G 100 100 2R442R43 100 LED_R 2R42 3.3k 2R45 2.2k 1 2Q4 2N3904 3

VCC5

VCC5 CVBS-OUT CVBS-OUT RIN1 GIN1 BIN1 H_SYNC1 V_SYNC1 VGA_SDA VGA_SCL CVBS1

SVH-Y SVH-C IR ADC_IN1 ADC_IN2 ADC_IN3

SVH-Y SVH-C IR ADC_IN1 ADC_IN2 ADC_IN3 MUTE PANEL_ON 1POWER_ON SDA SCL LED_R LED_G BACK_PWM BACK_EN VCC5 VCC5 VCC5 VCC3.3 VCC3.3 VCC1.8 VCC3.3_PANEL VCC1.8 VCC3.3_PANEL

100

VCC1.8

2L6

+1.8V_ADC +1.8V_CORE +1.8V_RPLL

BACK_PWM 2R46 10k + 2EC19 10u 16V

VGA_SDA VGA_SCL VCC5 2Y1 4 3 2 1 VCC3.3 10k 1 2R47 + 47u 19.6608M 2CON2 2R48 100 2C59 100n 2R49 100 2 2EC21 16V 2C60 30p 2C61 30p 2EC20 47u 16V + IR-SW 8125IR A18

RIN1 GIN1 BIN1 H_SYNC1 V_SYNC1 VGA_SDA VGA_SCL CVBS1

+3.3V_LBADC +3.3V_RPLL

IR-SW SDA SCL DVD-Y DVD-PB DVD-PR

IR-SW DVD-Y DVD-PB DVD-PR AUDIO-SEL0 8125IR 8125IR AUDIO-SEL1

2

2L10 +3.3V_I/O_HUDSON 2L11 +3.3V_LVDS 2L12

RIN2 GIN2 BIN2 CVBS0 TV_MENU

RIN2 GIN2 BIN2 CVBS0 TV_MENU Title

MUTE PANEL_ON 1POWER_ON SDA SCL LED_R LED_G BACK_PWM BACK_EN

AUDIO-SEL0 1POWER_ON 1POWER_ON SLEEP SLEEP IR IR AUDIO-SEL1

<Title> Size A3 Date: Document Number LT-61501 Wednesday, March 15, 2006 3 of 5

VCC9

1L6 3C12 1 + 1EC5 220u 16V

TUNER1 TCL MNM05-4 NC1 NC2 VCC-T SCL SDA AS NC3 NC4 NC5 NC6 2nd SIF V-OUT VCC-IF A-OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 3R22 3R21 100 SCL SDA 3C10 3EC12 100n 100u 16V 1 + 3L1 68u 1 VCC5_TUNER

100n 2 + 3EC13 100u 16V 10u 16V GND + GND 3EC15 3R30 10k 3R32 47k 3R29 10k 1 2

3R23 0 3R24 20

3R27 10k 3 3Q3 3R31 2N3904300

3C13 100n 1 2

3C11 100n TV_SIF CVBS0 TV_R TV_L 3C14 3EC14 100n 100u 16V 1 + 3L2 68u

3EC16 ROUT 10u 16V +

TV_MONO 3R28 75 3R25 3R26 0

VCC5 VCC16 1 1 3EC24 + 100u 25V 2.2u TV_L 2.2u TV_R 2.2u 2.2u SCL 3R35 100 3R37 180k SDA 3R40 + 3EC30 + 3EC31 100 2.2u 4.7u TV_SIF 3C25 100p VCC5_A 3C31 1 3C29 220n 1 2 3C32 100n + 3EC36 0.33u 3R17 1M 3R19 1M VCC16 2 + 3EC39 3EC38 25V 100u + 1000u 25V 3C38 100n 1 2 100n 1EC6 220u 16V 2 25V + 100u 3EC2 3R54 10k 2 + 3R51 1k 1 3Q5 2N3904 POWER_ON 3 1L7 VCC5_TUNER YPbPr_L AV_L 3C30 1 100n AV_R 4052-L TV_R YPbPr_R 3C16 100n 3U3 LM7809 IN OUT G 3 1 VCC16 SCL SDA VCC9

VCC5 VCC16 VCC9

3U4 VCC9 + 3EC25 100u 16V 1 2 3C18 2.7n 3C20 2.7n 3 4 VDD AGND TREL TRER

PT2314 VREF SCL SDA DGND L_OUT R_OUT BOUTR BINR BOUTL BINL LOUT LIN LIN1 LIN2 28 27 26 25

3EC21 3R33 100 3R34 100 3EC27 +

22u 16V

3U2 1
C

AN5832A L-R REF NC4 L-OUT R-OUT AGC DET SCL PE GND SDA STER REF SIF REF INPUT NC3 VCC PLL PILOT DET 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 + 3EC20 3EC23 3EC26 + + 3EC17 +

3C17 100n

3EC18 10u +

NC1 WB TIME WB DET SPE TIME SPE DET SPE FIL IIC/PARA AGC SW MODE FOMO MUTE SIF/BB NOISE DET SAP DET L+R DET NC2

3EC19 0.33u 3 3EC22 0.33u 4 VCC5_A 3C15 100n 1 2 5 3C19 22n 3R36 3R38 3R39 3R42 3R44 3R46 0 0 0 6 7 8 9 + 0 10 0 11 0 12 3C27 100n 1 2 13 3C28 22n 14 + 3EC35 2.2u 15 16 +

5 3EC28 RIN 10u 6 ROUT 16V 3C21 1 2 7 LOUD_R 100n 8 RIN4 + 9 10 11 2 12 13 14 RIN3 RIN2 RIN1 LOUD_L LIN4 LIN3

24 23

3EC29 3C22 100n 2 3C23 3R41 100n 21 1 2 3C24 5.6k 100n 20 1 2 3C26 3R45 100n 19 1 2 5.6k 3EC32 18 10u 16V 17 22 1 + + 16 15

10u 16V 10u 16V

VOLUME_L VOLUME_R

3R43 10k 3R47 10k 10u 16V 3EC34 TV_L 4052-R 3R50 10k 3R49 47k 2 + 3 1 3Q4 3R48 2N3904300

3EC33 LOUT 10u 16V +

3C33 100n 1 2 3D1 3R56 Q1 1N4148 1k 2N3906 1 3 1 3D3 1N4148 MUTE 1

3R52 4.7k 3D2 1N4148 1

3R53 470

VCC16

3R55 4.7k 3 2 1 2 3Q6 2N3904

POWER_ON

POWER_ON

+ 3C34 470u 25V

LOUT ROUT

LOUT ROUT

3U5 VOLUME_L 3CON1 VCC GND SW ADJ 1 2 3 4 5 3L3 VCC16 3C35 470n 1 2 BACK_EN BACK_PWM 3 1 + 3L4 2 3C37 3EC37 100n 100u 25V OUT_R OUT_L 3EC40 1000u 25V 4 3EC41 + + 5 6 7 3C36 8 9 470n -INV1 SGND SVRR OUT1 PGND OUT2 VP M/SS -INV2

TDA1517P GND GND GND GND GND GND GND GND GND 18 17 16 15 14 13 12 11 10 1 25V + 100u 3EC2 1R42 47k 1R41 100 VCC MUTE 2 OUT_R OUT_L AV_R AV_L YPbPr_R YPbPr_L 3Q7 2N3906 470 1R43 21 1D4 1N4148 MUTE 2 Title LTD-61502 Size A3 Date: Document Number <Doc> Wednesday, March 15, 2006 Sheet
1

4052-R 4052-L

4052-R 4052-L

BACK_PWM BACK_EN MUTE SDA SCL CVBS0 VCC16 VCC5_TUNER GND

BACK_PWM BACK_EN MUTE SDA SCL CVBS0 VCC16 VCC5_TUNER

A

OUT_R OUT_L AV_R AV_L YPbPr_R YPbPr_L

VOLUME_R

1N4148 1

1000u 25V

1D3

GND

Rev 1.0 4 of 5

VCC5 1CON6 1 2 3 4 5 6 1 2 3 4 5 6 VCC16

1L8 VCC + 1EC7 220u 16V LOW LEVEL 1 ON 1C8 104 1EC8 100u 25V 1 + VCC16 1R22 100k 1R23 10k 4 3 2 1 1U1 VCC OCSET EN FB AP1513 OUT1 OUT2 VSS1 VSS2 5 6 7 8 2 1L9 33uH/2A VCC5 1D1 SS23 1R21 3.3k 1R24 3k 1R26 1.2k GND 1C11 10n +
D

VCC5

1C9 100n

GND GND GND

1EC9 1C10 220u GND100n 16V

1Q4 2N3904 VCC5 2

POWER_ON 1R25 10k

1C12 100n

100n 1C13

+ 2 VCC16 1EC10 100u 16V 4R9 4.7k 4R10 4.7k 4R11 4.7k 1R28 100k 1 1R29 10k 4 3 2 1 1L10 33uH/2A OUT1 OUT2 VSS1 VSS2 5 6 7 8 2 1D2 SS23 1R27 1.8k 1R30 2k 1R31 1.2k GND 1C17 10n + 1 VCC3.3 1L11 3 1 1EC13 100u 16V + 2 1U3 AIC1117-1.8 VIN OUT GND 1 2
C

1U2 VCC OCSET EN FB AP1513

VCC1.8 2 1 +

1EC11 + 100u 25V

GND 1EC14 220u GND 1C18 16V 100n 2 1C15 100n 1C16 1EC12 100n 100u 16V

1CON7 1 2 3 4 5 ADC_IN1 ADC_IN2 ADC_IN3 KEY_ADC_IN3 GND GND 2

1C14 1C19 100n 100n

2L13 2L15

2L14 2L16

VCC3.3 GND VCC16

B

VCC3.3_PANEL 1R32 10k 1 1 2 3 4 1U4 FDS9435 S1 D1 8 S2 D2 7 S3 D3 6 G D4 5

VCC5 1L13 1C23 100n 1 1R33 10k 1 2 3 4 1U5 FDS9435 S1 D1 8 S2 D2 7 S3 D3 6 G D4 5

VCC5_TUNER

GND 1L12 VCC16 1EC17 100u 16V +

+ 1EC15 100u 16V

1C20 100n 1EC18 100u 16V +

+ 1EC16 100u 16V 1 1R37 10k

1C21 100n
B

GND

VCC16 VCC5_STB 4R12 3.3k 4R16 3.3k 8 7 6 5 1

VCC5_STB 4R13 4R14 4R15 4.7k 4.7k 4.7k 4R17 100 VCC PB5 1 100 2 PB2 PB4 4R18 PB1 PB3 3 PB0 GND 4 GND 4R20 100 ATTINY12L 4U1 4R22 4R23 4R24 4.7k 4.7k 4.7k 4R26 0 4R25 4R27 4R29 100 100 100 IR

1C22 100n

1R34 100

GND 1 1R36 10k 1POWER_ON 1POWER_ON PANEL_ON POWER_ON LED_R LED_G IR ADC_IN1 ADC_IN2 ADC_IN3 PANEL_ON

1Q5 2N3904 2

1R35 100

GND

1Q6 2N3904 2

VCC5 VCC5 VCC3.3 VCC1.8 VCC3.3_PANEL VCC5_TUNER GND

POWER_ON 4R19 0 4R21 VCC5_STB 0

VCC LED_R LED_G VCC16 IR LED_R LED_G

VCC VCC16 IR LED_R LED_G

HZ5V1 2D1

GND 4EC1 100u 1C24 100n 25V 2

PANEL_ON POWER_ON LED_R LED_G IR ADC_IN1 ADC_IN2 ADC_IN3

VCC5 VCC3.3 VCC1.8 VCC3.3_PANEL VCC5_TUNER GND

A

0 KEY_POWER 4R28 KEY_ADC_IN3 0 SLEEP 4R30 IR

Title VCC5_STB SLEEP IR

3

VCC5_STB SLEEP Size A4 Date:

2

<Title> Document Number LT-61501 Wednesday, March 15, 2006 Sheet 5

1

1POWER_ON

2 Rev V1.0 of 5

SLOTIN1389HD_TOHEI_HD62_V1 MT1389HD(LQFP256) DVD MP Board for SANYO HD62 PUH (Small Size) MDxxx
Rev History The original released. (modified from 3-SY1389P3-V1) Supports 1389HD & Memory Card Interface P# Date 2005/10/08

1 2 3 4 5

INDEX & POWER, RESET MT1389HD SDRAM & FLASH VIDEO OUT & AV-CON AUDIO OUT - WM8766

V1

NAME VCC DV33 RFV33 AV33 V18 SD33 +12V -12V AVDD5 DVDD3

TYPE Digital 5V Digital 3.3V Servo 3.3V Laser Diode 3.3V Digital 1.8V Digital 3.3V Audio +12V Audio -12V Audio 5V Audio 3.3V

DEVICE SUPPLY MT1389HD MT1389HD MT1389HD SDRAM OP AMP. OP AMP. Audio DAC Audio DAC

URST# IR

URST# IR

[2,4] [2]

J9 VCC 1 2 3 4 5 6 7 8 9 10 CONN PCB 10 +P12V GND GND VCC IR1 DVD-R GND DVD-L GND VSTB VCC [2 4] IR C1 100pF [4] [4] DVD-L DVD-R DVD-L DVD-R

R1 IR1 10

[2]

VSTB

VSTB

V33 L1 V33 DV33 FB CB1 GND OUT 3 CB3 + CE3 104 CDV220uF/25V BA033 SOT223 U2 V18 V33 +P12V L3 +12V FB + CE8 CB7 CDV47uF/25V 0.1uF +12V + CE5 CDV10uF/25V DC100BC CB5 0.1uF 3 1 IN ADJ/GND AZ1117-Adj SOT-223 R3 680,1% R0603 OUT 2 + CE6 + CDV220uF/25V CE7 CB6 V18 D1 1N4148 R2 10k TP1 2 DV33
B

DV33

L2 VCC 50 CB57
B

V33 L0805 1 U1 IN V33 0.1uF

CB2 + CE1 + CDV220uF/25V CE2 0.1uF CDV47uF/25V

RESET Circuit

CB4 + CE4 104 104 CDV220uF/25V

CDV47uF/25V 0.1uF URST#

Ra

Rb

R4 300,1% R0603

CE9 CDV10uF/25V DC100BC

Vo=1.25x(1+Rb/Ra)
VCC L4 AVCC FB + CE10 CDV47uF/25V CB8 0.1uF FB + CE11 CDV47uF/25V CB9 0.1uF AVCC DV33 L5 RFV33 RFV33

AZ1117
Fix regulator Adj regulator

Rb 0 ohm

Ra

OFF

2,3

DV33

DV33

AVCC

AVCC

[2 4 5]

300 1% 680 1% 1.25x(1+Rb/Ra) Note for Fix or Adj Regulator

GND 1,2,4,5,6

MediaTek Confidential
Title

Ra = 680 FOR 1.8V Ra = 560 FOR 1.92V

MediaTek (ShenZhen) Inc.

SLOTIN1389HD_TOHEI_HD62
Document Number Drawn: Tom Wang

Size C Date:

INDEX
Saturday, October 29, 2005

Checked: Tom Wang Sheet 1 of

Rev 1 5

L6 RFV33 C3 R6 2200pF 680k OPO C4 0.1uF/NC R7 0 ADIN OPOP+ R9 150k R14 SPSP+ IO_18
D

RFV33 FB C5 0.1uF C6 0.01uF C7

RFVDD3

V1P4

JITFO 0.1uF TP2 0.47uF/NC

C2 R5

390pF 750k

JITFN TP3 CE13 CDV100uF/25v ADACVDD APLLVDD3 DACVDD3 L7 L8 + 3.3uH 3.3uH L9 CE12 CDV10uF/25v DC100bc

DV33

MS_SDIO

100k

FB

20pF

TP4 TP5 TP6 R13

2200pF R12 15k C16 0.1uF R8 1000pF

C8 0.1uF

C10 CDV10uF/25v C11 CDV10uF/25v XI XO CE14 CDV100uF/25V C17 4.7uF 0 0 ADACVDD + CB11 0.1uF + V18 +

CB10 0.1uF

C9

MS_SDIO

MS_SDIO

R10 150k R/NC 1 0 LIMIT 1 2 3 4 5 6 J1

R11 C14 2200pF 680k V1P4 6.8 CB13 0.1uF + CE15 CDV100uF/25V RFVDD3 PLLVDD3

C12

RFVDD3 0.047uF

0.033uF

R18 R19

0.1uF

0.047uF

TP9 TP12 C18 CDV10uF/25v TP17 APLLVDD3 ASPDIF MC_DATA ASDAT4

RFVDD3

PLLVDD3

JITFN JITFO XTALI R16 R17 RFV18

89_ALS

CB12 0.1uF TP7 TP8 TP11 TP10 TP13 TP14 TP15 TP16 TP18 DV33 ASDAT3 ACLK ABCK ALRCK SPBCK SPLRCK SPDATA SPMCLK ASDAT2 ASDAT1 MS_SDIO GPIO_4 GPIO_5 GPIO_6 ASDAT0 DACVDD3 VREF FS DACVDD3 C27 C/NC YUV0 TP19

C15

C13

R15 Y1 XI C23 33pF 27MHz

100k XO C24 33pF

0.1uF

C21

C25 0.1uF V2P8 CB14 + CB15 CE16 CDV47uF/25V 0.1uF V20 + CB16 CE17 CDV47uF/25V 0.1uF V1P4 + CE18 CDV47uF/25V

DV33

6x1 W/HOUSING 10k LIMIT 0.1uF V18

R20

256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193

C20 C26

SLSL+

C22

C19

AVDD3 IREF RFGC OSN OSP RFGND CRTPLP HRFZC RFRPAC RFRPDC RFVDD3 ADCVSS ADCVDD3 LPFOP LPFIN LPFIP LPFON PLLVDD3 IDACEXLP PLLVSS JITFN JITFO XTALI XTALO RFVDD18 RFGND18 ADACVDD2 ADACVDD1 ALF/(CTR) ALS/SDATA0 AL/SDATA2 AVCM AR/SDATA1 ARS/SDATA3 ARF(SW) ADACVSS1 ADACVSS2 APLLVSS APLLCAP APLLVDD3 SPDIF MC_DATA ASDATA4 DVDD18 ASDATA3 ACLK ABCK ALRCK DVDD3 SPBCK SPLRCK SPDATA SPMCLK ASDATA2/GPO_0 ASDATA1/GPO_1 GPIO_3 GPIO_4 RCLKB/GPIO_5 RVREF/GPIO_6 ASDATA0/GPO_2 DACVDDC VREF FS YUV0/CIN

DV33 V18

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

FF+ T+ TC/c D/d CD/DVD SW RF A/a B/b F GND-PD Vc(Vref) Vcc E NC VR-CD VR-DVD CD-LD MD HFM NC DVD-LD GND-LD

L10 V18 FB RFV18 CB17 0.1uF TP20 TP21 TP23 TP25 TP26 C B A D RFO C B A D TP28 TP29 TP31 TP33 TP35 TP36 TP38 TP40 TP42 AVCC R25 10k RFVDD3 TP44 TP46 CB18 2 0.1uF 1 3 R26 10k IOA Q1 2N3904 R27 100k AVCC FB L11 V1P4 C37 0.1uF + CE19 CDV100uF/25V CB19 TP68 AVCC1 MDI1 LD-CD TP69 E AVCC1 V20 GND F B A RFO IOA D C DV33 5600pF C36 C/NC R30 R/NC TRO FOO TP63 TP53 TP55 TP57 TP59 TP61 C35 0.1uF SUBA SUBB SUBC SUBD E F MDI1 MDI2 LDO2 LDO1 TP48 TP50 V2P8 V20 V1P4 FEO TEO TEZISLV OPO OPOP+ DMO FMO TROPEN RFOP RFON C28 C30 C33 1uF C29 1uF 1uF TP27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

1uF C31 1uF C32 120pF/NC

TDO TCK TMS TDI IO_19

R65 R67 R68 R66 R22

0 0 0 0 0

TRCLOSE STBY TRIN TROUT IOA

C
1

E3

2N3904
R24 100k

SANYO SF-HD62
D

2
3
C

1 Q2 2SK3018 2 2 R28 R29 0 0

1 Q3 2SK3018

2SK3018

HA1 GND LD-DVD

DV33

L14 CB22

DVDD3 IOWR# A16 HIGHA7 HIGHA6 HIGHA5 HIGHA4 HIGHA3 HIGHA2 HIGHA1 IOA20 IOCS# IOA1 IOCE# AD0 AD1 DVSS AD2 AD3 AD4 AD5 AD6 IOA21 ALE AD7 DVSS A17 IOA0 DVDD18 UWR# URD# DVDD3 UP1_2 UP1_3 UP1_4 UP1_5 UP1_6 UP1_7 UP3_0 UP3_1 UP3_4 UP3_5 ICE PRST# IR INT0# DQM0 IO_19 RD7 RD6 RD5 RD4 RD3 DVDD3 RD2 RD1 RD0 RD15 RD14 RD13 RD12 RD11 RD10 RD9

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Very Important to reduce Noise

2

L12 FB

CB20 0.1uF V18

C
L13 1 10uH CB21 0.1uF Q4 2 2SB1132 1 L15 + 3 LDO_DVD CE20 CDV47uF/25V RFV33

2SB1132

USBP USBM USBVDD ADIN TDI TMS TCK TDO V18 A2 A3 A4 A5 A6 A7 A8 A18 A19

AGND DVDA DVDB DVDC DVDD DVDRFIP DVDRFIN MA MB MC MD SA SB SC SD CDFON CDFOP TNI TPI MDI1 MDI2 LDO2 LDO1 SVDD3 CSO/RFOP RFLVL/RFON SGND V2REFO V20 VREFO FEO TEO TEZISLV OP_OUT OP_INN OP_INP DMO FMO TROPENPWM PWMOUT1/V_ADIN9 TRO FOO VPLLVSS CAPPAD VPLLVDD3 USB_VSS USBP USBM USB_VDD3 FG/V_ADIN8 TDI/V_ADIN4 TMS/V_ADIN5 TCK/V_ADIN6 TDO/V_ADIN7 DVDD18 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 HIGHA0 IOA18 IOA19

MT1389HD
Pin Assignment v1.5

DACVSSC YUV1/Y DACVDDB YUV2/C DACVSSB YUV3/CVBS DACVDDA YUV4/G DACVSSA YUV5/B YUV6/R VSYNC/V_ADIN1 YUV7 HSYNC/V_ADIN2 DVSS IO_17 C0/IO_0 C1/IO_1 DVDD18 C2/IO_2 C3/IO_3 C4/IO_4 DVDD3 C5/IO_5 C6/IO_6 C7/IO_7 YUVCLK/IO_8 Y0/IO_9 Y1/IO_10 Y2/IO_11 Y3/IO_12 Y4/IO_13 DVDD18 Y5/IO_14 Y6/IO_15 Y7/IO_16 DVDD3 RA4 RA5 RA6 RA7 RA8 RA9 RA11 DVSS CKE RCLK DVDD3 RA3 RA2 DVDD18 RA1 RA0 RA10 BA1 BA0 RCS# RAS# CAS# RWE# DQM1 DVDD3 IO_18 RD8

192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129

DACVDD3

FS VREF R21 C34

TP22 TP24

DACVDD3 YUV4 YUV5 YUV6 VSYNC# YUV7 HSYNC# IO_17 IO_0 IO_1 IO_2 IO_3 IO_4 IO_5 IO_6 IO_7 IO_8 IO_9 IO_10 IO_11 IO_12 IO_13 IO_14 IO_15 IO_16 MA4 MA5 MA6 MA7 MA8 MA9 MA11

0.1uF

560 URST# IR

TP30 TP32 TP34 ALRCK TP37 TP39 TP41 TP43 TP45 TP47 TP49 TP51 TP52 TP54 TP56 TP58 TP60 TP62 TP64 TP65 TP66 TP67 R23 [1]

URST# IR

[1,4] [1]

VSTB

POWER/ON/OFF

1k SPBCK SPLRCK SPDATA SPMCLK YUV7 IO_[0..19] ASDAT[0..3] SPBCK SPBCK SPLRCK SPDATA SPMCLK YUV7 IO_[0..19] ASDAT[0..3]

[3] [3] [3] [3] [3] [3]

C

DISCDET

89_ALS

89_ALS

[3]

HSYNC# DCKE DCLK MA3 MA2 MA1 MA0 MA10 BA1 BA0 CS# RAS# CAS# WE# DQM1 IO_18 DQ8 V18 DCKE CAS# RAS# WE# CS# VSYNC# YUV[4..6]

HSYNC# VSYNC# YUV[4..6]

[3] [3] [4]

VIDEO INTERFACE A[0..21] AD[0..7] PRD# PWR# PCE# MA[0..11] DQ[0..15] BA[0..1] DQM[0..1] DCLK A[0..21] AD[0..7] PRD# PWR# PCE# FLASH MA[0..11] [3,4] [3] [3] [3] [3] [3]

TOP

DQ[0..15] [3] BA[0..1] [3] DQM[0..1] DCLK DCKE CAS# RAS# WE# CS# MEMORY [3] [3] [3] [3] [3] [3] [3]

HEADER 24 SMD0.5 TOP 10uH

R31 R32 Q5 3

4.7 4.7 + 2SB1132 1

FB 0.1uF

65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

CB23 U3 MT1389HD 0.1uF

CB24 0.1uF

CB25 0.1uF

CB26 0.1uF

CB27 0.1uF

INT0#

CE21 CDV47uF/25V LDO_CD

VCC

L16 FB

MO_VCC

DV33 ALE V18 UP1_2 power VSTB play SCL SDA stop RXD TXD ICE URST# IR UWR# URD# AD7

DQM0 IO_19 DQ7 DQ6 DQ5 DQ4 DQ3

PWR# A16 A15 A14 A13 A12 A11 A10 A9 A20 PCE# A1 PRD# AD0 AD1

DQ2 DQ1 DQ0 DQ15 DQ14

AD2 AD3 AD4 AD5 AD6 A21

TP70 R33 1 R34 1 TTP82 TP84 MO_VCC SL+ SLT+ 15 16 17 18 19 20 21 30 R43 20k FMSO TRSO V1P4 STBY 22 23 24 25 26 27 28

TP71 R35 1 VOFC+ VOFCVOSL+ VOSLPGND PVCC1 VCC G1 VNFFC VOSL VINSLVINSL+ CF2 CF1 VINFC 14 13 12 11 10 9 8 29 7 6 5 4 3 2 1 R44 10k V1P4 R46 FOSO 20k C43 150pF MO_VCC C44 0.1uF U5 + CE22 CDV47uF/25V + CE23 CDV10uF/25V CB40 0.1uF 1 2 3 4 VCC BOUT GND AOUT BA6208F AIN GND NC BIN 8 7 6 5 R48 R50 R52 R45 20k DMSO LOADLOAD+ 2 1 CON2 CON2.0-2 J3 R36 1 FOSO TRSO FMSO DMSO C38 C39 C40 0.1uF R37 R38 R39 R40 C41 0.015uF V1P4 20k 18k 15k 10k FOO TRO FMO DMO TP73 TP79 TP72

A17 A0

FF+

DQ9 DQ10 DQ11 DQ12 DQ13

DV33

SCL SDA IIC

SCL SDA

[3] [3]

CB28 0.1uF

CB29 0.1uF

CB30 0.1uF

CB31 0.1uF ASDAT[0..2]

ASDAT[0..2] [3] ALRCK ACLK ABCK ASPDIF [5] [5] [5] [4]

U4 VOTK+ VOTKVOLD+ VOLDPGND VNFTK PVCC2 G2 PREGND VINLD CTK2 CTK1 VINTK BIAS STBY BA5954 R47 10k CB39 0.1uF

TP74 TP75 TP80

TP76 TP77

TP78 TP81 DV33

SPSP+

TP83 TP85 MO_VCC

ALRCK ACLK ABCK ASPDIF

330pF 330pF

CB32 VCC J2 R41 R42 33k 33k TROUT DISCDET 1 2 3 CON3 CON2.0-3 0.1uF

CB33 0.1uF

CB34 0.1uF

CB35 0.1uF

CB36 0.1uF

CB37 AUDIO INTERFACE 0.1uF USBP USBM USBVDD UP1_2 USBP USBM USBVDD UP1_2 [4] [4] [4] [4]

C42 150pF

CB38 0.1uF

VCC 10k 10k 10k TRCLOSE R51 TROPEN R53 R49 100 33k 100 TRIN 1 2 3 4

J4

DV33 RxD TxD 1 2 3 4

J5

[1]

AVCC

AVCC

4x1 W/HOUSING CON2.0-4

[1] 4x1 W/HOUSING RFV33

A

VCC

VCC

RFV33

RS-232
A

R54 NC/10K

R55 NC/10K GND Q6 NC/2N3906 SOT23 Q7 NC/2N3906 SOT23 + CE25 NC/100uF/25V R57 LDO_DVD LDO1 0 LDO_CD VCC 10k 10k 10k 1,2,4,5,6 J6 power play stop R69 R70 R71 1 2 3 4 4x1 W/HOUSING CON2.0-4

reserve this circuit for protection OPU

MediaTek Confidential
Title

CE24 NC/100uF/25V R56

MediaTek (ShenZhen) Inc.

SLOTIN1389HD_TOHEI_HD62
Drawn: Tom Wang

LDO2 0

Size Document Number CustomMT1389HD TQFP Date:

256

Saturday, October 29, 2005

Checked: Tom Wang Sheet 2 of

Rev 1 5

[2] [2] [2]

ACLK ABCK ALRCK

ACLK ABCK ALRCK [1] AVCC AVCC [1] DVD-L [1] DVD-R DVD-L DVD-R

[2]

89_ALS

89_ALS

AVCC
D

L26 AVDD FB + CE29 CB60 CDV47uF/25V 0.1uF CB58 0.1uF CB59 0.1uF
D

ABCK ALRCK ACLK

R94 R95 R96

33 33 33 0

SBCLK1 SLRCK1 SACLK1 DAC_ASDAT0

89_ALS R97

+12V CE30 DAC_ML C61 9k R101 180K CDV10uF/25V R102 100K C62 2 2000p 3 U10 SLRCK1 DAC_ASDAT0 SBCLK1 DAC_MR CE33 + CDV10uF/25V WM8714 CB65 0.1u
C

R98

R99 12k

R100 OPEN CB61 0.1uF 4 U9A 1 NJM4558

SOP8

CB62 0.1uF

CB63 0.1uF

GND

1 2 3 4 5 6 7

LRCIN MCLK DIN FMT BCKIN DEMPH NC NC CAP MUTE VOUTR VOUTL GND VDD

14 13 12 11 10 9 8

SACLK1

4.7K R106

VER R107 10K + CE32 R108 CDV100uF/25V 8K2

DAC_ML

10 NC R109 R110 R111 12k R112 OPEN C64 CE34 DAC_MR + R116 R117 180K CDV10uF/25V 100K 9k C65 1000p VER R113 R114 5.1k 4 220p 6 5 U9B 7 NJM4558
SOP8

I2S FORMAT HARDWARE MODE

GND

1,2,4,5,6

+ R103 5.1k

220p CE31 R104 CDV10uF/25V 100 L27 10uH DVD-L C63 R105 22p 100K

+12V CB64 0.1uF

WM8766 R86 R94 R98 R109 R120 R127 C67 C72 C78 C82 C86 C90
DVD-R C66 R118 22p 100K

Int. DAC 31k 31k 31k 31k 31k 31k 1000pF 1000pF 1000pF 1000pF 1000pF 1000pF 100pF 100pF 100pF 100pF 100pF 100pF
C

22k 22k 22k 22k 22k 22k 1800pF 1800pF 1800pF 1800pF 1800pF 1800pF 180pF 180pF 180pF 180pF 180pF 180pF

CE35 R115 CDV10uF/25V 100

L28 10uH

+12V

C64 C69 C73 C79 C83 C87

MediaTek Confidential
Title

MediaTek (ShenZhen) Inc.

SLOTIN1389HD_TOHEI_HD62
Document Number Drawn: Tom Wang

Size C Date:

AUDIO OUT
Saturday, October 29, 2005

Checked: Tom Wang Sheet 5 of

Rev 1 5

[2] [2]

UP1_2 A21

UP1_2 A21 +5VV +5VV L18

AVCC

[1]

AVCC

AVCC

[2] [2]

YUV[4..6] ASPDIF

YUV[4..6] ASPDIF C49 0.1uF C50 1uF C51

FB ASPDIF CDV10uF/25V
D

CON3 +5VV [2] [2] USBM USBP USBM USBP +5VV 2 R81 75,1%/NC R82 [4] [4] [4] Y U V Y YUV4 U V R83 75,1% C53 47P C54 120P C52 47P 1 L19 0.56uH L20 0.56uH Q8 3906/NC 0 Y D3 1N4148 2 1 D2 1N4148 [4] OPTICAL OPTICAL R80 33 OPTICAL 1 2

OPTICAL
2x1 W/HOUSING CON2.0-2

3906 C B E
R84

+5VV

+5VV
C

75,1%/NC 0

2 D4 1N4148 U D5 1N4148 Q9 3906/NC 1 2 1

R85 L21 0.56uH YUV5 R86 75,1% C55 47P C56 120P L22 0.56uH

C57 47P J10 7 6 5 4 3 2 1 CON7 1N4148 R90 0 V 2 1 USBP USBM GND VCC 1 2 3 4 4x1 W/HOUSING con0402w [1] VCC VCC GND V GND U GND Y GND

+5VV +5VV R89 75,1%/NC

B

2 D6

J8
B

L23 0.56uH YUV6 R93 75,1% C59 47P C60 120P L24 0.56uH C58 47P Q10 3906/NC

D7 1N4148 1

MediaTek Confidential
GND 1,2,4,5,6

MediaTek (ShenZhen) Inc. Title

Size Document Number Custom VIDEO OUT Date: Drawn:

SLOTIN1389HD_TOHEI_HD62
Tom Wang

& AV-CON
1

Saturday, October 29, 2005

Checked: Tom Wang Sheet of 4

Rev 1 5

[2] [2] [2] [2] [2] [2] [2] [2] [2]

D

MA[0..11] BA[0..1] DQM[0..1] DCLK DCKE CAS# RAS# WE# CS# DRAM

MA[0..11] BA[0..1] DQM[0..1] DCLK DCKE CAS# RAS# WE# CS#

U6 U7 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 DBA0 DBA1 SDCLK SDCKE 23 24 25 26 29 30 31 32 33 34 22 35 20 21 38 37 19 18 17 16 15 39 36 40 54 41 28 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 BA0/A13 BA1/A12 CLK CKE CS RAS CAS WE DQML DQMH NC NC VSS VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VCC VCC VCC VCCQ VCCQ VCCQ VCCQ VSSQ VSSQ VSSQ VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 6 12 46 52 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DV33 SD33 R59 SD33 DV33 10k PCE# PRD# PWR# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AA20 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10 26 28 11 12 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 CE OE WE RESET MX29LV160 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 WP/ACC BYTE VCC GND1 GND2 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 14 R58 47 37 27 46 CB41 0.1uF AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
D

[2] [2] [2] [2,4]

PCE# PRD# PWR# A[0..21]

PCE# PRD# PWR# A[0..21]

DV33 A0 0

FLASH RN2 DCS# DRAS# DCAS# DWE# DBA0 DBA1

C

7 5 3 1 33x4 R60 R61 R62 R63 R64

8 6 4 2 33 33 33 33

CS# RAS# CAS# WE# BA0 BA1 DCKE DCLK AA20

DCS# DRAS# DCAS# DWE# DQM0 DQM1

TSOP 48 pin
C

SDCKE SDCLK A20

16Mb

ESMT M12L64164A-7T TSOP54

DV33 L17

SD33 FB SD33

DQ[0..15] DRAM

DQ[0..15] + AD[0..7] FLASH J7 13 12 11 10 9 8 7 6 5 4 3 2 1 CONN RCPT 13 SPDATA VSYNC# YUV7 ASDAT0 MS_CD ASDAT3 IO_17 ASDAT2 HSYNC# MS_SDIO ASDAT1 GND DV33 CE26 CB42 CB43 0.1uF CB44 0.1uF CB45 0.1uF CB46 0.1uF CB47 0.1uF CB48 0.1uF CB49 0.1uF

CDV100uF/25V 0.1uF 2 AD[0..7]

1,2 1 2 2
B

DV33 SD33 SCL SDA

DV33 SD33 SCL SDA IIC

CB50 + CE27 0.1uF CDV100uF/25V

CB51 0.1uF

CB52 0.1uF

CB53 0.1uF

CB54 0.1uF

CB55 0.1uF
B

Memory Card I/F

DV33 DV33 DV33 U8 CB56 0.1uF 1 2 3 4 NC NC NC GND VCC WP SCL SDA 8 7 6 5 DV33 GND SCL SDA R74 1k R72 1k SCL SDA

2 2 2 2 2 2 2 2
A

MS_SDIO IO_17 SPDATA SPMCLK YUV7 HSYNC# VSYNC# ASDAT[0..3]

MS_SDIO IO_17 SPDATA SPMCLK YUV7 HSYNC# VSYNC# ASDAT[0..3]

EEPROM 24C16 24C02

MediaTek Confidential
A

Memory Card I/F

MediaTek (ShenZhen) Inc. Title

GND 1,2,4,5,6 Size B Date: Document Number Drawn:

SPDATA SPMCLK R78 R79

SD_CD 0 MS_CD 0

SLOTIN1389HD_TOHEI_HD62
Tom Wang Checked: Tom Wang 3 of Sheet Rev 1 5

SDRAM&FLASH
Saturday, October 29, 2005

J1 1 2 3 4 5 PH05-2A

F1 3A R1 1206-102 R2 471 Q3 2 C1 220uF/25V R3 202 4 Q4 IC_VCC D1 7.5B 1 C6 105 2N3904 2N3906 105 Q5 2N7002 1 C23 1 AP4511 R6 560 8 1 3 2 6 3 7 C3 106 C4 472 C5 102 BAV99 223 CR2 2 1 BAV99 R4 681 R5 Q1 2N3904

NIA19LES018
1 8

J2 1 2 8.0-2A 3 CR1 2 OP1

D

Q2 5 5 T1 7

C2 10pF/3KV

C24 105

16

15

14

13

12

11

10

CLAMP

CTPWM

PWMOUT

MODSEL

PWMDC

C7 223

C8 100 R7 683

NOUT1

ISEN

VDD

U1 Q6 R8 103 4 3 2 5 6 7 8 AP4511 R9 104 R13 OP1 1SS355 C17 222

B C

BIT3193
ON/OFF CTOSC NOUT2 TIMER LOAD GND CMP INN

T2

J3 8 1 2 8.0-2A 3 CR3 2 3 CR4 2 1 BAV99 R10 681 R11 BAV99 223 R14 560 1 OP2

C9 10pF/3KV 5 7

IC_VCC C11 222

105 C22 1 C10 106 C12 472 D2 C13 102

R12 NC R15 683

B

C14 821

C15 105

C16 104 153

D3

D4 1SS355 C18 222

R16 OP2 153

1SS355 C19 474 R17 474

R18 203

Beyond Innovation Technology Co., LTD.

A

C20 NC

R19 103

5F,No.136, Sec.3, Nanjing E. Road,Taipei,Taiwan,R.O.C.

Tel886-2-2778-5939 Fax886-2-2778-1050
The circuits shown are intended to explain typical application of the products concerned. BiTEK is not responsible for any infringement of third party or any other intellectual property rights that may arise from the use of these circuits.

Title

BIT3193 2 LAMPS 2 TX H.B VER0.1FOR E-MAX Document Number INV537001020 Friday, March 17, 2006
1

Size Custom Date:

5 4 3 2

Task Code <Number> Sheet 1 of 1

Rev 0.3

Part 4 Disassemble/Assemble Procedure

1. Fig1: Whole assembly diagram in which: LCD screen (1), bottom base (2), remote sensor (3), power indicator (4)

2.

Fig2: Back view of the LCD TV without bottom base. Remove six screws for bottom base fixing from (A) positions, screws for rear panel fixing from (B) positions and screws for handle fixing from (C) positions.

3.

Fig3: Whole assembly diagram in which: Rear Panel (1), handle (2).

67

4.

Fig4: Assembly diagram without the rear panel in which: shield A (1), speaker (2). Remove the screws from (A) positions.

5.

Fig5: Assembly diagram without shield A in which: Main board (1), Power board (2), DVD board (3), Keypad board (4), USB and Headphone board (5), shield B (6).

68

6.

Fig6: remove the USB and Headphone board to see the Card board (1). Remove the screws for USB and Headphone board fixing from the (A) positions.

7.

Fig7: Remove DVD board to see the HI-voltage Board (1). Remove the screws for DVD board fixing from (B) positions. Remove the Card board and the screws for its fixing from (A) positions.

8.

Fig8: Whole Assembly diagram in which: DVD board (1), DVD Loader (2). Remove the screws for DVD board and loader fixing from (A) positions.

69

9.

Fig9: Remove the front panel and the screws for its fixing from (A) positions.

10. Fig10: Remove the HI-voltage Board and the screws for its fixing from(A) positions and remove the base.

70

11. Fig11: The LCD Screen, HI-voltage Board and LVDS (1). Remove the screws for screen fixing to shield from (A) positions. Remove the screws for screen fixing to front panel from (B) positions.

12. Fig13: The connections between DVD board and Card board, USB and Headphone board, Key pad board.

71

Part 5 Part list of TEACLCDV1501M

No. Serial number of material Specification QNTY Position

Plastic molding pieces 1 2 3 4 5 6 7 8 9 10 11 01.00.SJ.LTD61501.E001 LTD61501-front panel 01.00.SJ.LTD61501.E002 LTD61501-middle panel (black) 1 1 1 1 1 1 1 1 1 1 1 LTD-61501-RE001 LTD-61501-RE002 LTD-61501-RE003 LTD-61501-RE004 LTD-61501-RE005 LTD-61501-RE006 LTD-61501-RE007 LTD61901ZPTG-RE04 LTD61901ZPTG-RE06 LTD61901ZPTG-RE07 LTD61901ZPTG-RE08

01.00.SJ.LTD61501.E003 LTD61501-rear panel 01.00.SJ.LTD61501.E004 LTD61501-side panel 01.00.SJ.LTD61501.E005 LTD61501-bottom base 01.00.SJ.LTD61501.E006 01.00.SJ.LTD61501.E007 01.00.SJ.61901.E004 01.00.SJ.61901.E006 01.00.SJ.61901.E007 01.00.SJ.61901.E008 LTD61501-cover of rotating axes LTD61501-cover for lines output LTD61901-handle LTD61901-function keystoke LTD61901-indicator transparency LTD61901-remote control signal receiver transparency

Metals parts 12 13 14 15 16 17 18 19 20 01.00.WJ.TJ.E753 01.00.WJ.TJ.E754 01.00.WJ.TJ.E755 01.00.WJ.TJ.E756 01.00.WJ.TJ.E757 01.00.WJ.TJ.E758 01.00.WJ.TJ.E759 01.00.WJ.TJ.E760 01.00.WJ.TJ.E318 LTD61501-LCD shield LTD61501-DVD loader fixing frame LTD61501-right shield panel LTD61501-lower shield panel LTD61501-shield cover LTD61501-bottom panel LTD1510-LCD fixing frame LTD61901-bracket of bottom base 6600-grounding patch Radiator 21 22 23 01.00.WJ.TJ.E268 01.00.WJ.TJ.E761 01.00.WJ.TJ.E762 28*28*10mm 41*54*30*25MM 25*54*25*41MM 1 1 1 used for Power board used for Power board 1 1 1 1 1 1 2 1 1 LTD-61501-PT01 LTD-61501-PT02 LTD-61501-PT03 LTD-61501-PT04 LTD-61501-PT05 LTD-61501-PT06 LTD1510-PT16 LTD61901PT-011 G1(used for Power board)

72

 24 01.32.ZZ.E125 LTD-61501 1 Magnetism ring 25 01.13.L.H.E002 22*14*6.5 Screw front panel and middle panel (8), LCD shield and front panel (10), Card board and middle panel (3), 26 01.00.WJ.JG.E321 3*8PAHO 32 Keystoke board and side panel (5), USB board and middle panel (2),Remote control board and front panel(2), LCD shield and middle panel (2). LCD fixing frame and LCD shield (4), loader frame 27 01.00.WJ.JG.E717 3*4PWBTTNI 29 and DVD board (4), lower panel of shield and LCD shield (4), right panel and LCD shield (3), shield cover(14) 28 29 01.00.WJ.JG.E517 01.00.WJ.JG.E390 4*12 PMHO 3*6PAHO 4 12 rotating axes and bracket of bottom base speaker and middle panel(8),right panel of shield and jack of Main board (4) Main board and LCD shield (5),Power board and LCD shield (4), TFT driver board and LCD shield 30 01.00.WJ.JG.E311 3*5PWMNI W=7.4 27 (3), LCD Screen and LCD fixing frame (4), loader and loader frame (4), loader frame and LCD shield (4), VGA board and LCD shield (3) 31 32 33 34 35 36 37 01.00.WJ.JG.E388 01.00.WJ.JG.E519 01.00.WJ.JG.E520 01.00.WJ.JG.E675 01.00.WJ.JG.E718 01.00.WJ.JG.E719 01.00.WJ.JG.E721 4*12PAHO 4*6 KMHO 3*6 KBHO 3*10PAHO 4*8 PMHO 4*10 PMHO 3*5 CBANI 38 01.00.BP.DZ.E000 According to customers choice 1 12 4 6 2 6 4 3 front panel and rear panel bracket of bottom base and bottom panel bottom panel and bottom base side panel and front panel rotating axes and LCD shield handle and shield cover matchingU1,D3,D4(used for Power board) 1 Tuner commutator

39 01.00.DP.JY.E135 LTD-1510 1 Module of DVD loader 40 01.15.JX.ETDS208SVB TD-S208S-SV-B(long line) 1

LCD Screen
73

41

01.17.LCD.E15SGD

15 Shanghai

SVA-NEC

liquid crystal display screen Speaker

42

01.00.SP.E089

LD7040A-027-1(8 3W)

Remote Controller 43 01.00.RC.RC6043 RC-6043 1

() 44 02.02.MCA-60 MCA-60 1 According to customers choice

Alkalescence battery 45 01.14.DX.B.E0007 7# 1 Commutator 46 01.40.CON.DDZ.E001 N 775-41207-00 47 01.47.CNT.LJX.5.E015 1 1

48 01.00.FZ.QT.E122 12CM 2

AC Power line 49 01.47.CNT.ACX.E077 355+LASR-85 1 Power board to external power supply

50 01.47.CNT.CTX.E106 RCA F (L190mm) 1

LVDS connections bus 51 01.47.CNT.LJX.2.E138 1.25-20P-1.25-20P-150mm 1

Connections bus 52 53 54 55 01.47.CNT.LJX.7.E325 01.47.CNT.LJX.7.E326 01.47.CNT.LJX.7.E327 01.47.CNT.LJX.7.E328 2.0-4Y-4Y-140MM Contrary 2.0-11Y-11Y-230MM Contrary (shield) 2.0-5Y-5Y-460MM (shield) 2.0-4Y-4Y-190MM Same Contrary 1 1 1 1 VGA board to Main board VGA board to Main board Keystoke board to Main board Keystoke board to DVD board

74

56 57 58 59 60 61 62 63

01.47.CNT.LJX.7.E329 01.47.CNT.LJX.7.E330 01.47.CNT.LJX.7.E331 01.47.CNT.LJX.7.E188 01.47.CNT.LJX.7.E332 01.47.CNT.LJX.7.E333 01.47.CNT.LJX.7.E334 01.47.CNT.LJX.7.E335

2.0-5Y-5Y-210mm Contrary 2.0-4Y-4Y-150MM Contrary 2.0-13Y-13Y-140MM Contrary 2.0-5Y-5Y-260MM Same 2.0-10Y-10Y-140MM Contrary 2.0-11Y-11Y-140mm Contrary (shield) 2.54-6Y-6Y-180MM Same 2.54-6Y-6Y-140MM Same Flat bus

1 1 1 1 1 1 1 1

Headphone board to Main board Headphone board to DVD board Card board to DVD board TFT driver board to Main board DVD board to Main board DVD board to Main board Power board to Main board Inner of Main board

64

01.48.BPX.2.E025

0.5*24P*220mmB

Loader to DVD board

No. Serial number of material Name and type

Specification Assemblies

QNTY

Position

65 01.00.DP.XJ.E172 66 01.00.DP.JY.E124 67 01.00.DP.QT.E001 68 01.00.DP.JY.E183

Silica gel pad Insulation pad

LTD-2030

10*15*7.8MMblack TO-220 sil-pad 400-2820 145*44*0.5mm(single side glue) black Circuit boards

6 1 1 1 matching U1(used for Power board) matching U1(used for Power board) Insulation pad for TFT driver board

69 02.11.LTD06M3227C01 70 02.15.LTD06K3228C01 71 02.22.LTD06T3229C01 72 02.14.LTD06I3230C01 73 02.14.LTD06I3307C01 74 02.14.LTD06I3308C01 75 02.23.LTD06V2805C01 76 02.19.LTD06P2956C01

Main board Keystoke board TV board VGA board Card board USB and Headphone board DVD board Power board

LTD06M-3227C01 LTD06K-3228C01 LTD06T-3229C01 LTD06I-3230C01 LTD06I-3307C01 LTD06I-3308C01 LTD06V-2805C01 LTD06P-2956C01

1 1 1 1 1 1 1 1 1

77 02.07.MINV1507SVA1B01 HI-voltage Board MINV15-07SVA1B01 Accessories 78 01.00.BP.DC.E000 According to customers

75

choice 79 01.00.YS.SM1.E000 80 01.00.YS.ZX2.E000 81 01.00.YS.TZ.M.E000 82 01.00.YS.FY3.E049 83 01.00.YS.SC.E002 84 01.00.BZ.X.W.E000 85 01.00.BZ.X.B.E000 86 01.00.DP.QT.E016 87 01.00.BZ.D.H.E004 88 01.00.BZ.D.H.E029 Users manual Packing list Bar code Certificate Warranty card Package box White box EPE cushion Warranty card According to customers choice According to customers choice LTD-61501 15*33cm 6*23cm According to customers choice According to customers choice According to customers choice 1 1 1 1 1 1 1 1 1 2 Packing bag for VGA line Packing bag for VGA line, Packing bag for S-Video line Packing bag for power adapter 89 01.00.BZ.D.H.E002 11*28cm 2 line, Packing bag for power line 90 01.00.BZ.D.H.E163 91 01.00.BZ.D.H.E198 92 01.00.BZ.D.Z.E035 9*33CM 58*75CM 7.5*8CM 1 1 1 Packing controller Packing bag for the machine Packing bag for 7# battery bag for remote

76

Part 6 Debugging Procedures

1. Workflow Of The System

POWER SUPPLY

Panel 15 TFT LCD

RGB LR

AT49F040B
FLASH

PC FLI8125
Decoder & Scaler
YPbPr CVBS Hsync VSync

IN

24LC01B/02B
EEPROM

AV IN
L R

YC

SVIDEO IN

L R

CVBS

TUNER

AN5832SA
SIF

SIF demodulation

L R

PT2314

DVD
MXX29LV160BT
FLASH

L R

audio processor

TDA1517
audio power amplify

K4S641632H
SDRAM

MT1389HD
Decoder

AT24C16
EEPROM

BA5494
Motor Driver

BA6208F
reversible motor driver

LOARDER

77

2. Signal process diagram

78

79

80

81

3.

Debugging Strategy

Debug start No Led green? No Led red? Yes Power on Make sure the power adapter is correctly connected.

Yes LOGO appears? Yes Yes FLASH No Accessed? No Check the connection between FLASH and FLI8125 Check the speed of FLASH

EEPROM works normally?

No Check the connection between EEPROM and FLI8125

Video

signal

from No

Check Pins of FLI8125 If in TV mode, check the tuner

8125 is OK?

Blue screen? No

Yes

Make sure the unit is turned on and the connections are correct.

Audio signal OK? Yes No

Check PT2314 and TDA1517 Make sure the speakers work correctly and the amplifier is not muted. In TV mode, make sure setting the correct sound mode. In DVD mode, make sure the sound setup of DVD disc is correct.

82

In DVD mode

Is tray works Ok?

No

Check the Pin STB(147)of FLI8125 is low

Can

sled

return

to

No

Is signal of SL+ OK? SL-

Check No motor driver BA6208F

position automatically?

Yes Check the circuit connected with the loader

Focus operation OK?

No

Drive signal of F+/F- OK?

No Check periphery circuit of BA5954

Yes Check circuit between laser head and BA5954

IR and Keys are all OK?

No

Check communications between IR, Key mode and FLI8125

Check periphery circuit of IR, Keypad, driver IC

Check wiring circuit of IR, Keypad

83

End debugging

4. Tips Of Some Typical Troubleshooting

White screen
First check voltage in HI-voltage Board; otherwise check the voltage of MAIN board , if abnormal , the problem occurs in 1U2. If the voltage is OK, check the LVDS. At last the connection between the main board and drive board may be the target for troubleshooting.

Black screen
This problem often arise from the voltage input to the screen, so the first step is to check the voltage of invert circuit. Otherwise check if the status is standby. If in TV mode, check the power for tuner is correct.

No color
Check if the connection with the external device is correct. Otherwise make sure the saturation is not zero. At last the problem may arise from the FLI8125.

Abnormal picture
Check if the range of the signal input to FLI8125 is correct. If no, the problem may be in the AFE(Analog Front End). Otherwise make sure the color system is correct. Then check the LVDS and the LCD Screen.

Pictures with no sound

Firstly, make sure the speakers works well. If so, the trouble mostly occurred in TDA1517 in 3U5 in main board, then PT2314 in 3U4.

Sounds with no picture

Check if any signal inputs to FLI8125, if yes, the problem may be in the AFE. Otherwise check the LVDS.

84