Académique Documents
Professionnel Documents
Culture Documents
Count (C) will be retained by a D Register Next value of counter (N) computed by combinational logic
C3 0 0 0 0 1 1 1 1 C2 0 0 1 1 0 0 1 1 C1 N3 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 0 N2 0 1 1 0 0 1 1 0 N1 1 0 1 0 1 0 1 0
N1
1 1 0 1 0
C3
1 0
N 2
C3
0 1 0 1 0 0 1
C1 0
C1 1 C3
C2
N3
0 0 1 1 0
C2
1 1
C1 0
C2
C1 C2 D Q D Q C3
D Q
C1
C2
C3
D CLK
Next-state logic
Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized states of operation At each clock edge, combinational logic computes outputs and next state as a function of inputs and present state
Combinational Logic
n Q D
CLK
L6: MIC502 2013
FlipFlops
Timing requirements for FSM are identical to any generic sequential system with feedback
Minimum Clock Period Minimum Delay
inputs + present state
Combinational Logic
Combinational Logic
Tlogic
Tcq
Q FlipFlops D
Tlogic,cd
Tcq,cd
Q FlipFlops D
CLK
Tsu
CLK
Thold
Flip- Q Flops
n
Comb. Logic
outputs yk = fk(S)
present state S
Mealy FSM:
direct combinational path!
inputs
x0...xn
Comb. Logic
S+
n CLK
FlipFlops
S
L6: MIC502 2013 Digital Systems Laboratory 6
A level-to-pulse converter produces a single-cycle pulse each time its input goes high. In other words, its a synchronous risingedge detector. Sample uses:
Buttons
and switches pressed by humans for arbitrary periods of time Single-cycle enable signals for counters
D Q
D Q
L=1 00 01
Edge Detected!
L=1 11
High input, Waiting for fall
L=0
L=1
P=0
if L=0 at the clock edge, then stay in state 00.
P=0
This is the output that results from this state. (Moore or Mealy?)
Transition diagram is readily converted to a state transition table (just a truth table)
L=1 L=0 L=1 L=1
Current State S1 0 0 0 0 1 1 S0 0 0 1 1 1 1
In L 0 1 0 1 0 1
Out
P 0 0 1 1 0 0
00
Low input, Waiting for rise
01
Edge Detected!
11
High input, Waiting for fall
P=0
P=1
L=0
P=0 L=0
S+ Comb. Logic
n CLK D Flip- Q
S1S0 for S0 00 01 11 10 L 0 0 0 0 X 1 1 1 1 X
+:
Flops
n
Comb. Logic
P S0 S1 0 1
for P:
0 0 1 1 X 0
P = S1S0
inputs
x0...xn
Flip- Q Flops
n
Comb. Logic
outputs yk = fk(S)
S1 = LS0 S0+ = L
+
Q Q
S0
S1+
Q Q
S1
10
S+ Comb. Logic
n CLK
D Flip- Q
Flops
n
Comb. Logic
Since outputs are determined by state and inputs, Mealy FSMs may need fewer states than Moore FSM implementations
1. When L=1 and S=0, this output is asserted immediately and until the state transition occurs (or L changes).
L P Clock State
0
Input is low L=0 | P=0
1
Input is high
L=1 | P=0
2. After the transition to S=1 and as long as L remains at 1, this output is 0.
11
L=1 | P=1
Pres. State
In L 0 1 0 1
Next State S+ 0 1 0 1
Out
P 0 1 0 0
0
Input is low L=0 | P=0 L=0 | P=0
1
Input is high L=1 | P=0
S 0 0 1 1
Q Q
FSMs state simply remembers the previous value of L Circuit benefits from the Mealy FSMs implicit single-cycle assertion of outputs during state transitions
Digital Systems Laboratory 12
outputs are based on state only Mealy outputs are based on state and input Therefore, Mealy outputs generally occur one cycle earlier than a Moore:
13
Design the FSM controller for a Soda Vending Machine All selections are $0.30. The machine makes change. (Dimes and nickels only.) Inputs: limit 1 per clock
Q
30
30
COINS ONLY
25
14
...
...
got35c
got40c
got45c
got50c
15
idle
N=1 D=1 D=1 D=1 D=1 D=1 D=1
got5c
N=1
got10c
N=1
Q=1
got15c
N=1 Q=1
got20c
N=1 Q=1 Q=1
got25c
N=1
* *
chg35
DN=1
got30c
DC=1
Q=1
got35c
DC=1
* * * *
got40c
DC=1
chg40
DD=1
*
chg45b
DN=1
got45c
DC=1
chg45
DD=1
got50c
DC=1
chg50
DD=1
chg50b
DD=1
16
idle
N=1 D=1 D=1 D=1 D=1 D=1 D=1
same outputs, and The same transitions There are two duplicates in our original diagram.
Q=1
got5c
N=1
got5c
N=1
got10c
N=1
Q=1
D=1
got10c
N=1
got15c
N=1 Q=1
D=1
got15c
N=1 Q=1
got20c
N=1
D=1
got20c
N=1
D=1
got25c
N=1
got25c
N=1
*
rtn5
D=1
got30c
DC=1
got30c
DC=1
*
chg35
DN=1
got35c
DC=1
* * * *
got40c
DC=1
chg40
DD=1
*
chg45b
DN=1
got35c
DC=1
* * * *
DN=1
got40c
DC=1
rtn10
DD=1
* *
got45c
DC=1
chg45
DD=1
got45c
DC=1
rtn15
DD=1
got50c
DC=1
chg50
DD=1
chg50b
DD=1
got50c
DC=1
rtn20
DD=1
17
Comb. Logic
n CLK
State Q Register
n
Comb. Logic
module mooreVender (N, D, Q, DC, DN, DD, clk, reset, state);" input N, D, Q, clk, reset;" output DC, DN, DD;" output [3:0] state;" reg [3:0] state, next;"
State register
(sequential always block)
18
GOT_25c:
if (Q) next = GOT_50c;" else if (D) next = GOT_35c;" " else if (N) next = GOT_30c;" " else next = GOT_25c;" next next next next next = = = = = IDLE;" RETURN_5c;" RETURN_10c;" RETURN_15c;" RETURN_20c;" = = = = RETURN_10c;" RETURN_5c;" IDLE;" IDLE;"
(Q) next = GOT_25c;" (D) next = GOT_10c;" if (N) next = GOT_5c;" next = IDLE;" (Q) next = GOT_30c;" (D) next = GOT_15c;" if (N) next = GOT_10c;" next = GOT_5c;" (Q) next = GOT_35c;" (D) next = GOT_20c;" if (N) next = GOT_15c;" next = GOT_10c;" (Q) next = GOT_40c;" (D) next = GOT_25c;" if (N) next = GOT_20c;" next = GOT_15c;" (Q) next = GOT_45c;" (D) next = GOT_30c;" if (N) next = GOT_25c;" next = GOT_20c;"
19
State Output
idle
got5c got15c
got20c got45c
rtn15 rtn5
idle
10
20
next = GOT_25c;" next = GOT_10c;" next = GOT_5c;" IDLE;" next = GOT_30c;" next = GOT_15c;" next = GOT_10c;" GOT_5c;" next = GOT_35c;" next = GOT_20c;" next = GOT_15c;" GOT_10c;" next = GOT_40c;" next = GOT_25c;" next = GOT_20c;" GOT_15c;" next = GOT_45c;" next = GOT_30c;" next = GOT_25c;" GOT_20c;" next = GOT_50c;" next = GOT_35c;" next = GOT_30c;" GOT_25c;"
RETURN_20c: begin" DD = " end" RETURN_15c: begin" DD = end" RETURN_10c: begin" DD = end" RETURN_5c: begin" DN = " end"
FSM state bits may not transition at precisely the same time Combinational logic for outputs may contain hazards Result: your FSM outputs may glitch!
during this state transition...
got10c
D=1
0010! 0110!
0! 1! glitch
0!
got20c
0100!
assign DC = (state == GOT_30c || state == GOT_35c ||! state == GOT_40c || state == GOT_45c || ! state == GOT_50c);!
If the soda dispenser is glitch-sensitive, your customers can get a 20-cent soda!
L6: MIC502 2013 Digital Systems Laboratory 22
D Output Q CLK
Registers
registered outputs
inputs
D CLK
State Q Registers
n
present state S
Move output generation into the sequential always block Calculate outputs based on next state
reg DC,DN,DD;" // Sequential always block for state assignment" always @ (posedge clk or negedge reset) begin" if (!reset) state <= IDLE;" else if (clk) state <= next;" DC <= (next next next DN <= (next DD <= (next next end" == == == == == == GOT_30c || next == GOT_35c ||" GOT_40c || next == GOT_45c || " GOT_50c);" RETURN_5c);" RETURN_20c || next == RETURN_15c || " RETURN_10c);"
23
idle
N=1 D=1
got5c
N=1
A Mealy machine can eliminate states devoted solely to holding an output value.
Q=1
D=1
got10c
N=1
D=1
got15c
N=1 Q=1
*
D=1
D=1
got20c
N=1
D=1
got25c
N=1
Q=1 Q=1
* | DN=1
* | DD=1
Q=1 | DC=1
D=1
got30c
DC=1
got35c
DC=1
Q=1
rtn5
DN=1
got10c N=1
Q=1 | DC=1
rtn5
* * * *
got40c
DC=1
rtn10
DD=1
* *
Q=1 | DC=1
rtn10
* | DD=1
got45c
DC=1
rtn15
DD=1
got50c
DC=1
rtn20
DD=1
rtn15
rtn20
* | DD=1
24
module mealyVender (" input N, D, Q, clk, reset," output reg DC, DN, DD," output reg [3:0] state" );" reg [3:0] next;" parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter IDLE = 0;" GOT_5c = 1;" GOT_10c = 2;" GOT_15c = 3;" GOT_20c = 4;" GOT_25c = 5;" RETURN_20c = 6;" RETURN_15c = 7;" RETURN_10c = 8;" RETURN_5c = 9;"
// Sequential always block for state assignment" always @ (posedge clk or negedge reset)" if (!reset) state <= IDLE;" else state <= next;"
25
always @ (state or N or D or Q) begin" DC = 0; DN = 0; DD = 0; case (state)" IDLE: if (Q) else if (D) "else if (N) "else next = GOT_5c: // defaults"
if (Q) begin" DC = 1; next = IDLE; " end" else if (D) next = GOT_15c;" "else if (N) next = GOT_10c;" "else next = GOT_5c;" if (Q) DC = end" else if (D) "else if (N) "else next = if (Q) DC = end" else if (D) "else if (N) "else next = begin" 1; next = RETURN_5c;" next = GOT_20c;" next = GOT_15c;" GOT_10c;" begin" 1; next = RETURN_10c;" next = GOT_25c;" next = GOT_20c;" GOT_15c;"
GOT_10c:
RETURN_20c:
GOT_15c:
1; next = RETURN_10c;"
1; next = RETURN_5c;"
1; next = IDLE;"
1; next = IDLE;"
GOT_20c:
if (Q) begin" DC = 1; next = RETURN_15c;" end" else if (D) begin" " DC = 1; next = IDLE;" " end" "else if (N) next = GOT_25c;" "else next = GOT_20c;"
26
State Output
idle
got5c got15c
got20c rtn15
rtn5
idle
10
Clock
II
III
?
All of them can be, if more than one happens simultaneously within the same circuit. Idea: ensure that external signals directly feed exactly one flip-flop
Clocked Synchronous System Async Input Q0
D Q
Sequential System
Clock D Q Q1
Clock
Clock
This prevents the possibility of I and II occurring in different places in the circuit, but what about metastability?
29
Preventing metastability turns out to be an impossible problem High gain of digital devices makes it likely that metastable conditions will resolve themselves quickly Solution to metastability: allow time for signals to stabilize Likeley to be metastable right after sampling Very unlikely to be metastable for >1 clock cycle Extremely unlikely to be metastable for >2 clock cycle
D Q
D Q D Q
Clock
Depends on many design parameters(clock speed, device speeds, ) For our class, one or maybe two synchronization registers is sufficient
Digital Systems Laboratory 30
Two
Moore
outputs are a function of current state Mealy outputs are a function of current state and input
A
Register
outputs of combinational logic for critical control signals all asynchronous inputs
Use
Synchronize Clock
31
CLout
In
D Q
Combinational
Logic
Wire delay
D Q
ClkD
Clk CLK
CLKD
>0
T >
Tcq + Tlogic + Tsu -
Tcq,cd + Tlogic,cd > Thold +
L6: MIC502 2013 Digital Systems Laboratory 32
The image part with relationship ID rId3 was not found in the le.
The image part with relationship ID rId4 was not found in the le.
34
VDD
The image part with relationship ID rId7 was not found in the le.
Vin
Vout CL
V DD (b) High-to-low
review
V out CL Ron
vin
vout C
V out CL
tp = ln (2) = 0.69 RC
L6: MIC502 2013 Digital Systems Laboratory
35