Vous êtes sur la page 1sur 35

Acknowledgements: Lecture material adapted from Chapters 6&7 of R. Katz, G.

Borriello, Contemporary Logic Design (second edition), Prentice-Hall/Pearson Education, 2005.

L6: MIC502 2013

Digital Systems Laboratory

Count (C) will be retained by a D Register Next value of counter (N) computed by combinational logic
C3 0 0 0 0 1 1 1 1 C2 0 0 1 1 0 0 1 1 C1 N3 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 0 N2 0 1 1 0 0 1 1 0 N1 1 0 1 0 1 0 1 0
N1
1 1 0 1 0

C3
1 0

N 2

C3
0 1 0 1 0 0 1

C1 0

C1 1 C3

C2

N3
0 0 1 1 0

C2
1 1

C1 0

C2
C1 C2 D Q D Q C3

N1 := C1 N2 := C1 C2 + C1 C2 := C1 xor C2 N3 := C1 C2 C3 + C1 C3 + C2 C3 := C1 C2 C3 + (C1 + C2 ) C3 := (C1 C2) xor C3 From [Katz05]



L6: MIC502 2013 Digital Systems Laboratory CLK

D Q

C1

C2

C3

Output logic Registers

D CLK

Next-state logic

N1 := C1 N2 := C1 C2 + C1 C2 := C1 xor C2 N3 := C1 C2 C3 + C1 C3 + C2 C3 := C1 C2 C3 + (C1 + C2 ) C3 := (C1 C2) xor C3

L6: MIC502 2013

Digital Systems Laboratory

Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized states of operation At each clock edge, combinational logic computes outputs and next state as a function of inputs and present state

inputs + present state

Combinational Logic

outputs + next state

n Q D

CLK
L6: MIC502 2013

FlipFlops

Digital Systems Laboratory

Timing requirements for FSM are identical to any generic sequential system with feedback
Minimum Clock Period Minimum Delay
inputs + present state

inputs + present state

Combinational Logic

outputs + next state

Combinational Logic

outputs + next state

Tlogic
Tcq

Q FlipFlops D

Tlogic,cd
Tcq,cd

Q FlipFlops D

CLK

Tsu

CLK

Thold

T > Tcq + Tlogic + Tsu



L6: MIC502 2013 Digital Systems Laboratory

Tcq,cd + Tlogic,cd > Thold



5

Moore and Mealy FSMs are distinguished by their output generation


Moore FSM: inputs
x0...xn
next state S+ Comb. Logic
n CLK D

Flip- Q Flops
n

Comb. Logic

outputs yk = fk(S)

present state S

Mealy FSM:
direct combinational path!

inputs
x0...xn
Comb. Logic

outputs yk = fk(S, x0...xn)


Comb. Logic
n

S+
n CLK

FlipFlops

S
L6: MIC502 2013 Digital Systems Laboratory 6

A level-to-pulse converter produces a single-cycle pulse each time its input goes high. In other words, its a synchronous risingedge detector. Sample uses:
Buttons

and switches pressed by humans for arbitrary periods of time Single-cycle enable signals for counters

Level to L P Pulse Converter


Whenever input L goes from low to high... CLK

...output P produces a single pulse, one clock period wide.

L6: MIC502 2013

Digital Systems Laboratory

Block diagram of desired system:


Synchronizer
unsynchronized user input CLK

Edge Detector Level to L P Pulse FSM

D Q

D Q

State transition diagram is a useful FSM representation and design aid


if L=1 at the clock edge, then jump to state 01.

L=1 00 01
Edge Detected!

L=1 11
High input, Waiting for fall

Binary values of states

L=0

Low input, Waiting for rise

L=1

P=0
if L=0 at the clock edge, then stay in state 00.

P=1 L=0 L=0

P=0
This is the output that results from this state. (Moore or Mealy?)

L6: MIC502 2013

Digital Systems Laboratory

Transition diagram is readily converted to a state transition table (just a truth table)
L=1 L=0 L=1 L=1

Current State S1 0 0 0 0 1 1 S0 0 0 1 1 1 1

In L 0 1 0 1 0 1

Next State S1+ 0 0 0 1 0 1 S0+ 0 1 0 1 0 1

Out
P 0 0 1 1 0 0

00
Low input, Waiting for rise

01
Edge Detected!

11
High input, Waiting for fall

P=0

P=1
L=0

P=0 L=0

Combinational logic may be derived by Karnaugh maps


S1S0 for S1 : 00 01 11 10 L 0 0 0 0 X 1 0 1 1 X
+

S+ Comb. Logic
n CLK D Flip- Q

S1S0 for S0 00 01 11 10 L 0 0 0 0 X 1 1 1 1 X

+:

Flops
n

Comb. Logic

P S0 S1 0 1

for P:
0 0 1 1 X 0

S1+ = LS0 S0+ = L

P = S1S0

L6: MIC502 2013

Digital Systems Laboratory

inputs
x0...xn

next state S+ Comb. Logic


n CLK D

Flip- Q Flops
n

Comb. Logic

outputs yk = fk(S)

S1 = LS0 S0+ = L
+

present state S P = S1S0

Moore FSM circuit implementation of level-to-pulse converter:


L
S0+
CLK

Q Q

S0

S1+

Q Q

S1

L6: MIC502 2013

Digital Systems Laboratory

10

direct combinational path!

S+ Comb. Logic
n CLK

D Flip- Q

Flops
n

Comb. Logic

Since outputs are determined by state and inputs, Mealy FSMs may need fewer states than Moore FSM implementations
1. When L=1 and S=0, this output is asserted immediately and until the state transition occurs (or L changes).

L P Clock State

L=1 | P=1 L=0 | P=0

0
Input is low L=0 | P=0

1
Input is high

L=1 | P=0
2. After the transition to S=1 and as long as L remains at 1, this output is 0.

Output transitions immediately. State transitions at the clock edge.


L6: MIC502 2013

Digital Systems Laboratory

11

L=1 | P=1

Pres. State

In L 0 1 0 1

Next State S+ 0 1 0 1

Out
P 0 1 0 0

0
Input is low L=0 | P=0 L=0 | P=0

1
Input is high L=1 | P=0

S 0 0 1 1

Mealy FSM circuit implementation of level-to-pulse converter:


P L
S+
CLK

Q Q

FSMs state simply remembers the previous value of L Circuit benefits from the Mealy FSMs implicit single-cycle assertion of outputs during state transitions
Digital Systems Laboratory 12

L6: MIC502 2013

Remember that the difference is in the output:


Moore

outputs are based on state only Mealy outputs are based on state and input Therefore, Mealy outputs generally occur one cycle earlier than a Moore:

Moore: delayed assertion of P


L P Clock State[0]

Mealy: immediate assertion of P


L P Clock State

Compared to a Moore FSM, a Mealy FSM might...


Be

more difficult to conceptualize and design Have fewer states

L6: MIC502 2013

Digital Systems Laboratory

13

Design the FSM controller for a Soda Vending Machine All selections are $0.30. The machine makes change. (Dimes and nickels only.) Inputs: limit 1 per clock
Q

30

30
COINS ONLY

25

10 5 Coke Sprite Fanta Water Pepsi

quarter (25) inserted D dime (10) inserted N nickel (5) inserted

Outputs: limit 1 per clock


DC

- dispense can DD - dispense dime DN - dispense nickel

L6: MIC502 2013

Digital Systems Laboratory

14

A starting (idle) state:


idle

A state for each possible amount of money captured:


got5c got10c got15c

...

Whats the maximum amount of money captured before purchase?


25 cents (just shy of a purchase) + one quarter (largest coin)

...

got35c

got40c

got45c

got50c

States to dispense change (one per coin dispensed):


got45c
Dispense Dime Dispense Nickel

L6: MIC502 2013

Digital Systems Laboratory

15

Heres a first cut at the state transition diagram.

idle
N=1 D=1 D=1 D=1 D=1 D=1 D=1

got5c
N=1

got10c
N=1

Q=1

got15c
N=1 Q=1

got20c
N=1 Q=1 Q=1

got25c
N=1

* *
chg35
DN=1

got30c
DC=1

Q=1

got35c
DC=1

* * * *

Is there a better way of doing it?

got40c
DC=1

chg40
DD=1

*
chg45b
DN=1

got45c
DC=1

chg45
DD=1

got50c
DC=1

chg50
DD=1

chg50b
DD=1

L6: MIC502 2013

Digital Systems Laboratory

16

Duplicate states have:


The idle
N=1 D=1

idle
N=1 D=1 D=1 D=1 D=1 D=1 D=1

same outputs, and The same transitions There are two duplicates in our original diagram.
Q=1

got5c
N=1

got5c
N=1

got10c
N=1

Q=1

D=1

got10c
N=1

got15c
N=1 Q=1

D=1

got15c
N=1 Q=1

got20c
N=1

D=1

got20c
N=1

D=1

got25c
N=1

Q=1 Q=1 Q=1

got25c
N=1

Q=1 Q=1 Q=1

*
rtn5

D=1

got30c
DC=1

got30c
DC=1

*
chg35
DN=1

got35c
DC=1

* * * *

got40c
DC=1

chg40
DD=1

*
chg45b
DN=1

17 states 5 state bits

15 states 4 state bits

got35c
DC=1

* * * *

DN=1

got40c
DC=1

rtn10
DD=1

* *

got45c
DC=1

chg45
DD=1

got45c
DC=1

rtn15
DD=1

got50c
DC=1

chg50
DD=1

chg50b
DD=1

got50c
DC=1

rtn20
DD=1

L6: MIC502 2013

Digital Systems Laboratory

17

Comb. Logic

n CLK

State Q Register
n

Comb. Logic

module mooreVender (N, D, Q, DC, DN, DD, clk, reset, state);" input N, D, Q, clk, reset;" output DC, DN, DD;" output [3:0] state;" reg [3:0] state, next;"

States defined with parameter keyword


parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter IDLE = 0;" GOT_5c = 1;" GOT_10c = 2;" GOT_15c = 3;" GOT_20c = 4;" GOT_25c = 5;" GOT_30c = 6;" GOT_35c = 7;" GOT_40c = 8;" GOT_45c = 9;" GOT_50c = 10;" RETURN_20c = 11;" RETURN_15c = 12;" RETURN_10c = 13;" RETURN_5c = 14;"

FSMs are easy in Verilog. Simply write one of each:

State register
(sequential always block)

Next-state combinational logic


(comb. always block with case)

Output combinational logic block


(comb. always block or assign statements)

State register defined with sequential always block


always @ (posedge clk or negedge reset)" if (!reset) state <= IDLE;" else state <= next;"

L6: MIC502 2013

Digital Systems Laboratory

18

Next-state logic within a combinational always block


always @ (state or N or D or Q) begin" case (state)" IDLE: if else if " else " else GOT_5c: if else if " else " else GOT_10c: if else if " else " else GOT_15c: if else if " else " else GOT_20c: if else if " else " else

GOT_25c:

if (Q) next = GOT_50c;" else if (D) next = GOT_35c;" " else if (N) next = GOT_30c;" " else next = GOT_25c;" next next next next next = = = = = IDLE;" RETURN_5c;" RETURN_10c;" RETURN_15c;" RETURN_20c;" = = = = RETURN_10c;" RETURN_5c;" IDLE;" IDLE;"

(Q) next = GOT_25c;" (D) next = GOT_10c;" if (N) next = GOT_5c;" next = IDLE;" (Q) next = GOT_30c;" (D) next = GOT_15c;" if (N) next = GOT_10c;" next = GOT_5c;" (Q) next = GOT_35c;" (D) next = GOT_20c;" if (N) next = GOT_15c;" next = GOT_10c;" (Q) next = GOT_40c;" (D) next = GOT_25c;" if (N) next = GOT_20c;" next = GOT_15c;" (Q) next = GOT_45c;" (D) next = GOT_30c;" if (N) next = GOT_25c;" next = GOT_20c;"

GOT_30c: GOT_35c: GOT_40c: GOT_45c: GOT_50c:

RETURN_20c: RETURN_15c: RETURN_10c: RETURN_5c:

next next next next

default: next = IDLE;" endcase" end"

Combinational output assignment


assign DC = (state state state assign DN = (state assign DD = (state state endmodule" == == == == == == GOT_30c || state == GOT_35c ||" GOT_40c || state == GOT_45c || " GOT_50c);" RETURN_5c);" RETURN_20c || state == RETURN_15c || " RETURN_10c);"

L6: MIC502 2013

Digital Systems Laboratory

19

State Output

idle

got5c got15c

got20c got45c

rtn15 rtn5

idle

10

L6: MIC502 2013

Digital Systems Laboratory

20

Next-state and output logic combined into a single always block


always @ (state or N or D or Q) begin" DC = 0; DD = 0; DN = 0; case (state)" IDLE: if (Q) else if (D) " else if (N) " else next = GOT_5c: else " else " else GOT_10c: else " else " else GOT_15c: else " else " else GOT_20c: else " else " else GOT_25c: else " else " else L6: MIC502 2013 if (Q) if (D) if (N) next = if (Q) if (D) if (N) next = if (Q) if (D) if (N) next = if (Q) if (D) if (N) next = if (Q) if (D) if (N) next = // defaults" GOT_30c: GOT_35c: GOT_40c: GOT_45c: GOT_50c: " begin" DC = 1; end" begin" DC = 1; end" begin" DC = 1; end" begin" DC = 1; end" begin " DC = 1; end" next = IDLE;" next = RETURN_5c;" next = RETURN_10c;" next = RETURN_15c;" next = RETURN_20c;"

next = GOT_25c;" next = GOT_10c;" next = GOT_5c;" IDLE;" next = GOT_30c;" next = GOT_15c;" next = GOT_10c;" GOT_5c;" next = GOT_35c;" next = GOT_20c;" next = GOT_15c;" GOT_10c;" next = GOT_40c;" next = GOT_25c;" next = GOT_20c;" GOT_15c;" next = GOT_45c;" next = GOT_30c;" next = GOT_25c;" GOT_20c;" next = GOT_50c;" next = GOT_35c;" next = GOT_30c;" GOT_25c;"

RETURN_20c: begin" DD = " end" RETURN_15c: begin" DD = end" RETURN_10c: begin" DD = end" RETURN_5c: begin" DN = " end"

1; next = RETURN_10c;" 1; next = RETURN_5c;" 1; next = IDLE;" 1; next = IDLE;"

default: next = IDLE;" endcase" end" 21

Digital Systems Laboratory

FSM state bits may not transition at precisely the same time Combinational logic for outputs may contain hazards Result: your FSM outputs may glitch!
during this state transition...
got10c
D=1

...the state registers may transtion like this...

...causing the DC output to glitch like this!

0010! 0110!

got10c got30c got20c

0! 1! glitch
0!

got20c

0100!

assign DC = (state == GOT_30c || state == GOT_35c ||! state == GOT_40c || state == GOT_45c || ! state == GOT_50c);!

If the soda dispenser is glitch-sensitive, your customers can get a 20-cent soda!
L6: MIC502 2013 Digital Systems Laboratory 22

Output Comb. Logic NextState Comb. Logic next state


n

D Output Q CLK

Registers

registered outputs

inputs

D CLK

State Q Registers
n

present state S

Move output generation into the sequential always block Calculate outputs based on next state

reg DC,DN,DD;" // Sequential always block for state assignment" always @ (posedge clk or negedge reset) begin" if (!reset) state <= IDLE;" else if (clk) state <= next;" DC <= (next next next DN <= (next DD <= (next next end" == == == == == == GOT_30c || next == GOT_35c ||" GOT_40c || next == GOT_45c || " GOT_50c);" RETURN_5c);" RETURN_20c || next == RETURN_15c || " RETURN_10c);"

L6: MIC502 2013

Digital Systems Laboratory

23

idle
N=1 D=1

got5c
N=1

A Mealy machine can eliminate states devoted solely to holding an output value.
Q=1

D=1

got10c
N=1

D=1

got15c
N=1 Q=1

*
D=1

idle N=1 got5c N=1 D=1 Q=1

D=1

got20c
N=1

D=1

got25c
N=1

Q=1 Q=1

* | DN=1

* | DD=1

Q=1 | DC=1

D=1

got30c
DC=1

got35c
DC=1

Q=1

rtn5
DN=1

got10c N=1

Q=1 | DC=1

rtn5

* * * *

got40c
DC=1

rtn10
DD=1

* *

D=1 D=1 | DC=1 D=1 N=1 | DC=1

got15c N=1 got20c N=1 got25c

Q=1 | DC=1

rtn10

* | DD=1

got45c
DC=1

rtn15
DD=1

Q=1 | DC=1 D=1 | DC=1 Q=1 | DC=1

got50c
DC=1

rtn20
DD=1

rtn15

rtn20

* | DD=1

L6: MIC502 2013

Digital Systems Laboratory

24

module mealyVender (" input N, D, Q, clk, reset," output reg DC, DN, DD," output reg [3:0] state" );" reg [3:0] next;" parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter IDLE = 0;" GOT_5c = 1;" GOT_10c = 2;" GOT_15c = 3;" GOT_20c = 4;" GOT_25c = 5;" RETURN_20c = 6;" RETURN_15c = 7;" RETURN_10c = 8;" RETURN_5c = 9;"

// Sequential always block for state assignment" always @ (posedge clk or negedge reset)" if (!reset) state <= IDLE;" else state <= next;"

L6: MIC502 2013

Digital Systems Laboratory

25

always @ (state or N or D or Q) begin" DC = 0; DN = 0; DD = 0; case (state)" IDLE: if (Q) else if (D) "else if (N) "else next = GOT_5c: // defaults"

For state GOT_5c, output DC is only asserted if Q=1


GOT_25c: if (Q) DC = end" else if (D) " DC = end" "else if (N) " DC = end" "else next = begin" 1; next = RETURN_20c;" begin" 1; next = RETURN_5c;" begin" 1; next = IDLE; GOT_25c;"

next = GOT_25c;" next = GOT_10c;" next = GOT_5c;" IDLE;"

if (Q) begin" DC = 1; next = IDLE; " end" else if (D) next = GOT_15c;" "else if (N) next = GOT_10c;" "else next = GOT_5c;" if (Q) DC = end" else if (D) "else if (N) "else next = if (Q) DC = end" else if (D) "else if (N) "else next = begin" 1; next = RETURN_5c;" next = GOT_20c;" next = GOT_15c;" GOT_10c;" begin" 1; next = RETURN_10c;" next = GOT_25c;" next = GOT_20c;" GOT_15c;"

GOT_10c:

RETURN_20c:

RETURN_15c: " RETURN_10c: " RETURN_5c: "

GOT_15c:

begin" DD = end" begin" DD = end" begin" DD = end" begin" DN = end"

1; next = RETURN_10c;"

1; next = RETURN_5c;"

1; next = IDLE;"

1; next = IDLE;"

GOT_20c:

if (Q) begin" DC = 1; next = RETURN_15c;" end" else if (D) begin" " DC = 1; next = IDLE;" " end" "else if (N) next = GOT_25c;" "else next = GOT_20c;"

default: next = IDLE;" endcase" end" endmodule"

L6: MIC502 2013

Digital Systems Laboratory

26

State Output

idle

got5c got15c

got20c rtn15

rtn5

idle

10

(note: outputs should be registered)


L6: MIC502 2013 Digital Systems Laboratory 27

What about external signals?


Sequential System

Cant guarantee setup and hold times will be met!

Clock

When an asynchronous signal causes a setup/hold violation...


I Q D Clock
Transition is missed on first clock cycle, but caught on next clock cycle.
L6: MIC502 2013

II

III
?

Transition is caught on first clock cycle.

Output is metastable for an indeterminate amount of time.

Q: Which cases are problematic?


Digital Systems Laboratory 28

All of them can be, if more than one happens simultaneously within the same circuit. Idea: ensure that external signals directly feed exactly one flip-flop
Clocked Synchronous System Async Input Q0

D Q

Sequential System

Clock D Q Q1

Clock

Clock

This prevents the possibility of I and II occurring in different places in the circuit, but what about metastability?

L6: MIC502 2013

Digital Systems Laboratory

29

Preventing metastability turns out to be an impossible problem High gain of digital devices makes it likely that metastable conditions will resolve themselves quickly Solution to metastability: allow time for signals to stabilize Likeley to be metastable right after sampling Very unlikely to be metastable for >1 clock cycle Extremely unlikely to be metastable for >2 clock cycle

D Q

D Q D Q

Complicated Sequential Logic System

Clock

How many registers are necessary?


Depends on many design parameters(clock speed, device speeds, ) For our class, one or maybe two synchronization registers is sufficient
Digital Systems Laboratory 30

L6: MIC502 2013

Two

types of Finite State Machines introduced

Moore

outputs are a function of current state Mealy outputs are a function of current state and input
A

standard template can be used for coding FSMs

Register

outputs of combinational logic for critical control signals all asynchronous inputs
Use

Synchronize Clock

two back to back registers

skew and jitter are important considerations

L6: MIC502 2013

Digital Systems Laboratory

31

CLout
In
D Q

Combinational
Logic

Wire delay

D Q

ClkD

Clk CLK
CLKD
>0

T >
Tcq + Tlogic + Tsu -
Tcq,cd + Tlogic,cd > Thold +

L6: MIC502 2013 Digital Systems Laboratory 32

The image part with relationship ID rId3 was not found in the le.

The image part with relationship ID rId4 was not found in the le.

Launching edge arrives before the receiving edge


The image part with relationship ID rId2 was not found in the le. The image part with relationship ID rId5 was not found in the le.

Receiving edge arrives before the launching edge


Adapted from J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective Copyright 2003 Prentice Hall/Pearson.

L6: MIC502 2013 Digital Systems Laboratory 33

L6: MIC502 2013

Digital Systems Laboratory

34

VDD

The image part with relationship ID rId7 was not found in the le.

Vin

Vout CL

V DD Ron (a) Low-to-high

V DD (b) High-to-low

review
V out CL Ron
vin

vout C

V out CL

tp = ln (2) = 0.69 RC
L6: MIC502 2013 Digital Systems Laboratory

(time to reach 0.5V)

35

Vous aimerez peut-être aussi