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This document discusses the design of a sequential circuit using J-K flip-flops. It provides a state diagram and state table for the circuit with 4 states and 1 input. An excitation table is then derived showing the input conditions for each transition. Boolean functions for the flip-flop inputs are obtained from the table and plotted on Karnaugh maps to minimize the logic. The final logic diagram implements the circuit with J-K flip-flops and combinational logic gates.
This document discusses the design of a sequential circuit using J-K flip-flops. It provides a state diagram and state table for the circuit with 4 states and 1 input. An excitation table is…