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5

Cathedral Peak 2A Block Diagram


DDR2

Project code: 91.4K901.001


PCB P/N
: 48.4K901.001
REVISION
: 08220- -1
PCB STACKUP

667/800MHz

AMD Giffin CPU


S1G2 (35W)

667/800 MHz
8,9

DDR2

22

IN

3D3V_S5(6A)

38
OUTPUTS

RT8202 X 2
INPUTS

1D1V_S0(7.5A)

BOTTOM

LCD

16X16

SYSTEM DC/DC

GND

15

DCBATOUT
1D2V_S0(4A)

14

SYSTEM DC/DC
INPUTS

39
OUTPUTS

DCBATOUT

1D8V_S3(11A)

RT8202

AMD RS780M
CPU I/F

LVDS, CRT I/F

LAN

INTEGRATED GRAHPICS

TXFM

Giga LAN
BCM5764

RJ45

27

26

RT9026PFP

27

0D9V_S3

PWR SW
TPS223128

New card

INT MIC

Codec

A-Link
4X4

AZALIA

28

PCIex1

Kedron a/b/g/n

South Bridge

BIOS

ATA 66/100

Line Out
(No-SPDIF)

WPC773L

MAX8731

DEBUG
CONN.32

32
31

1D2V_S5
(400mA)

CHARGER

LPC

MXIC
MX25L1605

KBC
Winbond

High Definition Audio

APA205730

40

3D3V_S5

ETHERNET (10/100/1000Mb)

OP AMP

INPUTS

CHG_PWR

PCI/PCI BRIDGE
17,18,19,20,21

SATA

MODEM
MDC Card
24

USB

Mini USB
Blue Tooth 24

HDD SATA
23

CardReader
Realtek
RTS5158E
25
USB
3 Port

ODD SATA

18V

DCBATOUT

LPC I/F

Touch
Pad 31

41

OUTPUTS

ACPI 1.1

30

5V

100mA

CPU DC/DC
ISL6265HR 36
INPUTS OUTPUTS
VCC_CORE_S0_0

MS/MS Pro/xD
/MMC/SD
5 in 1

0~1.55V

25

DCBATOUT

18A

VCC_CORE_S0_1
0~1.55V

18A

VDDNB
0~1.55V

18A

24
<Core Design>

Camera

Daughter Board
LAUNCH Board
08575

16

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

BLOCK DIAGRAM
Size

A3

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

6.0A

UP+5V

INT.
KB 31

23

40
1D5V_S0
(1A)

G9161

LPC BUS

USB 2.0/1.1 ports

INT.SPKR

RJ11

2D5V_S0
(200mA)

G957

28

29
AMD SB700

40

3D3V_S0

3D3V_S0

30

30

RT9161

Mini Card

ALC268
MIC In

39
DDR_VREF_S3

5V_S5

11,12,13

30

5V_S5(6A)

North Bridge

ICS9LPRS480BKLFT 71.09480.A03
RTM880N-796-VB-GRT 71.00880.A03

37
OUTPUTS

DCBATOUT

CRT
OUT

TPS51125

4,5,6,7

CLK GEN. 3

SYSTEM DC/DC
INPUTS

VCC

638-Pin uFCPGA638

667/800MHz

667/800 MHz
8,9

TOP

G792

Sheet
1

-1
of

43

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HISTORY
Size

A3

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

of

43

3D3V_S0

3D3V_CLK_VDD

3D3V_S0

3000mA.80ohm

R371 1 0R0402-PAD
2
R372 1 0R0402-PAD
2

CLK_PCIE_MINI1_1
CLK_PCIE_MINI1#_1

R373 1 0R0402-PAD
2
R374 1 0R0402-PAD
2

CLK_PCIE_NEW_1
CLK_PCIE_NEW#_1
CLK_SRC0T_LPRS
CLK_SRC0C_LPRS

TPAD14-GP
TP201
TPAD14-GP
TP202

VDDSRC
VDDSRC_IO
VDDSRC_IO

35
34

VDDSB_SRC
VDDSB_SRC_IO

40
4
55
56
63

VDDSATA
VDD
VDDHTT
VDDREF
VDD48

51

PD#

22
21
20
19
15
14
13
12
9
8
42
41
6
5
37
36
32
31

R375 1 0R0402-PAD
2
R376 1 0R0402-PAD
2

12 CLK_NBHT_CLK
12 CLK_NBHT_CLK#

NB HT

CLK_NBHT_CLK_1
CLK_NBHT_CLK#_1

54
53

SMBCLK
SMBDAT

2
3

CLK_SMBCLK
CLK_SMBDAT

30
29
28
27

CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#

23
45
44
39
38

CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#

CPUKG0T_LPRS
CPUKG0C_LPRS
SRC0T_LPRS
SRC0C_LPRS
48MHZ_0
SRC1T_LPRS
SRC1C_LPRS
SRC2T_LPRS
REF0/SEL_HTT66
SRC2C_LPRS
REF1/SEL_SATA
SRC3T_LPRS
REF2/SEL_27
SRC3C_LPRS
SRC4T_LPRS
SRC4C_LPRS
SRC6T/SATAT_LPRS
GNDSATA
SRC6C/SATAC_LPRS
GNDATIG
SRC7T_LPRS/27MHZ_SS
GND
SRC7C_LPRS/27MHZ_NS
GNDHTT
GNDREF
GNDCPU
SB_SRC0T_LPRS
GND48
SB_SRC0C_LPRS
SB_SRC1T_LPRS
GNDSRC
SB_SRC1C_LPRS
GNDSRC

50
49

CPU_CLK_1
CPU_CLK#_1

HTT0T_LPRS/66M
HTT0C_LPRS/66M

G45
G44

2
1
2
1
GAP-CLOSE
GAP-CLOSE

CLK_48

59
58
57

TP128
TP135
TP132
TP136
TP133

SC33P50V2JN-3GP

SMBC0_SB 8,9,18
SMBD0_SB 8,9,18

SB

CLKREQ# Internal
pull Low

CLK_NB_GFX 12
CLK_NB_GFX# 12

REF0
REF1
REF2

1
1

TP207 TPAD14-GP
TP208 TPAD14-GP

64

C198

2ND = 82.30005.951

CL=20pF0.2pF

ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS

16
17
11

GEN_XTAL_IN
GEN_XTAL_OUT

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP

R377 1 0R0402-PAD
2
R378 1 0R0402-PAD
2

CPU_CLK
CPU_CLK#

RN22

1
2

6
6
CLK48_USB 18

4
3

CLK48_5158E 25

SRN33J-5-GP-U

CLK_NB_GPPSB_1
CLK_NB_GPPSB#_1

VDDCPU
VDDCPU_IO

61
62

CLK_PCIE_LAN_1
CLK_PCIE_LAN#_1

R369 1 0R0402-PAD
2
R370 1 0R0402-PAD
2

48
47

X1
X2

EC69

DY
43
24
7
52
60
46
1

DY

EC68

SA

SC22P50V2JN-4GP

R367 1 0R0402-PAD
2
R368 1 0R0402-PAD
2

VDDATIG
VDDATIG_IO

SC22P50V2JN-4GP

26 CLK_PCIE_LAN
26 CLK_PCIE_LAN#

28 CLK_PCIE_NEW
28 CLK_PCIE_NEW#

CLK_PCIE_SB_1
CLK_PCIE_SB#_1

26
25

1
2

VDD_REF
3D3V_48MPWR_S0
PD#

NEW

X4
X-14D31818M-35GP
82.30005.891

U13
1D1V_CLK_VDDIO

R365 1 0R0402-PAD
2
R366 1 0R0402-PAD
2

28 CLK_PCIE_MINI1
28 CLK_PCIE_MINI1#

10MR2J-L-GP

17 CLK_PCIE_SB
17 CLK_PCIE_SB#

12 CLK_NB_GPPSB
12 CLK_NB_GPPSB#

DY

3D3V_CLK_VDD

1
2

C218
SCD1U10V2KX-4GP

C210
SCD1U10V2KX-4GP

C200
SCD1U10V2KX-4GP

C215
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C192

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

C232

MINI

SB
C201
SC27P50V2JN-2-GP

1 R295
2
0R0603-PAD
C206
SC1U10V2KX-1GP

NB A-Link

Clock chip has internal serial terminations


for differencial pairs, external resistors are
reserved for debug purpose.

R141

3D3V_CLK_VDD

LAN

1D1V_CLK_VDDIO

C230

SB A-Link

Due to PLL issue on current clock chip, the SBlink clock


need to come from SRC clocks for RS740 and RS780.
Future clock chip revision will fix this.

C197
SC1U10V2KX-1GP

DY

3D3V_S0

1 R308
2
0R0603-PAD
1D1V_S0
R154
1
DY 2
0R3-0-U-GP

C190

3D3V_48MPWR_S0

2
2R3J-GP

SC4D7U6D3V3KX-GP

C211
SCD1U10V2KX-4GP

C194
SCD1U10V2KX-4GP

DY

C193
SCD1U10V2KX-4GP

C209
SCD1U10V2KX-4GP

C216
SCD1U10V2KX-4GP

C219
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

DY C217

C220

C213

R139

1 R140
2
0R0603-PAD

10
18

GNDSB_SRC

33

GND

65

RS740

RX780

RS780

HT_REFCLKP
66M SE(SINGLE END)

3D3V_S0

NB CLOCK INPUT TABLE


NB CLOCKS

NC

100M DIFF
100M DIFF

100M DIFF
100M DIFF

REFCLK_N

14M SE (3.3V)
NC

14M SE (1.8V)
NC

14M SE (1.1V)
vref

GFX_REFCLK

100M DIFF

100M DIFF

100M DIFF(IN/OUT)*

GPP_REFCLK

NC

100M DIFF

NC or 100M DIFF OUTPUT

GPPSB_REFCLK

100M DIFF

100M DIFF

100M DIFF

ICS9LPRS480BKLFT-GP

HT_REFCLKN

71.09480.A03
2nd = 71.00880.A03

REFCLK_P

PD#
RN29

3D3V_S5

3D3V_S0

8
7
6
5

1
2
3
4

PCI_REQ#5
RUNPWROK_D

PCI_REQ#5

17

RUNPWROK_D

34

DY
R151
10KR2J-3-GP

R148
10KR2J-3-GP

SEL_27
REF2

DY

DY

27MHz non-spreading singled clock on pin 5


and 27MHz spread clock on pin 6

0*

100MHz differential spreading SRC clock


REF0

SEL_SATA
REF1
SEL_HTT66
REF0

100MHz non-spreading differential SATA clock

0*

100MHz differential spreading SRC clock

66MHz 3.3V single ended HTT clock

0*

100MHz differential HTT clock

R150
10KR2J-3-GP

R147
10KR2J-3-GP

R146
10KR2J-3-GP

REF0
REF1
REF2

DY

* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.

DY

R144
10KR2J-3-GP

DY

SRN10KJ-6-GP

CPU_CLK(200MHz)

2
2

R145
150R2F-1-GP
1

CLK_NB_14M 12

1
R149
75R2F-2-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

OSC_14M_NB
RS780M 1.1V 158R/90.9R

Title

CLKGEN_ICS9LPRS480
Size

A3

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

of

43

1D2V_S0

DY
2

1
2

1
2

DY

1.5Amp

C445
SC180P50V2JN-1GP

DY

C425
SC180P50V2JN-1GP

C409
SCD22U6D3V2KX-1GP

DY

C413
SCD22U6D3V2KX-1GP

C416
SC4D7U6D3V5KX-3GP

C417
SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

Place close to socket


C434

U42A

D1
D2
D3
D4

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

HT LINK

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

11
11
11
11

HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1

J3
J2
J5
K5

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1

N1
P1
P3
P4

11
11
11
11

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

AE2
AE3
AE4
AE5

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

Y1
W1
Y4
Y3

HT_CPU_NB_CLK_H0 11
HT_CPU_NB_CLK_L0 11
HT_CPU_NB_CLK_H1 11
HT_CPU_NB_CLK_L1 11

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

R2
R3
T5
R5

HT_CPU_NB_CTL_H0 11
HT_CPU_NB_CTL_L0 11
HT_CPU_NB_CTL_H1 11
HT_CPU_NB_CTL_L1 11

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11

SKT-CPU638P-GP-U2

62.10055.111
2ND = 62.10055.251

SKT-BGA638H176

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU_HT_LINK I/F_(1/4)
Size

A3

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

of

43

U42C
MEM:DATA

Place near to CPU


1

DY
2

1
2

C158
SC180P50V2JN-1GP

C161
SC180P50V2JN-1GP

C153
SC180P50V2JN-1GP

C157
SC180P50V2JN-1GP

0D9V_S3

SC180P50V2JN-1GP

SC180P50V2JN-1GP

DY

C150

180P x 6
C160

C155
SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

DY
2

C156

0.22u X 2
C154
SC4D7U6D3V5KX-3GP

C165
SC4D7U6D3V5KX-3GP

DY
2

C169
SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

DY
2

C175

4.7u x 4

750 mA

CLOSE TO CPU
1D8V_S3

U42B

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

8,10 MEM_MA0_CS#0
8,10 MEM_MA0_CS#1

T20
U19
U20
V20

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

8,10 MEM_MA_CKE0
8,10 MEM_MA_CKE1

J22
J20

MA_CKE0
MA_CKE1

MEMVREF

W17

1
2

TP83 TPAD14-GP

MEM_RSVD_M2 1

TP120

RSVD_M2

B18

MB0_ODT0
MB0_ODT1
MB1_ODT0

W26
W23
Y26

MEM_MB0_ODT0 9,10
MEM_MB0_ODT1 9,10

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

V26
W25
U22

MEM_MB0_CS#0 9,10
MEM_MB0_CS#1 9,10

MB_CKE0
MB_CKE1

J25
H26

MEM_MB_CKE0 9,10
MEM_MB_CKE1 9,10

MEM_MB_CLK0_P
MEM_MB_CLK0_N
MEM_MB_CLK1_P
MEM_MB_CLK1_N

MEM_MA_CLK0_P
MEM_MA_CLK0_N
MEM_MA_CLK1_P
MEM_MA_CLK1_N

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4

P22
R22
A17
A18
AF18
AF17
R26
R25

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

MEM_MB_ADD0 9,10
MEM_MB_ADD1 9,10
MEM_MB_ADD2 9,10
MEM_MB_ADD3 9,10
MEM_MB_ADD4 9,10
MEM_MB_ADD5 9,10
MEM_MB_ADD6 9,10
MEM_MB_ADD7 9,10
MEM_MB_ADD8 9,10
MEM_MB_ADD9 9,10
MEM_MB_ADD10 9,10
MEM_MB_ADD11 9,10
MEM_MB_ADD12 9,10
MEM_MB_ADD13 9,10
MEM_MB_ADD14 9,10
MEM_MB_ADD15 9,10

8,10 MEM_MA_BANK0
8,10 MEM_MA_BANK1
8,10 MEM_MA_BANK2

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

MEM_MB_BANK0 9,10
MEM_MB_BANK1 9,10
MEM_MB_BANK2 9,10

8,10 MEM_MA_RAS#
8,10 MEM_MA_CAS#
8,10 MEM_MA_WE#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U25
U24
U23

MEM_MB_RAS# 9,10
MEM_MB_CAS# 9,10
MEM_MB_WE# 9,10

8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10
8,10

RN21

1
2

N19
N20
E16
F16
Y16
AA16
P19
P20

8
8
8
8

VREF_DDR_CLAW

C186

C183
SCD1U10V2KX-4GP

T19
V22
U21
V19

Y10 VTT_SENSE

SC1KP50V2KX-1GP

RSVD_M1

VTT_SENSE

4
3

SRN1KJ-7-GP

MEM_RSVD_M1

MEMZP
MEMZN

C189
SCD1U10V2KX-4GP

AF10
AE10
H16

8,10 MEM_MA0_ODT0
8,10 MEM_MA0_ODT1

MEMZP
MEMZN

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9

1D8V_S3

VTT1
VTT2
VTT3
VTT4

W10
AC10
AB10
AA10
A10

R273
39D2R2F-L-GP
1
2
1
2
R263
39D2R2F-L-GPTP119

D10
C10
B10
AD10

9
9
9
9

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

8
8
8
8
8
8
8
8

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

MEM_MA_DQS0_P
MEM_MA_DQS0_N
MEM_MA_DQS1_P
MEM_MA_DQS1_N
MEM_MA_DQS2_P
MEM_MA_DQS2_N
MEM_MA_DQS3_P
MEM_MA_DQS3_N
MEM_MA_DQS4_P
MEM_MA_DQS4_N
MEM_MA_DQS5_P
MEM_MA_DQS5_N
MEM_MA_DQS6_P
MEM_MA_DQS6_N
MEM_MA_DQS7_P
MEM_MA_DQS7_N

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MEM_MB_DATA0 9
MEM_MB_DATA1 9
MEM_MB_DATA2 9
MEM_MB_DATA3 9
MEM_MB_DATA4 9
MEM_MB_DATA5 9
MEM_MB_DATA6 9
MEM_MB_DATA7 9
MEM_MB_DATA8 9
MEM_MB_DATA9 9
MEM_MB_DATA10 9
MEM_MB_DATA11 9
MEM_MB_DATA12 9
MEM_MB_DATA13 9
MEM_MB_DATA14 9
MEM_MB_DATA15 9
MEM_MB_DATA16 9
MEM_MB_DATA17 9
MEM_MB_DATA18 9
MEM_MB_DATA19 9
MEM_MB_DATA20 9
MEM_MB_DATA21 9
MEM_MB_DATA22 9
MEM_MB_DATA23 9
MEM_MB_DATA24 9
MEM_MB_DATA25 9
MEM_MB_DATA26 9
MEM_MB_DATA27 9
MEM_MB_DATA28 9
MEM_MB_DATA29 9
MEM_MB_DATA30 9
MEM_MB_DATA31 9
MEM_MB_DATA32 9
MEM_MB_DATA33 9
MEM_MB_DATA34 9
MEM_MB_DATA35 9
MEM_MB_DATA36 9
MEM_MB_DATA37 9
MEM_MB_DATA38 9
MEM_MB_DATA39 9
MEM_MB_DATA40 9
MEM_MB_DATA41 9
MEM_MB_DATA42 9
MEM_MB_DATA43 9
MEM_MB_DATA44 9
MEM_MB_DATA45 9
MEM_MB_DATA46 9
MEM_MB_DATA47 9
MEM_MB_DATA48 9
MEM_MB_DATA49 9
MEM_MB_DATA50 9
MEM_MB_DATA51 9
MEM_MB_DATA52 9
MEM_MB_DATA53 9
MEM_MB_DATA54 9
MEM_MB_DATA55 9
MEM_MB_DATA56 9
MEM_MB_DATA57 9
MEM_MB_DATA58 9
MEM_MB_DATA59 9
MEM_MB_DATA60 9
MEM_MB_DATA61 9
MEM_MB_DATA62 9
MEM_MB_DATA63 9

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MEM_MB_DQS0_P
MEM_MB_DQS0_N
MEM_MB_DQS1_P
MEM_MB_DQS1_N
MEM_MB_DQS2_P
MEM_MB_DQS2_N
MEM_MB_DQS3_P
MEM_MB_DQS3_N
MEM_MB_DQS4_P
MEM_MB_DQS4_N
MEM_MB_DQS5_P
MEM_MB_DQS5_N
MEM_MB_DQS6_P
MEM_MB_DQS6_N
MEM_MB_DQS7_P
MEM_MB_DQS7_N

9
9
9
9
9
9
9
9

9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9

SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU_DDR_(2/4)
Size

A3

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

of

43

The Processor has


reached a preset
maximum operating
temperature. 100
I=Active HTC
O=FAN

8
7
6
5

1D8V_S0

C117

F6
E6

36 CPU_VDD1_RUN_FB_H
36 CPU_VDD1_RUN_FB_L

R248
300R2J-4-GP

-1

Y6
AB6

VDD1_FB_H
VDD1_FB_L

VDDNB_FB_H
VDDNB_FB_L

H6
G6

G10
AA9
AC9
AD9
AF9

DBRDY
TMS
TCK
TRST_L
TDI
TEST23

1
1

CPU_TEST18
CPU_TEST19

H10
G9

TEST18
TEST19

TP81
TP80

1CPU_TEST25_H
1CPU_TEST25_L

E9
E8

1
1
1

1 R242
2
0R0402-PAD

TDO

AB8
AF7
AE7
AE8
AC8
AF8

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27

CPU_TEST9

C2
AA6

TEST9
TEST6

A3
A5
B3
B5
C1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

8
7
6
5
36
36

CPU_DBREQ#

THERMTRIP#
PROCHOT#
CPU_MEMHOT#

1 R241
2
0R0402-PAD

CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L

E10 CPU_DBREQ#
AE9 CPU_TDO

36
36

LAYOUT: Route FBCLKOUT_H/L


differentially impedance 80

J7
H8

CPU_TEST28_H 1
CPU_TEST28_L 1

TP79
TP89

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14

1
1
1
1

TP74
TP75
TP72
TP76

TEST7
TEST10

C3
K8

TEST8

C4

TEST29_H
TEST29_L

C9
C8

CPU_TEST29H
CPU_TEST29L

1
1

TP73
TP82
B

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

H18
H19
AA7
D5
C5

36 CPU_PWRGD_SVID_REG

LDT_PWROK

HDT Connectors

SKT-CPU638P-GP-U2

HDT1

2ND = 84.03904.H11

DY
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

C482
SCD1U16V2ZY-2GP

Q18 DY
C
E
MMBT3904-3-GP
84.03904.T11

LDT_PWROK

1
2
R275 0R2J-2-GP

LDT_PWROK

R269
2K2R2J-2-GP

C489
SCD1U16V2ZY-2GP

1D8V_S3

3
5
7
9
11
13
15
17
19
21
23

DY

CPU_PWRGD_SVID_REG

Near CPU PIN


1

SA

PROCHOT#_SB 17

H_THERMDC 22
H_THERMDA
22
1DY 2
C145
SC100P50V2JN-3GP
CPU_VDDIO_SUS_FB_H 1
TP87
CPU_VDDIO_SUS_FB_L
1
TP88

TEST28_H
TEST28_L

TEST25_H
TEST25_L

CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27

LDT_PWROK_G

DBREQ_L

CPU_SVC
CPU_SVD

internal pull high 300 ohm

W9
Y9

TP93
TP90

TP182
TP85
TP183

AF6
AC7
AA8

VDDIO_FB_H
VDDIO_FB_L

AD7

THERMTRIP_L
PROCHOT_L
MEMHOT_L

A6
A4

VDD0_FB_H
VDD0_FB_L

CPU_TEST23

TP179

SVC
SVD

W7
W8

R270
DY 2K2R2J-2-GP

B 2

DY

RN14
SRN300J-1-GP

M11
W18

THERMDC
THERMDA

TP175

CPU_TEST21

RN62
SRN1KJ-7-GP

KEY1
KEY2

R277
10KR2J-3-GP

3
4

36 CPU_VDD0_RUN_FB_H
36 CPU_VDD0_RUN_FB_L

2
1D8V_S3

CLKIN_H
CLKIN_L

HT_REF0
HT_REF1

TP178

3D3V_S0

A9
A8

R6
P6

CPU_HTREF0
2
2 44D2R2F-GP CPU_HTREF1
44D2R2F-GP

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

VDDA1
VDDA2

SIC
SID
ALERT_L

1
R77 1
R71

R88
300R2J-4-GP

F8
F9

AF4
AF5
AE6

1 CPU_SIC
1 CPU_SID
1CPU_ALERT#

TPAD14-GP
TP172
TPAD14-GP
TP173
TPAD14-GP
TP174

1D2V_S0

U42D

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

LDT_PWROK
LDT_STP#_CPU
CPU_LDT_REQ#_CPU

For HDT DBG

TP84

1D8V_S3

1
2
3
4

CLKCPU_IN
CLKCPU#_IN

1D8V_S3

2
1

SCD22U16V3ZY-GP

DY

B7
A7
F10
C6

1
2
R258
0R0402-PAD

DY

1
2
R284
169R2F-GP
2
2SC3900P50V2KX-2GP
SC3900P50V2KX-2GP

1
C5011
C500
LDT_RST#_CPU
HDT_RST#

C137
SC10U10V5ZY-1GP

CPU_CLK
CPU_CLK#

C143

C132

DY

Cloce To CPU
3
3

C125

SC3300P50V2KX-1GP

12,17 ALLOW_LDTSTOP

2D5V_VDDA_S0

1 R69
2
0R0603-PAD

SC4D7U10V5ZY-3GP

17 CPU_LDT_STOP#

2D5V_S0

1 R256
2
LDT_RST#_CPU 12
0R0402-PAD
LDT_PWROK
1
2
R265 0R0402-PAD
1
2
LDT_STP#_CPU 12
R91
0R0402-PAD
CPU_LDT_REQ#_CPU
1
2
R253 0R0402-PAD

SC10U10V5ZY-1GP

17,43 CPU_PWRGD

IF 0 ohm IS NOT GOOD ENOUGH, TRY 68.00082.491

17,43 CPU_LDT_RST#

LYAOUT:ROUTE VDDA TRACE APPROX.


50mils WIDE(USE 2X25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

C366
SC100P50V2JN-3GP

1DY

1
2
3
4

RN15
SRN300J-1-GP

THERMTRIP#

1
2
1D8V_SUS_Q2

Q19
E
C
MMBT3904-3-GP
84.03904.T11 2ND

4
6
8
10
12
14
16
18
20
22
24
26

SMC-CONN26A-FP
HDT_RST#
<Core Design>

KBC_THERMTRIP# 22,31

= 84.03904.H11

CPU exceeds to 125

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU_Control&Debug_(3/4)
Size

A3

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

of

43

1
2

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

1
2

1
2

1
2

1
2

2
1
2

2
1

SC4D7U6D3V3KX-GP

DY

SC4D7U6D3V3KX-GP

DY

SCD22U6D3V2KX-1GP

DY

SCD22U6D3V2KX-1GP

SC10U6D3V5KX-1GP

DY

C208 C212 C185 C204 C187 C191

DY

DY

SC10U6D3V5KX-1GP

SKT-CPU638P-GP-U2

C180 C195 C203 C181 C179 C184 C182 C199 C207 C205 C188

SCD22U6D3V2KX-1GP

Bottom Side Decoupling

3A for VDDIO
1D8V_S3
Place near to CPU

SCD22U6D3V2KX-1GP

3A for VDDIO
1D8V_S3

DY

SCD01U50V2KX-1GP

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

DY

SCD01U50V2KX-1GP

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

DY

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

C144 C147 C118 C133 C151 C164 C162

SC180P50V2JN-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

Bottom Side Decoupling

SC10U6D3V5KX-1GP

C174

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

SC10U6D3V5KX-1GP

C196

K16
M16
P16
T16
V16

VCC_CORE_S0_1

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

SCD22U6D3V2KX-1GP

3A for VDDNB

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

SCD01U50V2KX-1GP

SC180P50V2JN-1GP

SCD01U50V2KX-1GP

SCD22U6D3V2KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

VDDNB

C173

DY

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

SC180P50V2JN-1GP

DY

C149 C114 C168 C146 C176 C170 C159

SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SC180P50V2JN-1GP

SC180P50V2JN-1GP

U42E

Bottom Side Decoupling

SC10U6D3V5KX-1GP

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

36A for VDD0&VDD1

VCC_CORE_S0_0

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

U42F

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

SKT-CPU638P-GP-U2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU_Power_(4/4)
Size
A3

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

of

43

DIMM1

110
115

MEM_MA0_CS#0 5,10
MEM_MA0_CS#1 5,10

CKE0
CKE1

79
80

MEM_MA_CKE0 5,10
MEM_MA_CKE1 5,10

CK0
CK0#

30
32

MEM_MA_CLK0_P 5
MEM_MA_CLK0_N 5

CK1
CK1#

164
166

MEM_MA_CLK1_P 5
MEM_MA_CLK1_N 5

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

10
26
52
67
130
147
170
185

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

50
69
83
120
163

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

DY

11
29
49
68
129
146
167
186

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

5
5
5
5
5
5
5
5

MEM_MA_DQS0_P
MEM_MA_DQS1_P
MEM_MA_DQS2_P
MEM_MA_DQS3_P
MEM_MA_DQS4_P
MEM_MA_DQS5_P
MEM_MA_DQS6_P
MEM_MA_DQS7_P

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

114
119

OTD0
OTD1

1
2

VREF
VSS
GND

GND

201

MH1

MH2

MH2

5,10 MEM_MA0_ODT0
5,10 MEM_MA0_ODT1

C256

SCD1U10V2KX-4GP

C261
SC2D2U6D3V3KX-GP

VREF_DDR_MEM

Place C2.2uF and 0.1uF <


500mils from DDR connector

202
MH1

1D8V_S3

PLACE CLOSE TO PROCESSOR


WITHIN 1.5 INCH

MEM_MA_CLK0_P
C241
SC1D5P50V2CN-1GP
MEM_MA_CLK0_N
MEM_MA_CLK1_P
C240
SC1D5P50V2CN-1GP
MEM_MA_CLK1_N

DDR_VREF
1D8V_S3

VREF_DDR_MEM

C533
SCD1U10V2KX-4GP

RN67
1
2

4
3

SRN1KJ-7-GP
2

MEM_MA_DQS0_N
MEM_MA_DQS1_N
MEM_MA_DQS2_N
MEM_MA_DQS3_N
MEM_MA_DQS4_N
MEM_MA_DQS5_N
MEM_MA_DQS6_N
MEM_MA_DQS7_N

DY

(A0)

5
5
5
5
5
5
5
5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C254
SCD1U10V2KX-4GP

NC#50
NC#69
NC#83
NC#120
NC#163/TEST

C253
SC2D2U6D3V3KX-GP

C539

198
200

SA0
SA1

3D3V_S0

VDDSPD

SMBD0_SB 3,9,18
SMBC0_SB 3,9,18

195
197
199

5
5
5
5
5
5
5
5

SCD1U10V2KX-4GP

SDA
SCL

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

CS0#
CS1#

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

MEM_MA_RAS# 5,10
MEM_MA_WE# 5,10
MEM_MA_CAS# 5,10

BA0
BA1

108
109
113

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

107
106

RAS#
WE#
CAS#

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

5,10 MEM_MA_BANK2
5,10 MEM_MA_BANK0
5,10 MEM_MA_BANK1

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

NORMAL TYPE

5,10
5,10
5,10
5,10
5,10
5,10
5,10
5,10
5,10
5,10
5,10
5,10
5,10
5,10
5,10
5,10

C257
SC1KP50V2KX-1GP

LAYOUT: Locate close to DIMM

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DDR2-200P-22-GP-U2

62.10017.A61
Title

2ND = 62.10017.A51

DDR_SO-DIMM SKT_1

HI 9.2mm

Size
Document Number
Custom

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

of

43

DIMM2

MEM_MB_DQS0_N
MEM_MB_DQS1_N
MEM_MB_DQS2_N
MEM_MB_DQS3_N
MEM_MB_DQS4_N
MEM_MB_DQS5_N
MEM_MB_DQS6_N
MEM_MB_DQS7_N

11
29
49
68
129
146
167
186

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

5
5
5
5
5
5
5
5

MEM_MB_DQS0_P
MEM_MB_DQS1_P
MEM_MB_DQS2_P
MEM_MB_DQS3_P
MEM_MB_DQS4_P
MEM_MB_DQS5_P
MEM_MB_DQS6_P
MEM_MB_DQS7_P

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

114
119

OTD0
OTD1

1
2

VREF
VSS

SC2D2U6D3V3KX-GP

C532

SCD1U10V2KX-4GP

C536

VREF_DDR_MEM

CS0#
CS1#

110
115

MEM_MB0_CS#0 5,10
MEM_MB0_CS#1 5,10

CKE0
CKE1

79
80

MEM_MB_CKE0 5,10
MEM_MB_CKE1 5,10

CK0
CK0#

30
32

MEM_MB_CLK0_P 5
MEM_MB_CLK0_N 5

CK1
CK1#

164
166

MEM_MB_CLK1_P 5
MEM_MB_CLK1_N 5

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

10
26
52
67
130
147
170
185

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

SA0
SA1

198
200

NC#50
NC#69
NC#83
NC#120
NC#163/TEST

50
69
83
120
163

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

81
82
87
88
95
96
103
104
111
112
117
118

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

DIMM2_SA1
1
R157

3D3V_S0

2
10KR2J-3-GP

C527 DY
SC2D2U6D3V3KX-GP

202

GND

GND

201

MH1

MH1

MH2

MH2

VDDSPD

SMBD0_SB 3,8,18
SMBC0_SB 3,8,18

C530

DY SCD1U10V2KX-4GP
2

195
197
199

5
5
5
5
5
5
5
5

SDA
SCL

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

5
5
5
5
5
5
5
5

5,10 MEM_MB0_ODT0
5,10 MEM_MB0_ODT1
A

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

MEM_MB_RAS# 5,10
MEM_MB_WE# 5,10
MEM_MB_CAS# 5,10

(A2)
1D8V_S3

PLACE CLOSE TO PROCESSOR


WITHIN 1.5 INCH
C

MEM_MB_CLK0_P
1

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63

BA0
BA1

108
109
113

C266
SC1D5P50V2CN-1GP

5
5
5
5
5
5
5
5
5
5

107
106

RAS#
WE#
CAS#

MEM_MB_CLK0_N

5,10 MEM_MB_BANK2
5,10 MEM_MB_BANK0
5,10 MEM_MB_BANK1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

C265
SC1D5P50V2CN-1GP

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

REVERSE TYPE

5,10 MEM_MB_ADD0
5,10 MEM_MB_ADD1
5,10 MEM_MB_ADD2
5,10 MEM_MB_ADD3
5,10 MEM_MB_ADD4
5,10 MEM_MB_ADD5
5,10 MEM_MB_ADD6
5,10 MEM_MB_ADD7
5,10 MEM_MB_ADD8
5,10 MEM_MB_ADD9
5,10 MEM_MB_ADD10
5,10 MEM_MB_ADD11
5,10 MEM_MB_ADD12
5,10 MEM_MB_ADD13
5,10 MEM_MB_ADD14
5,10 MEM_MB_ADD15

MEM_MB_CLK1_N

MEM_MB_CLK1_P

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SKT-SODIMM20020U3GP

62.10017.661

Title

2ND = 62.10017.A41

Place C2.2uF and 0.1uF <


500mils from DDR connector

DDR_SO-DIMM SKT_2
Size
Document Number
Custom

LOW 5.2 mm

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

of

-1
43

Decoupling Capacitor

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

SC10P50V2JN-4GP

1
2
3
4

SRN47J-4-GP
RN37
8
7
6
5

MEM_MA0_CS#0 5,8
MEM_MA_RAS# 5,8
MEM_MA0_ODT0 5,8
MEM_MA_ADD13 5,8

1
2
3
4

MEM_MB_BANK0 5,9
MEM_MB_ADD10 5,9
MEM_MB_ADD1 5,9
MEM_MB_ADD3 5,9

C263

1
2
3
4

MEM_MA_ADD15 5,8
MEM_MA_ADD14 5,8
MEM_MA_ADD7 5,8
MEM_MA_ADD11 5,8

SRN47J-4-GP
RN41
8
7
6
5

C262

1
2
3
4

SRN47J-4-GP
RN38
8
7
6
5

MEM_MB_CKE1 5,9
MEM_MB_ADD15 5,9
MEM_MB_ADD14 5,9
MEM_MB_ADD7 5,9

C573

DY
2

1
2
3
4

SRN47J-4-GP
RN44
8
7
6
5

1
2
3
4

SRN47J-4-GP
RN34
8
7
6
5

C575

MEM_MB_ADD9 5,9
MEM_MB_ADD12 5,9
MEM_MB_BANK2 5,9
MEM_MB_CKE0 5,9

SRN47J-4-GP
RN39
8
7
6
5

C578

1
2
3
4

MEM_MA_ADD12 5,8
MEM_MA_ADD9 5,8
MEM_MA_BANK2 5,8
MEM_MA_CKE0 5,8

C577

SRN47J-4-GP
RN32
8
7
6
5

1
2
3
4

C574

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to 0D9V_S3

SCD1U16V2ZY-2GP

MEM_MB_RAS# 5,9
MEM_MB0_CS#0 5,9
MEM_MB0_ODT0 5,9
MEM_MB_ADD13 5,9

SCD1U16V2ZY-2GP

SRN47J-4-GP
RN46
8
7
6
5

SCD1U16V2ZY-2GP

1
2
3
4

SC2D2U6D3V3KX-GP

MEM_MA_ADD4 5,8
MEM_MA_ADD2 5,8
MEM_MA_BANK1 5,8
MEM_MA_ADD0 5,8

SC2D2U6D3V3KX-GP

SRN47J-4-GP
RN36
8
7
6
5

SC2D2U6D3V3KX-GP

1
2
3
4

Place these Caps near DM2


1

C239

1
2

DY

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to 0D9V_S3

SC180P50V2JN-1GP

C236
SC180P50V2JN-1GP

C238
SCD01U50V2KX-1GP

C531
SCD01U50V2KX-1GP

C235
SC2D2U6D3V3KX-GP

0D9V_S3

C529
SC2D2U6D3V3KX-GP

MEM_MB0_CS#1 5,9
MEM_MB0_ODT1 5,9
MEM_MB_CAS# 5,9
MEM_MB_WE# 5,9

SC2D2U6D3V3KX-GP

SRN47J-4-GP
RN42
8
7
6
5

C528

C237

1D8V_S3

SC2D2U6D3V3KX-GP

1D8V_S3

Place these Caps near PARALLEL TERMINATION


1
2
1

C225

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1
2

1
2
1

C251

DY

C223

DY

SCD1U16V2ZY-2GP

1
2
1

C245

SCD1U16V2ZY-2GP

2
1

C247
SCD1U16V2ZY-2GP

C222
SCD1U16V2ZY-2GP

DY

C249

SCD1U16V2ZY-2GP

C248

DY

SCD1U16V2ZY-2GP

C271
SCD1U16V2ZY-2GP

DY

C229

SCD1U16V2ZY-2GP

C270
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C250

SCD1U16V2ZY-2GP

C252

DY

SCD1U16V2ZY-2GP

C226

DY

C227
SCD1U16V2ZY-2GP

C274
SCD1U16V2ZY-2GP

DY

C268
SCD1U16V2ZY-2GP

Do not share the Term resistor between


the DDR addess and Control Signals.

C246
SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

SRN47J-4-GP

SRN47J-4-GP

C258

1D8V_S3

SC2D2U6D3V3KX-GP

MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD8
MEM_MA_CKE1

MEM_MA_BANK0 5,8
MEM_MA_ADD10 5,8
MEM_MA_ADD3 5,8
MEM_MA_ADD1 5,8

C221

Place these Caps near DM1

SRN47J-4-GP
RN33
8
7
6
5

C233

SC10P50V2JN-4GP

MEM_MB_ADD6 5,9
MEM_MB_ADD2 5,9
MEM_MB_ADD0 5,9
MEM_MB_BANK1 5,9

C228

SC1KP50V2KX-1GP

SRN47J-4-GP
RN45
8
7
6
5

DY

SC1KP50V2KX-1GP

1
2
3
4

C224

MEM_MB_ADD4 5,9
MEM_MB_ADD11 5,9
MEM_MB_ADD5 5,9
MEM_MB_ADD8 5,9

1
2
3
4

5,8
5,8
5,8
5,8

C272

SC1KP50V2KX-1GP

8
7
6
5

C244

SC1KP50V2KX-1GP

1
2
3
4

C269

DY

SCD1U16V2ZY-2GP

MEM_MA0_ODT1 5,8
MEM_MA0_CS#1 5,8
MEM_MA_WE# 5,8
MEM_MA_CAS# 5,8

C242

SCD1U16V2ZY-2GP

RN40

8
7
6
5

C259

SCD1U16V2ZY-2GP

1
2
3
4

C260

SCD1U16V2ZY-2GP

0D9V_S3
RN35

C243

SCD1U16V2ZY-2GP

Put decap near power(0.9V) and pull-up resistor


0D9V_S3

Put decap near power(0.9V) and pull-up resistor

SCD1U16V2ZY-2GP

PARALLEL TERMINATION

C273
SCD1U16V2ZY-2GP

0D9V_S3

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR_DAMPING & TERMINATION


Size
A3

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

10

of

43

U31A

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15

4
4
4
4

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_NB_CPU_CLK_H0 4
HT_NB_CPU_CLK_L0 4
HT_NB_CPU_CLK_H1 4
HT_NB_CPU_CLK_L1 4

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_NB_CPU_CTL_H0 4
HT_NB_CPU_CTL_L0 4
HT_NB_CPU_CTL_H1 4
HT_NB_CPU_CTL_L1 4

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

PCE_CALRP
PCE_CALRN

AC8
AB8

HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

4
4
4
4

HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

4
4
4
4

HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1

M22
M23
R21
R20
C23
A24

2 R216
301R2F-GP

HT_RXCALP
HT_RXCALN

Place < 100mils from pin C23 and A24

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HYPER TRANSPORT CPU I/F

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

HT_TXCALP
HT_TXCALN

4
4
4
4
4
4
4
4
4
4
4
4

Placement: close RS780


2 R215
301R2F-GP

Place < 100mils from pin B25 and B24

RS780M-GP-U2
U31B

26
26
28
28
28
28

LAN
MINICARD
NEW CARD

PCIE_RXP1
PCIE_RXN1
PCIE_RXP2
PCIE_RXN2
PCIE_RXP5
PCIE_RXN5

TPAD14-GP
TP16
TPAD14-GP
TP15
A

A-LINK

17
17
17
17
17
17
17
17

GPP_RX5P
GPP_RX5N

ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
ALINK_NBRX_SBTX_P1
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
ALINK_NBRX_SBTX_P3
ALINK_NBRX_SBTX_N3

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PART 2 OF 6

PCIE I/F GFX

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

PCIE I/F GPP

PCIE I/F SB

RS780M-GP-U2

RS780M Display Port Support(muxed on GFX)


DP0 GFX_TX0,TX1,TX2,TX3,AUX0,HPD0
DP1 GFX_TX4,TX5,TX6,TX7,AUX1,HPD1

TXP1
TXN1
TXP2
TXN2
TXP5
TXN5

C342
C341
C345
C344
C343
C340

1
1
1
1
1
1

2
2
2
2
2
2

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

GPP_TX5P
GPP_TX5N

26
26
28
28
28
28

LAN
MINICARD
NEW CARD

TP149 TPAD14-GP
TP154 TPAD14-GP

ALINK_NBTX_SBRX_P0
ALINK_NBTX_SBRX_N0
ALINK_NBTX_SBRX_P1
ALINK_NBTX_SBRX_N1
ALINK_NBTX_SBRX_P2
ALINK_NBTX_SBRX_N2
ALINK_NBTX_SBRX_P3
ALINK_NBTX_SBRX_N3
PCE_PCAL
PCE_NCAL

PCIE_TXP1
PCIE_TXN1
PCIE_TXP2
PCIE_TXN2
PCIE_TXP5
PCIE_TXN5

C367
C374
C362
C365
C354
C357
C348
C352

1
R196 1
R19

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

2
2 1K27R2F-L-GP
2KR2F-3-GP

ALINK_NBTX_C_SBRX_P0
ALINK_NBTX_C_SBRX_N0
ALINK_NBTX_C_SBRX_P1
ALINK_NBTX_C_SBRX_N1
ALINK_NBTX_C_SBRX_P2
ALINK_NBTX_C_SBRX_N2
ALINK_NBTX_C_SBRX_P3
ALINK_NBTX_C_SBRX_N3

17
17
17
17
17
17
17
17

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

1D1V_S0
Size
A3

Place < 100mils from pin AC8 and AB8

ATi-RS780M_HT LINK&PCIe(1/3)

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

11

of

43

3D3V_S0

3D3V_S0

L2
1
2
FCM1608CF-221T02-GP

STRAP_DEBUG_BUS_GPIO_ENABLEb

SC1U10V2KX-1GP

8
7
6
5

C27
DYSCD1U10V2KX-4GP

RN1
SRN3K3J-1-GP

220ohm 200mA
2ND = 68.00084.A81 C41

3D3V_S0_AVDD

Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC#)


:Disable
0 : Enable

*1

RS780: Enables Side port memory ( RS780 use HSYNC#)

DAC_HSYNC
DAC_VSYNC
DAC_SCL
DAC_SDA

G14

DAC_RSET

A12
D14
B12

PLLVDD
PLLVDD18
PLLVSS

VDDA18HTPLL

H17

VDDA18HTPLL

VDDA18PCIEPLL

D7
E7

VDDA18PCIEPLL1
VDDA18PCIEPLL2

D8
A10
C10
C12

SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP

3 CLK_NBHT_CLK
3 CLK_NBHT_CLK#

C25
C24

HT_REFCLKP
HT_REFCLKN

CLK_NB_14M

E11
F11

REFCLK_P/OSCIN
REFCLK_N

GMCH_BLUE
15 GMCH_HSYNC
15 GMCH_VSYNC
15 GMCH_DDCCLK
15 GMCH_DDCDATA

1 R23
2DAC_RSET
768R2F-1-GP

L3
1
2
FCM1608CF-221T02-GP

220ohm 200mA
2ND = 68.00084.A81 C44

DY

SB

C56

DY

C613
SC47U6D3V5MX-1-GP

220ohm 200mA
2ND = 68.00084.A81

L7
1
2
FCM1608CF-221T02-GP
SC1U10V2KX-1GP

1D8V_S0

DY

1D8V_S0_PLVDD18
C39

DY SCD1U10V2KX-4GP

SC1U10V2KX-1GP

C612
SC47U6D3V5MX-1-GP

1D1V_S0_PLLVDD

1 R195
2 NB_ALLOW_LDTSTOP
0R0402-PAD

1D1V_S0

6,17 ALLOW_LDTSTOP

NB_LDT_STOP#
1 R87
2
0R0402-PAD

SYSREST#
C57

6 LDT_STP#_CPU

18,34 NB_PWRGD

SCD1U10V2KX-4GP

1D1V_S0
RN5

ENABLE External CLK GEN


1D8V_S0

1
2

4
3

3 CLK_NB_GFX
3 CLK_NB_GFX#

SRN1KJ-7-GP

VDDA18HTPLL

L9
1
2
FCM1608CF-221T02-GP

220ohm 200mA
2ND = 68.00084.A81 C75 DY

TPAD14-GP
TP151
TPAD14-GP
TP153

NB_REFCLK_N
CLK_NB_GFX
CLK_NB_GFX#

T2
T1

GFX_REFCLKP
GFX_REFCLKN

CLK_NBGPP_CLK
CLK_NBGPP_CLK#

U1
U2

GPP_REFCLKP
GPP_REFCLKN

V4
V3

GPPSB_REFCLKP
GPPSB_REFCLKN

B9
A9
B8
A8
B7
A7

I2C_CLK
I2C_DATA
DDC_CLK0/AUX0P
DDC_DATA0/AUX0N
DDC_DATA0/AUX0N DDC_CLK0/AUX0P
DDC_CLK1/AUX1P
DDC_DATA1/AUX1N

3 CLK_NB_GPPSB
3 CLK_NB_GPPSB#

SC1U10V2KX-1GP

SB
C58
SCD1U10V2KX-4GP

NB_LDT_STOP#
NB_ALLOW_LDTSTOP

14 CLK_DDC_EDID
14 DAT_DDC_EDID
1D8V_S0
L1
C21

STRP_DATA

DY SCD1U10V2KX-4GP

B10

STRP_DATA
RESERVED

VCC_NB

1.0V 1.1V

*1

TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN

B16
A16
D16
D17

VDDLTP18
VSSLTP18

A13
B13

VDDLT18_1
VDDLT18_2
VDDLT33_1
VDDLT33_2

A15
B15
A14
B14

VSSLT1
VSSLT2
VSSLT3
VSSLT4
VSSLT5
VSSLT6
VSSLT7

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON
LVDS_BLON
LVDS_ENA_BL

GMCH_TXACLK+
GMCH_TXACLKGMCH_TXBCLK+
GMCH_TXBCLK-

14
14
14
14

C379
SC1U10V2KX-1GP

RS780_AUX_CAL

C8

R18
150R2F-1-GP

1D8V_S0
L20
1
2
FCM1608CF-221T02-GP
C378
SCD1U10V2KX-4GP

1D8V_S0_VDDLP18

2ND = 68.00084.A81

DY

L4
1
2
PBY201209T-221Y-N-GP

1D8V_S0_VDDLT18
C50
SC4D7U6D3V3KX-GP

E9
GMCH_BL_ON
F7
G12 LVDS_ENA_BL

DY C47

2ND = 68.00216.161

SCD1U10V2KX-4GP

GMCH_LCDVDD_ON
GMCH_BL_ON 31
TP20 TPAD14-GP

RN4

2
1

14

3
4

R24

TMDS_HPD
HPD

D9
D10

NB_DVI_HPD

SUS_STAT#

D12

SUS_STAT#

THERMALDIODE_P
THERMALDIODE_N

AE8
AD8

TESTMODE

TP17
TP18

2
R15
G792_DXP3_1
G792_DXN3_1

TPAD14-GP
TPAD14-GP

1
10KR2J-3-GP

SA

3D3V_S0

G792_DXP3 22
G792_DXN3 22

1
G8
G6
GAP-CLOSE
GAP-CLOSE

D13 TESTMODE_NB

AUX_CAL

2 100KR2J-1-GP

DY

STRP_DATA

14
14
14
14
14
14

SRN4K7J-8-GP

MIS.

G11

GPIO MODE

GMCH_TXBOUT0+
GMCH_TXBOUT0GMCH_TXBOUT1+
GMCH_TXBOUT1GMCH_TXBOUT2+
GMCH_TXBOUT2-

R26
1K8R2F-GP

C22
SC1U10V2KX-1GP

220ohm 200mA
2ND = 68.00084.A81

1
2 VDDA18PCIEPLL
FCM1608CF-221T02-GP

NB_DVI_CLK
NB_DVI_DATA

TPAD14-GP
TP155
TPAD14-GP
TP14

B18
A18
A17
B17
D20
D21
D18
D19

15

TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

A11
B11
F8
E8

15 GMCH_GREEN

14
14
14
14
14
14

RED
REDb
GREEN
GREENb
BLUE
BLUEb

GMCH_TXAOUT0+
GMCH_TXAOUT0GMCH_TXAOUT1+
GMCH_TXAOUT1GMCH_TXAOUT2+
GMCH_TXAOUT2-

G18
G17
E18
F18
E19
F19

GMCH_RED

A22
B22
A21
B21
B20
A20
A19
B19

15

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

C_Pr
Y
COMP_Pb

PART 3 OF 6

E17
F17
F15

1D8V_S0_AVDDQ

AVDD1
AVDD2
AVDDDI
AVSSDI
AVDDQ
AVSSQ

R28
140R2F-GP

R31
150R2F-1-GP

150R2F-1-GP

GMCH_RED
R30

F12
E12
F14
G15
H15
H14

CRT/TVOUT

GMCH_GREEN

C52
SCD1U10V2KX-4GP

ST100U6D3VBM-5GP

GMCH_BLUE

U31C

220ohm 200mA
2ND = 68.00084.A81 C49

SC1U10V2KX-1GP

SA

0 : Enable

Selects Loading of STRAPS From EEPROM


Bypass the loading of EEPROM straps and use Hardware Default Values
*10 :: I2C
Master can load strap values from EEPROM if connected,
or use default values if not connected

PLL PWR
LVTM

TC1

:Disable

SUS_STAT#

C54
SCD1U10V2KX-4GP

CLOCKs PM

SA

R29
1
2
FCM1608CF-221T02-GP

Close to NB ball

1D8V_S0

DY

C364
SC330P50V2KX-3GP

GMCH_VSYNC
GMCH_HSYNC

*1

1D8V_S0_AVDDDI

R27 2
1
0R0603-PAD
C48
SC1U10V2KX-1GP

SYSREST#

17,26,31 PLT_RST1#

1
2
3
4

1D8V_S0

DY

1 R186
2
0R0402-PAD
1

0R2J-2-GP

6 LDT_RST#_CPU

R190
1

RS780M-GP-U2

3D3V_S0

R17

<Core Design>

DY 2K2R2J-2-GP

Wistron Corporation

STRP_DATA

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

ATi-RS780M_LVDS&CRT_(2/3)

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

12

of

43

U31F

1
2

C16

C15

C28

DY

C8

DY
2

1
2

C45

1
2

1
2

C46

1 R199
2
0R0603-PAD

3D3V_S0

+3.3V_RUN_VDD33

1
C18
SCD1U10V2KX-4GP

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

1 R11
2
0R0603-PAD
1

C9

DY

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

DY

PART 6/6

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

RS780M-GP-U2

C19
SCD1U10V2KX-4GP

1
2

AE10
AA11
Y11
AD10
AB10
AC10
H11
H12

C38

VDD_MEM

RS780M-GP-U2

SC1U10V2KX-1GP

VDD33_1
VDD33_2

C42

1
2
1
2

2
1
2
1

1
2

1
2
1
2

1
2
1

1
2

POWER

1
2

1
2

2
1
2
1
2
1
2

C381

VDD18_1
VDD18_2
VDD18_MEM1
VDD18_MEM2

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

SC10U6D3V5KX-1GP

F9
G9
AE11
AD11

+1.8V_RUN_VDD18_MEM

VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6

1D1V_S0

RS780M: 1V ~ 1.1V, check PWR team

SC10U6D3V5KX-1GP

SCD1U10V2KX-4GP

DY

+NB_VCORE

Per check list (Rev 0.02)

SCD1U10V2KX-4GP

C29

C17
SC4D7U6D3V3KX-GP

7A per ANT Rev1.1, Page3

SCD1U10V2KX-4GP

C35

SCD1U10V2KX-4GP

SC1U10V2KX-1GP

1 R202
2
0R0603-PAD

DY

C30

SCD1U10V2KX-4GP

C34

C26

DY

SCD1U10V2KX-4GP

C33

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

C20

SCD1U10V2KX-4GP

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

C12

DY

SCD1U10V2KX-4GP

C59

DY

+1.8V_RUN_VDDA18PCIE
SCD1U10V2KX-4GP

C383

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17

SCD1U10V2KX-4GP

C40
SCD1U10V2KX-4GP

1D8V_S0

C32
SC4D7U6D3V3KX-GP

2ND = 68.00216.161

SC4D7U6D3V3KX-GP

220 ohm @ 100MHz,2A

80mil Width

SCD1U10V2KX-4GP

L5

DY

SCD1U10V2KX-4GP

1D8V_S0
C

1
2
PBY201209T-221Y-N-GP

C70
SCD1U10V2KX-4GP

2ND = 68.00216.161

DY

300mil Width

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

SCD1U10V2KX-4GP

C387
SC4D7U6D3V3KX-GP

220 ohm @ 100MHz,2A

+1.2V_RUN_VDDHTTX
C62
C55

SCD1U10V2KX-4GP

L21
1
2
PBY201209T-221Y-N-GP

DY

SCD1U10V2KX-4GP

1D2V_S0

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

2ND = 68.00216.161

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

SC1U10V2KX-1GP

C71

220 ohm @ 100MHz,2A

H18
G19
F20
E21
D22
B23
A23

PART 5/6

SC1U10V2KX-1GP

1
2
PBY201209T-221Y-N-GP

+1.1V_RUN_VDDHTRX
C65
C64
C63

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

SCD1U10V2KX-4GP

0.45A per ANT Rev1.1, Page3

L8

J17
K16
L16
M16
P16
R16
T16

SCD1U10V2KX-4GP

1D1V_S0

DY

1D1V_S0

U31E
SCD1U10V2KX-4GP

DY

SCD1U10V2KX-4GP

2ND = 68.00216.161

+1.1V_RUN_VDDHT
C60
C53
SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

220 ohm @ 100MHz,2A

C61

C51

L6
1
2
PBY201209T-221Y-N-GP

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

GROUND

0.6A per ANT Rev1.1, Page3

1D1V_S0

U31D

AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13

AD16
AE17
AD17

MEM_BA0
MEM_BA1
MEM_BA2

W12
Y12
AD18
AB13
AB18
V14

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

V15
W14

MEM_CKP
MEM_CKN

SBD_MEM/DVO_I/F

PAR 4 OF 6
MEM_DQ0/DVO_VSYNC
MEM_DQ1/DVO_HSYNC
MEM_DQ2/DVO_DE
MEM_DQ3/DVO_D0
MEM_DQ4
MEM_DQ5/DVO_D1
MEM_DQ6/DVO_D2
MEM_DQ7/DVO_D4
MEM_DQ8/DVO_D3
MEM_DQ9/DVO_D5
MEM_DQ10/DVO_D6
MEM_DQ11/DVO_D7
MEM_DQ12
MEM_DQ13/DVO_D9
MEM_DQ14/DVO_D10
MEM_DQ15/DVO_D11

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

MEM_DQS0P/DVO_IDCKP
MEM_DQS0N/DVO_IDCKN
MEM_DQS1P
MEM_DQS1N

Y17
W18
AD20
AE21

MEM_DM0
MEM_DM1/DVO_D8

W17
AE19

IOPLLVDD18
IOPLLVDD

AE23
AE24

IOPLLVSS

AD23

Wistron Corporation

MEM_VREF

AE18

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

AE12
AD12

MEM_COMP_P and MEM_COMP_N trace


width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

MEM_COMPP
MEM_COMPN

1D8V_S0

1 R210
2
0R0402-PAD

+1.8V_IOPLLVDD18

1D1V_S0

1 R211
2
0R0402-PAD

<Core Design>

+1.1V_IOPLLVDD

RS780M-GP-U2
Title

ATi-RS780M_Side Port&PWR&GND(3/3)

Size
A3

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

13

of

43

LCD/INVERTER/CCD CONN

12 CLK_DDC_EDID
12 DAT_DDC_EDID

CCD_PWR
BLON_OUT

R177
1

BRIGHTNESS_CN
2BLON_OUT_1

33R2J-2-GP
DCBATOUT
F1

Symbol

Vin

Vin

Brightness

PH at P22
U2

BLON

GND

GND

CCD Pin
Pin

ACES-CONN40A-2GP

SCD1U50V3ZY-GP

SC10U25V6KX-1GP

Pin

GMCH_TXBCLK+ 12
GMCH_TXBCLK- 12
GMCH_TXBOUT2+ 12
GMCH_TXBOUT2- 12
GMCH_TXBOUT1+ 12
GMCH_TXBOUT1- 12
GMCH_TXBOUT0+ 12
GMCH_TXBOUT0- 12
GMCH_TXACLK+ 12
GMCH_TXACLK- 12
GMCH_TXAOUT2+ 12
GMCH_TXAOUT2- 12
GMCH_TXAOUT1+ 12
GMCH_TXAOUT1- 12
GMCH_TXAOUT0+ 12
GMCH_TXAOUT0- 12

OUT

VDD

LID_CLOSE#

LID_CLOSE# 22,31

GND
EC11
SCD1U16V2ZY-2GP

ME268-002-GP

DY

74.00268.07B
EC12
SCD1U16V2ZY-2GP

69.50007.A41
DY EC76

C306

PWR_INVERTER

3D3V_AUX_S5

Inverter Pin

GMCH_TXBCLK+
GMCH_TXBCLKGMCH_TXBOUT2+
GMCH_TXBOUT2GMCH_TXBOUT1+
GMCH_TXBOUT1GMCH_TXBOUT0+
GMCH_TXBOUT0GMCH_TXACLK+
GMCH_TXACLKGMCH_TXAOUT2+
GMCH_TXAOUT2GMCH_TXAOUT1+
GMCH_TXAOUT1GMCH_TXAOUT0+
GMCH_TXAOUT0-

POLYSW-1D1A24V-1-GP

Cover Up Switch

SC10U10V5ZY-1GP

CLK_DDC_EDID
DAT_DDC_EDID

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

C4
DY SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP

3D3V_S0

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

C5

USBPP8_R

DY

C6

R180 1
2
0R0402-PAD

USBPP8

CCD_PWR

2nd: 20.F1048.040
3nd: 20.F1084.040

USB-

USB+

74.00268.A7B

GND

74.00268.C7B

GND

BRIGHTNESS_CN

R178 1
2
0R0402-PAD

BRIGHTNESS 31

BLON_OUT
C312

1
2

RN52
SRN4K7J-8-GP

C308

DY

SC100P50V2JN-3GP

SC100P50V2JN-3GP

DY
4
3

BLON_OUT 16,31

3D3V_S0

Symbol

20.F0993.040

18

41
2

USBPN8_R

LCD1

R179 1
2
0R0402-PAD

USBPN8

18
D

LCDVDD

CLK_DDC_EDID
DAT_DDC_EDID
3D3V_S0
LCDVDD
U21

SC4D7U6D3V3KX-GP

DY

IN#1
OUT
EN
GND

GND
IN#8
IN#7
IN#6
IN#5

9
8
7
6
5

C322
SCD1U16V2ZY-2GP

C320

GMCH_LCDVDD_ON

12 GMCH_LCDVDD_ON

1
2
3
4

G5281RC1U-GP

74.05281.093

Layout 40 mil

C319
SC4D7U6D3V3KX-GP

F3

3D3V_S0

FUSE-1D1A6V-8GP

69.41101.021

C314
SC4D7U10V5ZY-3GP

C315

<Core Design>

DY SCD1U16V2ZY-2GP

CCD_PWR

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

LCD CONN

Document Number

A3
Date: Friday, August 22, 2008
5

Rev

Cathedral Peak 2A
Sheet
1

14

of

-1
43

Layout Note:
Place these resistors
close to the CRT-out
connector
12

Ferrite bead impedance: 10 ohm@100MHz


L17

GMCH_RED

CRT_R

2
FCB1608CF-GP

68.00230.021
L16

Hsync & Vsync level shift

12 GMCH_GREEN

CRT_G

2
FCB1608CF-GP

5V_S0

68.00230.021

C325
SCD1U16V2ZY-2GP

14

C318

CRT_HSYNC1

3
U22A
TSAHCT125PW-GP

12 GMCH_HSYNC

14

C321

1
2

1
2

DY
2

1
2

1
1
2
3
4

RN2
SRN150F-1-GP

DY

CRT_B
C324

SC6D8P50V2DN-GP

68.00230.021

SC6D8P50V2DN-GP

2
FCB1608CF-GP

EC77

SC6D8P50V2DN-GP

DY

EC78
SC3P50V2CN-1-GP

SC3P50V2CN-1-GP

8
7
6
5

EC79

SC3P50V2CN-1-GP

GMCH_BLUE

L15
12

5V_S0

Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

BAV99PT-GP-U
D16
CRT_G 3

CRT_VSYNC1

DY
2

2
1

C316
SC18P50V2JN-1-GP

DY

DY

C317
SC18P50V2JN-1-GP

CRT_R 3

12 GMCH_VSYNC
D17

U22B
TSAHCT125PW-GP

DY
1

BAV99PT-GP-U
D15
CRT_B 3

DY
1

BAV99PT-GP-U

DDC_CLK & DATA level shift

5V_S0

3D3V_S0

5V_CRT_S0

3D3V_S0

CRT I/F & CONNECTOR

D14
BAS16-1-GP

CRT1

16
F2

CRT_B

7
12
8
13
9
14
10
15

4
CRT_IN#_R

CRT_VSYNC1

DAT_DDC1_5

5V_CRT_S0

CRT_HSYNC1

SCD01U16V2KX-3GP
12 GMCH_DDCDATA

8
7
6
5

84.27002.F3F

12 GMCH_DDCCLK

2nd:
3nd:

CRT_IN#_R
DAT_DDC1_5

2N7002EDW-GP

SA

20.20378.015

RN50
SRN10KJ-6-GP

CLK_DDC1_5

R176
1

CRT_DEC#

<Core Design>

5V_S0
CRT_IN#_R

D13

2
1

470R2J-2-GP

DY C304

DY

SC220P50V2JN-3GP

31

1
2

1
2

SC100P50V2JN-3GP

DY

CLK_DDC1_5
DAT_DDC1_5
C309
C313
DY SC100P50V2JN-3GP

5V_CRT_DDC

Q13
C307

CLK_DDC1_5

VIDEO-15-42-GP-U
C311

69.50007.691

CRT_VSYNC1

17

CRT_HSYNC1

SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

C310

FUSE-1D1A6V-4GP-U

RN51
SRN2K2J-1-GP

1
2
3
4

CRT_G

6
11

3
4

2
1

CRT_R

C305
SC100P50V2JN-3GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY

BAV99PT-GP-U
1

Title
Size

CRT Connector

Document Number

Rev

Cathedral Peak 2A
Date: Friday, August 22, 2008
5

Sheet
1

15

of

-1
43

Q25

E
R2
PDTC143ZU-GP-U

3D3V_S5
LED2

STDBY_LED

STDBY_LED#_BD

R1

FRONT_PWRLED#_R 3
STDBY_LED#_R

DC_BATFULL#

R1

Q24
31 CHARGE_LED

CHARGE_LED#

R1

R361
1
2
56R2J-4-GP
R362
1
2
56R2J-4-GP

DC_BATFULL#_R

SRN10KJ-5-GP

R2
1
R1
1

2
56R2J-4-GP

FRONT_PWRLED#_R_1 3

2
56R2J-4-GP

STDBY_LED#_R_1 4

83.00195.I70

LED-GY-14-GP

83.00195.I70

Q8

R58

WLAN_LED#_1

R2

WLAN_LED#

1
2
33R2J-2-GP

R1

3D3V_S0

RN8

PDTA143ZU-GP

84.00143.C1K

1
2
3
4

Q7
2N7002E-1-GP

84.2N702.D31

.
. .
.
31 WLAN_TEST_LED

3D3V_S0

BT_LED#

EC52 SCD1U16V2ZY-2GP
1
2

R2
PDTC143ZU-GP-U

Q4

84.00143.E1K

R1

31

NUM_LED

E Power Button

NUM_LED#_R
LAUNCHCN1
16

E
R2
PDTC143ZU-GP-U
84.00143.E1K

R3
E-BUTTON#_CN_1 1

31

E-BUTTON#

CAP_LED

E-BUTTON# 31

DY EC3
2

5V_S0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

R1

CAP_LED#_R

R2
PDTC143ZU-GP-U
84.00143.E1K

470R2J-2-GP

SCD1U16V2ZY-2GP
2

2ND = 84.00143.D1K

SW2

C85
1

DY

Q5

G
C

R1

BT_LED

WIRELESS_BTN#
BT_BTN#
E-BUTTON#

8
7
6
5
SRN10KJ-6-GP

Q6
31

BLON_OUT 14,31

LED1

LED-GY-14-GP

84.00143.E1K

KBC_PWRBTN#

4
3

3D3V_S5

STDBY_LED#_BD

R2
PDTC143ZU-GP-U

RN49

1
2

2nd: 62.40009.671

PWRLED#_DB
CHARGE_LED#_R

28 WLAN_LED#_MC

3D3V_AUX_S5

EC75
SC1KP50V2KX-1GP

LED3

84.00143.E1K

KBC_PWRBTN# 31

3D3V_AUX_S5

E
R2
PDTC143ZU-GP-U

DY

KBC_PWRBTN#

470R2J-2-GP

62.40009.681

SA
B

SW-TACT-122-GP

83.00195.I70

Q23
31 DC_BATFULL

5
2

LED-GY-14-GP

84.00143.E1K

R175
KBC_PWRBTN#_1

E
R2
PDTC143ZU-GP-U

Q26

SW1

R360
1
2
56R2J-4-GP
R363
1
2
56R2J-4-GP

84.00143.E1K

31

Power Button

PWRLED#_DB

R1

31 FRONT_PWRLED

2ND = 84.00143.D1K

SC1KP50V2KX-1GP

SW-TACT-122-GP

62.40009.681

2nd: 62.40009.671

EC51
SCD1U16V2ZY-2GP
2

DY
WLAN_LED#
BT_LED#
Volume_Up#
BT_BTN#
WIRELESS_BTN#
Volume_Down#
MEDIA_LED#
CAP_LED#_R
NUM_LED#_R
INT_MIC

Volume_Up# 31
BT_BTN# 31
WIRELESS_BTN# 31
Volume_Down# 31
MEDIA_LED# 19

INT_MIC 29

17

MLX-CON15-1-GP

20.K0185.015
DY

BT_LED#
EC43

2
SC220P50V2JN-3GP

EC50

2
SC220P50V2JN-3GP

DY

Volume_Down#
EC18

2
SC220P50V2JN-3GP

DY

WIRELESS_BTN#
EC20

2
SC220P50V2JN-3GP

DY

BT_BTN#
EC21

2
SC220P50V2JN-3GP

EC14
NUM_LED#_R
EC13
CAP_LED#_R
EC15
MEDIA_LED#
EC16

2
SC220P50V2JN-3GP

DY
1

2
SC220P50V2JN-3GP

2
SC220P50V2JN-3GP

DY
1

EC22

5V_S0

AFTE14P-GP

TP30

3D3V_S0

AFTE14P-GP

TP44

1
1
1
1
1
1
1
1
1
1

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

TP29
TP28
TP27
TP26
TP25
TP24
TP23
TP22
TP21
TP19

WLAN_LED#
BT_LED#
Volume_Up#
BT_BTN#
WIRELESS_BTN#
Volume_Down#
MEDIA_LED#
CAP_LED#_R
NUM_LED#_R
INT_MIC

DY

2
SC220P50V2JN-3GP

DY

Volume_Up#

Delete main source 20.K0228.015

DY

INT_MIC

DY

WLAN_LED#

-1

2
SC220P50V2JN-3GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3

BUTTON/LED/LAUNCH

Document Number

Date: Friday, August 22, 2008


5

Rev

Cathedral Peak 2A
Sheet
1

16

of

-1
43

U9A

PLT_RST1#_B 28,32

10

R99

DY

TSLVC08APW-1-GP

2
10MR2J-L-GP

X3
X-32D768KHZ-46GP
82.30001.861

L20
L19

GPP_CLK1P
GPP_CLK1N

M19
M20

GPP_CLK2P
GPP_CLK2N

N22
P22

GPP_CLK3P
GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

R229

1
2
0R0402-PAD
TP169
TPAD14-GP

R97
10MR2J-L-GP

J20

25M_X2

2ND = 82.30001.691

A3

32K_X1

2
1
C167 SC15P50V2JN-2-GP

GPP_CLK0P
GPP_CLK0N

2
1
C152
SC15P50V2JN-2-GP

32K_X2

B3

F23
F24
F22
G25
G24

X2

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ
RTCCLK
INTRUDER_ALERT#
VBAT

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15
C3
C2
B2

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

TP197
TP108
TP184
TP86
TP190
TP115
TP94
TP95
TP92
TP91

PCI_LOCK#

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
PM_CLKRUN# 31

TP189

INT_PIRQE#
INT_PIRQF# 1
INT_PIRQG# 1
INT_PIRQH# 1

TP106
TP107
TP116
TP117

TPAD14-GP

R86
10KR2J-3-GP

DY
LPC_LAD[0..3]

LPCCLK0_R R225 1
LPCCLK1_R R226 1

2 22R2J-2-GP
2 22R2J-2-GP
EC87
LPC_LAD0 31,32
EC88
LPC_LAD1 31,32
LPC_LAD2 31,32
LPC_LAD3 31,32
LPC_LFRAME# 31,32
LDRQ0#
TP162 TPAD14-GP
LDRQ1#
TP180 TPAD14-GP
PCI_REQ#5
PCI_REQ#5 3
INT_SERIRQ 31
RTC_AUX_S5
RTC_CLK 21,22
INTRUDER#
RTC_AUX_S5_R
C172

DY

LPC_LAD[0..3]

31,32

PCLK_FWH 21,32
PCLK_KBC 21,31

DY 2
DY 2SC22P50V2JN-4GP
SC22P50V2JN-4GP

-1

RTC1

C178

DY

TP99 TPAD14-GP
1
2
R118
1KR2J-1-GP
SCD1U16V2ZY-2GP

1
1

C171

SC1U10V2KX-1GP

SB700-1-GP-U1
A

21
21
21
21
21
21
21
21

SCD1U16V2ZY-2GP

6,12 ALLOW_LDTSTOP
6 PROCHOT#_SB
6,43 CPU_PWRGD
6 CPU_LDT_STOP#
6,43 CPU_LDT_RST#

X1

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

AD3
AC4
AE2
AE3

SLT_GFX_CLKP
SLT_GFX_CLKN

J19
J18

CPU_HT_CLKP
CPU_HT_CLKN

M23
M22

LPC

12,26,31 PLT_RST1#

NB_HT_CLKP
NB_HT_CLKN

P17
M18

DY DY DY DY

M24
M25

PCI INTERFACE

U12C

TPAD14-GP

1
2
NP1
NP2

NB_DISP_CLKP
NB_DISP_CLKN

TP101

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

K23
K22

RTC

14

3D3V_S5

CLOCK GENERATOR

PCI_CLK2 21
PCI_CLK3 21
CLK_PCI4 21
CLK_PCI_LOM 21

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

CPU

SC1U10V2KX-1GP

SC1U10V2KX-1GP

3 CLK_PCIE_SB
3 CLK_PCIE_SB#

PCIRST#_SB

TPAD14-GP
TPAD14-GP

N25
N24

Place R <100mils form pins T25,T24

N1

PCIE_PVSS

PCI CLKS

PCIE_PVDD

P25

PCIRST#

TP192
TP195
1
2
10R0402-PAD
2
10R0402-PAD
2
10R0402-PAD
2
0R0402-PAD

R114
R115
R116
R117

C411

PCIE_CALRP
PCIE_CALRN

P24

RTC XTAL

C392

2ND = 68.00216.161

T25
T24

220 ohm 2A

PCIE_CALRP
2 562R2F-GP
2 2K05R2F-GP PCIE_CALRN

PCI_CLK0_R
PCI_CLK1_R
PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R
PCI_CLK5_R

SC22P50V2JN-4GP

1
2
PBY201209T-221Y-N-GP

1
1

>15mil Width 43 mA

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

P4
P3
P1
P2
T4
T3

EC59

R49
R46
L10

U22
U21
U19
V19
R20
R21
R18
R17

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

SC22P50V2JN-4GP

PCIE_VDDR

ALINK_NBTX_C_SBRX_P0
ALINK_NBTX_C_SBRX_N0
ALINK_NBTX_C_SBRX_P1
ALINK_NBTX_C_SBRX_N1
ALINK_NBTX_C_SBRX_P2
ALINK_NBTX_C_SBRX_N2
ALINK_NBTX_C_SBRX_P3
ALINK_NBTX_C_SBRX_N3

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

SC22P50V2JN-4GP

+1.2V_RUN_PCIE_PVDD

11
11
11
11
11
11
11
11

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

V23
V22
V24
V25
U25
U24
T23
T22

SC22P50V2JN-4GP

1D2V_S0

2
2
2
2
2
2
2
2

Part 1 of 5

EC61

C422
C429
C410
C403
C400
C398
C415
C419

1
1
1
1
1
1
1
1

SB700
A_RST#

EC64

ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
ALINK_NBRX_SBTX_P1
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
ALINK_NBRX_SBTX_P3
ALINK_NBRX_SBTX_N3

N2

ALINK_NBRX_C_SBTX_P0
ALINK_NBRX_C_SBTX_N0
ALINK_NBRX_C_SBTX_P1
ALINK_NBRX_C_SBTX_N1
ALINK_NBRX_C_SBTX_P2
ALINK_NBRX_C_SBTX_N2
ALINK_NBRX_C_SBTX_P3
ALINK_NBRX_C_SBTX_N3

EC63

11
11
11
11
11
11
11
11

NB_RST#

PCI EXPRESS INTERFACE

R271
33R2J-2-GP
1
2

12,26,31 PLT_RST1#

PWR
GND
NP1
NP2

BAT-CON2-1-GP-U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATi-SB700_PCIE&PCI_(1/5)
Size
A3

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

17

of

-1
43

DY

10KR2J-3-GP
FP_ID

10KR2J-3-GP

3D3V_S5

1
R259
1
R272
1
R107

DY

DY

DY

SB_TEST2
2K2R2F-GP
SB_TEST1
2K2R2F-GP

-1

SB_TEST0
2K2R2F-GP

RSMRST#_KBC

1
R123
1
R137
1
R261

DY
DY
DY

2
2
2

G8

10KR2J-3-GP

FP_ID
GPIO6
GPIO4

AE18
AD18
AA19
W17
V17
W20
W21
SMBC0_SB AA18
SMBD0_SB W18
SMB_CLK
K1
SMB_DATA
K2
DDC1_SCL
AA20
DDC1_SDA
Y18
SATA_DET#
C1
GPIO5
Y19
GEVENT7#
G5

TPAD14-GP
TP69
TPAD14-GP
TP167

SMB_ALERT#
10KR2J-3-GP
PM_SLP_S5#
ECSCI#_1
ECSWI#
PM_SLP_S3#

1
2
3
4

29

ACZ_SPKR

SRN10KJ-6-GP

TPAD14-GP
TP60
TPAD14-GP
TP170
TPAD14-GP
TP98
TPAD14-GP
TP168
TPAD14-GP
TP196

3D3V_S5

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#

RN70

1
2

24 ACZ_SDATAOUT_MDC
29 ACZ_SDATAOUT
29 ACZ_SDATAIN0
24 ACZ_SDATAIN1

ACZ_BIT_CLK
ACZ_SDATAOUT_R

4
3

M1
M2
J7
J8
ACZ_SDIN2
L8
TPAD14-GP
TP176
ACZ_SDIN3
M3
TPAD14-GP
TP186
ACZ_SYNC_R
L6
ACZ_RST#_R M4
TP185
GPM8# L5
1

SRN33J-5-GP-U
RN71 SRN33J-5-GP-U
1
4
2
3

24,29 ACZ_SYNC
24,29 ACZ_RST#

3D3V_S0

ACZ_RST#_R 21

TP165
TP166
TP164

R218

NEWCARD /GLAN

DY

5
6
7
8
4
3
2
1

SRN4K7J-10-GP

1
1
1

IMC_GPIO0
IMC_GPIO1
IMC_GPIO2
IDE_RST#

H19
H20
H21
F25

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3

1
1
1
1

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

D22
E24
E25
D23

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

10KR2J-3-GP TP63
TP62
TP58
TP59

RN20

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

TO STRAPS

3D3V_S0
3D3V_S5

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

2
1

2
1

2
1

1
1

DY

10KR2J-3-GP

DY DY DY DY DY

R109
SC12P50V2JN-3GP

SC12P50V2JN-3GP

SC12P50V2JN-3GP

SC12P50V2JN-3GP

SC12P50V2JN-3GP

10KR2J-3-GP

10KR2J-3-GP

DY DY

EC67 EC66 EC62 EC58 EC65

R255 R251

B9
B8
A8
A9
E5
F8
E4

INTEGRATED uC

29
ACZ_BITCLK
24 ACZ_BTCLK_MDC

24
28

RN69
SRN33J-5-GP-U
1
4
2
3

ECSWI#
USB_OC#5
TPAD14-GP
TP78
USB_OC#4
CPPE#
USB_OC#2
TPAD14-GP
TP191
USB_OC#1
TPAD14-GP
TP181
24
USB_OC#0

HD AUDIO

31

Close to SB700

USB OC

RSMRST#_KBC

INTEGRATED uC

2
31 RSMRST#_KBC

CLK48_USB

E6
E7

1
1 DY2
DY 2CLK48_USB_R2 C479
R257
10KR2J-3-GP
SC10P50V2JN-4GP

Place these close SB700

Place R near pin14. Route it with 10mils


Trace width and 25mils spacing to any
signals in X, Y, Z directions.

USB_FSD12P
USB_FSD12N

F7
E8

USB_HSD11P
USB_HSD11N

H11
J10

USBPP7 28
USBPN7 28

USB_HSD10P
USB_HSD10N

E11
F11

USBPP8 14
USBPN8 14

USB_HSD9P
USB_HSD9N

A11
B11

USBPP9 28
USBPN9 28

Pair

USB_HSD8P
USB_HSD8N

C10
D10

USBPP4 24
USBPN4 24

11

USB_HSD7P
USB_HSD7N

G11
H12

USB_HSD6P
USB_HSD6N

E12
E14

USB_HSD5P
USB_HSD5N

C12
D12

USBPP5 24
USBPN5 24

USB_HSD4P
USB_HSD4N

B12
A12

USBPP2 24
USBPN2 24

USB_HSD3P
USB_HSD3N

G12
G14

USB_HSD2P
USB_HSD2N

H14
H15

USB_HSD1P
USB_HSD1N

A13
B13

USB_HSD0P
USB_HSD0N

B14
A14

IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

G20
G21
D25
D24
C25
C24
B25
C23

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

RSMRST#

R268
10KR2J-3-GP

26,28
26,28
3,8,9
3,8,9

USB_FSD13P
USB_FSD13N

ICH_PME#
PCIE_WAKE#

CLK48_USB
USB_PCOMP 1
R252
11K8R2F-GP

1%

10KR2J-3-GP

RN18

8
7
6
5

D3

C8

USB_RCOMP

USB MISC

ECSMI#_KBC

USBCLK/14M_25M_48M_OSC

USB 2.0

R70

NB_PWRGD
300R2J-4-GP

Part 4 of 5

SB700
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD

USB 1.1

E1
E2
H7
F5
22,28,31,33,34 PM_SLP_S3#
G1
28,31,39 PM_SLP_S5#
H2
31,43 PM_PWRBTN#
H1
34
SB_PWRGD
PM_SUS_STAT# K3
TPAD14-GP
TP194
SB_TEST2
H5
SB_TEST1
H4
SB_TEST0
H3
Y15
31
KA20GATE
W15
31
KBRCIN#
K4
31
ECSCI#_1
ECSMI#_KBC
K24
GEVENT5#
F1
TPAD14-GP
TP111
SYS_RST#
J2
TPAD14-GP
TP102
H6
26,28 PCIE_WAKE#
EC_TMR
F2
31
EC_TMR
SMB_ALERT#
J6
NB_PWRGD_R
W14

GPIO

1ICH_PME#
1 RI#
1 S2#

TP118
TP199
TP177

3D3V_S0

U9D

1D8V_S0

1
R236
1
R219

ACPI / WAKE UP EVENTS

NB_PWRGD_R
1
0R2J-2-GP

DY

2
R237

12,34 NB_PWRGD

USB

USBPP10 25
USBPN10 25

Device
MINIC1

10

WEBCAM

NEW1

USB3

CardReader

NC

OCP4#

Bluetooth

USB2

NC

NC

NC

USB1

OCP0#

USBPP0 24
USBPN0 24

SB_GPO16
SB_GPO17

21
21

Strap Pin / define to use LPC or SPI ROM


B

SB700-1-GP-U1

SMB_CLK
SMB_DATA
SMBC0_SB
SMBD0_SB

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATi-SB700_USB&GPIO_(2/5)
Size
A3

Document Number

Rev

-1

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

18

of

43

AE12
AD12

SATA_RX2N
SATA_RX2P

AD13
AE13

SATA_TX3P
SATA_TX3N

AB14
AC14

SATA_RX3N
SATA_RX3P

AE14
AD14

SATA_TX4P
SATA_TX4N

AD15
AE15

SATA_RX4N
SATA_RX4P

SB

C134
SC12P50V2JN-3GP

R83
10MR2J-L-GP

2ND = 82.30020.791
2

R243
1KR2F-3-GP
1
2

X2
XTAL-25MHZ-102-GP
82.30020.851

Very Close to SB700

SATA_X2_R

1
R79

C148
SC15P50V2JN-2-GP
1D2V_S0

SATA_TX5P
SATA_TX5N

AE16
AD16

SATA_RX5N
SATA_RX5P

SATA_CAL

V12

SATA_CAL

SATA_X1

Y12

SATA_X1

SATA_X2AA12

SATA_X2

2
300R2J-4-GP
16

AB16
AC16

W11

MEDIA_LED#

PLLVDD_SATA

W12

XTLVDD_SATA

1
2

C464

DY

3D3V_S0
B

XTLVDD_SATA

SCD1U10V2KX-4GP

C463
SC1U10V2KX-1GP

LAN_RST#/GPIO13
ROM_RST#/GPIO14

U15
J1

P5
P8
R8

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

C6
B6
A6
A5
B5

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

A4
B4
C4
D4
D5
D6
A7
B7

AVDD

F6

AVSS

G7

C454
SC1U10V2KX-1GP

1
2

CLK_ID_0
CLK_ID_1

Dummy CKG select

-1
3D3V_S0

LAN_RST#
ROM_RST#

TP187
TP109
TP110
TP200
TP96

CLK_ID_1
CLK_ID_0

TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP

R67
10KR2J-3-GP

R63
10KR2J-3-GP

RTM

SEG

TP171 TPAD14-GP
TP97 TPAD14-GP

R66
10KR2J-3-GP

R62
10KR2J-3-GP

ICS+SEG

ICS+RTM

ALERT#

CLK_ID
(1,0)
ICS: 0,0
SEG: 0,1
RTM: 1,0

22

PSW_CLR#
B

PSW_CLR#
AVDD_HWM

>15mil Width
1 R239
2
0R0603-PAD

G6
D2
D1
F4
F3

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

PCB_VER0
PCB_VER1
PCB_VER2

SB_SPI_MISO
SPI_MOSI_R
ICH_SPICLK
SB_SPI_HOLD
ICH_SPICS0#

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS#/GPIO32

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

SATA_ACT#/GPIO67

AA11

>15mil Width

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

M8
M5
M7

93 mA

PLLVDD_SATA

1 R250
2
0R0603-PAD

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SATA_TX2P
SATA_TX2N

SATA_RX1N
SATA_RX1P

AB12
AC12

SATA_RXN1_C AD11
SATA_RXP1_C AE11

2SCD01U50V2KX-1GP
2SCD01U50V2KX-1GP

DY

C461 1
C457 1

R51
10KR2J-3-GP

PlanarID
(2,1,0)
SA: 0,0,0
SB: 0,0,1
-1: 0,1,0
-2: 0,1,1

SATA_RXN1
SATA_RXP1

R52
10KR2J-3-GP

23
23

SATA_TX1P
SATA_TX1N

SATA_TXP1_C AE10
SATA_TXN1_C AD10

R54
10KR2J-3-GP

2SCD01U50V2KX-1GP
2SCD01U50V2KX-1GP

R59
10KR2J-3-GP

C571 1
C567 1

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

SATA_RX0N
SATA_RX0P

SATA_TXP1
SATA_TXN1

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

SATA_RXN0
SATA_RXP0

23
23

Part 2 of 5

DY

23
23

SATA_RXN0_C AB10
SATA_RXP0_C AC10

ATA 66/100/133

SATA_TX0P
SATA_TX0N

2SCD01U50V2KX-1GP
2SCD01U50V2KX-1GP

SPI ROM

AD9
AE9

C460 1
C465 1

HW MONITOR

SATA ODD

SATA_TXP0
SATA_TXN0

23
23

SERIAL ATA

SATA HDD

SATA_TXP0_C
SATA_TXN0_C

SATA PWR

PCB_VER2
PCB_VER1
PCB_VER0

SB700

2SCD01U50V2KX-1GP
2SCD01U50V2KX-1GP

R55
10KR2J-3-GP

DY

U9B
C300 1
C299 1

R60
10KR2J-3-GP

PLACE SATA AC DECOUPLING


CAPS CLOSE TO SB700

3D3V_S0

3D3V_S5

G10

>15mil Width

RN16
MEDIA_LED#
PSW_CLR#
ALERT#

GAP-OPEN

C141

DY
2

1
2

SC2D2U6D3V3KX-GP

3D3V_S0

1
2
3
4

C480

SCD1U10V2KX-4GP

SB700-1-GP-U1

8
7
6
5

1 R260
2
0R0603-PAD

Layout connect to Cap then GND

SRN10KJ-6-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATi-SB700_SATA-IDE_(3/5)
Size

A3

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

19

of

-1
43

U9C

SB700-1-GP-U1

1
2

C140
SC10U10V5ZY-1GP

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

2ND = 68.00216.161

>15mil Width

R262

1KR2J-1-GP
D8
1

H18
J17
J22
K25
M16
M17
M21
P16

3D3V_S0

CH751H-40PT
83.R0304.A8F

2ND = 83.R2004.B8F

F9

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

AVSSC

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
B

L17

SB700-1-GP-U1

47 mA

>15mil Width
1

C452
SC1U10V2KX-1GP DY

C453
SCD1U10V2KX-4GP

3D3V_S0

2 L23
1
0R0603-PAD

AVDDCK_3D3V

1D2V_S0

62 mA

C431
C436
SCD1U10V2KX-4GP
DY SC1U10V2KX-1GP

>15mil Width

L22 2
1
0R0603-PAD

<Core Design>

AVDDK_1D2V

DY

C469

C467

C127

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

5V_S0

L14
2
PBY201209T-221Y-N-GP

DY

1
2

3D3V_AVDDC

17mA

C471

DY

3D3V_S5

AVDDK_1D2V

PLL

1
2

3.3V_S5 I/O

AVDDCK_1.2V

K17

C444

USB I/O

1
2

DY

C472

DY

C468

SC1U10V2KX-1GP

C443

J16

SCD1U10V2KX-4GP

C446

SCD1U10V2KX-4GP

C126

SCD1U10V2KX-4GP

DY

SC1U10V2KX-1GP

C119

SC1U10V2KX-1GP

DY

SC10U10V5ZY-1GP

C131
SC10U10V5ZY-1GP

AVDDCK_3.3V

AVDDCK_3D3V

E9

C483

>10mil Width

V5_VREF

AVDDC

2
A10
B10

AE7

V5_VREF

C470

197 mA

SC1U10V2KX-1GP

>50mil Width

2ND = 68.00216.161

1D2V_S5

SCD1U10V2KX-4GP

AVDD_USB

1
2
PBY201209T-221Y-N-GP

658 mA

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

C104

>30mil Width

Use Plane Shape for +3.3V_AVDD_USB


A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

DY

113 mA

SATA I/O

1
2

1
2

1
2

G2
G4

C412

SCD1U10V2KX-4GP

S5_1.2V_1
S5_1.2V_2

DY

C435

SCD1U10V2KX-4GP

1
2

A17
A24
B17
J4
J5
L1
L2

C432

SC1U10V2KX-1GP

SCD1U10V2KX-4GP

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

USB_PHY_1.2V_1
USB_PHY_1.2V_2

3D3V_S5
L12

C99

>20mil Width

SC1U10V2KX-1GP

AA14
AB18
AA15
AA17
AC18
AD17
AE17

C447

DY

1D2V_S0

1 R217
2
0R0402-PAD

SC4D7U6D3V3KX-GP

C437
SCD1U10V2KX-4GP

SC1U10V2KX-1GP

DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP

DY EC55

C440

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

DY

SCD1U10V2KX-4GP

567 mA

1
2
PBY201209T-221Y-N-GP
C121

C94

DY

SCD1U10V2KX-4GP

L13

C129

32 mA

SC1U10V2KX-1GP

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

AVDD_SATA

= 68.00216.161 >50mil Width

DY

3D3V_S5

P18
P19
P20
P21
R22
R24
R25

1D2V_S0 2ND

CORE S0
CLKGEN I/O

IDE/FLSH I/O

POWER

CORE S5

1
2

1
2

1
2

C394

DY

SCD1U10V2KX-4GP

C402
SCD1U10V2KX-4GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP

C397

DY

C98

DY

Part 5 of 5

C86

SC2D2U6D3V3KX-GP

C420

DY

SC2D2U6D3V3KX-GP

C88

C101

DY

SC2D2U6D3V3KX-GP

600 mA

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

L21
L22
L24
L25

SC2D2U6D3V3KX-GP

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

PCIE_VDDR

220 ohm 2A

C438

CKVDD

A-LINK I/O

1
2

1
2

1
2

1
2

SCD1U10V2KX-4GP

Y20
AA21
AA22
AE25

71 mA

>100mil Width

2ND = 68.00216.161

DY

SB700

C450

>50mil Width

1D2V_S0
L11
1
2
PBY201209T-221Y-N-GP

C455

SC10U10V5ZY-1GP

C466

C458

SCD1U10V2KX-4GP

C473
SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

DY

C448

>100mil Width

L15
M12
M14
N13
P12
P14
R11
R15
T16

SCD1U10V2KX-4GP

C451

SCD1U10V2KX-4GP

DY

C96

SC1U10V2KX-1GP

SC10U10V5ZY-1GP

C93

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

SC1U10V2KX-1GP

3D3V_S0

PCI/GPIO I/O

3D3V_S0

Part 3 of 5

U9E

1D2V_S0

510 mA

SB700
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

SC1U10V2KX-1GP

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

131 mA

GROUND

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATi-SB700_POWER&GND_(4/5)
Size

A3

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

20

of

-1
43

REQUIRED STRAPS
REQUIRED SYSTEM STRAPS
D

DY

DY

R230

DY

R133

DY

R266

DY

R224

DY

R222

DY

R124

DY

R127

DY

3D3V_S5

R131

R130

3D3V_S0

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

2K2R2F-GP
PCI_CLK2 17
PCI_CLK3 17
CLK_PCI4
17
CLK_PCI_LOM 17
PCLK_FWH 17,32
PCLK_KBC 17,31
RTC_CLK
17,22
ACZ_RST#_R 18
SB_GPO17 18

RN60
SRN2K2J-1-GP

18

SB_GPO16

TPAD14-GP
TP198
TPAD14-GP
TP112
TPAD14-GP
TP193
TPAD14-GP
TP103
TPAD14-GP
TP113
TPAD14-GP
TP104
TPAD14-GP
TP114
TPAD14-GP
TP105

R228

DY 2K2R2F-GP
2

DEBUG STRAPS

4
3

10KR2J-3-GP

10KR2J-3-GP

RN57
SRN10KJ-5-GP

DY
10KR2J-3-GP

DY

10KR2J-3-GP

3
4

DY

4
3

RN19
SRN10KJ-5-GP

1
2

R134

R267

1
2

R125

2
1

R128

PCI_CLK2

PULL
HIGH

PCI_CLK3

WatchDOG
(NB_PWRGD)
ENABLED

CLK_PCI_LOM
CLK_PCI4

USE
DEBUG
STRAPS

PCLK_FWH PCLK_KBC
IMC
ENABLED

(Use Internal)

RESERVED

PULL
LOW

CLKGEN
ENABLED

WatchDog
(NB_PWRGD)
DISABLED

IGNORE
DEBUG
STRAPS

IMC
DISABLED

DEFAULT

DEFAULT

DEFAULT

CLKGEN
DISABLED
(Use External)
DEFAULT

RTCCLK
INTERNAL
RTC

AZ_RST#
ENABLE PCI
ROM BOOT

DEFAULT

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

PCI_AD28 PCI_AD27 PCI_AD26

SB_GPO17 , SB_GPO16
ROM TYPE:

PULL
HIGH

H, H = Reserved
H, L = SPI ROM

DISABLE PCI
ROM BOOT

L, H = LPC ROM

DEFAULT

L, L = FWH ROM

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30

DEFAULT

PULL
LOW

USE
LONG
RESET
(DEFAULT)
USE
SHORT
RESET

17
17
17
17
17
17
17
17

PCI_AD25

PCI_AD24

USE PCI
PLL

USE ACPI
BCLK

USE IDE
PLL

USE DEFAULT
PCIE STRAPS Reserved

PCI_AD23

(DEFAULT)

(DEFAULT)

(DEFAULT)

(DEFAULT)

(DEFAULT)

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

Reserved

PCI_AD30
PCI_AD29

Reserved

Note: SB700 has 15K internal PU FOR PCI_AD[30:23]

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTCCLK

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATi-SB700_STRAPPING_(5/5)
Size

A3

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

21

of

-1
43

FAN1_VCC

DY SC2200P50V2KX-2GP
2

RN53
SRN10KJ-5-GP

FAN1_VCC

AFTE14P-GP

TP4

FAN1_FG1

AFTE14P-GP

TP3

FAN1_VCC

2ND = 83.00016.F11

14,31

LID_CLOSE#

LID_CLOSE#

FAN1

1
2

C3

4
3

3
D1
BAS16-1-GP
83.00016.B11

C1
SC4D7U10V5ZY-3GP

DY
2

C2
SCD1U16V2ZY-2GP

5V_S0

3D3V_AUX_S5

*Layout* 15 mil

FAN1_FG1

3
2

1
4

C323
SC1KP50V2KX-1GP

*Layout* 15 mil

MLX-CON3-10-GP-U

20.F1000.003

2nd: 20.F0714.003
3nd: 20.D0246.103

SA
5V_S0

U5

G792_DXN2
G792_DXN3

G5

DXP1:108 Degree
DXP2:H/W Setting
DXP3:88 Degree
32KHZ

R129
10R2J-2-GP
1
2

C
SC470P50V3JN-2GP
SC2200P50V2KX-2GP

G792_DXN3 12

2ND = 84.03904.H11

3.System Sensor, Put between CPU and NB.

Q9
MMBT3904-3-GP

C111

SC2200P50V2KX-2GP

G9

2ND = 84.03904.H11

H_THERMDA 6

Place near chip as close


as possible

C106
SC2200P50V2KX-2GP
H_THERMDC 6

G792_32K

1.For CPU Sensor

RTC_CLK

17,21

U12A

18,28,31,33,34 PM_SLP_S3#

Q16
MMBT3904-3-GP

BDY

14

3D3V_S5

GAP-CLOSE

G792SFUF-GP
74.00792.A79

C406

8
10
12

G792_DXP3 12

SGND1
SGND2
SGND3

C107 C83

GAP-CLOSE

R65
49K9R2F-L-GP

5
17

2.H/W Shutdown

RUNPWROK

DGND
DGND

SA

G792_DXP2
G792_DXP3

ALERT#
THERM#
THERM_SET
RESET#

SMBD_G792 31
SMBC_G792 31

2
1

15
13
3
2

G792_32K

SC470P50V3JN-2GP

V_DEGREE
34

DXP1
DXP2
DXP3

1
4
14
16
18
19

ALERT#
T8_HW_SHUT#

T8=90

7
9
11

FAN1
FG1
CLK
SDA
SCL
NC#19

2
SCD1U16V2ZY-2GP
19

VCC
DVCC

C97
SCD1U16V2ZY-2GP

DY

1
1

R64
21KR2F-GP

C105
SC1U10V3ZY-6GP

C92

SC4D7U10V5ZY-3GP

6
20

C87

5V_G792_S0

2
R50
10R2J-2-GP

*Layout* 30 mil
1

5V_S0

TSLVC08APW-1-GP

BL3#

32K suspend clock output


5V_AUX_S5

5V_AUX_S5
B

U33

HW thermal shut down tempature


setting 95 degree . Put Near SB.

LOW3_OFF

G680LT1UF-GP

DY
3D3V_AUX_S5

SET
GND DY
OUT#

VCC

HYST

G709_VCC
SB_TH_HYST

G709T1UF-GP

174KR2F-GP

RSMRST# 31

R40
0R2J-2-GP

DY
2

OUT#: Hi active / mount R1110


Low active / mount R1108

DY

1
2
3

R42
0R2J-2-GP

DY

DY R206
D22
BAW56-7-F-GP
3D3V_AUX_S5

U32

C380
SCD1U16V2ZY-2GP

1
2
3

31,43 S5_ENABLE

2 SB_THSET
18KR2F-GP
T8_HW_SHUT#

DY

1
1

DY

2
3

R208
0R2J-2-GP

D20
BAT54-4-GP

DY

HTH

1
R200
10KR2J-3-GP

U3

R44

C95
SCD01U16V2KX-3GP
R203
6K04R2F-GP

T8_HW_SHUT#

LTH

1
2
3

R43
150R2J-L1-GP-U
5V_AUX_S5

HTH
DY
GND
RESET#/RESET LTH

DY

VCC

1MR2F-GP

DY R201

HTH

DY
2

C384
SCD1U16V2ZY-2GP

DCBATOUT

HW Thermal Throttling

A
B
GND

VCC

DY

S5PWR_ENABLE 37

<Core Design>

NC7S08M5X-NL-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1
R209

2
1KR2J-1-GP

1
D21
BAS16-1-GP
2

Title

G792

KBC_THERMTRIP# 6,31
Size

A3

Document Number

Rev

Date: Friday, August 22, 2008


5

-1

Cathedral Peak 2A
Sheet
1

22

of

43

SATA ODD Connector

SATA Connector

ODD1
SATA1

5V_S0

P3
P2

DP
MD

ODD_DP
ODD_MD

TP204 TPAD14-GP

SB

MP

SATA_TXN1

SATA_RXN1

SATA_TXP1

SATA_RXP0 19
SATA_RXN0 19

C589

D28
SSM24PT-GP

SATA_TXN0 19
SATA_TXP0 19

62.10065.471

2nd: 62.10065.551

SATA_TXP0
D40
BAV99PT-GP-U

D41
BAV99PT-GP-U

D39
BAV99PT-GP-U

3D3V_S0

3D3V_S0
3D3V_S0

3D3V_S0

3
2

D38
BAV99PT-GP-U

3D3V_S0
3D3V_S0

SATA_TXN0

BAV99PT-GP-U

1
3D3V_S0

SATA_RXN0

MP

D36
BAV99PT-GP-U

SATA_RXP0

D37

D35
BAV99PT-GP-U

MP

DY

SKT-SATA22P-27-GP

D34
BAV99PT-GP-U

TC28

16
17
18
19
20
21
22
NP2
24

2nd: 62.10065.481
3nd: 62.10065.441

SATA_RXP1

DY

SCD1U16V2ZY-2GP

R317
10KR2J-3-GP

62.10065.541

5V_S0

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SSM24PT-GP

SKT-SATA7P+6P-39-GP
TC23

C558
SCD1U16V2ZY-2GP

DY

DY
D27

+5V
+5V

P1
P4

2
3
4
5
6
7
8
9
10
11
12
13
14
15

A+
A-

S2
S3

23
NP1
1

19 SATA_TXP1
19 SATA_TXN1
C

GND
GND
GND
GND
GND
GND
GND

B+
B-

9
8
P6
P5
S7
S4
S1

S6
S5

19 SATA_RXP1
19 SATA_RXN1

3D3V_S0

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

HDD & CDROM

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

23

of

-1
43

5V_USB1_S0

USB1
USB1

5V_USB1_S0

74.00545.A79

2nd: 22.10218.T51
3nd: 22.10321.111

2nd source 74.09711.079


18

5V_USB1_S0

USB_OC#0

USB2
USB2

2
3
4

5V_USB2_S0

5V_S5
U40

5V_USB2_S0

SKT-USB-198-GP

31 USB_PWR_EN#

USB3

R285
0R0402-PAD
2
1
2
1
R288
0R0402-PAD

DY

EC92

TC14

EC60

DY
2

DY

2nd source 74.00545.A79

1
USB_4USB_4+

TC15

1
1

DY
EC93
SCD1U16V2ZY-2GP

USB_OC#4 18

SC1000P50V3JN-GP

USB_OC#4

74.09711.079

USB3

USBPN4
USBPP4

60mil

8
7
6
5

RT9711BPF-GP

5V_USB2_S0

VOUT
VOUT
VOUT
FLG#

SCD1U16V2ZY-2GP

USB_PWR_EN#

GND
VIN
VIN
EN/EN#

ST150U6D3VDM-18GP

1
2
3
4

ST100U6D3VBM-5GP

C492
SC4D7U10V3KX-GP

2nd: 22.10218.T51
3nd: 22.10321.111

22.10218.W51

R238
0R0402-PAD

18
18

1
USB_2USB_2+

USBPN2
USBPP2

EC54

DY

EC86
SCD1U16V2ZY-2GP

18
18

EC19

DY

DY

R235
0R0402-PAD
2
1
2
1

TC10

GND

G545A2P8U-GP

DY

USB_PWR_EN#

TC8

SC1000P50V3JN-GP

OC#
EN/EN#

SCD1U16V2ZY-2GP

22.10218.W51

5
4

100 mil
ST150U6D3VDM-18GP

C385
SC4D7U10V3KX-GP

8
7
6

ST150U6D3VDM-18GP

OUT#8
OUT#7
OUT#6

6
SKT-USB-198-GP

IN#3
IN#2

R205
0R0402-PAD

U35

3
2

2
3
4

USB_0USB_0+

5V_S5

USBPN0
USBPP0

18
18

5V_USB1_S0

R204
0R0402-PAD
2
1
2
1

2
3
4
6
SKT-USB-198-GP

22.10218.W51

2nd: 22.10218.T51
3nd: 22.10321.111

BLUETOOTH MODULE

MDC 1.5 CONN


2

1.5A / High Active Voltage 2V


3D3V_S0
3D3V_BT_S0
U66

BLUETOOTH_EN 31

18,29
ACZ_SYNC
18 ACZ_SDATAIN1

G5240B1T1U-GP

74.05240.A7F

2nd:74.09711.A7F

4
6
8
10
12
17
18

3D3V_S5

R174
0R0402-PAD
2
1

18,29 ACZ_RST#

ACZ_BTCLK_MDC 18
C303

TYCO-CONN12A-2-GP-U1
C591
SC22P50V2JN-4GP

20.F0917.012
C590

DYSC100P50V2JN-3GP
2

BLUE1

2nd: 20.F0604.012

6
4
3
2

USB_5USB_5+

3D3V_BT_S0

USBPN5
USBPP5

18
18

1
R172
100KR2J-1-GP

DY

3D3V_S5

SC4D7U10V5ZY-3GP

EC21 put near


BLUE1 / all
USB put one
choke near
connector by
EMI request

3
5
R337 2 0R0402-PAD
ACZ_SYNC_A
1
7
R336 1 33R2J-2-GP
ACZ_SDATAIN1_A
2
9
11
2 R335
1ACZ_RST#_MDC
NP2
0R0402-PAD
16

DY 2

EN

15
14
2

13
NP1
1

IN

ACZ_SDATAOUT_MDC

OUT
GND
NC#3

18 ACZ_SDATAOUT_MDC

1
2
3

C607
SC4D7U10V5ZY-3GP

EC74 DY
SCD1U16V2ZY-2GP

3D3V_BT_S0

C302
SC4D7U10V5ZY-3GP

MDC1

C301
DUMMY-C2

13
14
15

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

R173
0R0402-PAD

USB_51
USB_5+ 1
3D3V_BT_S0 1

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

TP147
TP146
TP144

Title

USB/BLUETOOTH/MDC
Size

Document Number

Rev

Cathedral Peak 2A
Date: Friday, August 22, 2008

12

20.F0984.004

16
17
18

Wistron Corporation

ETY-CON4-21-GP-U

2nd: 20.D0197.104
3nd: 20.F0689.004

11

24

Sheet
1

of

-1
43

3D3V_S0

3D3V_D_S0

3D3V_A_S0

R355
0R0603-PAD
1
2

XD_CD#
SD_WP
SD_CD#
XD_D4
XD_D5/MS_BS
SD_DAT1/XD_D3/MS_D1_1
SD_DAT0/XD_D6/MS_D0
SD_DAT7/XD_D2/MS_D2
MS_INS#
SD_DAT6/XD_D7/MS_D3
SD_CLK/XD_D1/MS_CLK
SD_DAT5/XD_D0
SD_DAT4/XD_WP#
XD_R/B#
SD_DAT3/XD_WE#
SD_DAT2/XD_RE#
XD_ALE
XD_CE#
XD_CLE

SD_DAT1/XD_D3/MS_D1_1
R357
0R0603-PAD
1
2

CARD_3D3V_S0

C609
SC1U10V3KX-3GP

R338
0R2J-2-GP
1 SD_DAT1/XD_D3/MS_D1
DY

XD_D4

R341
0R0402-PAD

DY

3D3V_D_S0

3V3_IN

33
11

D3V3
D3V3

EECS
EESK
EEDO
EEDI

45
36
14
2
44

MODE_SEL
SD_CMD
GPIO0
RREF
RST#

3D3V_A_S0

8
7
6
5

C597
SCD1U16V2ZY-2GP

DY

2
EEDO
EEDI

6
12
32
46
C

-4

DY C600

RTS5158E-GR-GP

71.05158.A0G

SC5D6P50V2CN-1GP
1

12M_XI

R349
0R0402-PAD
2
1

3D3V_D_S0

DY
2

X6
XTAL-12MHZ-11GP

DY

DY

82.30006.191

12M_XO

1
C601
SC5D6P50V2CN-1GP

R352
0R0402-PAD
2
1

CLK48_5158E

R347
270KR2F-GP

2 R354
1 USB_10+
0R0402-PAD
2 R353
1USB_100R0402-PAD

USBPN10

C596
SC1U10V3KX-3GP

DU
ORG
GND

C603
SCD1U16V2ZY-2GP

EEDO
EEDI

USBPP10

18

EESK
EECS

18

DY 10KR2J-3-GP

12M_XI
12M_XO

R344

C599 DY
SC47P50V2JN-3GP

XDAL_CTR

R342
100KR2J-1-GP

DY VCC

S
C
D
Q

M93C46-WMN6TP-GP

0R2J-2-GP

15
18

MODE_SEL

RST#_1

EESK
EECS

RST#

6K19R2F-GP
R379
1
2

GND
GND
GND
GND

17
16

3D3V_D_S0

RREF

XTLI
XTLO

LED-W-23-GP

1
2
3
4

30
7
3

DY

XTAL_CTR

MODE_SEL
SD_CMD

K VBUS_LED
R356
1

NC#30
NC#7
NC#3

47
48

LED4
ADY

VBUS_R

VREG

DP
DM

24
22

AV_PLL

5
4

DY

C592

U65

MS_D5
MS_D4

DY SCD1U16V2ZY-2GP
1

1
2

C594
SCD1U16V2ZY-2GP

68R2-GP

3D3V_D_S0

C604

DYSCD1U16V2ZY-2GP
R358

12M_XO

5 IN1 CARD-READER (SD/MMC/MS/MS PRO/XD)

NP1
NP2

1
2

1
2

1
2

1
2

37
38
13
22

SC22P50V2JN-4GP

GROUND
GROUND
4IN1_GND
4IN1_GND

SC22P50V2JN-4GP

SD_CLK/XD_D1/MS_CLK
MS_INS#
XD_D5/MS_BS

EC111

15
17
21

SC22P50V2JN-4GP

MS_SCLK
MS_INS
MS_BS

EC110

SD_DAT0/XD_D6/MS_D0
SD_DAT1/XD_D3/MS_D1_1
SD_DAT7/XD_D2/MS_D2
SD_DAT6/XD_D7/MS_D3

SC22P50V2JN-4GP

NP1
NP2

19
20
18
16

EC114

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3

DY DY DY DY DY DY DY DY
SC22P50V2JN-4GP

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

EC113

8
9
26
27
28
30
31
32

SD_WP
SD_CD#
SD_CMD
SD_CLK/XD_D1/MS_CLK

SC22P50V2JN-4GP

SD_DAT5/XD_D0
SD_CLK/XD_D1/MS_CLK
SD_DAT7/XD_D2/MS_D2
SD_DAT1/XD_D3/MS_D1_1
XD_D4
XD_D5/MS_BS
SD_DAT0/XD_D6/MS_D0
SD_DAT6/XD_D7/MS_D3

35
36
12
24

EC109

Pin27 change to
SD_DAT1/XD_D3/MS_D1_1
for XD fail

SD_WP_SW
SD_CD_SW
SD_CMD
SD_CLK

SC22P50V2JN-4GP

XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP
XD_CD_SW

SD_DAT0/XD_D6/MS_D0
SD_DAT1/XD_D3/MS_D1
SD_DAT2/XD_RE#
SD_DAT3/XD_WE#

EC108

1
2
3
4
5
6
7
34

25
29
10
11

SC22P50V2JN-4GP

XD_R/B#
SD_DAT2/XD_RE#
XD_CE#
XD_CLE
XD_ALE
SD_DAT3/XD_WE#
SD_DAT4/XD_WP#
XD_CD#

SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3

EC112

XD_VCC
SD_VCC
MS_VCC

C605
SCD1U16V2ZY-2GP
DY

EC115

C611
SC4D7U10V5ZY-3GP

CARD1

33
23
14

CARD_3D3V_S0

CARD_3D3V_S0

SD_DAT0/XD_D6/MS_D0
SD_DAT1/XD_D3/MS_D1
SD_DAT2/XD_RE#
SD_DAT3/XD_WE#
SD_WP
SD_CD#
SD_CMD
SD_CLK/XD_D1/MS_CLK

10

3V_VBUS_S0

3D3V_S0

RST#

1
VREG

CARD_3V3

AV_PLL

R364
0R0603-PAD
1
2
C610
SC4D7U6D3V5KX-3GP

13

VREG

C602
SCD1U16V2ZY-2GP

R351
0R0603-PAD
1
2

C606
SC1U10V3KX-3GP

3D3V_S0

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16
SP17
SP18
SP19

19
20
21
23
25
26
27
28
29
31
34
35
37
38
39
40
41
42
43

U63

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

SA

CARDBUS38P-GP-U

CARDREADER- RTS5158E
Size

2nd:20.I0081.001
3nd:20.I0067.001
5

20.I0079.001

Document Number

Rev

Cathedral Peak 2A
Date: Friday, August 22, 2008
3

Sheet
1

25

of

-1
43

R220

C108
SCD1U10V2KX-4GP

2XTALVDD_G

FCM1608K-601T03GP
68.00217.241

3D3V_LAN_S5

R207

72.45011.B01

2BIASVDD_G

R35

2LAN_AVDD

2
GPHY_PLLVDDL

3D3V_LAN_S0

GPHY_PLLVDD
C82
SCD1U10V2KX-4GP

1 R38
2
0R0603-PAD

PCIE_PLLVDD

30
27

PCIE_PLLVDDL
PCIE_PLLVDDL

TRD3_N
TRD3_P

49
50

TRD2_N
TRD2_P

47
46

MDI2MDI2+

27
27

TRD1_N
TRD1_P

43
44

MDI1MDI1+

27
27

TRD0_N
TRD0_P

41
40

LINKLED#
SPD100LED#
SPD1000LED#
TRAFFICLED#

2
1
67
66

MDI3MDI3+

27
27

MDI0MDI0+

Place PLLVDD/AVDDL
CKT as close to chip as
possible

3D3V_AUX_S5
27
27

3D3V_S0

C76
SCD1U10V2KX-4GP

35

C77
SCD1U10V2KX-4GP

AVDDL
AVDDL
AVDDL

C382
SCD1U10V2KX-4GP

FCM1608K-601T03GP
68.00217.241

FCM1608K-601T03GP
68.00217.241

39
45
51

AT45DB011D-SH-T-GP

LAN_AVDD
LAN_AVDD

C408
SCD1U10V2KX-4GP

48
42

DY

XTALVDD_G

SI

8
7
6
5

SO
GND
VCC
WP#

23

SI
SCK
RESET#
CS#

C139

XTALVDDH

1
2
3
4

BIASVDD_G

36

SO
SCLK
AT45_RESET#
CS#

2
BIASVDDH

VDDC_IO
VDDC_IO
VDDC
VDDC
VDDC
VDDC

AVDDH
AVDDH
AVDDL_G
AVDDL_G
AVDDL_G

U8

38
52
68
DC#38
DC#52
DC#68

2
SCD1U10V2KX-4GP

6
56
61
15
19
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

5
55
13
20
34
60

R82
10KR2J-3-GP

2D5V_1D2V_LAN

C401

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1D2V_LAN_S5

U7

3D3V_LAN_S5

SCD1U10V2KX-4GP

1 R78
2
0R0603-PAD
SCD1U10V2KX-4GP

C81

3D3V_LAN_S5

C69

SCD1U10V2KX-4GP

C68

C123

SCD1U10V2KX-4GP

SC4D7U10V5ZY-3GP

C427

3D3V_LAN_S5

3D3V_S5

C124

LAN_AVDD

1D2V_LAN_S5

R53

33
24

PCIE_VDDL
PCIE_VDDL

DY 10KR2J-3-GP
2

C428

1D2V_LAN_S5

2D5V_1D2V_LAN

Q17

REGCTL12

14

REGCTL12

3
4
2

DCP69A-13-GP
84.DCP69.01B

LAN_CLKREQ#

3D3V_LAN_S5

11

SRN1KJ-10-GP-U

BCM5764MKMLG-GP

71.05764.M01

SUPER_IDDQ

16
2

GND

VMAINPRSNT
VAUX_PRESENT
LAN_CLKREQ#

69

8
7
6
5

C396
SC4D7U10V5ZY-3GP
C456
SCD1U10V2KX-4GP

2
1

1
2

1 R213
2PCIE_SDSVDD
0R0603-PAD

1D2V_LAN_S5

C424
SC10U10V5ZY-1GP

RN7

1
2
3
4

C89

2ND = 84.00069.A1B

CLKREQ#

3D3V_LAN_S0

1K2R2F-1-GP

C449
R249
0R0603-PAD

RDAC

37

1 R39
2PCIE_PLLVDD
0R0603-PAD
C90
SC4D7U10V5ZY-3GP

3D3V_LAN_S5

C426
SCD1U10V2KX-4GP

1
1
18

1RDAC

REGOUT12_IO

R36

17

Wistron Corporation
C418
SCD1U10V2KX-4GP

XTALO
XTALI

VDDC_IO

1
2

2ND = 82.30020.791

C115

SMB_CLK
SMB_DATA

SC4D7U10V5ZY-3GP

LAN_XI

SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

X1
XTAL-25MHZ-102-GP
82.30020.851

2
1LAN_SMB_CLK 58
20R0402-PAD
1LAN_SMB_DATA 57
0R0402-PAD
R57
2
1LAN_X0
200R2J-L1-GP
22
21

C
C

C109

2D5V_1D2V_LAN

LAN_XO_R

C393

R48
R45

VAUX_PRSNT
VMAIN_PRSNT
LOW_PWR

SCD1U10V2KX-4GP

18,28 SMB_CLK
18,28 SMB_DATA

C72
SC4D7U10V5ZY-3GP

1
0R2J-2-GP

R61
4K7R2J-2-GP

2 R72
DY

C74

59

SCD1U10V2KX-4GP

VAUX_PRESENT54
VMAINPRSNT 53
LOW_PWR
3

LOW_PWR

2GPHY_PLLVDD

FCM1608K-601T03GP
68.00217.241

SCD1U10V2KX-4GP

31

R34

C78

C73
SC4D7U10V5ZY-3GP

ENERGY_DET 31

ENERGY_DET

2 AVDDL_G

SCLK
SI
SO
CS#

SB
B

R33

FCM1608K-601T03GP
68.00217.241

R56

1
2

C395

65
63
64
62

TP71 TPAD14-GP
TP70 TPAD14-GP
TP67 TPAD14-GP

C130

SCLK/EECLK
SI
SO/EEDATA
CS#

UART_MODE
GPIO1
GPIO0

C423

9
7
4

2
1

UART_MODE
GPIO_1/SERIAL_DI
GPIO_0/SERIAL_DO

C404

SCD1U10V2KX-4GP

PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
WAKE#
PERST#
PCIE_REFCLK_P
PCIE_REFCLK_N

TP68 TPAD14-GP

SCD1U10V2KX-4GP

C120
SC47P50V2JN-3GP

LAN_RST

3 CLK_PCIE_LAN
3 CLK_PCIE_LAN#

26
25
31
32
12
10
29
28

GPIO2

SCD1U10V2KX-4GP

18,28 PCIE_WAKE#

PCIE_RXDP
PCIE_RXDN

SC4D7U10V5ZY-3GP

2 R74
1
0R0402-PAD

12,17,31 PLT_RST1#

1 C100
1 C103

GPIO_2

SCD1U10V2KX-4GP

SCD1U10V2KX-5GP 2
SCD1U10V2KX-5GP 2

PCIE_RXP1
PCIE_RXN1
PCIE_TXP1
PCIE_TXN1

ENERGY_DET

SCD1U10V2KX-4GP

11
11
11
11

10M/100M/1G_LED# 27
LAN_ACT_LED# 27

C389
SCD1U10V2KX-4GP

DY 10KR2J-3-GP
2

PCIE_SDSVDD

3D3V_LAN_S5

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

BCM5764MKMLG
Size
A3

Document Number

Rev

Date: Friday, August 22, 2008


2

-1

Cathedral Peak 2A
Sheet
1

26

of

43

LAN Connector

1.route on bottom as differential pairs.


2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.

LAN_ACT_LED#
10M/100M/1G_LED#

DY

DY

C369
C326
SC1KP50V2KX-1GP SC1KP50V2KX-1GP

XF1
26

MDI0+

23

RJ45_1

26

MDI0-

3
1

22
24

RJ45_2
MCT1

4
5

21
20

MCT2
RJ45_3

LAN Connector
RJ45

V_DAC

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

MDI1+

26

MDI1-

19

RJ45_6

26

MDI2+

17

RJ45_4

14
9
10
11
1

CONN_PWR
RJ45_1

C328

DY
2

C355

26

26 10M/100M/1G_LED#

RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
CONN_PWR2

9:GREEN
13:Orange

2
3
4
5
6
7
8
12
13
15

26 LAN_ACT_LED#

RJ45-92-GP

26

MDI3+

9
7

16
18

10
11

15
14

MCT4
RJ45_7

SA

22.10245.E91

2nd:
LAN Link: Green(9), behavior is the
same for 10/100/1000 bits

C329
SCD1U10V2KX-4GP

DY
2

C351
SCD1U10V2KX-4GP

26

MDI2-

RJ45_5
MCT3

LAN Data: Yellow(13), when LAN is


transfering data.
26

MDI3-

12

13

RJ45_8

XFORM-275-GP

DOC_TIP,DOC_RING,TIP,RING:
W/S : 10/100 @ Surface layers
10/20 @ Inner layers

68.89240.30A

RN55

EC84

EC80

8
7
6
5

MCT1
MCT2
MCT3
MCT4

DY

1
2
3
4

RN54
SRN75J-1-GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP

DY

SRN470J-3-GP

CONN_PWR2
CONN_PWR

8
7
6
5

1
2
3
4

3D3V_LAN_S5

MCT_R

C376
SC1KP2KV8KX-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LAN CONN
Size
A3

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


A

Sheet
E

27

of

-1
43

NEWCARD Connector

NEW2

Mini Card Connector(WLAN)

CARDBUS-SKT107-GP

21.H0168.001

31
31

11 PCIE_TXN2
11 PCIE_TXP2
3D3V_MINI

20.F1336.026

2nd: 62.10081.131
3nd: 20.F1311.026

4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54

E51_RxD
E51_TxD

11 PCIE_RXN2
11 PCIE_RXP2

SB

3
5
7
9
11
13
15

3 CLK_PCIE_MINI1#
3 CLK_PCIE_MINI1

5V_S5

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

3D3V_S5

3
4

WLAN_LED#_MC 16
TP163
TPAD14-GP

NC#16
NC#14
NC#13
NC#5
NC#4
16
14
13
5
4

3D3V_S0

R76
1

0R2J-2-GP
2

3D3V_S5

R73
1

0R2J-2-GP
DY 2

3D3V_MINI

C102

C43

C80

3D3V_S5

DY

C79

1
2

DY

1D5V_S0

C122
SCD1U16V2ZY-2GP

Place them Near to Connector

C276

3D3V_NEW_LAN_S5

C277
SC1U10V3ZY-6GP

C282

1D5V_NEW_S0

SCD1U16V2ZY-2GP

C280
SC1U10V3ZY-6GP

TPAD14-GP
TP161

SCD1U16V2ZY-2GP

TPS2231RGP-GP-U

SCD1U16V2ZY-2GP

TC3

ST330U6D3VDM-17GP

74.02231.073

3D3V_NEW_S0

C84
SCD1U16V2ZY-2GP

LED_WPAN#

3D3V_S0
3D3V_NEW_S0

3D3V_S0

LED_WWAN#

SC1U6D3V2KX-GP

3D3V_S0
3D3V_NEW_S0
1D5V_S0
1D5V_NEW_S0
3D3V_S5
3D3V_NEW_LAN_S5

GND

1D5V_S0
1D5V_NEW_S0

Place them Near to Chip

SMB_CLK 18,26
SMB_DATA 18,26

SRN33J-5-GP-U

Place near MINIC1

SCD1U16V2ZY-2GP

2
3
12
11
17
15

4
3

USBPN7 18
USBPP7 18

3D3V_S0

3.3VIN
3.3VOUT
1.5VIN
1.5VOUT
AUXIN
AUXOUT

DY

62.10043.461

SB

SC1U6D3V2KX-GP

STBY#
RCLKEN
OC#
THERMAL_PAD

1
R47
0R0402-PAD

1
18
19
21

WIRELESS_EN 31
PLT_RST1#_B 17,32

RN9
SMB_CLK_WLAN 1
SMB_DATA_WLAN2

2nd: 20.F1049.052
3nd: 62.10043.511

PLT_RST1#_B 17,32

C278
SC100P50V2JN-3GP

SHDN#
PERST#
CPUSB#
CPPE#
SYSRST#
18,22,31,33,34 PM_SLP_S3#

2 R160
1
0R0402-PAD
1

DY 2
10KR2J-3-GP

PLT_RST1#_WLAN

20
8
9
10
6

U14

SB

SRN100KJ-6-GP
PLT_RST1#_NEWCARD

R41

C91
SC100P50V2JN-3GP

DY

SB

SKT-MINI52P-13-GP

RN48
CPUTSB# 2
CPPE#
1
18,31,39 PM_SLP_S5#

3D3V_MINI

MINI_WAKE#

53
NP1
1

TPAD14-GPTP156
TPAD14-GPTP156

FCI-CON26-7-GP

TPS2231_PERST#

3D3V_MINI

MINIC1

NP2
26
25
11 PCIE_TXP5
24
11 PCIE_TXN5
23
22
11 PCIE_RXP5
21
11 PCIE_RXN5
20
19
3 CLK_PCIE_NEW
3D3V_NEW_S0
18
3 CLK_PCIE_NEW#
CPPE#
17
18
CPPE#
NEW_PIN16
16
TP143
15
14
3D3V_NEW_LAN_S5
TPS2231_PERST#
13
12
PCIE_WAKE#_NEW
1
2
11
DY
18,26 PCIE_WAKE#
R159 0R2J-2-GP
10
1D5V_NEW_S0
RN47
9
1
4 SMB_DATA_NEW 8
DY
18,26 SMB_DATA
SMB_CLK_NEW
2
3
7
18,26 SMB_CLK
CONN_TP1 6
SRN33J-5-GP-U
TP142
CONN_TP2 5
TP141
CPUTSB#
4
3
18 USBPP9
2
18 USBPN9
1
NP1

1D5V_S0

2nd: 21.H0182.001
3nd: 21.H0183.001

NEW1

C275
SCD1U16V2ZY-2GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

NEW CARD/MINI CARD


Size

Document Number

Rev

Cathedral Peak 2A
Date: Friday, August 22, 2008
A

Sheet
E

28

of

-1
43

5V_S0

4.75V / 300mA
U52

1
2
3

EN
GND
VIN

VOUT

5VA_S0

NC#5

"VAUX" Pull high to enable standby mode


RN65

R294
10KR2J-3-GP

SPKR_SB_1

C515
SC100P50V2JN-3GP

SCD47U16V3ZY-3GP

1
2

1
2

1
2

RESET#

2
R301

BCLK

2 R298

1
0R0402-PAD

1
0R0402-PAD

1
2
C520
DY
SC22P50V2JN-4GP

SC4D7U10V3KX-GP
SC4D7U10V3KX-GP
SC1U16V3ZY-GP
SC1U16V3ZY-GP

30 AUD_MICIN_L
30 AUD_MICIN_R
16
INT_MIC

2
2
1
1

2 SEL_MIC
1KR2F-3-GP
1
1
2
2

C535
C537
C526
C534

MIC1-L_PORT-B
MIC1-R_PORT-B
IMT_MIC1-L
IMT_MIC1-R

29
31

LINE1-VREFO
GPIO1

21
22
16
17

MIC1-L_PORT-B
MIC1-R_PORT-B
MIC2-L_PORT-F
MIC2-R_PORT-F

32
28
30

MIC1-VREFO-R
MIC1-VREFO-L
MIC2-VREFO

34
13
SENSE_B
SENSE_A

44
43

12
11
10
6
33

MIC_JD# 30

Sense resistors need close codec


5
8

AC97_DATIN
1
R297

2
33R2J-2-GP

ACZ_SDATAOUT 18
ACZ_SDATAIN0 18

SPDIFO
EAPD

48
47

NC#45
DMIC-CLK

45
46

HP-OUT-L_PORT-A
HP-OUT-R_PORT-A

39
41

FRONTL 30
FRONTR 30

LINE-OUT-L_PORT-D
LINE-OUT-R_PORT-D

35
36

SOUNDL 30
SOUNDR 30

AMP_SHUTDOWN# 30,31

ALC_EAPD

D24
BAW56-7-F-GP

DY

R306
0R0402-PAD

DMIC-12/GPIO0
DMIC-34/GPIO3

2ND = 83.00056.G11
R300

DY

2 3D3V_S0

10KR2J-3-GP

CD-L
CD-R
CD-G

ALC268-GR-GP

18
20
19

2
3

71.00268.00G
2

VREF

JDREF
MONO-OUT
40
37
JDREF

27

AVSS1
AVSS2
DVSS
DVSS
1

C234
SCD47U16V3ZY-3GP

R299
10KR2F-2-GP

MONO-OUT
TP203
TPAD14-GP

Change to 71.00268.A0G

DY

R307
20KR2F-L-GP

1
2

C548
SC10U10V5ZY-1GP

R305
1
2
20KR2F-L-GP

30 ALC268_EAPD

VREF

DY

SC22P50V2JN-4GP

ALC268

26
42
4
7

C550
SC4D7U10V5ZY-3GP

C549
SC4D7U10V5ZY-3GP

C551
SC4D7U10V5ZY-3GP

SRN2K2J-2-GP

MIC1V_R
MIC1V_L
MIC2-VREFO

8
7
6
5

ALC268_SENSE

C519
1
2DY

SDATA-OUT
SDATA-IN

RN31

1
2
3
4

LINEOUT_JD# 30

LINE1-L_PORT-C
LINE1-R_PORT-C
NC#14
NC#15

R304
1
2
39K2R2F-L-GP

R155

SA

23
24
14
15

NC#44
NC#43

DVDD
DVDD-IO
AVDD1
AVDD2

U48

PCBEEP
RESET#
SYNC
BCLK
NC#33

1
9
25
38

ACZ_RST# 18,24

ACZ_SYNC 18,24
ACZ_BITCLK 18

2
SCD47U16V3ZY-3GP

SB

C513 SC100P50V2JN-3GP
1
2

ACZ_SPKR

SC1U10V3KX-3GP

SRN47KJ-1-GP

C544
C231
SC10U10V5ZY-1GP
C521
SCD1U10V2KX-4GP
DY
SC10U10V5ZY-1GP

C508
1

2AUDIP_PC_BEEP

18

KBC_BEEP

C524
SCD1U10V2KX-4GP

C516
1

AUDIO_BEEP

31

C507
1

5
6
7
8

4
3
KBC_BEEP_1 2
1

DY

AMP_BEEP_1
2
SCD47U16V3ZY-3GP

C506
1

AMP_BEEP

C543
SC10U10V5ZY-1GP

5VA_S0

3D3V_S0
30

74.09198.A7F
74.09091.F3F
G9091-475T12U-GP

C525
SC1U10V3KX-3GP

RT9198-4GPBG-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

Azalia codec ALC268


Document Number

Rev

Date: Friday, August 22, 2008


5

-1

Cathedral Peak 2A
Sheet
1

29

of

43

AUDIO OP AMPLIFIER
5V_S0

2 R326
1
0R0402-PAD

INR_A

5V_S0

29

FRONTL

SPKR_L+
SPKR_L-

BIAS

C555
SCD1U16V2ZY-2GP

C563
SC1U10V3KX-3GP

R313
0R2J-2-GP
2
DY 1

U54

1
2
3
4
5
6
7
8
9
10
11
12
13
14

INR_A
INR_H
INL_A
INL_H

C553
SC2D2U6D3V3MX-1-GP

1
2

1
2

INL_H

5V_S0

R329
40K2R2F-GP

C557
SC1U10V3KX-3GP

GND
BEEP
AMP_EN#
SET
BIAS
HP_EN
PGND
ROUT+
ROUTPVDD
HVDD
HP_L
HP_R
HVSS
CVSS

VDD
GND
INR_A
INR_H
INL_A
INL_H
PGND
LOUT+
LOUTPVDD
CVDD
CP+
CGND
CP-

HP_EN
AMP_BEEP 29
C554
SCD1U16V2ZY-2GP

29
28
27
26
25
24
23
22
21
20
19
18
17
16
15

R311
0R2J-2-GP
DY 1

AMP_SHUTDOWN# 29,31

SPK_EN#
SET
BIAS
HP_EN

2 R312
1
0R0402-PAD

DY

ALC268_EAPD 29
5V_S0

C570
SC3D3U10V5KX-2GP

R316
30KR2F-GP

INR_H

C566

SPKR_R+
SPKR_R-

R314
10KR2J-3-GP
5V_S0
3D3V_S0

SPKR_L+1
SPKR_R+1

SPK_EN#

C564

FRONTR

R327
40K2R2F-GP

SC10U6D3V5MX-3GP

29

SET
SCD1U16V2ZY-2GP

C569
SC3D3U10V5KX-2GP

INL_A

2 R328
1
0R0402-PAD

SOUNDL

29

3D3V_S0

C546
SC1U10V3KX-3GP
4

Layout Note
C218,C219,C220 near U110
R315
16KR2F-GP

APA2057ARI-TRL-GP

C556
SC1U10V3KX-3GP

Q20
2N7002E-1-GP

.
. .
.

84.2N702.D31

74.02057.01G

SOUNDR

29

C547
SC1U10V3KX-3GP

AMP_SHUTDOWN# 29,31

2nd: 20.F0984.002

SPKR_L_A1

2nd: 22.10251.491
3nd: 22.10147.131

SPKR_R_A1

LINE OUT

U51
SD05C-1-GP

1
B

Wistron Corporation

R309

SPKR_L+1

R310
1KR2J-1-GP

DY DY

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

C552

DY DY SC680P50V2KX-2GP
2

C545

DY

4
3
SRN51J-GP

1
2

22.10133.B21

SPKR_R+1

RN68

SPKR_L_A1
EC105

PHONE-JK235-GP-U2

LINEOUT_JD# 29

SPKR_R_A1

1KR2J-1-GP

TP139
TP138
TP137
TP134
TP129
TP126

LINEOUT_JD#

SC680P50V2KX-2GP

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

NP2
NP1
5
4
3
6
2
1

SC1KP50V2KX-1GP

1
1
1
1
1
1

U53 DY
SD05C-1-GP

DY

LOUT1

LINEOUT_JD#
SPKR_R_A1
SPKR_L_A1
MIC_JD#
AUD_MICIN_R
AUD_MICIN_L

22.10133.B01

D26
1SS400PT

DY
2

1
2

DY

D25
1SS400PT

DY

PHONE-JK233-GP-U3

For ESD

5V_S0

EC102

DY

5V_S0

DY

2nd: 22.10251.511
3nd: 22.10147.151

EC101

20.D0197.102

1
2

1
2

1
2

R302

ACES-CON2-1-GP-U2

DY
SC100P50V2JN-3GP

TP2
TP1
TP11
TP10

EC81

DY
SC100P50V2JN-3GP

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

EC82

DY
SC100P50V2JN-3GP

SC100P50V2JN-3GP

1
1
1
1

EC1

AUD_MIC_L

DY 10KR2J-3-GP

SHIELDING

DY

SPKR_LSPKR_L+
SPKR_RSPKR_R+

R296
10KR2J-3-GP

2
4
EC2

SRN1KJ-7-GP

SC1KP50V2KX-1GP

SPKR_L-

29 AUD_MICIN_L

AUD_MIC_R

3
4

SC1KP50V2KX-1GP

3
1

SPKR_L+

RN66

2
1
1

INTSPK_L1

MIC_JD#

29 AUD_MICIN_R

20.D0197.102

29

ACES-CON2-1-GP-U2

remove to LED Board


NP2
NP1
5
4
3
6
2
1

SC1KP50V2KX-1GP

2
4

Analog Int. Mic

MICIN1

2DY 1

SPKR_R-

MIC IN

EC104

INTSPK_R1

3
1

SHIELDING

Internal Speaker
SPKR_R+

AUDIO AMP AND JACK


Size

Document Number

Rev

-1

Dolomites
Date: Friday, August 22, 2008
D

Sheet
E

30

of

43

3D3V_S0 R233
10KR2J-3-GP
1
2 E51_RxD

16

GPIO74/SDA2
GPIO73/SCL2
GPIO22/SDA1
GPIO17/SCL1

81

NUM_LED

24 BLUETOOTH_EN

SP

GPIO66/G_PWM

28 WIRELESS_EN
16 WLAN_TEST_LED

RN12
E51_TxD
SHBM

-1

SRN4K7J-8-GP

26

SPI

111
113
CCD_ON 112

E51_TxD
E51_RxD
TPAD14-GPTP66
TPAD14-GPTP66

LOW_PWR
SB_ID

LOW_PWR

GPIO77/SPI_DI
GPIO76/SPI_DO/SHBM
GPIO75/SPI_CLK
GPIO81

22,43 S5_ENABLE

GPO83/SOUT_CR/BADDR1
GPIO87/SIN_CR
GPO84/BADDR0

114
14
15

GPIO16
GPIO34
GPIO36/TB3

GPIO34 and GPIO46 swap


VCORF

44

SER/IR

KBC_XO_R2

1
2

1
2

1
2

1
2

GPIO14/TB1
GPIO20/TA2
GPIO56/TA1
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM

13
12
11
10
71
72

GPIO12/PSDAT3
GPIO25/PSCLK3
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1

86
87
90
92

F_SDI
F_SDO
F_CS0#
F_SCK

32KX2
GPIO55/CLKOUT

63
117
31
32
118
62

TPDATA
TPCLK

CRT_DEC# 15
32
32
32
32

PM_SLP_S3# 18,22,28,33,34
KBC_PWRBTN# 16
AC_IN#
41
LID_CLOSE# 14,22

SPIDI
SPIDO
SPICS#
SPICLK

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

54
55
56
57
58
59
60
61

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

1
1
1
1
1
1
1
1

TP54
TP43
TP38
TP55
TP40
TP56
TP39
TP46

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GPC
AFTE14P-GP

VCC_POR#

85

ECRST#

KBC

FIU

DC_BATFULL 16

SPI_WP_R#

3D3V_S0

FRONT_PWRLED 16
STDBY_LED 16
CAP_LED 16
AD_OFF 42
RSMRST#_KBC 18
PM_SLP_S5# 18,28,39
CHARGE_LED 16

3D3V_S0
WPC775L-0DG-GP-U

RN11
SRN10KJ-6-GP

RN61
3D3V_AUX_S5

RN10
SRN10KJ-6-GP

DY

-1

BT_BTN# 16
E-BUTTON# 16
BT_LED
16
BLON_OUT 14,16
WIRELESS_BTN# 16

CRT_DEC#
Volume_Up#
Volume_Down#

18

USB_PWR_EN# 24

3D3V_S0

5
6
7
8

4
3
2
1

ECRST#
MODEL_SEL
KA20GATE
KBRCIN#
Q15
B

SRN10KJ-6-GP
KBC_GPI93
KBC_GPI95
KBC_GPI96

22

1
R231

ECSCI#_1

RSMRST#

MMBT3906-3-GP
84.03906.R11

DY 2 ECSCI#_KBC
0R2J-2-GP
D23

C399

2ND = 84.03906.P11

RN58

18

ECSWI#

GND
GND
GND
GND
GND
GND

SPI_WP# 32

3D3V_S5
3D3V_AUX_S5
SB_ID
S5_ENABLE

ECSWI#_KBC

CH731UPT-GP
83.R0304.A8H

LOW_PWR
1
2KBC_THERMTRIP#
3
4

8
7
6
5

SRN10KJ-6-GP

2ND = 83.R3004.A8E

WPC775L-0DG-GP-U

1
R232

TOUCH PAD

DY

AFTE14P-GPTP125
AFTE14P-GPTP123
AFTE14P-GPTP122
AFTE14P-GPTP124
AFTE14P-GPTP121

RIGHT1
TP_RIGHT

Internal KeyBoard Connector

5V_S0

5V_S0

0R2J-2-GP

1
1
1
1
1

5V_S0
TP_DATA
TP_CLK
TP_LEFT
TP_RIGHT

EC41
EC44
EC46
EC45

1
1
1
1

DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP

KCOL8
KCOL7
KCOL6
KCOL5

EC31
EC30
EC25
EC24

1
1
1
1

DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP

KROW4
KROW3
KROW2
KROW1

EC49
EC48
EC47
EC42

1
1
1
1

DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP

DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP

KCOL12
KCOL11
KCOL10
KCOL9

DY 2

KCOL0 EC26 1

KCOL4
KCOL3
KCOL2
KCOL1

1
27
ETY-CON26-2-GP

2nd: 20.K0251.026
3nd: 20.K0333.026

EC23
EC29
EC28
EC27

1
1
1
1

KCOL17 EC40 1

SC220P50V2JN-3GP

EC35
EC34
EC33
EC32

1
1
1
1

DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP

RN63
SRN10KJ-5-GP

2
1

3
4

TP_DATA
TP_CLK

SRN33J-5-GP-U
TP_RIGHT

12

T/P
TP_LEFT

DY 2

12
11
10
9
8
7
6
5
4
3
2

2nd: 20.K0359.012

<Core Design>

20.K0228.012

EC100

DY

DY

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

SA

Size

A3

KBC WPC775

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

EC99

DY

Wistron Corporation

62.40009.681
1

EC97

SW-TACT-122-GP

ACES-CON12-4-GP-U

20.K0127.026

4
5

13

SC220P50V2JN-3GP

2nd: 62.40009.671

LEFT1
TP_LEFT

EC95

DY

14

RN64

TPDATA
TPCLK

62.40009.681

KROW0
KROW7
KROW6
KROW5

DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP
DY 2SC220P50V2JN-3GP

1
1
1
1

3
SW-TACT-122-GP

TPAD1

SC100P50V2JN-3GP

EC39
EC38
EC37
EC36

SC100P50V2JN-3GP

KCOL16
KCOL15
KCOL14
KCOL13

EC98
SCD1U10V2KX-4GP

1
2

5
EC96
SCD1U10V2KX-4GPDY

EMI Bypass cap.

SC100P50V2JN-3GP

KROW7

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

SC100P50V2JN-3GP

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6

TP47
TP31
TP32
TP45
TP33
TP48
TP34
TP49
TP50
TP35
TP51
TP36
TP37
TP52
TP41
TP53
TP57
TP42

MODEL_SEL

Change to 71.00773.00G

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

PS/2

28

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17

103

KB1

CHG_ON#

KBC_THERMTRIP# 6,22

KBC_GPI95
KBC_GPI96

SPI_WP_R# 2 R234
1
0R0402-PAD

5
18
45
78
89
116

AGND

C66
SCD1U16V2ZY-2GP

1
1
2

VCORF

GPIO

79
30

KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17

4
3

28
28

KBC_GPI93

1
2

SHBM

64
95
93
94
119
6
109
120
65
66
16
17
20
21
22
23
24
25
26
27
28
73
74
75
110

32KX1/32KCLKIN

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

SC1U10V3KX-3GP

DY

84
83
82
91

VCC
VCC
VCC
VCC
VCC

19
46
76
88
115

102
AVCC

SMB

DY

R68
10KR2J-3-GP
1
2 E51_TxD

GPIO01/TB2
GPIO03/AD6
GPIO06
GPIO07/AD7
GPIO23/SCL3
GPIO24
GPIO30
GPIO31/SDA3
GPIO32/D_PWM
GPIO33/H_PWM
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/TRST#
GPIO47/SCL4
GPIO50/TDO
GPIO51/TA3
GPIO52/RDY#
GPIO53/SDA4
GPIO70
GPIO71
GPIO72
GPO82/TRIS#

-1

KBC_CIR

TPAD14-GPTP157
TPAD14-GP
TP157
18,43 PM_PWRBTN#
TPAD14-GP
TP158
29
KBC_BEEP
18
EC_TMR
14
BRIGHTNESS

26 ENERGY_DET

D/A

77

BATTERY----->

68
67
69
70

SMBD_G792
SMBC_G792
41,42
BAT_SDA
41,42
BAT_SCL

KBC_XO

1 10KR2J-3-GP

DY

22
22

GPI94/DA0
GPI95/DA1
GPI96/DA2
GPI97/DA3

101
105
106
107

2 KBC_XI
10MR2J-L-GP

1
R212

29,30 AMP_SHUTDOWN#

AD_IA
41
Volume_Up# 16
Volume_Down# 16

R32

U34B

2ND = 82.30001.691

THERMAL----->

GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05/AD4
GPIO04/AD5

BAT_IN#

4
3

LPC

104
97
98
99
100
108
96

TPAD14-GP
TP61
TPAD14-GP
TP159

12 GMCH_BL_ON

R37
100KR2F-L1-GP

VREF

5V_AUX_S5

4
3
2
1

SC4D7P50V2CN-1GP

LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
INT_SERIRQ
PM_CLKRUN#
KBRCIN#
KA20GATE

A/D

X-32D768KHZ-46GP
82.30001.861

5
6
7
8

C430
1 DY2PCLK_KBC_RC

17,32
17,32
17,32
17,32
17,32
17
17
18
18

3D3V_AUX_S5

X5

4
3
2
1

R227
0R2J-2-GP
DY

VDD

GPIO10/LPCPD#
LRESET#
LCLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
GPIO11/CLKRUN#
KBRST#
GA20
ECSCI#/GPIO54
GPIO65/SMI#
GPIO67/PWUREQ#

5
6
7
8

17,21 PCLK_KBC

80
GPIO41

1
2

124
7
2
3
126
127
128
1
125
8
122
121
ECSCI#_KBC 29
9
ECSWI#_KBC123

PLT_RST1#_1

1
2

1
2

1
2

1
2

1
2
3
4

1
2

8
7
6
5

DY

C386

R214
30KR2F-GP

C407
SC27P50V2JN-2-GP

C388
SCD1U16V2ZY-2GP

12,17,26 PLT_RST1#

U34A

C67
SCD1U16V2ZY-2GP

2 R221
1
0R0402-PAD

BAT_IN#

DY

C405
SCD1U16V2ZY-2GP

42

C421 C414

C390
SCD1U16V2ZY-2GP

LPC_LAD[0..3]

17,32 LPC_LAD[0..3]

C442

3D3V_S0

SC10U10V5ZY-1GP

DY

3D3V_S0

SCD1U16V2ZY-2GP

SMBC_G792
SMBD_G792

C439

1 R75
2
0R0603-PAD

SC10U10V5ZY-1GP

BAT_SCL
BAT_SDA

C128

SCD1U16V2ZY-2GP

DY

C391

SC15P50V2JN-2-GP

C433

DY

C441

SC10U10V5ZY-1GP

SC1U16V3ZY-GP

RN56
SRN4K7J-10-GP

VBAT

3D3V_AUX_S5

SC15P50V2JN-2-GP

VBAT
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

FOR KBC DEBUG


3D3V_AUX_S5

EC90

3D3V_S0

3D3V_AUX_S5

Sheet
1

31

of

-1
43

3D3V_AUX_S5

5
6
7
8

3D3V_AUX_S5

RN59

DY

EC85
SCD1U16V2ZY-2GP

SRN10KJ-6-GP

4
3
2
1

R223
0R0603-PAD

U36
SPI_HOLD#

CS#
DO
WP#
GND

VCC
HOLD#
CLK
DIO

BIOS_VCC
SPI_HOLD#
BIOS_CLK
BIOS_DIO

8
7
6
5

ER1 2
ER2 2

1 0R2J-2-GP
1 0R2J-2-GP

SPICLK
SPIDO

31
31

16M Bits
SPI FLASH ROM
main: 72.25165.A01
2nd: 72.25X16.A01

EC56

DY

SC4D7P50V2CN-1GP

DY

EC53

W25X16VSSIG-GP

72.25X16.001

SC4D7P50V2CN-1GP

DY

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

DY

EC91

EC89

1
2BIOS_DO
33R2J-2-GP SPI_WP#

1
2
3
4

ER3

31

SPICS#
SPIDI
SPI_WP#

31
31

17,31 LPC_LAD[0..3]

LPC_LAD[0..3]

GOLDEN FINGER FOR DEBUG BOARD


TOP VIEW

5V_S0

5V_S0
U20

(B1)

A14

(B2)

17,28 PLT_RST1#_B
17,31 LPC_LFRAME#

LPC_LFRAME#

PCLK_FWH

17,21 PCLK_FWH

(B14)

A1

(B15)

3D3V_S0

R359
100R2J-2-GP

LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
EXT_FWH#

A2

DY

....

....

A15

PCLKFWH

DY C608

3D3V_S0

SC10P50V2JN-4GP

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15

PLT_RST1#_B
LPC_LFRAME#
PCLK_FWH
3D3V_S0
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
EXT_FWH#

TP206 TPAD14-GP

3D3V_S0

FOX-GF30

ZZ.GF030.XXX

(BOTTOM VIEW)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3

Document Number

BIOS

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008

Sheet
1

32

of

-1
43

Aux Power
I min = 150 mA

3D3V_AUX_S5

1
2
3
4

DCBATOUT
RUN_POWER_ON

1
1

R345
100KR2J-1-GP

330KR2J-L1-GP

SCD22U25V3KX-GP

10KR2J-3-GP

3D3V_S0

R339

3D3V_S5

D29
PDZ9D1B-GP

1
2
3
4

83.9R103.C3F

U64
S
S
S
G
AO4468-GP

1D8V_S3

Z_12V_D4

R343
PM_SLP_S3# 18,22,28,31,34

2ND = 84.03400.A37

2
1MR2F-GP

1D8V_S0_ON

C598
SC22P50V2JN-4GP

2N7002EDW-GP
Z_12V_D3

U61
APM2300AAC-TRLGP
84.02300.B31

84.27002.F3F

Z_12V_D3

2
D

DY

8
7
6
5

84.04468.037 2ND = 84.04800.D37

Q22
2N7002-11-GP

D
D
D
D

1D8V_S0

U62

8
7
6
5

3D3V_S0

C593 1

R340

2ND = 84.00610.D31

3D3V_runpwr

D
D
D
D

AO4468-GP

2 R348
1 Z_12V_G3
330KR2J-L1-GP

DY R346
100R5J-3-GP

U60
S
S
S
G

84.04468.037 2ND = 84.04800.D37

2 Z_12V
S
10KR2J-3-GP
Q21
NDS0610-NL-GP
84.S0610.B31

1
R350

DY

2nd source:74.09198.G7F

BC1

C588
SCD1U25V3KX-GP
1 DY2

G909-330T1U-GP
74.00909.03F

GAP-OPEN-PWR

Run Power

NC#4

3D3V_AUX_S5_G 1

VOUT

SC1U16V3ZY-GP

SC1U16V3ZY-GP

DY
2

BC2

5V_S5

5V_S0

G7

VINDY
GND
SHDN#

3D3V_AUX_S5

U4

1
2
3

5V_AUX_S5
D

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3

RUN AND AUX POWER

Document Number

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

33

of

Rev

-1
43

3D3V_S0

4
3

2D5V_S0

RN17
SRN100KJ-6-GP
D

1
2

C163

D9
2D5V_S0_PG

2
BAW56-3-GP
83.00056.K11
1

SC1U10V3ZY-6GP
18,22,28,31,33 PM_SLP_S3#

VCORE_EN 36,38

2ND = 83.00056.G11
R105
37

3V/5V_POK

DY

0R2J-2-GP
R106
1 DY
2

39 1D8V_S3_PWRGD

0R2J-2-GP

P/H @ 1D8V_S3 PAGE


R138
36

VRM_PWRGD

DY

1D1V_PWRGD 38

0R2J-2-GP

1D8V_S3

.
.
. .

Q10

14

3D3V_S5

SB_PWRGD 18
B

D10

RUNPWROK

NB_PWRGD 12,18

U12B

22

2N7002E-1-GP

84.2N702.D31
2ND = 84.2N702.E31

18,22,28,31,33 PM_SLP_S3#
B

38 1D1V_PWRGD

2
BAW56-3-GP
83.00056.K11
1

RUNPWROK_D

TSLVC08APW-1-GP
73.07408.L16

2ND = 73.07408.L15
RUNPWROK_D

PH in page 3

2ND = 83.00056.G11

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

POWER ON LOGIC
Size

A3

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

34

of

-1
43

Adapter
Input Signal
AD_OFF

Input Signal

AD_IN#

(O)

Input Power
AD_JK

Output Signal

Input Signal
VCORE_EN

ENTRIP1

Output Power

PGOOD

Input Power
DCBATOUT

Output Power
VCLK

VIN

CPU_CORE
ISL6265HRTZ

VREG3
VREG5

Input Signal

Output Signal

SVD

VOUT
VRM_PWRGD

PGOOD

CPU_SVC

VOUT

+15V_ALW
3D3V_AUX_S5

Output Power

Input Power
V5FILT
V5DRV
DCBATOUT

1D2V_S0

VTT

V(I)

5V_AUX_S5
3D3V_S5
5V_S5

SVC

DCDC 1D1V(RT8202)

VCORE_EN

ENABLE

DCDC 1D8V(RT8202)

CPU_PWRGD_SVID_REG

PWROK
Input Power

+5V_RUN

Input Signal
PM_SLP_S5#

Output Power

VCC

DCBATOUT

VCC_CORE(O)

VIN

VCC_CORE(O)
VCC_CORE(O)

Input Signal

EN_PSV

1D2V_PWRGD

PGOOD

Input Power

5V_S5

Output Power

V5IN

VCC_CORE1
DCBATOUT
VDDNB

VTT

G9161
PM_SLP_S5#

+5V_SUS
1D8V_S3

PGOOD

EN_PSV

Input Signal

1D1V_PWRGD

Output Power

V5FILT
VTT

V5DRV

V(I)

DCBATOUT

RT9026

1D2V_S0

V(I)

CHARGER MAX8731

Output Signal

LDO_SHDN#

Output Signal

1D8V_S3_PWRGD
Input Power

VCC_VORE0

Output Signal

Input Signal

Output Signal

0D9V LDO
1D2V LDO

1D2V_PWRGD
PGOOD

EN_PSV

3V/5V OK
5V_S5

CPU_SVD

Output Signal

ENTRIP2

AD+

VCC(O)

VCC(I)

DCDC 1D2V(RT8202)

EN0
S5_ENABLE

DCDC 5V/3D3V(TPS51125)

Output Signal

(I)

Input Signal
MAX8731A ACIN

LDO_POK

Output Signal

ACIN
MAX8731A ACOK

5V_S5
Input Power
3D3V_S5

IN

Output Power
OUT

Input Power

Output Power

VIN
1D2V_S5

1D8V_S3

PBAT_SMBDAT

LDO_OUT

0D9V_S3

PBAT_SMBCLK

LDO_OUT

VLDOIN

ACOK

SDA
SCL
Input Power

1D5V LDO
2D5V LDO
Input Signal

R9161

G9571

Input Signal

Input Power
Input Power
IN

3D3V_AUX_S5

Output Signal

3D3V_S0

AD+

Output Signal

Output Power
OUT

3D3V_S0
2D5V_S0

Output Power

IN

OUT

Output Power

DCIN
VDDSMB

<Core Design>

1D5V_S0

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3

Power Block Diagram


Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

+VCHGR

V(O)

Sheet
1

35

of

-1
43

1 R80
26265_FB_NB_R
1
44K2R2F-1-GP
C136

GNDA_VCORE

6265_OFS/VFIXEN

DY

2 R264
1
0R2J-2-GP

DY

R278
1KR2F-3-GP
1
2

2
SC1KP50V2KX-1GP

3D3V_S0

R287

2 R286
1
316KR2F-GP

C496
1
2

6265_FB1_R
1
C499

2 R283
1
0R2J-2-GP

DY

R289
2
DY 2 1 DY
10R2F-L-GP NTC-10K-9-GP
ISP1_R
ISN1
2
G39

2
SC1KP50V2KX-1GP
C497

54K9R2F-L-GP SC1KP50V2KX-1GP

DY

ISP1

C494 SC180P50V2JN-1GP
1
2DY

R280
C498
C493
1
2
1
2
1
2
249R2F-GP
SC4700P50V2KX-1GP SC180P50V2JN-1GP

R274

1
2
6K81R2F-1-GP
SC180P50V2JN-1GP

6265_FB0_R
1
C484

1
2

1
2

1
2

1
2

1
2

5
6
7
8
G
S
S
S

1
2

G
S
S
S

4
3
2
1

S
S
S
G

1
2
54K9R2F-L-GP

2 R96
1
910KR2J-GP

6265_FB1_C

ESR=15mohm
B

TC18
SE330U2VDM-L-GP

1
2

1
2

1
2
R279
4K02R2F-GP
1
2
C495 SCD1U16V2KX-3GP

AOL1412-GP
S
S
S
G

3D3V_S0

4
3
2
1
1

2
5
6
7
8

1
AOL1412-GP

4
3
2
1

5
6
7
8

1
2

Close to
CPU socket

R282

R104
C487
C488
1
2
1
2
1
2
1
2
249R2F-GP
C490 SC1KP50V2KX-1GP
SC4700P50V2KX-1GP SC180P50V2JN-1GP

TC17 TC4
SE330U2VDM-L-GP

Parts
close to
PWM IC

SE330U2VDM-L-GP

U41

LGATE1
C491 SC180P50V2JN-1GP
1
2 DY

TC20

VCC_CORE_S0_1
Design Current: 12.6A
Peak current: 18A
OCP_min:24A

VCC_CORE_S0_1

1
2
IND-D36UH-9-GP
R276
16K2R2F-GP

D
D
D
D

R121
10R2F-L-GP

D
D
D
D

R122
10R2J-2-GP

BOOT1 1
2
C166
SCD22U10V3KX-2GP
U11

Parallel

L26
PHASE_NB 1
2
IND-4D7UH-88-GP
68.4R710.20D

LGATE_NB

L25

UGATE1
PHASE1

6 CPU_VDD1_RUN_FB_L
6 CPU_VDD1_RUN_FB_H

1
2

5
6
7
8
4
3
2
1

1
2

1
2

DY 0R2J-2-GP

C502
SCD1U25V3KX-GP

DY

C505
SC10U25V6KX-1GP

C504
SC10U25V6KX-1GP

C503
SC10U25V6KX-1GP

U43
AOL1426-GP

R126

C514

VDDNB: Design Current: 2.1A


Peak current: 3A OCP_min:5A

DCBATOUT_6265_2
ISN1
ISP1

6 CPU_VDD0_RUN_FB_H
6 CPU_VDD0_RUN_FB_L

C485
1
2

UGATE_NB
BOOT_NB 1
2
C462
SCD22U10V3KX-2GP

S
S
S
G

R120
10R2J-2-GP

C512

VDDNB
C486
SC2D2U10V3KX-1GP

D
D
D
D

R119
10R2J-2-GP

Close to
CPU socket

R101

D
D
D
D
LGATE1
PHASE1
UGATE1
BOOT1

U44
SI4800BDY-T1
84.04800.D37

6265_VDIFF1
6265_FB1
6265_COMP1
6265_VW1

ISP0
ISN0

1D8V_S3
VCC_CORE_S0_0
VCC_CORE_S0_1

1KR2F-3-GP
1 R102
2

2
ISP0

5V_S0
LGATE0

74.06265.073

change to 74.06265.A73

U46
SI4800BDY-T1
84.04800.D37

ISP0
ISN0
VSEN0
RTN0
RTN1
VSEN1
VDIFF1
FB1
COMP1
VW1
ISP1
ISN1

U38

BOOT_NB
BOOT0
UGATE0
PHASE0

36
35
34
33
32
31
30
29
28
27
26
25

4
3
2
1

BOOT_NB
BOOT0
UGATE0
PHASE0
PGND0
LGATE0
PVCC
LGATE1
PGND1
PHASE1
UGATE1
BOOT1

13
14
15
16
17
18
19
20
21
22
23
24

IC CTRL ISL6265HRTZ-T QFN 48P

GNDA_VCORE

6265_FB0_C

2
4
3
2
1

C511

DY

SE220U2VDM-8GP

1
GAP-CLOSE-PWR-3-GP

5
6
7
8

OFS/VFIXEN
PGOOD
PWROK
SVD
SVC
ENABLE
RBIAS
OCSET
VDIFF0
FB0
COMP0
VW0

G11

CPU_VDDNB_RUN_FB_L

ISP0_R
ISN0
2
G12

D
D
D
D

1
2

1
2
3
4
5
6
7
8
9
10
11
12

CPU_PWRGD_SVID_REG
6265_SVD
1 0R0402-PAD
2
6265_SVC
1 0R0402-PAD
2
6265_ENABLE
1 0R0402-PAD
2
6265_RBIAS
1
2
93K1R2F-L-GP
6265_OCSET
6265_VDIFF0
6265_FB0
6265_COMP0
6265_VW0

GAP-CLOSE-PWR-3-GP

R247 2
1
0R0402-PAD

SCD1U25V3KX-GP

GNDA_VCORE

UGATE_NB

CPU_VDDNB_RUN_FB_L_R

R862 close
to L75

SC10U25V6KX-1GP

R98

1
2
R100 23K7R2F-GP

LGATE0

SC10U25V6KX-1GP

GNDA_VCORE
R92
R93
R95

4
3

SRN10J-7-GP

1 R135
2
4K02R2F-GP
1
2
C177 SCD1U16V2KX-3GP
R136
R240
1
2
DY 2 1 DY
10R2F-L-GP
NTC-10K-9-GP

DCBATOUT_6265_0
GNDA_VCORE

R84 DY
0R2J-2-GP

R90
10KR2F-2-GP

1
2

PHASE_NB

0R2J-2-GP

6265_OCSET_NB

DY R254

3D3V_S0

34 VRM_PWRGD
6 CPU_PWRGD_SVID_REG
6
CPU_SVD
6
CPU_SVC
34,38 VCORE_EN

6265_VIN
6265_VCC
6265_FB_NB
6265_COMP_NB
6265_FSET_NB
6265_VSEN_NB

CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L

C478
SCD1U25V3KX-GP

RN13

TC11
SE330U2VDM-L-GP

3D3V_S0

PHASE_NB
1 R245
2
11K3R2F-2-GP
LGATE_NB

TC12
SE330U2VDM-L-GP

R85
0R0603-PAD

DY

VDDNB

1 R89
2R3J-GP

TC2

Parts
close to
PWM IC

SE330U2VDM-L-GP

R94
10KR2F-2-GP

U10
AOL1412-GP

S
S
S
G

GAP-CLOSE-PWR

L24
68.R3610.20C
1
2
IND-D36UH-9-GP
R103
16K2R2F-GP

D
D
D
D

CPU_VDDNB_RUN_FB_H

S
S
S
G

5V_S0

BOOT0 1
2
C481
SCD22U10V3KX-2GP
U39
AOL1412-GP

D
D
D
D

R2461 0R0402-PAD
2

DCBATOUT_6265_3

GAP-CLOSE-PWR
G34
1
2

UGATE0
PHASE0

GNDA_VCORE

GNDA_VCORE

VCC_CORE_S0_0

2
SCD1U10V2KX-4GP

1 R81
2
22KR2F-GP

C459
SC1U10V3KX-3GP

VCC_CORE_S0_0
Design Current: 12.6A
Peak current: 18A
OCP_min:24A

2R3J-GP

1
C138

C474

5
6
7
8

GAP-CLOSE-PWR

GAP-CLOSE-PWR
G38
1
2

2
SC1KP50V2KX-1GP

R244

C476

5
6
7
8

5V_S0

U37
AOL1426-GP

C135 SC180P50V2JN-1GP
1
2

5
6
7
8

GAP-CLOSE-PWR
G40
1
2

2
SC33P50V2JN-3GP

4
3
2
1

1
C142

C477

DY

49
48
47
46
45
44
43
42
41
40
39
38
37

1
2

1
2

GAP-CLOSE-PWR
G42
1
2

GAP-CLOSE-PWR
G37
1
2

C475

SCD1U25V3KX-GP

GAP-CLOSE-PWR

SC10U25V6KX-1GP

GAP-CLOSE-PWR
DCBATOUT
DCBATOUT_6265_1
G36
1
2

DCBATOUT_6265_1

SC10U25V6KX-1GP

GAP-CLOSE-PWR
G46
1
2

DCBATOUT_6265_3

SC10U25V6KX-1GP
D
S
D
S
D
S
D
G

GAP-CLOSE-PWR
G48
1
2

G35

GAP-CLOSE-PWR
G41
1
2

TC16
SE100U25VM-L1-GP

SE100U25VM-L1-GP

GAP-CLOSE-PWR
G49
1
2

TC19

DCBATOUT

G43

G50

DCBATOUT_6265_2

4
3
2
1

DCBATOUT

DCBATOUT_6265_0

GND
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB

DCBATOUT

R858 close
to L77
<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

GAP-CLOSE-PWR-3-GP
Title

1 R281

CPU Vcore(ISL6265HR)
Size

6K81R2F-1-GP

A3

2
SC180P50V2JN-1GP

Document Number

Rev

Cathedral Peak 2A

Date: Friday, August 22, 2008


3

Sheet
1

36

of

-1
43

DCBATOUT_51125_3V

3D3V_PWR

5V_AUX_S5

3D3V_PWR

Q11
2N7002E-1-GP

84.2N702.D31

.
. .
.

R158
143KR2F-GP

DY

22 S5PWR_ENABLE

84.27002.F3F

51125_ENTIP2
C255

5V_PWR

GAP-CLOSE-PWR
G84
1
2
GAP-CLOSE-PWR
G81
1
2

GAP-CLOSE-PWR

GAP-CLOSE-PWR
G82
1
2

DCBATOUT_51125_5V

GAP-CLOSE-PWR
G83
1
2

DCBATOUT_51125_5V

DCBATOUT_51125_3V

GAP-CLOSE-PWR

SKIPSEL

VCLK

18

1
R320

Close to VFB Pin (pin5)


3D3V_AUX_S5

0R2J-2-GP

0R2J-2-GP

1
R333

DY

1
R334

1
2

4
3
2
1

DY

TP205
TPAD14-GP
C562
SC18P50V2JN-1-GP

5V_AUX_S5

R325
30KR2F-GP

51125_FB1_R

DY

G70

3V/5V_POK

3V/5V_POK 34

GAP-CLOSE-PWR-3-GP

R321
20KR2F-L-GP

Close to VFB Pin (pin2)

C580
SC10U6D3V5KX-1GP

DY

SC10U6D3V5KX-1GP

0R2J-2-GP

51125_VCLK

R322
0R2J-2-GP

2
1

GAP-CLOSE-PWR-3-GP

C565
51125_VREF

Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm

1 2

74.51125.073

2
1
0R2J-2-GP

DY

VREG5

VREG3

TPS51125RGER-GP

G
S
S
S

2
GND

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

1
R332

Title
Size

A3

DCDC 5V/3D3V_TPS51125

Document Number

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

TC27
ST220U6D3VDM-15GP

TONSEL

25

DY

15

51125_ENTIP1

17

51125_SKIPSEL

R324

0R2J-2-GP

GND

G65

3D3V_AUX_S5

23

VREF

3D3V_AUX_S5

51125_VREF

SI4812BDY-T1-E3-GP

C587

14

D
D
D
D

5
6
7
8
4

ENTRIP2

5V_AUX_S5_51125

51125_FB2_R
C560

51125_TONSEL

G64

Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm

3
C561

PGOOD
ENTRIP1

EN0

U58

51125_FB1

5V_PWR

8
7
6
5

51125_FB2
5
2
1
DYR331
0R2J-2-GP
51125_EN
1
2
13
R330
820KR2F-GP
51125_ENTIP2 6
51125_VREF

VFB1

L30

Iomax=6A

1
2
IND-3D3UH-57GP

VFB2

51125_VO1

1
2
5
6
7
8

24

D
D
D
D

VO1

Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A

G
S
S
S

VO2

51125_VO2

0R2J-2-GP

1 2

51125_DRVL1

3D3V_AUX_S5_5_51125 8

1
1

19

DRVL2

SCD22U6D3V2KX-1GP

DRVL1

LL2

12

DRVH2

51125_LL1

51125_DRVL2

1
2
3
4

1
2

1
2

LL1

20

11

VBST1

SCD1U10V2KX-4GP

21

10

G
S
S
S

SI4812BDY-T1-E3-GP

DRVH1

51125_DRVH1

51125_LL2

DYSC18P50V2JN-1-GP

R319
10KR2F-2-GP

51125_VBST1 1

SCD1U25V3KX-GP 51125_DRVH2

D
D
D
D

R323
6K65R2F-GP

22

VBST2

51125_VBST2 9

4
3
2
1

C568
1

Id=7A
Qg=8.7~13nC
Rdson=23~30mohm G

3D3V_AUX_S5

DYR318

C572
SCD1U25V3KX-GP

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

ST220U6D3VDM-15GP

SCD1U10V2KX-4GP

G63

U57

VIN

1
2
3
4

TC29

16

8
7
6
5

1
2

S
L29

DY

U59
SI4800BDY-T1

C586
SCD1U25V3KX-GP

SI4800BDY-T1

1
2
IND-3D3UH-57GP
C595

C582

DY

SC10U25V6KX-1GP

U55

C584
SC10U25V6KX-1GP

U56

DY

G
S
S
S

3D3V_PWR

Id=7A
Qg=8.7~13nC
Rdson=23~30mohm

D
D
D
D

Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U25V3KX-GP

Iomax=6A

C583

C576
SCD01U50V2KX-1GP

C581

SC4D7U25V5KX-GP

C579

DY

GAP-CLOSE-PWR
G86
1
2

GAP-CLOSE-PWR

C585

G85

GAP-CLOSE-PWR
G74
1
2

5V_S5

R156
143KR2F-GP

DY
2

2N7002EDW-GP
C264

GAP-CLOSE-PWR
G92
1
2

GAP-CLOSE-PWR
G75
1
2

SE100U25VM-L1-GP

GAP-CLOSE-PWR
G87
1
2

DCBATOUT_51125_5V

S5PWR_PH1
51125_ENTIP1

GAP-CLOSE-PWR
G88
1
2

G76

Q12

SC18P50V2JN-1-GP

DCBATOUT

3V/5V_POK

GAP-CLOSE-PWR
G89
1
2

GAP-CLOSE-PWR
G80
1
2

RN43
SRN100KJ-6-GP

GAP-CLOSE-PWR
G90
1
2

GAP-CLOSE-PWR
G79
1
2

GAP-CLOSE-PWR

TC26

4
3

1
2

2
D

G91

SC18P50V2JN-1-GP

SE100U25VM-L1-GP

TC24

3D3V_S5

G78

DCBATOUT

Sheet
1

37

of

Rev

-1
43

DCBATOUT_8202_1D1V
DCBATOUT_8202_1D1V
G25

NC#5
NC#14

RT8202_BST_1D1V_L 1
RT8202_DH_1D1V
1R2F-GP
RT8202_LX_1D1V
RT8202_DL_1D1V
R7

10
3

RT8202_OC_1D1V 1
2
RT8202_FB_1D1V
6K2R2F-GP
1D1V_PWR

VOUT

1
2

1
1

1
2

Fujitsu OS-CON
6.3*5.7mm
330uF, 2.5V,14mohm
C

Vout=0.75*(1+Rh/Rl)=1.10625V
DCBATOUT_8202_1D2V
1D2V_PWR

5
14

NC#5
NC#14

RT8202APQW-GP

BOOT
UGATE
PHASE
LGATE

13
12
11
8

RT8202_BST_1D2V_L 1
RT8202_DH_1D2V
1R2F-GP
RT8202_LX_1D2V
RT8202_DL_1D2V
R165

OC
FB

10
3

RT8202_OC_1D2V 1
2
RT8202_FB_1D2V
6K2R2F-GP
1D2V_PWR

VOUT

1
2

2
1
2

2
G
S
S
S

4
3
2
1

RT8202_FB_1D2V

RT8202_DL_1D2V

GAP-CLOSE-PWR
G77
1
2

TC25

GAP-CLOSE-PWR
G66
1
2
GAP-CLOSE-PWR

R167
10KR2F-2-GP

C288

2RT8202_LX_1D2V

C267

1
1

5
6
7
8
D
D
D
D

1
2

1
VDDP

2
VDD

EN/DEM

PGND

15

C285

DY SCD1U25V3ZY-1GP
A

TON
PGOOD

R166
6K04R2F-GP

SCD1U25V3KX-GP

Vout=0.75*(1+Rh/Rl)=1.10625V
RT8202_LX_1D2V

<Core Design>

GND
GND

RT8202_EN_1D2V

16
4

R163

GAP-CLOSE-PWR
G73
1
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

17
6

RT8202_PGOOD_1D2V

C295
SC1U10V3ZY-6GP

U17

DY

2 R162
1
0R0402-PAD

VCORE_EN

1
2
1

2 R170
1
0R0402-PAD

RT8202_BST_1D2V

R171
10KR2F-2-GP

5V_S5

C287
SC1KP50V2KX-1GP

GAP-CLOSE-PWR
G72
1
2

C291
SC47P50V2JN-3GP

CH521S-30-GP-U1
RT8202_TON_1D2V

Iomax=4A
OCP>8A

SE220U2VDM-8GP

3D3V_S0

GAP-CLOSE-PWR
G71
1
2

IND-3D3UH-57GP
U19
SI4800BDY-T1

D12

1 R161
2
1MR2F-GP

GAP-CLOSE-PWR
G69
1
2

1
2

C289
SC1U10V3ZY-6GP

GAP-CLOSE-PWR
G67
1
2

Voutsetting=1.203V1D2V_PWR

5V_S5

1D2V_S0
Iomax=3.35A

SCD1U10V2KX-4GP

DCBATOUT_8202_1D2V

C296

L28

RT8202_LX_1D2V
RT8202_VDD_1D2V

5
6
7
8
D
D
D
D
G
S
S
S

4
3
2
1

RT8202_DH_1D2V

C297

SCD1U50V3KX-GP

5V_S5

C294
SC100P50V2JN-3GP

C298

SC10U25V6KX-1GP

U18
SI4800BDY-T1

GAP-CLOSE-PWR
G18
2
1

GAP-CLOSE-PWR
G19
2
1

1D2V_PWRGD

1D2V_S0
G68

GAP-CLOSE-PWR
G20
2
1

D
D
D
D

R22
10KR2F-2-GP
RT8202_LX_1D1V

R164
10R2F-L-GP

34,36

TC7
SE220U2VDM-8GP

GAP-CLOSE-PWR

1D2V_PWRGD

RT8202_FB_1D1V

RT8202_DL_1D1V

SC10U25V6KX-1GP

TC5
ST15U25VDM-1-GP

DY

D
D
D
D

4
3
2
1
5
6
7
8

G21

C36
SC47P50V2JN-3GP

2RT8202_LX_1D1V

C327

17
6

C14

R21
4K75R2F-1-GP

OC
FB

RT8202APQW-GP

DCBATOUT_8202_1D2V

IND-2D2UH-46-GP-U
U24
SI4812BDY-T1-E3-GP

SCD1U25V3KX-GP

13
12
11
8

1D1V_S0

5
14

BOOT
UGATE
PHASE
LGATE

1D1V_PWR

L18

EN/DEM

RT8202_LX_1D1V

15

PGND

2
DCBATOUT

VDDP

TON
PGOOD

RT8202_DH_1D1V

CH521S-30-GP-U1

R9

C24

DY SCD1U25V3ZY-1GP

C11
SC1U10V3ZY-6GP

2
RT8202_EN_1D1V

2 R14
1
0R0402-PAD

16
4

D7

GND
GND

RT8202_PGOOD_1D1V

VDD

U1

DY

1D2V_PWRGD

1D2V_PWRGD

2 R198
1
0R0402-PAD

1
C377
SC100P50V2JN-3GP

1
2

1D1V_PWRGD

5V_S5

C31
SC1KP50V2KX-1GP

Iomax=7.5A
OCP>11A

SCD1U10V2KX-4GP

R197
10KR2F-2-GP

RT8202_TON_1D1V

RT8202_BST_1D1V

1 R16
2
1MR2F-GP

C332

5
6
7
8

3D3V_S0

G
S
S
S

DCBATOUT_8202_1D1V

5V_S5

C37
SC1U10V3ZY-6GP

C335

GAP-CLOSE-PWR

G
S
S
S

RT8202_VDD_1D1V

4
3
2
1

GAP-CLOSE-PWR
G22
2
1

34 1D1V_PWRGD

C334

DY

U23
SI4800BDY-T1

2
1
R20
10R2F-L-GP

GAP-CLOSE-PWR
G23
2
1

GAP-CLOSE-PWR
G27
2
1

SCD1U50V3KX-GP

ST15U25VDM-3-GP

5V_S5

SC10U25V6KX-1GP

TC6

-1

-1
1

SC10U25V6KX-1GP

DCBATOUT

Title
Size

A3

DCDC_RT8202_1D1V/1D2V

Document Number

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

38

of

Rev

-1
43

DCBATOUT

DCBATOUT_8202_1D8V

1D8V_PWR

DCBATOUT_8202_1D8V

1
1

GAP-CLOSE-PWR
G57
1
2

2
5
6
7
8
D
D
D
D
G
S
S
S

R292
10R2F-L-GP

RT8202_DH_1D8V

GAP-CLOSE-PWR
G56
1
2

5V_S5

2 R303
1RT8202_EN_1D8V
0R0402-PAD
C522
DY SCD1U25V3ZY-1GP

TON
PGOOD

15

EN/DEM

BOOT
UGATE
PHASE
LGATE

13
12
11
8

OC
FB

10
3

16
4

NC#5
NC#14

RT8202APQW-GP

RT8202_OC_1D8V 1
2
RT8202_FB_1D8V
6K2R2F-GP
1D8V_PWR

2
1

1
2

1
2

GAP-CLOSE-PWR
G62
1
2
GAP-CLOSE-PWR
G55
1
2
GAP-CLOSE-PWR

R143
10KR2F-2-GP

1
2
3

C214
SCD1U25V3KX-GP

RT8202_LX_1D8V

RT8202_FB_1D8V

Fujitsu OS-CON
6.3*5.7mm
470uF, 2.5V,13mohm

R142
14KR3F-GP

2
R152
RT8202_BST_1D8V_L 1
1R2F-GP
RT8202_DH_1D8V
RT8202_LX_1D8V
RT8202_DL_1D8V
R153

RT8202_DL_1D8V

C202
SC47P50V2JN-3GP

TC22
SE330U2D5VDM-1GP

SI4634DY-T1-E3-GP

RT8202_LX_1D8V

Vout=0.75*(1+Rh/Rl)=1.800V

GND
GND

PGND

VOUT

5
6
7
8

C559

17
6

5
14

C523
SC1U10V3ZY-6GP

RT8202_PGOOD_1D8V

VDD

U45

VDDP

2 R291
1
0R0402-PAD

C517
SC1KP50V2KX-1GP

DY

18,28,31 PM_SLP_S5#

5V_S5

1
2
1
C510
SC100P50V2JN-3GP

820KR2F-GP
R290
10KR2F-2-GP

U50

RT8202_TON_1D8V

D11
CH521S-30-GP-U1
RT8202_BST_1D8V

34 1D8V_S3_PWRGD

R293

C509
SC1U10V3ZY-6GP

SCD1U10V2KX-4GP

3D3V_S5

GAP-CLOSE-PWR
G61
1
2

IND-2D2UH-44-GP

RT8202_VDD_1D8V

DCBATOUT_8202_1D8V

1D8V_PWR

GAP-CLOSE-PWR
G60
1
2

Iomax=11A
OCP>16A

L27

RT8202_LX_1D8V

DY

4
3
2
1

5V_S5

GAP-CLOSE-PWR

C540

U49
SI4800BDY-T1

GAP-CLOSE-PWR
G51
2
1

-1

C542

SCD1U50V3KX-GP

TC21

C541

SC10U25V6KX-1GP

GAP-CLOSE-PWR
G52
2
1

GAP-CLOSE-PWR
G58
1
2

-1
SC10U25V6KX-1GP

SE100U25VM-L1-GP

GAP-CLOSE-PWR
G53
2
1

1D8V_S3
G59

G54

DDR_0.9V
Iomax=1.5A
OCP>3A

2
1

C279
SC10U10V5KX-2GP

DDR_VREF_PWR
C281
G13
SCD1U10V2KX-4GP
1
2

C293
SC1U16V3KX-2GP

1D8V_S3

5V_S5

1
C283
SC10U10V5KX-2GP

GAP-CLOSE-PWR

RT9026PFP-GP

11

C292
SCD1U10V2KX-4GP

GAP-CLOSE-PWR
G14
1
2

1
2
3
4
5

VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS
GND

10
9
8
7
6

DDR_VREF_S3

9026_S5
2 R169
1
0R0402-PAD
9026_S3
2 R168
1
0R0402-PAD

0D9V_S3

GAP-CLOSE-PWR
G15
1
2

U15

18,28,31 PM_SLP_S5#

C286
SC10U10V5KX-2GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

A3

DCDC_1D8V_RT8202/LDO 0D9V
Document Number

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

39

of

Rev

-1
43

1D5V_S0
Iomax=1A

G957

1D5V_S0_LDO

1D5V_S0
G16

1
C290

GAP-CLOSE-PWR-3-GP
G17
1
2

SC10U6D3V5KX-1GP

U16

GAP-CLOSE-PWR-3-GP

3
2
1

3D3V_S0

VOUT
GND
VIN

C284
SC1U10V3KX-3GP

G957T65UF-GP

74.95765.03C

1D2V_S5
Iomax=400mA

For MINI Card.NEW Card power SW

3D3V_S5

1D2V_S5

DY

1
2

IN
GND
OUT

1
2
3

1
2

G9161-120U65U-GP

74.09161.E3C

C113
SC10U6D3V5KX-1GP

C112

U6

SC10U6D3V5KX-1GP

DY

SC10U10V5KX-2GP

SC1U10V3KX-3GP

C116
C110

Place near to SB700

2D5V
Iomax=0.2A
3D3V_S0

2D5V_LDO

U47

G47

3
2
1

VOUT
VIN
GND

2D5V_S0

GAP-CLOSE-PWR-3-GP
C518

SC22U6D3V5MX-2GP

SC1U10V3ZY-6GP

RT9161-A-25PG-GP

C538

Place near to CPU

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

LDO 2D5V/1D5V/1D2V_S5

Document Number

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

40

of

Rev

-1
43

AD+

1
2
3
4

DCBATOUT

R192
100KR2J-1-GP

AO4433-GP

R10
1

AD+_TO_SYS

AD+_G_2

GAP-CLOSE-PWR

R189
470KR2J-2-GP

G3

BT+_R

CCV
CCI
CCS
REF
DAC
GND

MAX8731A_REF

RN6
SRN100KJ-6-GP

FBSA

1
2

1
2

1
2

G
S
S
S

15

BATT_SENSE 42

MAX8731A_CSIP

100R2F-L1-GP-U
C338
SCD1U25V2ZY-1GP

74.08731.A73

MAX8731A_CSIN
MAX8731AETI-GP

CHG_AGND

2
R194
0R0402-PAD

1
2

CHG_AGND

Q3
2N7002E-1-GP

.
.
. .

84.2N702.D31

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

C25
SC1U10V3KX-3GP

AC_IN#

31

AC_IN#

C7

1
CHG_AGND

4
3

3D3V_AUX_S5

GND

C373

BATT_SENSE_R

C350

R182

29

1
2

1
2

C375

C371

SCD1U25V2ZY-1GP

C372

SC1U10V3KX-3GP

MAX8731A_CCV
MAX8731A_CCI
MAX8731A_CCS
MAX8731A_REF
MAX8731A_DAC

SCD01U50V2ZY-1GP

2
4K7R2F-GP

SCD01U50V2ZY-1GP

C23
SCD01U50V2ZY-1GP

10KR2F-2-GP

C361
SC220P50V2KX-3GP

R187

1MAX8731_CCV1

R12
B

16

FBSB

GAP-CLOSE-PWR

4
3
2
1

6
5
4
3
7
12

GAP-CLOSE-PWR

C331

SCD1U50V3KX-GP

INP

C333

SC10U25V6KX-1GP

C330

SC10U25V6KX-1GP

18
17

G2

SC10U25V6KX-1GP

2 R188
1
0R0402-PAD

AD_IA

CSIP
CSIN

G1

U25
SI4800BDY-T1

SC10U25V6KX-1GP

CHG_AGND
MAX8731A_IINP

BATSEL

14

1
D
D
D
D

MAX8731A_LOW_G

D01R2512F-4-GP

19

IND-5D6UH-39-GP

PGND

MAX8731A_LX1_R
SCD1U50V3KX-GP

20

C353

R5
1

DLO

BT+
L19

23

SDA

CHG_AGND
CHG_AGND

MAX8731A_HIGH_G
R183 1R3F-GP
MAX8731A_LX1
1
2
1
2
C339
SC220P50V2KX-3GP

1
2

SCL
LX

31,42 BAT_SDA

SC1U10V3KX-3GP

BAT54PT-GP

24

MAX8731A_BST

DHI

C336
1
2

ACOK

AC_OK 2 R184
1 MAX8731A_ACOK 13
C358
0R0402-PAD
SC1U10V3KX-3GP
10
31,42 BAT_SCL

MAX8731A_VDDP

5
6
7
8

25
21

D
D
D
D

BST
LDO

D4

U30
SI4800BDY-T1

G
S
S
S

MAX8731A_CSSN
MAX8731A_VCC

4
3
2
1

ASNS

CSSN
VCC

27
26

VDD

28

TC9

DY ST15U25VDM-1-GP

5
6
7
8

11

CSSP

C349

DY

SCD1U25V2ZY-1GP

ACIN

C346
SC10U25V6KX-1GP

DCIN

C347
SC10U25V6KX-1GP

22

MAX8731A_ACIN

C360
SC10U25V6KX-1GP

MAX8731A_DCIN

1
2 SC1U10V3KX-3GP
R181
33R2F-3-GP
2

CHG_AGND
C356
1

U26

3D3V_AUX_S5

DCBATOUT

CHG_AGND

C370
SCD01U50V2KX-1GP

C359
SCD1U50V3KX-GP

AC_OK

C363
SCD1U50V3KX-GP
2
1 MAX8731A_CSSP

SC1U25V0KX-GP

R13
365KR3F-GP

GAP-CLOSE-PWR

G4

AD+
C337

84.27002.F3F

31

8
7
6
5

D18
1SS4000GPT-GP

Q14
2N7002EDW-GP

R191
49K9R2F-L-GP

D
D
D
D

AO4433-GP
C368
SCD1U25V2ZY-1GP

DC_IN_D

U27
S
S
S
G

AD+

R193
10KR2F-2-GP

AD+_G_1

1
2
3
4

AD+

D01R2512F-4-GP

2
R185
10KR2F-2-GP

BT+

U29
S
S
S
G

D
D
D
D

8
7
6
5

Title

AC_OK

Charger MAX8731
Size

A3

Document Number

Rev

Date: Friday, August 22, 2008


5

-1

Cathedral Peak 2A
Sheet
1

41

of

43

Adaptor in to generate DCBATOUT

7
5
4
3
2

AD+

D19

AD+_2

C13
SC1U50V5ZY-1-GP

E
C

R1

PDTA124EU-1-GP

R6
100KR2J-1-GP

Q1
AFTE14P-GP
AFTE14P-GP

31

R1

E
R2
PDTC124EU-1-GP

AD_OFF

TP12
TP13

8
7
6
5

R2

Q2
AD_OFF#_JK

2nd: 20.F1170.005

D
D
D
D

AO4433-GP

R8
200KR2F-L-GP

U28
S
S
S
G

83.P6SBM.AAG

P6SBMJ24APT-GP

SA

1
1

1
2
3
4

K
C10
SCD1U50V3ZY-GP

20.F1002.005

1
6
ACES-CON5-7-GP-U1

SCD1U50V3KX-GP

DY

AD_JK
EC10

AD_JK
AD_JK

AD_JK

DC1

R25
1KR2F-3-GP

BATTERY CONNECTOR

BATA_SDA_1
BATA_SCL_1
BAT_IN#_1
BT+
BT+

D6
BAV99PT-GP-U

9
8
7
6
5
4
3
2
1

RN3

1
2
3
4

31,41 BAT_SDA
31,41 BAT_SCL

8
7
6
5

BATA_SDA_1
BATA_SCL_1
BAT_IN#_1

SRN33J-7-GP

BT+

41 BATT_SENSE

DY

DY EC7
2

EC8

1
2

1
2

1
2

K
A

DY EC9

SC10P50V2JN-4GP

DY EC6

SC10P50V2JN-4GP

EC4
SCD1U50V3ZY-GP

SC1000P50V3JN-GP

DY

SC1000P50V3JN-GP

D2
MMPZ5232BPT-GP

EC5
SCD1U50V3ZY-GP

BAT_IN#

31

AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP

1
1
1
1
1

TP7
TP8
TP9
TP6
TP5

BAT1

DY

DY

D5
BAV99PT-GP-U

DY
3

D3
BAV99PT-GP-U

3D3V_AUX_S5

GND
GND
GND
GND
DAT
CLK
BAT_IN
BT+2
BT+1

ALP-CON7-9-GP

20.81094.007

R4
1
2
0R0402-PAD

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

AD/BATT CONN

Document Number

Rev

Cathedral Peak 2A
Date: Friday, August 22, 2008
A

Sheet
E

42

of

-1
43

H10
HOLE

H16
HOLE

H20
HOLE

H21
HOLE

H6
HOLE

H3
HOLE

H1
HOLE

13

14

5V_S0

10

14

5V_S0

14

3D3V_S5

12
11

12

11

U12D
TSLVC08APW-1-GP

H14
PAD-1P-3-GP

H15
PAD-1P-3-GP

EC83

DY

EC70

DY

EC73

DY

1
2

EC71

DY

-1
H2
H5
H9
H12
H13
PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP PAD-1P-3-GP
SCD1U25V2ZY-1GP

EC72

DY

SCD1U25V2ZY-1GP

EC106

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

EC107

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

EC103

DY

SCD1U25V2ZY-1GP

DY

SCD1U25V2ZY-1GP

EC94
SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

SCD1U25V2ZY-1GP

EC17

DY

EC57

DY

U22D
TSAHCT125PW-GP

BT+

DCBATOUT

U22C
TSAHCT125PW-GP

13

TOP

BOTTOM

GND1
SPRING-48-GP

34.43G01.002
DY

BOTTOM

TOP

BOTTOM

Check test point


SA

CPU

NB

H7
HOLE

H8
HOLE

H19
HOLE

MDC

MINIC1

H11
HOLE

H17
HOLE

H4
HOLE

SB

-1

3D3V_S0

TP140

TPAD14-GP

TP148

TPAD14-GP

3D3V_S5

TP145

TPAD14-GP

5V_S5

TP127

TPAD14-GP

18,31 PM_PWRBTN#

TP65

TPAD14-GP

6,17 CPU_PWRGD

TP188

TPAD14-GP

TP160

TPAD14-GP

TP77

TPAD14-GP

3D3V_AUX_S5

H18
HOLE

34.4G502.001

34.4G502.001

34.42Y01.011

34.4B602.001

34.4B602.001

34.4B602.001

34.4B602.001

22,31 S5_ENABLE
6,17 CPU_LDT_RST#

Test PointDimm Door

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

EMI/Spring/Boss
Document Number

Cathedral Peak 2A

Date: Friday, August 22, 2008


5

Sheet
1

43

of

Rev

-1
43

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