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  • Alu Program-: NAME-Shivendra Kumar Singh Roll No - 29 Section - E3001

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    Shivendra Kumar Singh
    20 vues3 pages
    This document contains code for an ALU module and test bench in Verilog. The ALU module defines inputs and outputs and uses a case statement to perform different operations on inputs a and b based on the value of the select signal sel. The test bench initializes input values for a, b and sel over multiple timesteps and tests the ALU module.

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    pragram of vlsi to implement alu

    Titre original

    Alu Program

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    This document contains code for an ALU module and test bench in Verilog. The ALU module defines inputs and outputs and uses a case statement to perform different operations on inputs a and b based on the value of the select signal sel. The test bench initializes input values for a, b and sel over multiple timesteps and tests the ALU module.

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    Attribution Non-Commercial (BY-NC)
    Téléchargez comme DOCX, PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    20 vues3 pages

    Alu Program-: NAME-Shivendra Kumar Singh Roll No - 29 Section - E3001

    Transféré par

    Shivendra Kumar Singh
    This document contains code for an ALU module and test bench in Verilog. The ALU module defines inputs and outputs and uses a case statement to perform different operations on inputs a and b based on the value of the select signal sel. The test bench initializes input values for a, b and sel over multiple timesteps and tests the ALU module.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme DOCX, PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 3

    NAME- Shivendra Kumar Singh

    Roll No 29
    Section E3001

    ALU PROGRAMmodule alu123(a, b, sel, z);


    input [7:0]a,b;
    input [3:0]sel;
    output [7:0]z;
    reg [7:0]z;
    always@(sel,a,b)
    begin
    case(sel)
    4'b0000: z=a+b;
    4'b0001: z=a-b;
    4'b0010: z=b-1;
    4'b0011: z=a*b;
    4'b0100: z=a&&b;
    4'b0101: z=a||b;
    4'b0110: z=!a;
    4'b0111: z=~a;
    4'b1000: z=a&b;
    4'b1001: z=a|b;
    4'b1010: z=a^b;
    4'b1011: z=a<<1;
    4'b1100: z=a>>1;
    4'b1101: z=a+1;
    4'b1110: z=a-1;
    endcase
    end
    endmodule

    VERILOG TEST BENCHmodule assqq_v;


    // Inputs
    reg [7:0] a;
    reg [7:0] b;
    reg [3:0] sel;
    // Outputs
    wire [7:0] z;
    // Instantiate the Unit Under Test (UUT)
    add00 uut (
    .a(a),
    .b(b),
    .sel(sel),
    .z(z)
    );
    initial begin
    // Initialize Inputs
    a = 8'b00000001; b = 8'b00001000; sel = 4'b0000;
    #10 a = 8'b01000101; b = 8'b00000110; sel = 4'b0001;
    #10 a = 8'b00000001; b = 8'b11000001; sel = 4'b0010;
    #10 a = 8'b10001001; b = 8'b00000111; sel = 4'b0011;
    #10 a = 8'b01010101; b = 8'b10010001; sel = 4'b0100;
    #10 a = 8'b01001001; b = 8'b10101010; sel = 4'b0101;
    #10 a = 8'b10101001; b = 8'b00000000; sel = 4'b0110;
    #10 a = 8'b10001010; b = 8'b00000000; sel = 4'b0111;
    #10 a = 8'b10101101; b = 8'b10011100; sel = 4'b1000;
    #10 a = 8'b00010001; b = 8'b01010001; sel = 4'b1001;
    #10 a = 8'b00100001; b = 8'b10100110; sel = 4'b1010;
    #10 a = 8'b11101001; b = 8'b00000000; sel = 4'b1011;
    #10 a = 8'b00111101; b = 8'b00000000; sel = 4'b1100;

    #10 a = 8'b01001001; b = 8'b00000000; sel = 4'b1101;


    #10 a = 8'b10100001; b = 8'b00000000; sel = 4'b1110;
    #10 $stop;
    end
    endmodule

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