SVTH: 1.BI MINH SINH 2.O C QUANG 3.

BI T THCH 09DT1 09DT3 09DT1

Gii thiu

Thit k mt b MIPS 32-bit Single cycle CPU n gin Cc lnh m CPU c thc hin l LW, SW, J, BNE,BNEZ, XOR,XORI, ADD, SUB, SLT,v JR Chng ta s dng 2 project trc l Register(lab1) v ALU(lab2) + mt s khi cn thit =>CPU c th thc hin c cng vic ca mnh

- Mi lnh s c bt u khi c xung dng sn ln (hoc xung) ca 1 xung clock v kt thc cng bng 1 sn ln (hoc xung) ca xung clock tip theo

State element 1

Combinational logic

State element 2

clock

one clock cycle

Cc bc thit k b Processor theo kin trc MIPs

1. Phn tch cc kin trc tp lnh 2. Chn cc thnh phn datapath cn thit cho mi lnh 3. Nhm cc thnh phn datapath li 4. Xc nh nhng tn hiu iu khin cn thit 5. Nhm cc cng iu khin logic li 6. Kim tra thit k

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Cu trc n gin ch gm
Khi lnh arithmetic-logic : add, sub, xor, slt Khi lnh b nh: lw, sw Khi lnh r nhnh: bnq, j
6 bits
op

5 bits
rs

5 bits
rt

5 bits
rd

5 bits
shamt

6 bits
funct R-Format

6 bits
op

5 bits
rs

5 bits
rt

16 bits
offset I-Format

6 bits
op

26 bits
address J-Format

Thanh ghi PC dng cung cp a ch lnh ly lnh t memory ng thi tng PC ln 3 khi dng Store/Fetch Instruction , v tng thanh ghi PC ln l :

Instruction address PC Instruction Instruction memory Add Sum

a. Instruction memory

b. Program counter

c. Adder

Nhng lnh trong MIPs c chiu di l 4byte ( 1word), v th thanh ghi PC s c tng ln 4 a vo a ch c lnh tip theo T 3 khi ny ta xy dng c datapath nh sau :

Add 4 Instruction Memory PC Read Address Instruction

Tng quan v cc khi : - Thanh ghi PC : //reg [31:0]PC; wire [31:0] PC, PCin; wire [31:0] PC4; // PC4 = PC+4 wire [31:0] instruction; // PC4 = PC + 4 Add Add1(PC,32'b100,PC4); // InstructionMem InstructionMem InstructionMem1(instruction, PC); // PC Block PC_Reg(PC,PCin,reset,clk);

Addbit:Addbit30
a a y b cou cin cin b

Addbit:Addbit31

Addbit:Addbit0 A[31..0] B[31..0]

0 a a y b cou cin cin b

Addbit:Addbit1
y cou

Y[31..0]

Thi hnh :
Instruction <- MEM[PC] PC <- PC + 4

ADD
4

PC
ADDR

Memory

RD

Instruction

Nhng lnh ton hc ca cc Register vi nhau dng khun dng lnh R-type - op l trng opcode ca lnh, fuc th dnh cho nhng lnh ton hc c bit - rs,rt,v rd l thanh ghi ngun v ch
31 R-type: op 25 rs 20 rt 15 rd 10 shamt 5 funct 0

Chng ta s dng 2 khi l Register v ALU thc hin nhng lnh kiu R
5 Register numbers 5 5 Read register 1 Read register 2 Registers Write register Write data 3 Read data 1 Data Read data 2 Zero ALU ALU result ALU control

Data

RegWrite a. Registers b. ALU

Register-type instructions V d: add $r1, $r2, $r3

000000 00010 op rs 00011 rt 00001 rd 00000 shamt 100000 funct

Instruction op rs
5

rt
5

rd
5

shamt funct
Operation
3

RN1

RN2

Register File
WD

WN RD1

ALU

Zero

RD2 RegWrite

c gi tr cha trong thanh ghi rs ( chn thanh ghi c c bng RN1). c gi tr cha trong thanh ghi rt ( chn thanh ghi c c bng RN2). ALU thc hin cc php Add,Sub,Xor,Slt gia hai thanh ghi RN1 v RN2 Kt qu ng ra ca ALU s c lu vo trong thanh ghi rd( chn thanh ghi WN) khi c tn hiu RegWrite

File thanh ghi :

Regfile Register_File(ReadData1,ReadData2, WriteData,rs,rt,WriteRegister,RegWrite,reset,clk);

B Alu :
ALU ALU1(ReadData1, //BusA of ALU BusB, ALUcontrolOut, ALU2Out, ZeroFlag, OverflowFlag, CarryFlag, NegativeFlag);

Hot ng Load v store :

a ch ca b nh c tnh bng cch cng a ch ca thanh ghi vi phn m rng 16 bit ca trng offset. Store gi tr ( c t file thanh ghi trong qu trnh m ha) l ghi vo Data Memory. Load gi tr, c t Data Memory, ghi vo register file

Ta xy dng c datapath
RegWrite ALU control overflow zero
Address ALU Data Memory Read Data Write Data

MemWrite

Instruction

Read Addr 1 Register Read Data 1 Read Addr 2 File Write Addr Read Write Data Data 2

Sign 16 Extend

MemRead
32

Data memory : dataMem DataMem1(DataMemOut, //data ALU2Out, //address ReadData2, //writedata MemWrite, //writeenable MemRead, //readenable clk);

c gi tr cha trong thanh ghi rs ( chn thanh ghi c c bng RN1).

Offset c a vo khi EXTND chuyn gi tr 16 bit thnh 32 bit. ALU thc hin cng gi tr c t thanh ghi rs v gi tr ng ra ca khi EXTND. Kt qu ng ra ca ALU s l a ch ca thanh ghi trong b nh cha d liu cn load. Ng ra RD ca khi DATA MEMORY s cha d liu cn load v a v li khi REGISTER FILE ghi d liu vo thanh ghi ch rt ( c chn bng WN)

Lw rt, offset(rs)

Thi hnh :

R[rt] <- MEM[R[rs] + s_extend(offset)];

sw rt, offset(rs)
MEM[R[rs] + sign_extend(offset)] <- R[rt]

c gi tr cha trong thanh ghi rs ( chn thanh ghi c c bng RN1).

c gi tr cha trong thanh ghi rt ( chn thanh ghi c c bng RN2).Gi tr ny chnh l d liu cn c lu vo b nh. Offset c a vo khi EXTND chuyn gi tr 16 bit thnh 32 bit.

ALU thc hin cng gi tr c t thanh ghi rs v gi tr ng ra ca khi EXTND.

Kt qu ng ra ca ALU s l a ch ca thanh ghi trong b nh c chn ghi d liu.

Hot ng ca lnh Jump

Thay th 28 bit thp ca PC vi 26 bit thp ca lnh sau khi dch v m rng.

Add 4 Instruction Memory 4 Shift left 2 26

Jump address
28

PC

Read Address

Instruction

Thi hnh :

B Control ly u vo l t cc bit phn opcode ca cc lnh

B Control tng qut dng iu khin : + B ALU Control + Cho php cc tn hiu cn thit nh read,wirte + Chn iu khin cho mi b MUX.

M t b Main Control : + Datapath ca Main Control :

RegDst Jump Branch MemRed MemReg ALUop Memwrite Aluscr Regwrite

Instruction [31:26]

Main Control

u vo ca b Main Control l 6 bit trng opcode ca cu lnh, u ra ca n l 7 tn hiu iu khin 1 bit v tn hiu iu khin b Aluop 2 bit. Cc tn hiu iu khin 1 bit : (Control Signal )

Tn Signal RegDst Regwrite AluScr

nh hng khi mc 0 Ch ra thanh ghi ch vi vic Write Register t trng rt [20:16] Khng nh hng a ton hng th 2 u vo ca b ALU l t u ra ca file thanh ghi th 2 ( Read data 2 ) Khng nh hng

nh hng khi mc 1 Ch ra thanh ghi ch vi vic Write Register t trng rd [15:11] Cho php ghi d liu t u vo Writedata vo thanh ghi u vo WriteRegister Ton hng th 2 ca b ALU c ly t b Sign-Extend, ( 16 bit thp c ly t Instruction [0:15] ) Ni dung ca b nh d liu c ch nh bi u vo address s c a ra u ra Read address Ni dung ca b nh d liu c ch nh bi u vo address c thay th bi gi tr ca u vo Write data u vo Write data ca b Register s c ly t Data memory

MemRead

MemWrite

Khng nh hng

MemtoReg

Kt qu u ra ca b ALU s c a vo u vo Writedata ca b Register

Tn hiu iu khin Aluop : ( 2 bit ) Dng iu khin b ALU Control iu khin : 00 : dng ton hc add khi s dng lnh LW/SW 01 : dng ton hc sub khi s dng lnh Branch ( bne) 10 : dng cho cc lnh kiu R

Xc nh cc tn hiu iu khin cho cc lnh da trn trng opcode :

Memto- Reg Mem Mem Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0 Jump R-format 1 0 0 1 0 0 0 1 0 0 lw 0 1 1 1 1 0 0 0 0 0 sw X 1 X 0 0 1 0 0 0 0 bne X 0 X 0 0 0 1 0 1 0 j X X X X X X X X X 1

Thit k b Main control :

Signal j name Op5 Op4 Op3 Op2 Op1 Op0 RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch Jump ALUOp1 ALUOP2 Rlw 1 0 1 0 1 1 x 1 x 0 0 1 0 0 0 0 sw 0 0 0 1 0 1 x 0 x 0 0 0 1 0 0 1 bne 0 0 0 0 1 0 x x x x x x x 1 x x

format 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 1 0 0 0

Output

Inputs

Main Control :
Control Control1(instruction[31:26],//Opcode RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite );

T ta thit k b Main control nh sau :

Hot ng ca lnh Branch ( bne ) So snh phn t c t file thanh ghi xem th c khng bng nhau hay ko ( a ra Zero ca b ALU) Tnh ton a ch ca lnh sau khi branch:
destination address = (PC + 4) + (4 * offset)

Ngoi vic tnh ton a ch nhy,cn quan tm n iu kin khng bng nhau ca hai thanh ghi.Nu iu kin l ng th lnh tip theo l lnh ti a ch r nhnh,nu khng th thc hin lnh ngay sau n

=> Do Datapath thc hin hai cng vic: so snh 2 thanh ghi v tnh ton a ch ch ca lnh
-

tnh ton lnh nhy,datapath phi c mt n v m rng du v mt b cng. so snh chng ta s dng tp thanh ghi ly hai gi tr ca hai ton t thanh ghi. Thm vo vic so snh c thc hin bng ALU.Nu hai tn hiu khng bng nhau th tn hiu ZERO=0

Ta xy dng c datapath

Add 4 Shift left 2 Add

Branch target address

ALU control
PC Read Addr 1 Register Read Data 1 Read Addr 2 File Write Addr Read Write Data Data 2

zero (to branch control logic)

ALU

Instruction

Sign 16 Extend

32

Thi hnh :

Bne rs, rt, offset

if (R[rs] != R[rt]) then PC <- PC+4 + s_extend(offset<<2)

*i vi lnh xori:

-i vi lnh ny ta cng khng cn thay i datapath,n c khun dng ca lnh I-type. *Bng tn hiu iu khin:

*Bng s tht ca b main control

*i vi lnh JR:

-Nhy n v tr m v tr c lu trong thanh ghi $Rs (Rs cha v tr cn nhy n).Jr thuc khun dng R-type. -Lnh JR s lm cho datapath c s thay i: Thm 1 b mux2x32to32 gi l MuxJreg,tn hiu iu khin gi l jreg c ly t u ra ca ALUcontrol. u vo th nht l u ra ca MuxJump,u vo cn li l ReadData1 ($Rs) Bnh thng jreg =0,ch khi c lnh JR th jreg=1 th #Pcin=[Rs].

N gm 2 u vo l ALUop ( 2 bit ) c ly t b Main Control v trng Function trong Instruction ( 6 bit )

u ra ca b Alu Control c a vo b ALU v mt tn hiu iu khin jreg a vo b MuxJr

T ALU control ca b ALU ca project 2 ALU CONTROL LINES 00 01 10 11 FUNCTION Add Xor Sub SLT

Bng s tht ca b ALU Control

T bng trn ta lp c mt bng chn tr nh sau

ALUOp1 Fct0 Fct1 Fct2 Fct3 Fct4 Fct5 ALU Control 0 ALU Control 1

ALUOp0

0 1

0 0

X 1

X 0

X 0

X 0

X 0

X 0

0 0

0 0

1
0 1 1

0
1 0 0

1
X 1 1

0
X 0 0

0
X 0 1

1
X 0 0

1
X 1 1

0
X 0 0

0
1 1 1

1
0 0 1

module ALUcontrol_Block(ALUOp,Function,ALUcontrol,jreg); input [1:0] ALUOp; input [5:0] Function; output [1:0] ALUcontrol; // 2 dau cho vao ALU , output jreg; //1 la jreg

S khi b ALU Control

Dch tri 2 bit - Thm 2 bit 0 vo cui - Hm : shift_left_2 shift_left_2_jump({6'b0,instruction[25:0]}, //In32 ~ 26-bit offset of jump instruction JumpAddress); //Out32 ~ 28-bit after shifting left 2 bits

module

shift_left_2(In32, Out32); input [31:0] In32; output [31:0] Out32; assign Out32 = {In32[29:0],2'b00}; endmodule

Nu l ton hng dng th ta thm 16 bit 0 Nu l ton hng m th ta thm 16 bit 1 Hm : // sign_extend wire [31:0] Sign_extend_Out; sign_extend sign_extend_1(instruction[15:0],Sign_extend_Out); module sign_extend(In16,Out32); input [15:0] In16; output [31:0] Out32; assign Out32 = {{16{In16[15]}},In16}; endmodule

thc hin c lnh loi R v cc lnh loi I ta thm 4 b mux: chn gi tr vo ALU s l gi tr t thanh ghi(resad data 2) hay gi tr hng (offset/immediate) .
chn gi tr c a v khi REGISTER FILE s l gi tr ca ng ra ALU hay gi tr c t b nh. chn a ch thanh ghi ch s l bit th 20-16 (lnh loai I) hay bit th 15-11 ( lnh loi R).

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Mux5b :

// Select WriteRegister mux2x5to5 mux2x5to5_1(instruction[20:16], instruction[15:11], RegDst, data_in);

module mux2x5to5(AddressIn0, AddressIn1, Sel, AddressOut);
input [4:0] AddressIn0, AddressIn1; input Sel; output [4:0] AddressOut; mux2to1 SelAddress0(AddressIn0[0], AddressIn1[0], Sel, AddressOut[0]); mux2to1 SelAddress1(AddressIn0[1], AddressIn1[1], Sel, AddressOut[1]); mux2to1 SelAddress2(AddressIn0[2], AddressIn1[2], Sel, AddressOut[2]); mux2to1 SelAddress3(AddressIn0[3], AddressIn1[3], Sel, AddressOut[3]); mux2to1 SelAddress4(AddressIn0[4], AddressIn1[4], Sel, AddressOut[4]); endmodule

Mux32b : // Select Data to WriteData for regfile

mux2x32to32 mux2x32to32_2(ALU2Out, //DataIn0 DataMemOut, //DataIn1 MemtoReg, //Sel WriteData); //DataOut mux2x32to32 muxBranch(PC4, //DataIn0 ALUBranchOut, //DataIn1 BranchSel, //Sel MuxBranchOut); //DataOut mux2x32to32 muxJump(MuxBranchOut, //DataIn0 {PC4[31:28],JumpAddress[27:0]},//DataIn1 Jump, //Sel PCin); //DataOut

// ALU control wire jreg; // mux dung cho lenh JR mux2x32to32 muxJr(MuxJumpOut, ReadData1, jreg, PCin);

MIPs Single-Cycle CPU

/*0 4 8 12 16 20 24 28

lw $1,0($0) //[$1]=1 lw $2,4($0) //[$2]=2 lw $3,8($0) //[$3]=3 lw $4,12($0) //[$4]=48 add $5,$0,$1 //[$5]=0+1=1 sub $6,$4,$3 //[$6]=48-3=45 slt $8,$1,$2 //[$8]=1 xori $10,$1,2 //[$10]=3

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32 sw $4,16($0) 36 jr $4 // nhay den vi tri dc luu tru trong $4 ,[$4]=48==>> nhay den lenh bne $1,$2,label_1 . 40 add $11,$0,$1 //[$11]=0+1=1 44 bne $1,$2,label_1 48 add $10,$3,$4 //[$10]=3+48=51 52 label_1: lw $9,16($0) //[$9]=48 56 add $10,$2,$4 //[$10]=2+48=50
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