Slide Flipflop

R.
Lauwereins Imec 2001
Course contents
Digital design Combinatorial circuits: without status Sequential circuits: with status FSMD design: hardwired processors Language based HW design: VHDL
Digital design Combinatorial circuits Sequential circuits FSMD design
VHDL
3/1
R.Lauwereins Imec 2001
Sequential Circuits
The flip-flop as building block Design of synchronous sequential circuits Design of asynchronous sequential circuits Basic RTL building blocks
VHDL
3/2
Sequential Circuits
VHDL
3/3
The flip-flop as building block

Definitions:
Combinatorial circuit: the output is function of the current value of the inputs Sequential circuit: the output is function of the current value of the inputs and of the current state (i.e. also function of the sequence of past inputs)
VHDL
3/4

Definitions
Asynchronous sequential circuits: outputs and state change as soon as an input changes Synchronous sequential circuits: outputs and state change only when a special input, the clock, gets a certain value Clock period: duration between two consecutive 10 transitions of the clock Clock frequency: 1 / (clock period) Duty cycle: (duration that the clock equals 1) / (clock period) Rising edge: 01 transition of the clock Falling edge: 10 transition of the clock
VHDL
3/5
Sequential Circuits
SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop types
VHDL
Design of synchronous sequential circuits Design of asynchronous sequential circuits Basic RTL building blocks
3/6
Sequential Circuits
VHDL
3/7
SR Latch
Set
S R 0 1 0 1 Q(next) Q 0 1 NA
Reset
0 0 1 1
VHDL
S R Q Q Undefined
3/8
SR Latch
Note that a Boolean signal now already consists of 5 values:
0: the logical signal 0 1: the logical signal 1 x: dont care Z: high impedant U: undefined
VHDL
The oscillation is called critical race The oscillation only happens when the delay of both gates is exactly equal When the delays are not equal, the fastest gates determines the end result: implementation and run-time dependent undefined
3/9
SR Latch
Set
S R 1 0 1 0 Q(next) Q 0 1 NA
Reset
1 1 0 0
Set and Reset active low
VHDL
S R Q Q
3/10
Sequential Circuits
VHDL
3/11
Gated SR Latch
Set Q Clock Q Reset
C 0 0 0 0 1 1 1 1 S 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 Q(next) Q Q Q Q Q 0 1 NA
C=1: follow inputs C=0: latch outputs
VHDL
3/12
Sequential Circuits
VHDL
3/13
Gated D Latch
D Q Clock Q C=1: follow input C=0: latch output
C 0 0 1 1 D 0 1 0 1 Q(next) Q Q 0 1
DQ delay when C high:

CQ delay when D high: when D low:
VHDL
L-to-H H-to-L L-to-H H-to-L
delay: delay: delay: delay:
2.4+1.4+1.4=5.2 1+2.4+1.4=4.8 2.4+1.4+1.4=5.2 2.4+1.4=3.8
3/14
Gated D Latch
D
S
Q
C=1: follow input C=0: latch output

C 0 0 1 1 D 0 1 0 1 Q(next) Q Q 0 1
Clock R Q
VHDL
D must not change immediately before H-to-L of the clock (during the setup time); reason: clock changes between the switching of D and of D hence Set and Reset switch from H to L at the same time undefined (setup time = H-to-L of invertor) D C
S
D R
3/15
Gated D Latch
D
S
Q

C 0 0 1 1 D 0 1 0 1 Q(next) Q Q 0 1
Clock R Q
VHDL
When D switches at least setup time before the clock transition, S and R will not switch from H to L at the same time OK (S is longer high than R, hence Q will come high following the D input) D C
S
D R
3/16
Gated D Latch
D
S
Q

C 0 0 1 1 D 0 1 0 1 Q(next) Q Q 0 1
Clock R Q
Analogously, D may not switch immediately after H-to-L of the clock (during the hold time) Symbol D Q 5.2/3.8 C Q Given values: 5.2=C to QLH 3.8=C to QHL
VHDL
3/17
Sequential Circuits
SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity
Level-sensitive latch Master-slave flip-flop Edge-triggered flip-flop

Flip-flop types
VHDL
3/18
Sequential Circuits

Flip-flop types
VHDL
3/19
Level sensitive latch

All previous gated latches are level sensitive
Transparent when clock is high Remembering the last value when clock is low
Level sensitive latches give problems for shift registers for example
The input signal may ripple through multiple stages during one clock-high phase making it very hard to meet setup/hold time requirements See next slide
VHDL
3/20
Level sensitive latch

X D Q1 4/3 C D Q2 4/3 C D Q3 4/3 C
Clk
Clk X Q1 Q2 Q3 Two solutions: Master-slave Edge-triggered
VHDL
3/21
Sequential Circuits

Flip-flop types
VHDL
3/22
Master-slave flip-flop
X Master D Qm1 4/3 C Slave D Qs1 4/3 C Q1 Master D Qm2 4/3 C Slave D Qs2 4/3 C Y
Clk
Clk X Qm1 Q1 Qm2
VHDL
Y
The master clocks at the falling clock edge The slave clocks at the rising edge
3/23
Sequential Circuits

Flip-flop types
VHDL
3/24
Edge-triggered flip-flop
A Set Latch Set Q Clk Reset B D Q Output Latch
Reset Latch
VHDL
Clk
D B A R S Q
3/25
Sequential Circuits
VHDL
3/26
SR flip-flop JK flip-flop D flip-flop T flip-flop Asynchronous set and reset Design of synchronous sequential circuits Design of asynchronous sequential circuits
Sequential Circuits
VHDL
3/27
SR flip-flop JK flip-flop D flip-flop T flip-flop Asynchronous set and reset Design of synchronous sequential circuits Design of asynchronous sequential circuits
SR flip-flop
Symbol
S Q Characteristic table (for design of SR flip-flop)
S 0 0 1 1 R 0 1 0 1 Q(next) Q 0 1 NA
Clk R Q Triangle next to clock means positive edge-triggered
VHDL
Negative edge-triggered
Positive level triggered Negative level triggered
Excitation table (for design with SR flip-flop)

Q 0 0 1 1 Q(next) 0 1 0 1 S 0 1 0 x R x 0 1 0
3/28
Sequential Circuits
VHDL
SR flip-flop JK flip-flop D flip-flop T flip-flop Asynchronous set and reset Design of synchronous sequential circuits Design of asynchronous sequential
3/29
JK flip-flop
Symbol
J Q Characteristic table (for design of JK flip-flop)
J 0 0 1 1 K 0 1 0 1 Q(next) Q 0 1 Q
Clk K Q
VHDL
Excitation table (for design with JK flip-flop) Circuits that use JK flip-flops are cheaper than those using SR flip-flops: more dont cares
Q 0 0 1 1 Q(next) 0 1 0 1 J 0 1 x x K x x 1 0
3/30
Sequential Circuits
VHDL
3/31
D flip-flop
Symbol
D Q Characteristic table (for design of D flip-flop)
D 0 1 Q(next) 0 1
Clk Q
VHDL
Excitation table (for design with D flip-flop)

Q Q(next) 0 1 0 1 D 0 1 0 1
Designing with D flip-flop is easy
0 0 1 1
3/32
Sequential Circuits
VHDL
3/33
T flip-flop
Symbol
T Q Characteristic table (for design of T flip-flop)
T 0 1 Q(next) Q Q
Clk Q
VHDL
Excitation table (for design with T flip-flop) T D Q

Q 0 0 1 1 Q(next) 0 1 0 1 T 0 1 1 0
Clk Q
3/34
Sequential Circuits
VHDL
3/35
Asynchronous set and reset

Preset A Set Q
Clk
Reset D Clear Asynchronous set and reset are useful to put the flip-flop initially in a known state (see lab sessions) D PRS Q B Q
VHDL
Clk
CLR
3/36

Why are the asynchronous preset and clear connected to both layers of SR-flipflops?
The first layer passes input modifications to the second layer only at the rising clock edge The second layer reacts immediately, without waiting for the rising clock edge => needed for asynchronous reaction If they were only connected to the second layer, the first layer would not know in what state the second layer was put and could give a conflicting command to the second layer at the next rising clock edge, e.g. reset since D=0 and at the same time an asynchronous preset
VHDL
3/37

Why are the asynchronous preset and clear active low?
Because wired-or of open drain circuits is used to avoid short circuits when there are multiple sources driving them:
R No preset No preset Open drain
VHDL
preset
3/38
Implements an AND function (hence wired-or ...) with unlimited number of inputs: preset The bus is only 1 when all inputs to the bus are equal to 1
Sequential Circuits
VHDL
3/39
Sequential Circuits
The flip-flop as building block Design of synchronous sequential circuits
Finite State Machine (FSM) State-based or Moore-type FSM Input-based or Mealy-type FSM Step 1: State diagram Step 2: State minimization Step 3: State encoding Step 4: Choice of the flip-flop type Step 5: Realization of the combinatorial logic Step 6: Timing analysis
VHDL
3/40
Design of asynchronous sequential circuits Basic RTL building blocks
Sequential Circuits
VHDL
3/41
Finite State Machine

Design a modulo 4 Counter, that counts when the input CE (Count Enable) equals 1 and stops counting when the input CE equals 0. Step 1: translate to a Finite State Machine (FSM):
CE=0 CE=0 Count=0 CE=1 Count=1 CE=1
VHDL
CE=1
CE=0
Count=3 CE=1
Count=2
CE=0
3/42
Transition to the next state happens at each rising clock edge (a synchronous FSM is clocked!). At each rising clock edge, exactly one transition condition should be true: for each input combination, a transition should be specified in each of the states. CE=0 CE=0 Count=0 CE=1 Count=1 CE=1 CE=0
CE=1 CE=0 Count=3 CE=1
VHDL
Count=2
3/43
1. We are in state Count=0 2. CE input equals 0: we are waiting at the tip of the edge 3. CE=1: wait at tip of other edge, but do not count yet! 4. Rising clock edge: go to Count=1, still with CE=1 5. CE input becomes 0: wait at tip of other edge 6. Rising clock edge: go to Count=1, with CE=0

Step 2: Minimise the number of states. It is already the minimum number. Step 3: Encode the states:
CE=0 Q1Q0=00 CE=1 CE=0 Q1Q0=11 CE=1 CE=1 Q1Q0=01 CE=1
CE=0
VHDL
Q1Q0=10
CE=0
3/44

Step 4: Select the flip-flop type. We select the D type for its simplicity. Step 5: Realise the circuit. See next slides:
VHDL
3/45

Translate the FSM in a next-state table:
CE=0 Q1Q0=00 CE=1 CE=0 Q1Q0=11
Present state Q1Q0 00 01 10 11
CE=0 CE=1 Q1Q0=01
CE=1
Q1Q0=10 CE=0
VHDL
CE=1
3/46
Next state Q1nQ0n CE=0 CE=1 00 01 01 10 10 11 11 00

Determine the excitation functions:
Present state Q1Q0 00 01 10 11 Next state Q1nQ0n CE=0 CE=1 00 01 01 10 10 11 11 00
VHDL
Excitation table for D flip-flop

Q 0 0 1 1 Q(next) 0 1 0 1 D 0 1 0 1
Q0 Q1n=D1 Q1 0 0 1 CE 0 1 0 1 1 CE Q0n=D0
Q0 Q1 0 1 1 0 1 0 0 1
3/47
D to be applied is identical to Qn

Implement:
Q0 Q1n=D1 0 0 CE CE Q1 Q0 Q1n 0 1 Q1 1 1 0 1 CE Q0n=D0 Q0 Q1 0 1 1 0 1 0 0 1
VHDL
D1
Q1
Q Q0 Q
Q0n
D0
3/48

Step 6: Timing analysis
CE Q1 Q0 Q1n Q1
D1
Q
Q0 Q
Q0n
D0
VHDL
Clk
CE
Q1
3/49
Q0
Sequential Circuits
VHDL
3/50
State-based or Moore-type FSM

Design a modulo 4 Counter, that counts when the CE input equals 1 and stops counting when CE equals 0. The output Y equals 1 when the count value equals 3. Step 1: translate to FSM:
CE=0 CE=0 Count=0 Y=0 CE=1 CE=0 Count=3 Y=1 CE=1 Count=1 Y=0 CE=1 Count=2 Y=0 CE=0
VHDL
CE=1
3/51

Be extremely careful about timing issues!! Assume that the Y output is used as a load-enable for a register and as the add/subtract line for an adder/subtractor: when arriving in state 3, Y becomes 1, immediately causing the adder/subtractor to switch to subtract mode, but NOT causing the register to load a new value!!! The loading will only occur at the next state transition (i.e. the next clock edge)
VHDL
LE
CE
Register
Clk
Clocked
Counter A/S Add/Subtract Combinatorial
3/52

State-based:
the output is indicated for each state the output is only function of the current state, not of the inputs applied Hence, the output value is indicated in the circle representing the state
VHDL
3/53

Step 2: Minimise the number of states. This is already the minimum number. Step 3: Encode the states:
CE=0 Q1Q0=00 Y=0 CE=1 CE=0 Q1Q0=11 Y=1 CE=1 Q1Q0=01 Y=0 CE=1 Q1Q0=10 Y=0
CE=0
VHDL
CE=0
CE=1
3/54

VHDL
3/55

Translate the FSM in a next-state table:
CE=0
Q1Q0=00 Y=0
CE=0 CE=1
Q1Q0=01 Y=0
CE=1 CE=0
Q1Q0=11 Y=1
CE=1
Q1Q0=10 Y=0
CE=0
VHDL
CE=1
3/56
Next state Q1nQ0n CE=0 CE=1 00 01 01 10 10 11 11 00
Outputs Y 0 0 0 1
Y is only dependent on the current state, not on the inputs

Present state Q1Q0 00 01 10 11 Next state Q1nQ0n CE=0 CE=1 00 01 01 10 10 11 11 00 Outputs Y 0 0 0 1
VHDL

Q 0 0 1 1 Q(next) 0 1 0 1 D 0 1 0 1
Q0 Q1n=D1 Q1 0 0 1 CE 0 1 0 Y Q1 1 1 Q0 0 0 0 1 CE Q0n=D0
Q0 Q1 0 1 1 0 1 0 0 1
3/57

Implement:
Q0 Q1n=D1 Q1 0 0 1 1 CE 0 1 0 1 CE Q0n=D0 0 1 1 0 Q0 Q1 1 0 0 1 Y Q1 Q0 0 0 0 1
CE Q1 Q0 Q1n
VHDL
D1
Q1
Q Q0 Q
Q0n
D0
3/58

CE Q1 Q0 Q1n Q1 Y
D1
Q
Q0 Q
Q0n
D0
VHDL
Clk CE Q1 Q0
3/59
Danger for Glitch!

Is a glitch harmful?
When the output with the glitch is connected to the clock of some clocked circuit:
VHDL
This clocked circuit will unintentionally clock: harmful Hard to debug: glitch may disappear when probe is connected due to increased capacitance and hence also increased delay
When the output with the glitch is connected to a combinatorial circuit that eventually is the input of a register:
3/60
Not harmful, since the register looks at its input only at the clock edge Dissipates unnecessary power
Sequential Circuits
VHDL
3/61
Input-based or Mealy-type FSM

Design a modulo 4 Counter, that counts when the CE input equals 1 and stops counting when CE equals 0. The Y output value equals 1 when the count=3 while the input CE equals 1. Step 1: translate to FSM:
CE=0/Y=0 CE=0/Y=0 Count=0 CE=1/Y=0 Count=1 CE=1/Y=0 Count=2 CE=0/Y=0 CE=1/Y=0
VHDL
CE=1/Y=1 CE=0/Y=0 Count=3
3/62

Transition to the next state happens at each rising clock edge CE=0/Y=0 Count=0 CE=1/Y=0 Count=1 CE=1/Y=0 Count=2 CE=0/Y=0 CE=1/Y=0 1. We are in state Count=2 2. CE input equals 1: wait at tip of edge with Y=0 3. Rising clock edge: go to Count=3, still with CE=1: Y=1 4. C input becomes 0: wait at tip of other edge with Y=0; combinatorial circuit driven by Y reacts, clocked dont CE=0/Y=0
CE=1/Y=1 CE=0/Y=0 Count=3
VHDL
3/63
5. Rising clock edge: Y=0 is clocked into output register

Be extremely careful about timing issues!! Assume that the Y output is used as a load-enable for a register and as the add/subtract line for an adder/subtractor: when arriving in state 3 with CE=1, Y becomes 1 adder/subtractor switches to subtract, but register doesnt load new value!!! When CE=0, Y becomes 0 adder/subtractor switches to add, and LE=0. When the next clock edge comes while CE=0, register will not load.
LE Register Clk Clocked
VHDL
CE
Counter A/S Add/Subtract Combinatorial
3/64

Input-based:
the output is specified for each state and each combination of inputs in that state the output is function of the current state, and of the applied inputs Hence the output is specified next to each transition
VHDL
3/65

Step 2: Minimise the number of states. This is already the minimum number. Step 3: Encode the states:
CE=0/Y=0 Q1Q0=00 CE=1/Y=1 CE=0/Y=0 Q1Q0=11 CE=1/Y=0 CE=1/Y=0 Q1Q0=01
CE=0/Y=0
VHDL
CE=1/Y=0 Q1Q0=10 CE=0/Y=0
3/66

VHDL
3/67

Translate FSM to next-state table:
CE=0/Y=0
Q1Q0=00
CE=0/Y=0 CE=1/Y=0
Q1Q0=01
CE=1/Y=1 CE=0/Y=0 Q1Q0=11

CE=1/Y=0
Q1Q0=10 CE=0/Y=0
VHDL
CE=1/Y=0
3/68
Next state/Outputs Q1nQ0n/Y CE=0 CE=1 00/0 01/0 01/0 10/0 10/0 11/0 11/0 00/1
Y does not only depend on the current state, but also on the inputs

Q 0 0 1 1 Q(next) 0 1 0 1 D 0 1 0 1
Next state/Outputs Q1nQ0n/Y CE=0 CE=1 00/0 01/0 01/0 10/0 10/0 11/0 11/0 00/1 Q0
Q0
VHDL
Q1n=D1
Q1
0 0 1 1
Q0n=D0
Q1
0 1 1 0
CE Y
0 1 0 1 Q0
Q1 0 0 0 0 0 0 0 1
CE
1 0 0 1
3/69
CE

Implement:
Q0 Q1n=D1 Q1 0 0 1 1 CE 0 1 0 1 CE Q0n=D0 0 1 1 0 Q0 Q1 1 0 0 1 CE Y Q0 Q1 0 0 0 0 0 0 1 0
CE Q1 Q0 Q1n
VHDL
D1
Q1
Q Q0 Q
Q0n
D0
3/70

CE Q1 Q0 Q1n Q1 Y
D1
Q
Q0 Q
Q0n
D0
VHDL
Clk CE Q1 Q0
3/71
Danger for Glitch!
State-based model
Inputs I Clock D Clk S*=F(S,I) Outputs O Q Next State S* Current State S
D Clk
O=H(S)
VHDL
Next State Combinatorial Logic
Output Combinatorial Logic

Q
Clk
3/72
Input-based model
Clock Inputs I Next State S* Current State S
D Clk S*=F(S,I)
Q Outputs O
D Clk
O=H(S,I)
VHDL
Next State Combinatorial Logic
Output Combinatorial Logic

Q
Clk
3/73
Sequential Circuits
VHDL
3/74
Step 1: construction of the FSM

The first step in the design of synchronous sequential circuits is the construction of the FSM starting from the description in natural language (ambiguous and incomplete) Example: Modulo-3 up/down counter Count enable (C):
C=1: count C=0: do not count D=1: count down D=0: count up
Direction (D):
VHDL
Output (Y): Y=1 when (count equals 2 and we count up) or when (count equals 0 and we count down) What is the meaning of We count up?
3/75
Do we have to count (C=1) and up (D=0)

First step: is this a State-based or an Input-based design?
It is Input-based, since the output depends on the state and the input
Second step: construct the FSM starting from the first state, for each combination of inputs from each state
See next slide Note: when an output needs to remain high during several consecutive states, it should be assigned a high value in each of these states!! Each output should be assigned a value in each state!
VHDL
3/76

CD=10 Y=1 CD=0X Y=0 CD=0X Y=0 CD=0X Y=0
u0
CD=10 Y=1 CD=10 Y=0
CD=10 Y=0
u1
CD=10 Y=0 CD=10 Y=0
u2
CD=11 Y=0 CD=11 Y=1
VHDL
d0
CD=0X Y=0
CD=11 Y=0
CD=11 Y=0
CD=0X Y=0
d1
CD=11 Y=0
CD=0X Y=0
d2
CD=11 Y=1
3/77
Sequential Circuits
VHDL
3/78
Step 2: minimise the number of states

Goal: less states means less flip-flops Principal: equivalent behavior of two FSMs Two FSMs are equivalent when they produce the same output sequence for the same input sequence
VHDL
3/79

Two states in an FSM may be replaced by 1 state when both states produce the same outputs for the same inputs and when both jump to equivalent next states for the same inputs Formally: states sj and sk are equivalent (sjsk) if and only if
VHDL
iI: h(sj,i)=h(sk,i): both states produce the same output for each combination of inputs and iI: f(sj,i)f(sk,i): the next states are equivalent for each input combination
3/80

In practice: build the next state table out of the state diagram first
PRESENT STATE u0 u1 u2 d0 d1 d2 NEXT STATE / OUTPUT CD=0X CD=10 CD=11 u0/0 u1/0 d2/1 u1/0 u2/0 d0/0 u2/0 u0/1 d1/0 d0/0 u1/0 d2/1 d1/0 u2/0 d0/0 d2/0 u0/1 d1/0
VHDL
3/81

Construct the implication table: 1 square per combination of 2 states
VHDL
u1
u2 d0 d1 d2
3/82
u0
u1
u2
d0
d1

Delete all combinations that have different outputs for the same inputs
VHDL
u1
u2 d0 d1 d2
3/83
u0
u1
u2
d0
d1

Indicate for the remaining which next states have to be equivalent to make the current states equivalent
VHDL
u1
u2 d0 d1 d2
OK
OK OK u0 u1 u2 d0 d1
Minimum number of states: 3 ie. {u0,d0}=s0 {u1,d1}=s1 {u2,d2}=s2
3/84

Construct the new next state table
Minimum number of states: 3 ie. {u0,d0}=s0 {u1,d1}=s1 {u2,d2}=s2
VHDL
PRESENT STATE s0 s1 s2
3/85
NEXT STATE / OUTPUT CD=0X CD=10 CD=11 s0/0 s1/0 s2/1 s1/0 s2/0 s0/0 s2/0 s0/1 s1/0

FYI: draw new state diagram
PRESENT STATE s0 s1 s2 NEXT STATE / OUTPUT CD=0X CD=10 CD=11 s0/0 s1/0 s2/1 s1/0 s2/0 s0/0 s2/0 s0/1 s1/0
CD=10 Y=1 CD=0X Y=0 CD=0X Y=0 CD=0X Y=0
VHDL
CD=10 Y=0 CD=11 Y=0
CD=10 Y=0 CD=11 Y=0
s0
s1
s2
3/86
CD=11 Y=1
This could have been constructed from the begin -ning, but better 1 state too much than too little

This example did not show how you should manipulate the implication table Hence an imaginary example showing all problems:
PRESENT STATE s0 s1 s2 s3 s4 s5 NEXT STATE / OUTPUT AB=00 AB=01 AB=10 s4/1 s2/0 s1/1 s2/0 s5/1 s4/1 s1/1 s0/0 s3/1 s2/0 s5/1 s4/1 s0/0 s5/1 s1/1 s2/0 s4/1 s2/1
VHDL
3/87

Construct the implication table: 1 square per combination of 2 states
VHDL
s1
s2 s3 s4 s5
3/88
s0
s1
s2
s3
s4

Delete all combinations with different outputs for same inputs
VHDL
s1
s2 s3 s4 s5
3/89
s0
s1
s2
s3
s4

Indicate for the remaining which next states have to be equivalent to make the current states equivalent
PRESENT STATE s0 s1 s2 s3 s4 s5
OK 0-2 4-5 2-4 0-2 1-4 4-5 2-4
VHDL
s1
s2 s3 s4 s5
1-4 1-3
NEXT STATE / OUTPUT AB=00 AB=01 AB=10 s4/1 s2/0 s1/1 s2/0 s5/1 s4/1 s1/1 s0/0 s3/1 s2/0 s5/1 s4/1 s0/0 s5/1 s1/1 s2/0 s4/1 s2/1
0-2, 4-5 1-2
3/90
s0
s1
s2
s3
s4

Delete those states that are equivalent when non-equivalent next states would have been equivalent
OK 0-2: 0-2? 4-5 2-4 0-2: 0-2? 1-4: 1-4? 4-5 2-4
VHDL
s1
s2 s3 s4 s5
1-4: 1-4? 1-3:OK 1-3
0-2, 4-5 1-2
3/91
s0
s1
s2
s3
s4

Delete again as long as states are deleted during an iteration
OK 0-2: ? 4-5 2-4 0-2: ? 1-4: ? 4-5 2-4
VHDL
s1
s2 s3 s4 s5
1-4: ? 1-3:OK
0-2, 4-5 1-2
Minimum number of states: 3 ie. {s0,s2}=u0 {s1,s3,s4}=u1 {s5}=u2
3/92
s0
s1
s2
s3
s4

Construct the new next state table
Minimum number of states: 3 ie. {s0,s2}=u0 {s1,s3,s4}=u1 {s5}=u2
VHDL
PRESENT STATE u0 u1 u2
3/93
NEXT STATE / OUTPUT AB=00 AB=01 AB=10 u1/1 u0/0 u1/1 u0/0 u2/1 u1/1 u0/0 u1/1 u0/1
Sequential Circuits
VHDL
3/94
Step 3: State encoding

n states require at least log2n flip-flops. There are n! possible encodings (n choices for the first state, n-1 for the second, etc.)
No. s0 1 2 3 4 5 6 7 8 9 10 11 12 00 00 00 00 00 00 01 01 01 01 01 01 s1 01 01 10 10 11 11 00 00 10 10 11 11 s2 10 11 01 11 01 10 10 11 00 11 00 10 s3 11 10 11 01 10 01 11 10 11 00 10 00 No. 13 14 15 16 17 18 19 20 21 22 23 24 s0 10 10 10 10 10 10 11 11 11 11 11 11 s1 00 00 01 01 11 11 00 00 01 01 10 10 s2 01 11 00 11 00 01 01 10 00 10 00 01 s3 11 01 11 00 01 00 10 01 10 00 01 00
VHDL
3/95
Step 3: State encoding

Does the chosen encoding matters?
Yes. Each choice leads to a different combinatorial circuit with different cost and delay.
Often chosen encodings:

Straightforward Minimum-bit-change One-hot
VHDL
3/96
Step 3: State encoding: Straightforward

Straightforward encoding uses the binary representation of the state number as code (s0000, s5101, ) Straightforward encoding is mostly used when the state number has a physical meaning
E.g. a counter whose count value is sent to a display
VHDL
Straightforward encoding is dangerous for glitches and leads to non-minimal area and power consumption: multiple bits have to change at each state transition
(multiple bit-changes seldomly happen concurrently; each bit-change requires some logic to implement it; each bit-change consumes power)
3/97
Step 3: State encoding: Straightforward

VHDL
PRESENT STATE 00 01 10
NEXT STATE / OUTPUT CD=0X CD=10 CD=11 00/0 01/0 10/1 01/0 10/0 00/0 10/0 00/1 01/0
3/98
Step 3: State encoding: Minimum-bit-change

For minimum-bit-change encoding we assign the codes such that the total number of bit-changes for all state transitions is minimal Minimum-bit-change encoding is mostly used when area and power need to be minimized (CMOS)
00 2 11 1 01 2 1 10 00 1 01 1
VHDL
Gray code counter
10
11
3/99
Straightforward
Minimum-bit-change
Step 3: State encoding: Minimum-bit-change

VHDL
2
PRESENT STATE 00 10 11
All transitions are equally likely Preferrably only 1 bit difference between each pair of transitions This can only be realised between two of the three pairs
3/100
NEXT STATE / OUTPUT CD=0X CD=10 CD=11 00/0 10/0 11/1 10/0 11/0 00/0 11/0 00/1 10/0
Possible encoding: s0=00 s1=10 s2=11
Step 3: State encoding: One-hot

Each state has 1 flip-flop, hence no encoding; Q of 1 FF =1, Q of others=0 Flip-flop cost = O(n) i.o. O(logn), hence only useful for small number of states: controller Very easy to realise: short design time (time-to-market, e.g. exam) Very small combinatorial circuits to drive the inputs of the flip-flops: cheap combinatorial part, more expensive flipflop part
An FPGA possesses per half CLB a small combinatorial circuit and 1 flip-flop: one-hot encoding is ideal for FPGA implementations (except counters: too many states)
VHDL
3/101

One-hot encoding s0=001 s1=010 s2=100

PRESENT STATE 001 010 100 NEXT STATE / OUTPUT CD=0X CD=10 CD=11 001/0 010/0 100/1 010/0 100/0 001/0 100/0 001/1 010/0
VHDL
3/102

CD=10 Y=1 CD=0X Y=0 CD=10 Y=0 CD=11 Y=0 CD=0X Y=0 CD=10 Y=0 CD=11 Y=0 CD=0X Y=0
s0
CD=11 Y=1
s1
s2
VHDL
Q0 D
Q1 D
Q2 D
3/103
C D

Implementation rule for One-hot with D flip-flop:
Each arriving transition at a state needs an AND gate
VHDL
3/104

CD=10 Y=1 CD=0X Y=0 CD=10 Y=0 CD=11 Y=0 CD=0X Y=0 CD=10 Y=0 CD=11 Y=0 CD=0X Y=0
s0
CD=11 Y=1
s1
s2
VHDL
Q0 S R
Q1 S R
Q2 S R
C Y
3/105
C D

Implementation rule for One-hot with SR flip-flop:
Each arriving transition starting at another state requires an AND gate at the S input Each departing transition to another state requires an AND gate at the R input
VHDL
3/106
Sequential Circuits
VHDL
3/107
Step 4: Choice of the flip-flop type

JK flip-flop
Most expensive flip-flop Most difficult design Largest number of dont cares: probably cheapest (and fastest) combinatorial control logic Used when a different signal sets resp. resets the flip-flop
VHDL
SR flip-flop
Cheap flip-flop Difficult design Many dont cares: probably cheap (and fast) control logic Used when a different signal sets resp. resets the flip-flop
3/108

D flip-flop
Cheap flip-flop Most easy design No dont cares: probably most expensive (and slowest) combinatorial control logic Used when the same signal sets resp. resets the flip-flop, i.e. when the value of a signal has to be remembered temporarily
VHDL
T flip-flop
Cheap flip-flop Easy design No dont cares: probably most espensive (and slowest) combinatorial control logic Used for counters and frequency dividers: fast toggling
3/109

No fixed selection rule exists
When we want the cheapest circuit, all variants have to be tried out When the fastest design time is needed, D flipflops are the best choice FPGAs only possess D flip-flops
VHDL
3/110
Sequential Circuits
VHDL
3/111
Step 5: Realization of the combinatorial logic: D flip-flop

Determine the excitation functions
Q0 Q1 0 x 0 0 x 0 0 x 0
Y 0 D C 0 1
0 0 x 1 Q0
VHDL

Q 0 0 1 1 Q(next) 0 1 0 1 D 0 1 0 1
Q0
Q1n=D1 Q1 1 0 0 Q0n=D0 0 C 0 1
Q1
0 0 x 1 D
C 0 0 x 1 0 x 0 1 x
0 1 x 0 D
1 x 0 0 x 1 0 x 0
3/112
Step 5: Realization of the combinatorial logic: D flip-flop

Q0 Q1n=D1 Q1 Q0n=D0 0 0 x 1 D C 0 0 x 1 1 0 x 0 0 1 x 0 Clr D C Q0 Q1 0 1 x 0 1 x 0 0 x 1 0 x Clr Y 0 0 1 0 D C Y 0 0 1 0 Q0 Q1 0 x 0 0 x 0 0 x 0 0 x 1
VHDL
Q1 D
Q0 D
Cost: 35
1.5 CLB
3/113
C D
Step 5: Realization of the combinatorial logic: T flip-flop

Q0 Q1 0 x 0 0 x 0 0 x 0
Y 0 D C 0 1
0 0 x 1 Q0
VHDL
Excitation table for T flip-flop

Q 0 0 1 1 Q(next) 0 1 0 1 T 0 1 1 0
Q0
T1 Q1 T0 0 C 0 1
Q1
0 0 x 0 D
C 0 0 x 1 0 x 0 1 x 0 1 1
0 0 x 0 D
0 x 0 1 x 1 1 x 0
3/114
Step 5: Realization of the combinatorial logic: T flip-flop

Q0 T1 Q1 0 0 x 0 D C 0 0 x 0 1 0 x 1 0 1 x 1 Clr D C T0 Q0 Q1 0 0 x 0 0 x 0 1 x 1 1 x Clr Y 0 0 1 0 D C Y 0 0 1 0 Q0 Q1 0 x 0 0 x 0 0 x 0 0 x 1
VHDL
Q1 T
Q0 T
Cost: 32
3/115
C D
Step 5: Realization of the combinatorial logic: SR flip-flop

VHDL
Excitation table for SR flip-flop

Q 0 0 1 1 Q(next) S 0 1 0 1 0 1 0 x R x 0 1 0
Q0
S1 Q1 R1 x C 0 x
Q0
Q1
0 0 x x D
C 0 0 x 1 0 x 0 1 x x 0 0
x x x 0 D
x x 0 x x 1 0 x 1
3/116

Q0 Q1 0 x 0 0 x 0 0 x 0
Y 0 D C 0 1
0 0 x 1 Q0
VHDL
Excitation table for SR flip-flop

Q 0 0 1 1 Q(next) 0 1 0 1 S 0 1 0 x R x 0 1 0
Q0
S0 Q1 R0 x C x 0
Q1
0 x x 0 D
C 0 x x 0 0 x 1 0 x 0 1 0
x 0 x x D
0 x x 1 x 0 1 x x
3/117

Q0 Q0 S1 Q1 0 0 x x D C 0 0 x x 1 0 x 0 0 1 x 0 D C R1 x x x x 0 x x 0 Q1 x 0 x 0 x 1 x 1
VHDL
Q1 S R
Q0 S R
3/118
C D

Q0 Q0 S0 Q1 0 x x 0 D C 0 x x 0 0 0 x 1 1 0 x 0 D C R0 x 0 x 0 x 1 0 1 Q1 x x x x x 0 x x
VHDL
Q1 S R
Q0 S R
3/119
C D

Q0 Q0 Q0 S0 Q1 0 x x 0 D C 0 x x 0 0 0 x 1 1 0 x 0 D C R0 x 0 x 0 x 1 0 1 Q1 x x x x x 0 x x D C Y 0 0 1 0 Q1 0 x 0 0 x 0 0 x 0 0 x 1
VHDL
Q1 S R
Q0 S R
Cost: 32
3/120
C D
Step 5: Realization of the combinatorial logic: JK flip-flop

VHDL
Excitation table for JK flip-flop

Q 0 0 1 1 Q(next) 0 1 0 1 J 0 1 x x K x x 1 0
Q0
J1 Q1 K1 x C x x
Q0
Q1
0 0 x x D
C 0 0 x 1 0 x 0 1 x x x x
x x x 0 D
x x 0 x x 1 x x 1
3/121

Q0 Q1 0 x 0 0 x 0 0 x 0
Y 0 D C 0 1
0 0 x 1 Q0
VHDL
Excitation table for JK flip-flop

Q 0 0 1 1 Q(next) 0 1 0 1 J 0 1 x x K x x 1 0
Q0
J0 Q1 K0 x C x x
Q1
0 x x 0 D
C 0 x x 0 x x 1 x x 0 1 0
x 0 x x D
0 x x 1 x x 1 x x
3/122

Q0 Q0 J1 Q1 0 0 x x D C 0 0 x x 1 0 x x 0 1 x x D C K1 x x x x x x x x Q1 x 0 x 0 x 1 x 1
VHDL
Q1 J K
Q0 J K
3/123
C D

Q0 Q0 Q0 J0 Q1 0 x x 0 D C 0 x x 0 0 x x 1 1 x x 0 D C K0 x 0 x 0 x 1 x 1 Q1 x x x x x x x x D C Y 0 0 1 0 Q1 0 x 0 0 x 0 0 x 0 0 x 1
VHDL
Q1 J K
Q0 J K
Cost: 26
3/124
C D
Sequential Circuits
VHDL
3/125

Determine maximum clock frequency
Max. clock frequency = 1/(delay of critical path) Critical path is the path with the longest combinatorial delay between two clock edges Example:
VHDL
Q1 D
Clr
Q0 D
Clr
C D
3/126

Slide Flipflop

Transféré par

Informations du document

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Slide Flipflop

Transféré par

Droits d'auteur :

Formats disponibles

R.

Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

The flip-flop as building block

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

The flip-flop as building block

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

Set and Reset active low

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

C=1: follow inputs C=0: latch outputs

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

DQ delay when C high:

L-to-H H-to-L L-to-H H-to-L

delay: delay: delay: delay:

2.4+1.4+1.4=5.2 1+2.4+1.4=4.8 2.4+1.4+1.4=5.2 2.4+1.4=3.8

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

C=1: follow input C=0: latch output

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

C=1: follow input C=0: latch output

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

C=1: follow input C=0: latch output

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

Level-sensitive latch Master-slave flip-flop Edge-triggered flip-flop

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

Level-sensitive latch Master-slave flip-flop Edge-triggered flip-flop

R.Lauwereins Imec 2001

Level sensitive latch

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Level sensitive latch

Digital design Combinatorial circuits Sequential circuits FSMD design

Clk X Q1 Q2 Q3 Two solutions: Master-slave Edge-triggered

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

Level-sensitive latch Master-slave flip-flop Edge-triggered flip-flop

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design