Coimbatore Institute of Engineering and Technology

Department of Electronics and Communication Engineering

INTERNAL TEST III (25.04.2013) FN
Class: III ECE/ VI SEM

Time: 1Hr 30 min

Subject: VLSI Design

Max.Marks: 50

Part A (Answer all the Questions)

1.

(5x 2 Marks) = 10 Marks

What are the operating regions occurred in MOSFET device? Write down drain current
equation for all the regions.

2.

What is transmission gate? Draw EX-OR gate design using transmission gate.

3.

Explain the tri state circuit operation with neat diagram.

4.

Draw the switch level model & Layout design model for NOR gate.

5.

What is Large FET model?

Part B (Answer all the Questions)

6.

(1x8 Marks) + (2 x 16 Marks) = 40 Marks

(i) Explain in detail about the operation of MOSFET with a neat sketch.

(8)

(or)

7.

(ii) Explain latch-up problem in CMOS circuit and give its prevention methods?

(8)

(i) Explain MOSFET switch model & Square law model in detail.

(8)

(ii) What are parasitic problems in CMOS circuits? Explain MOSFET parasitic in detail? (8)
8.

(i) Explain pass transistor logic in detail.

(8)

(ii) What is a complex logic gates? Draw the gate level model & Layout design model for
F= (a+b) . (c+d)

(8)

Prepared By,
Mr. M. Ramkumar Raja, AP/ECE & Mr. B.Sakthivel, AP/ECE