FINAL STUDY

MULTIPURPOSE INTELLIGENT
STUDENT IDENTITY CARD
USING
RFID SYSTEM

RFID GENERAL DETAILS

Main parts in our system are

1
 (1)RFID reader
(2)RFID tag
(3)AT 89C51
(4)RTC
(5)LCD
(6)Keypad
(7)Max 232
(8)EEPROM
(9)Power Supply

RFID is the radio identification its an ADC(automated data

collection) technology which uses :
1. Radio frequency waves to transfer data between a
reader and movable item to identify categories and
track.

2. It is fact and does not require physical sight or

contact between readers/scanners and tagged item.

3. It performs the operation using low cast components.

4. It attempts to provide unique identification and

backend integration that allows for wide range of
application.

Overview: Other Automated Data Collection

technologies
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1.Barcodes
It is a leading ADC technology. First barcode patent
was issued in 1934. In 1970’s the UPC standard was
adopted by grocery industry. More than 250 barcode
schemes exist. It is one of the most accurate ADC
method error rate is 10000 time lower in manual
keyboard entry. Use to encode numeric or alpha
numeric character. As it is having so many
advantages its good idea but the main thing is it
needs line of sight between the reader and the bar.
2.Magnetic Stripes
It is a thin plastic film containing small magnetic
particles whose pole orientation can be used to
encode data. It is widely used in financial
applications.
Advantages: Large data storage capacity. Data can
be altered.
Disadvantages: Stripes must be in contact with the
scanning equipment for reading. It is expensive.
3.Optical Character Recognition
Specially designed alphanumeric characters machine
readable optical reading device. Both horizontal and
vertical features must be analyzed during decoding.
Advantages: Character can be read by humans and
machine.
Disadvantages: Manually operated scanning
required some skills.

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 First read rate often less than 50%. High substitution
error rate.
Near contact scanning required. Lower scanning rate.

4.Radio Frequency Identification (RFID)

It is a considered as one of the best alternating to
other ADC. It uses RF technology. Communication
occurs in two directions.
HOW IT IS: An identification tag with electronically
encoded data is attached to the item. This tag is a
transponder. It is a device capable of emitting a
signal of its own. When it receives a signal from an
external source, consist of microchip antenna.
The reader transmits low level RF magnetic field
that serve as the power source for the transponder
when it is close enough. When activated the tag
sends data to reader through RF. The reader decodes
and validates RF signal before transmitting it to
collection computer system.
Advantages: NO need of line of sight.

RFID SYSTEM COMPONENT DIAGRAM:

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RFID
Readr Ethern
RFIDTagAnteNworkWsi

RFID SYSTEM LOGICAL VIEW

RFID COMMUNICATION:
The following diagram simply explain the
communication between tag and the reader. There is
a communication channel between the tag and the
reader.

The RFID reader continuously emits radio waves up to

certain rang. The passive tag receive energy form the
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 radio waves and get activated. The reader then gives
command to the tag. Tag receives command and gives
response to the reader. It can be easily understood
from above diagram.

LIMITING FACTORS FOR PASSIVE RFID

1. Reader transmitter power. (Govt. limited)
2. Reader receiver sensitivity.
3. Reader antenna gain. (Govt. limited)
4. Tag antenna gain. (size limted)
5. Power required at tag. (silicon process limited)
6. Tag modular efficiency.
DETAILS OF OPERATIONAL FREQUENCIES FOR RFID

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 UHF Microwave
Frequency LF HF
868 - 915 2.45 GHz &
Ranges 125 KHz 13.56 MHz
MHz 5.8 GHz
Typical Max
Shortest Short Medium Longest
Read Range 1”-12” 2”-24” 1’-10’ 1’-15’
(Passive Tags)
Active tags with
Generally passive Active tags with
integral battery
Generally passive tags only, using integral battery or
Tag Power or passive tags
tags only, using inductive or passive tags using
Source inductive coupling capacitive
using capacitive
capacitive storage,
storage,
coupling E-field coupling
E-field coupling
Data Rate Slower Moderate Fast Faster
Ability to read
near
Better Moderate Poor Worse
metal or wet
surfaces
Access Control &
Security
Identifying widgets Highway toll Tags
Library books supply chain
through Identification of
Laundry tracking
manufacturing private vehicle
Applications processes or in
identification Highway toll
fleets in/out of a
Access Control Tags
harsh environments yard or facility
Employee IDs
Ranch animal Asset tracking
identification
Employee IDs

(A)EFEECTS OF COMMON MATERIAL ON RF (B)

RFID CLASSES
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(A) MATERIAL EFFECT ON RF SIGNAL
Cardboard Absorption (moisture)
Detuning (dielectric)

Conductive liquid Absorption

(shampoo)
Plastics Detuning (Dielectric)
Metals Reflection
Group of cans Complex effects (lenses,
filters)
Reflection
Human body/animals Absorption
Detuning(dielectric)
Reflection

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 (B)

RFID READER
1. Readers are devices which continuously emits radio
frequency up to certain range depending upon the
type of reader used.
2. It is a trans-receiver which can transmit as receive an
information using radio frequency.
3. These devices can be hand-held or portable
depending upon the application.
4. The typical reader has an antenna to communicate
with the tag. The size and the form of the antenna
depend on the application and frequency used.
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5. There are two main classes of RFID readers:
(a)Read only Reader.
(b)Read/write type of reader.

A. Read only reader: These reader are capable of only

reading the information on the tag. We can not
change the information on the tag.
B. Read/write type of reader: These reader can read
the information on the tag as well as this have
capability of change the information present on the
tag.

REDAER FUNCTIONING:
It is used to power up the tag. It established
bidirectional data link. It can communicate with
network server. Inventory tags and filter results. It
can read 100 to 300 tags per tag. These readers
can be fixed or mobile type.

READER’s GENERAL ANATOMY:

A typical reader generally has following parts
1. Digital Signal Processor.
2. Network Processor.
3. Following Radio modules
a. 915MHz
b. 13.56MHz
c. 125KHz
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BLOCK DIAGRAM OF TYPICAL RFID READER
WITH FSK

Probable PCB mounted diagram for RFID

reader with RS232 Interface

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12
The above shown is the probable PCB mounted
diagram of typical
RFID reader for understanding purpose. There are two
processors
these are DSP and N/W processors. DSP deals with
the radio frequency signals. The other circuitry is also
shown in the diagram.
There is a coil antenna which is quit big in size with
other components. This antenna is used for radio
wave transmission.
There are also four pin outs as follows:
1. VCC: This is for providing required voltage to
circuit.
2. GND: For grounding purpose.
3. Sout: Signal out pin to interface with RS232.
4. En : This is kept at ground level.

Readers can also be categorized as follows:

A.RS232 READERS
1. These readers provide raw data on the RS232
port every time the tag is read.
2. Data is not stored insight the reader and will
be lost if controller or PC connected to it does
not read it.
3. Controller can offer many features regarding
RFID readers as per their requirement.

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 B.READERS WITH TCP/IP & controller
1.These readers have TCP/IP Ethernet LAN
controller as well as inbuilt controller with
limited functionality.
2.These readers can be connected to the LAN
network and can be configured to send data
to the server.
3.These are efficiently used over many
systems.

RFID READER VENDORS:

PRINTER FIXED READER HAND HELD

ENCODE READER
Zebra TI Symbol
Printronix Intermec Intermec
Datamax Matrices Hand Held
Products
Sato Alien PCS
AWD PSION TEKLOGIX
Thing Magic

DIFFRENCE BETWEEEN DEDICATED &

EMBEDDED READERS

DEDICATED READERS EMBEDDED READERS

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 Specific functionality &
tag support optimize for
supply chain applications
Maximum performance for
read rate range.
Middleware require for
application integration.
Embedded feature in
another product.
Optimum performance
given cost space and
power requirement.
Single, Intuitive
application interface
native to reader.

RFID TAGS
1. RFID Tags are made of a small silicon chip having a
rotating coil type of antenna. It is a very small circuit.
2. Tags can be attached to almost anything i. e. items
cases , pallet of product, high value goods etc.
3. Vehicles, assets, livestock or personals.
There are two types of tags:
a. Passive tags
b. Active tags
A.Passive tags
1. These tag do not contain internal battery that is
why these are known as Passive tags. It draws
energy from interrogator field.
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 2. It has lower storage capacity.
3. Shorter read range (4 inch to 15 inch).
4. Usually read-ones-write-many/read only tags.
5. Cost about 25 cents to few dollars.
B.Active Tags
1. Battery Powered.
2. High storage capabilities (512kb).
3. Longer read range (300 feet).
4. Typically can be rewritten by RF interrogator.
5. It cost around $50 to $250
There are two main components present in the RFID
tag. Firstly a small silicon chip or integrated circuit
which contain unique identification number secondly an
antenna that can send and receive radio waves. The
antenna consist of flat, metallic conductive coil rather
than protruding FM style aerial. These tags can be quit
small, thin and increasingly easily embedded within
packaging, plastic cards, ticket, clothing label, pallet
and block.

RFID TAG internal Block diagram

RFID TAG MEMORY

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 A. Read only Tags
Tag Id is assigned at the factory during
manufacturing
a. It can never be changed.
b. No additional data can be assigned to tag.
B. Write ones, read many (WORM) tags
Data written once that is during manufacturing
a. Tag is locked once data is written.
b. Similar to the compact disk or DVD.
C. Read/write
Tag data can be changed over time
a. Part of all the data section can be locked.

In our system we are using passive tag. These tags do not

contain their own power source or transmitter. When
radio waves from reader reach the chip antenna, the
energy is converted by the antenna to electricity that can
power up the microchips antenna (parasitic power) then
the tag is able to send back any information in it by
reflecting the electromagnetic waves.

RFID TAG’s LOOK LIKE AS FOLLOWS

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The unique ID that will be serially transmitted to the
reader as 12-byte printable ASCII has the following
format.
Start ID ID ID ID ID ID ID ID ID ID Stop
byte(0X Digit Digit Digit Digit Digit Digit Digit byte(0X
Digit Digit Digit
0A) 1 2 3 4 8 9 10 0D)
5 6 7

The start and the stop bytes are used to easily identify
that the correct string has been received from the reader.
The baud rate is configured as 2400 bps. It is a standard
communication speed supported by most of up’s or PC’s
and cant be changed.

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The face of the tag should be held parallel to the front or
back face to antenna (where the majority of RF energy is
focused). If the tag is held sidewise (perpendicular to
antenna) you may have difficulty getting the tag to be
read. Only one transponder tag is held up to the antenna
at a time. The use of multiple tag at one time can cause
tag collision and confuse the reader.

TAG COLLISION PROBLEM

1. Multiple tag simultaneously respond to query which
results in collision at reader.
2. To avoid this problem, some of the protocols or
approaches are used. These are as follows
a. Tree algorithm.
b. Memory less protocol.
c. Contactless protocol.
d. I-code protocol.

READER-TAG Coupling Types

A. INDUCTIVE COUPLING

B. PROPAGATION COUPLING

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MULTIPLE TAGS IN THE RANGE AT SAME TIME
When multiple tags are in range of reader, all tag
will be excited at the same time and make it very
difficult to distinguish between tags. This is one of the
main problem regarding RFID systems.

There are some tag collision avoiding mechanisms as

follows
1. PARABALISTIC
In this mechanism the tags are return at
different time.
2. DETERMINISTIC
In this mechanism the reader searches for
the specific tag in a group of tag.
EPC & PML
The EPC has following main contents
a. EPC- Electronic Product Code
b. Header- It handles version and upgrades.
c. EPC MANEGER- Product manufacturing code.
d. Object class- class/type of product.
e. Serial no. – Unique object identity.

PML- Physical Markup Language

a. Representation of tagged object information.
b. Introduction of logged object information.

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RFID CLASS STRUCTURE

Microcontroller AT89C51
History:
In 1981, Intel Corporation introduced an eight bit uc
called 8051. This uc had 128 bytes of RAM, 4K of on-chip
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ROM, two timers, one serial port, and 4 ports (8bytes
each) all on single chip. At the time it was also refer as
“System on Chip”. 8051 is an eight bit processor that
means CPU can work 8 bit data at a time. The data more
than 8 bit is broken in to 8 bit data and then processed
through CPU.
The 8051 became more popular after Intel allowed
the manufactures to make and market any flavor of 8051
they pleased with the condition that they remain code
compatible with 8051. This has led to many different
versions of 8051 with different speeds and On-chip ROM.
It is important to note that though there are different
flavors of 8051, all of them are compatible with original
8051 instructions. It means that if you write your program
for one, it will be used for all other flavors.
Basic features:

Features Quantity
ROM 4k bytes
RAM 128 Bytes
TIMER 2
I/O Pins 32
Serial Port 1
Interrupt Sources 6

Basic Architectural block diagram

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AT89C51 from ATMEL Corporation
This popular chip has on-chip ROM in the form of flash
memory. This is ideal for fast development since flash
memory can be erased in seconds. To use AT89C51 to
develop a uc based system requires a ROM burner that
supports a flash memory; however, a ROM eraser not
needed. Note that in flash memory you have to erase it
entirely to reprogram it. This erasing is done by PROM
burner that’s why separate eraser does not needed. To
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eliminate the need for the PROM burner ATMEL is working
on a version of AT89C51 that can be programmed from
the serial com port of IBM PC.
There are various products of ATMEL but we are
interested in AT89C51 only. Actually it is “AT89C51-12PC”.
Here the ‘C’ before the 51 is for CMOS technology, which
has low power consumption, ‘12’ indicates 12 MHz, ‘P’ for
plastic dual in package, ‘C’ is for commercial (‘M’
indicates military). Often AT89C51-12PC is useful for
student projects.
AT89C51 Details
Features
• Compatible with MCS-51™ Products
• 4K Bytes of In-System Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• Fully Static Operation: 0 Hz to 24 MHz
• Three-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial Channel
• Low-power Idle and Power-down Modes
Description
The AT89C51 is a low-power, high-performance CMOS 8-
bit microcomputer with 4K bytes of Flash programmable
and erasable read only memory (PEROM). The device is
manufactured using Atmel’s high-density nonvolatile
memory technology and is compatible with the industry-
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standard MCS-51 instruction set and pin out. The on-chip
Flash allows the program memory to be reprogrammed
in-system or by a conventional nonvolatile memory
programmer. By combining a versatile 8-bit CPU with
Flash on a monolithic chip, the Atmel AT89C51 is a
powerful microcomputer which provides a highly-flexible
and cost-effective solution to many embedded control
applications.

Pin Configuration of PDIP (i.e. using in our

RFID System)

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Block Diagram:

26
27
Pin Description

VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as
highimpedance inputs.

Port 0 may also be configured to be the multiplexed

loworder dress/data bus during accesses to external
program and data memory. In this mode P0 has internal
pullups.

Port 0 also receives the code bytes during Flash

programming, and outputs the code bytes during
program verification. External pullups are required during
program verification.

Port 1
Port 1 is an 8-bit bi-directional I/O port with internal
pullups. The Port 1 output buffers can sink/source four
TTL inputs. When 1s are written to

Port 1 pins they are pulled high by the internal pullups

and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL)
because of the internal pullups.
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Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port 2
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX
@ DPTR). In this application, it uses strong internal pull-
ups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during Flash programming and
verification.

Port 3
Port 3 is an 8-bit bi-directional I/O port with internal
pullups. The Port 3 output buffers can sink/source four
TTL inputs. When 1s are written to

29
Port 3 pins they are pulled high by the internal pullups
and can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IIL)
because of the pullups.

Port 3 also serves the functions of various special

features
of the AT89C51 as listed below:

Port 3 also receives some control signals for Flash

programming and verification.
RST
Reset input. A high on this pin for two machine cycles
while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low
byte of the address during accesses to external memory.
This pin is also the program pulse input (PROG) during
Flash programming.
In normal operation ALE is emitted at a constant rate of
1/6 the oscillator frequency, and may be used for external
timing or clocking purposes. Note, however, that one ALE

30
pulse is skipped during each access to external Data
Memory.
If desired, ALE operation can be disabled by setting bit 0
of SFR location 8EH. With the bit set, ALE is active only
during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external
program memory. When the AT89C51 is executing code
from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are
skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external
program memory locations starting at 0000H up to
FFFFH.
Note, however, that if lock bit 1 is programmed, EA will
be internally latched on reset. EA should be strapped to
VCC for internal program executions. This pin also
receives the 12-volt programming enable voltage (VPP)
during Flash programming, for parts that require 12-volt
VPP.

XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
Oscillator Characteristics

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XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use
as an on-chip oscillator, as shown in Figure 1. Either a
quartz crystal or ceramic resonator may be used. To drive
the device from an external clock source, XTAL2 should
be left unconnected while XTAL1 is driven as shown in
Figure 2. There are no requirements on the duty cycle of
the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum voltage high and low time
specifications must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the
onchip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the
special functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset. It should be noted that
when idle is terminated by a hard ware reset, the device
normally resumes program execution, from where it left
off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access
to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.

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Figure 2. External Clock Drive Configuration

Power-down Mode
In the power-down mode, the oscillator is stopped, and
the instruction that invokes power-down is the last
instruction executed. The on-chip RAM and Special
Function Registers retain their values until the power-
down mode is terminated. The only exit from power-down
is a hardware reset. Reset redefines the SFRs but does
33
not change the on-chip RAM. The reset should not be
activated before VCC is restored to its normal operating
level and must be held active long enough to allow the
oscillator to restart and stabilize.
PROGRAMMING THE FLASH
The AT89C51 is normally shipped with the on-chip Flash
memory array in the erased state (that is, contents =
FFH) and ready to be programmed. The programming
interface accepts either a high-voltage (12-volt) or a low-
voltage (VCC) program enable signal. The low-voltage
programming mode provides a convenient way to
program the AT89C51 inside the user’s system, while the
high-voltage programming mode is compatible with
conventional thirdparty Flash or EPROM programmers.
The AT89C51 is shipped with either the high-voltage or
low-voltage programming mode enabled. The respective
top-side marking and device signature codes are listed
in the following table.

The AT89C51 code memory array is programmed byte-

by-byte in either programming mode. To program any
nonblank byte in the on-chip Flash Memory, the entire
memory must be erased using the Chip Erase Mode.

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Programming Algorithm: Before programming the
AT89C51, the address, data and control signals should be
set up according to the Flash programming mode table
and Figure 3 and Figure 4. To program the AT89C51, take
the following steps.
1. Input the desired memory location on the address
lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming
mode.
5. Pulse ALE/PROG once to program a byte in the Flash
array or the lock bits. The byte-write cycle is self-timed
and typically takes no more than 1.5 ms. Repeat steps 1
through 5, changing the address and data for the entire
array or until the end of the object file is reached.

35
 RTC DS1307 (Real Time Clock)
1. First of all, a real-time clock (RTC) is a computer clock
that will keep track of the current time. You can find
RTC in almost any electronic device that needs to
keep accurate time.
2. Due to the low power consumption and free the main
system for time critical tasks, the RTC is the
favorable choice and always being applied into
electronic device. Beside that, RTC often have an
alternate source of power, and this to allow it to keep
time accurately, even though the primary source of
power is off or unavailable.
3. The alternate source of power is normally a lithium
battery in order systems, but some newer systems
use a supercapacitor, due to they’re rechargeable
and can be soldered easily! In addition, the alternate
power source can supply power to battery backed
RAM too.
4. Today’s PIC project uses a 12C Real Time Clock IC
(DS1307) and four digit seven segment display to
create a standard desk clock. The DS1307 (RTC) Real
Time Clock IC is an 8 pin device that using a 12C
interfaces.
5. It has eight read/write registers that store some
important timing information! By the way, there is a
36
 Clock Halt (CH) bit which is bit 7 of address 0. You
need to reset the CH bit to zero to let the chip
operate.
6. In this way the real time clock can be used in many
embedded projects where the time measurement is
an important factor. Simply we can say that It’s a
device which keeps the record of each second, hour,
day, month, year in this manner.

FEATURES OF DS1307
1. Real time clock counts seconds, minutes, hours,
date of the month, month, day of the week, and
year with leap year compensation valid up to
2100.
2. 56 byte nonvolatile RAM for data storage.
3. 2-wire serial interface.
4. Programmable square wave output signal.
5. Automatic power-fail detect and switch circuitry
6. Consumes less than 500 nA in battery backup
mode with oscillator running
7. Optional industrial temperature range -40°C to
+85°C (IND) available for DS1307 and DS1308.
8. DS1307 available in 8-pin DIP or SOIC DS1308
available in 36-pin SMD BGA (Ball Grid Array).
9. DS1308 accuracy is better than ±2
minute/month at 25°C.
ORDERING INFORMATION
a. DS1307 Serial Timekeeping Chip;8-pin DIP
37
 b. DS1307Z Serial Timekeeping Chip
c. 8-pin SOIC (150-mil)
d. DS1307N 8-pin DIP (IND)
e. DS1307ZN 8-pin SOIC (IND)
f. DS1308 36-pin BGA
g. DS1308N 36-pin BGA (IND)

PIN ASSIGNMENT

38
39
TECHNICAL DESCRIPTION DS1307
The DS1307 Serial Real Time Clock is a low power,
full BCD clock/calendar plus 56 bytes of nonvolatile
SRAM. Address and data are transferred serially via
a 2-wire bi-directional bus. The clock/calendar
provides seconds, minutes, hours, day, date, month,
and year information. The end of the month date is
automatically adjusted for months with less than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The DS1307 has a built-in power
sense circuit which detects power failures and
automatically switches to the battery supply. The
40
DS1308 incorporates the DS1307 chip with a 32.768
kHz crystal in a surface mountable, 36-pin ball grid
array package (BGA). The close proximity of the
embedded crystal to the high impedance crystal
input pins on the DS1307 minimizes capacitive
loading and noise injection problems associated with
many other oscillator designs. The total area required
for installation is less than that of one United States
dime: thus, minimizing PCB space required.

OPERATION
The DS1307/1308 operates as a slave device on
the serial bus. Access is obtained by implementing a
START condition and providing a device identification
code followed by a register address. Subsequent
registers can be accessed sequentially until a STOP
condition is executed. When VCC falls below 1.25 x
VBAT
the device terminates an access in progress and
resets the device address counter. Inputs to the
device will not be recognized
this time to prevent erroneous data from being
written to the device from an out of tolerance
system. When V CC falls below VBAT the device
switches into a low current battery backup mode.
Upon power up, the device switches from battery to
VCC when VCC is greater than VBAT +0.2V and
recognizes inputs when VCC is greater than 1.25 x
41
 VBAT. The block diagram in Figure 1 shows the main
elements of the Serial Real Time Clock.

BLOCK DIAGRAM DS1307

SIGNAL DESCRIPTIONS
1. Vcc,GND: DC power is provided to the device on
these pins. VCC is the +5 volt input. When 5 volts
42
 is applied within normal limits, the device is fully
accessible and data can be written and read.
When a 3-volt battery is connected to the device
and VCC is below 1.25 x VBAT,reads and writes
are inhibited. However, the Timekeeping function
continues unaffected by the lower input voltage.
As VCC falls below VBAT the RAM and timekeeper
are switched over to the external power supply
(nominal 3.0V DC) at VBAT.
VBAT- Battery input for any standard 3-volt
lithium cell or other energy source. Battery
voltage must be held between 2.0 and 3.5 volts
for proper operation. The nominal write protect
trip point voltage at which access to the real time
clock and user RAM is denied is set by the internal
circuitry as 1.25 x VBAT nominal. A lithium
battery with 48mAhr or greater will back up the
DS1307/DS1308 for more than 10 years in the
absence of power at 25 degrees C.
2. SCL (Serial Clock Input): SCL is used to
synchronize datavement on the serial interface.
3. (Serial Data Input/Output): SDA is the
input/output pin for the 2-wire serial interface.
The SDA pin is open drain which requires an
external pullup resistor.
4. SQW/OUT (Square Wave/ Output
Driver):When enabled, the SQWE bit set to 1, the
SQW/OUT pin outputs one of four square wave

43
 frequencies (1 Hz, 4 kHz, 8 kHz, 32 kHz). The
SQW/OUT pin is open drain which requires an
external pullup resistor. NOTE: X1, X2 are not
applicable for the DS1308 or DS1308N.
5. X1, X2: Connections for a standard 32.768 kHz
quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a
specified load capacitance (CL) of 12.5 pF. For
more information on crystal selection and crystal
layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real
Time Clocks.” The DS1307 can also be driven by
an external 32.768 kHz oscillator. In this
configuration, the X1 pin is connected to the
external oscillator signal and the X2 pin is floated.

RTC AND RAM ADDRESS MAP

The address map for the RTC and RAM registers
of the DS1307/DS1308 is shown in Figure 2. The
real time clock registers are located in address
locations 00h to 07h. The RAM registers are located
in address locations 08h to 3Fh. During a multi-byte
access, when the address pointer reaches 3Fh, the
end of RAM space, it wraps around to location 00h,
the beginning of the clock space.

CLOCK AND CALENDAR

44
 The time and calendar information is obtained
by reading the appropriate register bytes. The real
time clock registers are illustrated in Figure 3. The
time and calendar are set or initialized by writing
the appropriate register bytes. The contents of the
time and calendar registers are in the Binary-
Coded Decimal (BCD) format. Bit 7 of Register 0 is
the Clock Halt (CH) bit. When this bit is set to a 1,
the oscillator is disabled. When cleared to a 0, the
oscillator is enabled. Please note that the initial
power on state of all registers is not defined.
Therefore it is important to enable the oscillator
(CH bit=0) during initial configuration. The
DS1307/DS1308 can be run in either 12-hour or
24-hour mode. Bit 6 of the hours register is
defined as the 12- or 24-hour mode select bit.
When high, the 12-hour mode is selected. In the
12-hour mode, bit 5 is the AM/PM bit with logic
high being PM. In the 24-hour mode, bit 5 is the
second 10 hour bit (20-23 hours).

45
 Fig: ADDRESS MAP

MAX 232
GENERAL
1. The MAX232 is an integrated circuit that converts
signals from an RS-232 serial port to signals suitable
for use in TTL compatible digital logic circuits.
2. The MAX232 is a dual driver/receiver and typically
converts the RX, TX, CTS and RTS signals.
3. The drivers provide RS-232 voltage level outputs
(approx. ± 7.5 V) from a single + 5 V supply via on-
chip charge pumps and external (typically 100 nF)
capacitors.
46
 4. This makes it useful for implementing RS-232 in
devices that otherwise do not need any voltages
outside the 0 V to + 5 V range, as power supply
design does not need to be made more complicated
just for driving the RS-232 in this case.
5. The receivers reduce RS-232 inputs (which may be
as high as ± 25 V), to standard 5 V TTL levels. These
receivers have a typical threshold of 1.3 V, and a
typical hysteresis of 0.5 V.
FEATURES
1. Meet or Exceed TIA/EIA-232-F and ITU
Recommendation V.28
2. Operate With Single 5-V Power Supply
Operate Up to 120 kbit/s
3. Two Drivers and Two Receivers
±30-V Input Levels
4. Low Supply Current . . . 8 mA Typical
5. Designed to be Interchangeable With
Maxim MAX232
6. ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)

DIAGRAM

47
48
ORDERING INFORMATION

DESCRIPTION
The MAX232 is a dual driver/receiver that
includes a capacitive voltage generator to supply
EIA-232 voltage levels from a single 5-V supply. Each
receiver converts EIA-232 inputs to 5-V TTL/CMOS
levels. These receivers have a typical threshold of 1.3
V and a typical hysteresis of 0.5 V, and can accept
±30-V inputs. Each driver onverts TTL/CMOS input
levels into EIA-232 levels. The driver, receiver, and
voltage-generator functions are available as cells in
the Texas Instruments LinASIC library.

49
FUNCTION TABLE

LOGIC DIAGRAM (Positive Logic)

50
4×4 KEYPADS
51
STANDARD KEYPADS (GENERAL DETAILS)
1. Standard keypads allow users to press keys or
enter codes to control equipment and machinery.
They use several basic switching technologies. Direct
membrane keypads consist of a membrane painted
with conductive ink, a spacer, and a substrate. Holes
punched in the spacer are arranged so that pressing
a key deflects the contacts on the membrane to
complete the circuit on the substrate.
2. Indirect full-travel membrane keypads mount keys
above three layers of punched, flexible polymer
sheets that are sandwiched together. Circuits are silk-
screened with a conductive silver ink on both the top
and bottom membrane layers.
3. A middle spacer separates the two circuits and holes
punched in the top spacer are arranged so that
pressing a key deflects the top circuit to connect with
the bottom circuit. Carbon pill keypads contain
protruding, pill-shaped covers that are molded over
the top of each key. When a key is pressed, the
conductive pill actuates a pad trace. The average life
for a carbon pill exceeds 5 million actuations. The
contact resistance is usually less than 200 W.
4. Standard keypads mount on the front or rear of
panels and are made from a variety of plastic,
thermoplastic, and metallic materials. There are four
standard keypad sizes: 1 x 4, 3 x 4, 4 x 4 and 5 x 4.
For each keypad size, the first number indicates the
52
 number of columns and the second indicates the
number of buttons.
5. The example of above explanation: let 1 x 4 keypads
have one column and four rows of buttons. 3 x 4
keypads are telephone-style devices with three
columns and four rows of buttons. 4 x 4 keypads
have four columns and four by rows of buttons. 5 x 4
keypads have five columns and four rows of buttons.
6. Electrical switch specifications for standard keypads
include maximum current rating, maximum
alternating current (AC) voltage rating, and maximum
direct current (DC) current rating. Standard keypads
with X-Y outputs are matrix-style devices. Devices
with a single pole or common bus outputs require the
same number of pins as buttons.
7. Standard keypads are often backlit and include light
emitting diodes (LED) to indicate process status,
system functions, machine interlocks, and alarm
conditions. Embossed switches have graphics or
alphanumerical characters that are raised from
switch surface.

8. Switches, panels and keypads that are designed for

outdoor use are water resistant or waterproof and
can withstand both ultraviolet (UV) light and
variations in temperature. Standard keypads that are
used in medical and electronics applications provide
protection from electromagnetic interference (EMI),
53
 radio frequency interference (RFI), and electrostatic
discharge (ESD).

9. ESD protection may be accomplished with static-

dissipative or conductive elements in the switch
material, or through special electronics grounding.

FEATURES
• Quality, Economical Keyboards
• Easily Customized Legends
• Matrix Circuitry
• Backlit and Shielded Options
Available
• Termination Mates With Standard
Connectors
• Tactile Feedback to Operator
• 1,000,000 Operations per Button
• Compatible With High Resistance
Logic Inputs

54
 EEPROM AT24C04
GENERAL
1. EEPROM (also written E2PROM and pronounced e-e-
prom or simply e-squared), which stands for
Electrically Erasable Programmable Read-Only
Memory, is a type of non-volatile memory used in
computers and other electronic devices to store
small amounts of data that must be saved when
power is removed, e.g., calibration tables or device
configuration.
55
 2. When larger amounts of static data are to be stored
(such as in USB flash drives) a specific type of
EEPROM such as flash memory is more economical
than traditional EEPROM devices.
MODE OF FUNCTION
There are different types of electrical interfaces to
EEPROM devices. Main categories of these interface types
are:
• Serial bus

• Parallel bus

How the device is operated depends on the electrical

interface.
Serial bus devices
Most common serial interface types are SPI, I²C,
Microwire, UNI/O, and 1-Wire. These interfaces require
between 1 and 4 control signals for operation, resulting in
a memory device in an 8 pin (or less) package.
The serial EEPROM typically operates in three phases: OP-
Code Phase, Address Phase and Data Phase. The OP-Code
is usually the first 8-bits input to the serial input pin of
the EEPROM device (or with most I²C devices, is implicit);
followed by 8 to 24 bits of addressing depending on the
depth of the device, then data to be read or written.
Each EEPROM device typically has its own set of OP-Code
instructions to map to different functions. Some of the
common operations on SPI EEPROM devices are:
• Write Enable (WREN)
• Write Disable (WRDI)
• Read Status Register (RDSR)
56
 • Write Status Register (WRSR)
• Read Data (READ)
• Write Data (WRITE)
Other operations supported by some EEPROM devices
are:
• Program
• Sector Erase
• Chip Erase commands
Parallel bus devices
Parallel EEPROM devices typically have an 8-bit data bus
and an address bus wide enough to cover the complete
memory. Most devices have chip select and write protect
pins. Some microcontrollers also have integrated parallel
EEPROM.
Operation of a parallel EEPROM is simple and fast when
compared to serial EEPROM, but these devices are larger
due to the higher pin count (28 pins or more) and have
been decreasing in popularity in favor of serial EEPROM
or Flash.
Comparison EPROM and EEPROM/Flash
The difference between EPROM and EEPROM lies in the
way that the memory programs and erases. EEPROM can
be programmed and erased electrically using field
emission (more commonly known in the industry as
"Fowler–Nordheim tunneling").
EPROMs can't be erased electrically, and are programmed
via hot carrier injection onto the floating gate. Erase is via
an ultraviolet light source, although in practice many
57
EPROMs are encapsulated in plastic that is opaque to UV
light, and are "one-time programmable".
Most NOR Flash memory is a hybrid style—programming
is through hot carrier injection and erase is through
Fowler–Nordheim tunneling.

PIN DIAGRAMs AT24C04 DIFFERENT PACKAGES

PIN CONFIGURATION
58
FEATURES
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x
8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write
Modes
• Partial Page Writes Allowed
• Self-timed Write Cycle (5 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years

59
 • Automotive Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra
Thin Mini-MAP (MLP 2x3), 5-lead
SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped
Wafers

Pin Description

1. SERIAL CLOCK (SCL): The SCL input is used to

positive edge clock data into each EEPROM
device and negative edge clock data out of each
device.
2. SERIAL DATA (SDA): The SDA pin is
bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with
any number of other open-drain or opencollector
devices.
3. DEVICE/PAGE ADDRESSES (A2, A1, A0): The
A2, A1 and A0 pins are device address inputs
that are hard wired for the AT24C01A and the
AT24C02. As many as eight 1K/2K devices may
be addressed on a single bus system (device
addressing is discussed in detail under the
Device Addressing section). The AT24C04 uses
the A2 and A1 inputs for hard wire addressing
and a total of four 4K devices may be addressed
on a single bus system. The A0 pin is a no
connect and can be connected to ground. The
AT24C08A only uses the A2 input for hardwire
addressing and a total of two 8K devices may be
60
 addressed on a single bus system. The A0 and
A1 pins are no connects and can be connected
to ground.
The AT24C16A does not use the device address
pins, which limits the number of devices on a
single bus to one. The A0, A1 and A2 pins are no
connects and can be connected to ground.
4. WRITE PROTECT (WP): The
AT24C01A/02/04/08A/16A has a Write Protect pin
that provides hardware data protection. The
Write Protect pin allows normal Read/Write
operations when connected to ground (GND).
When the Write Protect pin is connected to VCC.

RFID RELATED DIAGRAMS

61
CIRCUIT DIAGRAM: ‘MISIC USING RFID’

62
POWER SUPPLY CIRCUIT DIAGRAM

63
64