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Copyright 2007, 2000, 1996 New Age International (P) Ltd., Publishers
Published by New Age International (P) Ltd., Publishers
All rights reserved.
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xerography, or any other means, or incorporated into any information retrieval
system, electronic or mechanical, without the written permission of the publisher.
All inquiries should be emailed to rights@newagepublishers.com
ISBN : 978-81-224-2446-1
PUBLISHING FOR ONE WORLD
NEW AGE INTERNATIONAL (P) LIMITED, PUBLISHERS
4835/24, Ansari Road, Daryaganj, New Delhi - 110002
Visit us at www.newagepublishers.com
PREFACE TO THE FOURTH EDITION
The fourth edi ti on of the book has been thoroughl y revi sed and enl arged. I t i s sui tabl e
for the fi rst course on computer organi zati on and archi tecture, whi ch i s taught at B.Tech.,
BCA and MCA l evel . The fourth edi ti on of the book gi ves the l atest i nformati on on processors,
peri pheral s, supporti ng chi ps, bus standards and softwares. New topi cs i ncl uded i n the book
are as menti oned bel ow:
Chapter 1: Centri no Notebooks, Centri no Duo Mobi l e Technol ogy, mi ddl eware, freeware,
mul ti threadi ng, termi nol ogi es of mobi l e phone standards and data communi cati on, short
range wi rel ess, mi croprogrammed control uni t, vi rus, MP3 compressi on standard, MPEG,
PMP, Di vX etc.
Chapter 3: Al ternati ve ci rcui ts for Mod 3, Mod 5, Mod 6, Mod 10 and Mod 12 counters.
Chapter 5: I ntel 8086 i nstructi ons, Penti um 4, EPI C and I tani um processors, Athl on
64, Athl on 64 FX, Opti ron and Athl on 64 2 processors, Transmeta Corporati on Crusoe
chi ps, VI A C3, ARM and Cel l processors.
Chapter 6: DDR SDRAM, RDRAM (Rambus RAM), Magneto-resi stance, non-vol ati l e
RAM, WPCMCI A etc.
Chapter 7: TFTLCD moni tor, OLED (Organi c Li ght Emi tti ng Di ode) di spl ays, MFDs,
Chi psets, GPU (Graphi cal Processi ng Uni t), etc.
Chaper 8: Opti cal mouse, SQL, DDL, DCL, DML, WI NDOWS-XP, WI NDOWS-2000,
WI NDOWS-2003, Mi crosoft Offi ce-XP, FrontPage, etc.
Chapter 9: Corel Draw, I nstant Messegi ng, Groupware, etc.
Chapter 10: USB, I EEE1394, PCI Express etc.
Chapter 11: Pi pel i ni ng, Array Processors, mul ti processor system, Vector processor;
UMA, SMP and NUMA systems, Cache coherence, snoopy cache scheme, di rectory-based
scheme, Cl usters, di stri buted memory type mul ti processor system, Fl i nns cl assi fi cati on of
computersSI SD, SI MD, MI SD and MI MD etc.
Dr. B. RAM
(v)
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ACkNOWLEDSEMENT
The author wi shes to thank Dr . U.S. Tr i yar , Pr i nci pal , APEEJAY Col l ege of
Engi neer i ng, Sohna, Har yana and Pr of. A.K. Sahni , Depar tment of El ectr i cal
Engi neeri ng, NI T, Patna for thei r val uabl e suggesti ons and encouragement.
Fi nal l y, the author wi shes to thank M/s New Age I nternati onal (P) Ltd., Publ i shers,
New Del hi , for bri ngi ng out the fourth edi ti on of the book.
Dr. B. RAM
(vii)
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CONTENTS
Preface (v)
Acknowledgement (vii)
1. INTRODUCTION 1.1
1.1 Di gi tal and Anal og Computers 1.1
1.2 Evol uti on of Di gi tal Computers 1.2
1.3 Major Components of a Di gi tal Computer 1.7
1.4 Memory Addressi ng Capabi l i ty of a CPU 1.13
1.5 Word Length of a Computer 1.13
1.6 Processi ng Speed of a Mi croprocessor 1.14
1.7 Mi croprocessors 1.14
1.8 Si ngl e-Chi p Mi crocomputers (Mi crocontrol l ers) 1.17
1.9 Computer Cl assi fi cati on 1.18
1.10 User I nterface 1.21
1.11 Hardware, Software, Fi rmware, Mi ddl eware and Freeware 1.21
1.12 Batch Processi ng, Mul ti programmi ng and Mul ti user System 1.23
1.13 Mul ti threadi ng 1.24
1.14 Computer Network 1.24
1.15 Di stri buted Processi ng (Computi ng) or Mul ti processi ng 1.24
1.16 Local Area Network (LAN) and Wide Area Network (WAN) 1.25
1.17 Some Termi nol ogi es of Mobi l e Phone Standards
and Data Communi cati on 1.28
1.18 Short Range Wi rel ess 1.30
1.19 Control Fl ow And Data Fl ow Computers 1.30
1.20 RI SC, CI SC and EPI C Processors 1.31
1.21 Computer Appl i cati ons 1.32
1.22 I mpact of Computers on Soci ety 1.33
1.23 Future Devel opments 1.35
1.24 Virus 1.35
(ix)
1.25 MP3 Compressi on Standard 1.36
1.26 MPEG Compressi on Standard 1.36
1.27 Personal Medi a Pl ayer PMP 1.36
1.28 Di v X 1.36
Problems 1.36
2. NUMBER SYSTEM 2.1
2.1 I ntroducti on 2.1
2.2 Deci mal Number System 2.1
2.3 Bi nary Number (or Base-2) System 2.2
2.4 Conversi on of a Bi nary Number to Deci mal Number 2.3
2.5 Conversi on of a Deci mal Number to a Bi nary Number 2.4
2.6 Addi ti on of Bi nary Numbers 2.6
2.7 Bi nary Subtracti on 2.7
2.8 Use of Compl ements to Represent Negati ve Numbers 2.8
2.9 Conversi on of a Bi nary Fracti on to a Deci mal Fracti on 2.15
2.10 Conversi on of a Deci mal Fracti on to a Bi nary Fracti on 2.16
2.11 Bi nary Coded Deci mal (BCD Codes) 2.17
2.12 Hexadeci mal Number System 2.19
2.13 Octal Number System 2.23
2.14 ASCI I and I SCI I Codes 2.27
2.15 EBCDI C Code 2.30
2.16 Gray Codes 2.30
2.17 Fi xed Poi nt Representati on of Numbers 2.33
2.18 Fl oati ng-Poi nt Representati on 2.34
2.19 Overfl ow and Underfl ow 2.39
Problems 2.40
3. DIGITAL DEVICES 3.1
3.1 Logi c Gates 3.1
3.2 Fl i p-Fl ops 3.8
3.3 Latches 3.17
3.4 Regi sters 3.17
3.5 Shi ft Regi sters 3.17
3.6 Buffers/Dri vers 3.18
3.7 Encoders, Decoders and Code Converters 3.18
3.8 Counters 3.19
(x)
3.9 Di gi tal Mul ti pl exers/Data Sel ectors 3.28
3.10 Di gi tal Demul ti pl exers/Decoders 3.29
Problems 3.30
4. LOGIC DESIGN 4.1
4.1 Bool ean Al gebra 4.1
4.2 Mi ni mum Bool ean Expressi on 4.23
4.3 Karnaugh Map Method of Si mpl i fi cati on of Logi c Expressi on 4.23
4.4 Combi nati onal and Sequenti al Ci rcui ts 4.42
4.5 Ari thmeti c Ci rcui ts 4.43
Problems 4.49
5. CENTRAL PROCESSING UNIT (CPU) 5.1
5.1 I ntroducti on 5.1
5.2 CPU Organi zati on 5.1
5.3 I nstructi on 5.4
5.4 Addressi ng Modes 5.8
5.5 I nterrupts and Excepti ons 5.12
5.6 Pi n Confi gurati on or I ntel 8085 5.13
5.7 Generati on of Some Speci al Control Si gnal s for
Memory and I /O devi ces 5.15
5.8 I nstructi on Cycl e 5.16
5.9 I nstructi on and Data Fl ow 5.17
5.10 Ti mi ng Di agram 5.18
5.11 Mi croprocessors 5.24
5.12 I ntel 8085 5.24
5.13 I ntel 8086 5.24
5.14 Bri ef Descri pti on of I ntel Mi croprocessors 5.35
5.15 I ntel 486 (I ntel 80486) 5.37
5.16 Penti um Processor 5.47
5.17 Penti um MMX Processor 5.48
5.18 Penti um PRO 5.48
5.19 Penti um I I and Penti um I I XEON 5.50
5.20 Cel eron Processor 5.50
5.21 Penti um I I I Processor 5.51
5.22 Penti um 4 Processor 5.52
5.23 I tani um Processor 5.53
(xi)
5.24 PowerPC Mi croprocessor 5.54
5.25 MI PS Mi croprocessors 5.57
5.26 DECS Al pha Mi croprocessors 5.57
5.27 Cyri x Mi croprocessors 5.57
5.28 AMD (Advanced Mi cro Devi ces) Processors 5.58
5.29 Suns Ul trasparc Mi croprocessor 5.58
5.30 Nati onal Semi conductors Mi croprocessors 5.58
5.31 Motorol a Mi croprocessors 5.58
5.32 Transmeta Corporati ons Crusoe Chi ps 5.59
5.33 VI As C3 Processor 5.60
5.34 ARM Mi croprocessors 5.60
5.35 Cel l Processors 5.60
5.36 RI SC, CI SC and EPI C Machi nes 5.60
Problems 5.61
6. MEMORY 6.1
6.1 Mai n Memory, Secondary Memory and Backup Memory 6.1
6.2 Cache Memory 6.2
6.3 Real (or Physi cal ) and Vi rtual Memory 6.4
6.4 Semi conductor Memory 6.5
6.5 Memory Control l ers 6.9
6.6 Magneti c Memory 6.11
6.7 Opti cal Di sks 6.21
6.8 CCD (Charge Coupl ed Devi ces) 6.25
6.9 Direct Access Storage Devi ces (DASDs) 6.26
6.10 Destructi ve and Nondestructi ve Readout 6.26
6.11 Program and Data Memory 6.26
6.12 Memory Management Uni t (MMU) 6.26
6.13 PCMCI A or WPCMCI A Cards and Sl ots 6.29
Problems 6.29
7. I/O DEVICES, MICROCONTROLLERS, I/O
PROCESSORS AND ARITHMETIC PROCESSORS 7.1
7.1 I nput Devi ces 7.1
7.2 Output Devi ces 7.11
7.3 Pri nters 7.19
7.4 Pl otters 7.24
(xii)
7.5 Other Forms of Output Devi ces 7.25
7.6 I nput and Output Port 7.25
7.7 Seri al Data Transfer 7.28
7.8 Programmabl e I nterval Ti mer/Counter 7.33
7.9 Chi psets 7.34
7.10 Data Transfer Schemes 7.34
7.11 Si ngl e-Chi p Mi crocomputers (Mi crocontrol l ers) and
Embedded Mi croprocessors 7.45
7.12 DSP (Di gi tal Si gnal Processor) 7.47
7.13 I /O Processor 7.47
7.14 Ari thmeti c Processors 7.49
7.15 Graphi cs Processors 7.51
Problems 7.51
8. SYSTEM SOFTWARE AND PROGRAMMING TECHNIQUES 8.1
8.1 Machi ne Language 8.2
8.2 Assembl y Language 8.2
8.3 Low-Level and Hi gh-Level Languages 8.3
8.4 Stack 8.8
8.5 Subrouti nes 8.9
8.6 Debuggi ng of Programs 8.11
8.7 Macro 8.12
8.8 Macro Processor (or Keyboard Enhancer) 8.13
8.9 Program Desi gn 8.14
8.10 Software Devel opment 8.18
8.11 Fl ow Charts 8.20
8.12 Mul ti programmi ng or Concurrent Programmi ng 8.22
8.13 Mul ti user or Ti me-Share System 8.23
8.14 Mul ti taski ng System 8.23
8.15 Protecti on 8.24
8.16 Problems in Accessi ng Resources 8.24
8.17 Operati ng System 8.25
8.18 Uti l i ty Programs 8.31
8.19 Appl i cati on Packages 8.32
8.20 BI OS 8.45
Problems 8.46
(xiii)
9. COMPUTER APPLICATIONS 9.1
9.1 Computer Appl i cati ons i n Offi ces 9.1
9.2 Use of Computers i n Books Publ i cati on 9.2
9.3 Desktop Publ i shi ng System 9.3
9.4 Appl i cati on of Computers for Data Anal ysi s 9.4
9.5 Accounti ng, I nvestment, I nventory Control etc. 9.4
9.6 Appl i cati on of Computers i n Graphi cs 9.5
9.7 CAM (Computer Ai ded Manufacture) 9.8
9.8 Appl i cati on of Computers i n Database Management 9.8
9.9 Appl i cati on of Computers i n Project Management 9.9
9.10 Use of Computers i n Communi cati ons 9.10
9.11 Appl i cati on of Computers i n Educati on 9.14
9.12 Appl i cati on of Computers i n Medi cal Fi el d 9.15
9.13 Appl i cati on of Computers i n I ndustri al
Control and I nstrumentati on 9.16
9.14 Ai rl i nes and Rai l ways Ti cket Reservati on 9.17
9.15 Robots 9.18
9.16 Arti fi ci al I ntel l i gence 9.18
9.17 Mi l i tary Appl i cati on of Computers 9.20
9.18 Appl i cati on of Computers i n Banks 9.20
9.19 Appl i cati on of Computers i n Desi gn and Research Work 9.20
9.20 Real -Ti me or Onl i ne Appl i cati ons 9.21
9.21 Poi nt of Sal e (POS) Termi nal s 9.21
9.22 Financial Transaction Termi nal s 9.22
9.23 Some Other Appl i cati on of Computers 9.22
9.24 Computers wi th Vi si ons 9.23
Problems 9.25
10. BUS ARCHITECTURE 10.1
10.1 I ntroducti on 10.1
10.2 I SA BUS 10.1
10.3 EI SA BUS 10.2
10.4 PCI Bus 10.3
10.5 AGP (Accel erated Graphi c Port) 10.3
10.6 PCI Express Bus 10.3
10.7 Uni versal Seri al Bus (USB) 10.5
10.8 I EEE 1394 10.5
(xiv)
10.9 I EEE-1284 10.6
10.10 I EEE-488 BUS 10.6
10.11 Bus System i n a Mul ti processor System 10.6
Problems 10.9
11. PARALLEL PROCESSING 11.1
11.1 I ntroducti on 11.1
11.2 Pi pel i ned Processors 11.1
11.3 Array Processors 11.3
11.4 Vector Processors 11.4
11.5 Mul ti processor system 11.4
11.6 Fl i nns Cl assi fi cati on of Computers 11.11
Problems 11.11
Appendix A-1
Bibliography B-1
I ndex I -1
(xv)
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1.1
1
CHAPTER
164,7+61
INTRODUCTION
Computer i s the most powerful tool man has ever created. Computers have made a great
i mpact on our everyday l i fe. Thei r presence i s fel t at al most every worki ng pl ace, vi z. homes,
school s, col l eges, offi ces, i ndustri es, hospi tal s, banks, retai l stores, rai l ways, research and
desi gn organi zati ons and so on. Computers, l arge and smal l , are used nowadays by al l ki nds
of peopl e for a vari ety of tasks i n a modern and i ndustri al i zed soci ety.
A computer i s basi cal l y a programmabl e computi ng machi ne. Earl i er, computers were
used for compl ex computati ons and used by onl y sci enti sts and engi neers. The trend was to
desi gn l arge and powerful computers to handl e l arge data and sol ve compl ex probl ems. They
were very costl y and hence, onl y l arge organi zati ons coul d afford them. The technol ogi cal
breakthrough i n desi gn and fabri cati on of semi conductor devi ces has made now possi bl e to
manufacture powerful mi crocomputers whi ch are wi thi n the reach of smal l organi zati ons and
even i ndi vi dual s. These computers bei ng very fast can be used not onl y for computati on but
al so to store and retri eve i nformati on, to control certai n processes and machi nes, to measure
and di spl ay certai n physi cal and el ectri cal quanti ti es and so forth. Devel opments i n software
al l ow massi ve appl i cati ons of computers for non-computati onal jobs l i ke text preparati on,
mani pul ati on, storage and retri eval ; transmi ssi on of texts, graphi cs and pi ctures from one
pl ace to another; and arti fi ci al i ntel l i gence and expert systems, for exampl e, robots, and so on.
1.1 DIGITAL AND ANALOG COMPUTERS
Computers whi ch are i n use today are di gi tal computers. They mani pul ate numbers.
They operate on bi nary di gi ts 0 and 1. They understand i nformati on composed of onl y 0s and
1s. I n the case of al phabeti c i nformati on, the al phabets are coded i n bi nary di gi ts. A bi nary
di gi t i s cal l ed bit. A group of 8 bi ts i s cal l ed a byte. Computers do not operate on anal og
quanti ti es di rectl y. I f any anal og quanti ty i s to be processed, i t must be converted i nto di gi tal
quanti ty before processi ng. The output of a computer i s al so di gi tal . I f anal og output i s
needed, the di gi tal output has to be converted i nto anal og quanti ty. I f output i s to be di spl ayed
i n the form of text, the di gi tal output i s converted to al phabets. The components whi ch
convert al phanumeri c characters to bi nary format and bi nary output to al phanumeri c characters
are the essenti al parts of a di gi tal computer. But the el ectroni c components whi ch convert
1.2 COMPUTER FUNDAMENTALS
anal og quanti ty to di gi tal quanti ty or di gi tal quanti ty to anal og quanti ty are connected to a
di gi tal computer as peri pheral s where needed. Processi ng of anal og quanti ty i s usual l y
encountered i n i ndustri al control and i nstrumentati on, not i n general purpose computati on,
text mani pul ati on or i nformati on storage, retri eval or transmi ssi on.
The computer whi ch can process anal og quanti ti es i s cal l ed an analog computer. Today,
anal og computers are rarel y used. Earl i er, anal og computers were used to si mul ate certai n
systems. They were used to sol ve di fferenti al equati ons.
1.2 EVOLUTION OF DIGITAL COMPUTERS
El ectroni c computers usi ng val ves appeared i n 1940s. The successful general purpose
mechani cal computers were devel oped i n 1930s. Before 1930 mechani cal cal cul ators were
bui l t for automati c addi ti on, subtracti on, mul ti pl i cati on and di vi si on. A cal cul ator i s not a
programmabl e devi ce. Cal cul ati ons are performed usi ng step-by-step techni que. The user does
not prepare program for hi s cal cul ati on. A computer i s a programmabl e machi ne. A program
i s to be prepared to sol ve a probl em.
1.2.1 The Mechanical Era
The fi rst mechani cal cal cul ator was devel oped i n 1623 by Wi l hel m Schi ckhard, a professor
at the Uni versi ty of Tubi ngen. Hi s machi ne di d not become popul ar. A popul ar mechani cal
cal cul ator was devel oped i n 1642 by the great French phi l osopher and sci enti st Bl ai se Pascal .
Hi s machi ne was capabl e of performi ng addi ti on and subtracti on automati cal l y. For thi s the
machi ne empl oyed counter wheel s. There were two sets of si x di al s or counter wheel s to
represent deci mal numbers. The cal cul ator contai ned a mechani sm for automati c transfer of
carry whi l e performi ng the sum of two numbers. The numbers were represented by the
posi ti ons of the counter wheel s. Around 1671 Pascal s machi ne was extended to perform
mul ti pl i cati on and di vi si on automati cal l y by German phi l osopher and sci enti st Gottfri ed Lei bni z.
Thi s machi ne consi sted of two parts: one part to perform addi ti on and subtracti on and the
other part to perform mul ti pl i cati on and di vi si on. The part whi ch performed addi ti on and
subtracti on was si mi l ar to the cal cul ati ng box of Pascal . I t further i ncl uded two addi ti onal sets
of wheel s to represent mul ti pl i er and mul ti pl i cand. Chai ns and pul l eys were used to i mpl ement
mul ti pl i cati on.
I n 1823, Charl es Babbage tri ed to bui l d a mechani cal computi ng machi ne capabl e of
performi ng automati c mul ti step cal cul ati ons. He named hi s machi ne a di fference engi ne.
Thi s was desi gned to compute tabl es of functi ons such as l ogari thms and tri gonometri c
functi ons. A pol ynomi al was used to represent a functi on. The method of fi ni te di fferences
was used to eval uate a functi on. He coul d not compl ete the machi ne. Swede George Scheutz
successful l y bui l t a di fference engi ne whi ch coul d handl e thi rd-degree pol ynomi al s and
15-di gi t numbers.
I n 1830s Charl es Babbage concei ved of a much more powerful mechani cal computer. He
cal l ed thi s machi ne an anal yti cal engi ne. Thi s machi ne was desi gned to per for m any
mathemati cal cal cul ati on automati cal l y. I t contai ned al l the essenti al components of a modern
di gi tal computer, namel y:
(i) A processor capabl e of performi ng addi ti on, subtracti on, mul ti pl i cati on and di vi si on.
He cal l ed i t a mi l l .
C
H
A
P
T
E
R

1
I NTRODUCTI ON 1.3
(ii) A memory uni t. I t was constructed from deci mal counti ng wheel s. I ts capaci ty was
1000 numbers, each number consi sti ng of 50 di gi ts.
(iii) Several I /O devi ces such as a card punch, a punch-card reader and a pri nter.
The anal yti cal machi ne was a programmabl e machi ne. I t had a mechani sm for enabl i ng
a program to change the sequence of i ts operati ons automati cal l y. I n other words there were
condi ti onal branches of i nstructi ons i n the program. The condi ti on was based on the si gn of
a number. One sequence of operati ons was to be performed i f the si gn were posi ti ve, and
another one, i f negati ve. Babbages anal yti cal machi ne was al so not compl eted.
I n the l ate ni neteenth century punched cards were commerci al l y used. Herman Hol l eri th
was the i nventor of punched-card tabul ati ng machi ne. The major appl i cati on of hi s machi ne
came about i n the 1890 Uni ted States Census. I n 1896 he formed the Tabul ati ng Machi ne
Company to manufacture hi s machi nes. I n 1911 hi s company was merged wi th several others
to form the Computi ng-Tabul ati ng Recordi ng Company. Thi s very company was renamed as
the I nternati onal Busi ness Machi nes Corporati on (I BM) i n 1924.
Successful general purpose mechani cal computers were bui l t i n 1930s. Konard Zuse
devel oped a mechani cal computer, the Z1, i n 1938 i n Germany. The Z1 used bi nary number
system i nstead of deci mal system. Konard was unaware of Babbages work. He bui l t several
smal l mechani cal computers. The Z3 was compl eted i n 1941. I t i s bel i eved to be the fi rst
operati onal general purpose computer. The Z3 empl oyed rel ays (el ectromechani cal bi nary
swi tches) to construct ari thmeti c uni t. The machi ne used fl oati ng-poi nt number representati on.
Howard Ai ken, a professor of Physi cs at Harvard Uni versi ty, desi gned a general purpose
mechani cal di gi tal computer. Thi s machi ne was called an Automati c Sequence Control l ed
Cal cul ator and l ater as Harvard Mark I . I t was constructed i n cooperati on wi th I BM, a l eadi ng
manufacturer of offi ce equi pment at that ti me. Ai ken was aware of Babbages work. He used
deci mal counters wheel s for i ts mai n memory. I ts memory capaci ty was seventy two 23-di gi t
deci mal numbers. Punched paper tape was used to program and control the machi ne. Mark
I started worki ng i n 1944. Later, Mark I I was built by Ai ken and hi s col l eagues. Mark I I
empl oyed el ectromechani cal rel ays for i ts operati on. Many computers usi ng el ectromechani cal
rel ays were bui l t i n the 1940s. But they were qui ckl y superseded by faster and more rel i abl e
el ectroni c computers.
1.2.2 The Electronic Era
The fi rst el ectroni c computer usi ng val ves was devel oped by John V. Atanasoff i n the
l ate 1930s at I owa State Uni versi ty. I t contai ned an add-subtract uni t. I t was rel ati vel y a
smal l computer and used about 300 val ves. I ts memory uni t consi sted of capaci tors mounted
on a rotati ng drum. I t used bi nary numbers for i ts operati on. Each capaci tor was capabl e of
stori ng one bi nary di gi t. I t used a number of i nput/output (I /O) devi ces i ncl udi ng a card punch
and a card reader. I t was compl eted i n 1942. I t was a speci al purpose computer to sol ve
si mul taneous equati ons. Several other el ectroni c computers usi ng val ves were successful l y
constructed i n the earl y 1940s. Some i mportant computers were the seri es of computers
cal l ed Col ossus devel oped i n Engl and.
The fi rst popul ar general purpose el ectroni c di gi tal computer was the ENI AC (El ectroni c
Numeri cal I ntegrator and Cal cul ator). I t was devel oped at the Uni versi ty of Pennsyl vani a
under the gui dance of John W. Mauchl y and J. Presper Eckert. John von Neumann was the
consul tant of the ENI AC project. I t was a very l arge machi ne wei ghi ng about 30 tons and
contai ni ng about 18000 vacuum tubes. I t took 200 mi croseconds for addi ti on and 3 mi l l i seconds
1.4 COMPUTER FUNDAMENTALS
to perform a 10-di gi t mul ti pl i cati on. I t used deci mal numbers for i ts operati on rather than
bi nary numbers. I ts worki ng memory was composed of 20 el ectroni c accumul ators. Each
accumul ator was capabl e of stori ng a si gned 10-di gi t deci mal number. A deci mal di gi t was
stored i n a ri ng counter consi sti ng of 10 vacuum-tube fl i p-fl ops connected i n a cl osed l oop.
Li ke Anal yti cal Engi ne and Mark I , i n ENI AC al so programs and data were stored i n separate
memori es. I ntroduci ng a new program or modi fyi ng a program was an extremel y tedi ous job
wi th separate memori es for program and data.
The ENI AC desi gners, most notabl y John von Neumann, gave an i dea to use a hi gh-
speed memory to store both program as wel l as data duri ng program executi on. Thi s i dea i s
known as stored program concept and was fi rst publ i shed by Neumann for a new computer
EDVAC (El ectroni c Di screte Variable Automati c Computer) i n 1945. Thi s machi ne started
operati on i n 1951. I t used bi nary rather than deci mal numbers for i ts operati on. I t used seri al
bi nary-l ogi c ci rcui ts. I t used a l arger mai n memory (mercury-del ay l i ne) 1 K words and a sl ow
secondary memory (magneti c wi re memory) 20 K words (where K stands for Ki l o whi ch i s
equal to 1024 to be exact). Access to the mai n memory was bi t by bi t, i .e., seri al .
Neumann and hi s col l eagues desi gned and bui l t a new computer cal l ed I AS (I nsti tute of
Advanced Studi es) at the I nsti tute for Advanced Studi es i n Pri nceton duri ng 1946-1952. Thi s
machi ne had the features of a modern computer. I t used random access mai n memory
consi sti ng of cathode-ray-tube. An enti re word coul d be accessed i n one operati on. I t used
paral l el bi nary ci rcui ts. The CPU contai ned several hi gh-speed (vacuum tube) regi sters to
store operands and resul ts. Thi s computer served as the prototype for most subsequent
general purpose computers. The basi c l ogi cal structure proposed by Neumann i s sti l l used i n
a standard computer. The term Neumann Computer became synonymous wi th standard
computer archi tecture. A standard archi tecture i ncl udes a CPU, memory and i nput/output
devi ces. I n future the archi tecture may change; i nstead of a central i zed processi ng, di stri buted
processi ng may be used wi th correspondi ng other changes i n the desi gn and archi tecture.
The transi stor was i nvented i n 1948 at AT & T Bel l Laboratori es. I n the 1950s the
engi neers started usi ng transi stors i n pl ace of vacuum tubes to construct computers. One of
the earl i est computers usi ng transi stors was TX-O. I t was an experi mental computer bui l t at
the Massachusetts I nsti tute of Technol ogys Li ncol n Laboratori es. I t started operati on i n
1953. Commerci al computers usi ng transi stors were constructed i n the l ate 1950s and earl y
1960s by many compani es. For exampl e, I BM i ntroduced a l arge computer, the 7090, for
sci enti fi c appl i cati ons. I t was a transi stori zed versi on of the I BM 709, a vacuum-tube computer.
The transi stori zed computers used transi stors as the components of CPU. These computers
used ferri te core mai n memory and magneti c di sk, drum and tapes as secondary memory.
Ferri te core memori es consi st of ti ny ri ngs (cores) of magneti c materi al cal l ed ferri te. Each
ferri te core stores a si ngl e bi t of i nformati on. Transi stori zed computers were faster and
compact, and consumed much l ess power compared to vacuum tube computers.
I ntegrated Ci rcui ts (I Cs) were fi rst desi gned and fabri cated i n 1958-1959 by Jack S. Ki l by
at Texas I nstruments, and by Robert S. Noyce at Fai rchi l d i ndependentl y. The fi rst commerci al
I C was i ntroduced i n 1961 by Fai rchi l d. I Cs began to repl ace transi stor ci rcui ts si nce 1965.
The exampl es of computers usi ng I Cs are I BM 370 and PDP-8. By 1970 al l new computers
used I Cs, SSI and MSI as CPU components and LSI for mai n memory. SSI , MSI , LSI , VLSI
and ULSI are the cl assi fi cati on of I Cs based on components densi ty. SSI contai ns components,
usual l y transi stors, 1 to 100, MSI 100 to 1000, LSI 1000 to 10,000, VLSI more than 10,000
and ULSI mi l l i ons.
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The fi rst LSI chi ps were i ntroduced i n 1970 i n the form of computer memory uni ts. Wi th
the advent of LSI and VLSI chi ps i t became possi bl e to fabri cate the whol e CPU uni t on a
si ngl e chi p cal l ed mi croprocessor. The fi rst mi croprocessor, the 4004 was i ntroduced i n 1971
by I ntel Corporati on. The fi rst si ngl e-chi p mi crocomputer TMS 1000, a 4-bi t mi crocontrol l er,
was devel oped by Texas I nstruments i n the year 1974. An 8-bi t mi crocontrol l er, the 8048 was
i ntroduced i n 1976 by I ntel . Computers bui l t i n 1970s and onwards used mi croprocessors and
other LSI , VLSI and ULSI components.
Computer Generations
First Generation (1946-1954). The di gi tal computers usi ng el ectroni c val ves (vacuum
tubes) are known as fi rst-generati on computers. Some exampl es of the fi rst-generati on
computers are: I BM 700 seri es-I BM 701, I BM 704, I BM 709, EDVAC and UNI VAC. The fi rst-
generati on computers usual l y used vacuum tubes as CPU components. The hi gh cost of
vacuum tubes prevented thei r use for mai n memory. So l ess costl y but sl ower devi ces such
as acousti c del ay l i nes wer e used for memor y. They stor ed i nfor mati on i n the for m of
propagati ng sound waves. El ectrostati c memori es have al so been used i n the fi rst generati on
computers. Magneti c tape and magneti c drums were used as secondary memory. A fi rst
generati on computer, Whi rl wi nd I , constructed at MI T was the fi rst computer to use ferri te
core memory. The fi rst generati on computers used machi ne l anguage and assembl y l anguage
for programmi ng. They used fi xed-poi nt ari thmeti c. Punched cards and paper tapes were
devel oped to feed programs and data and to get resul ts. Punched card and paper tape readers
and pri nters were i n use.
Second Generation (1955-1964). The second-generati on computers used transi stors for
CPU components and ferri te cores for mai n memory, and magneti c di sks and tapes for
secondary memory. They used hi gh-l evel l anguages such as FORTRAN (1956), ALGOL
(1960) and COBOL (1960) for pr ogr ammi ng. Fl oati ng-poi nt ar i thmeti c har dwar e was wi del y
used. I /O pr ocessor was i ncl uded to contr ol i nput/output oper ati ons. I t r el i eved CPU fr om
many ti me-consumi ng r outi ne tasks. Exampl es of second gener ati on computer s ar e: I BM
1620 (1960), I BM 7090 (1960), I BM 7094I (1962), 7094I I (1964); Contr ol Data Cor por ati ons
CDC 1604; and Di gi tal Data Cor por ati ons PDP 1 (1957), PDP 5 (1963) and PDP 8 (1965).
PDP (Pr ogr ammed Data Pr ocessor ) ser i es i s a ser i es of mi ni computer s. PDP 8 was a 12-
bi t mi ni computer. I ts ear l i er uni ts used tr ansi stor s; I C ver si on was i ntr oduced i n 1967.
Punched car ds and paper tapes and thei r r eader s wer e used as I /O devi ces. Pr i nter s wer e
i n use.
Third Generation (1965-1974). The thi rd-generati on computers used I Cs (SSI and MSI )
for CPU components. I n the begi nni ng thi rd generati on computers used magneti c core memory,
but l ater on semi conductor memori es (RAMs and ROMs) were used. Semi conductor memori es
were LSI chi ps. Magneti c di sks, and tapes were used as secondary memori es. Cache memory
was al so i ncorporated i n the computers of thi rd generati on. Mi croprogrammi ng, paral l el
processi ng (pi pel i ni ng, mul ti processor system, etc.), mul ti processi ng, mul ti programmi ng,
mul ti user system (ti me-share system), etc. were i ntroduced. The concept of vi rtual memory
was al so i ntroduced. The exampl es of thi rd generati on computers are: I BM/370 seri es (1970),
CDC 7600 (1969), PDP 11 (16-bi t mi ni computer, 1970), CDCs CYBER-175 and STAR-100, etc.
I /O devi ces were punched cards, magneti c tapes and pri nters.
Fourth Generation (1975-1990). I n the fourth-generati on computers mi croprocessors
were used as CPU. VLSI chi ps were used for CPU, memory and supporti ng chi ps. The
el ectroni c ci rcui try of up to 1.2 mi l l i on transi stors were pl aced on a si ngl e si l i con chi p.
1.6 COMPUTER FUNDAMENTALS
Computers of earl i er generati on used separate I Cs for cache memory, FPU (Fl oati ng-Poi nt
Uni t i.e., Match Processor), MMU (Memory Management Uni t) etc. Now mi croprocessor chi ps
contai ned al l such uni ts besi des CPU on a si ngl e chi p. They were packed i n a si ngl e I C.
Mul ti functi onal peri pheral chi ps were avai l abl e. They contai ned i nterrupt control l er, DMA
control l er, ti mer-counters, bus control l er etc. i n a si ngl e I C. These are essenti al components
requi red for a computer. Computer of thi s generati on were very fast. They performed i nternal
operati ons i n mi croseconds. 8, 16 and 32-bi t mi croprocessors were devel oped duri ng thi s peri od.
Mai n memory used fast semi conductor chi ps up to 4 Mbi ts si ze. Hard di sks were used
as secondary memory. Hard di sk dri ves of hundreds of megabytes were avai l abl e. Fl oppy
di sks and magneti c tapes were used as backup memory. Keyboard, CRT di spl ay (moni tor), dot-
matri x pri nters etc. were used as peri pheral s. I nkjet, l aser and l i ne pri nters, were devel oped
duri ng thi s peri od. PCs (Personal Computers) were avai l abl e. Such computers can be easi l y
pl aced on a desk and hence, they were al so known as desk computers. They were si ngl e-user
computer s. Dur i ng thi s per i od computer s wer e wi thi n the r each of smal l or gani zati on,
i nsti tuti ons, professi onal s and i ndi vi dual s. The desktop computers were more powerful than
the mai nframe computers of 1970s. Computers became very powerful and smal l i n si ze.
Duri ng thi s peri od computer network: LANs and WANs were al so devel oped. Operati ng
systems MS-DOS, UNI X, Appl es Maci ntosh etc. were avai l abl e. Appl es Maci ntosh wi th GUI
(Graphi cal User I nterface) was devel oped. Object-ori ented l anguage C
++
was devel oped. Si ngl e-
chi p mi crocomputers (mi crocontrol l ers) were avai l abl e. They were wi del y used i n i ndustri al
control , i nstrumentati on, commerci al appl i ances etc. Software packages for word processi ng,
spread-sheet, database management etc. were devel oped. Exampl es of fourth-generati on
computers were: I ntel s 8088, 80286, 80386 and 80486 based computers; Motorol as 6800,
68020, 68030 and 68040 based computers, I BM 3090, VAX 9000, Supercomputers-Cray-1, Cray-
2, Cray X-MP, Cray Y-MP, Hi tachi 828/80 etc.
Fifth-Generation (1991-Continued). Fi fth-generati on computer use ULSI (Ul tra-Large
Scal e I ntegrati on) chi ps. Mi l l i ons of transi stors are pl aced i n a si ngl e I C i n ULSI chi ps. I ntel s
Penti um 4 Prescott contai ns 160 mi l l i on transi stors and I tani um 2 processor contai ns more
than 400 mi l l i on transi stors. 64-bi t mi croprocessors have been devel oped duri ng thi s peri od.
Data fl ow and EPI C archi tectures of processors have been devel oped. I ntel s processors
Penti um Pro onwards use data fl ow archi tecture and I tani um uses EPI C archi tecture. Von
Neumann archi tecture are sti l l used i n l ess powerful CPUs. RI SC and CI SC both types of
desi gn are used i n modern processors. I ntel s up to Penti um 4 and AMDs processors use CI SC
desi gn. SUN, MI PS, HP etc. use RI SC desi gn for thei r processors. 32-bi t mi crocontrol l ers
(Si ngl e-Chi p Mi crocomputers) have been devel oped for i ndustri al and commerci al appl i cati on.
Nowadays mul ti medi a computers are becomi ng common. A mul ti medi a computer can accept
text, sound and/or i mage as i nput and gi ve output i n the form of text, sound and/or i mages.
They can handl e ani mati on. Computers usi ng arti fi cal i ntel l i gence (expert systems) are now
avai l abl e. Robots have been devel oped. They can work i n envi ronment where human bei ngs
can not do. Powerful handhel d and notebook computers are now avai l abl e. Fi fth-generati on
computers use extensi ve paral l el processi ng, mul ti pl e pi pel i nes, mul ti pl e processors etc.
Memory chi ps and fl ash memory up to 1Gbi ts, hard di sk dri ves up to 600 Gbytes and
opti cal di sks up to 50 GB have been devel oped. I nkjet and l aser pri nters are commonl y used.
I n some appl i cati ons dot-matri x pri nters are sti l l used. Computers wi th vi si on have been
devel oped. I nternet i s becomi ng popul ar and peopl e are getti ng al l ki nds of i nformati on from
di stant pl aces usi ng I nternet. Vi deo conferenci ng i s al so i n use. Object-ori ented l anguage Java
for I nternet programmi ng i s wi del y used. Heterogeneous computers are connected to I nternet.
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Heterogeneous computers mean computers of di fferent make and havi ng di fferent operati ng
systems. Programs wri tten i n Java for one computer can run on any other computer. I t
means that Java i s qui te sui tabl e for I nternet programmi ng for heterogeneous computers.
Operati ng systems avai l abl e today are : WI NDOWS-95, 98, XP, 2000, 2003; Appl es Mac OS-
8, 9, 10 and X; SUNs Sol ari s, LI NUX etc. Al l OS now i ncl ude GUI . Exampl es of processors
are: I ntel s Penti um to Penti um 4, I tani um; Motorol as Power PC, MI PS, Compaqs Al pha,
SUNs Ul tra SPARC I I I , AMDs Athl on, Athl on 64, ARM processors, Cel l processors etc.
I nternal processi ng ti me i s now i n nanoseconds.
Super scal ar pr ocessor s, vector pr ocessor s, DSP (Di gi tal Si gnal Pr ocessor ), symbol i c
processors, SI MD (Si ngl e I nstructi on Mul ti pl e Data) processors, mul ti core processors, expert
systems empl oyi ng arti fi ci al i ntel l i gence, etc. have been devel oped. Supercomputers avai l abl e
today are I BMs Bl ueGene/L DD2 Beta-system havi ng speed of 70.7 TFLOPS, Col umbi a
(NASA) havi ng speed of 51.9 TFLOPS, Earth si mul ator (NEC) havi ng speed of 40 TFLOPS etc.
1.3 MAJOR COMPONENTS OF A DIGITAL COMPUTER
The major components of a di gi tal computer are: CPU (central processi ng uni t), memory,
i nput devi ce and output devi ce. The i nput and output devi ces are al so known as peri pheral s.
Fi g. 1.1 shows a schemati c di agram of a di gi tal computer.
Fig. 1.1 Schemati c di agram of a di gi tal computer.
1.3.1 CPU
The CPU i s the brai n of a computer. I ts pri mary functi on i s to execute programs. Besi des
executi ng programs, the CPU al so control s the operati on of al l other components such as
memory, i nput and output devi ces. Under i ts control , programs and data are stored i n the
memory and di spl ayed on the CRT screen or pri nted by the pri nter.
The CPU of a smal l computer i s a mi croprocessor. Fi g. 1.2 shows the schemati c di agram
of a mi crocomputer. The CPU of a l arge computer contai ns a number of mi croprocessors and
other I Cs on one or more ci rcui t boards. Each mi croprocessor i n a l arge CPU performs a
speci fi c task.
Fi g. 1.3 shows the schemati c di agram of a CPU or mi croprocessor. The major secti ons
of a CPU are:
(i) Arithmetic and Logic Unit (ALU)
The functi on of an ALU i s to perform ari thmeti c and l ogi c operati ons such as addi ti on,
subtracti on, mul ti pl i cati on, and di vi si on; AND, OR, NOT (compl ement) and EXCLUSI VE-OR
operati ons. I t al so performs i ncrement, decrement, shi ft and cl ear operati ons.
1.8 COMPUTER FUNDAMENTALS
Fig. 1.2 Schemati c di agram of a mi crocomputer.
Fig. 1.3 Schemati c di agram of a CPU or mi croprocessor
(ii) Timing and Control Unit
The ti mi ng and control uni t generates ti mi ng and control si gnal s necessary for the
executi on of i nstructi ons. I t provi des status, control and ti mi ng si gnal s necessary for the
operati on of other parts of the CPU, memory and I /O devi ces. I t control s the enti re operati on
of a computer. I t i s actual l y the control secti on of the CPU, whi ch acts as the brai n of a
computer.
(iii) Accumulator, General and Special Purpose Registers
The accumul ator i s a regi ster whi ch hol ds one of the operands pri or to the executi on of
an i nstructi on and servi ces resul t of the most ari thmeti c and l ogi cal operati ons. I t i s the most
frequentl y used regi ster. Some CPUs contai n a si ngl e accumul ator, and some contai n several
accumul ators. General purpose regi sters store data and i ntermedi ate resul ts duri ng the
executi on of a program. They are accessi bl e to programmers through i nstructi ons i f they are
worki ng i n an assembl y l anguage. Speci al purpose regi sters are not accessi bl e to users. They
are used by the computer for di fferent purposes duri ng program executi on. Exampl es of
speci al purpose regi sters are: program counter, stack poi nter, i ndex regi sters, i nstructi on
regi ster, etc.
1.3.2 Memory
The functi on of the memory i s to store i nformati on. I t stores program, data, resul ts or
any other ki nd of i nformati on. Two or three l evel s of memori es such as mai n memory,
secondary memory and cache memory are provi ded i n a di gi tal computer. The main memory
(or pri mary memory) i s a fast memory. I t stores programs al ong wi th data, whi ch are to be
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I NTRODUCTI ON 1.9
executed. I t al so stores necessary programs of the system software, whi ch are requi red to
execute the users program. The mai n memory i s di rectl y addressed by the CPU. Semi conductor
memori es, RAMs are used as mai n memory. I t possesses random access property, and has
smal l er access ti me, about 50 ns (nanosecond). Secondary (or auxiliary) memory stores operati ng
system, data fi l es, compi l ers, assembl ers, appl i cati on programs, etc. The CPU does not read
i nformati on (resi di ng i n the secondary memory) di rectl y from the secondary memory. The
programs and data (resi di ng i n secondary memory), i f needed by CPU, are fi rst transferred
from the secondary memory to the pri mary memory. Then the CPU reads them from the
pr i mar y memor y. The r esul ts ar e al so stor ed i n the secondar y memor y. The secondar y
memory i s a mass storage memory. I t i s sl ow but cheap. I t i s a permanent memory whi l e
the mai n memory (RAM) i s vol ati l e memory. The capaci ty of the mai n memory i s comparati vel y
much smal l er than that of the secondary because of i ts hi gh cost. Hard di sks are used as
secondary memory. Thei r access ti me i s about 5-10 ms (mi l l i second).
The cache memory i s pl aced i n between the CPU and the mai n memory. I t i s much faster
than the mai n memory; access ti me about 10 ns. I t stores i nstructi ons and data whi ch are
to be i mmedi atel y executed. I t i s much costl i er than the mai n memory. Hence, from cost
consi derati on i ts capaci ty i s kept much l ess than that of the mai n memory.
Destructive and Nondestructive Readout
I n some memori es the process of readi ng the memory destroys the stored i nformati on.
Thi s property i s cal l ed destructive readout (DRO). Exampl e of a memor y havi ng DRO
characteri sti c i s a dynami c RAM. I n some memori es the process of readi ng i nformati on does
not destroy the stored i nformati on. Thi s characteri sti c of the memory i s cal l ed nondestructive
read-out (NDRO). Exampl es of memori es havi ng NDRO features are stati c RAM, hard di sks,
fl oppy di sks, magneti c tapes, etc.
Real (or Physical) and Virtual Memory
The real or physi cal memory i s the actual mai n memory avai l abl e i n a computer system.
I t i s di rectl y addressed by the CPU.
The techni que whi ch al l ows a program to use mai n memory more than a computer
real l y has i s cal l ed virtual memory technique. For exampl e, the 80386 mi croprocessor can
have the maxi mum physi cal memory capaci ty 4 gi gabytes (GB) but i ts vi rtual memory capaci ty
i s much l arger, 64 terabytes (TB) [see detai l s i n Chapter 6].
Direct Access Storage Devices (DASD), On-Line and Off-Line Memory Devices
Whi l e processi ng data i t i s often requi red to access any record at any ti me. I t may be
desi red to access a si ngl e record, update i t and put i t back i n i ts ori gi nal pl ace. Thi s type
of data pr ocessi ng i s cal l ed di r ect pr ocessi ng or r andom pr ocessi ng. I t needs l ocati ng,
retri evi ng and updati ng any record stored i n a fi l e wi thout readi ng the precedi ng or succeedi ng
records i n the fi l e. These requi rements can be ful fi l l ed wi th di rect access storage devi ces
(DASD equi pment). DASD i ncl udes hard di sks, fl oppy di sks and several forms of opti cal
di sks.
Memory devi ces whi ch al ways remai n connected to a computer system are cal l ed on-l i ne
devi ces. Hard di sks are on-l i ne secondary memory. The devi ces that can be connected to the
system when needed are known as off-l i ne memory. Magneti c tape i s an exampl e of off-l i ne
memor y.
1.10 COMPUTER FUNDAMENTALS
Memory Management
I n a mul ti user, mul ti taski ng or mul ti programmi ng system, memory must be speci fi cal l y
managed to a handl e mul ti pl e programs. The physi cal si ze of the mai n memory i s usual l y not
l arge enough to accommodate the operati ng system and al l of the appl i cati on programs whi ch
are needed to execute the programs of vari ous users. I n a mul ti user system users shoul d not
i nterfere wi th one another, and al so they shoul d not i nterfere wi th the operati ng system. Thi s
i s achi eved by provi di ng sui tabl e memory management scheme. Memory management can be
provi ded total l y by the operati ng system or wi th the hel p of hardware cal l ed MMU (memory
management uni t).
I n a uni programmi ng system, the mai n memory i s parti ti oned i nto two porti ons: one
porti on for the operati ng system and the other porti on for the program currentl y bei ng
executed. I n a mul ti programmi ng system the users porti on of the memory must be further
subdi vi ded to accommodate mul ti pl e tasks. The task of subdi vi si on i s done dynami cal l y by the
memory management scheme. Modern MMUs provi de vi rtual memory to handl e l arge program
or a l arge number of programs. Thi s i s achi eved by usi ng swappi ng techni que.
Memory Devices. There are three types of memori es from technol ogy poi nt of vi ew:
semi conductor, magneti c and opti cal memory. Semi conductor memory i s stati c, faster, l i ghter,
smal l er i n si ze and consumes l ess power. I t i s used as mai n memory of a computer. Magneti c
memory i s sl ower but cheaper than semi conductor memory. I t i s used as secondary and back
up memory of a computer for mass storage of i nformati on. RAMs, ROMs, EPROMs, fl ash
memory etc. are semi conductor memori es, and hard di sks, fl oppy di sks and magneti c tapes
are magneti c memori es. Opti cal di sks and tapes are used as mass storage and back up
memor y.
Semiconductor Memory
Semi conductor memori es are of two types: RAM (random access memory) and ROM (read
onl y memory). RAM i s a read/wri te memory. I nformati on can be wri tten i nto and read from
a RAM. I t i s s vol ati l e memory. I t stores i nformati on so l ong as power suppl y i s on. When
power suppl y goes off or i nterrupted the stored i nformati on i n the RAM i s l ost. ROM i s a
permanent type memory. I ts contents are not l ost when power suppl y goes off. The user
cannot wri te i nto a ROM. I ts contents are deci ded by the manufacturer and wri tten at the
ti me of manufacture. RAMs up to 1 Gbi ts capaci ty are avai l abl e. ROMs store permanent
programs and other types of i nformati on whi ch are needed by the computer to execute users
programs.
Programmabl e ROMs are al so avai l abl e. They are cal l ed PROMs. Further, di fferent types
of PROMs such as erasabl e PROM cal l ed EPROM, el ectri cal l y erasabl e PROM cal l ed E
2
PROM are avai l abl e. User can wri te permanent i nformati on i n PROMs. Such i nformati on i s
requi red whi l e executi ng users programs. Fl ash memory whi ch i s el ectri cal l y erasabl e and
programmabl e, i s avai l abl e. I t i s si mi l ar to EEPROM, but has hi gher packi ng densi ty, l ower
cost and greater rel i abi l i ty.
Magnetic Memory
Magneti c memori es are nonvol ati l e memory. They store i nformati on permanentl y. They
are sl ower than semi conductor memory. The commonl y used magneti c memori es are of three
types: hard di sks, fl oppy di sks and tapes. These devi ces are bul k storage devi ces. They are
used to store i nformati on at a l ower cost compared to semi conductor devi ces. These are not
stati c devi ces. They are rotated whi l e readi ng or wri ti ng i nformati on.
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Floppy Disks. These are thi n ci rcul ar pl asti c di sks coated wi th magneti c materi al (i ron
oxi de or bari um ferri te) on the surface. They are used as backup memory. The capaci ty of
a 3.5 i nch fl oppy i s 1.44 MB. The use of fl oppy di sks i s di mi ni shi ng day by day. Now peopl e
prefer to use opti cal di sks. Fl oppy di sks are cheaper than opti cal di sks.
Hard Disks. Hard di sks are made of al umi ni um or other metal or metal al l oy whi ch
are coated on both si des wi th magneti c materi al usual l y i ron oxi de. Unl i ke fl oppy di sks,
hard di sks are not removabl e from the computer. To i ncrease the stori ng capaci ty several
di sks are packed together and mounted on a common dri ve to form a disk pack. A di sk
i s al so cal l ed platter. The di sks uni t packed i n a seal ed contai ner i s cal l ed Winchester di sk
dri ve. As the seal ed contai ners are dust-free, they al l ow very hi gh speed, usual l y 7200 rpm-
15,000 rpm. A hard di sk i s more stabl e as i t i s ri gi d and contai ned i n dust-free envi ronment.
I ts track and bi t densi ti es are much hi gher than those of fl oppy di sks. A hard di sk may have
more than 10,000 tracks per surface and bi t densi ty 15,000 bi ts per i nch of a track. The data
transfer rate i s 33.3-700 MB/sec. The average access ti me i s about 5-10 ms. The rel i abi l i ty
of data i s 1 i n 10
11
whi ch i s much better than that of fl oppy di sk, that i s 1 i n 10
8
10
10
. Hard
di sks come i n 2.5 i nch and 3.5 i nch di ameter. The stori ng capaci ty per di sk i s upto 133 GB.
The capaci ty of hard di sk dri ve uni t i s upto 600 GB. A hard di sk uni t contai ns more than
one pl atter.
Hard di sk control l ers are used to i nterface hard di sks to a processor. An exampl e of hard
di sk control l er i s I ntel 82064. There are two types of hard di sk control l ers: I DE (I ntegrated
Dri ve El ectroni cs) and SCSI (Smal l Computer System I nterface). SCSI are i ntel l i gent control l er
and they connect a number of I /O devi ces such as hard di sks, fl oppy di sks, tape dri ve, opti cal
di sks, pri nters, scanners etc. I t i s costl i er than I DE control l er. Actual l y, SCSI and I DE are not
control l ers; they are adapters. But peopl e cal l them control l ers. SATA (Seri al ATA I nterface)
i s now avai l abl e for hard di sk dri ves. I ts data transfer rate i s 3GB/s.
Magnetic Tape. Magneti c tape i s a mass storage devi ce. I t i s used as back up storage.
I t i s seri al access type storage devi ce. I ts mai n di sadvantage i s that i t stores i nformati on
sequenti al l y. I t i s made up of pl asti c materi al . Standard si zes are 1/2 i nch, 1/4 i nch, 8 mm
and 3 mm wi de. Earl i er, tapes used 9 tracks to store a byte wi th pari ty bi t. Today tapes use
18 or 36 tracks to store a word or doubl e word wi th pari ty bi ts. Newer tape i s packed i n
cassette form whi ch i s cal l ed cartri dge tape. The stori ng capaci ty i s 2 GB-800 GB of compressed
data. The data densi ty of 18-track tape i s about 40,000 characters per i nch.
Optical Memory. I nformati on i s wri tten to or read from an opti cal di sk or tape usi ng
l aser beam. Opti cal memory i s used as archi val and backup memory. Opti cal di sks are not
sui tabl e for secondary memory because thei r access ti me i s more than that of hard di sks.
Thei r advantage i s that they have very hi gh storage capaci ty. Types of opti cal memory are:
CD-ROM, CD-R (CD Recordabl e), CD-RW, DVD-ROM, DVD-R and DVD-RW. CD-ROM i s al so
cal l ed compact di sk ROM. I nformati on on CD-ROM i s wri tten at the ti me of manufacture. I t
i s a read-onl y type memory. Di sk si ze i s 5.25 i nch di ameter. 650MB CD-ROMs are avai l abl e.
Thei r access ti me i s 80 ms. Data transfer rate i s 4800KB/s. A typi cal val ue of track densi ty
i s 16000 tracks per i nch.
CD-R/W (Read/Wri te) of 700 MB capaci ty are now avai l abl e.
A DVD-ROM i s si mi l ar to CD-ROM. I t uses shorter wavel ength of l aser beam and hence,
stores much more data than CD-ROM. DVD-ROMs of capaci ty 4.7 GB to 50 GB are now
avai l abl e.
1.12 COMPUTER FUNDAMENTALS
1.3.3 Input Devices
I nfor mati on i s enter ed i nto a computer thr ough i nput devi ces. An i nput devi ce conver ts
i nput i nfor mati on i nto sui tabl e bi nar y for m acceptabl e to a computer. The commonl y used
i nput devi ce i s a keyboar d. Sever al i nput devi ces whi ch do not r equi r e typi ng of i nput
i nfor mati on have been devel oped, for exampl e, mouse, joysti ck, l i ght pen, gr aphi c tabl et,
touch scr een and tr ackbal l s. Each of these al l ows user s to sel ect one of the i tems or
i mages di spl ayed on the scr een. Ther efor e, these devi ces ar e cal l ed pointing devices. The
r equi r ed i nput i s fed to the computer when contr ol button i s pr essed. I n i ndustr i al contr ol
el ectr i cal si gnal s r epr esenti ng physi cal or el ectr i cal quanti ti es such as temper atur e,
pr essur e, for ce, cur r ent, vol tage, fr equency, etc. ar e enter ed a computer for thei r
measur ement and contr ol . The sensor s, tr ansducer s and data acqui si ti on system act as
i nput devi ces. Nowadays voi ce i nput systems have al so been devel oped. A mi cr ophone i s
used as an i nput devi ce. I n many appl i cati ons, computer s wi th vi si on ar e r equi r ed, for
exampl e, r obots, computer -based secur i ty system, etc. The i nput systems for thi s type of
computer s use opti cal system, semi conductor devi ces sensi ti ve to l i ght, devi ces based on
ul tr asoni c waves, etc. Such i nput devi ces pr oduce di gi tal si gnal s cor r espondi ng to i mages,
pi ctur es etc. A mul ti medi a computer accepts i nput i n the for m of text, i mages, gr aphi cs
and voi ce.
1.3.4 Output Devices
The output devi ces recei ve resul ts and other i nformati on from the computer and provi de
them to users. The computer sends i nformati on to an output devi ce i n the bi nary form. An
output devi ce converts i t i nto a sui tabl e form conveni ent to users such as pri nted form,
di spl ay on a screen, voi ce output, etc. I n some appl i cati ons the computers output may al so
be converted by an output uni t i n the form whi ch can be used as an i nput to other devi ces,
equi pment, machi nes, etc. Thi s i s parti cul arl y true i n i ndustri al appl i cati ons. The commonl y
used output devi ces are CRT screen and pri nters. Other output devi ces are LEDs (l i ght
emi tti ng di odes), LCDs (l i qui d crystal di spl ays), pl asma di spl ays, pl otters, mi crofi l m, mi crofi che,
speaker or tel ephone system, etc.
The di spl ay screen i s al so cal l ed moni tor or CRT (Cathode Ray Tube) di spl ay. Two types
of di spl ay uni ts are avai l abl e: monochrome and col our moni tor. Monochrome moni tor di spl ays
texts i n a si ngl e col our: bl ue, whi te, yel l ow or amber. A col our moni tor di spl ays text or
graphi cs i n mul ti col our. I t may be desi red i n art/graphi cs appl i cati ons. For graphi cs di spl ay,
screens of hi gher resol uti ons are requi red. To provi de hi gher resol uti on, screens contai n
more number of pi xel s to di spl ay text or i mages.
1.3.5 Buses
Memory and I /O devi ces are connected to the CPU through a group of l i nes cal l ed a
bus. These l i nes are meant to carry i nformati on. There are three types of buses: address
bus, data bus and control bus. An address bus carri es the address of a memory l ocati on or
an I /O devi ce that the CPU wants to access. The address bus i s uni di recti onal . The data
and control buses are bi di recti onal because the data can fl ow i n ei ther di recti on; from CPU
to memory, (or I /O devi ce) or from memory (or I /O devi ce) to the CPU. Exampl es of control
si gnal s are:
RD, WR,
ALE, etc. Fi g. 1.4 shows the schemati c di agram of I /O or memory
connecti on to CPU.
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Fig. 1.4 I /O or Memory Connecti on to CPU.
Di fferent types of bus archi tectures such as I SA, PCI , AGP, USB etc. have been descri bed
i n Chapter 10.
1.4 MEMORY ADDRESSING CAPABILITY OF A CPU
The memory addressi ng capabi l i ty of a CPU depends on the number of l i nes avai l abl e
i n an address bus, that i s, wi dth of the address bus. Wi th n-bi t wi de address bus a CPU can
di rectl y address up to 2
n
memory l ocati ons. For exampl e, a CPU wi th 20 bi t wi de address bus
wi l l address 2
20
memory l ocati ons di rectl y. 2
20
= 1 mi l l i on. One memory l ocati on stores one
byte of i nformati on and hence a CPU wi th 20-bi t address bus wi l l di rectl y address up to 1 MB
memory, wi th 16-bi t address bus 64 KB memory, wi th 24-bi t address bus 16 MB memory and
wi th 32-bi t address bus 4 GB memory.
I t can be very easi l y shown that wi th n address l i nes, 2
n
memory l ocati ons can be
addressed. Fi rst take a si mpl e case of onl y 2 l i nes. A l i ne carri es ei ther 0 or 1 bi nary di gi t.
Usi ng two l i nes onl y, possi bl e memory addresses are: 00, 01, 10 and 11. These are 2
2
= 4. I f
there are 3 l i nes, the possi bl e addresses wi l l be 000,001, 010, 011, ..... 111 whi ch are 2
3
= 8.
Si mi l arl y, wi th four address l i nes possi bl e addresses are: 0000, 0001, 0010, 0011, 0100, ....,
1111 whi ch come out to be 2
4
= 16. Si mi l arl y, wi th n address l i nes up to 2
n
memory l ocati ons
can be addressed.
1.5 WORD LENGTH OF A COMPUTER
A di gi tal computer oper ates on bi nar y di gi ts, 0 and 1. I t can under stand i nfor mati on
onl y i n ter ms of 0s and 1s. As al r eady menti oned a bi nar y di gi t i s cal l ed a bit. The wor d
bi t i s the shor t for m of binary digit. A gr oup of 8 bi ts i s cal l ed a byte. The number of bi ts
that a computer can pr ocess at a ti me i n par al l el i s cal l ed i ts word length. The commonl y
used wor d l engths ar e: 8, 16, 32 or 64 bi ts. I t i s a measur e of the computi ng power of a
computer. Computer wi th l onger wor d l ength ar e mor e power ful . When we tal k of a
32-bi t computer, i t means that i ts wor d l ength i s 32 bi ts. Si mi l ar l y when we say 8-bi t,
16-bi t or 32-bi t mi cr opr ocessor, 8-bi t, 16-bi t or 32-bi t i ndi cates the wor d l ength of the
mi cr opr ocessor.
1.14 COMPUTER FUNDAMENTALS
1.6 PROCESSING SPEED OF A MICROPROCESSOR
The processi ng speed of a mi croprocessor i s usual l y measured i n mi l l i ons of i nstructi ons
per second. I n short i t i s wri tten as MIPS. I n computer l i terature term throughput i s al so
used for the number of i nstructi ons executed per second. The MI PS rati ng i s used to speci fy
the i nteger computati on performance of a processor. The processi ng speed of a mi croprocessor
for fl oati ng-poi nt computati on i s measured i n mi l l i ons of fl oati ng-poi nt i nstructi ons per second,
MFLOPS. As the i nstructi ons di ffer from mi croprocessor to mi croprocessor for a hi gh-l evel
l anguage program, the MI PS rati ng does not gi ve correct i dea of processi ng speed of a
mi croprocessor. I f the same program runs on a RI SC as wel l as on a CI SC processor, the
MI PS rati ng of the RI SC processor wi l l be hi gher because the i nstructi ons of a RI SC processor
are si mpl er than those of a CI SC processor.
Further, to compare processors wi th di fferent cl ock cycl es and di fferent i nstructi on sets i s
not total l y correct. Today SPEC rati ngs are wi del y used to speci fy processors performance. SPEC
i s the abbrevi ati on of System Performance Eval uati on Commi ttee. Thi s commi ttee was formed
i n 1989 to devel op i ndustry-standard benchmark to eval uate processors rati ng. SPEC rati ngs are
gi ven i n SPECi nt95 to measure i nteger performance, and SPECfp95 to measure fl oati ng-poi nt
performance. The i nt stands for i nteger, fp for fl oati ng-poi nt, 95 i s the year i n whi ch thi s standard
was devel oped. SPECi nt95 i s wri tten i n C l anguage, and SPECfp95 i n FORTRAN.
Some other ratings are as follows
TPS (Transactions Per Second). I t i s used for on-l i ne processi ng appl i cati on of a
computer. On-l i ne appl i cati ons demand rapi d i nteracti ve processi ng for l arge number of rel ati ve
si mpl e transacti ons. Each transacti on may i nvol ve a database search, query, answeri ng, and
database update operati ons. They are supported by very l arge databases. Exampl es are:
rai l ways reservati ons, ai rl i nes reservati ons, automated tel l er machi nes, etc.
KLIPS. For a knowl edge-based computer, performance can be measured i n ki l o l ogi cal
i nferences per second (KLI PS).
iCOMP. I t i s I ntel s Comparati ve Mi rcroprocessor Performance. I t consi sts of a col l ecti on
of benchmarks to eval uate an i ndex of rel ati ve performance of I ntel mi croprocessors.
LINPACK Rating. I t uses FORTRAN programs for sol vi ng l i near system of equati ons
of the order of 100 and hi gher. I ts programs contai n hi gh percentage of fl oati ng-poi nt operati ons.
I t i s very sensi ti ve to vector operati on and the degree of vectori zati on by the computer.
Hence, i t i s gi ven wi th speci fi c compi l er and degree of l i near equati ons. I t i s measured i n
MFLOPS or GFLOPS.
Dhyrstone. I t i s syntheti c testi ng benchmark. I t gi ves i nteger performance. I ts uni t i s
Kdhrystone per second. I ts di sadvantage i s that i t i s sensi ti ve to compi l ers.
Whetstone. I t i s a FORTRAN based syntheti c testi ng benchmark. I t measures both
i nteger and fl oati ng-poi nt performance. I ts programs take i nto account array i ndexi ng,
subrouti ne cal l s, parameter passi ng, condi ti onal branchi ng, and tri gonometri c/transcendental
functi ons. I ts uni t i s KWhetstone per second. I t i s sensi ti ve to compi l ers. Whetstone tests do
not perform I /O or system cal l s.
1.7 MICROPROCESSORS
Wi th the advances i n LSI and VLSI technol ogy i t became possi bl e to bui l d the whol e
CPU of a di gi tal computer on a si ngl e I C. A CPU bui l t on a si ngl e LSI , VLSI or ULSI chi p
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i s cal l ed a microprocessor. I t i s the l atest devel opment i n the fi el d of computer technol ogy as
wel l as semi conductor technol ogy. A di gi tal computer has a mi croprocessor as i ts CPU. A
mi cr opr ocessor combi ned wi th memor y, an i nput devi ce and an output devi ce for ms a
mi crocomputer. The CPU of a l arge computer contai ns a number of mi croprocessors. Each
mi croprocessor performs a speci fi ed task wi thi n the CPU. The mi croprocessors i n the CPU
of a l arge computer operate i n paral l el .
Table 1.1 Important Intel Microprocessors
Micropro- Year of Word Memory Pins Clock Remarks
cessor I ntro- Length Addressing
duction Capacity
4004 1971 4-bit 1 KB 16 750KHz Fi rst mi croprocessor
8085 1976 8-bit 64KB 40 3-6MHz Popul ar 8-bi t mi cro-
processor
8086 1978 16-bit 1 MB 40 5-10MHz
8088 1980 16-bit 1 MB 40 5-8 MHz Data bus 8-bi t, I nternal
archi tecture 16-bi t,
wi del y used i n PC XT.
80286 1982 16-bit 16MB real , 68 6-12.5MHz Wi del y used i n PC/AT
4GB Vi rtual
80386 1985 32-bit 4GB real , 100 20MHz Popul ar 32-bi t Mi cro-
64 TB Vi rtual processor
80486 1989 32-bit 4GB real , 168 25-100MHz I mproved 32-bit processor,
64TB (1717) contai ns FPU and cache
Virtual on the chi p.
Penti um 1993 32-bit 4GB real 237PGA 233MHz Contai ns 2 ALUs, data
bus 64-bi t, address
bus 32-bi t.
Penti um 1995 32-bit 64GB real 387 pi n 150-200MHz Data fl ow archi tecture,
Pro PGA contai ns 2nd-l evel cache,
operates at 3.3V.
Penti um I I 32-bit 64GB real 450MHz Penti um Pro wi th MMX
technol ogy
Cel eron 1998 32-bit 2.6MHz Cheaper 32-bi t processor,
based on Penti um Pr o
cor e.
Penti um I I I 1999 32-bi t 64GB real 370PGA 500-1000MHz penti um I I + 70 mul ti -
medi a i nstructi ons.
Penti um 4 2000 32-bit 64 GB 423PGA 1.3-3.2 GHZ
Penti um 4EE
and Penti um 2004 64-bit 3-3.7 GHZ
6XX seri es
I tanium 2001 64-bit 423PGA EPI C Processor
1.16 COMPUTER FUNDAMENTALS
Nowadays mi croprocessors al so perform tasks other than those of a CPU. A number of
mi croprocessors are al so used to control i nput and output devi ces of a l arge computer. For
exampl e, a mi croprocessor i s used to control the operati on of a keyboard and CRT di spl ay
uni t. I t i s used to control the operati on of a pri nter and so on.
The fi rst mi croprocessor, I ntel 4004, a 4-bi t mi croprocessor, was i ntroduced i n 1971 by
I ntel Corporati on. I n 1972 I ntel i ntroduced the fi rst 8-bi t mi croprocessor, I ntel 8008. These
mi croprocessors used PMOS technol ogy. A more powerful and faster mi croprocessor, the I ntel
8080, usi ng NMOS technol ogy was i ntroduced i n 1973. The 8-bi t mi croprocessors were
i ntroduced by a number of compani es; exampl es are: Motorol as MC 6809, Zi l ogs Z80 and
Z800, MOS Technol ogys 6500 seri es, Nati onal Semi conductors NSC 800 etc. The l atest 8-bi t
mi croprocessor of I ntel i s 8085 i ntroduced i n 1976. I t i s very popul ar and wi del y used. The
fi rst I ndi an 8-bi t mi croprocessor was SCL 6502, manufactured by Semi conductor Compl ex
Ltd. 8-bi t mi croprocessors were soon fol l owed by 16-bi t mi croprocessors. Exampl es of 16-bi t
mi croprocessors are: I ntel 8086, 80186 and 80286; Motorol as 68000, 68010, 68012; Texas
I nstruments TMS 9900, Fai rchi l d 9440, Di gi tal Equi pments LSI 11 and so on. I n the 1980s,
32-bi t mi croprocessors were i ntroduced, and they are sti l l wi del y used. Exampl es of 32 bi t
mi croprocessors are I ntel 80386, 80486, Penti um, Penti um Pro, Penti um I I . Penti um I I I ,
Cel eron and Penti um 4.
Penti um Pro, Penti um I I , Penti um I I I and Penti um 4 use data fl ow archi tecture. Earl i er,
I ntel s 4004 to Pentium were Von Neumann type processors. Penti um I I I i s an i mproved
versi on of Penti um I I . I t i ncl udes MMX pi pel i ne to provi de MMX features. Furthermore, i t
contai ns I nternet Streami ng SI MD i nstructi ons to enhance mul ti medi a performance on the
I nternet such as streami ng audi o and vi deo, ani mati on, 3-D si mul ati on, advanced i magi ng,
speech recogni ti on etc. Cel eron processor i s a l ow-cost 32-bi t processor. I t i ncl udes MMX
features and I nternet streami ng SI MD i nstructi ons. Penti um 4 i s an i mproved versi on of
Penti um I I I . I t contai ns more I nternet Streami ng SI MD i nstructi ons and i t i s faster than
Penti um I I I . Penti um M i s l ow-cost processor for notebook computers. 32-bi t processors of
other compani es are: Motorol as 68020, 68030, 68040 and 68060, Power PC 601, 603, 604, 740
and 750, Nati onal Semi conductors NS 32032, NS 32332 NS32C532 and M300, AMDs K5, K6
and Athl on (K7), Cyri x 586 and 686 etc.
Penti um 4 EE (Extreme Edi ti on) and Penti um 4 6XX seri es are 64-bi t processors. Penti um
4 EE 840 i s a dual core processor sui tabl e for servers. I tani um i s a 64-bi t processor of I ntel
Corporati on. 64-bi t processors of other compani es are: AMDs Athl on 64, Athl on 64 FX seri es,
Opti ron, Athl on 64X2; PowerPC 620, PowerPC G4, I BMs G5, SUNs Ul tra SPARC I I I , Compaqs
Al pha 21264, MI PS 12000; C-DACs Param 10,000 and Param Padma, HPs PA 8500 seri es etc.
AMDs Opti ron and Athl on 64X2 are dual core processors.
Table 1.2 Important Microprocessors of Companies other than Intel
Micropr- Make Year of Word length Clock Number of Remarks
ocessor I ntroduc- Transistors
tion
6809 Motorol a 1979 8-bit 4-8 MHz Popul ar 8-bi t mi cr o-
processor
68000 Motorol a 1979 32-bi t i nter- 10-25 MHz 70,000 Popular
nal archi tect- and wi del y used
ure, 16-bi t
data bus
(Contd.)...
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68040 Motorol a 1989 32-bit 20-33 MHz 1.2 mi l l i on Contai ns FPU, MMU,
on-chi p data cache and
i nstructi on cache
Power PC Motorol a, 1993 32-bit 120 MHz 2.8 mi l l i on RI SC processor
601 I BM and
Apple
Power PC Motorol a, 1997 32-bit 400 MHz Sui tabl e for notebooks,
750 I BM and mobi l e and desktop
Apple
K6-3, AMD 1999 32-bit 500 MHz Contai ns 2nd l evel and
Athl on 3rd l evel cache. K7 i s
cal l ed Athl on
586, 686 Cyrix 32-bit 233 MHz 6X86MX outperforms
and Penti um I I
6X86MX
Power PC Motorol a, 64-bit 250 MHz 710
6
Sui tabl e for
620 I BM and workstati on
Apple
Alpha DEC 64-bit 700 MHz- 9.310
6
RI SC processor.
21164, Compaq 1000MHz (21164)
21264 for 21264
ULTRA- SUN 64-bit 200 MHz 3.810
6
RI SC processor
SPARC
MIPS MIPS 1999 64-bit 300 MHz 6.410
6
RI SC processor.
10,000, (MI PS Sui tabl e for work-
12000 10000) stations.
PA 8500 H.P. 1999 64-bit 440 MHz
68060 Motorol a 1995 32-bit Sui tabl e for embedded
application
Athl on 0.13 mi cron
64, Athl on AMD 2003 64-bit 2.66 GHZ process technol ogy
64 FX
Opti ron, Dual -core
Athl on AMD 2005 64-bit 2.4 GHZ processors
64X2
1.8 SINGLE-CHIP MICROCOMPUTERS (MICROCONTROLLERS)
Wi th the devel opment of VLSI technol ogy i t became possi bl e to fabri cate a di gi tal computer
on a si ngl e I C chi p. A di gi tal computer fabri cated on a si ngl e I C chi p i s cal l ed single-chip
microcomputer. Si nce i t i s wi del y used for contr ol appl i cati on, i t i s al so cal l ed
microcontroller. I t i s very smal l and compact. I t forms the part of the devi ce or equi pment
whi ch i s to be control l ed. I t i s used for i ndustri al control , process control , consumer and
appl i ances control , i nstrumentati on, etc. I t contai ns a CPU, memory (RAM, and ROM/EPROM/
Fl ash memory) and I /O l i nes. A powerful mi crocontrol l er may contai n some other components
1.18 COMPUTER FUNDAMENTALS
whi ch are needed for control appl i cati ons such as anal og-to-di gi tal converter, di gi tal -to-anal og
converter, i nterrupt control l er, DMA control l er, wave generator, etc.
I ntel devel oped 8-bi t mi crocontrol l ers 8048 seri es, i n 1976. I n 1980 i mproved 8-bi t
mi crocontrol l ers 8051 seri es was devel oped . 8-bi t mi crocontrol l ers are used for si mpl e and
l ow-cost control appl i cati ons. I n 1983, I ntel devel oped 16-bi t mi crocontrol l ers, 8096 seri es.
Later on, i t devel oped 80196 seri es of 16-bi t mi crocontrol l ers. These were more powerful and
were used i n sophi sti cated i ndustri al control , i ntel l i gent computer peri pheral s, i nstrumentati on,
etc.
Other manufacturers al so devel oped 4-bi t, 8-bi t, 16-bi t and 32-bi t mi crocontrol l ers. Motorol a
devel oped 32-bi t mi crocontrol l ers, MPC-505. I BM devel oped 32-bi t mi crocontrol l ers, 403GA. 32-
bi t mi crocontrol l ers are used for compl ex control appl i cati ons. See more detai l i n Chapter 7.
1.9 COMPUTER CLASSIFICATION
Modern computers are cl assi fi ed as fol l ows:
(i) Pal mtop computers, al so known as pal m PCs or PDA (Personal Di gi tal Assi stant).
(ii) Notebook computers, al so known as l aptop computers. Some trade names of notebook
computers are: I BMs Thi nkpad 570, Compaqs Armada -E700, M700, M300 seri es,
H.P.s Omni book, Si emens Sceni c mobi l e 750 AGB (hi gh-end mul ti medi a notebook),
Apples ibook, etc.
(iii) Desktop Computers
(iv) Workstati ons
(v) Servers
(vi) Super Computers
Palmtop or Handheld Computers. These are the smal l est computers avai l abl e. They
can be hel d i n pal m and hence, they are cal l ed pal mtop computers. They can easi l y be kept
i n a shi rt pocket. They are used for tracki ng appoi ntments, mai ntai ni ng l i sts, jotti ng notes,
etc. They use ti ny keyboard and have smal l di sk memory. They can be connected to wi rel ess
network. Some pal mtops use touch screen. Pal mtops al so accept handwri tten i nputs usi ng an
el ectroni c pen whi ch can be used to wri te on the pal mtop screen. The system has to be
trai ned on the users handwri ti ng before i t can be used. A pal mtop can be used as a mobi l e
phone, fax and E-mai l . Some pal mtops use a propri etary operati ng system, but i t can swap
data wi th a WI NDOWS PC. Some pal mtops use Mi crosofts WI NDOWS-CE operati ng system.
WI NDOWS-CE i s a stri pped-down versi on of Mi crosoft WI NDOWS. I t i s desi gned to provi de
a WI NDOWS i nterface for pal m PCs, some other types of very smal l computers, and tool s
and appl i ances other than PCs.
Notebook PCs or Notebook Computers (Laptop Computers). These are portabl e
computers. They contai n 32-bi t CPU, hard di sks, fl oppy di sks, CD-ROM dri ve, modem and fl at
LCD screen. Col our di spl ays are avai l abl e. They consume l ess power and use batteri es for
thei r operati on. They are used for word processi ng and spreadsheet computi ng whi l e a person
i s travel l i ng. They can be connected to computer network. Wi rel ess connecti on can be pro-
vi ded to l aptop computers so that they can get i nformati on from l arge stati onary computers.
They general l y use WI NDOWS-XP operati ng system. Notebook PC wi th LI NUX operati ng
system has al so been devel oped. Hard di sk capaci ty up to 60 GB, RAM capaci ty up to 256 MB,
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etc. are avai l abl e on a notebook. Mul ti medi a system i s now avai l abl e. Some notebook com-
puters are provi ded wi th fi nger recogni ti on system.
Centrino Notebooks. The notebooks whi ch are manufactured usi ng I ntel s Penti um M
processor, I ntel s mobi l e chi pset (the 855 GME or 915 M) and I ntel PROSet wi rel ess LAN
card, are sai d to have Centrino technology.
Centrino Duo Mobile Technology (NAPA)
I ntel I ndi a has l aunched Centri no Duo Mobi l e technol ogy i n January, 2006. I ts code
name i s NAPA. Centri no Duo i s the next generati on of mobi l e computi ng pl atform. I t consi sts
of the fol l owi ng three parts:
(i) Intel Core Duo Processor Called Yonah. I t uses 65 nm (nanometer) process
technol ogy. I t i s a dual core processor desi gned for mobi l e computers. I t has on-di e
32 KB i nstructi on cache and 32 KB data cache. A 2 MB L2 cache i s shared by two
cores usi ng the I ntel Smart Cache technol ogy whi ch al l ows dynami c al l ocati on of
cache to the cores dependi ng on processi ng l oad on the cores.
(ii) Mobile Intel 945 Express chipset family. I t gi ves dual channel DDR2 667 support.
Thi s chi pset has two vari ants-945 GM and 945 PM. The 945 PM i s pure performance
chi pset whi ch consumes l ess power. The 945 GM offers I ntel Medi a Accel erator 950
to del i ver i mproved graphi cs performance.
(iii) Intel PRO/Wireless 3945ABG Network Connection. I t i s a smarter, smal l er
and sl eeker wi rel ess sol uti on. I t i s compati bl e wi th the l atest 802.11e standard.
Desktop Computers. These computers are si ngl e-user personal computers (PCs) and
can be pl aced on a desk and hence, they are cal l ed desktop computers. They use 32-bi t
processors such as Penti um 4, Cel eron, Athl on-XP etc. The hard di sk capaci ty of 80GB and
RAM capaci ty of 512 MB are used. Opti cal di sks and 3.5 i nch fl oppy di sks are used as backup
memory. Operati ng system used are: WI NDOWS-XP, WI NDOWS-NT, LI NUX, Mac OS-X etc.
Some desktop computers use fi ngerpri nt recogni ti on system to provi de better securi ty. Such
a system fal l s under Bi ometry. For fi nger recogni ti on, the user has to sl i de hi s fi ngers
across a scanner, whi ch senses the patterns caused by the ri dges and furrows on the fi ngerti p.
Workstation. Workstati ons are more powerful computers than desktop computers. They
are sui tabl e for numeri c and graphi c i ntensi ve appl i cati ons. They are used i n sci enti fi c and
engi neeri ng appl i cati ons such as computer ai ded desi gn (CAD), si mul ati on etc., whi ch requi re
greater processi ng power, l arger storage capaci ty and better graphi cs capabi l i ty. They have
l onger col our vi deo di spl ay uni t (moni tor of 19 i nch or more). They have hard di sk and RAM
capaci ty more than those of a desktop computer. The RAM capaci ty may be of a few GB and
hard di sk capaci ty of a few hundred GB. They use RI SC processors such as SUNs Ul traSPARC
I I I , HPs PA-8500 or 8800, Compaqs Al pha 21264, MI PS 12000, etc. Operati ng systems used
are mul ti user such as UNI X, SUNs Sol ari s, HPs HP-UX etc.
Servers. These are powerful computers. A number of PCs and termi nal s can be connected
to a server. Servers are provi ded wi th l arge di sk and RAM capaci ty. I n a l ow-end server onl y
one mi croprocessor i s used to act as a CPU. On the other hand i n a hi gh-end server, a
number of mi croprocessors are provi ded i n the CPU. Mi croprocessors i n a mul ti processor
CPU operate i n paral l el . The user worki ng on a PC connected to a server, makes si mpl e
computati on on hi s own PC, but for more compl ex computati on he can connect hi s PC to the
server through the LAN, WAN or I nternet. He can uti l i ze computi ng power, al l faci l i ti es and
database avai l abl e wi th the server. He can al so avai l the faci l i ti es avai l abl e at other PCs
1.20 COMPUTER FUNDAMENTALS
connected to the server. The computer connected to the server through a network i s cal l ed
client. The aforesai d type of computi ng i s known as cl i ent-server computi ng. Recentl y mul ti core
64-bi t processors have been devel oped by many compani es. These are qui te sui tabl e for server
computers. Servers use mul ti user operati ng systems such as UNI X, LI NUX, HP-UX, SUNs
Sol ari s etc.
Super Computers. These are the most powerful computers. They are used for very
compl ex computati on work. They use vector processors. I ntensi ve paral l el i sm i s used i n
supercomputers. A number of RI SC mi croprocessors are used i n the CPU of a supercomputer.
Supercomputers are used for weather forecasti ng, i n aerodynami cs, sei smol ogy; atomi c, pl asma
and nucl ear anal ysi s; for weapons research and devel opment, sendi ng rockets i nto space, etc.
I n some appl i cati ons i n aerodynami cs and nucl ear physi cs, as many as 10
13
ari thmeti c
operati ons are needed for a si ngl e probl em. Thi s may take a number of hours of computi ng
ti me on a supercomputer. Hence, there i s a constant demand to i ncrease the power of a
supercomputer. Exampl es of supercomputers are: Cray-1 (1976), Cray 2 (1985), Cray T3D
(1993), NECs SX-S/44 (1991), Fuji tsu VP 2600/10 (1991), Hi tachi 820/80 (1987), C-DACs PARAM
seri es of supercomputers etc. Current worl ds top supercomputers are: Bl ueGene/L DD2 Beta-
system of I BM whi ch has a speed of 70.7 TFLOPS and uses 400 PowerPC processors; Col umbi a
(NASA) whi ch has a speed of 51.9 TFLOPS and uses 10,240 I tani um 2 processors; Earth
Si mul ator (NEC) wi th a speed of 40 TFLOS and uses 5120 NEC CPUs; etc. C-DACs PARAM
10,000 uses 160 Ul traSPARC I I I processors. I ts computi ng power i s 100 GFLOPS. I t has open
fr ame ar chi tectur e and can scal e upto TFLOPS l evel . I t uses C-DACs own desi gned
communi cati on processor and network. C-DACs PARAM Padma supercomputer has a peek
computi ng power of 1 TFLOPS and 5 terabytes of storage. I t i s powered by 248 I BMs Power
4 RI SC processors of 1 GHZ cl ock frequency. I t runs AI X 5.1L operati ng system. I ts pri mary
i nterconnect i s ParamNet-I I , 2.5 GFLOPS, ful l dupl ex wi th backup gi gabyte Ethernet network.
I ts paral l el programmi ng i s done through C-DAC HPCC software. I t ranked 171 i n June 2003
l i st of top 500 supercomputers i n the worl d. Other I ndi an supercomputers are: C-Dots (Center
for Devel opment of Tel emeti cs) Chi p-152, Nati onal Aeronauti cal Laboratorys Mark-3, Bhabha
Atomi c Research Centres (BARC) Anupam; PACE seri es of supercomputers of Defence Research
and Devel opment Organi zati on (DRDO), Hyderabad, etc.
Earlier Classification. Ear l i er, computer s wer e cl assi fi ed as mi cr ocomputer s,
mi ni computers, mai nframe (or l arge) computers and supercomputers. Thi s cl assi fi cati on i s no
l onger used. Mi crocomputers are l ow-cost smal l computers. They i ncl ude portabl e computers,
per sonal computer s i .e., PCs (si ngl e-user desktop computer s), computer s for dedi cated
appl i cati ons l i ke i ndustri al control , i nstrumentati on, appl i ance control etc. Mi ni computers are
more powerful mul ti user computers. They contai n more RAM and hard di sk capaci ty compared
to mi crocomputers. Hi gh-end mi ni computers contai n more than one mi croprocessor i n thei r
CPU. Large or mai nframe computers are more powerful than mi ni computers. They use very
l arge capaci ty of RAM and hard di sk. They use UNI X and other mul ti user operati ng system.
Exampl es of mai nframe computers are: I BMs ES-9000, DECs VAX-9000, CDC Cyber-2000 V,
etc. Supercomputers have al ready been descri bed i n new cl assi fi cati on.
1.9.1 Computer Pen
I t i s a computer housed wi thi n a pen. I t can functi on as a di ary, al arm, notetaker and
can recei ve E-mai l and pager messages. Unl i ke a conventi onal handhel d computer, i t has no
keyboard. I t does not need a screen to work. I t saves i n i ts memory what user i s wri ti ng.
I t l i nks to a pri nter, mobi l e phone, modem or PC al l owi ng handwri tten notes to be transmi tted.
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I t has been devel oped by BI , a research l aboratory i n U.K. The prototype i s cal l ed SmartQui l l .
I t has abi l i ty to record handwri ti ng not onl y on paper but al so on any fl at surface-hori zontal
or verti cal . A ti ny l i ght at the ti p al l ows wri ti ng i n dark. SmartQui l l can even transl ate
i nvi si bl e wri ti ng i n the ai r.
1.10 USER INTERFACE
User i nterface provi des communi cati on means between an user and the computer. There
are two types of user i nterface : text/typi ng type and i con/mouse type. I n text/typi ng type user
i nterface, the user has to type commands usi ng a keyboard. I n DOS operati ng system the
user has to type commands. I t provi des text/typi ng type user i nterface. I n i con (smal l graphi cal
symbol ) type user i nterface, the user tel l s the computer to carry out certai n commands by
poi nti ng to an i con. Such user i nterface i s al so cal l ed GUI (Graphi cal User I nterface). A
poi nti ng devi ce such as mouse can be used to poi nt to an i con. Such system al so provi des a
l i st of avai l abl e commands cal l ed a menu. The user can poi nt to a command i n the menu.
Today GUI i s commonl y used by most of the operati ng systems.
1.11 HARDWARE, SOFTWARE, FIRMWARE, MIDDLEWARE AND FREEWARE
The physi cal components of a computer are cal l ed hardware. A physi cal component may
be el ectr oni c, el ectr i cal , magneti c, mechani cal or opti cal . Exampl es of har dwar e ar e
mi croprocessors and other I Cs, hard di sks, fl oppy di sks, opti cal di sks, cathode ray tube (CRT),
keyboard, pri nter, pl otter, etc.
A sequence of i nstructi ons gi ven to a computer to perform a parti cul ar task i s cal l ed a
program. A set of programs wri tten for a computer i s cal l ed software. The software requi red
to execute users program i s known as system software. The term software i ncl udes both
system softwar e and user s pr ogr ams. The system softwar e i ncl udes oper ati ng system,
assembl er, compi l er, i nterpreter, debuggi ng programs, text edi tors, etc. The operating system
i s a col l ecti on of programs whi ch control s the overal l operati on of a computer. The programs
stored i n ROMs, PROMs, EPROMs or Fl ash memory are cal l ed firmware. Nowadays a l arge
vari ety of prewri tten programs are avai l abl e to sol ve speci fi c tasks. Users need not prepare
programs for such tasks. They shoul d si mpl y know how to use such prewri tten programs.
Prewri tten programs for speci fi c tasks are cal l ed application programs or application packages.
I mportant appl i cati on packages avai l abl e are WordStar and MS-Word for text mani pul ati on,
LOTUS 1-2-3 and MS-Excel for preparati on of spreadsheet; MS-ACCESS, ORACLE, UNI FY
and FOXBASE for handl i ng database, etc. MS-Offi ce i s an i ntegrated package. I t i ncl udes a
word processi ng package-Word, a spreadsheet package-Excel , a database management package-
Access, a presentati on package-PowerPoi nt, and a Schedul i ng and Organi zati on package-
Outl ook. Software package for desi gni ng bui l di ngs, structures, power systems, i nventory
control , accounti ng, deal i ng wi th projects, etc. are avai l abl e.
Middleware. I t i s software that operates at the l evel between an appl i cati on program
and a networ k. I t can medi ate the i nter acti on between separ ate appl i cati ons acr oss
heterogeneous computi ng pl atforms on a network.
Some software are avai l abl e free of cost. They can be downl oaded form I nternet. Such
software are cal l ed freeware.
1.22 COMPUTER FUNDAMENTALS
1.11.1 Operating System
An operati ng system i s a col l ecti on of programs whi ch control s the overal l operati on of
a computer. I t manages fi l es on a di sk. I t permi ts users to create, pri nt, copy, del ete, read,
wri te to fi l es. I t formats di sks and control s i nput and output devi ces. I t executes programs,
al l ocates memory space to users, schedul es jobs, provi des user i nterface to computers, prevents
i nterference between users i n a mul ti user system, i t processes users commands, and so on
and so forth.
Several operati ng systems have been devel oped over the years. Some i mportant operati ng
systems whi ch are for si ngl e-user systems are: MS-DOS, OS/2, WI NDOWS-98, WI NDOWS-
XP etc. At present WI NDOWS-XP i s commonl y used. Operati ng systems for mul ti user system
are: UNI X, LI NUX, Novel l Netware, SUNs Sol ari s, WI NDOWS-2003, Mac OS X(ten), etc.
1.11.2 Programming Languages
A computer understands i nformati on composed of onl y zeros and ones. A program wri tten
i n terms of 0s and 1s i s cal l ed a machine language program. Computer i nstructi ons are
wri tten i n bi nary codes. A machi ne l anguage uses onl y bi nary codes. The wri ti ng of programs
i n machi ne l anguage i s a very di ffi cul t, ti resome and very bori ng job. Moreover, i t i s errorprone.
To overcome thi s di ffi cul ty a program can be wri tten i n al phanumeri c symbol s i nstead of 0s
and 1s. Meani ngful symbol s cal l ed mnemonics are used for thi s purpose. For exampl e, ADD
i s used for addi ti on, SUB for subtracti on, CMP for compari son, etc. A l anguage whi ch uses
mnemoni cs i s cal l ed an assembly language. A program wri tten i n an assembl y l anguage i s
cal l ed an assembl y l anguage program.
An instruction i s a command gi ven to a computer to perform speci fi ed task. The i nstructi on
set of a processor i s the col l ecti on of i nstructi ons that the processor i s desi gned to execute.
I n assembl y l anguage a mnemoni c i s an i nstructi on. I nstructi ons are cl assi fi ed i nto groups
l i ke data transfer, ari thmeti c, l ogi cal , branch control , and I /O and machi ne control i nstructi ons..
Data transfer group i ncl udes i nstructi ons for transferri ng data from regi ster to regi ster,
regi ster to memory and memory to regi ster. I nstructi on of ari thmeti c group perform addi ti on,
subtracti on, mul ti pl i cati on, di vi si on, etc. on data pl aced i n a regi ster or memory. Logi cal
group i nstructi ons perform AND, OR, EX-OR, compari son, rotate, etc. operati ons on the
contents of regi sters. I nstructi ons of branch control group perform condi ti onal and uncondi ti onal
jumps, subrouti ne cal l and return, and restart. I /O and machi ne control group i nstructi ons
perform i nput, output, stack and machi ne control operati ons.
When a program i s wri tten i n a l anguage other than machi ne l anguage, the computer
wi l l not understand thi s. Therefore, a program wri tten i n other l angauges must be transl ated
i nto machi ne l anguage before i t i s executed. The task of transl ati on i s done by software. A
program whi ch transl ates an assembl y l anguage program i nto a machi ne l anguage program
i s cal l ed an assembler.
A l anguage i n whi ch each statement or an i nstructi on i s di rectl y transl ated i nto a si ngl e
machi ne code i s known as a low-level l anguage. Each mnemoni c of an assembl y l anguage has
a uni que machi ne code. An assembl y l anguage i s a l ow-l evel l anguage. A machi ne l anguage
i s al so a l ow-l evel l anguage. An assembl y l anguage depends on the i nternal archi tecture of
a processor. Each processor has i ts own assembl y l anguage. Assembl y l anguage of one processor
cannot be used for another processor. I n other words i t i s not portable. To wri te an assembl y
l anguage program, a programmer must have the detai l ed knowl edge of the i nstructi on set of
the parti cul ar processor, i ts i nternal archi tecture, regi sters, and connecti on of pheri pheral s
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to ports etc. I t i s not very fast and effi ci ent programmi ng l anguage. To overcome the di ffi cul ti es
associ ated wi th assembl y l anguage, hi gh-l evel (procedure-ori ented/object-ori ented) l anguages
have been devel oped. I n a hi gh-l evel l anguage an i nstructi on i s cal l ed statement rather than
mnemoni c. Statements more cl osel y resembl e Engl i sh and Mathemati cs than mnemoni cs.
Hi gh-l evel l anguages permi t programmers to descri be tasks i n the forms whi ch are probl em
ori ented rather than computer ori ented. Programmi ng i n a hi gh-l evel l anguage does not
requi re preci se knowl edge of the archi tecture of a computer whi ch i s to be used. A program
wri tten i n a hi gh-l evel l anguage wi l l run on any computer whi ch has a compi l er for that
l anguage. I n other words a hi gh-l evel l anguage i s portabl e.
A program whi ch transl ates a hi gh-l evel l anguage program i nto a machi ne l anguage
program i s cal l ed a compiler. An interpreter i s al so a program whi ch transl ates a hi gh-l evel
l anguage program i nto machi ne l anguage program. I t reads one statement at a ti me, transl ates
i t i nto machi ne codes, executes i t and then goes to the next statement of the program. On
the other hand a compi l er reads an enti re program once or twi ce and then transl ates i t. A
compi l er i s faster and more powerful than an i nterpreter. A compi l er i s a l arger program and
occupi es more memory space. I t i s costl i er than i nterpreter.
I mportant hi gh-l evel l anguages are: BASI C, FORTRAN, COBOL, PASCAL, C and C
++
l anguages, PROLOG, JAVA etc. BASI C i s a abbrevi ati on for Begi nners Al l -purpose Symbol i c
I nstructi on Code. I t i s a very si mpl e and easy l anguage for begi nners. I t i s sui tabl e for
sci enti fi c cal cul ati on. FORTRAN stands for Formul a Transl ati on. I t i s a powerful l anguage for
sci enti fi c and engi neeri ng computati ons. COBOL stands for Common Busi ness Ori ented
Language. I t i s sui tabl e for busi ness data processi ng. PASCAL i s a mul ti purpose l anguage
sui tabl e for both sci enti fi c and busi ness appl i cati ons. Thi s l anguage has been named i n
honour of Bl ai se Pascal , a gr eat mathemati ci an and i nventor. PROLOG stands for
Programmi ng i n LOGI C. I t i s sui tabl e for arti fi ci al i ntel l i gence appl i cati ons. I t has been
chosen for fi fth generati on computers. A l arge number of hi gh-l evel l anguages have been
devel oped. A parti cul ar l anguage may be very effi ci ent for a parti cul ar fi el d. JAVA i s an object
ori ented l anguage. I t i s sui tabl e for I nternet appl i cati ons.
1.12 BATCH PROCESSING, MULTIPROGRAMMING AND MULTIUSER SYSTEM
I n a batch processi ng system a computer serves one user at a ti me. When the program
of one user i s compl eted, then onl y, another program i s started. Thi s type of system does not
al l ow a user to i nteract wi th the computer. The l arge computers used i n the 1960s, executed
programs one by one usi ng thi s method.
I n mul ti programmi ng several programs are processed by a computer si mul taneousl y.
Usual l y, a CPU i s much faster as compared to I /O devi ces. Whi l e I /O devi ces are performi ng
certai n tasks the CPU may not be doi ng any task, i t may be l yi ng i dl e. To keep CPU busy
for most of the ti me, i t i s desi rabl e to process a number of programs concurrentl y. Thi s i s
achi eved by over l appi ng CPU and I /O oper ati ons when sever al pr ogr ams ar e r unni ng
si mul taneousl y. The mul ti programmi ng i s an i mprovement over batch processi ng, but i t sti l l
does not al l ow users to i nteract wi th the computer.
I n a multiuser system a number of users can work si mul taneousl y. I t al l ows each user
to i nteract wi th the computer. I t i s al so known as time-shared system. A number of vi deo
termi nal s are connected to a computer. Users enter data at very sl ow rate, and computer
processes data at very fast rate. Maki ng use of thi s fact a computer serves several users
1.24 COMPUTER FUNDAMENTALS
si mul taneousl y by attendi ng them i n turn. I t usual l y gi ves 20 mi l l i seconds ti me to each user.
Each user feel s that he i s usi ng the computer excl usi vel y because the computer processes hi s
data as fast as he enters i t. Each user can uti l i ze the common resources such as hi gh-speed
pri nter, computers memory, etc. A demeri t of a mul ti user system i s that when computer i s
down al l computi ng jobs are stopped. They can be resumed onl y when the computer i s up and
runni ng agai n. Another demeri t i s that i ts response ti me to each user becomes unreasonabl y
l ong when the number of users becomes more. Server-cl i ent type of computi ng i s al so a ki nd
of system. Nowadays i t i s wi del y used. Ti me-shared type mul ti user systems were used earl i er.
I n an i ndustry a number of processes are control l ed by a computer si mul taneousl y. Thi s
is called multitasking. The term mul ti taski ng i s more often used i n real -ti me control i n
i ndustr y. When thi s ter m i s used el sewher e i n gener al sense, i t si mpl y means
mul ti pr ogr ammi ng. The ti me-shar ed appr oach of mul ti user system i s not sui tabl e for
mul ti taski ng system. I n a mul ti user system al l users are attended at approxi matel y equal
ti me i nterval s. I n mul ti taski ng system for i ndustri al control pri ori ty-based job schedul i ng i s
used. A hi gh pri ori ty task can i nterrupt a l ow pri ori ty task.
1.13 MULTITHREADING
Multithreading. A thread i s the smal l est executabl e el ement of an appl i cati on. Therefore,
i f an appl i cati on has the abi l i ty to execute, at l east two threads si mul taneousl y, i t wi l l run
twi ce as fast on a dual -core processor. So a dual -core i s benefi ci al , i f an appl i cati on i s
mul ti threaded. But most appl i cati ons whi ch are avai l abl e today are not mul ti threaded. However,
some PC users run more appl i cati ons at a ti me, so they wi l l be benefi ted by usi ng dual -core
pr ocessor.
1.14 COMPUTER NETWORK
A processi ng compl ex consi sti ng of two or more i nterconnected computers i s cal l ed a
computer network. When the computers of a computer network are wi thi n a bui l di ng or
campus, they are i nterconnected through a l ocal area network (LAN). I f computer uni ts are
si tuated at l arge di stances, they are i nterconnected through tel ecommuni cati on l i nks. Satel l i tes
are al so used for thi s purpose. A computer network spread over a wi de area i s known as
WAN. The I nternet i s al so a ki nd of WAN.
1.15 DISTRIBUTED PROCESSING (COMPUTING) OR MULTIPROCESSING
I n a computer network each computer operates i ndependentl y on separate tasks. When
a number of users work on separate computers i nterconnected i n a computer network, the
processi ng techni que i s known as distributed processing (computi ng) or mul ti processi ng. The
term mul ti processi ng i s al so used i n case of a mul ti processor system (i .e., when a computer
contai ns several processors). For di stri buted processi ng a l arge powerful central computer
wi th l arge memory and hi gh-speed pri nter i s used i n a computer network (LAN or WAN). A
number of PCs or workstati ons are connected to the central computer (Server). Each user
wi th a PC, performs hi s task l ocal l y i n an i ndependent manner. I f he wants to use the server
for compl ex computati on or to access database avai l abl e wi th the server, he can do so. I n thi s
system the user can sel ect the l ocal computer best sui ted to the l ocal computati onal needs.
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A company or organi zati on al so can use di stri buted computati on techni que. The companys
work are done partwi se at di fferent computers whi ch are connected through a LAN or WAN
or I nternet.
Di sadvantages of a ti me-shared system i s el i mi nated to a great extent i n a di stri buted
processi ng system. I f the l arge computer i s down, al l the jobs are not stopped. Most of the
tasks are carri ed out on the l ocal mi crocomputer. The burden on the l arge computer i s
reduced to a great extent, as much of the computi ng work i s done by l ocal mi crocomputers.
1.16 LOCAL AREA NETWORK (LAN) AND WIDE AREA NETWORK (WAN)
I n an i ndustry, commerci al organi zati on or an offi ce whi ch has several computers i n a
bui l di ng or a campus, need may ari se to transmi t data between computers. I n such a si tuati on
a hi gh-speed i nterconnecti ng network cal l ed local area network (LAN) i s needed to i nterconnect
the computers so that they can communi cate wi th each other. There are vari ous ways for
i nterconnecti ng computers such as star, common-bus, ri ng type LAN, and so on. I n a star
type LAN there i s a central control l er that coordi nates al l communi cati on between computers
on the LAN. The common-bus type LAN al so known as Ethernet, does not have any central
control l er. Rather, the control of the bus i s spread among al l the computers connected to the
common-bus. The common-bus i s si mpl y a wi re usual l y a co-axi al cabl e to whi ch any number
of computers can be easi l y connected. Any computer can take over the bus to transmi t data.
Two computers are not al l owed to transmi t data at the same ti me. Al so, i n the ri ng type LAN,
the control i s di stri buted among al l of the computers on the network. A bi nary code cal l ed
token i s passed around the ri ng from workstati on to workstati on. Al l workstati ons are l i nked
to form a conti nuous l oop. A computer whi ch wants to transmi t data must possess the token.
I t takes the token from the bus, to prevent any other computer from transmi tti ng. After the
transmi ssi on i s compl eted, i t puts the token on the ri ng so that another computer whi ch has
to transmi t data can recei ve i t.
LANs ar e cl assi fi ed accor di ng to thei r data tr ansfer speed, as: hi gh speed, medi um-
speed and l ow-speed LANs. I n hi gh-speed LANs data ar e tr ansmi tted at the r ate a few
gi gabi ts per second (Mbps). Such LANs ar e desi gned to l i nk ser ver computer s. I n medi um-
speed LANs data ar e tr ansmi tted at the r ate of about a gi gabi ts per second. Such LANs
ar e sui tabl e to l i nk smal l er ser ver s and PCs. Exampl e of a medi um-speed LAN i s Ether net.
I ts speed i s 1 Gbi ts/s. Low-speed LANs tr ansmi t data at a few hundr ed Mbps. They ar e
sui tabl e to l i nk PCs and other wor kstati ons. Wi r el ess LAN, cal l ed WLAN has al so been
devel oped.
WAN. When computers/termi nal s are spread over a wi de area, they can be connected
through publ i c or pri vate communi cati on system. Thi s type of network i s cal l ed wide area
network (WAN). I nternet i s al so a ki nd of WAN.
1.16.1 Internet
A worl dwi de computer network i s cal l ed I nternet. Any two computers on the I nternet
can communi cate to each other. Each computer on the I nternet has an address whi ch i s
uni versal l y recogni zed throughout the network. Web, al so cal l ed World Wide Web (WWW) i s
a col l ecti on of resources that one can access from anywhere i n the worl d, over the I nternet.
These resources can provi de textual documents, stati c graphi c i mages, vi deo cl i ps, programs,
database or any other ki nd of i nformati on. Web i s just one of the many servi ces avai l abl e on
1.26 COMPUTER FUNDAMENTALS
the I nternet. The servi ces avai l abl e on the I nternet other than Web are : E-mai l , FTP,
Mai l i ng l i sts, Usenet news and arti cl es, Chat sessi ons, etc. The WWW i s a vast l i brary of
i nformati on i n the fi el d of art, sci ence, engi neeri ng, commerce and so on. On I nternet
exchange of i nformati on takes pl ace on cl i ent/server model . A client i s a computer whi ch
recei ves i nformati on from the server. A server i s a computer whi ch gi ves i nformati on to
other computers on the I nternet. Servers and cl i ents communi cate through a protocol , HTTP
(Hyper Text Transfer Protocol ). The set of rul es for i nformati on exchange between server and
cl i ent i s cal l ed protocol.
I mportant termi nol ogi es rel ated to I nternet are gi ven bel ow:
URL (Uniform Resource Locator). I t i s pronounced as earl . I t i s descri pti ve address
for a Web page or any other fi l e on the I nternet. An exampl e i s http://www. i ntel .com/Penti um
I I I /
Thi s address i s to obtai n i nformati on regardi ng Penti um I I I mi croprocessor from I ntel
Corporati on. A si mpl e URL for a Web page i ncl udes (i) the name of the Web protocol (http),
(ii) a col on, (iii) two forward sl ashes, (iv) a domai n name and (v) a fi nal sl ash. The domai n
name i s the I nternet name of the server whi ch serves i nformati on.
HTML (Hyper Text Markup Language). I t i s a computer l anguage to prepare Web
pages. Hypertext i s a text wi th extra features l i ke formatti ng, i mages, mul ti medi a and l i nks
to other documents. Markup i s the process of addi ng extra symbol s to ordi nary text. Each
symbol whi ch i s used i n HTML has i ts own syntax, sl ang and rul es. I t i s not a programmi ng
l anguage. I t i s a markup l anguage. I t cl assi fi es the parts of a document accordi ng to thei r
functi on. I n other words i t i ndi cates whi ch part i s ti tl e, whi ch part i s a subheadi ng, whi ch part
i s the name of the author, and so on.
Web Site. Web server i s known as Web si te. I t i s the l ocati on at whi ch pages are stored.
Web Page and Home Page. Web page i s an i nformati on (document) wri tten i n HTML,
whi ch can be put on a Web server. I t may gi ve i nformati on about a person, a company, a
group of peopl e, an organi zati on, a product, and so on. Web pages provi de easy and effi ci ent
method for di stri buti ng i nformati on, fi l es and softwares. Home page contai ns i ntroductory
i nformati on and/or master menu of the document.
Web Browser. The cl i ent software package cal l ed Web browser accesses the Web and
contacts a server computer on the I nternet, and exchanges i nformati on wi th the server. I t
understands how to communi cate to a Web server through HTTP protocol , di spl ays i nformati on
and gi ves a way to represent hyper text l i nks. The two most popul ar Web browsers are:
Netscapes Navi gator and Mi crosofts I nternet Expl orer (I E). These Web browsers use graphi cal
user i nterface. Other servi ces can al so be used from a Web browser such as Usenet, FTP, etc.
The server computer i s al so provi ded wi th proper software to faci l i tate the exchange of
i nformati on. Such a software i s known as Web server software. Netscapes Navi gator and
I nternet Expl orer al so al l ow user to use other servi ces on the I nternet, such as E-mai l , to
downl oad fi l es from FTP servers, read and post arti cl es to Usenet newsgroups, etc.
Some other Web browsers are : Lynx (a text-onl y browser), Mosai c (the fi rst graphi cal
browser on whi ch Navi gator and I E are based), Web TV (runs on a tel evi si on set), Amaya,
Udi WWW, GNUscape, Opera, Arena, DOSLynx, etc.
Usenet News. I t i s forum for onl i ne di scussi on or exchange of i nformati on. I nformati on
may be on any topi c. News cl i ent programs such as Mi crosofts I nternet News, Netscape
News, etc. are avai l abl e, whi ch al l ow you to get news or i nformati on or arti cl e on any topi c
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from news servers through Usenet. Netscape News comes wi th Netscape Navi gator. The
Usenet servi ce i s avai l abl e on I nternet. NNTP (Network News Transfer Protocol ) i s used to
di stri bute news on I nternet.
FTP (File Transfer Protocol). I t i s a servi ce used on I nternet to exchange fi l es. Fi l es
may be text fi l e, programs or i mages. There are FTP servers. FTP cl i ent can access a FTP
ser ver.
Telnet. I t i s a protocol to connect users to database, l i brary catal ogs and other i nformati on
resources on the I nternet. WI NDOWS-95 has tel net program whi ch can be used to access
tel net servers on the I nternet. Nei ther Navi gator nor I E i ncl ude tel net.
Gopher. I t i s an I nternet servi ce that al l ows users to access gopher servers on the
I nternet. A few gopher servers sti l l exi st on the I nternet, but i t i s al most exti nct now.
TCP/IP (Transmission Control Protocol/Internet Protocol). TCP works wi th I P.
They are si mpl y di fferent l ayers of control . They work on both LANs and WANs. They
provi de error checki ng, fl ow control (to prevent swampi ng of an user by another faster or
more powerful user), and status and synchroni zati on control . TCP i s a transport l ayer. I P i s
a network l ayer whi ch handl es routi ng and del i very. To connect a computer to the I nternet,
TCP/I P i s i nstal l ed. Then I SP or onl i ne servi ce i s requi red to connect the computer to the
I nternet. TCP/I P i ncl udes standards for many common appl i cati ons i ncl udi ng E-mai l , FTP,
remote l ogi n, etc.
ISP (Internet Service Provider). I n I ndia Vi desh Samachar Ni gam Li mi ted (VSNL)
provi des access to the I nternet through the Gateway I nternet Access (GI AS). Some other
compani es are al so I SP, for exampl e, Satyam, MTNL (Mahanager Tel ephone Ni gam Ltd.),
Bharti BT, etc.
Search Engine. A search engi ne i s a program whi ch l ooks through i ts database for
i nformati on that matches your request. I nformati on i n the database are about Web si tes
and thei r contents. Exampl es of search engi nes are : Alta Vi sta, Yahoo, HotJava, Exci te,
I nfoseek, AOL NetFi nd, Lycos, HotBot, LookSmart, SEARCH.COM, etc. Some I ndi an search
engi nes are : Jadoo, Khoj, I Love I ndi a, 123 I ndi a, etc. Alta Vi sta i s for Web and Usenet.
Yahoo i s for Web, Usenet, E-mai l addresses, current news, peopl e search, ci ty maps and
stocks. Yahoo i s not a search engi ne. I t has a huge l i st of Web si tes, stored i nto categori es.
Yahoo provi des l i nks to search engi nes. HotBot i s good to fi nd si te whi ch uses a parti cul ar
technol ogy, such as JavaScri pt or VRML. HotJava i s wri tten i n Java. I t has been devel oped
by SUN Mi crosystems. I t i s avai l abl e for SPARC/Sol ari s pl atform as wel l as WI NDOWS
pl atform.
Web Crawler. I t i s a program that crawl s through the Web and col l ects i nformati on
regarding the Web si tes. These i nformati on are put i nto the database of a search engi ne.
Worms, Spi ders or robots are the types of crawl ers.
Packet. I t i s the basi c data bui l di ng bl ock. A packet i s sel f-contai ned data structure
whi ch can be sent over the network. I t consi sts of two parts : the header and data. The
header i ncl udes address i nformati on regardi ng the ori gi nati on, desti nati on and the type of the
packet. The data i s a bl ock of data.
Applets. These are smal l Java appl i cati on programs devel oped for I nternet appl i cati ons.
One can devel op new appl i cati on programs usi ng appl ets. Appl ets can be combi ned for an
appl i cati on usi ng a scri pti ng l anguage JavaScri pt. Appl ets avai l abl e at Web si tes can be down
l oaded vi a I nternet, and executed on the l ocal computer.
1.28 COMPUTER FUNDAMENTALS
Hub. I t i s central pl ace to connect computers to a network, tradi ti onal l y for a star
topol ogy. There are two types of hub: passi ve and smart. A passi ve hub si mpl y connects the
vari ous nodes. A smart hub can be remotel y control l ed by the system operator. I t can send
back the i nformati on of packet traffi c for anal ysi s.
Bridge. A bri dge connects networks (or two segments of LAN) that have the same
Network Operati ng System (NOS), but di fferent hardware.
Gateways. Gateways are si mi l ar to bri dges except that they can transl ate protocol and
convert data. They connect networks whi ch operate at di fferent network operati ng systems.
The connected networks through a gateway may or may not have si mi l ar hardware. For
exampl e, a gateway can al l ow a Token Ri ng runni ng I PX packet and an Ethernet runni ng
TCP/I P packet to communi cate freel y.
Routers. They control and di rect network traffi c. A network can be segmented i nto
smal l networks usi ng a router. The smal l networks are known as zones. I f the packets
desti nati on i s i n the same zone, the packet i s not exposed to the other zones. Thi s l i mi ts
traffi c across the enti re network.
Intranet. A corporate or organi zati onal network whi ch uses the same protocol s, (namel y
TCP/I P) as used on the I nternet to share fi l es and send E-mai l , i s cal l ed I ntranet. An I ntranet
i s cut off from the outsi de worl d. I t permi ts i ts users to access the I nternet, but i t prevents
outsi de access to i nternal fi l es by hi di ng behi nd a securi ty system known as a firewall. I n
many l arge organi zati on i ntranet i s a wi de area network.
Extranet. When computers of many organi zati on are connected through TCP/I P protocol ,
such a network i s cal l ed Extranet.
1.17 SOME TERMINOLOGIES OF MOBILE PHONE STANDARDS AND DATA
COMMUNICATION
Broadband. The mi ni mum bandwi dth for broadband must be 256 kbps (ki l obi ts per
second). Usi ng broadband mul ti pl e channel s can be sent over a si ngl e l i nk. I f there i s
i nsuffi ci ent bandwi dth, then mul ti pl e servi ces can not run rel i abl y over the same connecti on
(l i nk). Wi th broadband the user can go beyond Web browsi ng, E-mai l and downl oads; for
exampl e, now he can go for audi o/vi deo streami ng to l i sten to songs or watch movi es etc.
DSL (Digital Subscriber Line). I t i s a broadband technol ogy. I t uses exi sti ng tel ephone
l i nes to transmi t data. I ts data transmi ssi on rate l i es i n the range of 1.5-8 mbps.
ADSL (Asymmetrical DSL). I n ADSL the data fl ow i s faster i n one di recti on than i n
the other. Usual l y, downl oads rates are hi gher than upl oad (outwards rates) rates.
DTH (Direct To Home). I n DTH a di sh antenna i s used. One can get a number of
channel s on hi s TV, say 100 channel s or more. El ectri ci ty consumpti on i s 40 watts. I t i s cheap
and compact. The di ameter of the di sh i s 45-60 cm. I t i s based on di gi tal technol ogy. A set-
top-box i s al so there wi th the di sh to control channel s. I t i s not connected through cabl e. I t
recei ves si gnal s di rectl y from a satel l i te.
Wi-Fi. Wi rel ess LAN standards I EEE 802.11, namel y 802.11 b, g and a are cal l ed Wi -Fi .
Wi rel ess LAN i s abbrevi ated as WLAN. I n Wi -Fi , Wi i s for wi rel ess but Fi i s not meani ngful .
Wi -Fi i s si mi l ar to Hi -Fi . 802.11a, b and c operate at 2.4 GHZ, 2.4 GHZ and 5 GHZ respecti vel y.
Thei r throughputs are 54 Mbi ts/s, 11 Mbi ts/s and 54 Mbi ts/s respecti vel y.
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WEP (Wired Encripted Piracy). I t i s a bui l t-i n securi ty method i n Wi -Fi . I mproved
securi ty methods descri bed bel ow have been devel oped for Wi -Fi .
RADIUS (Remote Authentication Dial-In User Service). I t i s a securi ty protocol for
Wi -Fi .
VPN. I t i s a poi nt-to poi nt tunnel i ng Protocol (PPTP) to provi de encri pti on over Wi -Fi
network. I t i s a securi ty measure for Wi -Fi network.
WPA (Wi-Fi Protected Access). I t i s an extensi on of 802.11 wi rel ess LAN standards,
802.11i , whi ch i s for more robust securi ty.
WiMAX. I EEE 802.16 standard i s al so cal l ed Wi Max (Worl dwi de I nteroperabi l i ty for
Mi crowave Access). Mi crowave radi o or terrestri al wi rel ess can be used to bui l d wi rel ess LAN
and by I SPs to provi de wi rel ess I nternet servi ces. Mi crowave wi rel ess system work i n the 900
MHZ to 40 GHZ frequency band. I t can be used i n a poi nt-to-poi nt (P-T-P) or poi nt-to-
mul ti poi nt (P-T-M) confi gurati ons.
FSO (Free Space Optics). I t uses l aser technol ogy to pr ovi de wi r el ess data
communi cati on. I t i mposes l i ne of si ght l i mi tati on.
VSAT. I nternet access to remote areas can be provi ded by satel l i te.
D-AMPS (Digital Advanced Mobile Phone System). I t was a second-generati on mobi l e
phone standard. I t was wi del y used i n USA.
GSM (Global System for Mobile Communication). I t i s a second-generati on mobi l e
phones standard. The fi rst-generati on of mobi l e phones was anal og voi ce. The second-generati on
was for di gi tal voi ce. I t was used everywhere i n the worl d except USA. I n USA, D-AMPS was
used. The GSM channel s are much wi der (200 KHZ) than the D-AMPS (30KHZ).
CDMA (Code Division Multiple Access). I t i s a standard for mobi l e phones and
techni cal l y superi or to D-AMPS and GSM. I t i s the basi s for thi rd-generati on mobi l e phone
systems. I t i s al so a second-generati on di gi tal scheme. I ts speed i s 144 kbps.
GPRS (General Packet Radio Service). I t i s a mobi l e phone standard i n between the
second-generati on and the thi rd-generati on. I t i s cal l ed 2.5G scheme. I t i s an overl ay packet
network on the top of D-AMPS or GSM. I ts maxi mum speed i s 56 kbps. For GSM users,
I nternet access i s provi ded through GPRS.
EDGE (Enhanced Data rates for GSM Evolution). I t i s al so cal l ed 2.5G scheme. I ts
maxi mum data transmi ssi on speed i s 230 kbps. I t i s a radi o based hi gh-speed mobi l e data
standard.
W-CDMA (Wideband CDMA). I t i s a thi rd-generati on (3G) mobi l e phone standard. I t
runs at 5MHZ bandwi dth and i ts speed i s 1920 kbps. I t i s desi gned to i nterwork wi th GSM
networks al though i t i s not backward compati bl e wi th GSM. Furthermore, i t has the property
that a cal l er can l eave a W-CDMA cel l and enter a GSM cel l wi thout l osi ng the cal l . The W-
CDMA does not work wi th CDMA. The thi rd-generati on schemes are for di gi tal voi ce and
data. Wi th 3G, users have the faci l i ti es for vi deo through the I nternet, vi deo conferenci ng etc.
EV-DO (Evolution Date Only). I t i s a 3G mobi l e phone standard. I t provi des 2.4 mbps
bandwi dth to mobi l e users on a CDMA network.
UMTS (Universal Mobile Telecommunication System). I t i s a 3G mobi l e technol ogy.
I ts data transfer speed i s 1920 kbi ts/s.
1.30 COMPUTER FUNDAMENTALS
1.18 SHORT RANGE WIRELESS
Short range wi rel ess system i s used for communi cati on between personal di gi tal devi ces.
There i s a term PAN (Personal Area Network) whi ch i s used when personal devi ces are
connected i n a network. Wi rel ess PAN i s cal l ed WPAN. Nowadays, peopl e can connect thei r
PDA to thei r PC or l aptop, answer mobi l e cal l s through a wi rel ess headset, do shooti ng a
vi deo wi th a di gi tal camera and streami ng i t to a tel evi si on etc. Al l thi s type of thi ngs can
be done usi ng WPAN. The three technol ogi es, namel y Bl uetooth 2.0, WUSB (Wi rel ess USB)
and Zi gBee are used nowadays for WPAN.
Bluetooth 2.0. I t operates i n the frequency band of 2.45 GHZ. I t i s same as that for i ts
previ ous versi on Bl uetooth 1.2. But data transfer rate of Bl uetooth 2.0 i s 2.1 Mbps agai nst
1 Mbps for versi on 1.2. I ncreased data transfer rate enabl es faster transmi ssi on of musi c and
vi deo. Bl uetooth 2.0 consumes l ess power and the maxi mum di stance can go up to 100
metres. I t gi ves i mproved qual i ty of servi ce for better audi o and vi deo streami ng. I t al so
supports mul ti cast usi ng whi ch one Bl uetooth devi ce can si mul taneousl y transfer data to
many Bl uetooth devi ces.
WUSB (Wireless USB). I t gi ves up to 480 Mbps throughput. I t i s sui tabl e for transferri ng
l arge amount of data over wi rel ess system. I t uses Ul tra-Wi deband technol ogy for transferri ng
data. I t can use a band whi ch i s 7 GHZ wi de rangi ng from 3.1 to 10.6 GHZ.
ZigBee. I t i s sui tabl e for remote moni tori ng appl i cati ons such as home, bui l di ng and
i ndustri al automati on. I t i s used for sensor devi ces for ai r condi ti oni ng, cool i ng, smoke al arms
etc. For such appl i cati ons very hi gh throughputs are not requi red. Such appl i cati ons requi re
l ow power consumpti on so that batteri es can go for l onger peri ods.
1.19 CONTROL FLOW AND DATA FLOW COMPUTERS
The basi c archi tecture of a conventi onal computer consi sts of a CPU, memory and i nput-
output devi ces. Thi s archi tecture was gi ven by John von Neumann i n mi d 1940s, and hence
such an archi tecture i s cal l ed von Neumann archi tecture. The program i s stored i n the
memory. The CPU fetches one i nstructi on from the memory at a ti me and executes i t. Thus
the i nstructi ons are executed sequenti al l y whi ch i s i nherentl y a sl ow process. Neumann
machi nes are cal l ed control flow computers because i nstructi ons are executed sequenti al l y as
control l ed by a program counter. The speed of a sequenti al machi ne i s l i mi ted by the speed
at whi ch the CPU fetches i nstructi ons and data from the memory, and the speed at whi ch
the CPU executes i nstructi ons. To i ncrease the speed of data processi ng paral l el computers
have been devel oped i n whi ch several CPUs are connected i n paral l el to sol ve a probl em.
Even i n paral l el computers the basi c bui l di ng bl ocks are Neumann processors. The paral l el i sm
i s not tackl ed at basi c l evel . The enti re burden of sol vi ng a probl em usi ng paral l el processi ng
rests on the programmi ng techni que.
The data fl ow desi gn approach treats the i ssue of paral l el i sm at a fundamental l evel . I n
data fl ow approach an i nstructi on i s executed whenever i ts requi red operands become avai l abl e.
No pr ogr am counter i s needed i n a data fl ow computer. Oper ati ons ar e car r i ed out
asynchronousl y as soon as operands requi red for the operati on become avai l abl e. The fetch/
decode uni t of the processor, fetches 20 to 30 i nstructi ons i n advance. The i nstructi ons are
decoded and thei r opcodes are kept i n an instruction pool. The di spatch/execute uni t of the
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processor checks the opcode of an i nstructi on i n the i nstructi on pool , and exami nes whether
i ts data are avai l abl e for i ts executi on. I f data are avai l abl e, the i nstructi on i s executed. I f
data are not avai l abl e for the executi on of an i nstructi on, di spatch uni t goes ahead and
exami nes the next i nstructi on i n the i nstructi on pool . Thus i t executes onl y those i nstructi ons
for whi ch data are avai l abl e. The i nstructi on whi ch are not executed due to non-avai l abi l i ty
of data, are executed i n the next round of checki ng of the i nstructi ons i n the i nstructi on pool .
Whenever data become avai l abl e remai ni ng i nstructi ons are executed. Thus i t i s seen that
the processor does not wai t, when data are not avai l abl e for some i nstructi ons. Thi s techni que
i ncreases the speed of the processor. Penti um Pro, Penti um I I , Penti um I I I and Penti um 4
are data fl ow processors.
1.20 RISC, CISC AND EPIC PROCESSORS
RI SC stands for Reduced I nstructi on Set Computer. CI SC stands for Compl ex I nstructi on
Set Computer. Where RI SC and CI SC are used as adjecti ve C i n RI SC and CI SC stands for
Computi ng. There are two techni ques of desi gni ng a control uni t of a processor : hardware
techni que and software techni que. For the executi on of an i nstructi on a number of steps are
needed. For each step a number of control si gnal s are generated by the control uni t of the
processor. I n a RI SC processor, al l the necessary si gnal s for the executi on of an i nstructi on
are generated by an el ectroni c ci rcui t of the control uni t. For each i nstructi on there i s an
el ectroni c ci rcui t i n the control uni t, to generate necessary control si gnal s. Thi s i s a hardware
techni que of desi gni ng a control uni t. I n thi s techni que mi croprogrami ng i s not used.
I n CI SC processor, a mi croprogram i s executed to generate necessary control si gnal s for
the executi on of an i nstructi on. A mi croprogram i s wri tten for each i nstructi on usi ng a
sequence of mi croi nstructi ons. Thi s techni que i s known as microprograming. When a
mi croi nstructi on i s executed a set of control si gnal s i s produced for the operati on of certai n
step of an i nstructi on. The mi croi nstructi ons of a mi croprogram are executed one by one, and
i n turn, the necessary control si gnal s are produced i n steps for the executi on of an i nstructi on.
For each mi croi nstructi on, there i s a mi crocode. Mi crocodes are stored i n a ROM whi ch i s
wi thi n the processor. More detai l s are gi ven i n Chapter 5.
The checki ng of mi croi nstructi ons can be done more easi l y than the checki ng of computer
i nstructi ons to see that they work properl y. I f there i s an error i n a computer i nstructi on,
the desi gner can correct i t by changi ng mi croi nstructi ons. On the other hand i n a RI SC
processor (hard-wi red CPU), i f an i nstructi on i s erroneous, the desi gner has to change compl ex
connecti ons or the chi p desi gn. I n a mi crcoprogrammed desi gn of computer, new i nstructi ons
can be i mpl emented by wri ti ng new sets of mi croi nstructi ons. Thi s i s si mi l ar to wri ti ng
vari ous programs usi ng an i nstructi on set of a computer. Such a computer can al so be made
to execute the i nstructi ons of an another computer. Thi s process i s known as emulation.
These advantages of mi croprogrami ng are achi eved at the cost of processi ng speed.
EPI C (Expl i ci tl y Paral l el I nstructi on Computi ng) processor has been di scussed i n Secti on
5.11.
1.20.1 Microprogrammed Control Unit
Mi croprogrammi ng has al ready been expl ai ned i n the Secti on 1.20. Fi g 1.5 shows a
schemati c di agram of mi croprogrammed control uni t. The i nstructi on regi ster contai ns the
operati on control code (opcode) of an i nstructi on whi ch i s to be executed. The decoder decodes
1.32 COMPUTER FUNDAMENTALS
the opcode and gi ves starti ng address of the mi croprogram. The mi croprogram counter, PC
contai ns the address of the next mi croi nstructi on to be executed. I t i s al so cal l ed control
address regi ster. The control memory stores the sets of mi croi nstructi ons. The mi croi nstructi on
i s r ead fr om the contr ol memor y and sent to the contr ol buffer r egi ster. Then the
mi croi nstructi on i s decoded and control si gnal s are generated and i ssued. The control si gnal s
acti vate the necessary ari thmeti c and l ogi c uni t etc. to perform the requi red operati ons
defi ned by the mi croi nstructi on code. I n thi s way a mi croi nstructi on i s executed. The next
address i nformati on i s al so i ssued and sent to the sequenci ng l ogi c. The sequenci ng l ogi c uni t
sends the address of next mi croi nstructi on to PC. I t al so sends a read command to the
control memory. I n thi s way the mi croi nstructi ons of a mi croprogram are executed one bye
one to execute an i nstructi on.
Fig. 1.5 Mi croprogrammed Control Uni t
1.21 COMPUTER APPLICATIONS
Computer i s the most versati l e tool man has ever created. Nowadays they are bei ng used
al most i n every sphere of our l i fe. Earl i er, a computer was used onl y for sci enti fi c and
engi neeri ng computati onal work. But nowadays, besi des computati onal work computers are
extensi vel y used for non-computati onal wor k such as stor i ng i nfor mati on, tr ansmi tti ng
i nformati on, creati ng and handl i ng fi l es i n offi ces, control l i ng i ndustri al machi nes and processes,
control l i ng home, busi ness and commerci al appl i ances; ti cket reservati on i n pl anes and rai l ways,
tel ephone exchange, di agnosi ng di seases, recordi ng games events, composi ti on of musi c,
pai nti ng, book pri nti ng, pri nti ng newspapers, prepari ng drawi ngs, i n securi ty arrangements
to watch and supervi se certai n areas, to hel p pol i ce i n cri me i nvesti gati on, i n educati on, and
so on. About 75% of the work done by computers today i s of non-computati onal nature.
Computers are extensi vel y used i n offi ces for handl i ng fi l es, stori ng i nformati on, creati ng
fi l es, admi ni strati ve purposes, i n keepi ng records of staff, prepari ng sal ary bi l l s and for
communi cati on. I f al l work of an offi ce are done by computers, i t i s cal l ed an electronic office.
The term offi ce automati on i s used when computers are extensi vel y used for offi ce work.
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Wordprocessi ng softwares are used for creati ng, mani pul ati ng and stori ng text such as l etters,
notes, i nvoi ces, reports, l egal bri efs, etc.
Computers are bei ng wi del y used for prepari ng accountants l edger, budget, i nventory
control ; anal ysi s of profi t and l oss i n an i nvestment scheme, purchasi ng shares and debentures
of a company, and many other accounti ng work. Accounti ng tasks are qui ckl y anal yzed and
resul ts may be tabul ated or produced i n graphi cal forms.
Modern computer systems can store huge amount of i nformati on. A col l ecti on of i nformati on
may be kept i n the form of a database. A l arge col l ecti on of data i s cal l ed a database. From
a database the requi red i nformati on can be sorted i n the desi red manner. To handl e database
speci al programs cal l ed database programs have been devel oped. Vari ous organi zati ons bui l d
and mai ntai n thei r databases for thei r work. Some organi zati ons do busi ness to suppl y
i nformati on i n certai n speci al i zed areas such as medi ci ne, engi neeri ng, busi ness, etc. Customer
becomi ng a subscri ber can get i nformati on from such organi zati on through the I nternet.
Banks are al so usi ng computers for offi ce work, accounti ng work and deal i ng wi th
customers. Computers al l ow customers to make deposi ts and wi thdrawal s. Cash di spensi ng
machi nes are al so used to make payment i n cash and al so to recei ve cash. These are al so
computer-based machi nes, called ATM (Automati c Tel l er Machi ne).
Computers are now wi del y used i n home and offi ce appl i ances such as washi ng machi nes,
TV, tel ephone recei vers, mobi l e phones etc.
I n the medi cal fi el d computers are used i n the di agnosi s of di seases, i n cl i ni cal tests, i n
offi ce work; i n keepi ng records of cases of pati ents, treatments, drugs, etc. Some computer
expert systems have been devel oped to di agnose di seases and prescri be medi ci nes. These
expert computers are based on the expert knowl edge of speci al i sts. Thei r knowl edge i s kept
updated. The doctors have to suppl y i nformati on such as symptoms, medi cal hi story, cl i ni cal
test resul ts etc. At present expert systems are used to hel p doctors, not to substi tute doctors.
Robots are computer-control l ed programmabl e machi nes. They have hands, l egs, opti cal
sensors to see objects etc. They are used i n i ndustry to move materi al s, parts; to assembl e
machi nes etc. They can work i n pl aces where human bei ngs cannot work, for exampl e i n
pl aces where temperature i s unbearabl e and where nucl ear radi ati on are present. They can
handl e harmful chemi cal s, radi oacti ve materi al s and so on.
I nternet i s a worl dwi de computer network. There are a l arge number of Web si tes to
provi de di fferent ki nds of i nformati on through the I nternet i n al most al l spheres of l i fe.
I nformati on i s avai l abl e i n the fi el d of arts, sci ence, engi neeri ng, commerce, and so on.
Presentl y, there are numerous more appl i cati ons of computers. For more detai l s see
Chapter 9.
1.22 IMPACT OF COMPUTERS ON SOCIETY
Nowadays computers are being widely used in industries, offices, schools, colleges, universities
and research organi zati ons; games, mi l i tary, communi cati ons, hospi tal s, banks, hotel s, homes
and so on. They are bei ng used i n al most every fi el d concerni ng the soci ety. They have a great
i mpact on the soci ety. They are changi ng the way of our worki ng, even the way of l i fe. The
use of computers i n i ndustri es has i mproved thei r effi ci ency. The cost of producti on goes down.
The qual i ty of products i s i mproved. Unpl easant and hazardous work can be performed by
robots. Worki ng hours of l abourers are reduced; they get more l ei sure.
1.34 COMPUTER FUNDAMENTALS
The use of computers i n offi ces i mproves thei r worki ng effi ci ency. Record keepi ng becomes
very easy. I nformati on can be searched i mmedi atel y. Reports, notes, memos, etc. can be
prepared i mmedi atel y. The bureaucrati c del ay can be mi ni mi zed to a great extent. I t i mproves
offi ce admi ni strati on. The management task becomes easy.
Computers are capabl e of mani pul ati ng and transmi tti ng texts at very fast rate. They
have revol uti oni zed the fi el d of communi cati ons. A person si tti ng at home can contact any
offi ce, bank and i nformati on suppl yi ng organi zati ons through a computer. I nstead of usi ng a
computer he may use hi s tel evi si on set and an adapter and a keyboard attached to i t for such
purposes. Si tti ng at home, he may do offi ce work, bank transacti ons, marketi ng, purchase of
shares, reservati on of pl ane and bus ti ckets and so on. Offi cers and manages can contact any
branch offi ce anywhere i n the worl d through the computer network. Text, voi ce, data and
pi cture can easi l y be transmi tted nowadays usi ng modern communi cati on systems whi ch
heavi l y depend upon computers. I nformati on i s transmi tted over l ong di stances through
satel l i tes. Vi deo conferenci ng al l ows two-way communi cati on between persons. They can see
each other on the screen. Nowadays vi deo conferences are bei ng arranged. Peopl e parti ci pate
i n conference whi l e si tti ng at thei r homes or offi ces. El ectroni c mai l i s bei ng used to transmi t
i nformati on. I nformati on can be stored i f a person i s physi cal l y not avai l abl e. Later, he can have
the i nformati on. I nformati on may be ei ther i n text form di spl ayed on the screen or voi ce form.
Many organi zati ons have set up i nformati on centres. They have created databases for
speci al i zed as wel l as general servi ces. Professi onal s can get i nformati on i n speci al i zed fi el ds
such as engi neeri ng, medi ci ne, l aw etc. for thei r gui dance. General peopl e can get i nformati on
regardi ng certai n products, stock exchange, market i nformati on, reservati ons for tours, weather
i nformati on, news and so on.
Computers enabl e peopl e getti ng better servi ces from government or pri vate organi zati ons.
There wi l l be shorter wai ti ng l i nes i n queue i n banks, rai l way ti cket reservati on counters,
ai rl i ne ti cket offi ces; better and fast servi ces at hospi tal s, i mproved cl i ni cal tests and di agnosi s
of di seases and so on.
Computers are pl ayi ng an i mportant rol e i n educati on. One can get l essons on certai n
topi cs, speci al l ectures prepared by experts etc. on the screen as many ti mes as he wants
unti l he understands the topi c. Computers are worki ng as teachers or hel pi ng teachers i n
educati onal i nsti tuti ons.
Thus we see that computers have great i mpact on our soci ety. They are even changi ng
the way we work. There are certai n di sadvantages al so. There may be cases of embezzl ement
i n banks, l eakage or mi suse of personal i nformati on, etc. When a person i s usi ng computer
for marketi ng, offi ce work, col l ecti on of i nformati on, etc. hi s acti vi ty i s recorded. One can
mi suse thi s record. So i ndi vi dual pri vacy i s not guaranteed. An effi ci ent securi ty measure has
to be taken. Hardwares and softwares are avai l abl e for such purposes. Someone can pl ay
mi schi ef on computer. He can erase certai n i mportant data. He may take away some i mportant
and pri vate data. Extensi ve use of computers for the job whi ch i s l abour ori ented wi l l cause
unempl oyment. But i n i ndustri es computers can be used for machi ne control and process
control etc. for whi ch el ectroni c or el ectromechani cal control systems were empl oyed i n the
past. Such appl i cati ons of computers do not much affect l abour empl oyment.
I ndustri al revol uti on changed our soci ety from an agri cul tural soci ety to an i ndustri al
soci ety. Now computer i s changi ng our soci ety from an i ndustri al soci ety to an i nformati on
soci ety. I n U.S.A., around 1900, 35% of l abour force was engaged i n agri cul ture, 27 per cent
i n i ndustri es and 13% i n i nformati on sector. By 1980, about 50% were engaged i n i nformati on
sector, 23% i n i ndustri es and onl y 2% i n agri cul ture.
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I NTRODUCTI ON 1.35
The technol ogy i tsel f does not deci de the future of the soci ety. The way we appl y the
technol ogy for the wel fare of manki nd i s i mportant. Thi s i s al so true for computers. As we
use automobi l es and el ectri c motors today extensi vel y, computers wi l l al so be wi del y used by
us. As computers are more powerful , thei r i mpact on the soci ety wi l l be much more than the
appl i cati on of any other tool s.
1.23 FUTURE DEVELOPMENTS
At present si l i con i s used as semi conductor materi al to manufacture semi conductor
devi ces: LSI and VLSI chi ps. El ectrons can move more easi l y i n gal l i um-arseni de (GaAs) than
i n si l i con. Research i s goi ng on to use GaAs to manufacture semi conductor components of a
computer. Fuji tsu of Japan i s maki ng efforts i n thi s di recti on. I t i ntroduced a supercomputer
VP-200 i n 1982, whi ch i ncorporates GaAs technol ogy to some extent.
Research i s al so goi ng on to use l i ght beam i nstead of el ectrons i n semi conductor
devi ces. Bel l Labs. Research worker Devi d Mi l l er has devel oped an opti cal transi stor or chi p.
I t control s l i ght beam i n the same way as a transi stor control s el ectri c current i n i t. Computers
whi ch wi l l use photons (that i s, l i ght beam) i nstead of el ectrons for thei r operati on wi l l be
cal l ed opti cal computer or quantum computer. An opti cal computer wi l l be much more faster
and powerful than computers usi ng si l i con technol ogy.
Further, research i s al so goi ng on to devel op bi ochi ps. Such chi ps wi l l use organi c
materi al for thei r fabri cati on. Mol ecul es of a substance wi l l be organi zed to act as el ectroni c
memory or swi tchi ng devi ces. Research i s al so goi ng on i n Japan and U.S.A. to study the
behavi our of some worms, whi ch wi l l be hel pful to devel op computers of tomorrow. I t has
been observed that some worms are more i ntel l i gent than todays computers and more
dexterous than robots. Some show i nformati on processi ng capabi l i ty and can l earn somethi ng
whi ch todays computer cannot do. For detai l s the reader may refer to the book menti oned
i n Ref. 4.
1.24 VIRUS
A computer vi rus i s a smal l program wri tten wi th bad moti ve to affect badl y the operati on
of a computer. Vi ruses are prepared by anti soci al el ements to damage others computers,
thei r i mportant fi l es etc. They may corrupt fi l es, erase fi l es, make a computer sl ow and so
on. Such harmful programs are cal l ed vi rus because they can spread from one computer to
another computer. They reproduce themsel ves and then cause damage. They i nfect other fi l es
and then spread. They spread vi a E-mai l or through fi l es whi ch are downl oaded. When vi rus
i s present i n a fi l e that i s stored i n a CD or fl oppy, i t wi l l spread to another computer whi ch
uses that CD/fl oppy.
A vi rus hi di ng i n a program i s known as Trojan horse. When the Trojan horse program
i s run, the vi rus l oads i tsel f i nto the computers memory. Once i t i s there, i t can secretl y
attach i tsel f to other fi l es/programs or store i tsel f on any other di sks run on the computer
i ncl udi ng the hard di sk.
To protect computer from vi ruses, anti -vi rus softwares are avai l abl e. Before downl oadi ng
any fi l e from Web, i t must be scanned whether i t i f free from vi ruses. When any fi l e i s to
be copi ed from CD or fl oppy, i t must be scanned.
1.36 COMPUTER FUNDAMENTALS
1.25 MP3 COMPRESSION STANDARD
MP3 i s a standard method of compressi on of audi o si gnal s. I t i s the short form for
Movi ng Pi ctures Expert Group-Versi on2-Layer 3 audi o compressi on standard. The memory
space requi rement i s reduced by a factor about 10 when MP3 standard i s used to store an
audi o fi l e. A 60 mi nutes MP3 musi c fi l e requi res onl y about 50 MB memory space. Wi thout
compressi on, 60 mi nutes musi c fi l e i n di gi tal form requi res about 600 MB memory space.
1.26 MPEG COMPRESSION STANDARD
MPEG i s a standard compressi on method for vi deo si gnal s. I t i s short form for Moti on
Pi ctures Group. I t i s pronounced as em-peg. I t i s not a si ngl e standard, but a seri es of
standards. MPEG-1 i s for TV qual i ty vi deo and l ow resol uti ons vi sual di spl ay uni t (VDU) of
a personal computer (640 X 480 pi xel s resol uti on). MPEG-2 supports HDTV (Hi gh Defi ni ti on
TV). HDTV i s a form of di gi tal transmi ssi on. I t gi ves better qual i ty of pi ctures and excepti onal
sound. Earl i er, most routi ne broadcasts used anal og tel evi si on si gnal s, whi ch were transmi tted
l i ke radi o si gnal s. MPEG-2 i s an emergi ng new standard for TV broadcasts.
1.27 PERSONAL MEDIA PLAYER PMP
After MP3, i t i s the personal medi a pl ayer taki ng portabl e entertai nment worl d by
storm. PMPs pl ay al most al l ki nds of di gi tal audi o and vi deo formats dependi ng upon the
devi ce capabi l i ty. A PMP contai ns a mi ni har d dr i ve, a LCD scr een and a r emovabl e
rechargeabl e battery. The user can vi ew vi deo fi l es on the LCD screen. Most of the PMPs
contai ns at l east 20 GB hard dri ve. A 20 GB hard dri ve can carry about 15 Di v X movi es
al ong wi th 500 songs.
1.28 DIV X
Di v X i s a medi a format. A new package Di v X Create Bundl e i s avai l abl e. I t i s vi deo
compressi on uti l i ty. I t i ncl udes the new i mproved Di v X 6 codec, Di v X converter and Di v X
pro. The new versi on of the Di v X codec represents a si gni fi cant update over versi on 5 and
offers better i mage qual i ty. The Di v X converter converts a vi deo fi l e i n Di v X format. The
user can sel ect Di v X profi l e. I f there are a number of vi deo fi l es havi ng same resol uti on and
frame rate, they can be combi ned i nto one si ngl e fi l e wi th the sel ecti on of menu. There i s
an extensi on to Di v X whi ch al l ows to add menu, chapter ti tl es, subti tl es etc. A Di v X pl ayer
pl ays a Di v X-encoded fi l e.
PROBLEMS
1. What are the essenti al components of a computer? Draw the schemati c bl ock di agram of a
computer showi ng i ts essenti al components. Di scuss the functi on of each component.
2. Di scuss the i mportant features of vari ous generati ons of computers. Gi ve some exampl es of
computers for each generati on.
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3. Expl ai n pri mary memory, secondary memory and cache memory. What type of memory
devi ces are used i n each of these categori es of memory?
4. Expl ai n what you understand by real and vi rtual memory.
5. Di scuss the features of di rect access storage devi ces and seri al access storage devi ces.
6. Show that the memory addressi ng capabi l i ty of a CPU i s equal to 2
n
bytes, where n i s the
number of address l i nes of the CPU.
7. Expl ai n what are MI PS, MFLOPS, SPECi nt, SPECfp, KLI PS, Dhrystone and Whetstone.
8. Whi ch mi croprocessor i s sui tabl e for (i) Cl i ent computer, (ii) Server, (iii) Workstati on and
(iv) Supercomputer?
9. Di scuss the i mpor tant featur es of (a) Pal m PC, (b) Notebook (c) Desktop, (d) Ser ver,
(e) Workstati on and (f) Supercomputer.
10. Expl ai n the terms hardware, software, fi rmware and freeware.
11. Expl ai n what you understand by system software and operati ng system. Gi ve exampl es of
some i mportant operati ng systems.
12. What are appl i cati on programs? What i s thei r uti l i ty? Di scuss the features of an i ntegrated
package.
13. What i s an assembl er, compi l er and i nterpreter?
14. Expl ai n what you understand by l ow-l evel l anguage and hi gh-l evel l anguage. Gi ve exampl es
of each.
15. Di scuss mul ti programmi ng, mul ti taski ng and mul ti user system.
16. Expl ai n (i) Computer network and (ii) Di stri buted processi ng.
17. What i s mul ti threadi ng? Expl ai n.
18. What i s LAN, WAN and I nternet? What i s Ethernet?
19. What do you understand by the term, broadband;
20. Di scuss Wi -Fi and DTH.
21. What i s computer vi rus? Expl ai n.
22. What are RI SC, CI SC and EPI C processors?
23. Expl ai n MP3, MPEG, PMP and Di vX.
24. Di sti ngui sh between control fl ow and datafl ow computers.
25. Di scuss the i mportant appl i cati ons of computers i n di fferent areas.
26. What i s the i mpact of computers on our soci ety?
27. What i s arti fi ci al i ntel l i gence? Gi ve exampl es and appl i cati on of some systems empl oyi ng
arti fi ci al i ntel l i gence.
28. What i s a search engi ne? Gi ve some exampl es of search engi nes. What i s the rol e of a Web
crawl er?
29. Defi ne cl i ent and server computers?
30. What is Web browser? Gi ve i ts exampl es.
31. Expl ai n the fol l owi ng :
URL, Webpage, Websi te, FTP, TCP/I P, HTML, Appl ets, Packets, and I SP
32. Expl ai n the fol l owi ng:
Bri dge, Gateways, Routers and Hub.
33. What are Usenet and FTP?
34. What i s I ntranet? Where i s i t used.
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2
CHAPTER
2.1
7*-4 5;56-
CHAPTER
2.1 INTRODUCTION
We are fami l i ar wi th the deci mal number system whi ch i s used i n our day-to-day work.
I n the deci mal number system there are ten di gi ts whi ch are used to form deci mal numbers.
Ten separate symbol s 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9 are used to represent ten deci mal di gi ts.
A di gi tal computer stores, understands and mani pul ates i nformati on composed of onl y zeros and
ones. A programmer (or user) who works on a computer i s al l owed to use deci mal di gi ts; l etters
A, B, C,. . . Z, a, b, c,..... z, usual speci al symbol s, +, , etc. for hi s conveni ence. The deci mal
di gi ts, l etters, symbol s, etc. are converted to bi nary codes i n the form of 0s and 1s wi thi n the
computer. To understand the operati on of a computer the knowl edge of bi nary, octal and
hexadeci mal number system i s essenti al . Thi s chapter deal s wi th these number systems.
2.2 DECIMAL NUMBER SYSTEM
As the ten fi ngers of our hands are the most conveni ent tool s nature has gi ven, human
bei ngs have al ways used them i n counti ng. So the deci mal number system fol l owed natural l y
from thei r use. The base or radi x of a number system i s defi ned as the number of di gi ts i t
uses to represent numbers i n the system. Si nce the deci mal number system uses ten di gi ts,
from 0 to 9, i ts base or radi x i s 10. The deci mal number system i s al so cal l ed base-10 number
system. The wei ght of each di gi t of a deci mal number depends on i ts rel ati ve posi ti on wi thi n
the number. Thi s i s expl ai ned by the fol l owi ng exampl e.
Example. Take the deci mal number 6498 as an exampl e to expl ai n the wei ght of each
di gi t of the number.
6498 = 6000 + 400 + 90 + 8
= 6 10
3
+ 4 10
2
+ 9 10
1
+ 8 10
0
The wei ght of each di gi t of a deci mal number depends on i ts rel ati ve posi ti on wi thi n the
number as expl ai ned bel ow:
The wei ght of the 1st di gi t of the number from the ri ght hand si de = 1st di gi t 10
0
.
The wei ght of the 2nd di gi t of the number from the ri ght hand si de = 2nd di gi t 10
1
.
The wei ght of the 3rd di gi t of the number from the ri ght hand si de = 3rd di gi t 10
2
.
The wei ght of the 4th di gi t of the number from the ri ght hand si de = 4th di gi t 10
3
.
2.2 COMPUTER FUNDAMENTALS
The above expressi ons can be wri tten i n general form as fol l ows:
The wei ght of the nth di gi t of the number from the ri ght hand si de
= nth di gi t 10
n1
= nth di gi t (Base)
n1
The number system i n whi ch the wei ght of each di gi t depends on i ts rel ati ve posi ti on
wi thi n the number, i s cal l ed positional number system. The above form of general expressi on
i s true onl y for posi ti onal number system.
I t i s I ndi a that gave thi s posi ti onal method of expressi ng any number usi ng ten symbol s,
each symbol recei vi ng a val ue of posi ti on as wel l as an absol ute val ue. I t was a profound and
i mportant i dea. I ts meri t has been appreci ated by a famous mathemati ci an Marqui s de Lapl ace.
2.3 BINARY NUMBER (OR BASE-2) SYSTEM
The base (or radi x) of the bi nary number system i s 2. I t uses onl y two di gi ts, 0 and 1.
I n short a bi nary di gi t i s cal l ed a bi t. The stori ng or computi ng el ectroni c el ements of a
computer have onl y two stabl e states. The output of such an el ement at any ti me i s ei ther
HI GH (5 vol ts) or LOW (0 vol t). These are the onl y two stabl e states. There i s no other stabl e
state. These stabl e states can be represented by 1 and 0 respecti vel y, that i s HI GH i s
represented by 1 and LOW by 0. Due to thi s very l i mi tati on a computer can understand
i nformati on composed of onl y 0s and 1s. So al l computers perform thei r i nternal operati ons
and mani pul ati ons on bi nary di gi ts. For the conveni ence of the users (programmers) they are
al l owed to use data and other i nformati on i n the form of deci mal di gi ts, usual al phabets and
speci al symbol s. Thi s i nformati on i s converted to bi nary codes wi thi n the computer as the
computer operates on bi nary bi ts. Thus we see that the knowl edge of the bi nary number
system i s needed for those who want to understand the operati ng pri nci pl e of a computer. I t
i s not requi red by those who have to si mpl y use a computer for thei r work.
I n the deci mal number system there i s no di ffi cul ty i n representi ng numbers upto 9. But
there i s no symbol or di gi t to represent ten and therefore, i t i s represented by 10. I t i s si mpl y
a posi ti onal techni que. Agai n, after 99 we have to represent hundred and uti l i zi ng posi ti onal
techni que i t i s wri tten as 100. I n the bi nary number system zero i s represented by 0 and one
by 1. There i s no di gi t i n the bi nary number system to represent two. Therefore, usi ng
posi ti onal techni que i t i s wri tten as 10. Three i s wri tten as 11. Agai n four i s represented by
100. I n thi s way uti l i zi ng posi ti onal techni que we proceed further. Thus i t i s seen that a
bi nary number becomes very l ong and cumbersome. The wei ght of each bi nary bi t of a bi nary
number depends on i ts rel ati ve posi ti on wi thi n the number. I t has been expl ai ned by the
fol l owi ng exampl e.
Example. Take the bi nary number 1101 as an exampl e to expl ai n the wei ght of each bi t
of the number.
1101 (Bi nary Number) = 1 2
3
+ 1 2
2
+ 0 2
1
+ 1 2
0
= 8 + 4 + 0 + 1 = 13 (Deci mal Number)
The wei ght of each bi t of a bi nary number depends on i ts rel ati ve posi ti on wi thi n the
number as expl ai ned bel ow:
The wei ght of the 1st bi t of the bi nary number from the ri ght hand si de = 1st bi t 2
0
.
The wei ght of the 2nd bi t of the number from the ri ght hand si de = 2nd bi t 2
1
.
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The wei ght of the 3rd bi t of the number from the ri ght hand si de = 3rd bi t 2
2
.
The wei ght of the 4th bi t of the number from the ri ght hand si de = 4th bi t 2
3
.
The above expressi ons can be wri tten i n the form of a general expressi on gi ven bel ow.
The wei ght of the nth bi t of the number from the ri ght hand si de
= nth bi t 2
n1
= nth bi t (Base)
n1
.
I t i s seen that thi s rul e for a bi nary number i s same as that for a deci mal number. The
above rul e hol ds good for any other posi ti onal number system. The wei ght of a di gi t i n any
posi ti onal number system depends on i ts rel ati ve posi ti on wi thi n the number and the base
of the number system. Tabl e 2.1 shows bi nary equi val ent of deci mal numbers.
Table 2.1. Binary Equivalent of Decimal Numbers
Decimal Number Binary Equivalent Decimal Number Binary Equivalent
0 0 11 1011
1 1 12 1100
2 10 13 1101
3 11 14 1110
4 100 15 1111
5 101 16 10000
6 110 31 11111
7 111 32 100000
8 1000 63 111111
9 1001 64 1000000
10 1010 128 10000000
2.4 CONVERSION OF A BINARY NUMBER TO DECIMAL NUMBER
To convert a bi nary number to i ts deci mal equi val ent we use the fol l owi ng expressi on:
The wei ght of the nth bi t of the number from the ri ght hand si de = nth bi t 2
n1
.
Fi rst we mark the bi t posi ti on and then we gi ve the wei ght of each bi t of the number
dependi ng on i ts posi ti on. The sum of the wei ghts of al l bi ts gi ves the equi val ent number. The
fol l owi ng exampl e i l l ustrates the process.
Example 1. Convert the bi nary number 10 to i ts deci mal equi val ent.
The fi rst bi t counti ng from the ri ght hand si de = 0
I ts wei ght = 0 2
11
= 0 2
0
The 2nd bi t from the ri ght hand si de = 1
I ts wei ght 1 2
21
= 1 2
1
.
The deci mal equi val ent = 1 2
1
+ 0 2
0
= 2 + 0 = 2
Example 2. Convert the bi nary number 101 to i ts deci mal equi val ent.
Fi rst we can wri te the bi nary number i n the spread form and then show the bi t posi ti on
as shown bel ow.
2.4 COMPUTER FUNDAMENTALS
The bi nary number i n the spread form = 1 0 1
Bi t posi ti on from ri ght hand si de: 3rd 2nd 1st
The wei ght of each bi t i s assi gned and added together to gi ve the deci mal equi val ent.
101 (Bi nary number) = 1 2
2
+ 0 2
1
+ 1 2
0
= 4 + 0 + 1
= 5 (Deci mal Number).
Example 3. Convert the bi nary number 1010 to i ts deci mal equi val ent.
The bi nary number i n the spread form = 1 0 1 0
Bi t posi ti on from the ri ght hand si de: 4th 3rd 2nd 1st
1010 (Bi nary Number) = 1 2
3
+ 0 2
2
+ 1 2
1
+ 0 2
0
.
= 8 + 0 + 2 + 0
= 10 (Deci mal Number).
Example 4. Convert the bi nary number 11001 to i ts deci mal equi val ent.
The bi nary number i n the spread form = 1 1 0 0 1
Bi t posi ti on from the ri ght hand si de: 5th 4th 3rd 2nd 1st
11001 (Bi nary Number) = 1 2
4
+ 1 2
3
+ 0 2
2
+ 0 2
1
+ 1 2
0
= 16 + 8 + 0 + 0 + 1
= 25 (Deci mal Number).
To i ndi cate the base of a number the fol l owi ng techni que can be used:
(25)
10
= (11001)
2
or 25
10
= 11001
2
The suffi x 10 i ndi cates that the number 25 i s a deci mal number.
The suffi x 2 i ndi cates that the number 11001 i s a bi nary number.
2.5 CONVERSION OF A DECIMAL NUMBER TO A BINARY NUMBER
I n a deci mal number the 1st posi ti on from the ri ght hand si de i s for 1s, 2nd for 10s, 3rd
for 100s, 4th for 1000s and so on. Si mi l arl y, i n a bi nary number the 1st posi ti on from ri ght
hand si de i s for 1, 2nd for 2, 3rd for 4, 4th for 8, 5th for 16 and so on. Thi s fact i s uti l i zed
for the conversi on of a deci mal number to i ts bi nary equi val ent. A method i s to be devel oped
to determi ne whi ch mul ti pl es of 2 are present i n a gi ven deci mal number. For exampl e, the
deci mal number 13 i s equal to (8 + 4 + 1). I n other words i t has one 8, one 4 and a 1. I t does
not have any 2. Therefore, i ts bi nary equi val ent i s 1101. Based on thi s concept, for the
conversi on of a deci mal number to bi nary number, the deci mal number i s di vi ded by 2
successi vel y. The quoti ent and remai nder are noted down at each stage. The quoti ent of one
stage i s di vi ded by 2 at the next stage. The process i s repeated unti l the quoti ent becomes
zero. The bi nary number equi val ent to the deci mal number i s gi ven by the fol l owi ng expressi on.
Bi nary Number = R
k
R
k1
R
k2
... R
3
R
2
R
1
where R
1
, R
2
,... R
k
are the remai nders at 1st, 2nd,... and kth stage respecti vel y.
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Example 1. Convert the deci mal number 41 to i ts bi nary equi val ent.
Quotient Remainder Remark
41 2 = 20 , 1 (LSB) There are 20 twos and one 1.
20 2 = 10 , 0 There are 10 fours and no 2.
Thi s i s equi val ent to di vi di ng
by 4.
10 2 = 5 , 0 There are 5 ei ghts and no 4.
Equi val ent to di vi di ng by 8.
5 2 = 2 , 1 There are two 16s and one 8.
Equi val ent to di vi di ng by 16.
2 2 = 1 , 0 There i s one 32 and no 16.
Equi val ent to di vi di ng by 32.
1 2 = 0 , 1 (MSB) There i s no 64 and one 32.
Equi val ent to di vi di ng by 64.
Therefore, 41 (Deci mal Number) = 101001 (Bi nary Number). The fi rst remai nder i s the
l east si gni fi cant bi t (LSB) and the l ast remai nder the most si gni fi cant bi t (MSB).
Example 2. Convert the deci mal number 73 to bi nary.
Quotient Remainder
73 2 = 36 , 1 (LSB)
36 2 = 18 , 0
18 2 = 9 , 0
9 2 = 4 , 1
4 2 = 2 , 0
2 2 = 1 , 0
1 2 = 0 , 1 (MSB)
The deci mal number 73 = 1001001 (Bi nary Number).
Checki ng of the answer.
The deci mal equi val ent of the above bi nary number i s gi ven by
1001001 = 1 2
6
+ 0 2
5
+ 0 2
4
+ 1 2
3
+ 0 2
2
+ 0 2
1
+ 1 2
0
= 64 + 0 + 0 + 8 + 0 + 0 + 1 = 73 (Deci mal Number)
Example 3. Convert the deci mal number 153 to bi nary.
Quotient Remainder
153 2 = 76 , 1 (LSB)
76 2 = 38 , 0
38 2 = 19 , 0
19 2 = 9 , 1
9 2 = 4 , 1
4 2 = 2 , 0
2.6 COMPUTER FUNDAMENTALS
2 2 = 1 , 0
1 2 = 0 , 1 (MSB)
153 (Deci mal Number) = 10011001 (Bi nary Number).
Checki ng of the answer.
10011001 = 1 2
7
+ 0 2
6
+ 0 2
5
+ 1 2
4
+ 1 2
3
+ 0 2
2
+ 0 2
1
+ 1 2
0
= 128 + 0 + 0 + 16 + 8 + 0 + 0 + 1
= 153 (Deci mal Number).
2.6 ADDITION OF BINARY NUMBERS
I n the bi nary number system 1 + 0 = 1. When 1 i s added to 1, the sum i s 0 wi th a carry
1. I f the sum i s wri tten upto 2 bi ts, i t i s equal to 10 (2 deci mal ). The Tabl e 2.2 shows the
rul es for bi nary addi ti on.
Table 2.2 Binary Addition
A B A +B
0 0 0
0 1 1
1 0 1
1 1 1 0

Carry
When 1 i s added to 1, the sum i s 0 wi th a carry 1. Thi s carry i s added to the sum of
the adjacent bi ts.
Example 1
1001 (9 deci mal number)
+ 0101 (5 deci mal number)
1110 (14 deci mal number)
Example 2
0111 (7 deci mal number)
+ 0011 (3 deci mal number)
1010 (10 deci mal number)
Example 3
1010 (10 deci mal number)
+ 1101 (13 deci mal number)
10111 (23 deci mal number)

Carry
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2.7 BINARY SUBTRACTION
The fol l owi ng exampl es wi l l i l l ustrate bi nary subtracti on.
Example 1
Borrow

1110 (14 deci mal number)
0101 ( 5 deci mal number)
1001 (9 deci mal number)
Example 2
1010 (10 deci mal number)
0101 ( 5 deci mal number)
0101 (5 deci mal number)
Example 3
1010 (10 deci mal number)
0011 ( 3 deci mal number)
0111 (7 deci mal number)
Example 4
1101 (13 deci mal number)
0111 ( 7 deci mal number)
0110 (6 deci mal number)
I n the above exampl es smal l er number has been subtracted from a l arger number. Let
us see what happens i f a l arger number i s subtracted from a smal l er number.
Example 1
Borrow

0101 (5 deci mal number)


0111 ( 7 deci mal number)
1110 ( 2 deci mal number)
The resul t i s not a si mpl e representati on of 2 i .e., 0010. The resul t i s the 2s
compl ement of 2. Thi s wi l l be expl ai ned i n the next secti on.
Example 2
Borrow

0111 (7 deci mal number)
1000 ( 8 deci mal number)
1111 (1 deci mal number)
The resul t i s 2s compl ement of 1.
2.8 COMPUTER FUNDAMENTALS
2.8 USE OF COMPLEMENTS TO REPRESENT NEGATIVE NUMBERS
Most of the computers now perform subtracti on usi ng compl emented number. Thi s i s
economi cal because subtracti on can al so be performed usi ng the same el ectroni c ci rcui try
whi ch i s used for addi ti on. I n the bi nary number system there are two types of compl ements,
1s compl ement and 2s compl ement. To represent a negati ve bi nary number 2s compl ement
i s most wi del y used at present. To understand 1s and 2s compl ement i n the bi nary number
system one shoul d fi rst understand 9s and 10s compl ements i n the deci mal number system.
2.8.1 9s Complement
To form the 9s compl ement of deci mal number each di gi t of a deci mal number i s
subtracted from 9. The resul t so obtai ned i s known as 9s compl ement of the number. For
exampl e, the 9s compl ement of 37 i s (99 37) = 62. The 9s compl ement of 235 i s (999 235)
= 764.
2.8.2 10s Complement
The 10s compl ement of a deci mal number i s equal to the 9s compl ement of the
number pl us 1.
The 10s compl ement of a deci mal number = I ts 9s compl ement + 1.
The 10s compl ement of 37 = 62 + 1 = 63.
The 10s compl ement of 235 = 764 + 1 = 765.
Now l et us exami ne the sum of a deci mal number and i ts 10s compl ement.
Example 1
37 (deci mal number)
+ 63 (i ts 10s compl ement)
1 00
I gnore carry
I n the above exampl e the gi ven deci mal number i s of two di gi ts. I f the sum of the
number and i ts 10s compl ement i s consi dered onl y upto two di gi ts, the sum i s equal to zero.
I n other words the sum of a number and i ts 10s compl ement i s equal to zero i f the carry
of the l ast stage i s negl ected.
Example 2
235 (deci mal number)
+ 765 (i ts 10s compl ement)
1 000
I gnore carry
The deci mal number 235 i s of three di gi ts. I f the sum of a deci mal number and i ts 10s
compl ement i s consi dered onl y upto three di gi ts, the sum i s equal to zero. Therefore, i t i s
seen that the 10s compl ement represents the negati ve val ue of the number.
The 10s compl ement of a deci mal number = deci mal number.
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2.8.3 Addition in 10s Complement System
I f 10s compl ement of a number i s added to any number i t i s equi val ent to i ts subtracti on
from that number. 10s compl ement subtracti on i s used i n computers whi ch empl oy BCD
codes for the representati on of deci mal numbers.
Example 1. Add 86 and ( 21).
The 9s compl ement of 21 = 78
The 10s compl ement of 21 = 78 + 1 = 79
86
+ 79 (10s compl ement of 21)
1 65
I gnore carry
I f the carry of the l ast stage i s dropped, the resul t i s correct.
Example 2. Add 59 and ( 84)
The 9s compl ement of 84 = 15
The 10s compl ement of 84 = 15 + 1 = 16
59
+ 16 (10s compl ement of 84)
75 (10s compl ement of 25)
There i s no carry and the resul t i s i n 10s compl ement. I t i s the 10s compl ement of 25.
To get the correct resul t take 9s compl ement of the resul t, add 1 and put a si gn before
i t.
The 9s compl ement of 75 = 24
The 10s compl ement of 75 = 24 + 1 = 25
Resul t = 25, whi ch i s the correct resul t.
Example 3. Add ( 26) and ( 43)
The 9s compl ement of 26 = 73
The 10s compl ement of 26 = 73 + 1 = 74
The 9s compl ement of 43 = 56
The 10s compl ement of 43 = 56 + 1 = 57
74
+ 57
1 31
I gnore carry
The 10s compl ement of 31 = 69. The correct resul t i s 69.
Example 4. Add 34 and 58
34
58
92
2.10 COMPUTER FUNDAMENTALS
As the both numbers are posi ti ve, they are si mpl y added. The 10s compl ement i s not
requi red. The resul t i s posi ti ve and correct. There i s no carry at the l ast stage.
Conclusion
Whether the resul t i s posi ti ve or negati ve the carry of the l ast stage i s to be dropped.
I f the resul t i s posi ti ve i t i s correct as usual . I f the resul t i s negati ve, i t i s i n 10s compl ement.
Computer can represent si gned numbers, and hence recogni ze whether the resul t i s posi ti ve
or negati ve. I f the resul t negati ve, computer understands that i t i s i n the compl emented
form. So i t converts i t to get the resul t i n the usual form. Thi s has been expl ai ned whi l e
di scussi ng 2s compl ement whi ch i s si mi l ar to 10s compl ement i n the deci mal system.
2.8.4 1s Complement
The 1s compl ement i n the bi nary number system i s si mi l ar to 9s compl ement i n the
deci mal system. To obtai n 1s compl ement of a bi nary number each bi t of the bi nary number
i s subtracted from 1. For exampl e, the 1s compl ement of the bi nary number 010 i s 101. The
1s compl ement of 1110 i s 0001. Thus 1s compl ement of a bi nary number may be formed by
si mpl y changi ng each 1 to a 0 and each 0 to a 1.
Example 1. Fi nd 1s compl ement of the bi nary number 101100.
The 1s compl ement of 101100 = 010011
Example 2. Fi nd 1s compl ement of the bi nary number 0000.
The 1s compl ement 0000 = 1111
Example 3. Fi nd 1s compl ement of the bi nary number 1111.
The 1s compl ement of 1111 = 0000
2.8.5 2s Complement
The 2s compl ement i n the bi nary number system i s si mi l ar to 10s compl ement
i n the deci mal number system. The 2s compl ement of a bi nary number i s equal
to the 1s compl ement of the number pl us one.
The 2s compl ement of a bi nary number = I ts 1s compl ement + 1.
The 2s compl ement of 0101 = 1010 + 1 = 1011.
Example 1. Fi nd 2s compl ement of the bi nary number 101100.
The 2s compl ement of 101100 = 010011 + 1 =010100
Example 2. Fi nd 2s compl ement of the bi nary number 0000.
The 2s compl ement of 0000 = 1111 + 1 = 10000
Example 3. Fi nd 2s compl ement of the bi nary number 111.
The 2s compl ement of 111 = 000 + 1 = 001
Let us exami ne the sum of a bi nary number and i ts 2s compl ement.
Example 1. Add the bi nary number 1100 and i ts 2s compl ement.
The bi nary number = 1100
I ts 1s compl ement = 0011
I ts 2s compl ement = 0011 + 1 = 0100
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The number + i ts 2s compl ement = 1100
+ 0100
1 0000
I gnore carry
I f the carry of the l ast stage i s negl ected the sum of a bi nary number and i ts 2s
compl ement i s equal to zero. I n the above exampl e the bi nary number i s of 4 bi ts. I f a 4-bi t
processor i s used and the l ast carry i s negl ected, the sum wi l l be consi dered onl y upto 4 bi ts.
For an 8-bi t processor the bi nary number and i ts 2s compl ement i s wri tten upto 8 bi ts
as shown bel ow i n the exampl es 2 and 3.
Example 2. Add the bi nary number 1011 and i ts 2s compl ement.
The bi nary number = 00001011
I ts 1s compl ement = 11110100
I ts 2s compl ement = 11110100 + 1
= 11110101
The gi ven bi nary number = 00001011
+ I ts 2s compl ement + 11110101
1 00000000
I gnore carry
The sum onl y upto 8 bi ts i s equal to zero.
Example 3. Add 5 and ( 5).
5 (deci mal ) = 00000101 (bi nary)
5 = I ts 2s compl ement = 11111010 + 1 = 11111011
5 = 0 0 0 0 0 1 0 1
+ ( 5) + 1 1 1 1 1 0 1 1 (+ 2s compl ement of 5)
1 0 0 0 0 0 0 0 0
I gnore carry
I f the sum i s consi dered onl y upto 8 bi ts, i t i s equal to zero.
2.8.6 Binary Subtraction Using 2s Complement
The addi ti on of 2s compl ement of a number i s equi val ent to i ts subtracti on. Thi s wi l l
be cl ear from the fol l owi ng exampl e.
Example 1. Subtract 2 from 6.
Si mpl e bi nary subtacti on
0110 (6 deci mal )
0010 ( 2 deci mal )
0100 (4 deci mal )
Subtraction using 2s complement
1s compl ement of 0010 (2 deci mal ) = 1101
2s compl ement of 0010 (2 deci mal ) = 1101 + 1 = 1110
2.12 COMPUTER FUNDAMENTALS
0110 (6 deci mal )
+ 1110 (+ 2s compl ement of 2)
1 0100 (4 deci mal )
I gnore carry
The carry of the l ast stage i s to be negl ected i f we are usi ng 2s compl ement techni que.
Example 2. Substract 3 from 5
1s compl ement of 0011 (3 deci mal ) = 1100
2s compl ement of 0011 (3 deci mal ) = 1100 + 1
= 1101
0101 (5 deci mal )
+ 1101 (+ 2s compl ement of 3)
1 0010 (2 deci mal )
I gnore carry
The carry of the l ast stage i s negl ected.
2.8.7 Representation of Signed and Unsigned Numbers
I n the deci mal system we put + or si gn before a number to represent i ts si gn. I n
computer such notati on can not be empl oyed and therefore, a di fferent techni que has been
adopted. To represent posi ti ve si gn a 0 i s pl aced before the bi nary number. For exampl e +
9 i s represented by 0 1001. To represent negati ve number a 1 i s pl aced before the number.
For exampl e, 9 wi l l be represented as 1 1001. There i s onl y one way to represent a posi ti ve
number. But there are three di fferent ways to represent a negati ve number. These are:
(1) Si gned-Magni tude Representati on
(2) Si gned-1s Compl ement Representati on
(3) Si gned-2s Compl ement Representati on
The representati on of 9 i n above three representati ons are shown bel ow:
Si gned-magni tude representati on 1 1001
Si gned-1s compl ement representati on 1 0110
Si gned-2s compl ement representati on 1 0111
Hence, 9 i s represented by 4 bi nary bi ts and a separate bi t i s used to represent si gn. I n
a computer the MSB can be used to represent the si gn of the number. For exampl e an 8-bi t
computer wi l l represent 9 as shown bel ow. 7 bi ts are used to represent the number and
the MSB i s used to represent the si gn of the number.
Si gned-magni tude representati on 1 0001001
Si gned-1s compl ement representati on 1 1110110
Si gned-2s compl ement representati on 1 1110111
When al l the bi ts of the computer word are used to represent the number and no bi t
i s used for si gn representati on i t wi l l be cal l ed unsi gned representati on of the number.
NUMBER SYSTEM 2.13
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2.8.8 Addition in Signed 2s Complement
The 2s compl ement i n the bi nary number system i s si mi l ar to 10s compl ement i n the
deci mal system. We have al ready di scussed the rul es for addi ti on i n 10s compl ement. Those
rul es al so hol d good for 2s compl ement. A si gn bi t adjacent to the most si gni fi cant bi t i s used
to di sti ngui sh a posi ti ve number from a negati ve number. A 1 i n the si gn bi t i s used to
represent a negati ve number and a 0 i n the si gn bi t a posi ti ve number. The use of si gn bi t
cl earl y i ndi cates whether the resul t i s posi ti ve or negati ve. The fol l owi ng exampl es wi l l show
the di fferent si tuati ons i n 2s compl ement addi ti on.
Example 1. Addi ti on of two posi ti ve numbers.
Add 5 and 3.
Normal Notation Computer Notation
+ 0101 (+ 5 deci mal ) 0 0101 (+ 5 deci mal wi th si gn bi t)
+ 0011 (+ 3 deci mal ) 0 0011 (+ 3 deci mal wi th si gn bi t)
+ 1000 (+ 8 deci mal ) 0 1000 (+ 8 deci mal )
I n computer representati on si gn bi t has al so been i ncl uded. The fi rst bi t from the l eft
(or fi fth bi t from the ri ght) i s the si gn bi t. The addi ti on i s al so performed on the si gn bi t. I n
the above exampl e the sum 1000 i s correct i n the bi nary form and i t i s equal to 8 deci mal .
A 0 i n the si gn bi t i ndi cates that the resul t i s posi ti ve. There i s no carry at the l ast stage.
Example 2. Addi ti on of a posi ti ve and a negati ve number, the posi ti ve number bei ng
greater than the negati ve number.
Add 9 and (4).
The 1s compl ement of 0100 (4 deci mal ) = 1011
The 2s compl ement of 0100 = 1011 + 1 = 1100
Normal Notation Computer Notation
+ 1001 (+ 9 deci mal ) 0 1001 (+ 9 deci mal wi th si gn bi t)
0100 ( 4 deci mal ) 1 1100 (2s deci mal of 4 wi th si gn bi t)
+ 0101 (5 deci mal ) 1 0 0101 (+ 5 deci mal )
Negl ect carry
The sum 0101 i s correct i n the bi nary form and equal to 5 deci mal . The si gn bi t 0
i ndi cates the sum i s posi ti ve. There i s carry at the l ast stage. The carry i s to be dropped.
Example 3. Addi ti on of a posi ti ve and negati ve number, the negati ve number bei ng
greater than the posi ti ve number.
Add (9) and 3.
The 1s compl ement of 1001 (9 deci mal ) = 0110
The 2s compl ement of 1001 = 0110 + 1 = 0111
9 1 0111 (2s compl ement of 9 wi th si gn bi t)
+ 3 0 0011 (+ 3 wi th si gn bi t)
6 1 1010 (2s compl ement of 6 wi th si gn bi t)
The sum i s negati ve as i ndi cated by the si gn bi t. I t i s i n 2s compl ement. There i s no
carry at the l ast stage.
2.14 COMPUTER FUNDAMENTALS
When the resul t i s negati ve and i n 2s compl ement the fol l owi ng procedure can be
adopted to get i t i s the correct form.
Take 1s compl ement of the resul t, add 1 and put a si gn before i t. I n the above exampl e
the resul t i n 2s compl ement i s 1010. The correct resul t wi l l be:
The 1s compl ement of 1010 = 0101
+ 1
0110 ( 6 deci mal )
Example 4. Add ( 12) and ( 2).
The 1s compl ement of 1100 (12 deci mal ) = 0011
The 2s compl ement of 1100 = 0011 + 1
= 0100
The 1s compl ement of 0010 (2 deci mal ) = 1101
The 2s compl ement of 0010 = 1101 + 1
= 1110
Computer Notation
12 1 0100 (2s compl ement of 12 wi th si gn bi t)
2 1 1110 (2s compl ement of 2 wi th si gn bi t)
14 1 1 0010 (2s compl ement of 14 wi th si gn bi t)
carry = 1
The sum i s negati ve and i t i s i n 2s compl ement. There i s a carry through the si gn bi t.
I t i s to be dropped.
The above resul t i s i n 2s compl ement. The correct resul t can be obtai ned as fol l ows:
2s compl ement of 0010 (resul t) = 1110
= 14 (deci mal )
Conclusion
The carry of the l ast stage i s to be dropped. When the sum i s posi ti ve, i t i s i n the correct
bi nary form. When the sum i s negati ve i t i s i n 2s compl ement. The si gn bi t i ndi cates whether
the sum i s posi ti ve or negati ve. When the sum i s i n 2s compl ement, i t wi l l be converted to
the correct form for di spl ay by the computer very easi l y. Thi s i s true onl y when there i n no
overfl ow. The case of overfl ow has been di scussed l ater on i n thi s chapter i n Sec. 2.19.
I n the above exampl es we have taken a separate si gn bi t. I n a computer the most si gni fi cant
bi t may be reserved for si gn bi t; and the rest of the bi ts of the data word wi l l represent the
magni tude of a number. Consi der an 8-bi t computer. The magni tude of the number i s represented
by 7 bi ts. The MSB represents the si gn of the number. I f the si gn bi t i s 0, the number, i s posi ti ve,
I f the si gn bi t i s 1, the number i s negati ve. The negati ve numbers are represented i n 2s
compl emented. The fol l owi ng exampl e wi l l i l l ustrate the addi ti on of si gned bi nary numbers.
Example 5. Add + 14 and + 9
+ 14 00001110
+ 9 00001001
+ 23 00010111
Si gn bi t i s 0, so the sum i s posi ti ve.
NUMBER SYSTEM 2.15
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Example 6. Add + 14 and ( 9).
+ 14 00001110
9 11110111 (2s compl ement of 9 wi th si gn bi t).
+ 5 100000101 (+ 5 deci mal ).
Si gn bi t i s 0, so the resul t i s posi ti ve.
Carry = 1, i t i s negl ected.
Example 7. Add ( 14) and + 9.
14 11110010 (2s compl ement of 14 wi th si gn bi t).
+ 9 00001001
5 11111011 (2s compl ement of 5 wi th si gn bi t).
Si gn bi t i s 1, so the resul t i s negati ve.
00000100 1s compl ement of the resul t.
+ 1 Add 1
00000101(5 deci mal ).
Prefi x i s to show the resul t i n usual standard bi nary form.
Example 8. Add ( 14) and ( 9).
14 11110010 (2s compl ement of 14 wi th si gn bi t).
9 11110111 (2s compl ement of 9 wi th si gn bi t).
23 111101001 (2s compl ement of 23 wi th si gn bi t).
Si gn bi t i s 1, so the resul t i s negati ve.
Carry i s 1, i t i s negl ected.
00010110 1s compl ement of the resul t.
+ 1 Add 1
00010111 ( 23 deci mal ).
Prefi x i s to show the correct resul t i n usual standard bi nary form.
The above exampl es show that the addi ti on and subtacti on i n 2s compl ement i s very
si mpl e. The si gn bi t cl earl y i ndi cates whether the resul t i s posi ti ve or negati ve. I f i t i s
negati ve i t means that i t i s i n 2s compl ement. Then the computer converts i t to a standard
deci mal form to show i t on the screen. The case of overfl ow i s di scussed the Sec. 2.19.
2.9 CONVERSION OF A BINARY FRACTION TO A DECIMAL FRACTION
I n the deci mal number system the wei ghts of the di gi ts whi ch come after the deci mal
poi nt, are represented as:
0.635 = 0.6 + 0.03 + 0.005
= 6
1
10
3
1
100
5
1
1000
+ +
= 6 10
1
+ 3 10
2
+ 5 10
3
2.16 COMPUTER FUNDAMENTALS
Si mi l arl y, i n the bi nary number system the wei ghts of the bi nary bi ts whi ch come after
the bi nary poi nt, can be expressed as:
0.1101 = 1 2
1
+ 1 2
2
+ 0 2
3
+ 1 2
4
= 1
1
2
1
1
4
0
1
8
1
1
16
+ + +
= 0.5 + 0.25 + 0 + 0.0625
= 0.8125 (deci mal )
Example 1. Convert the bi nary fracti on 0.10111 to deci mal fracti on.
0.10111 = 1 2
1
+ 0 2
2
+ 1 2
3
+ 1 2
4
+ 1 2
5
= 1
1
2
0
1
4
1
1
8
1
1
16
1
1
32
+ + + +
= 0.5 + 0 + 0.125 + 0.0625 + 0.03125
= 0.71875 (deci mal ).
Example 2. Convert the bi nary real number 1101.1010 to a deci mal real number.
A bi nary real number consi sts of two parts an i nteger and a fracti on. The deci mal
equi val ent i s determi ned for both i nteger as wel l as fracti on and these are added to gi ve the
equi val ent deci mal real number.
1101.1010 = (1 2
3
+ 1 2
2
+ 0 2
1
+ 1 2
0
) + (1 2
1
+ 0 2
2
+ 1 2
3
+ 0 2
4
)
= (8 + 4 + 0 + 1) + (0.5 + 0 + 0.125 + 0)
= 13.625 (deci mal )
2.10 CONVERSION OF A DECIMAL FRACTION TO A BINARY FRACTION
To convert a deci mal fracti on to i ts bi nary equi val ent a techni que of successi ve mul ti pl i -
cati on by 2 i s used. The i nteger part i s noted down after the mul ti pl i cati on by 2 at each stage
and the remai nder new fracti on i s used for the mul ti pl i cati on by 2 at the next stage. The
fol l owi ng exampl e wi l l i l l ustrate the procedure.
Example 1. Convert the deci mal fracti on 0.8125 to an equi val ent bi nary fracti on.
Fraction Fraction 2 Remainder New Fraction Integer
0.8125 1.625 0.625 1 (MSB)
0.625 1.25 0.25 1
0.25 0.50 0.50 0
0.50 1.00 0.00 1 (LSB)
0.8125 (deci mal ) = 0.1101 (Bi nary)
Example 2. Convert the deci mal fracti on 0.635 to i ts bi nary equi val ent.
Fraction Fraction 2 Remainder New Fraction Integer
0.635 1.27 0.27 1 (MSB)
0.27 0.54 0.54 0
0.54 1.08 0.08 1
(Contd.)...
NUMBER SYSTEM 2.17
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0.08 0.16 0.16 0
0.16 0.32 0.32 0
0.32 0.64 0.64 0
0.64 1.28 0.28 1 (LSB)
. . . .
. . . .
. . . .
I n thi s exampl e i t i s seen that the fracti on has not become zero, and the process wi l l
conti nue further. For such a case an approxi mati on i s made. For thi s exampl e, we may take
the resul t up to 6th bi nary bi t after the bi nary poi nt.
0.635 (deci mal ) = 0.1010001 (bi nary)
Example 3. Convert the deci mal real number 12.625 to an equi val ent bi nary real number.
For the above deci mal real number the bi nary equi val ent i s obtai ned for both i nteger as
wel l as fracti on separatel y.
12 (deci mal ) i s fi rst converted to i ts bi nary equi val ent.
Quotient Remainder
12 2 = 6 0 (LSB)
6 2 = 3 0
3 2 = 1 1
1 2 = 0 1 (MSB)
12 (deci mal = 1100 (bi nary).
Then the deci mal fracti on 0.625 i s converted to i ts bi nary equi val ent.
Fraction 2 Fraction Remainder New Fraction Integer
0.625 1.25 0.25 1 (MSB)
0.25 0.50 0.50 0
0.50 1.00 0.00 1 (LSB)
0.625 (deci mal ) = 0.101 (bi nary).
Now addi ng the bi nary equi val ents of 12 and 0.625, we get
12.625 (deci mal ) = 1100.101 (bi nary)
2.11 BINARY CODED DECIMAL (BCD CODES)
The BCD i s the si mpl est bi nary code to represent a deci mal number. I n BCD code a
deci mal number i s represented by four bi nary bi ts. For exampl e, 3 i s represented by 0011.
I f a deci mal number consi sts of two or more than two di gi ts, each deci mal di gi t i s i ndi vi dual l y
represented by i ts 4-bi t bi nary equi val ent. For exampl e, 56 i s represented by 0101 0110.
Numbers are usual l y represented by some sort of bi nary codes. There i s a di fference
between a bi nary equi val ent of a deci mal number and the bi nary code of a deci mal number.
For exampl e, the bi nary equi val ent of the deci mal number 43 i s 101011, but i t i s represented
i n BCD code as 0100 0011.
2.18 COMPUTER FUNDAMENTALS
Tabl e 2.3 shows the standard BCD codes for one-di gi t and two-di gi t deci mal numbers.
Table 2.3. Standard BCD Codes
Decimal Number Standard BCD code
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 0001 0000
11 0001 0001
12 0001 0010
13 0001 0011
56 0101 0110
84 1000 0100
99 1001 1001
I n the standard BCD code the wei ghts of four bi nary bi ts whi ch represent an i ndi vi dual
di gi t i s 8, 4, 2, 1. At present modern computers perform subtracti on usi ng compl ements.
There i s di ffi cul ty i n formi ng compl ements when numbers are represented by standard
BCD. For exampl e, the 1s compl ement of 0010 (2 deci mal ) i s 110l (13 deci mal ) whi ch i s not
an acceptabl e BCD code i n thi s system. To overcome thi s di ffi cul ty other BCD codes such
as Excess-3 code; 2,4,2,1 code etc. have been used i n earl i er computers. I n excess-3 code
3 i s added to the i ndi vi dual di gi t of a deci mal number, then thei r bi nary equi val ents are
wri tten. For exampl e, 5 (deci mal ) = 1000 (8 deci mal ) i n excess-3 code. 253 (deci mal ) i n
excess-3 code wi l l be 0101 1000 0110. The drawback of thi s code i s that i t i s not a wei ghted
code, that i s the sum of wei ghts of bi nary bi ts i s not equal to the correspondi ng deci mal
di gi t.
Another BCD code i s 2, 4, 2, 1 code. I t i s a wei ghted code and i t has compl ements. For
exampl e, 5 i s 0101; 9 = 1111, 7 = 1101.
BCD codes are used where the deci mal i nformati on i s di rectl y (i n coded form) transferred
i nto or out of a di gi tal system. El ectroni c cal cul ators, di gi tal vol tmeters, frequency counters,
el ectroni c counters, di gi tal cl ocks etc. work wi th BCD numbers. BCD codes have al so been
used i n earl y computers. Modern computers do not use BCD numbers as they have to process
names and other nonnumeri c data.
I n addi ti on to di ffi cul ty i n formi ng compl ements for bi nary subtracti on there i s al so
di ffi cul ty i n performi ng addi ti on i n standard BCD. I f the resul t l i es i n the range 10 to 15 or
i f there i s carry from the 4th bi t of any BCD di gi t, a correcti on of + 6 has to be made to obtai n
the correct resul t. Thi s wi l l be cl ear from the fol l owi ng exampl e:
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Example 1. Add 8 and 5.
BCD
8 1000
+ 5 0101
13 1101 I ncorrect BCD
+ 0110 Add 6
00010011 Correct BCD 13
Example 2. Add 8 and 9.
BCD
8 1000
+ 9 1001
17 00010001 I ncorrect BCD
+ 0110 Add 6
00010111 Correct BCD 17
2.12 HEXADECIMAL NUMBER SYSTEM
The hexadeci mal number system i s now extensi vel y used i n computer i ndustry. I ts radi x
(base) i s 16. I ts di gi ts from 0 to 9 are same as those used by deci mal number system. I n the
hexadeci mal number system 10 i s represented by A, 11 by B, 12 by C, 13 by D, 14 by E and
15 by F. The deci mal number 16 i s represented by 10, 17 by 11 and so on.
A hexadeci mal di gi t i s represented by four bi nary bi ts. For exampl e, 5 i s represented by
0101, A by 1010 and D by 1101. I f a hexadeci mal number consi sts of two or more than two
di gi ts, each di gi t i s represented i ndi vi dual l y by four bi nary bi ts. For exampl e, 86 i s repre-
sented by 1000 0110, 5E by 0101 1110, 3B7 by 0011 1011 0111. Tabl e 2.4 shows hexadeci mal
numbers and thei r bi nary representati ons. The bi nary representati on of a hexadeci mal num-
ber i s al so cal l ed bi nary coded hexadeci mal number. The reason for usi ng 4 bi nary bi ts to
represent a hexadeci mal di gi t i s that the l argest hexadeci mal di gi t F requi res onl y 4 bi nary
bi ts for i ts representati on.
Let us exami ne the bi nary equi val ent of a deci mal number and i ts hexadeci mal repre-
sentati on. The bi nary equi val ent of the deci mal number 94 i s 1011110. The hexadeci mal
equi val ent of 94 (deci mal ) i s 5E. The bi nary representati on of 5E i s 0101 1110. I f we negl ect
the l eadi ng zero, that i s zero i n MSB posi ti on, both bi nary representati ons are i denti cal .
Table 2.4. Hexadeci mal Numbers and thei r Bi nary Representati ons
Decimal Number Hexadecimal Number Binary Coded
Hexadecimal Number
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
(Contd.)...
2.20 COMPUTER FUNDAMENTALS
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111
16 10 0001 0000
37 25 0010 0101
43 2B 0010 1011
94 5E 0101 1110
223 DF 1101 1111
255 FF 1111 1111
2.12.1 Hexadecimal Versus BCD
From Tabl e 2.4 i t i s cl ear that the hexadeci mal system uti l i zes the ful l capaci ty of four
bi nary bi ts, whereas BCD codes do not uti l i ze the same. The BCD codes do not uti l i ze the
bi nary codes from 1010 to 1111. I n the hexadeci mal system an 8-bi t word can represent up
to FF, that i s 11111111 (255 deci mal ) whereas i n BCD onl y up to 10011001 (99 deci mal ). Hence
the hexadeci mal i s a compact form of representati on, and i t occupi es l ess memory space,
thereby reduci ng the hardware cost. The ari thmeti c operati ons are al so si mpl er i n hexadeci -
mal system.
When a computer gi ves hardware or software error i t may be requi red to see the
i nformati on stored i n the memory. The memory stores i nformati on i n bi nary form whi ch i s
very di ffi cul t to exami ne. Therefore, the stored i nformati on i s pri nted out i n hexadeci mal
form whi ch i s very compact and easy to exami ne. Computers whi ch work i n bi nary produce
memory dumps i n hexadeci mal as pri ntouts that are very compact. Li sti ngs are al so produced
i n hexadeci mal .
Usual l y, the i nput data and the resul t (output) are i n the deci mal form. Before a bi nary
processor (hexadeci mal or octal ) performs ari thmeti c operati ons the i nput data have to be
converted i nto bi nary form (hexadeci mal or octal ). Agai n resul ts whi ch are i n the bi nary form
are to be converted to deci mal form. The bi nary system wi l l be effi ci ent for smal l i nput-output
requi rements and a l arge number of computati ons. A processor worki ng wi th BCD wi l l be
effi ci ent i f l arge i nput-output requi rements are i nvol ved and smal l number of computati ons
are requi red. The computers usi ng BCD codes perform ari thmeti c operati ons di rectl y on
deci mal data (BCD codes) and el i mi nate the requi rement for conversi on to bi nary and back
to deci mal .
Many deci mal fracti ons do not have exact bi nary equi val ents. I n some busi ness comput-
ers deal i ng wi th accounti ng appl i cati ons preci se cal cul ati ons are desi red. Therefore, BCD may
be desi red for the exact representati on of deci mal numbers i ncl udi ng the di gi ts after deci mal
poi nts. But BCD ari thmeti c takes more ti me for executi on and hence i t i s sl ower than bi nary
NUMBER SYSTEM 2.21
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ari thmeti c. Thus the pri ce pai d for preci se deci mal fracti ons i s l ess effi ci ent use of memory
and sl ower processi ng.
Some computers and al l cal cul ators empl oy BCD codes. Most of the modern computers
use hexadeci mal system. Some l arge computers may have the hardware faci l i ty for ari thmeti c
cal cul ati ons wi th both bi nary (hex.) as wel l as BCD.
2.12.2 Conversion of a Hexadecimal Number to a Decimal Number
For the conversi on of a hexadeci mal number to an equi val ent deci mal number the
fol l owi ng wel l known expressi on for the wei ghts of di gi ts of the number wi l l be used:
The wei ght of nth di gi t of the number from the ri ght hand si de = nth di gi t (Base)
n1
.
The fol l owi ng exampl es wi l l i l l ustrate the procedure.
Example 1. Convert the hexadeci mal number 4B8 to i ts equi val ent deci mal number.
8 i s the 1st di gi t of the number from the ri ght hand si de, therefore, i ts wei ght i s
8 16
0
.
B i s the 2nd di gi t of the number from the ri ght hand si de, therefore, i ts wei ght i s
B l 6
1
.
4 i s the 3rd di gi t of the number from the ri ght hand si de, therefore, i ts wei ght i s
4 16
2
.
Therefore, 4B8 (hex.) = 4 16
2
+ B 16
1
+ 8 16
0
= 4 256 + 11 16 + 8 1
= 1024 + 176 + 8
= 1208 (deci mal ).
Example 2. Convert the hexadeci mal number 6E to i ts deci mal equi val ent.
6E (hex.) = 6 16
1
+ E 16
0
= 6 16 + 14 1
= 94 + 14
= 110 (deci mal ).
Example 3. Convert the hexadeci mal number 2B6D to i ts equi val ent deci mal number.
2B6D (hex.) = 2 16
3
+ B 16
2
+ 6 16
1
+ D 16
0
= 2 4096 + 11 256 + 6 16 + 13 1
= 8192 + 2816 + 96 + 13
= 11117 (deci mal ).
2.12.3 Conversion of a Hexadecimal Fraction to a Decimal Fraction
I n the hexadeci mal system the wei ghts of the hexadeci mal di gi ts after the hexadeci mal
poi nt are as fol l ows:
0.5A6B = 5 16
1
+ A 16
2
+ 6 16
3
+ B 16
4
= 0.3125 + 0.0390625 + 0.0014648437 + 0.00016784667
= 0.35319519037 (hexadeci mal ).
2.12.4 Conversion of a Decimal Number to a Hexadecimal Number
For the Conversi on of a deci mal number to an equi val ent hexadeci mal number, the
deci mal number i s di vi ded by 16 successi vel y.
2.22 COMPUTER FUNDAMENTALS
Example 1. Convert the deci mal number 67 to an equi val ent hexadeci mal number.
Quotient Remainder
67 16 = 4 , 3 (LSD)
4 16 = 0 , 4 (MSD)
The deci mal number 67 = 43 (hexadeci mal ).
Example 2. Convert the deci mal number 952 to i ts hexadeci mal equi val ent.
Quotient Remainder
952 16 = 59 , 8 (LSD)
59 16 = 3 , 11 = B
3 16 = 0 , 3 (MSD)
The deci mal number 952 = 3B8 (hexadeci mal ).
2.12.5 Conversion of a Decimal Fraction to a Hexadecimal Fraction
For the conversi on of deci mal fracti on to i ts equi val ent hexadeci mal fracti on the tech-
ni que of repeated mul ti pl i cati on by 16 i s used. The i nteger part i s noted down after each
mul ti pl i cati on and the new remai nder fracti on i s used for mul ti pl i cati on at the next stage.
Example. Convert the deci mal fracti on 0.62 to i ts equi val ent hexadeci mal fracti on.
Fraction Fraction 16 Remainder I nteger
0.62 9.92 0.92 9 (MSD)
0.92 14.72 0.72 14 = E
0.72 11.52 0.52 11 = B
0.52 8.32 0.32 8
0.32 5.12 0.12 5
0.12 1.92 0.92 1 (LSD)
The process wi l l further conti nue. Therefore, the resul t has been taken upto 6 pl aces of
hexadeci mal poi nt.
The deci mal fracti on 0.62 = 0.9EB851 (hex.) approxi matel y.
2.12.6 Conversion of a Binary Number to a Hexadecimal Number
The conversi on of bi nary number to hexadeci mal number uses a very si mpl e techni que.
The base of the hexadeci mal number system i s 16. To convert a bi nary number to hexadeci mal ,
4-bi t bi nary groups (each group contai ns 4 bi nary bi ts) are formed i n the bi nary number. After
formi ng the groups, each group of 4 bi nary bi ts i s converted to i ts hexadeci mal equi val ent.
Example 1. Convert the bi nary number 01101110 to i ts equi val ent hexadeci mal number.
(01101110)
2
= (0110) (1110)
= 6E (hex.).
Example 2. Convert the bi nary number 1101001101 to i ts equi val ent hexadeci mal .
The formati on of groups of 4 bi ts each i n an i nteger bi nary number i s made from ri ght
hand si de to l eft.
(1101001101)
2
= (11) (0100) (1101)
NUMBER SYSTEM 2.23
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I n the above expressi on we see that the group of the most si gni fi cant bi nary bi ts contai ns
onl y 2 bi nary bi ts. Thi s can be extended to 4 bi nary bi ts by addi ng zeros i n MSB posi ti ons.
I f MSBs are extended by addi ng zeros the number remai ns unaffected. Therefore, the gi ven
number may be grouped as fol l ows:
(1101001101)
2
= (0011) (0100) (1101)
= 34D (hex.).
Example 3. Convert the bi nary real number 1011100 . 1000101 to i ts equi val ent hexa-
deci mal real number.
I n case of bi nary fracti on, the formati on of groupi ng of bi nary bi ts whi ch are after the
bi nary poi nt, i s made from l eft to ri ght. For the i nteger part group i s made from ri ght to l eft.
1011100.1000101 = (101) (1100).(1000) (101)
= (0101) (1100).(1000) (1010)
= 5C.8A (hex.).
2.12.7 Conversion of a Hexadecimal Number to a Binary Number
To convert a hexadeci mal number to i ts equi val ent bi nary number each di gi t of the gi ven
hexadeci mal number i s converted to i ts 4-bi t bi nary equi val ent.
Example 1. Convert the hexadeci mal number 6B9 to i ts equi val ent bi nary number.
(6B9)
16
= (0110) (1011) (1001)
= (011010111001)
2
= (11010111001)
2
Example 2. Convert the real hexadeci mal number 6D.3A to i ts equi val ent bi nary number.
(6D.3A)
16
= (0110) (1101).(0011) (1010)
= (01101101.00111010)
2
= (1101101.0011101)
2
2.13 OCTAL NUMBER SYSTEM
The base of the octal number system i s 8. Thi s system i s al so used i n computer i ndustry.
I t uses ei ght di gi ts 0, 1, 2, 3, 4, 5, 6 and 7. The deci mal number 8 i s represented by 10, 9
by 11, 10 by 12 and so on i n the octal number system. An octal number i s represented by
a group of three bi nary bi ts. For exampl e, 4 i s represented by 100, 6 by 110 and 7 by 111.
The reason for usi ng 3 bi nary bi ts to represent an octal number i s that the l argest octal di gi t
i s 7 whi ch can be represented by onl y 3 bi nary bi ts i .e., 7 = 111. I f an octal number contai ns
two or more than two di gi ts, each di gi t i s i ndi vi dual l y represented by a group of three bi nary
bi ts. For exampl e, 46 i s represented by 100 110 and 354 by 011 101 100. Tabl e 2.5 shows octal
numbers and thei r bi nary representati ons. The bi nary representati on of an octal number i s
al so cal l ed bi nary coded octal number.
Let us exami ne the bi nary equi val ent and bi nary representati ons of a deci mal number
i n octal and hexadeci mal . The bi nary equi val ent of the deci mal number 45 i s 101101. The
deci mal number 45 i s 2D hexadeci mal and 55 octal respecti vel y. 2D (hex.) can be represented
i n bi nary as 00101101, and 55 (octal ) as 101101. I f negl ect zeros i n MSB posi ti ons, al l the three
bi nary representati ons are same.
2.24 COMPUTER FUNDAMENTALS
Table. 2.5 Octal Number and thei r Bi nary Representati ons
Decimal Number Octal Number Binary Coded Octal Number
0 0 000
1 1 001
2 2 010
3 3 011
4 4 100
5 5 101
6 6 110
7 7 111
8 10 001 000
10 12 001 010
15 17 001 111
16 20 010 000
61 75 111 101
63 77 111 111
64 100 001 000 000
100 144 001 100 100
2.13.1 Conversion of an Octal Number to a Decimal Number
For the conversi on of a number from any number system to deci mal number system we
make the use of the fol l owi ng wel l known expressi on:
The weight of the n-th di gi t of the number from ri ght hand si de = nth di gi t (Base)
n1
.
Example 1. Convert the octal number 56 to i ts equi val ent deci mal number.
As the base of the octal number system i s 8, appl yi ng the general rul e of conversi on,
we get
56 (octal ) = 5 8
1
+ 6 8
0
= 40 + 6
= 46 (deci mal )
Example 2. Convert the octal number 364 to i ts deci mal equi val ent.
364 (octal ) = 3 8
2
+ 6 8
1
+ 4 8
0
= 3 64 + 6 8 + 4 1
= 192 + 48 + 4
= 244 (deci mal )
2.13.2 Conversion of an Octal Fraction to a Decimal Fraction
I n the octal system the wei ght of the octal di gi ts after the octal poi nt are as expl ai ned
bel ow:
0.563 (octal ) = 5 8
1
+ 6 8
2
+ 3 8
3
NUMBER SYSTEM 2.25
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= 0.625 + 0.09375 + 0.005859375
= 0.724609375 (deci mal )
2.13.3 Conversion of a Decimal to an Octal Number
For the conversi on of a deci mal number to an equi val ent octal number, the techni que
of repeated di vi si on by 8 i s used.
Example 1. Convert the deci mal number 62 to i ts equi val ent octal number.
Quotient Remainder
62 8 = 7 , 6 (LSD)
7 8 = 0 , 7 (MSD)
62 (deci mal ) = 76 (octal )
Example 2. Convert the deci mal number 958 to i ts equi val ent octal number.
Quotient Remainder
958 8 = 119 , 6 (LSD)
119 8 = 14 , 7
14 8 = 1 , 6
1 8 = 0 , 1 (MSD)
958 (deci mal ) = 1676 (octal )
Checking the answer:
1676 (Octal ) = 1 8
3
+ 6 8
2
+ 7 8
1
+ 6 8
0
= 512 + 384 + 56 + 6
= 958 (deci mal )
2.13.4 Conversion of a Decimal Fraction to an Octal Fraction
For the conversi on of a deci mal fracti on to i ts equi val ent octal fracti on the techni que of
repeated mul ti pl i cati on by 8 i s used. The i nteger part i s noted down and new remai nder
fracti on i s used for the mul ti pl i cati on at the next stage.
Example 1. Convert the decimal fraction 0.96 to its equivalent octal fraction.
Fraction Fraction 8 Remainder Fraction New I nteger
0.96 7.68 0.68 7 (MSD)
0.68 5.44 0.44 5
0.44 3.52 0.52 3
0.52 4.16 0.16 4
0.16 1.28 0.28 1 (LSD)
The process wi l l conti nue further so we may take the resul t upto 5 pl aces of octal poi nt.
0.96 (deci mal ) = 0.75341 (octal ) approxi matel y
2.13.5 Conversion of a Binary Number to an Octal Number
The octal number system i s a base-8 system. For bi nary to octal conversi on, groups of
3 bi nary bi ts each are formed i n the bi nary number. After formi ng the groups, each group
of 3 bi nary bi ts i s converted to i ts octal equi val ent.
2.26 COMPUTER FUNDAMENTALS
Example 1. Convert the bi nary number 101110 to i ts equi val ent octal number.
The formati on of groups of 3 bi ts each i n an i nteger bi nary number i s made from ri ght
to l eft.
(101110)
2
= (101) (110)
= 56 (octal )
Example 2. Convert the bi nary number 1101011 to i ts equi val ent octal number.
(1101011)
2
= (1) (101) (011)
As the l eftmost group consi sts of onl y one bi nary bi t, thi s group i s extended by addi ng
zeros i n MSBs.
(1101011)
2
= (001) (101) (011)
= 153 (octal )
Example 3. Convert the bi nary real number 1011.1011 to i ts equi val ent octal number.
I n the i nteger part of the bi nary number the group of 3 bi ts i s formed from ri ght to l eft.
I n the bi nary fracti on the group of 3 bi ts i s formed from l eft to ri ght.
(1011.1001)
2
= (1) (011).(101) (1)
= (001) (011).(101) (100)
= 13.54 (octal ).
2.13.6 Conversion of an Octal Number to a Binary Number
To convert an octal number to i ts equi val ent bi nary number each di gi t of the gi ven octal
number i s converted to i ts 3-bi t bi nary equi val ent.
Example 1. Convert the octal number 376 to i ts equi val ent bi nary number.
(376)
8
= (011) (111) (110)
= (011111110)
2
= (11111110)
2
Example 2. Convert the real octal number 56.34 to i ts equi val ent bi nary number.
(56.34)
8
= (101) (110).(011) (100)
= (101110.011100)
2
= (101110.0111)
2
2.13.7 Conversion of an Octal Number to a Hexadecimal Number and Vice-Versa
The conversi on of a hexadeci mal number to i ts equi val ent octal number or vi ce-versa can
easi l y be done through bi nary as i l l ustrated by the exampl e gi ven bel ow.
Example 1. Convert the hexadeci mal number 3DE to i ts equi val ent octal number.
The hexadeci mal number 3DE i s fi rst converted to i ts bi nary equi val ent.
3DE (hex) = (0011) (1101) (1110)
= (001111011110)
2
Now the above bi nary equi val ent i s di vi ded i nto groups of 3 bi ts to obtai n i ts octal equi val ent.
001111011110 = (001) (111) (011) (110)
= 1736 (octal )
NUMBER SYSTEM 2.27
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Example 2. Convert the real hexadeci mal number 5B.3A to i ts equi val ent octal number.
The number 5B.3A i s fi rst converted to i ts bi nary equi val ent.
5B.3A = (0101) (101l ).(0011) (1010)
= 01011011.00111010
Now formi ng the groups of 3 bi nary bi ts to obtai n i ts octal equi val ent we have,
01011011.00111010 = (01) (011) (011).(001) (110) (10)
= (001) (011) (011).(001) (110) (100)
= 133.164 (octal ).
Example 3. Convert the octal number 536 to i ts equi val ent hexadeci mal number.
Converti ng 536 (octal ) fi rst to i ts bi nary equi val ent, we get,
(536)
8
= (101) (011) (110)
= (101011110)
2
Now formi ng the groups of 4 bi nary bi ts to obtai n i ts hexadeci mal equi val ent we get,
(101011110) = (1) (0101) (1110)
= (0001) (0101) (1110)
= 15E (hex).
Example 4. Convert the real octal number 46.57 to i ts equi val ent hexadeci mal number.
Converti ng 46.57 (octal ) fi rst to i ts bi nary equi val ent we get,
46.57 = (100) (110).(101) (111)
= (100110.101111)
2
Now formi ng the groups of 4 bi nary bi ts to obtai n i ts hexadeci mal equi val ent we have,
100110.101111 = (10) (0110).(1011) (11)
= (0010) (0110).(1011) (1100)
= 26.BC (hex).
2.14 ASCII AND ISCII CODES
ASCI I i s pronounced as ask-ee. I t stands for Ameri can Standard Code for I nformati on
I nterchange. ASCI I code i s used extensi vel y i n smal l computers, peri pheral s, i nstruments and
communi cati on devi ces. I t has repl aced many of the speci al codes that were previ ousl y used
by manufacturers. I t i s a 7-bi t code. Mi crocomputers usi ng 8-bi t word l ength use 7 bi ts to
represent the basi c code. The 8th bi t i s used for pari ty or i t may be permanentl y 1 or 0. Tabl e
2.6 shows ASCI I codes. Wi th 7 bi ts up to 128 characters can be coded. A l etter, di gi t or speci al
symbol i s cal l ed a character. I t i ncl udes upper-and l ower-case al phabets, numbers, punctua-
ti on marks, speci al characters and control characters. Tabl e 2.7 shows the defi ni ti ons of
control characters. Some control characters whi ch are used i n seri al communi cati ons are:
ENQ, ACK, NAK, etc. ENQ i s used for enqui ry. ACK i s for acknowl edgement. I t i s used to
i ndi cate successful recepti on after compl eti ng error checki ng. NAK i s negati ve acknowl edge-
ment, used to i ndi cate errors i n recepti on.
I SCI I stands for I ndi an Standard Code for I nformati on I nterchange. I t i s an 8-bi t code for
I ndi an l anguages.
2.28 COMPUTER FUNDAMENTALS
Table 2.6 ASCII Codes
Characters or Hex codes for Characters or Hex Codes for
Abbreviations 7-bit ASCI I Abbreviations 7-bit ASCI I
NUL 00 & 26
SOH 01 ' 27
STX 02 ( 28
ETX 03 ) 29
EOT 04 * 2A
ENQ 05 + 2B
ACK 06 2C
BEL 07 - 2D
BS 08 . 2E
HT 09 / 2F
LF 0A 60
VT 0B : 3A
FF 0C ; 3B
CR 0D < 3C
SO 0E = 3D
SI 0F > 3E
DLE 10 ? 3F
DC1 11 @ 40
DC2 12 [ 5B
DC3 13 \ 5C
DC4 14 ] 5D
NAK 15 ^ 5E
SYN 16 5F
ETB 17 { 7B
CAN 18 | 7C
EM 19 } 7D
SUB 1A ~ 7E
ESC 1B DEL 7F
FS 1C a 61
GS 1D b 62
RS 1E c 63
US 1F d 64
SP 20 e 65
! 21 f 66
22 g 67
# 23 h 68
$ 24 i 69
% 25 j 6A
(Contd.)...
NUMBER SYSTEM 2.29
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k 6B K 4B
l 6C L 4C
m 6D M 4D
n 6E N 4E
o 6F O 4F
p 70 P 50
q 71 Q 51
r 72 R 52
s 73 S 53
t 74 T 54
u 75 U 55
v 76 V 56
w 77 W 57
x 78 X 58
y 79 Y 59
z 7A Z 5A
A 41 0 30
B 42 1 31
C 43 2 32
D 44 3 33
E 45 4 34
F 46 5 35
G 47 6 36
H 48 7 37
I 49 8 38
J 4A 9 39
Table 2.7 Definitions of Control Characters
NUL NULL DC2 DI RECT CONTROL 2
SOH START OF HEADI NG DC3 DI RECT CONTROL 3
STX START TEXT DC4 DI RECT CONTROL 4
ETX END TEXT NAK NEGATIVE ACKNOWLEDGE
EOT END OF TRANSMI SSI ON SYN SYNCHRONOUS I DLE
ENQ ENQUI RY ETB END TRANSMI SSI ON BLOCK
ACK ACKNOWLEDGE CAN CANCEL
BEL BELL EM END OF MEDI UM
BS BACKSPACE SUB SUBSTI TUTE
HT HORI ZONTAL TAB ESC ESCAPE
LF LI NE FEED FS FORM SEPARATOR
VT VERTI CAL TAB GS GROUP SEPARATOR
FF FORM FEED RS RECORD SEPARATOR
CR CARRI AGE RETURN US UNI T SEPARATOR
SO SHI FT OUT
SI SHI FT I N
DLE DATA LI NK ESCAPE
DC1 DI RECT CONTROL 1
2.30 COMPUTER FUNDAMENTALS
2.14.1 ASCII-8
A newer versi on of ASCI I i s known as ASCI I -8. I t i s an 8-bi t code. Wi th 8 bi ts code
capaci ty i s extended to 256 characters. Tabl e 2.8 shows ASCI I -8 codes.
Table 2.8 ASCII-8 Codes
Characters ASCI I -8 Codes Characters ASCI I -8 Codes
0 50 J AA
1 51 K AB
2 52 L AC
3 53 M AD
4 54 N AE
5 55 O AF
6 56 P B0
7 57 Q Bl
8 58 R B2
9 59 S B3
A Al T B4
B A2 U B5
C A3 V B6
D A4 W B7
E A5 X B8
F A6 Y B9
G A7 Z BA
H A8
I A9
2.15 EBCDIC CODE
I t i s pronounced as ebb-see-di ck. I t i s Extended Bi nary-Coded Deci mal I nterchange
Code. I t i s the standard character code for l arge computers. I t i s an 8-bi t code wi thout pari ty.
A ni nth bi t can be used for pari ty. Wi th 8 bi ts up to 256 characters can be coded. Tabl e 2.9
shows EBCDI C codes.
I n ASCI I -8 and EBCDI C fi rst 4 bi ts are known as zone bi ts and remai nder 4 bi ts repre-
sent di gi t val ues. In ASCI I fi rst 3 bi ts are zone bi ts and remai ni ng 4 bi ts represent di gi t
val ues. When an ASCI I -8 (or any other code) character i s entered, the computer recei ves the
bi nary equi val ent of the hex code for ASCI I -8. For exampl e, when ASCI I -8 key for di gi t 9 i s
pressed, the computer recei ves the bi nary equi val ent of 59 hex, whi ch must be converted to
the bi nary 1001 for ari thmeti c operati ons. Before ari thmeti c operati ons data must be con-
verted to proper format whi ch i s acceptabl e to ari thmeti c l ogi c ci rcui try. The data al so
i ndi cate whether they are posi ti ve or negati ve or unsi gned.
2.16 GRAY CODES
The Gray Code i s a bi nary code and i s shown i n Tabl e 2.10. I t i s used i n shaft encoder
whi ch i ndi cates the angul ar posi ti on of a shaft i n di gi tal form. The bi nary bi ts are arranged
NUMBER SYSTEM 2.31
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Table 2.9 EBCDIC Codes
Characters or Control Hex Codes for Characters or Control Hex Codes for
Characters EBCDI C Characters EBCDI C-
NUL 00 4A
SOH 01 . 4B
STH 02 , 6B
ETS 03 ? 6F
HT 05 : 7A
DEL 07 ; 5E
VT 0B ! 5A
FF 0C 7D
CR 0D 7F
SO 0E + 4E
SI 0F 60
DLE 10 6D
DC1 11 * 5C
DC2 12 / 61
DC3 13 = 7E
RES 14 < 4C
NL 15 > 6E
BS 16 ( 4D
CAN 18 ) 5D
EM 19 { 8B
FLS 1C } 9B
GS 1D [ AD
RDS 1E ] DD
US 1F | 4F
BYP 24 & 50
LF 25 $ 5B
EOB 26 5F
ENQ 2D % 6C
ACK 2E # 7B
BEL 2F @ 7C
SYN 32 a 81
DC4 35 b 82
EOT 37 c 83
NAK 3D d 84
SUB 3F e 85
SP 40 f 86
BLANK E0 g 87
(Contd.)...
2.32 COMPUTER FUNDAMENTALS
h 88 J D1
i 89 K D2
j 91 L D3
k 92 M D4
l 93 N D5
m 94 O D6
n 95 P D7
o 96 Q D8
p 97 R D9
q 98 S E2
r 99 T E3
s A2 U E4
t A3 V E5
u A4 W E6
v A5 X E7
w A6 Y E8
x A7 Z E9
y A8 0 F0
z A9 1 F1
A C1 2 F2
B C2 3 F3
C C3 4 F4
D C4 5 F5
E C5 6 F6
F C6 7 F7
G C7 8 F8
H C8 9 F9
I C9
i n such a way that onl y one bi nary bi t changes at a ti me when we make a change from any
number to the next. I ts use reduces the error i n readi ng shaft posi ti on. The l argest possi bl e
error wi l l be one l east si gni fi cant di gi t. Suppose that the shaft changes i ts posi ti on from 7 to
8, the Gray code wi l l change from 0100 to 1100. I f the bi nary bi t i s not pi cked up by the
sensor, the encoder, wi l l show the previ ous posi ti on that i s 7. But, i n case of standard bi nary
code 7 i s represented by 0111 and 8 by 1000. I f senor pi cks up the l east si gni fi cant bi ts that
i s 000, but fai l s to pi ck up the most si gni fi cant bi t 1, the output wi l l be 0000 i nstead of 1000.
There wi l l be l arge error i f standard bi nary code i s used for shaft encodi ng. I n thi s case an
error of the most si gni fi cant bi t may occur. The Gray code i s often used i n computer control l ed
machi nes such as l athes etc. Photoel ectri c coders or shaft posi ti on encoder di sks are used as
sensors. For detai l s the reader may consul t Ref. 5 and 10 (for books).
NUMBER SYSTEM 2.33
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Table 2.10 Gray and Excess-3 Gray Codes
Decimal Gray Codes Excess-3 Gray Codes.
0 0000 0010
1 0001 0110
2 0011 0111
3 0010 0101
4 0110 0100
5 0111 1100
6 0101 1101
7 0100 1111
8 1100 1110
9 1101 1010
10 1111
11 1110
12 1010
13 1011
14 1001
15 1000
The Gray code i s not sui tabl e for a deci mal code. Thi s i s due to the fact that the
transi ti on from 9 back to 0 i nvol ves a change of three bi ts (from 1101 to 0000). To overcome
thi s di ffi cul t Excess-3 Gray code as shown i n Tabl e 2.10 i s used. I n thi s case for a change from
9 to 0, the correspondi ng change i n excess-3 code Gray code wi l l be from 1010 to 0010, that
i s a change of onl y one bi t.
2.17 FIXED POINT REPRESENTATION OF NUMBERS
I n a fi xed-poi nt system of number representati on al l numbers are represented as i nte-
gers or fracti on. Si gned i ntegers or BCD numbers are referred to as fi xed poi nt numbers
because they contai n no i nformati on regardi ng the l ocati on of the bi nary poi nt or deci mal
poi nt. The bi nary or deci mal poi nt i s assumed at the extreme ri ght or l eft of the number. I f
the bi nary or deci mal poi nt i s at the extreme ri ght of the computer word, al l numbers are
posi ti ve or negati ve i ntegers. I f the radi x poi nt i s assumed to be at the extreme l eft, al l
numbers are posi ti ve or negati ve fracti on. Suppose one has to mul ti pl y 5.85 90.38. Thi s wi l l
be represented as 585 9038. The resul t wi l l be 5287230. The deci mal poi nt has to be pl aced
by the programmer to get the correct resul t, that i s 528.7230. Thus i n the fi xed-poi nt of
representati on the user has to keep the track of radi x poi nt whi ch i s a tedi ous job.
I n sci enti fi c appl i cati ons of computers fracti ons are frequentl y used. So a system of
representati on whi ch automati cal l y keeps track of the posi ti on of the bi nary or deci mal poi nt
i s requi red. Such a system of representati on i s cal l ed fl oati ng poi nt representati on of num-
bers. Thi s i s di scussed i n the next secti on. Many computers and al l el ectroni c cal cul ators use
fl oati ng-poi nt ari thmeti c operati ons. The computers whi ch do not have i nternal ci rcui try for
fl oati ng-poi nt operati ons can sol ve the sci enti fi c probl ems i nvol vi ng fracti ons wi th the hel p of
fl oati ng-poi nt software.
2.34 COMPUTER FUNDAMENTALS
2.18 FLOATING-POINT REPRESENTATION
A number whi ch has both an i nteger part as wel l as a fracti onal part i s cal l ed real
number or fl oati ng-poi nt number. A real number may be ei ther posi ti ve or negati ve. Exampl es
of real deci mal numbers are 215.58, 0.739, 516.46, 0.586 etc. Exampl es of bi nary real
numbers are 101.110, 0.1011, 101.1011, 0.1101 etc.
The real number 546.98 can al so be wri tten as 5.4698 10
2
, 0.009863 as 9.863 10
3
,
146.58 as 0.14658 10
3
etc. Such representati on i s known as sci enti fi c form of representati on.
I n sci enti fi c computati ons i t i s often necessary to carry out cal cul ati ons wi th very l arge
or very smal l numbers. Hence, sci enti sts have used a conveni ent notati on i n whi ch a number
i s expressed as a combi nati on of a manti ssa and an exponent. For exampl e 350000 may be
wri tten as 0.35 10
6
, where 0.35 i s the manti ssa and 6 i s the val ue of the exponent.
I n the general form a number N may be wri tten as N = MR
e
, where M i s the manti ssa,
e the exponent and R the radi x of the number system.
I n a computer a real or fl oati ng-poi nt number i s represented by two parts: manti ssa and
exponent. The fi rst part, the manti ssa, i s a si gned fi xed poi nt number. The second part, the
exponent i ndi cates the posi ti on of the bi nary or deci mal poi nt. For exampl e, the deci mal
number 3584.69 i s represented i n fl oati ng-poi nt representati on as shown bel ow.
Sign Sign
0 .358469
Manti ssa
" ! "
0 04
Exponent
!
A zero i n the l eftmost posi ti on of the manti ssa denotes pl us si gn. The manti ssa may be
ei ther a fracti on or i nteger. Most computers use fracti onal system of representati on for
manti ssa, but some manufacturers use the i nteger system. The deci mal poi nt shown above
i s an assumed deci mal poi nt. I t i s not physi cal l y i ndi cated i n the regi ster. The exponent
shown above i s +4 to i ndi cate that the actual posi ti on of the deci mal poi nt l i es four deci mal
posi ti ons to the ri ght of the assumed deci mal poi nt. I n the above i l l ustrati on the manti ssa
has been shown as a fracti on.
I f we use the i nteger system of representati on for manti ssa the number 3584.69 = 358469
10
2
wi l l be represented as shown bel ow:
Sign Sign
0 358469
Manti ssa
" ! "
1 02
Exponent
!
I n thi s representati on si gn of the exponent has been shown negati ve to i ndi cate that the
acutal posi ti on of the deci mal poi nt l i es two deci mal posi ti on to the l eft of the assumed
deci mal poi nt.
The deci mal number 0.0049586 = 0.49586 10
2
can be represented i n the fracti onal
system of representati on for manti ssa as i l l ustrated bel ow:
Sign Sign
0 4
Manti ssa
. 9586
" ! "
1 02
Exponent
!
NUMBER SYSTEM 2.35
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A negati ve number 563.5896 can be represented as shown bel ow:
Sign Sign
1 .
Manti ssa
5635896
"" ! ""
0 03
Exponent
!
A negati ve fracti on 0.000258637
= 0.258637 10
3
can be represented as
Sign Sign
1 . 58637
Manti ssa
2
"" ! ""
1 03
Exponent
!
The fl oati ng-poi nt bi nary number i s al so represented i n the same manner. For exampl e,
the bi nary number 1011.1010 can be represented i n a 16-bi t regi ster as shown bel ow:
Sign Sign
0 . 0111010
Manti ssa
1
"" ! ""
1 000100
Exponent
" ! "
The manti ssa occupi es 9 bi ts (i ncl udi ng si gn bi t) and the exponent 7 bi ts (i ncl udi ng si gn
bi t). The bi nary poi nt i s not physi cal l y i ndi cated i n the-regi ster, but i t i s onl y assumed to be
ther e.
I n the general form a fl oati ng-poi nt number i s expressed as
N = M R
e
The manti ssa M and the exponent e are physi cal l y present i n a regi ster of a computer.
But, the radi x R and the radi x-poi nt (deci mal or bi nary poi nt) are not i ndi cated i n the regi ster.
These are assumed thi ngs whi ch are taken i nto account by the el ectroni c ci rcui try whi ch
makes computati on and mani pul ati on.
2.18.1 Normalized Floating-Point Number
I f the most si gni fi cant di gi t of the manti ssa i s nonzero, the fl oati ng-poi nt number i s sai d
to be normal i zed. For exampl e, 0.00038695 10
5
and 0.058638 10
6
are not normal i zed
numbers. The correspondi ng normal i zed numbers wi l l be 0.38695 10
2
and 0.58638 10
7
are normal i zed numbers. Si mi l arl y, the bi nary numbers 0.10110 2
6
and 0.11010 2
7
are
normal i zed numbers. The bi nary numbers 0.0010110 2
8
and 0.0011010 2
5
are not normal i zed
numbers. Whi l e stori ng the fl oati ng-poi nt numbers the manti ssa i s shi fted l eft unti l i ts most
si gni fi cant bi t becomes nonzero, and the exponent i s adjusted accordi ngl y. I n other words the
fl oati ng-poi nt numbers are stored i n the normal i zed (or standard) form. The process of
shi fti ng of manti ssa l eft to make i ts most si gni fi cant bi t nonzero i s cal l ed normal i zati on.
2.18.2 Range of Stored Numbers
The range of the stored numbers depends on the word l ength of the computer and the
number of bi ts assi gned for the manti ssa and the number of bi ts assi gned for the exponent.
Suppose, a 16-bi t word i s empl oyed to store numbers. Out of 16 bi ts, 9 bi ts are used for the
storage of manti ssa i ncl udi ng si gn bi t and 7 bi ts for exponent i ncl udi ng si gn bi t. The maxi mum
val ue of the number whi ch can be stored i s shown i n Fi g. 2.1.
2.36 COMPUTER FUNDAMENTALS
The maxi mum val ue = 0.11111111 E 0111111
Where E i ndi cates exponent; 0 after E i ndi cates that the exponent i s posi ti ve.
Fig. 2.1 Maxi mum val ue of stored number.
The maxi mum val ue = (1 2
8
) 2
(2
6
1)
= (1 2
8
) 2
63
1 2
63.
= 10
19
The mi ni mum val ue of the number whi ch can be stored i s shown i n Fi g. 2.2.
The mi ni mum val ue = 0.10000000 E 1111111
The bi t 1 just after E i ndi cates that the exponent i s negati ve.
The mi ni mum val ue = (2
1
) 2
(2
6
1)
= (2
1
) 2
63
= 2
64
10
19
Then the range wi l l be 2
64
to 2
63
or 10
19
to 10
19
Fig. 2.2 Mi ni mum val ue of stored number.
Si mi l arl y, the range can be obtai ned for 32-bi t word l ength. Suppose out of 32 bi ts, 24
bi ts are empl oyed for the manti ssa i ncl udi ng si gn bi t and 8 bi ts for the exponent i ncl udi ng
si gn bi t.
The maxi mum val ue = (1 2
23
) 2
(2
7
1)
2
127
10
38
NUMBER SYSTEM 2.37
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The mi ni mum val ue = (2
1
) 2
(2
7
1)
= (2
1
) 2
127
= 2
128
10
38
The range of the numbers = 2
128
to 2
127
or 10
38
to 10
38
Biased Exponent
Whi l e determi ni ng the range of numbers whi ch a 32-bi t CPU can handl e, we have seen
that the exponent vari es from 128 to +127. The exponent i s negati ve, when a number i s l ess
than one. To el i mi nate the negati ve si gn of the exponent, we can add a constant +128 to the
exponent. Thi s modi fi cati on el i mi nates the need of a si gn bi t for the exponent. The modi fi ed
techni que i s known as biased exponent techni que. I n the modi fi ed techni que 8 bi ts are used
to represent a exponent i nstead of 7 bi ts.
Example 1. Represent a bi nary number 1101011 i n the fl oati ng-poi nt representati on
usi ng 32-bi t word l ength. 24 bi ts represent manti ssa and 8 bi ts represent exponent.
The bi nary number 1101011 = 0.1101011 2
7
For the above number, manti ssa = 0.1101011
The exponent = 7.
For bi ased representati on the exponent can be modi fi ed. The modi fi ed exponent = 7 +
128 = 135
135 = 10000111
Si nce the manti ssa i s posi ti ve, i ts si gn bi t wi l l be 0. The 32-bi t representati on of the
gi ven number i s
Si gn bi t

01101011 00000000 00000000 10000111


.......................................................... .............
| |
Manti ssa Exponent
Example 2. Represent 1101011 i n the fl oati ng-poi nt representati on for 32-bi t word l ength.
The gi ven bi nary number = 0.1101011 2
7
Si nce the gi ven number i s negati ve, i ts 2s compl ement i s used i n the representati on.
I ts 2s compl ement i s 0010101.
For the above negati ve number, manti ssa = 0.0010101
Exponent = 7. The bi ased exponent = 7 + 128 = 135
135 = 10000111
Si nce the gi ven number i s negati ve, the si gn bi t for the manti ssa wi l l be 1. The 32-bi t
representati on of the gi ven number i s
2.38 COMPUTER FUNDAMENTALS
Si gn bi t

10010101 00000000 00000000 10000111


.......................................................... ............
| |
Manti ssa Exponent
2.18.3 Floating-Point Arithmetic Operations
Ari thmeti c operati ons wi th fl oati ng-poi nt number are more compl i cated compared to
those wi th fi xed-poi nt numbers. More compl ex hardware ci rcui try i s requi red for thei r
processi ng. Al so, thei r processi ng takes l onger ti me. When addi ti on or subtracti on i s to be
performed wi th normal i zed fl oati ng-poi nt numbers, the exponents of the two numbers must
be made equal . To do thi s the manti ssa of the smal l er number i s shi fted ri ght by a number
of pl aces whi ch i s equal to the di fference i n exponents. The process of maki ng exponents
equal i s known as scaling or alignment of numbers. After maki ng the exponents equal the
manti ssas are added. After addi ti on or subtracti on the resul ts are normal i zed. The process
wi l l be cl ear by the exampl e gi ven bel ow:
Example 1. Add .586293 10
5
and .235000 10
3
.
Before addi ng these numbers, thei r exponents are made equal .
.586293 10
5
+ .002350 10
5
.588643 10
5
Example 2. Add .8794 10
6
and .7635 10
6
.8794 10
6
+ .7635 l 0
6
1.6429 10
6
= .16429 10
7
Example 3. Subtract .39 10
3
from .4935 10
5
.
.4935 10
5
.0039 l 0
5
.4896 10
5
I n case of fl oati ng-poi nt mul ti pl i cati on and di vi si on an al i gnment of manti ssas i s not
requi red. The product of two numbers i s obtai ned by mul ti pl yi ng the two manti ssas and
addi ng the exponents. The di vi si on of the number X by Y i s performed by di vi di ng the
manti ssa of X by the manti ssa of Y, and subtracti ng the exponent of Y from the exponent of
X. After mul ti pl i cati on or di vi si on the resul ts are normal i zed.
Example 4. Mul ti pl y .486 10
3
by .38 10
4
(.486 10
3
) (.38 10
4
)
= 1.8468 10
7
= .18468 10
8
NUMBER SYSTEM 2.39
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Example 5. Di vi de .93800 10
5
by .3500 10
2
(.93800 10
5
) (.3500 10
2
)
= 2.6800 10
3
= 0.26800 10
4
2.19 OVERFLOW AND UNDERFLOW
2.19.1 Integer Representation
I f two numbers of n di gi ts each are added and the sum contai ns n + 1 di gi ts, an overfl ow
wi l l occur. Thi s wi l l hol d good whether the numbers are si gned or unsi gned; bi nary or
deci mal . As a computer regi ster of n bi ts can not accommodate the resul t of n + 1 di gi ts, the
computer wi l l i ndi cate overfl ow. I f a posi ti ve number i s added to a negati ve number, overfl ow
does not occur because the sum i s smal l er than the l arger of the two ori gi nal numbers. An
overfl ow occurs when numbers to be added are both posi ti ve or both negati ve and the resul ts
exceeds the stori ng capaci ty of the regi ster.
Let us exami ne the case of addi ti on i n 2s compl ement. The fol l owi ng exampl es wi l l show
the addi ti on of two posi ti ve or two negati ve numbers. An 8-bi t regi ster stores numbers. 7 bi ts
are used to represent numbers. The l eftmost bi t i s used to represent the si gn of the number.
Example 1. Add 69 and 78.
+ 69 0 1000101 (Bi nary equi val ent of 69)
+ 78 0 1001110 (Bi nary equi val ent of 78)
+ 147 1 0010011
Carri es : 01
I n thi s case there i s a carry from the MSB of the numbers but no carry (or carry = 0)
out of the si gn bi t. The si gn bi t i s 1, whi ch i ndi cates negati ve sum. So resul t i s not correct.
Example 2. Add 69 and 78.
69 1 0111011 (2s compl ement of 69)
78 1 0110010 (2s compl ement of 78)
147 0 1101101
Carri es : 10
I n thi s case there i s no carry (carry = 0) from MSBs of the numbers but there i s a carry
from the si gn bi t. The si gn bi t of the resul t i s 0, so resul t i s not correct.
From the above exampl e i t i s cl ear that there i s an overfl ow i f two numbers are
posi ti ve but the sum has a negati ve si gn bi t or two numbers are negati ve but the resul t
has a posi ti ve si gn bi t. I n other words the overfl ow produces an erroneous si gn reversal .
To detect the overfl ow condi ti on the carry out of the MSBs of number (or carry i nto the
si gn bi t) and the carry out of the si gn bi t are exami ned. I f these two carri es are not equal
that i s one of them i s 0 and the other i s 1, an overfl ow condi ti on exi sts. I f both the carri es
are 0 or both are 1 there i s no overfl ow. Exampl es of addi ti on i n 2s compl ement i n Sec.
2.8.8 i ndi cate the condi ti ons where there i s no overfl ow. I n those exampl es both carri es are
zero or both are 1.
2.40 COMPUTER FUNDAMENTALS
2.19.2 Floating-point Representation
When the resul t i s too l arge or too smal l to be presented by the computer, an overfl ow
or underfl ow condi ti on exi sts. When two fl oati ng-poi nt numbers of the same si gn are added,
a carry may be generated out of hi gh-order bi t posi ti on. Thi s i s known as mantissa overflow.
I n case of addi ti on or subtracti on fl oati ng-poi nt numbers are al i gned. The manti ssa i s shi fted
ri ght for the al i gnment of a fl oati ng-poi nt number. Someti mes, the l ow order bi ts are l ost i n
the process of al i gnment. Thi s i s referred to as mantissa underflow. To perform the mul ti -
pl i cati on of two fl oati ng-poi nt numbers, the exponents are added. I n certai n cases the sum
of the exponents may be too l arge and i t may exceed the stori ng capaci ty of the exponent
fi el d. This is called exponent overflow. I n case of di vi si on the exponent of the di vi sor i s
subtracted from the exponent of the di vi dend. The resul t of subtracti on may be too smal l to
be represented. Thi s i s cal l ed exponent underflow.
Overfl ow or underfl ow resul ti ng from a manti ssa operati on can be corrected by shi fti ng
the manti ssa of the resul t and adjusti ng the exponent. But the exponent overfl ow or underfl ow
can not be corrected and hence, an error i ndi cati on has to be di spl ayed on the computer
scr een.
PROBLEMS
1. Why do di gi tal computers use bi nary numbers for thei r operati on?
2. Users of computers work wi th usual al phabets, speci al symbol s, deci mal numbers etc.,
whereas a computer can accept onl y bi nary di gi ts. Then how do computers understand the
i nformati on fed by the user?
3. Convert the fol l owi ng bi nary numbers to equi val ent deci mal numbers:
(i) 11010 (ii) 1011001 (iii) 1001011 (iv) 10011010
[Ans. (i) 26 (ii) 89 (iii) 75 (iv) 154]
4. Convert the fol l owi ng deci mal numbers to equi val ent bi nary numbers:
(i ) 19 (ii) 43 (iii) 154 (iv) 97.
[Ans. (i) 10011 (ii) 101011 (iii) 10011010 (iv) 1100001]
5. Convert the fol l owi ng bi nary fracti ons to equi val ent deci mal fracti ons:
(i) 0.1011 (ii) 0.1010 (iii) 0.011 (iv) 0.0101
[Ans. (i) 0.6875 (ii) 0.625 (iii) 0.375 (iv) 0.3125]
6. Convert the fol l owi ng real bi nary numbers to equi val ent deci mal numbers:
(i) 1001.101 (ii) 1101.11 (iii) 11001.0101 (iv) 101001.1101
[Ans. (i) 9.625 (ii) 13.75 (iii) 25.3125 (iv) 41.8125]
7. Convert the fol l owi ng deci mal numbers to equi val ent bi nary numbers:
(i) 17.71875 (ii) 50.7 (iii) 74.635 (iv) 100.5
[Ans. (i) 10001.10111 (ii) 110010.1011001 (iii) 1001010.1010001 (iv) 1100100.10]
8. Perform the fol l owi ng addi ti ons and check the resul t by converti ng the bi nary numbers to
deci mal :
(i) 1100 + 1001 (ii) 101011 + 110010 (iii) 1011001 + 11010
[Ans. (i) 10101 (ii) 1011101 (iii) 1110011]
9. Perform the fol l owi ng addi ti ons and check the resul t by converti ng the bi nary numbers to
deci mal :
NUMBER SYSTEM 2.41
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(i) 101.011 + 11.110 (ii) 1011.1010 + 1000.011 (iii) 11001.1011 + 10011.0110
[Ans. (i) 1001.001 (ii) 10100.00 (iii) 101101.0001]
10. Perform the fol l owi ng subtracti ons and check the resul t by converti ng the bi nary numbers
to deci mal :
(i) 1101 1001 (ii) 11001 10110 (iii) 10011010 1100001
[Ans. (i)100 (ii) 11 (iii) 111001]
11. Perform the fol l owi ng subtracti ons and check the resul t by converti ng the bi nary numbers
to deci mal :
(i) 101.101 11.011 (ii) 1100.01 1001.11 (iii) 1011.1 100.11
[Ans. (i) 10.01 (ii) 10.1 (iii) 110.11]
12. Fi nd 9s and 10s compl ements of the fol l owi ng deci mal numbers:
(i) 75 (ii) 438 (iii) 589 (iv) 183
[Ans. (i) 24, 25 (ii) 561, 562 (iii) 410, 411 (iv) 816, 817]
13. Fi nd 9s and 10s compl ements of the fol l owi ng deci mal numbers:
(i) 53.48 (ii) 0.863 (iii) 69.45 (iv) 54.99 (v) 48.9
[Ans. (i) 46.51, 46.52 (ii) 9.136, 9.137 (iii) 30.54, 30.55 (iv) 45.00, 45.01 (v) 51.0, 51.1]
14. Fi nd 1s and 2s compl ements of the fol l owi ng bi nary numbers:
(i) 1010 (ii) 11001 (iii) 000 (iv) 111
[Ans. (i) 0101, 0110 (ii) 00110, 00111 (iii) 111, 000 (iv) 000, 001]
15. Fi nd 1s and 2s compl ements of the fol l owi ng bi nary numbers:
(i) 0.101 (ii) 10.011 (iii) 100.11 (iv) 101.1
[Ans. (i) 1.010, 1.011 (ii) 01.100, 01.101 (iii) 011.00, 011.01 (iv) 010.0, 010.1]
16. Perform the fol l owi ng subtracti ons of bi nary numbers usi ng 2s compl ements:
(i) 1101 1001 (ii) 101 111 (iii) 101 0.11 (iv) 0.11 0.101
[Ans. (i) 0100 (ii) 10 (iii) 100.01 (iv) 0.001]
17. Why are subtracti ons usi ng 2s compl ements used i n modern computers? What are the
di ffi cul ti es wi th BCD or si mpl e bi nary subtracti ons?
18. How i s a negati ve number represented? Represent 5 i n bi nary number:
[Ans. Si gned-magni tude representati on 10101
Si gned 1s compl ement representati on 11010
Si gned 2s compl ement representati on 11011]
19. Convert the fol l owi ng hexadeci mal numbers to equi val ent deci mal numbers:
(i) 5A (ii) 1A5E (iii) AB7 (iv) 3A9 (v) 6B
[Ans. (i) 90 (ii) 6750 (iii) 2743 (iv) 937 (v) 107]
20. Convert the fol l owi ng deci mal numbers to equi val ent hexadeci mal numbers:
(i) 70 (ii) 950 (iii) 10761 (iv) 6747 (v) 428
[Ans. (i) 46 (ii) 3B6 (iii) 2A09 (iv) 1A5B (v) 1AC]
21. Convert the fol l owi ng deci mal numbers to equi val ent octal numbers:
(i) 63 (ii) 460 (iii) 2749 (iv) 201 (v) 3965
[Ans. (i) 77 (ii) 714 (iii) 5725 (iv) 311 (v) 7575]
2.42 COMPUTER FUNDAMENTALS
22. Convert the fol l owi ng octal numbers to equi val ent deci mal numbers:
(i) 72 (ii) 642 (iii) 5264 (iv) 704
[Ans. (i) 58 (ii) 418 (iii) 2740 (iv) 452]
23. Convert the fol l owi ng hexadeci mal numbers to equi val ent bi nary numbers:
(i) 6BC (ii) 5D, (iii) F2E (iv) 4C3F (v) 6E
[Ans. (i) 11010111100 (ii) 1011101 (iii) 111100101110 (iv) 100110000111111, (v) 1101110]
24. Convert the fol l owi ng bi nary numbers to equi val ent hexadeci mal numbers:
(i) 10110110111 (ii) 10010101 (iii) 1111110 (iv) 1101001100 (v) 101101
[Ans. (i) 5B7 (ii) 95 (iii) 7E (iv) 34C (v) 2D]
25. Convert the fol l owi ng octal numbers to equi val ent bi nary numbers:
(i) 435 (ii) 637 (iii) 256 (iv) 134
[Ans. (i) 100011101 (ii) 110011111 (iii) 10101110 (iv) 1011100]
26. Convert the fol l owi ng bi nary numbers to equi val ent octal numbers:
(i) 100011101 (ii) 1100101 (iii) 10110111 (iv) 11010110
[Ans. (i) 435 (ii) 145 (iii) 267 (iv) 326]
27. Convert the fol l owi ng hexadeci mal numbers to equi val ent octal numbers:
(i) 4B (ii) D9 (ii) 3F2 (iv) 5A3
[Ans. (i) 113 (ii) 331 (iii) 1762 (iv) 2643]
28. Convert the fol l owi ng octal numbers to equi val ent hexadeci mal numbers:
(i) 134 (ii) 67 (iii) 1527 (iv) 4753
[Ans. (i) 5C (ii) 37 (iii) 357 (iv) 9EB]
29. What are BCD codes? Di scuss thei r meri ts and demeri ts. What are thei r areas of appl i cati ons?
30. What i s the ful l form of ASCI I ? What i s the maxi mum number of characters, whi ch can be
represented by these codes? Di scuss i ts areas of appl i cati ons.
31. What are ASCI I -8 codes? What i s the maxi mum number of char acter s, whi ch can be
represented by these codes? Di scuss thei r areas of appl i cati ons.
32. What are EBCDI C codes? How many characters can be represented by these codes? Di scuss
thei r areas of appl i cati ons.
33. What are the advantage of Gray codes? Di scuss thei r areas of appl i cati ons.
34. Di scuss overfl ow and underfl ow phenomena whi ch occur i n a di gi tal computer.
I n thi s chapter our ai m i s not to di scuss al l di gi tal devi ces. Some i mportant devi ces l i ke
l ogi c gates, fl i p-fl ops, regi sters, mul ti pl exers etc. wi l l be descri bed. Some speci al purpose
di gi tal devi ces wi l l be di scussed i n other chapters.
3.1 LOGIC GATES
A di gi tal computer uses bi nary number system for i ts operati on. I n the bi nary system
there are onl y two di gi ts 0 and 1. The computer recei ves, stores, understands and mani pul ates
i nformati on composed of onl y 0s and 1s. The mani pul ati on of bi nary i nformati on i s done by
l ogi c ci rcui ts known as l ogi c gates. The i mportant l ogi c operati ons whi ch are frequentl y
per for med i n the desi gn of di gi tal systems ar e: AND, OR, NOT, NAND, NOR and
EXCLUSI VE-OR. An el ectr oni c ci r cui t whi ch per for ms a l ogi c oper ati on i s cal l ed a
logic gate. For exampl e, the el ectroni c ci rcui t whi ch performs AND operati on i s cal l ed AND
gate, whi ch performs OR operati on i s known as OR gate and so on. The l ogi c gates are the
basi c bui l di ng bl ocks of a di gi tal system. A l ogi c gate mani pul ates bi nary data i n a l ogi cal
way, i .e., the mani pul ati on has a l ogi cal meani ng. The knowl edge of l ogi c gates i s essenti al
to under stand the i mpor tant di gi tal ci r cui ts used i n computer s. The exampl e of such
ci rcui ts are: the di gi tal ci rcui ts used for addi ti on, subtracti on, mul ti pl i cati on etc. i n a di gi tal
computer.
3.1.1 AND Gate
An AND gate has two or more i nputs but i t has onl y one output. An i nput si gnal appl i ed
to a gate has onl y two stabl e states, ei ther 1 (HI GH) or 0 (LOW). There i s no i ntermedi ate
state. I n case of a 2-i nput AND gate the output i s 1 (hi gh) onl y i f both i nputs are 1 (hi gh),
otherwi se the output i s 0 (l ow). The l ogi cal operati on of an AND gate i s cal l ed the AND
operati on (or AND functi on). The l ogi cal AND operati on can easi l y be expl ai ned wi th the hel p
of two swi tches connected i n seri es, Fi g. 3.1(b). The current wi l l fl ow i n the ci rcui t onl y when
both swi tches, A and B, are cl osed. A swi tch has two stabl e states, ON and OFF. The ON state
i s taken as l ogi c 1, the OFF as l ogi c 0. When both swi tches are ON, i .e., A and B both have
l ogi c 1, the output i s 1. When anyone of the swi tches i s OFF, there i s no output (no current
i n the ci rcui t). The output i s taken as 0.
3.1
,1/16) ,-81+-5
CHAPTER
3
3.2 COMPUTER FUNDAMENTALS
Fig. 3.1(a) AND Gate. Fig. 3.1(b) A ci rcui t contai ni ng two swi tches i n seri es.
Fi g. 3.1(a) shows standard symbol for AND gate. The fi gure shows onl y two i nputs, A and
B. I f there are more than two i nputs, they wi l l be shown on the i nput si de. Tabl e 3.1 shows
the truth tabl e for a two-i nput AND gate. The output of an AND gate i s 1 onl y when al l the
i nputs are 1. I f anyone of the i nputs i s 0, the output wi l l be 0. Therefore, the output of an
AND gate i s same as the product of i nputs i .e., the output Y = A.B. The symbol
^
i s al so used
to denote AND operati on. A
^
B denotes AND operati on of A and B. I Cs are avai l abl e for AND
gate, for exampl e, 7408, 7415 and 7421 are 2-i nput, 3-i nput and 4-i nput AND gates respec-
ti vel y. Refer to secti on 4.1.1 for more detai l s.
Table 3.1. Truth Table for AND Gate
I NPUTS OUTPUT
A B Y =A.B
0 0 0
0 1 0
1 0 0
1 1 1
The real i zati on of vari ous types of l ogi c gates i s descri bed i n Appendi x I .
Truth Table
The output of an AND gate i s Y = A.B. I n thi s case A and B (i nputs) are i ndependent
vari abl es. Y (output) i s a dependent vari abl e. The tabl e whi ch shows the val ues of the
dependent vari abl e for al l possi bl e val ues of i ndependent vari abl es i s cal l ed truth table.
3.1.2 OR Gate
An OR gate i s al so known as I NCLUSI VE-OR gate. I t has two or more i nputs, but onl y
one output. The output of an OR gate wi l l be hi gh i f at l east anyone of the i nputs i s hi gh.
The output wi l l be 0 onl y when al l i nputs are 0. Thi s l ogi cal operati on wi l l be cal l ed OR
operati on (or OR functi on). Fi g. 3.2(a) shows a two-i nput OR gate. I ts truth tabl e has been
shown i n Tabl e 3.2. I ts output i s gi ven by Y = A + B. The l ogi cal OR operati on can easi l y
be expl ai ned taki ng an exampl e of two swi tches connected i n par al l el as shown i n
Fi g. 3.2(b). The current wi l l fl ow i n the ci rcui t when ei ther swi tch i s i n ON posi ti on (i .e.,
l ogi c 1). The current wi l l not fl ow at al l when both swi tches are i n OFF posi ti on (i .e., l ogi c
0). The symbol denotes OR operati on. A B denotes OR operati on of A and B. Exampl e
of OR gate i s: 7432, a 2-i nput OR gate. The rul es for OR operati on are not same as those
of ari thmeti c operati on. Here, 1 + 1 = 1 i s not val i d for ari thmeti c addi ti on. For more
details refer to secti on 4.1.2.
DI GI TAL DEVI CES 3.3
C
H
A
P
T
E
R

3
Fig. 3.2(a) OR Gate. Fig. 3.2(b) A ci rcui t contai ni ng two swi tches i n paral l el .
Table 3.2 Truth Table for OR Gate
I NPUTS OUTPUT
A B Y =A +B
0 0 0
0 1 1
1 0 1
1 1 1
3.1.3 NOT Gate
A NOT gate has onl y one i nput, and onl y one output
si gnal . I t i s al so cal l ed I NVERTER. I ts output i s the compl e-
ment of the i nput si gnal . The output i s 1 (HI GH) i f the i nput
i s 0 (Low). The output i s 0 when i nput i s 1. I ts output i s gi ven
by Y =
A
. NOT gates are used to i nvert the l ogi c l evel s i .e.,
from LOW to HI GH or HI GH to LOW where requi red. Fi g.
3.3 shows standard symbol for a NOT gate. Tabl e 3.3 shows i ts
truth tabl e. Exampl es of i nverter I Cs are 7404, 7405 etc.
Table 3.3. Truth Table for NOT Gate
I NPUT OUTPUT
Signal Signal
A Y =A
0 1
1 0
3.1.4 NAND Gate
A NAND gate has two or more i nputs but onl y one output. Fi g. 3.4(a) shows a two-i nput
NAND gate. The NAND functi on i s the compl ement of the AND functi on. An AND gate can
be combi ned wi th an I NVERTER to form a NAND gate. The abbrevi ati on NAND i s the short
form of NOT-AND. I ts output i s gi ven by Y =
A.B.
Tabl e 3.4 shows the truth tabl e for a 2-
i nput NAND gate.
Fig. 3.4(a) NAND Gate Fig. 3.4(b) Real i sati on of NAND Gate usi ng
AND gate and i nverter
Fig. 3.3 NOT Gate.
3.4 COMPUTER FUNDAMENTALS
Table 3.4 Truth Table for NAND Gate
I NPUTS OUTPUT
A B
Y = A B
0 0 1
0 1 1
1 0 1
1 1 0
The NAND operati on i s someti mes cal l ed universal operation because other l ogi c opera-
ti ons can be real i zed usi ng onl y NAND gates. A uni versal operati on i s one that can be used
to i mpl ement the three basi c l ogi c operati ons AND, OR and NOT. I t i s easi er to fabri cate
NAND and NOR gates empl oyi ng modern I C technol ogy compared to AND and OR gates.
NAND and NOR gates al so consume l ess power. Therefore, combi nati onal l ogi c networks are
real i zed usi ng onl y NAND gates. NAND gates are used as basi c bui l di ng bl ocks i n fabri cati ng
a di gi tal ci rcui t.
NAND gates are avai l abl e as a 2-, 3-, 4-, 8-, 12-, 13-i nput gate. For exampl e, 7400, 7410,
7420, 7430, 74134, 74133 are 2-i nput, 3-i nput, 4-i nput, 8-i nput, 12-i nput, and 13-i nput NAND
gates respecti vel y.
3.1.5 NOR Gate
A NOR gate has two or more i nputs but onl y one output. Fi g. 3.5(a) shows a two i nput
NOR gate. The NOR functi on i s the compl ement of OR functi on. An OR gate can be combi ned
wi th an I NVERTER to form a NOR gate as shown i n Fi g. 3.5(b). The abbrevi ati on NOR i s
the short form of NOT-OR. I ts output i s gi ven by
Y = A +B.
Tabl e 3.5 shows the truth tabl e
for a 2-i nput NOR gate.
Fig. 3.5(a) NOR Gate. Fig. 3.5(b) Real i sati on of NOR usi ng
OR gate and i nverter.
The NOR operati on i s al so a uni versal operati on. Other l ogi c gates such as AND, OR and
NOT can be real i zed usi ng onl y NOR gates. Combi nati onal l ogi c network can be real i zed
usi ng onl y NOR gates. NOR gates are used as basi c bui l di ng bl ocks i n fabri cati ng a di gi tal
network. NOR gates are avai l abl e i n I C forms. For exampl e, 7402, 7427, 7425 and 74260 are
2-i nput, 3-i nput, 4-i nput, 5-i nput NOR gates respecti vel y.
Table 3.5. Truth Table for NOR Gate
I NPUTS OUTPUT
A B
Y = + A B
0 0 1
0 1 0
1 0 0
1 1 0
DI GI TAL DEVI CES 3.5
C
H
A
P
T
E
R

3
3.1.6 Exclusive-OR (XOR) Gate
The output of XOR gate i s hi gh onl y when i ts i nputs are di fferent. I ts output i s l ow when
both i nputs A and B are same i .e., ei ther both are hi gh or both are l ow. I ts output i s gi ven
by
Y = A B
=
A B
=
AB AB +
Fig. 3.6 EXCLUSI VE-OR gate.
The XOR operati on i s al so cal l ed Modul o-2-sum operati on. Fi g. 3.6 shows the standard
symbol for a 2-i nput XOR gate. Tabl e 3.6 shows i ts truth tabl e. Exampl es of 2-i nput XOR gates
are 7486 and 74136.
Table 3.6. Truth Table for XOR Gate
I NPUTS OUTPUT
Y = A B
A B =
AB AB +
0 0 0
0 1 1
1 0 1
1 1 0
An XOR operati on can be di sti ngui shed from OR functi on as fol l ows:
A OR B means A or B or both whereas A XOR B means A or B but not both.
3.1.7 Exclusive-NOR (XNOR) Gate
The XNOR operati on i s the compl ement of XOR operati on. The output of XNOR i s hi gh
onl y when the l ogi c val ues of both i nputs A and B are same i .e., ei ther both are 1 or both
are 0. I ts output i s 0 when i ts i nputs are di fferent. Tabl e 3.7 shows i ts truth tabl e. The output
i s gi ven by
Y = A B
= AB + A B
Fig. 3.7 EXCLUSI VE-NOR gate
3.6 COMPUTER FUNDAMENTALS
Fi g. 3.7 shows a two-i nput XNOR gate. The 74135 i s an XOR/XNOR gate. I t has three
i nputs A, B and C. I f C i nput i s l ow i t operates as an XOR gate. I f C i nput i s hi gh i t operates
as XNOR gate.
Table 3.7 Truth Table for XNOR Gate
I NPUTS OUTPUT
A B Y =
A B
AB A B +
0 0 1
0 1 0
1 0 0
1 1 1
3.1.8 Realization of Other Logic Functions Using NAND/NOR
The NAND operati on i s sai d to be uni versal operati on because other l ogi c operati ons can
be real i zed usi ng onl y NAND gates. A l ogi c operati on i s sai d to be uni versal that can be used
Fig. 3.8 Real i sati on of other l ogi c operati ons usi ng NAND gates.
DI GI TAL DEVI CES 3.7
C
H
A
P
T
E
R

3
to i mpl ement other basi c l ogi c operati ons AND, OR and NOT. NOR gate i s al so a uni versal
gate. Other basi c l ogi c operati ons can be real i zed usi ng onl y NOR gates. I t i s easi er to
fabri cate NAND or NOR gates usi ng I C technol ogy than AND or OR gates. Another advantage
of NAND and NOR gates i s that they consume l ess power. Due to these reasons they are used
as basi c bui l di ng bl ocks i n fabri cati ng di gi tal networks. Fi g. 3.8 and Fi g. 3.9 show the real i -
zati on of other l ogi c gates usi ng onl y NAND gates and usi ng onl y NOR gates respecti vel y.
Fig. 3.9 Real i sati on of other l ogi c operati ons usi ng NOR gates
3.1.9 Tri-State Logic Gate
A tri -state l ogi c gate has three di sti nct output-state condi ti ons out of whi ch two states
are: hi gh and l ow, si mi l ar to a conventi onal gate. The thi rd state i s a hi gh i mpedance state.
I n the thi rd state the gate behaves as i f i ts output i s di sabl ed. The gate i s control l ed by a
separate control i nput si gnal C. I f C i s hi gh the gate behaves l i ke a normal l ogi c gate
provi di ng output 1 or 0. When C i s l ow the output i s di sabl ed i rrespecti ve of the val ues of
the i nputs. I n certai n cases the control si gnal i s desi gned to enabl e the gate, when i t i s l ow.
When a number of outputs of conventi onal gates are connected to a common bus, there
wi l l be l oadi ng probl em. To sol ve thi s tri -state gates are empl oyed. When tri -state gates are
connected to a common bus onl y one such gate whose control i s enabl ed gets access to the
bus. Fi g. 3.10(a) and (b) show a tri -state NAND gate wi th acti ve-hi gh and acti ve-l ow control
respecti vel y. Exampl es of tri -state l ogi c gate I Cs are:
74134 12-i nput posi ti ve tri -state NAND gate
74125 Tri -state quad bus buffer
74366 Tri -state hex i nverter.
3.1.10 Fan-Out and Fan-In
The fan-out of a l ogi c gate i s defi ned as the number of other l ogi c gates that can be
connected to the output of the gate. I n other words the fan-out of a l ogi c gate i s the maxi mum
3.8 COMPUTER FUNDAMENTALS
number of other gates whi ch can be dri ven by the gate. Si mi l arl y, the fan-i n i s defi ned as the
maxi mum number of gates whi ch can be connected to the i nput l i nes of the gate. Obvi ousl y,
the fan-i n wi l l be equal to the number of i nput l i nes of the gate.
Fig. 3.10 Tri -state NAND gate (a) wi th acti ve-hi gh control (b) wi th acti ve-l ow control .
3.2 FLIP-FLOPS
A devi ce i s sai d to be bi stabl e whi ch has two stabl e states. A fl i p-fl op i s a bi stabl e devi ce.
I t has two stabl e states: i ts output remai ns ei ther hi gh or l ow. The hi gh stabl e state, i .e., 1
i s cal l ed SET. The other stabl e state (l ow, i .e., 0) i s cal l ed RESET. I ts property i s to remai n
i n one state i ndefi ni tel y unti l i t i s changed by an i nput si gnal to swi tch over to the other
state. So i t can store bi nary bi t ei ther 1 or 0. Thus i t has stori ng capabi l i ty, i .e., memory.
I t i s a basi c memory el ement or storage cel l .
3.2.1 SR Flip-Flop
An SR fl i p-fl op can be real i zed connecti ng two NOR gates as shown i n Fi g. 3. 11 (a). R
and S are two i nput si gnal s to swi tch the fl i p-fl op from one stabl e state to the other. Fi g. 3.11
(b) i s another way of drawi ng the same ci rcui t. Q i s the output of the fl i p-fl op.
Q
i s the
compl ement of the output. To understand the operati ng pri nci pl e of the fl i p-fl op ci rcui t one
shoul d recal l that a hi gh on any i nput of a NOR gate wi l l force i ts output l ow i rrespecti ve
of the l ogi c val ue of the other i nput. Thus a hi gh on S (keepi ng R = 0) i nput wi l l make
Q
= 0.
Q
i s one of the i nputs of the upper NOR gate. As both i nputs (R and
Q
) of the upper
NOR gate are now l ow, i ts output Q wi l l be hi gh. Thus the fl i p-fl op stores bi nary bi t 1
Fig. 3.11 SR Fl i p-fl op usi ng NOR gates.
DI GI TAL DEVI CES 3.9
C
H
A
P
T
E
R

3
when S i s made hi gh. Even i f the set i nput S i s removed, the output Q wi l l remai n 1 because
Q i s one of the i nputs of the l ower NOR gate (i .e., Q acts as feedback). Si mi l arl y, when reset
i nput R i s made hi gh keepi ng S = 0, Q wi l l become l ow. So the fl i p-fl op now stores bi nary
bi t 0. Q i s al so one of the i nputs of the l ower NOR gate. As both i nputs of the l ower gate
(Q and S) are now l ow,
Q
i s hi gh. When R = 0, and S = 0, the fl i p-fl op wi l l remai n i n the
previ ous state, i .e., Q remai ns unchanged.
Tabl e 3.8 shows the truth tabl e for SR fl i p-fl op. An SR fl i p-fl op i s al so cal l ed a bi stabl e
mul ti vi brator.
Table 3.8. Truth Table for SR Flip-Flop
R S Q Action
0 0 Last No change
val ue
0 1 1 Set
1 0 0 Reset
1 1 I nval i d
condi ti on
When both S and R are made hi gh si mul taneousl y, i t wi l l make the outputs of both NOR
gates l ow whi ch i s agai nst the basi c defi ni ti on of a fl i p-fl op. However, i f such condi ti on occurs
i nci dentl y, Q wi l l be unpredi ctabl e bei ng 1 or 0 dependi ng upon the ci rcui t condi ti on.
Fig. 3.12 (a) S R Fl i p-Fl op empl oyi ng NAND gates.
(b) S R Fl i p-Fl op empl oyi ng NAND gates.
3.10 COMPUTER FUNDAMENTALS
A sl i ghtl y di fferent fl i p-fl op can be real i zed usi ng NAND gates as shown i n Fi g. 3.12(a).
I t may be cal l ed
S

R
fl i p-fl op. A 0 on any i nput to a NAND gate wi l l make i ts output hi gh.
Therefore, when we make
S
= 0 and
R
= 1, Q wi l l be 1 and Q = 0. Si mi l arl y, when
R
i s
made 0 keepi ng
S
= 1, Q wi l l become 0 and Q = 1. I f both
S
and
R
are made hi gh, the
fl i p-fl op wi l l remai n i n i ts previ ous output state. Both
S
= 0 and
R
= 0 wi l l make the output
of the fl i p-fl op unpredi ctabl e. To convert an
R S
fl i p-fl op i nto an RS fl i p-fl op the techni que
shown i n Fi g. 3.12(b) i s adopted.
Fl i p-fl op i n the si mpl est forms as shown i n Fi g. 3.12(a) and (b) i s cal l ed a latch. There
are uncl ocked l atches. There are some cl ocked l atches al so. They wi l l be di scussed l ater on
i n thi s chapter.
3.2.2 Clocked RS Flip-Flop
A cl ock si gnal i s added to the fl i p-fl op to control the i nstant at whi ch the fl i p-fl op changes
the state of i ts output. Fi gs. 3.13(a) and 3.13(b) show cl ocked RS fl i p-fl op. I n Fi g. 3.13(a) two
addi ti onal AND gates have been provi ded so as to appl y the cl ock si gnal . When cl ock i s l ow
the outputs of AND gates wi l l be forced to be l ow and hence the state of the fl i p-fl op i s not
changed. I t remai ns i n the previ ous state. The changes i n R and S has no effect on the fl i p-
fl op output Q. Thus the fl i p-fl op i s di sabl ed when cl ock i s l ow.
Fig. 3.13 Cl ocked RS Fl i p-Fl op
DI GI TAL DEVI CES 3.11
C
H
A
P
T
E
R

3
Fig. 3.14 Symbol for SR Fl i p-Fl op (a) Uncl ocked, (b) Cl ocked
When cl ock i s hi gh the outputs of AND gates wi l l respond to the changes i n i nputs R
and S. The fl i p-fl op wi l l now change i ts output accordi ng to the set or reset i nput. Thus the
fl i p-fl op i s enabl ed when cl ock i s hi gh. The SR fl i p-fl op shown i n Fi g. 3. 13(b) wi l l al so be
enabl ed when cl ock i s hi gh and di sabl ed when cl ock i s l ow.
Fi gs. 3.14(a) and (b) show standard symbol for uncl ocked and cl ocked SR fl i p-fl op
respecti vel y. Tabl e 3.9 shows the truth tabl e for cl ocked SR fl i p-fl op. Q
n + 1
denotes the
output state after the n
th
cl ock-pul se and Q
n
before the n
th
cl ock-pul se.
Table 3.9 Truth Table for Clocked SR Flip-Flop
I NPUTS OUTPUT
S
n
R
n
Q
n+1
0 0 Q
n
(No change, remai ns
i n l ast state)
1 0 1
0 1 0
1 1 Unpr edi ctabl e
(Not to be used)
SR fl i p-fl ops can be desi gned to be edge-tri ggered. The l evel -tri ggered SR fl i p-fl op i s
often cal l ed an SR latch. The uncl ocked si mpl e fl i p-fl ops and l evel tri ggered SR and D fl i p-
fl ops come under the category of latches. I n an uncl ocked l atch any change i n i nput i nfor-
mati on i s transferred i mmedi atel y to the output. I n a cl ocked l atch the change i n i nput data
i s transferred i mmedi atel y when cl ock i s hi gh. The output wi l l change i n response to the
changes i n i nput as l ong as the cl ock i s hi gh. On the other hand i n a fl i p-fl op the output
changes at a parti cul ar moment. So edge-tri ggered and master-sl ave devi ces fal l under the
category of fl i p-fl ops.
3.2.3 JK Flip-Flop
I n an SR fl i p-fl op the state of the output i s unpr edi ctabl e when S = R = 1. A
JK fl i p-fl op al l ows i nputs J = K = 1. I n thi s si tuati on the state of the output i s changed;
the compl ement of the pr evi ous state i s avai l abl e at the output ter mi nal . Fi g. 3.15(a)
shows the schemati c di agr am of a JK fl i p-fl op. I t has been r eal i zed by mak i ng
S = J. Q and R = K.Q. Fi g. 3.15(b) shows i ts standar d symbol . I ts tr uth tabl e i s gi ven
in Tabl e 3.10.
3.12 COMPUTER FUNDAMENTALS
Table 3.10 Truth Table-for J K Flip-Flop
I NPUTS OUTPUT
CLK J K Q
n+1
Q
n
(No change,
X 0 0 remai ns i n
l ast state)
1 0 1
0 1 0
1 1 Q
n
(toggl e)
i ndi cates posi ti ve-edge of the cl ock.
When J and K both are 0, the outputs of the AND gates i n Fi g. 3.15(a) wi l l be l ow, i .e.,
S and R are both l ow. When S and R are both l ow, there wi l l be no change i n the output state.
I t wi l l remai n i n previ ous state.
When J = 0 and K = 1, the output of the upper AND gate, i .e., S becomes l ow. Therefore,
i t i s not possi bl e to set the fl i p-fl op. As K = 1, the output of the l ower AND gate, i .e., R wi l l
be hi gh i f the other i nput of thi s gate Q i s hi gh. So the fl i p-fl op can be reset. But, i f the fl i p-
fl op i s al ready i n the reset state, i .e., Q = 0, R wi l l be l ow. So, the fl i p-fl op wi l l remai n i n
the reset state.
When J = 1 and K = 0, the output of lower AND gate, i .e., R becomes low. Therefore, it is not
possible to reset the flip-flop. As J = 1, the output of the upper AND gate, i.e., S will be high if the
other input of this gate
Q
is high. So the flip-flop can be set. But, if the flip-flop is already in the
set state, i.e.,
Q
= 0, S will be low. Therefore, the flip-flop will remain in the set state.
When J = 1 and K = 1, the fl i p-fl op can be set or reset dependi ng upon the previ ous state
of the output. I f Q = 1 and
Q
= 0, the upper AND gate i s di sabl ed and the l ower AND
gate enabl ed. Thi s makes S = 0 and R = 1. So the fl i p-fl op i s reset, i .e., Q becomes 0 and
Q
= 1. I f Q = 0 and
Q
= 1, S wi l l be 1 and R = 0. Hence, the fl i p-fl op wi l l be set, i .e.,
Q wi l l become hi gh and
Q
= 0. Thus i t i s seen that the fl i p-fl op i s forced to take the
compl ement of the previ ous state.
Fig. 3.15 JK Fl i p-Fl op (a) Schemati c di agram (b) Standard symbol .
DI GI TAL DEVI CES 3.13
C
H
A
P
T
E
R

3
I n Fi g. 3.15 (a) assume that RC ci rcui t has been removed. Wi th J = 1, K = 1 and hi gh
CLK, the output of the fl i p-fl op wi l l change to the compl ement of the previ ous state. The new
outputs are agai n fed back to the i nput AND gates. After the propagati on del ay the output
wi l l agai n change i f the hi gh CLK persi sts. Thus the output wi l l go on changi ng so l ong as
cl ock i s hi gh. So duri ng posi ti ve hal f cycl e of the cl ock the output of the JK fl i p-fl op
osci l l ates. Thi s si tuati on i s cal l ed race-around condi ti on or raci ng. To sol ve thi s probl em the
cl ock pul ses are converted to narrow spi kes usi ng RC ci rcui t havi ng a short ti me constant.
Because of AND gates, the fl i p-fl op becomes posi ti ve-edge-tri ggered. The output changes after
the posi ti ve edge of the spi ke stri kes. By the ti me new val ues of Q and
Q
return to the i nput
AND gates, the posi ti ve spi kes di e out. So onl y one change i n the output occurs duri ng each
cl ock cycl e. Propagati on del ay ti me prevents JK fl i p-fl op from raci ng.
The JK fl i p-fl op i s the most versati l e and commonl y used fl i p-fl op. I t i s an i deal fl i p-fl op
to be used for counti ng purposes.
3.2.4 Preset and Clear
When power i s swi tched on, the fl i p-fl ops go to random states. So presetti ng or cl eari ng
i s requi red before appl yi ng i nputs. For such purpose preset PR and cl ear CLR termi nal s are
provi ded as shown i n Fi gs. 3.16(a) and (b). Smal l bubbl es shown at PR and CLR termi nal s
i ndi cate that they are effecti ve when they are l ow. A l ow PR sets Q to 1. Si mi l arl y, a l ow CLR
resets Q to 0. PR and CLR can not be made l ow at the same ti me.
Fig. 3.16 Tri ggeri ng of Fl i p-fl ops (a) Posi ti ve-edge-tri ggered (b) Negati ve-edge-tri ggered.
3.2.5 Triggering of Flip-Flops
The fl i p-fl ops can be tri ggered to set/reset ei ther at one of the edges or l evel s of the cl ock
pul se. There are three types of tri ggeri ng as descri bed bel ow.
Positive-Edge-Triggered Flip-Flops
Posi ti ve-edge-tri ggered fl i p-fl ops set or reset at the posi ti ve (ri si ng or l eadi ng) edge of the
cl ock pul se dependi ng upon the state of the i nput si gnal s. The set or reset state of the output
remai ns steady for one cl ock peri od and the cl ock agai n sampl es the i nput si gnal on the next
posi ti ve edge of the cl ock. Fi g. 3.16(a) shows the schemati c representati on of a posi ti ve-edge-
tri ggered fl i p-fl op. The arrowhead symbol i s cal l ed dynami c si gnal i ndi cator. Exampl es of
posi ti ve edge-tri ggered fl i p-fl ops are:
7470 AND gated JK Fl i p-Fl ops wi th preset and cl ear.
7474 Dual D-type Fl i p-Fl ops wi th preset and cl ear.
74109 Dual JK Fl i p-Fl ops wi th preset and cl ear.
3.14 COMPUTER FUNDAMENTALS
Negative-Edge-Triggered Flip-Flops
Negati ve-edge-tri ggered fl i p-fl ops set or reset at the negati ve (fal l i ng or trai l i ng) edge of
the cl ock pul se. Fi g. 3.l 6(b) shows the symbol i c representati on of negati ve-edge-tri ggered fl i p-
fl ops. A smal l ci rcl e known as bubbl e i s pl aced before the arrowhead to show negati ve-edge-
tri ggeri ng. Exampl es of negati ve edge-tri ggered fl i p-fl ops are:
74H102 AND gated JK Fl i p-Fl ops wi th preset and cl ear.
74LS73A Dual JK Fl i p-Fl ops wi th cl ear.
74LS113A Dual JK Fl i p-Fl ops wi th preset.
74276 Quad J K Fl i p-Fl ops, separate cl ocks, common di rect cl ear and preset.
Level-Triggered (or Pulse-Triggered) Flip-Flops
The l evel tri ggeri ng may be ei ther posi ti ve tri ggeri ng or negati ve tri ggeri ng. I n posi ti ve
tri ggeri ng the fl i p-fl op sets or resets accordi ng to the state of the i nput l i nes when cl ock i s
hi gh. I f the i nput changes duri ng hi gh cl ock peri od, the output wi l l al so change, accordi ngl y.
When cl ock i s l ow the output does not change, i t remai ns i n the previ ous state whi ch was
at the end of the posi ti ve cl ock pul se.
Si mi l arl y, i n negati ve tri ggeri ng the fl i p-fl op sets or resets accordi ng to the state of the
i nput l i nes when cl ock i s l ow. When cl ock i s hi gh the output does not change. I t remai ns i n
the previ ous state whi ch was at the end of the negati ve cl ock pul se.
Level -tri ggered D type fl i p-fl ops or D l atches are transparent l atches. I n a transparent
l atch the output fol l ows the state of the i nput l i nes when cl ock i s hi gh. I f i nput i s changi ng
the output goes on changi ng when the cl ock i s hi gh. Thi s type of fl i p-fl ops are not sui tabl e
for computer appl i cati ons. But they are sui tabl e for some appl i cati ons i n other di gi tal sys-
tems. Level -tri ggered master-sl ave fl i p-fl ops are not transparent. Exampl es of l evel -tri ggered
fl i p-fl ops and l atches are:
7475, 7477 D type dual transparent l atches
74279 Quad
S R
l atch
7473, 7476 Dual JK Fl i p-Fl ops
74H71, 7472 Master-sl ave JK Fl i p-Fl ops
74L71 AND-gated SR Master-Sl ave Fl i p-Fl op
74259 8-bi t addressabl e l atches wi th cl ear
3.2.6 Master-slave JK Flip-Flops
Fi g. 3.17 shows the schemati c di agram of a master-sl ave JK fl i p-fl op. I t consi sts of two
cl ocked SR fl i p-fl ops. One i s cal l ed master and the other sl ave. When the cl ock i s hi gh,
the master i s acti ve and the sl ave i nacti ve. The master sets or resets accordi ng to the state
of the i nput si gnal s. As the sl ave i s i nacti ve duri ng thi s peri od i ts output remai ns steady
at the previ ous state. When the cl ock goes l ow the master i s i nacti ve and the sl ave i s
acti ve. The sl ave sets or resets accordi ng to i ts i nputs. The fi nal output Q of a master-sl ave
fl i p-fl op i s the output of the sl ave. The output of the sl ave i s avai l abl e at the end of the
cl ock pul se.
DI GI TAL DEVI CES 3.15
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3
Fig. 3.17 Master-sl ave JK Fl i p-fl op.
When i nputs, i .e., J and K both are hi gh the master-sl ave fl i p-fl op toggl es once. The
master toggl es once and then sl ave copi es the acti on of the master. There i s no race-around
condi ti on because the feedback i s from the output of the sl ave whi ch i s steady duri ng posi ti ve
hal f cycl e of the cl ock. JK master-sl ave fl i p-fl ops are very popul ar i n i ndustry. They are i deal
fl i p-fl ops to be used i n counti ng devi ces. Master-sl ave fl i p-fl ops are al so real i zed usi ng D fl i p-
fl ops. Exampl es of JK master-sl ave fl i p-fl op I Cs are: 74H71, 7472, 74110 and 74111. An
exampl e of SR master-sl ave fl i p-fl op i s 74L71. Al l these master-sl ave fl i p-fl ops are l evel -
tri ggered. A probl em associ ated wi th l evel tri ggered master-sl ave JK fl i p-fl ops i s that the J
and K i nputs must not change whi l e cl ock i s hi gh otherwi se the output wi l l be unpredi ctabl e.
I f a master-sl ave uni t contai ns edge-tri ggered fl i p-fl ops there wi l l be no such di ffi cul ty.
3.2.7 D Flip-Flop
An SR fl i p-fl op has two i nputs, S and R. To store 1 a hi gh S and l ow R are requi red.
To store 0 a hi gh R and l ow S are needed. Thus two si gnal s are to be generated to dri ve an
SR fl i p-fl op. Thi s i s a seri ous di sadvantage i n many appl i cati ons. To overcome thi s di ffi cul ty
D fl i p-fl op has been devel oped whi ch has onl y one i nput l i ne. A D fl i p-fl op can be real i zed
usi ng an SR fl i p-fl op as shown i n Fi g. 3.18(a). There i s no raci ng probl em wi th D fl i p-fl op.
A JK fl i p-fl op can al so be used to real i ze a D fl i p-fl op usi ng the techni que shown i n
Fi g. 3.18(a).
Fig. 3.18 D Fl i p-fl op (a) schemati c di agram. (b) Level tri ggered, (c) Posi ti ve-edge-tri ggered.
I f the devi ce shown i n Fi g. 3.18(a) i s l evel -tri ggered, i t i s often cal l ed a D l atch (or
bi stabl e l atch). Fi g. 3.18(b) shows i ts symbol i c representati on. I n l evel tri ggeri ng when cl ock
3.16 COMPUTER FUNDAMENTALS
(or enabl e si gnal ) i s hi gh the output Q fol l ows the state of i nput l i ne D. When D goes hi gh,
Q goes hi gh. When D goes l ow, Q goes l ow. When cl ock i s l ow, the output does not change.
I t remai ns i n the previ ous state. Tabl e 3.11 shows the truth tabl e for a D l atch. A D l atch
i s a transparent l atch. Such l atches are not sui tabl e for computer appl i cati ons but they are
sui tabl e for other appl i cati ons i n di gi tal ci rcui ts. Exampl es of transparent l atch I Cs are: 7475,
7477, 74100, 74116 and 74LS375.
Table 3.11 Truth Table for D Latch
CLK D I NPUT Q
n+1
0 X Q
n
(previ ous state)
1 0 0
1 1 1
I f the devi ce shown i n Fi g. 3.18(a) i s posi ti ve-edge-tri ggered i t i s cal l ed a D fl i p-fl op. The
fl i p-fl op sets or resets accordi ng to the state of the i nput D at the posi ti ve edge of the cl ock.
The set or reset state of the output remai ns for one compl ete cl ock peri od. Fi g. 3.18(c) shows
i ts schemati c di agram. Thi s type of D fl i p-fl ops are sui tabl e for computer ci rcui ts. Exampl es
of posi ti ve-edge-tri ggered D fl i p-fl op I Cs are: 7474, 74174, 74175, and 74273.
Tabl e 3.12 shows truth tabl e for a D fl i p-fl op. When cl ock i s l ow, Q remai ns i n the
previ ous state. On the arri val of posi ti ve edge of the cl ock Q i s set to 1 i f D i s 1; Q i s set
to 0 i f D i s 0. The posi ti ve edge of the cl ock i s marked by an upward arrow. On the negati ve
edge of the cl ock (marked by downward arrow), Q remai ns i n the l ast state.
Table 3.12. Truth Table for a D Flip-Flop
CLK D I NPUT Q
n+1
0 X Q
n
(l ast state)
1 1
0 0
X Q
n
(l ast state)
3.2.8 T Flip-Flop
A T fl i p-fl op acts as a toggl e swi tch. Toggl e means to swi tch over to the opposi te state.
I t can be real i zed usi ng a JK fl i p-fl op by maki ng T = J = K = 1, as shown i n Fi g. 3.19. I ts
truth tabl e i s shown i n Tabl e 3.13.
Fig. 3.19 T Fl i p-fl op
Table 3.13. Truth Table for T Flip-Flop
I NPUT OUTPUT
T Q
n+1
0 Q
n
1 Q
n
DI GI TAL DEVI CES 3.17
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3
3.3 LATCHES
A fl i p-fl op i n i ts si mpl est form i s cal l ed a l atch. A l atch stores a bi nary bi t 1 or 0. The
uncl ocked si mpl e fl i p-fl ops, and l evel -tri ggered SR and D fl i p-fl ops fal l under the category of
l atches. An n-bi t l atch consi sts of n-number si ngl e-bi t l atches. I t stores a bi nary word of n bi ts.
The n-bi ts of the bi nary word are transferred to the l atch si mul taneousl y i n paral l el . I n a
l atch there i s no faci l i ty to read i ts contents. The l atches are temporary storage devi ces. They
are i deal l y sui ted for stori ngs i nformati on between processi ng uni ts and I /O uni ts or i ndi cator
uni ts. The exampl es of l atch I Cs are:
74100 8-bi t bi stabl e l atches
74259 8-bi t addressabl e l atches
7475 4-bi t bi stabl e l atches
7477 4-bi t bi stabl e l atches
3.4 REGISTERS
Regi sters consi st of fl i p-fl ops rather than l atches. The fl i p-fl ops are connected i n paral l el .
All n-bi ts of an n-bi t regi ster are transferred i n paral l el . A regi ster stores a bi nary word. The
bi nary word remai ns stored unti l a new word i s appl i ed. Unl i ke a l atch, the contents of a
regi ster can be read at any ti me wi thout changi ng i ts val ue. Usual l y, regi sters consi st of D
type edge-tri ggered fl i p-fl ops. I C 74273 i s an 8-bi t regi ster. I t consi sts of 8 edge-tri ggered D
fl i p-fl ops, wi th common cl ock and cl ear l i nes. The regi sters of mi croprocessors are wi thi n the
mi croprocessors I C package.
3.5 SHIFT REGISTERS
I n a shi ft regi ster the fl i p-fl ops are connected i n seri es. The output of each fl i p-fl op i s
connected to the i nput of the adjacent fl i p-fl op. The contents of a shi ft regi ster can be shi fted
wi thi n the regi ster wi thout changi ng the order of the bi ts. Data are shi fted one posi ti on l eft
or ri ght at a ti me when one cl ock pul se i s appl i ed. Shi ft regi sters are used for the temporary
storage of data. They are used where bi t shi fti ng i s requi red for mani pul ati ng, computi ng or
processi ng data. They are i deal l y sui ted to processi ng seri al data, converti ng seri al data to
paral l el data, and converti ng paral l el data to seri al data. They can be bui l t usi ng D, JK or
SR fl i p-fl ops. Dependi ng upon the modes of l oadi ng and readi ng out the data there are four
types of shi ft-regi sters:
(i) Seri al -i n, seri al -out
(ii) Seri al -i n, paral l el -out
(iii) paral l el -i n, seri al -out
(iv) paral l el -i n, paral l el -out.
Exampl es of shi ft regi ster I Cs are:
(i) 7491 8-bi t seri al -i n, seri al -out shi ft regi sters.
(ii) 74164 8-bi t seri al -i n, paral l el -out shi ft regi sters.
(iii) 74165 and
74166 8-bi t seri al /paral l el -i n, seri al -out shi ft regi sters.
3.18 COMPUTER FUNDAMENTALS
(iv) 74198 8-bi t bi di recti onal uni versal shi ft regi sters.
(v) 74199 8-bi t seri al /paral l el -i n, paral l el -out shi ft regi sters.
Uni versal shi ft regi sters are provi ded wi th mode sel ect pi ns for I /O data transfer.
3.6 BUFFERS/DRIVERS
The functi on of a buffer/dri ver i s to i ncrease the output current/vol tage rati ngs. When
the output current of a di gi tal devi ce i s i nsuffi ci ent to dri ve another devi ce whi ch i s to be
connected to the output termi nal of the devi ce, a buffer i s empl oyed to ampl i fy the current.
A buffer i s a current ampl i fi er. I t i s represented by a tri angl e as shown i n Fi g. 3.20(a). For
an i nverti ng buffer a bubbl e i s pl aced at the output poi nt of tri angl e (Fi g. 3.20(b)). Someti mes,
an i ncreased vol tage i s requi red to dri ve rel ays, l amps etc. Sui tabl e dri vers are empl oyed for
such appl i cati ons.
Fig. 3.20 (a) Buffer, (b) I nverter buffer.
As the output current of standard TTL gates may be 10 ti mes the i nput current, a
certai n amount of bufferi ng i s done by a gate. But the devi ce i s sai d to be a buffer onl y when
the manufacturers opti mi ze the desi gn for hi gh current output. For exampl e, 7426 i s a quad
2-i nput NAND buffer. I ts NAND gates are opti mi zed for hi gh current output.
Exampl es of buffer/dri ver I Cs are:
7407,7417 Hex buffers/dri vers wi th open col l ector outputs
7406, 7416 Hex i nverter buffer/dri vers wi th open col l ector outputs
7428 Quad 2-i nput NOR buffers
7440 Dual 4-i nput NAND buffers.
3.7 ENCODERS, DECODERS AND CODE CONVERTERS
Di gi tal computers use bi nary numbers for thei r operati on. But users work wi th al pha-
bets and deci mal numbers. So el ectroni c devi ces are requi red to convert al phanumeri c char-
acters i nto bi nary codes. The functi on of an encoder i s to produce bi nary codes. The decodi ng
i s the reverse process of encodi ng. Exampl es of encoders and decoders are:
7441, 74141 BCD to deci mal decoders/dri vers, open col l ector outputs
7442 BCD to deci mal decoders/dri vers totem-pol e outputs
7417 Deci mal to BCD encoders
74148, 74348 Octal to BCD encoders.
The hexadeci mal to bi nary decoder i s real i zed empl oyi ng two 74148 encoders and a data
sel ector.
DI GI TAL DEVI CES 3.19
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3
There are a number of bi nary codes to represent numbers and al phanumeri c characters
such as BCD, hexadeci mal , octal , excess-3 code, Gray codes etc. Someti mes i t i s requi red to
convert i nformati on from one bi nary code to another. Devi ces used for such conversi on are
called code converters. Exampl es of code converters are:
74184 BCD to bi nary converter
74185 Bi nary to BCD converter
3.8 COUNTERS
Di gi tal counters consi st of a number of fl i p-fl ops. Thei r functi on i s to count el ectri cal
pul ses. To count certai n event, el ectri cal pul ses proporti onal to the event are produced for
the counti ng purpose. Counters can al so be used to count ti me i nterval or frequency. For
such purposes cl ock pul ses are appl i ed to the counter. As the cl ock pul ses occur at certai n
known i nterval s, the number of pul ses are proporti onal to ti me. Therefore, ti me i nterval can
easi l y be measured. The frequency i s i nversel y proporti onal to ti me. So frequency can al so
be measured.
There are basi cal l y two types of counters: synchronous and asynchronous. I n a synchro-
nous counter al l fl i p-fl ops are cl ocked si mul taneousl y. On the other hand i n asynchronous
counters the fl i p-fl ops are not cl ocked si mul taneousl y. Each fl i p-fl op i s tri ggered by the
previ ous fl i p-fl op.
3.8.1 Asynchronous or Ripple Counters
A bi nary asynchronous counter can be real i zed by the use of edge-tri ggered JK fl i p-fl ops
as shown i n Fi g. 3.21(a). The fl i p-fl ops are connected i n seri es. The Q output of one fl i p-fl op
i s connected to the cl ock termi nal of the next fl i p-fl op. I n other words the output of one fl i p-
fl op dri ves the next fl i p-fl op. So i t i s al so cal l ed serial counter. I t i s i nherentl y sl ow i n
operati on due to seri es connecti on. The tri ggers move through the fl i p-fl ops l i ke a ri ppl e i n
water. So i t i s cal l ed ri ppl e counter.
Fig. 3.21(a) Bi nary asynchronous (Ri ppl e) counter.
3.20 COMPUTER FUNDAMENTALS
Fig. 3.21(b) Ti mi ng di agram
Fl i p-fl ops are connected to operate as T fl i p-fl ops. When J and K i nputs of al l fl i p-fl ops
are made hi gh (i.e., when count enabl e i s hi gh); each fl i p-fl op wi l l change i ts state (toggl e)
on the recei pt of the negati ve edge of i ts i nput pul se. Suppose that the output of a T fl i p-fl op
i s 0. When cl ock i s appl i ed i ts output wi l l change from 0 to 1 on the recei pt of one cl ock pul se.
When cl ock goes l ow, the output wi l l remai n hi gh. On the recei pt of the second cl ock pul se,
i ts output wi l l change from 1 to 0. Thus a fl i p-fl op gi ves an output of one pul se on the recei pt
of two pul ses at i ts i nput. Fi g. 3.21(a) shows a bi nary ri ppl e counter consi sti ng of 3 fl i p-fl ops.
I f at the i nput termi nal of the fi rst fl i p-fl op 8 cl ock pul ses are appl i ed, fi rst fl i p-fl op wi l l gi ve
4 pul ses at i ts output termi nal . Now Q
0
acts as the cl ock i nput for the 2nd fl i p-fl op. At the
i nput termi nal of the 2nd fl i p-fl op 4 pul ses are now appl i ed. The 2nd fl i p-fl op wi l l gi ve 2 pul ses
at i ts output termi nal . Q
1
acts as the cl ock i nput for the 3rd fl i p-fl op. At the i nput termi nal
of the 3rd fl i p-fl op 2 pul ses are appl i ed. The thi rd fl i p-fl op wi l l gi ve one pul se at i ts output
termi nal .
Tabl e 3.14 shows how the counter contents advance on the recei pt of cl ock pul ses. I t i s
cl ear from the tabl e that counter content advances one count on the recei pt of each cl ock pul se.
Table 3.14 Truth Table of a Binary Ripple Counter
Clock Q
2
Q
1
Q
0
pulses
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
On the recei pt of 7 cl ock pul ses al l the three fl i p-fl ops show hi gh outputs. On the recei pt
of 8th cl ock pul se the 3rd fl i p-fl op gi ves an output of one pul se and al l fl i p-fl ops show 0 states.
A three fl i p-fl op counter counts from 0 to 7. I t has 8 states. I t i s cal l ed modul us-8 (or mod-
8) counter. Si mi l arl y, a four fl i p-fl op counter counts from 0 to 15. So i t i s a mod-16 counter.
A si x fl i p-fl op counter i s a mod-64 counter. Thus the number of output states of a counter
is called modulus of a counter.
I n a ri ppl e counter a decodi ng gate i s used, whi ch detects a gi ven state of the counter
and produces an output when that state i s detected.
DI GI TAL DEVI CES 3.21
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Exampl es of asynchronous counters are:
7490 BCD counters (di vi de by 2 and di vi de by 5).
7492 Di vi de-by 12 counters (di vi de by 2 and di vi de by 6).
7493 4-bi t bi nary counters (di vi de by 2 and di vi de by 8).
The ri ppl e counters are very si mpl e to bui l d but they are not sui tabl e for hi gh frequency
appl i cati ons. They are used as frequency di vi ders. Thei r operati on at l ower frequency i s
sati sfactory. Each fl i p-fl op has a del ay ti me. I n a ri ppl e counter the del ay ti me of al l the fl i p-
fl ops are added resul ti ng i n greater settl i ng ti me. Another probl em wi th ri ppl e counters i s
that gl i tches (unwanted pul ses) occur at the output of the gates. Both of these probl ems are
el i mi nated i n synchronous counters di scussed bel ow.
3.8.2 Synchronous (or Parallel) Counters
I n synchronous counters al l the fl i p-fl ops are di rectl y cl ocked at the same ti me so that
al l the fl i p-fl ops change thei r output state at the same ti me. Fi g. 3.22 shows the schemati c
di agram of synchronous counter. Exampl es of synchronous counters are:
74161 4-bi t bi nary UP counters.
74162 Decade Up counters.
74192 Decade UP/DOWN counters.
74193 4-bi t bi nary UP/DOWN counters.
Fig. 3.22 Synchronous Counter.
3.8.3 Mod-3, Mod-6 and Mod-12 Counters
The synchronous and asynchronous counters di scussed earl i er have a modul us of 2
n
,
where n i s the number of fl i p-fl ops i n the counter. The count 2
n
i s cal l ed natural count. The
counters consi sti ng of 1, 2, 3 and 4 fl i p-fl ops have thei r natural count 2, 4, 8 and 16 respec-
ti vel y. These counters progress one count at a ti me i n bi nary progressi on. Someti mes i t i s
desi rabl e to have the modul us of 3, 5 etc., other than 2
n
. Such modul us are cal l ed modi fi ed
3.22 COMPUTER FUNDAMENTALS
count. A counter of smal l er modul us can be real i zed from a counter of l arger modul us by
ski ppi ng certai n states. Fi g. 3.23(a) shows a counter of modul us 3. I ts truth tabl e i s shown
in Tabl e 3.15. The ti mi ng di agram i s shown i n Fi g. 3.23(b).
Fig. 3.23 Mod-3 counters (a) Schemati c di agram (b) Ti mi ng di agram
The counter progresses one count at a ti me upto 2. After two cl ock pul ses Q
0
i s l ow and
Q
1
is high. Q
1
i s feedback to J
0
. When Q
1
is high, Q
1
= 0. So J
0
= 0 and K
0
= 1. On the
arri val of the 3rd cl ock pul se the fi rst fl i p-fl op wi l l remai n i n the reset state. So Q
0
wi l l
remai n 0. At thi s moment J
1
= 0 and K
1
= 1. Hence the second fl i p-fl op wi l l al so reset. Thus
Q
1
wi l l al so become 0. Thus due to feedback of Q
1
to J
0
, the counter resets to 00 after
recei vi ng 3 cl ock pul ses. Mode-3 counter can al so be real i sed usi ng an al ternati ve ci rcui t.
Refer to secti on 3.8.4.3.
Table 3.15. Truth Table of Mod-3 Counter
Q
1
Q
0
Count
0 0 0
0 1 1
1 0 2
0 0 3
Mod-6 Counters
To real i ze mod-6 counter a fl i p-fl op i s added to Mod-3 counter as shown i n Fi g. 3.24.
Mode-6 counter can al so be real i sed usi ng an al ternati ve ci rcui t. Refer to secti on 3.8.4.2.
Fig. 3.24 Mod-6 counter
DI GI TAL DEVI CES 3.23
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3
Mod-12 Counters
Similarly, using 2 flip-flops and one mod-3 counter (2 3 2) we can realize a mod-12 counter.
The 7492A i s an asynchronous di vi de by 12 counter (di vi de by 2 and di vi de by 6). I t
consi sts of 4 Master-sl ave JK fl i p-fl ops. 74LS92A i s al so a di vi de by 12 (2 6) counter.
Mode-12 counter can al so be real i sed usi ng an al ternati ve ci rcui t. Refer to secti on 3.8.4.6.
3.8.4 Mod-5 Counters
Fi g. 3.25 (a) shows a mod-5 counter.
Q
2
i s fedback to J
0
. Q
0
and Q
1
are appl i ed to J
2
through an AND gate. Tabl e 3.16 shows the truth tabl e of a mod-5 counter.
The counter progresses one count at a ti me upto 4. At thi s moment Q
2
= 1,
Q
2
= 0. As
Q
2
i s fedback to J
0
, J
0
= 0. K
0
i s al ways 1. So the fi rst fl i p-fl op wi l l remai n i n reset state.
Q
0
= 0 i s al so appl i ed to J
2
through the AND gate resul ti ng i n J
2
= 0. Therefore, on recei pt
of 5
th
cl ock the thi rd fl i p-fl op wi l l now reset changi ng Q
2
from 1 to 0. Q
1
was al ready 0. Thus
the counters output i s 000. Thus the counter resets at 000 after recei vi ng 5 cl ock pul ses.
Fig. 3.25 (a) Mod-5 counter
Table 3.16 Truth Table of a Mod-5 Counter
Q
2
Q
1
Q
0
Count
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
0 0 0 5
3.8.4.1 Alternative Circuit For Mode-5 Counter
Fi g. 3.25(b) shows the schemati c di agram of a mode-5 counter. Q
0
and Q
2
are appl i ed to
a NAND gate. When Q
0
and Q
2
both are hi gh, then onl y i t gi ven 0 (l ow) output. The output
of the NAND gate i s appl i ed to an AND gate. The other i nput to the AND gate CLR (cl ear)
si gnal . When ei ther CLR i s l ow or the output of the NAND gate i s l ow, the output of the AND
gate i s l ow whi ch cl ears al l the fl i p-fl ops of the counter. Thi s resets the counter. The counter
progresses one count at a ti me up to 4 as shown i n Tabl e 3.16. I n thi s si tuati on Q
0
= 0, Q
1
= 0 and Q
2
= 1. When fi fth cl ock pul se i s appl i ed, Q
0
as wel l as Q
2
, both are 1, and hence
the output of the NAND gate becomes 0 (l ow) whi ch further makes the output of AND gate
l ow. Thi s resets al l the fl i p-fl ops of the counter thus the counter i s reset. When the counter
i s reset, i t shows 000. Thi s counter counts from 0 to 4 (fi ve number). Hence, i t i s cal l ed
mode-5 counter. The pri nci pl e of i ts ci rcui t i s easy to understand.
Fig. 3.25 (b) Mode-5 Counter.
3.8.4.2 Mode-6 Counter
Mode-6 counter can al so be real i zed modi fyi ng the ci rcui t of Fi g. 3.25(b) sl i ghtl y. When
Q
1
and Q
2
are appl i ed to the NAND gate, i t becomes Mode-6 counter. Though thi s ci rcui t
requi res more el ectroni c components, i ts pri nci pl e i s easy to understand.
3.8.4.3 Mode-3 Counter
To obtai n a mode-3 counter, a modi fi ed ci rcui t based on the pri nci pl e of the ci rcui t shown
i n Fi g. 3.25(b) can be used. For thi s onl y two fl i p-fl ops wi l l be used. There wi l l be a NAND
gate and an AND gate. Q
0
and Q
1
wi l l be appl i ed to the NAND gate. The resul ti ng ci rcui t
wi l l be ci rcui t for a Mode-3 counter.
3.8.4.4 Mod-10 (Decade or BCD) Counters
A decade counter can be real i zed usi ng a fl i p-fl op and a mod-5 counter (2 5 = 10). Fi g.
3.26 (a) shows a decade counter. Tabl e 3.17 shows i ts truth tabl e.
Table 3.17 Truth Table of a Decade Counter
Q
3
Q
2
Q
1
Q
0
Count
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
0 0 0 0 10
Fig. 3.26(a) Decade Counter
The I Cs 7490, 74L90, 74LS90, 74290, 74LS290, 74390 and 74490 are asynchronous decade
counters. They are 2 5 counters. 74190, 74LS190, 74Ll 92 and 74LS192 are BCD synchro-
nous counters.
3.8.4.5 An Alternative Circuit for Mode-10 (Decade or BCD) Counter
Fi g. 3.26(b) shows the schemati c di agram of a mode-10 (decade or BCD) counter. Q
1
and
Q
3
are appl i ed to a NAND gate. When Q
1
and Q
3
, both are hi gh, then onl y the output of the
NAND gate i s l ow. The output of the NAND gate i s appl i ed to an AND gate. The other i nput
to the AND gate i s CLR (cl ear) si gnal . When ei ther CLR or the output of the NAND gate i s
l ow, the output of the AND gate becomes l ow whi ch cl ears al l the fl i p-fl ops of the counter.
Thus the counter i s reset. The counter progresses one count at a ti me up to 9 as shown i n
the Tabl e 3.17. At thi s poi nt Q
0
= 1, Q
1
= 0, Q
2
= 0 and Q
3
= 1. On the recei pt to 10th cl ock
pul se Q
1
and Q
3
, both are hi gh and hence, the output of the NAND gate becomes l ow whi ch
further makes the output of the AND gate l ow. Thi s resets al l the fl i p-fl ops of the counter.
Thus thi s counter i s reset. When the counter i s reset, i t shows 0000. Thi s counter counts
fr om 0 to 9 (ten number s). Ther efor e, i t cal l ed mode-10 (decade or BCD) counter. The
pri nci pl e of i ts ci rcui t i s easy to understand.
Fig. 3.26(b) Mode-10 (Decade or BCD) counter
3.26 COMPUTER FUNDAMENTALS
3.8.4.6 Mode-12 counter
To obtai n a mode-12 counter, the ci rcui t of Fi g. 3.26(b) can be modi fi ed. When Q
2
and
Q
3
are appl i ed to the NAND gate, i t becomes a mode-12 counter.
3.8.5 Presettable Counters
A presettabl e counter starts counti ng from a number greater than zero. Thi s number
can be set before counti ng starts. Take an exampl e of presettabl e counter consi sti ng of 4 fl i p-
fl ops. I ts counti ng states are from 0000 to 1111. Suppose, i t has been preset at 0100 before
counti ng starts. When counti ng starts i t wi l l count 0101 on the recei pt of the fi rst cl ock pul se,
0110 on the recei pt of the second cl ock pul se and so on. I n thi s way i t wi l l count upto 1111
on the recei pt of subsequent cl ock pul ses. Thus we see that a presettabl e counter has vari abl e
modul us. I t has programmabl e modul us. Exampl es of presettabl e counter I Cs are:
74176, 74196 Presettabl e decade (bi qui nary) counters
74177, 74197 Presettabl e 4-bi t bi nary counters.
3.8.6 Up Counters, Down Counters and Up/Down Counters
Up Counters
I f a counter counts upward towards hi gher numbers, i t i s cal l ed up counter. The exam-
pl es of up counters are:
74160,74162 Decade Upcounters
Down Counters
The counters whi ch count downward towards l ower numbers are down counters.
Up/Down Counters
A counter whi ch i s desi gned to count ei ther towards hi gher numbers or towards l ower
numbers i s cal l ed an up/down counter. An U/D termi nal i s provi ded to control up/down
counti ng. I f U/D i s hi gh the counter becomes an up counter. I f i t i s l ow the counter becomes
a down counter. The exampl es of UP/DOWN counters are:
74168, 74190, 74192 Decade UP/DOWN synchronous counters.
74169, 74191, 74193, 4-bi t bi nary UP/DOWN synchronous counters.
3.8.7 Controlled Counters
A control l ed counter counts el ectri cal pul ses when i t i s asked to do so. There i s a control
termi nal COUNT to control counti ng. When i t i s hi gh, the counter counts pul ses appl i ed
to i t. When COUNT i s l ow i t does not do counti ng even though pul ses may remai n appl i ed
to i t.
3.8.8 Ring Counters
I nstead of counti ng numbers, a ri ng counter uses a bi nary word whi ch has onl y a si ngl e
hi gh bi t. Thi s word i s shi fted wi thi n the counter. Fi g. 3.27 shows a 4-bi t ri ng counter. I n a
ri ng counter fl i p-fl ops are connected i n seri es. The output Q of the one stage i s connected
to D i nput of the next stage. The output of the l ast stage i s fedback to the fi rst stage. Al l
fl i p-fl ops are cl ocked si mul taneousl y.
DI GI TAL DEVI CES 3.27
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3
Fig. 3.27 Ri ng counter.
A ri ng counter i s empl oyed to control a number of operati ons i n a sequence. The devi ces
may be connected to Q
0
, Q
1
, Q
2
, ... Q
n
outputs of the counter. The outputs Q
0
, Q
1
, Q
2
, ...
Q
n
go hi gh i n a sequence. For i ni ti al setti ng a bi nary word 0001 i s set i n a 4-bi t ri ng counter.
Fi rst CLR goes l ow. Q
0
i s made hi gh. Then CLR becomes hi gh. The devi ce connected to Q
0
i s acti vated. Now cl ock pul ses appl i ed to CLK termi nal acti vate devi ces. On the recei pt of the
fi rst cl ock pul se Q
1
becomes hi gh, and the devi ce connected to Q
1
i s acti vated. The second
cl ock pul se makes Q
2
hi gh, the 3rd cl ock pul se makes Q
3
hi gh and so on. At a ti me onl y one
output becomes hi gh and al l others remai n l ow. As the outputs Q
0
, Q
1
, Q
2
, ... Q
n
are made
hi gh i n a sequence, the devi ces connected to these outputs are acti vated i n a sequence. Ri ng
counters are used i n computers to control certai n operati ons i n a sequence. Thei r other
appl i cati ons are: to control stepper motors, encodi ng the outputs of el ectroni c keyboards etc.
3.8.9 Shift Counter (Johnson or Moebius Counter)
I t i s si mi l ar to a ri ng counter. I n a ri ng counter the Q output of the l ast stage i s fedback
to the D i nput of the 1st stage whereas i n a Johnson counter the compl emented output
Q
of the l ast stage i s fedback to D i nput of the 1st stage. I f JK fl i p-fl ops are used i n the counter
Q
i s fedback to J i nput and Q i s fedback to K i nput of the fi rst stage. I t i s al so cal l ed a
walking-ring, a twisted-ring or switched tail counter.
Tabl es 3.18 and 3.19 show the truth tabl e for 3-bi t and Mod-10 shi ft counters respecti vel y.
Such counters do not count i n bi nary or deci mal progressi on. Thei r counti ng sequence i s
shown i n the truth tabl es. I n counti ng sequence one fl i p-fl op gi ves hi gh output, then two fl i p-
fl ops gi ve hi gh outputs, then three and so on. At one stage al l fl i p-fl ops gi ve hi gh outputs.
After thi s one fl i p-fl op gi ves 0 output, then two fl i p-fl ops gi ve 0 output, then three and so on.
Fi nal l y, al l fl i p-fl ops gi ve 0 output.
Table 3.18. Truth Table for 3-Bit J ohnson Counter
Q
2
Q
1
Q
0
Count State
0 0 1 1 1
0 1 1 3 2
1 1 1 7 3
1 1 0 6 4
1 0 0 4 5
0 0 0 0 6
0 0 1 1
3.28 COMPUTER FUNDAMENTALS
Table 3.19. Truth Table for a Mod-10 J ohnson Counter
Q
4
Q
3
Q
2
Q
1
Q
0
Count State
0 0 0 0 1 1 1
0 0 0 1 1 3 2
0 0 1 1 1 7 3
0 1 1 1 1 15 4
1 1 1 1 1 31 5
1 1 1 1 0 30 6
1 1 1 0 0 28 7
1 1 0 0 0 24 8
1 0 0 0 0 16 9
0 0 0 0 0 0 10
0 0 0 0 1 1
Mod-10 shi ft counters empl oy fi ve fl i p-fl ops. For 5 fl i p-fl op counters there shoul d be 32
states. But there are onl y 10 states. Others are i nval i d states.
3.9 DIGITAL MULTIPLEXERS/DATA SELECTORS
A di gi tal mul ti pl exer has N i nputs and onl y one output. By appl yi ng control si gnal s
anyone i nput can be made avai l abl e at the output termi nal . I t i s al so cal l ed data sel ector.
Fi g. 3.28 shows the schemati c di agram of a di gi tal mul ti pl exer. The control si gnal s are appl i ed
to the sel ect l i nes to sel ect the desi red i nput. Exampl es of di gi tal mul ti pl exer/data sel ector
I Cs are:
74150 1 of 16 Data Sel ectors/Mul ti pl exers
74151A 1 of 8 Data Sel ectors/Mul ti pl exers
74152 1 of 8 Data Sel ectors/Mul ti pl exers
74153 Dual 4-l i ne to 1-l i ne data Sel ectors/Mul ti pl exers
Fig. 3.28 Di gi tal mul ti pl exer.
DI GI TAL DEVI CES 3.29
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3
3.10 DIGITAL DEMULTIPLEXERS/DECODERS
A di gi tal demul ti pl exer has 1 i nput and N outputs. The meani ng of demul ti pl exer i s one
i nto many. By appl yi ng control si gnal s the i nput si gnal can be made avai l abl e at anyone of
output termi nal s. I t performs reverse operati on of a mul ti pl exer. Fi g. 3.29 shows the sche-
mati c di agram of a demul ti pl exer.
Fig. 3.29 Di gi tal demul ti pl exer.
The 74154 i s a 1 to 16 demul ti pl exer/4 to 16 decoder. Fi g. 3.30 shows the connecti on of
74154 as a demul ti pl exer. The STROBE has to be l ow to acti vate the 74154. G
1
(Pi n 18) and
G
2
(pi n 19) are two strobe i nputs. To use 74154 as a demul ti pl exer the i nput si gnal can be
appl i ed to anyone of the strobe i nputs (i.e., ei ther to G
1
or G
2
) wi th other strobe i nput l ow.
Suppose G
1
i s sel ected as data i nput l i ne, then G
2
i s used as strobe and i t i s kept l ow. When
strobe i s l ow, the control si gnal s appl i ed to sel ect l i nes sel ect one of the output l i nes.
Fig. 3.30 Connecti ons of 74154 as a Demul ti pl exer.
3.30 COMPUTER FUNDAMENTALS
Fig. 3.31 Connecti ons of 74154 as a Decoder.
The sel ected output l i ne becomes l ow when i nput data i s l ow. When the data i nput i s
hi gh the sel ected output becomes hi gh. Thus the i nput si gnal can be made avai l abl e at the
sel ected output termi nal .
To use 74154 as a 4 to 16-l i nes decoder connecti ons can be made as shown i n Fi g. 3.31.
A decoder i s si mi l ar to a demul ti pl exer, wi th one excepti onthere i s no data i nput. G
1
(Pi n 18) and G
2
(Pi n 19) are grounded i n thi s case. The control si gnal s appl i ed to sel ect l i nes
sel ect one of the outputs. The sel ected output l i ne goes l ow. Other output l i nes remai n hi gh.
Due to thi s reason bubbl es have been shown on the output l i nes. Decoder i s used to connect
several devi ces to a mi croprocessor. By maki ng the sel ected output l i ne of the decoder l ow,
a device i s enabl ed.
Exampl es of demul ti pl exer/decoder I Cs are:
74138 1 to 8-l i nes demul ti pl exers or 3 to 8-l i nes decoders
74154 1 to 16-l i nes demul ti pl exers or 4 to 8-l i nes decoders
74155 Dual 1 to 4-l i nes demul ti pl exer s or 2 to 4 l i nes decoder s; 1 to 8-l i nes
demul ti pl exers or 3 to 8-l i nes decoders.
PROBLEMS
1. What are l ogi c gates? Di scuss AND operati on. Draw the schemati c bl ock di agram of a
3-input AND gate. Gi ve i ts truth tabl e.
2. Expl ai n OR operati on. Gi ve truth tabl e for 2-i nput and 3-i nput OR gates.
3. What are XOR and XNOR gates? Gi ve truth tabl es for 2 i nput XOR and XNOR gates.
4. What are NOR and NAND gates? Why are they cal l ed uni versal gates? Gi ve truth tabl es
for 3-i nput NAND and NOR gates.
DI GI TAL DEVI CES 3.31
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3
5. What i s tri -state l ogi c gate? Expl ai n i n bri ef.
6. What do you understand by fan-i n and fan-out of a l ogi c gate?
7. What i s a fl i p-fl op? What i s i ts functi on? Expl ai n how an SR fl i p-fl op i s real i zed empl oyi ng
(i) NOR gates, (ii) NAND gates. What i s the di fference between a fl i p-fl op and l atch?
8. What i s the shortcomi ng of an SR fl i p-fl op? Expl ai n how thi s shortcomi ng i s removed i n
JK fl i p-fl ops. Di scuss how a JK fl i p-fl op i s real i zed. Descri be i ts operati ng pri nci pl e. What
i s raci ng probl em i n JK fl i p-fl op?
9. Draw the schemati c di agram of a master-sl ave JK fl i p-fl op. Di scuss i ts worki ng pri nci pl e.
What are i ts advantages over other types of fl i p-fl ops?
10. What i s D fl i p-fl op? What i s i ts advantage over SR fl i p-fl op? What i s the di fference
between a D l atch and a D fl i p-fl op?
11. What i s tri ggeri ng of fl i p-fl ops? Di scuss di fferent types of tri ggeri ng wi th exampl es.
12. What are regi sters? What i s the di fference between a n-bi t regi ster and a n-bi t l atch?
13. What i s the functi on of a shi ft regi ster? What are i ts vari ous types? Where are such regi sters
used?
14. What are buffers/dri vers? Expl ai n i n bri ef.
15. Di scuss the functi on of encoders, decoders and code converters.
16. Draw the schemati c di agram of an asynchronous (ri ppl e) counter. Why i s i t cal l ed ri ppl e
counter? Gi ve some exampl es of asynchronous counter I Cs.
17. Di scuss the worki ng pri nci pl e of a synchronous (paral l el ) counter wi th i ts bl ock di agram.
What i s the advantage of synchronous counters over seri al counters.
18. What i s modul us of a counter? Di scuss the worki ng pri nci pl e of a mod-3 counter. How are
mod-6 and mod-12 counters real i zed usi ng mod-3 counters?
19. What i s a mod-5 counter? How i s i t bui l t? How i s a decade counter real i zed usi ng mod-5
counter?
20. Expl ai n the terms UP counter, DOWN counter and UP/DOWN counter.
21. What are presettabl e counters? What i s the nature of the modul us of a presettabl e counter?
22. Draw the schemati c bl ock di agram of a ri ng counter. Descri be i ts worki ng pri nci pl e. Menti on
i ts appl i cati ons.
23. What i s a shi ft-counter (Johnson counter)? How i s i t constructed?
24. What are di gi tal mul ti pl exers/sel ectors? Expl ai n thei r operati ng pri nci pl e. Gi ve a few exampl es
of mul ti pl exer I Cs.
25. What are demul ti pl exers/decoders? What i s the di fference between a demul ti pl exer and a
decoder? Show connecti on di agram of a demul ti pl exer and a decoder.
THIS PAGE
IS BLANK
Thi s chapter deal s wi th Bool ean al gebra, mi ni mi zati on techni ques for bool ean expres-
si ons, combi nati onal and sequenti al l ogi c ci rcui ts.
4.1 BOOLEAN ALGEBRA
Bool ean al gebra i s an al gebra of l ogi c. I t i s one of the most basi c tool s to anal yze and
desi gn l ogi c ci rcui ts. I t i s named after George Bool e who devel oped i t i n 1854. The ori gi nal
purpose of thi s al gebra was to si mpl i fy l ogi cal statements and sol ve l ogi c probl ems. I t had no
practi cal appl i cati on unti l 1939 when Shannon appl i ed i t to tel ephone swi tchi ng ci rcui ts.
Shannons work gave an i dea that Bool ean al gebra coul d be appl i ed to computer el ectroni cs.
Today i t i s the backbone of desi gn and anal ysi s of computer and other di gi tal ci rcui ts.
Now consi der the statement The man i s tal l . Thi s statement may be ei ther true or
fal se. So i t i s a l ogi cal statement. A symbol can be used to represent a l ogi cal statement. For
exampl e,
X = the man i s tal l
Further, 1 i s used to represent true, and 0 to represent fal se. I f the above menti oned
statement i s true, we wri te X = 1. I f the above statement i s fal se, we wri te X = 0. Here 1
and 0 represent onl y truth and fal sehood. They do not represent numeri cal val ues. 1 and 0
have no ari thmeti c si gni fi cance. They have onl y l ogi cal si gni fi cance.
4.1.1 AND Operation
We have al ready di scussed AND operati on i n Chapter 3. Here, the approach i s di fferent
i .e., i t i s from l ogi cal statement poi nt of vi ew. Now consi der the fol l owi ng statements:
The man i s tal l (= X)
The man i s wi se (= Y)
These statements can be wri tten as a compound statement gi ven bel ow:
The man i s tal l and the man i s wi se
Thi s compound statement can be wri tten i n the symbol i c form as fol l ows:
X AND Y
X may be true or fal se; and Y may be true or fal se. Therefore, the compound statement
4.1
CHAPTER
4
LOSIC DESISM
4.2 COMPUTER FUNDAMENTALS
X AND Y wi l l be true onl y when both X and Y are true. Tabl e 4.1 shows al l possi bi l i ti es of
truth and fal sehood of X and Y, and correspondi ng truth and fal sehood of X AND Y. Such a
tabl e i s cal l ed truth tabl e.
Table 4.1 Truth Table for AND Operation
X Y X AND Y
True AND True True
True AND Fal se Fal se
Fal se AND True Fal se
Fal se AND Fal se Fal se
A . i s used to represent AND operati on. So X AND Y wi l l be represented as X.Y.
Representi ng true by 1, fal se by 0 and AND by . the above tabl e can be repl aced by
Tabl e 4.2.
Other symbol s whi ch are used to represent AND operati on are

and . I n ordi nary


algebra . represents mul ti pl i cati on but i n Bool ean al gebra i t represents onl y l ogi cal AND
operati on. The rul es for AND operati on are exactl y same as those of si mpl e ari thmeti c
mul ti pl i cati on. Thi s i s just a coi nci dence whi ch enabl ed us to remember these rul es wi thout
any addi ti onal effort, though the AND operati on has nothi ng to do wi th the ari thmeti c
mul ti pl i cati on. However, i t i s used i n computers mul ti pl i cati on ci rcui ts because of the such
coi nci dence.
Table 4.2 Truth Table for AND Operation in Symbolic Form
X Y X.Y
1.1 = 1
1.0 = 0
0.1 = 0
0.0 = 0
4.1.2 OR Operation
Now consi der the fol l owi ng two basi c l ogi cal statements:
He wi l l gi ve me a pen (= X)
He wi l l gi ve me a penci l (= Y)
These two statements can be wri tten as a compound statement gi ven bel ow:
He wi l l gi ve me a pen or a penci l or both
Thi s compound statement can be wri tten i n the symbol i c form as shown bel ow:
X OR Y OR both
Thi s i s cal l ed i ncl usi ve-OR. Both i s not wri tten i n the statement. I f si mpl y OR i s wri tten,
i t i s understood that i t i s i ncl usi ve-OR. X OR Y means X OR Y OR both. Therefore, an
i ncl usi ve-OR i s si mpl y wri tten as gi ven bel ow:
X OR Y
There i s another connecti ve: excl usi ve-OR. I t i s wri tten as XOR. I t means X OR Y but
not both.
LOGI C DESI GN 4.3
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4
Here, we shal l consi der i ncl usi ve-OR. X may be true or fal se, and Y may be true or fal se.
The compound statement X OR Y wi l l be true when anyone or both statements are true.
Tabl e 4.3 shows al l possi bi l i ti es of truth and fal sehood of X and Y, and correspondi ng truth
and fal sehood of X OR Y.
Table 4.3 Truth Table for OR Operation
X Y X OR Y
True OR True True
True OR Fal se True
Fal se OR True True
Fal se OR Fal se Fal se
A + i s used to represent OR operati on. So X OR Y can be wri tten as X + Y. Represent-
i ng true by 1, fal se by 0 and OR by +, the above tabl e can be repl aced by Tabl e 4.4.
Table 4.4 Truth Table for OR Operation in Symbolic Notation
X Y X +Y
1 + I = 1
1 + 0 = 1
0 + 1 = 1
0 + 0 = 0
Other symbol s used to represent OR operati on are and . I n ordi nary al gebra +
means addi ti on, but i n Bool ean al gebra i t si mpl y represents l ogi cal OR operati on. The rul es
for OR operati on are not exactl y same as those of ari thmeti c addi ti on. The 1st rul e 1 + 1 =
1 i s not val i d for addi ti on. I t si mpl y i ndi cates that i f both statements are true, the compound
statement i s true. So we have to remember thi s parti cul ar rul e for OR operati on. The other
three rul es for OR operati on are exactl y same as those for ari thmeti c addi ti on.
4.1.3 NOT Operation
Now consi der the fol l owi ng statement:
The man i s wi se (assume i t i s = X)
Thi s statement may be true or fal se. I f thi s statement i s true, the statement gi ven bel ow
wi l l be fal se:
The man i s NOT wi se (= NOT X =
X
)
I f the statement The man i s wi se i s fal se, the statement The man i s NOT wi se wi l l
be true. Tabl e 4.5 i s the truth tabl e for NOT operati on.
Table 4.5 Truth Table for NOT Operation
X NOT X
True Fal se
Fal se True
NOT X i s represented by
X
or X

.
X
i s cal l ed the complement of X.
4.4 COMPUTER FUNDAMENTALS
I f X = l, X = 1 = 0
I f X = 0, X = 0 = 1
I t al so fol l ows that
X = X
1 = 1
0 = 0
Tabl e 4.6 shows the truth tabl e for NOT operati on i n symbol i c form.
Table 4.6. Truth Table for NOT Operation in Symbolic Form
X X
1 0
0 1
4.1.4 Examples of Switches to Illustrate Logic Operations
El ectri cal swi tches are very good exampl es to gi ve cl ear concept of AND, OR operati ons
and many Bool ean theorems. A swi tch has onl y two states: ei ther cl osed or open. These are
si mi l ar to truth and fal sehood of a statement. We can assume cl osed = 1 and open (off) = 0.
Now consi der two swi tches connected i n seri es as shown i n Fi g. 4.1. I t i s a very good
exampl e to i l l ustrate AND operati on. The bul b wi l l gl ow onl y when both the swi tches X and
Y are cl osed. Tabl e 4.7 shows i ts truth tabl e.
Fig. 4.1 Two swi tches i n seri es.
We can assume closed = 1, open = 0, ON = 1 and OFF = 0, then Table 4.8 wi l l repl ace
the Tabl e 4.7.
Si mi l arl y, two swi tches connected i n paral l el as shown i n Fi g. 4.2 i s an exampl e to
i l l ustrate OR operati on. The bul b wi l l gl ow when ei ther or both swi tches are on. Tabl e 4.9
shows i ts truth tabl e.
Table 4.7. The Behaviour of Two Switches Connected in Series
Switch X Switch Y Bulb B
Cl osed Cl osed ON
Cl osed Open OFF
Open Cl osed OFF
Open Open OFF
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Table 4.8. Truth Table for Two Switches Connected in Series
Switches Bulb B
X Y B =X.Y
1 1 1
1 0 0
0 1 0
0 0 0
Table 4.9. Behaviour of Two Switches Connected in Parallel
Switch X Switch Y Bulb B
Cl osed Cl osed ON
Cl osed Open ON
Open Cl osed ON
Open Open OFF
Fig. 4.2 Two swi tches i n paral l el .
Tabl e 4.10 shows the truth tabl e i n symbol i c form for two swi tches i n paral l el .
Table 4.10. Truth Table for Two Switches in Parallel
Switches Bulb
X Y B =X +Y
1 1 1
1 0 1
0 1 1
0 0 0
Now consi der the fol l owi ng:
A swi tch i s cl osed = A
A swi tch i s NOT cl osed, i .e., open = A
4.1.5 Boolean Variables, Operations and Functions
A computer i s a bi nary di gi tal system. Such a system operates on el ectri cal si gnal s whi ch
have onl y two possi bl e states: HI GH (5 vol ts) and LOW (0 vol t). These hi gh and l ow states
are represented by 1 and 0 respecti vel y. A si gnal that does not change i ts state (or val ue) i n
ti me i s cal l ed a constant si gnal . The val ue of a constant si gnal wi l l al ways remai n same:
ei ther 1 or 0. On the other hand, a si gnal whi ch changes i ts state i n ti me i s known as a
4.6 COMPUTER FUNDAMENTALS
variable si gnal . The val ue of a vari abl e si gnal may be 1 at some ti mes and 0 at some other
ti mes. For desi gn and anal ysi s of di gi tal systems a constant si gnal and a vari abl e si gnal wi l l
be treated just as a constant and as a vari abl e respecti vel y. Thus the vari abl es whi ch have
onl y two val ues 1 and 0, are cal l ed Boolean variables (or l ogi c vari abl es). These vari abl es
may be denoted by A, B, C, X, Y, Z etc. There are onl y two Bool ean constants 0 and 1. I n
ordi nary al gebra a vari abl e can have very l arge (or even i nfi ni te) number of val ues, but i n
Bool ean al gebra they can have onl y one of the two possi bl e val ues, 0 and 1. Thus, Bool ean
al gebra becomes much si mpl er than ordi nary al gebra.
The onl y al gebrai c operati ons used i n Bool ean al gebra are AND, OR and NOT. Al l other
operati ons can be expressed i n terms of these basi c operati ons. For exampl e, NAND opera-
ti on i s the combi nati on of AND fol l owed by NOT. Si mi l arl y, NOR i s the combi nati on of OR
fol l owed by NOT.
I n ordi nary al gebra we have the concept of expressi on or functi on. Si mi l arl y, i n Bool ean
al gebra, we have the concept of expressi on or functi on. A Bool ean functi on or expressi on
consi sts of Bool ean vari abl es. Consi der the fol l owi ng exampl e:
X = A + B.C + C.(D + E)
A, B, C, D and E are Bool ean vari abl es. The ri ght hand si de of the above equati on i s
known as an expression. Each occurrence of a vari abl e or i ts compl ement i n an expressi on
i s cal l ed literal. I n the above expressi on there are fi ve vari abl es and si x l i teral s. General l y,
. i s not wri tten i n an expressi on. I t can be wri tten where addi ti onal cl ari ty i s requi red.
Bool ean expressi on (or Bool ean functi on) i s al so cal l ed l ogi c expressi on (or l ogi c functi on).
I n the above equati on the vari abl e X i s the functi on of A, B, C, D, and E. Thi s can be
wri tten as
X = f (A, B, C, D, E)
4.1.6 Boolean Postulates
Fundamental condi ti ons or sel f-evi dent proposi ti ons are cal l ed postul ates. The postul ates
for Bool ean al gebra ori gi nate from the three basi c l ogi c operati onsAND, OR and NOT. The
properti es of these basi c operati ons gi ven i n Tabl es 4.2, 4.4 and 4.6 are the postul ates for
Bool ean al gebra. These are cal l ed Bool ean postul ates and they are summari zed i n Tabl e 4.11.
These postul ates defi ne the operati on of the AND, OR and NOT. I n other words these are
the resul ts of these basi c operati ons.
Table 4.11. Boolean Postulates
(1) 0.0 = 0 Derived from AND operati on
(2) 0.1 = 0
(3) 1.0 = 0
(4) 1.1 = 1
(5) 0 + 0 = 0 Deri ved from OR operati on
(6) 0 + 1 = 1
(7) 1 + 0 = 1
(8) 1 + 1 = 1
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(9)
0
= 1 Deri ved from NOT operati on
(10)
1
= 0
4.1.7 Boolean Theorems
Wi th the hel p of Bool ean postul ates many useful theorems known as Bool ean theorems
have been deri ved. These theorems are very useful i n si mpl i fyi ng l ogi cal expressi ons or
transformi ng them i nto other useful equi val ent expressi ons. Tabl e 4.12 presents the l i st of
Bool ean theorems.
I n Bool ean al gebra, i t i s possi bl e to test the val i di ty of the theorems by substi tuti ng al l
possi bl e val ues of the vari abl es because the vari abl es have onl y two val ues, vi z. 0 and 1. Thi s
techni que of provi ng theorems i s known as proof by perfect induction.
Table 4.12. Boolean Theorems
(1) 0.X = 0 Properties of AND operati on
(2) X.0 = 0
(3) 1.X = X
(4) X.1 = X
(5) X + 0 = X Properti es of OR operati on
(6) 0 + X = X
(7) X + 1 = 1
(8) 1 + X = 1
(9) X.X = X Combi ni ng a vari abl e wi th i tsel f or i ts compl ement
(10) X. X = 0
(11) X + X = X
(12) X + X = 1
(13) X = X Doubl e compl ementati on
(14) X + Y = Y + X Commutati ve l aws
(15) X.Y = Y.X
(16) X.(Y.Z) = (X.Y).Z = X.Y.Z Associ ati ve l aws
(17) (X + Y) + Z = X + (Y + Z)
= X + Y + Z
(18) X.(Y + Z) = X.Y + X.Z Di stri buti ve l aws
(19) X + Y.Z = (X + Y).(X + Z)
(20) X + XY = X
(21) X(X + Y) = X
(22) XY + XY = X
Absorpti on
(23) (X + Y)(X + Y ) = X
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4.8 COMPUTER FUNDAMENTALS
(24) (a) X + X Y = X + Y
(b) XZ + Z X Y = ZX + ZY
(25) X (X + Y) = XY
(26) (Z + X) (Z + X + Y) = (Z + X) (Z + Y)
(27) XY + X Z + YZ = XY + X Z
(28) (X + Y) (X + Z) (Y + Z) = (X + Y) (X + Z)
(29) XY + X Z = (X + Z) (X + Y)
(30) (X + Y) (X + Z) = XZ + X Y
(31)
X. Y. Z X Y + Z + ... ... = +
(32)
X + Y + Z + X Y. Z... ... . =
DeMorgans Theorem
Proofs of some theorems by perfect i nducti on and/or some other techni ques are gi ven bel ow:
Theorem 1
0.X = 0
Proof. I f X = 0, 0.X = 0.0
= 0 by Postul ate 1.
I f X = 1, 0.X = 0.1
= 0 by Postul ate 2.
Ther efor e, 0.X = 0
Theorem 4
X.1 = X
Proof. I f X = 0, X.1 = 0.1
= 0 by Postul ate 2.
= X
I f X = 1, X.1 = 1.1
= 1 by Postul ate 4.
= X
Ther efor e, X.1 = X
Theorem 5
X + 0 = X
Proof. I f X = 0, X + 0 = 0 + 0
= 0 by Postul ate 5.
= X
I f X = 1, X + 0 = 1 + 0
= 1 by Postul ate 7.
= X
Ther efor e, X + 0 = X
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Theorem 8
1 + X = 1
Proof. I f X = 0, 1 + X = 1 + 0
= 1 by Postul ate 7.
I f X = 1, 1 + X = 1 + 1
= 1 by Postul ate 8.
Ther efor e, 1 + X = 1
Si mi l arl y, upto theorem 13, al l of them can be proved very easi l y wi th the hel p of
postul ates.
Theorem 14
X + Y = Y + X
Proof. I f Y = 0, X + Y = X + 0
= X by Theorem 5.
Y + X = 0 + X
= X by Theorem 6.
Ther efor e, X + Y = Y + X
I f Y = 1, X + Y = X + 1
= X by Theorem 7.
Y + X = 1 + X
= X by Theorem 8.
Ther efor e, X + Y = Y + X.
Al ternati vel y, thi s can al so be proved taki ng an exampl e of a 2-i nput OR gate. I f two
i nputs of a 2-i nput OR gate are i nterchanged, the output remai ns same. Therefore, X + Y =
Y + X.
Another proof can be obtai ned by prepari ng a truth tabl e for an OR gate havi ng i nputs
X and Y. Take al l possi bl e val ues of X and Y, fi nd the output X + Y, and Y + X. You wi l l see
that X + Y = Y + X.
Yet another way i s to consi der two swi tches X and Y connected i n paral l el to i l l ustrate
OR operati on. I f X and Y are i nterchanged, the resul t i s not affected. So X + Y = Y + X.
Theorem 15
X.Y = Y.X
Proof. I f Y = 0, X.Y = X.0
= 0 by Theorem 2.
Y.X = 0.X
= 0 by Theorem 1.
I f Y = 1, X.Y = X.1
= X by Theorem 4.
4.10 COMPUTER FUNDAMENTALS
Y.X = 1.X
= X by Theorem 3.
Ther efor e, X.Y = Y.X
Al ternati vel y, take an exampl e of 2-i nput AND gate. I f i nputs of 2-i nput AND gate are
i nterchanged, the resul t remai ns unaffected. Therefore, X.Y = Y.X.
Another proof can be obtai ned by consi deri ng two swi tches X and Y connected i n seri es
to i l l ustrate AND operati on. I f the X and Y are i nterchanged, the resul t i s not affected. So
X.Y = Y.X.
Yet another way i s: prepare truth tabl e for X.Y and Y.X for a 2-i nput AND gate taki ng
al l possi bl e val ues of i nputs X and Y. You wi l l see that X.Y = Y.X.
Theorem 20
X + XY = X
Proof. X + XY = X(1 + Y)
= X.1 by Theorem 8.
= X
Theorem 21
X(X + Y) = X
Proof. X(X + Y) = X.X + X.Y
= X + XY
= X(1 + Y)
= X.1 by Theorem 8.
= X
Theorem 22
XY + XY = X
Proof. XY + XY = X(Y + Y )
= X.1 by Theorem 12.
= X.
Theorem 23
(X + Y) (X + Y ) = X
Proof. (X + Y) (X + Y ) = X.X + XY + YX + YY
= X + X(Y + Y) + 0
= X + X.1
= X + X
= X
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Theorem 24(a)
X + X Y = X + Y
Proof. X + X Y = X + XY + X Y putti ng X = X + XY by Theo-
rem 20.
= X + Y(X + X )
= X + Y
Al ternati vel y, prove thi s theorem usi ng truth tabl e. Prepare a truth tabl e for al l val ues
of X and Y as shown in Tabl e 4.13.
Table 4.13
X Y X + X Y X +Y
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1
From the above tabl e we concl ude that
X + X Y = X + Y
Theorem 27
XY + X Z + YZ = XY + X Z
Proof. XY + X Z + YZ = XY + X Z + YZ(X + X )
= XY + X Z + YZX + YZX
= XY (1 + Z) + X Z( 1 + Y)
= XY + X Z
Theorem 31
X. Y = X + Y (Taki ng onl y two vari abl es).
Proof. Thi s theorem can easi l y be proved by truth tabl e approach. For al l val ues of X
and Y, we cal cul ate X. Y and X + Y, and tabul ate the resul t as shown i n Tabl e 4.14.
Table 4.14
X Y X Y . X Y +
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
From the above truth tabl e we concl ude that
X. Y = X + Y
4.12 COMPUTER FUNDAMENTALS
Theorem 32
X + Y
=
X . Y
(Taki ng onl y two vari abl es)
Proof. To prove thi s theorem we can prepare the truth tabl e as shown i n Tabl e 4.15.
Table 4.15
X Y
X Y +
X Y .
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
From the above truth tabl e we concl ude that
X + Y
=
X . Y
4.1.8 Simplification of Boolean Expression by Algebraic Method
Bool ean theorems are very useful tool s for si mpl i fyi ng l ogi cal expressi ons. Some exam-
pl es of si mpl i fi cati on are gi ven bel ow:
Example 1. Si mpl i fy the l ogi cal expressi on
X Y Z + X Y Z W + XZ
The above expressi on can be wri tten as
X Y Z
(1 + W) + XZ =
X Y Z
+ XZ, as 1 + W = 1 by Theorem
8.
= XZ(Y + 1)
= XZ, as Y + 1 = 1 by Theorem 8.
Example 2. Si mpl i fy the Bool ean expressi on
X XY Y (X Y)XY + + + +
The above expressi on can be wri tten as
X XY Y + XXY + Y XY + +
= X + X Y + Y , as XX = 0, XX Y = 0,
as YY = 0, Y X Y = 0.
= X + Y + Y as X +X Y = X + Y by Theorem 24(a).
= X + 1 as Y + Y = 1 by Theorem 12.
= 1 by Theorem 7.
Example 3. Si mpl i fy the l ogi cal expressi on
Z(Y + Z)(X + Y + Z)
The above expressi on can be wri tten as
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(ZY + ZZ)(X + Y + Z) = (ZY + Z)(X + Y + Z), as ZZ = Z by Theorem 9.
= Z(X + Y + Z), as Z + ZY = Z, by Theorem 20.
= ZX + ZY + ZZ
= ZX + ZY + Z, as ZZ = Z, by Theorem 9.
= ZX + Z, as Z +ZY = Z, by Theorem 20.
= Z, as Z + ZX = Z by Theorem 20.
Example 4. Si mpl i fy the l ogi cal expressi on
X Y XZ YZ YZW + + +
At fi rst gl ance i t l ooks that i t cannot be reduced further. But appl yi ng a tri ck i t can be
reduced as fol l ows:
The above expressi on can be wri tten as
X Y XZ.1 YZ YZW + + +
=
X Y XZ(Y + Y) YZ YZW + + +
=
X Y XZY + XZY YZ YZW + + +
= X Y Z YZ(X +1) + YZW ( ) 1 + +
= X Y YZ + YZW +
Example 5. Si mpl i fy the expressi on
(X + Y) (
X
+ Z) (Y + Z)
The above expressi on can be wri tten as
(XX + XZ + YX + YZ)(Y + Z) = (XZ + YX + YZ) (Y + Z), as XX = 0
= XZY + YYX + YYZ + XZZ + YX Z + YZZ
= XZY + YX + YZ + XZ + YX Z + YZ
Rearrangi ng the terms we get
XZY +XZ + YX + YX Z + YZ, as YZ + YZ = YZ
= XZ(Y + 1) + YX + YZ(X + 1)
= XZ + YX + YZ
Now i t seems that i t cannot be reduced further. But appl y the fol l owi ng tri ck:
The above expressi on can be wri tten as
XZ + YX + YZ(X + X ), as X + X = 1
= XZ + YX + YZX + YZX
= XZ(1 + Y) + YX (1 + Z)
= XZ + YX
4.1.9 Dual and Complement of a Boolean Expression
Two expressi ons are cal l ed equivalent onl y when both are equal to 1 or equal to 0. Two
expressi ons are complements of each other i f one expressi on i s equal to 1 whi l e the other i s
equal to 0, and vi ce versa.
4.14 COMPUTER FUNDAMENTALS
To obtai n the compl ement of a Bool ean expressi on the fol l owi ng changes are made:
(i) al l . si gns are changed to + si gns
(ii) al l + si gns are changed to . si gns
(iii) al l 1s are changed to 0s
(iv) al l 0s are changed to 1s
(v) al l l i teral s are compl emented.
Example. Fi nd compl ement of 1.X + Y Z + 0
The compl ement of the above expressi on wi l l be
(0 X) (Y Z).1 + +
The dual of a Bool ean expressi on i s obtai ned by performi ng the fol l owi ng operati ons:
(i) al l . si gns are changed to + si gns
(ii) al l + si gns are changed to . si gns
(iii) al l 1s are changed to 0s
(iv) al l 0s are changed to 1s
I n fi ndi ng a dual of an expressi on l i teral s are not compl emented. The fol l owi ng exampl es
i l l ustrate the pri nci pl e. There i s no general rul e for the val ues of dual expressi ons. Both
expressi ons may be equal to 1 or both may be equal to 0. One may be equal to 1 whi l e the
other i s equal to 0.
Example 1. Fi nd the dual of the Bool ean expressi on
1.X + Y Z + 0
The dual of the above Bool ean expressi on i s
(0 + X) (Y + Z).1
Example 2. Fi nd the dual of the equati on
X.(Y + Z) = X.Y + X.Z
The dual of the above equati on wi l l be
X + Y.Z = (X + Y) (X + Z)
Example 3. Fi nd the dual of X + XY = X
The dual of the above expressi on i s
X.(X + Y) = X
Example 4. Find the dual of X + X .Y =X +Y
The dual of the above equati on i s
X.(X + Y) = X.Y
Example 5. Fi nd the dual of the expressi on X(Y + YZ) + YZ
The dual of the above expressi on i s
[X + Y .(Y + Z)].(Y + Z) = (X + Y Z)(Y + Z)
= XY + XZ
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Bool ean postul ates 5, 6, 7 and 8 are the dual s (or compl ements, as no l i teral s are
i nvol ved) of 4, 3, 2 and 1 respecti vel y and vi ce versa (see Tabl e 4.11).
From Tabl e 4.12, Bool ean theorems 5, 6, 7 and 8 are dual s of 4,3,2 and 1 respecti vel y
and vi ce versa. Agai n 9 i s the dual of 11, 10 i s the dual of 12, 14 i s the dual of 15, 18 i s the
dual of 19, 20 i s the dual of 21, 22 i s the dual of 23 and so on, and vi ce versa. I f any theorem
i s proved, i t i s not necessary to prove i ts dual .
4.1.10 Sum of Products and Product of Sums Forms of Logic Expressions
A l ogi c expressi on shoul d be i n such a form whi ch can easi l y be real i zed usi ng l ogi c
gates. There are two such forms di scussed bel ow.
(i) Sum of Products Form
A sum of products expressi on consi sts of several product terms l ogi cal l y added. A product
term i s a l ogi cal product of several vari abl es. The vari abl es may or may not be compl e-
mented. The fol l owi ng are exampl es of sum of products expressi ons:
(a) XY + XY + XY
(b) AB + ABC + BC
(c)
A + AB + BC
(d) ABC +
AB + ABC + ABC
Someti mes a product term may consi st of a si ngl e vari abl e.
(ii) Product of Sums Form
A product of sums expressi on consi sts of several sum terms l ogi cal l y mul ti pl i ed. A sum
term i s the l ogi cal addi ti on of several vari abl es. The vari abl es may or may not be compl e-
mented. The fol l owi ng are exampl es of product of sums expressi ons:
(a) (A + B) (A B) +
(b) A (B C) + (B + C)
(c) (X + Y) (X + Y + Z) (Y + Z)
(d) (X + Y + Z) (X + Y + Z) (X + Y + Z)
Someti mes a sum term may consi st of a si ngl e vari abl e.
4.1.11 Canonical Form of a Logic Expression
When each term of a l ogi c expressi on contai ns al l vari abl es, i t i s sai d to be i n the canonical
form. When a sum of products form of l ogi c expressi on i s i n canoni cal form, each product term
is called a minterm. Each mi nterm contai ns al l vari abl es. The canoni cal form of a sum of
products expressi on i s al so cal l ed minterm canonical form or standard sum of products.
Si mi l arl y, when a product of sums form of l ogi c expressi on i s i n canoni cal form, each sum
term i s cal l ed a maxterm. Each maxterm contai ns al l vari abl es. The canoni cal form of a product
of sums expressi on i s al so cal l ed maxterm canonical form or standard product of sums.
When a l ogi c expressi on i s not i n the canoni cal form, i t can be converted i nto canoni cal
form. I n the canoni cal form there i s a uni formi ty i n the expressi on, whi ch faci l i tates mi ni -
mi zati on procedure.
4.16 COMPUTER FUNDAMENTALS
The fol l owi ng are exampl es of the canoni cal form of sum of products expressi ons (or
mi nterm canoni cal form):
(i) Z = XY + XY
(ii) F =
XYZ + XYZ + XYZ + XYZ + XYZ
(iii) Y = AB CD + ABC D + A BCD + A BC D + ABCD + ABCD
I n case of 2 vari abl es, the maxi mum possi bl e product terms are 4, for 3 vari abl e possi bl e
product terms 8, for 4 vari abl es: 16, for n vari abl es, 2
n
. I n the above exampl es the expressi on
(ii) contai ns 5 of 8 possi bl e product terms and (iii) contai ns si x out of 16 possi bl e combi nati ons.
When the expressi on i s i n the canoni cal form al l terms are mutually exclusive. I t means that
for a gi ven set of val ues of the vari abl es, when one of the terms i s equal to 1, al l others must
be 0. Of course, i t i s possi bl e that al l terms may be 0.
The fol l owi ng are exampl es of canoni cal form of product of sums expressi ons (or maxterm
canoni cal form):
(i) Z = (X + Y) (X +
Y
)
(ii) F = (X + Y + Z) (X + Y + Z) (X + Y Z) +
(iii) Y = (A +
B
+ C + D) (A + B + C + D) (A + B + C + D) (A +
B
+ C + D)
4.1.12 Conversion of Sum of Products Expressions into Canonical Form
The fol l owi ng exampl es wi l l i l l ustrate how l ogi c expressi ons can be converted i nto ca-
noni cal form.
Example 1. Convert the expressi on X + XY i nto canoni cal form.
Thi s expressi on has two vari abl es. The fi rst term has onl y one vari abl e. So to make i t
of two vari abl es i t can be mul ti pl i ed by (Y + Y), as Y + Y = 1. After mul ti pl i cati on the gi ven
l ogi c expressi on can be wri tten as
X(Y + Y ) + XY , as Y + Y = 1
= XY + XY + XY
= XY + XY
Example 2. Convert the fol l owi ng l ogi c expressi on i nto canoni cal form:
X + YZ
Thi s expressi on has three vari abl es. The fi rst term has onl y one vari abl e. I t requi res two
more vari abl es. So i t i s to be mul ti pl i ed by (Y + Y ) and (Z + Z). The second term has two
vari abl es. To make i t of three vari abl es i t i s mul ti pl i ed by (X + X ). After mul ti pl i cati on the
gi ven l ogi c expressi on can be wri tten as
X(Y + Y ) (Z + Z) + YZ(X + X), as Y + Y = 1, Z + Z = 1 and X + X = 1
= (XY + XY ) (Z + Z) + XYZ + X YZ
= XYZ + XYZ + XY Z + XY Z + XYZ + X YZ
LOGI C DESI GN 4.17
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= XYZ + XYZ + XY Z + XY Z + X YZ,
as XYZ + XYZ = XYZ
Example 3. Convert the fol l owi ng expressi on i nto canoni cal form:
XZ + XYW + XZW
To i ntroduce the mi ssi ng vari abl es i n each term the above expressi on can be wri tten as
XZ (Y + Y ) (W + W) + X YW (Z + Z) + XZW (Y + Y )
= (XYZ + XYZ) (W + W) + XYZW + XYZW + XYZW +XYZW
= XYZW + XYZW + XYZW + XYZW+ XYZW + XYZW + XYZW + XYZW
= XYZW + XYZW + XYZW + XYZW+ XYZW + XYZW
as 2nd and 7th terms, and 4th and 8th terms are the same.
4.1.13 Conversion of Product of Sums Expressions into Canonical Form
Before we proceed for such conversi on a few i denti ti es shoul d be exami ned.
(i) We can wri te A = (A + B) (A + B)
Thi s can be proved as fol l ows:
A = A + A + 0
= A(B + B) + A.A + B. B, as B + B = 1
= AB + AB + AA + BB
= A(A + B) + B(A + B)
= (A + B) (A + B)
(ii) Si mi l arl y, we can wri te A + B = (A + B + C) (A + B + C )
(A + B + C) (A + B + C ) = AA + AB + AC + AB + BB + BC + AC + BC + CC
Rearrangi ng the terms we get
AA + BB + AC + BC + AC + BC + AB + AB, as CC = 0
= (A + B) + C (A + B) + C (A + B) + AB + AB
= (A + B) + (A + B) (C + C ) + AB + AB
= A + AB + B + AB
= A (1 + B) + B (1 + A)
= A + B
Thi s techni que can be extended to any number of vari abl es such as
(A + B + C) = (A + B + C + D) (A + B + C + D)
Example 1. Convert the fol l owi ng expressi on i nto canoni cal form:
(A + B) (B + C)
4.18 COMPUTER FUNDAMENTALS
To convert the above expressi on i nto canoni cal form the fol l owi ng i denti ty can be used:
X + Y = (X + Y + Z) (X + Y + Z)
Appl yi ng the above i denti ty, the gi ven l ogi c expressi on can be wri tten as
(A + B + C) (A + B + C ) (A + B + C ) (A + B + C)
= (A + B + C) (A + B + C ) (
A
+ B + C)
Example 2. Convert the fol l owi ng expressi on i nto canoni cal form:
X(Y + Z)
The fi rst term i s of a si ngl e vari abl e. I t can be fi rst extended to two vari abl es
X = (X Y) (X Y) + +
Now the gi ven l ogi c expressi on can be wri tten as
(X + Y) (X Y) (Y Z) + +
Now extendi ng each term to three vari abl es we get
(X + Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z)
= (X + Y + Z) (X + Y +
Z
) (X +
Y
+ Z) (X +
Y
+
Z
) (
X
+
Y
+
Z
)
as the 4th and 5th terms are the same.
Example 3. Wri te the fol l owi ng expressi on i n canoni cal form:
(A + B + C ) (A + D)
The above expressi on can be wri tten as
(A + B + C + D) (A + B + C + D) (A + C + D) (A + C + D)
= (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
(A + B + C + D) (A +
B
+ C + D)
= (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
as the 1st and 5th terms are the same.
4.1.14 Truth Tables and Boolean Expressions
The behavi our of a l ogi c network may be descri bed by truth tabl es or l ogi c expressi ons.
For a gi ven l ogi c expressi on a truth tabl e can be formed. Si mi l arl y, for a gi ven truth tabl e
a l ogi c expressi on can be obtai ned. A tabl e contai ni ng al l possi bl e val ues of the i nput vari abl es
(or i ndependent vari abl es) and the correspondi ng val ues of the output (or dependent vari -
abl es), i s known as truth table.
Truth Table for Boolean Expression
Take a functi on F = X + Y. To fi nd i ts truth tabl e, al l possi bl e val ues of X and Y are
wri tten as shown i n Tabl e 4.16. For a gi ven set of val ues of X and Y, correspondi ng val ue
of Z i s obtai ned and tabul ated as shown i n Tabl e 4.16.
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Table 4.16 Truth Table of F =X +Y
X Y Z =X + Y
0 0 1
0 1 0
1 0 1
1 1 1
Let us consi der another functi on F = X + YZ, and wri te al l possi bl e val ues of X, Y and
Z. Fi nd correspondi ng val ues of F as shown i n Tabl e 4.17.
Table 4.17 Truth Table of F =X +YZ
X Y Z F =X +YZ
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
4.1.15 Boolean Expression in Sum of Products Form from a Given Truth Table
I f a truth tabl e to descri be the behavi our of a l ogi c network i s gi ven, the correspondi ng
l ogi c expressi on can be obtai ned ei ther i n sum of products form or product of sums form. The
fol l owi ng exampl e wi l l i l l ustrate the procedure to obtai n the l ogi c expressi on i n sum of
products form.
Example. Tabl e 4.18 descri bes the behavi our of a di gi tal ci rcui t. Fi nd the correspondi ng
l ogi c expressi on i n sum of products form to descri be the behavi our of the ci rcui t.
Table 4.18
X Y Z F =f(X, Y, Z)
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
F = f (X, Y, Z) i s the desi red l ogi c expressi on. I ts val ues are gi ven i n the tabl e corre-
spondi ng to each set of val ues of X, Y and Z. A sum of products expressi on i s obtai ned by
sel ecti ng those product terms for whi ch the functi on F = 1 and l ogi cal l y addi ng them. I n the
4.20 COMPUTER FUNDAMENTALS
5th, 6th and 8th rows we fi nd F = 1. The product term for the 5th row wi l l be XY Z whi ch
makes F = 1 for the gi ven set of val ues of vari abl es X, Y and Z. The product term XY Z wi l l
be 0 for any other set of val ues of X, Y and Z. So i t descri bes the condi ti on of the 5th row
of the truth tabl e. Si mi l arl y, product terms whi ch gi ve F = 1 are XY Z and XYZ for 6th and
8th rows respecti vel y. The desi red l ogi cal expressi on i s gi ven by
F = XY Z + XYZ + XYZ
Thi s functi on wi l l sati sfy the Truth Tabl e 4.18. Thi s expressi on i s i n canoni cal sum of
pr oducts for m. Each ter m of thi s expr essi on i s mutual l y excl usi ve (See defi ni ti on i n
Sec. 4.1.11). Each term of the above expressi on corresponds to onl y one row i n whi ch F =
1. Thus the expressi on corresponds to the col l ecti on of three rows. For the remai ni ng fi ve
rows thi s expressi on wi l l have F = 0. So the expressi on sati sfi es Truth Tabl e 4.18.
The above expressi on can be si mpl i fi ed as
F = XY Z + XZ(Y + Y)
= XY Z + XZ
= X(Z + ZY)
= X(Z + Y) by Theorem 24(a)
= XY + XZ
4.1.16 Boolean Expression in Product of Sums Form from a Given Truth Table
A product of sums expressi on can be formed for Truth Tabl e 4.18 by sel ecti ng those sum
terms for whi ch F = 0 and mul ti pl yi ng them. The 1st row gi ves F = 0. The sum term i s
(X + Y + Z). The 2nd terms i s al so 0, the correspondi ng sum term whi ch gi ves F = 0 i s
(X + Y + Z). Si mi l arl y, al l other sum terms are formed and the desi red expressi on i s gi ven
bel ow:
F = (X + Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z).
Thi s expressi on can be si mpl i fi ed on appl yi ng i denti ty (ii) of Sec. 4.1.13 to
F = (X + Y) (X + Y) (X + Y + Z )
= X(
X
+ Y + Z ), appl yi ng i denti ty (i) of Sec.
4.1.13.
= XX + XY + XZ
= XY + XZ
Now i t can be seen that the l ogi c expressi ons (for Truth Tabl e 4.18) i n sum of products
form and product of sums form are equi val ent. A general i zed proof for thi s i s al so gi ven i n
Secti on 4.1.17.
4.1.17 Proof for Obtaining Expression in Product of Sums Form from a Given
Truth Table
Our ai m i s to obtai n a l ogi cal expressi on of a di gi tal system whi ch behaves accordi ng to
the truth tabl e gi ven i n Tabl e 4.18. Thi s tabl e can be rewri tten as shown i n Tabl e 4.19 wi th
an addi ti onal col umn
F
.
LOGI C DESI GN 4.21
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For the compl ementary functi on
F
we can wri te an expressi on i n mi nterm canoni cal form:
F = X Y Z + X Y Z + X Y Z + X YZ + XYZ
F =
F
= (X Y Z + X YZ + X Y Z + X YZ + XYZ)
Appl yi ng Demorgan s theorem thi s can be wri tten as
F =
(X Y Z) X YZ) X Y Z) X YZ) XYZ) ( ( ( (
= (X + Y + Z) (X + Y + Z) (X + Y + Z) (X + Y + Z)
(X + Y + Z)
Thi s expressi on can al so be wri tten di rectl y by col l ecti ng those sum terms for whi ch
F = 0, as we have done i n Sec. 4.1.16. So al gebrai cal l y i t has been proved that the techni que
used i n Sec. 4.1.16 i s correct.
Table 4.19
X Y Z F F
0 0 0 0 1
0 0 1 0 1
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0 0 1
1 1 1 1 0
4.1.18 Implementing Logic Expressions with Logic Gates
(i) Logic Expression in Sum of Product Form
I f l ogi c expressi ons are gi ven i n sum of products form the l ogi c network can be real i zed
using AND-OR gates or onl y NAND gates. Take a si mpl e expressi on gi ven bel ow:
Z = AB + CD
The gi ven expressi on wi l l requi re two AND gates and one OR gate. The l ogi c ci rcui t i s
shown i n Fi g. 4.3. As NAND gates are uni versal gates, they are used as bui l di ng bl ocks for
the real i zati on of l ogi c networks. An AND-OR network shown i n Fi g. 4.3 can be repl aced by
an equi val ent NAND network as shown i n Fi g. 4.4. Si mi l arl y, a sum of products expressi on
havi ng more vari abl es can be real i zed usi ng AND-OR or equi val ent NAND network.
Fig. 4.3 AND-OR Network to real i se l ogi c expressi on Z = AB + CD.
4.22 COMPUTER FUNDAMENTALS
Fig. 4.4 NAND network to real i ze l ogi c expressi on Z = AB + CD.
Take another exampl e gi ven bel ow:
Y = ABC + ABC + ABC
Fi gs. 4.5 and Fi g. 4.6 show AND-OR and NAND network respecti vel y for the above l ogi c
expressi on.
Fig. 4.5 AND-OR Network for l ogi c expressi on Y = ABC + ABC + ABC.
Fig. 4.6 NAND Network for l ogi c expressi on Y = ABC + ABC + ABC.
(ii) Logic Expressions in Product of Sums Forms
I f l ogi c expressi ons are gi ven i n product of sums forms, the l ogi c network can be real i zed
usi ng OR-AND gates or onl y NOR gates. Take an exampl e gi ven bel ow:
W = (A + B + C) (X + Y + Z)
Fi gs. 4.7 and 4.8 show OR-AND and NOR network respecti vel y for the above l ogi c
expressi on.
LOGI C DESI GN 4.23
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Fig. 4.7 OR-AND Network for l ogi c expressi on W = (A + B + C) ( X + Y + Z).
Fig. 4.8 NOR Network for l ogi c expressi on W = (A + B + C) (X + Y + Z).
4.2 MINIMUM BOOLEAN EXPRESSION
A l ogi c expressi on i s si mpl i fi ed before a l ogi c network i s real i zed usi ng l ogi c gates. The
si mpl i fi cati on i s essenti al to mi ni mi ze the cost of the l ogi c network. The expressi on must be
mi ni mi zed before i mpl ementati on. I t shoul d be ei ther a mi ni mum sum of products or mi ni -
mum product of sums. A mi ni mum sum of products i s one whi ch contai ns ei ther mi ni mum
number of terms of products or mi ni mum number of l i teral s. Si mi l arl y, a mi ni mum product
of sum i s one whi ch contai ns mi ni mum number of l i teral s or mi ni mum number of factors.
The type of mi ni mum expressi on desi red, contai ni ng mi ni mum terms or mi ni mum l i teral s,
depends on the ci rcumstances.
We have al ready seen that a l ogi c expressi on can be si mpl i fi ed by al gebrai c method usi ng
Bool ean theorems. The drawback of thi s techni que i s that there are no speci fi c rul es for
proceedi ng step by step to mani pul ate the process of si mpl i fi cati on. Even i f a mi ni mum i s
obtai ned, one may not be sure that i t i s mi ni mum. I f the expressi on i s qui te compl ex, i t i s
very di ffi cul t to obtai n a mi ni mum by al gebrai c mani pul ati on. For mi ni mi zati on of Bool ean
functi ons havi ng more than three vari abl es the al gebrai c method becomes i nconveni ent. The
Karnaugh map method provi des a si mpl e strai ghtforward techni que of si mpl i fi cati on of l ogi c
expressi ons. Thi s i s di scussed i n the next secti on.
4.3 KARNAUGH MAP METHOD OF SIMPLIFICATION OF LOGIC EXPRESSION
The Karnaugh map method i s a graphi cal techni que for si mpl i fyi ng Bool ean functi ons.
The Karnaugh map i s a two-di mensi onal representati on of a truth tabl e. I t provi des a si mpl er
method for mi ni mi zi ng l ogi c expressi ons. The map method i s i deal l y sui ted for four or l ess
vari abl es. But i t becomes cumbersome for fi ve or more vari abl es. A Karnaugh map i s a
di agram consi sti ng of squares. Each square of the map represents a mi nterm. Any l ogi c
4.24 COMPUTER FUNDAMENTALS
expressi on can be wri tten as a sum of products, i .e. sum of mi nterms. Therefore, a l ogi c
expressi on can easi l y be represented on a Karnaugh map.
A Karnaugh map for n vari abl es i s made up of 2
n
squares. Each square desi gnates a
product term of a Bool ean expressi on. For product terms whi ch are present i n the expressi on,
1s are wri tten i n the correspondi ng squares; 0s are wri tten i n those squares whi ch corre-
spond to product terms not present i n the expressi on. For cl ari ty of the map wri ti ng of 0s
can be omi tted. So bl ank squares i ndi cate that they contai n 0s.
Fi rst l et us consi der a map of two vari abl es as shown i n Fi g. 4.9(a) to expl ai n the
pri nci pl e. The fi rst row i s for B, the 2nd row for B. Si mi l arl y, 1st col umn i s for A and 2nd
col umn for A. For any square, see the vari abl es i n both row as wel l as col umn. For the 1st
square of the 1st row, vari abl es are B and A , and hence i t wi l l represent the product term
A B. For the 2nd square of the 1st row, the vari abl es are A and B, so i t represents A B.
Fig. 4.9 Two vari abl e Karnaugh Map.
0 and 1 wri tten at the top of the map shown i n Fi g. 4.9(b) i ndi cate 0 and 1 l ogi c for
variable A. I n other words 0 represents A , and 1 represents A. Si mi l arl y, 0 and 1 l ogi c are
for vari abl e B (i .e. 0 represents
B
and 1 represent B).
Suppose the Karnaugh maps are to be drawn for the Bool ean functi ons gi ven bel ow:
(a) Y = A
B
+ AB
(b) Y =
A B
+
A
B
I n these functi ons onl y two product terms are present. So 1s are wri tten i n the corre-
spondi ng squares as shown i n Fi g. 4.10(a) and (b).
Fig. 4.10 Karnaugh map for (a) Y = AB + AB (b) Y = A B + A B.
From the map shown i n Fi g. 4.9 i t can be seen that two adjacent squares di ffer onl y by
one vari abl e. They can be grouped for si mpl i fi cati on. Larger number of adjacent squares show-
i ng 1 can al so be grouped for si mpl i fi cati on. The fol l owi ng exampl es wi l l show the procedure.
LOGI C DESI GN 4.25
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Example 1. Si mpl i fy Y =
A B AB +
Draw Karnaugh map of the above functi on as shown i n Fi g. 4.11.
Fig. 4.11 Karnaugh map for Y = A B + AB.
Two adjacent squares contai ni ng 1 have been grouped together. To show the groupi ng,
they have been enci rcl ed. For si mpl i fi cati on we have to see that whi ch vari abl e i s common
to both squares. I n thi s case
B
i s common to both as the 1st row is for
B
. So thei r
si mpl i fi cati on wi l l resul t Y =
B
. Thi s can be veri fi ed al so al gebrai cal l y as fol l ows:
Y =
A B AB +
=
B (A + A)
=
B
So the vari abl e whi ch i s common to adjacent squares i s sel ected, and the vari abl e whi ch
i s not common i s di scarded.
Example 2. Si mpl i fy Y = AB + AB + AB
Fi g. 4.12 shows the Karnaugh map of the above functi on. Groups of adjacent 1-squares
are made as shown i n the fi gure. I n thi s case the 2nd col umn of the 2nd row i s common to
both groupi ngs. The group of hori zontal 1-squares gi ves resul t = B, and verti cal 1-squares =
A. So the si mpl i fi ed expressi on i s Y = A + B.
Fig. 4.12 Karnaugh map of Y = AB + AB + AB.
The resul t obtai ned by map method can al so be veri fi ed al gebrai cal l y as fol l ows:
Y =
AB + AB + AB
= A B + AB + AB + AB
= B(A + A) + A(B + B)
= B + A
Fi g. 4.13(a), (b), (c) and (d) show Karnaugh maps and si mpl i fi cati on of the fol l owi ng
functi ons:
4.26 COMPUTER FUNDAMENTALS
(a) Y =
A B + A B
(b) Y =
A B + AB
(c) Y = A B + A B + AB
(d) Y = A B + A B
Fig. 4.13 Karnaugh map for a few functi ons.
4.3.1 Karnaugh Map for Three Variables
Fi g. 4.14(a) shows Karnaugh map for three vari abl es. Fi g. 4.14(b) shows the al ternati ve
way of representi ng the vari abl es. The orderi ng of the vari abl es, i .e., 00, 01, 11, 10 i s i n Gray
(refl ected bi nary) code. One shoul d not wri te strai ght bi nary codes, i .e., 00,01, 10 and 11. The
strai ght bi nary codes are used i n Vei tch di agram. Mr. Karnaugh modi fi ed the Vei tch di agram
and used refl ected bi nary codes.
Whi l e formi ng groups of adjacent squares contai ni ng 1s the fol l owi ng consi derati ons
must be kept i n mi nd:
(i) Every square contai ni ng 1 must be consi dered at l east once.
(ii) A square contai ni ng 1 can be i ncl uded i n as many groups as desi red.
(iii) A group must be as l arge as possi bl e.
LOGI C DESI GN 4.27
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Fig. 4.14 Karnaugh map for three vari abl es.
(iv) A square contai ni ng 1 shoul d not be l eft al one to be i ncl uded i n the fi nal expres-
si on, i f there i s possi bi l i ty of i ts i ncl usi on i n a group of two squares contai ni ng 1.
Si mi l arl y, a group of two 1-squares (squares contai ni ng 1) shoul d not be made i f
these 1-squares can be i ncl uded i n a group of four 1-squares; and so on.
(v) The number of squares i n a group must be equal to 2
n
, such as 2, 4, 8, 16 etc. I t
cannot be 3, 5, 6, 7, 9, etc.
(vi) The map i s consi dered to be fol ded or cyl i ndri cal . Therefore, squares at the ends
of a row or col umn are treated as adjacent squares.
(vii) The si mpl i fi ed l ogi c expressi on obtai ned from Karnaugh map i s not uni que. Group-
i ngs of 1-squares can be made i n di fferent ways, whi ch resul ts i n more than one
l ogi c expressi ons.
(viii) Before drawi ng Karnaugh map the l ogi c expressi ons must be i n canoni cal (or
expanded) forms.
The fol l owi ng exampl es wi l l i l l ustrate the procedure of si mpl i fi cati on.
Example 1. Si mpl i fy the functi on Y = ABC + ABC, by Karnaugh map method.
Fi g. 4.15 shows the Karnaugh map for Exampl e l . The squares contai ni ng 1s are adjacent
squares. So they can be grouped together. The vari abl es AB are common to both squares, so
they are sel ected. There i s no other vari abl e common both squares. So uncommon vari abl es,
i .e. C and C are di scarded. The si mpl i fi ed functi on wi l l be
Y = AB
Fig. 4.15 Karnaugh map for Exampl e 1.
Example 2. Usi ng Karnaugh map method si mpl i fy the expressi on
Y = A B C + AB C
4.28 COMPUTER FUNDAMENTALS
Fig. 4.16 Karnaugh map for Exampl e 2.
Fi gure 4.16 shows the Karnaugh map for Exampl e 2. Observe the di agram from both row
wi se and col umn wi se for common vari abl es. Row wi se i t i s seen that C i s common to both
1-squares. Col umn wi se i t i s seen that A i s common to both. So consi deri ng al l the three
variables A C i s common to both squares. The si mpl i fi ed functi on i s
Y = A C
Example 3. Si mpl i fy the functi on Y = A B C + ABC A B C +
Fig. 4.17 Karnaugh map for Exampl e 3.
Fi gure 4.17 shows the Karnaugh map for Exampl e 3. Groups of adjacent 1-squares have
been made as shown i n the fi gure. I n thi s case the square representi ng A B C i s common
to two groups. The si mpl i fi ed functi on i s
Y = A B + A C
Thi s expressi on i s the mi ni mum sum of products. I t contai ns 4 l i teral s. I t wi l l requi re
two AND gates and one OR gate for i ts real i zati on. But i f i t i s expressed i n product of sums
form i t wi l l be
Y = A B + C) ( ,
Thi s contai ns onl y 3 l i teral s. I t wi l l requi re one AND gate and one OR gate. Thus we
see that we have to consi der both forms of si mpl i fi ed expressi on before the i mpl ementati on
of Bool ean functi on.
Example 4. Si mpl i fy the functi on Y = A B C A B C +
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Fi gure 4.18 shows the Karnaugh map for Exampl e 4. The squares at the ends of a row
or col umn are consi dered to be adjacent squares because the map i s treated as a fol ded or
cyl i ndri cal one. So two 1-squares of Fi g. 4.18 are adjacent squares. They can be grouped
together. The si mpl i fi ed functi on wi l l be
Y = B C
Fig. 4.18 Karnaugh map for Exampl e 4.
Example 5. Si mpl i fy Y = A B C AB C + A BC +
Fig. 4.19 Karnaugh map for Exampl e 5.
Fi gure 4.19 shows the Karnaugh map for Exampl e 5. I n thi s exampl e we see that there
are three adjacent squares contai ni ng 1. As the number of 1-squares i n a group must be some
power of 2 such as 2, 4, 8, 16 and so on. We cannot form the group of 3. So two groups of
1-squares have been formed as shown i n the fi gure. The si mpl i fi ed functi on wi l l be
Y = A C BC +
Example 6. Si mpl i fy Y = AB C AB C ABC ABC + + +
Fi gure 4.20 shows the Karnaugh map for Exampl e 6. I f we observe col umn wi se, we fi nd
that the vari abl e A i s common to al l the four squares. I f we see row wi se, no vari abl e i s
common to al l the four squares. Therefore, the functi on after si mpl i fi cati on i s
Y = A
Example 7. Fi g. 4.21 represents a Bool ean functi on on a three vari abl e Karnaugh map.
Fi nd the Bool ean functi on.
4.30 COMPUTER FUNDAMENTALS
Fig. 4.20 Karnaugh map for Exampl e 6.
Fig. 4.21 Karnaugh map for Exampl e 7.
I n Fi g. 4.21 four 1-squares are adjacent squares. So they have been grouped together.
From row si de C i s common to al l 1-squares. From col umn si de no vari abl e i s common to
al l . So the common vari abl e i s sel ected, and uncommon are di scarded. The si mpl i fi ed functi on
wi l l be
Y = C
Example 8. Fi g. 4.22 represents a Bool ean functi on on a three vari abl e Karnaugh map.
Fi nd the Bool ean functi on.
As the Karnaugh map i s treated as a cyl i ndri cal map, four 1-squares of Fi g. 4.22 are
adjacent squares. The vari abl e B i s common to al l 1-squares. The si mpl i fi ed functi on i s gi ven
by
Y = B
Fig. 4.22 Karnaugh map for Exampl e 8.
LOGI C DESI GN 4.31
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4.3.2 Karnaugh Map for Four Variables
The representati on of vari abl es and product terms of a four vari abl e Karnaugh map i s
shown i n Fi g. 4.23.
Fig. 4.23 Four vari abl e Karnaugh map.
The following examples illustrate the method of simplification of four variable Boolean functions.
Example 9. Si mpl i fy Y = ABCD + ABCD + ABCD + ABCD + A B C D
Fi g. 4.24 shows the Karnaugh map of Exampl e 9.
Four 1-squares bei ng adjacent squares have been grouped together. Column wi se the
vari abl e B i s common to al l the four squares. Row wi se the vari abl e D i s common to al l the
four squares. So these four squares wi l l gi ve BD after si mpl i fi cati on. The square representi ng
A B C D
i s l eft al one, so i t i s to be consi dered as a group of si ngl e 1-square. The si mpl i fi ed
functi on i s gi ven by
Y = BD + A B C D
Fig. 4.24 Karnaugh map for Exampl e 9.
4.32 COMPUTER FUNDAMENTALS
Example 10. Fi gure 4.25 represents a l ogi c functi on on a four vari abl e Karnaugh map.
Fi nd the l ogi c functi on.
Fig. 4.25 Karnaugh map for Exampl e 10.
Groupi ngs of 1-squares have been shown i n the fi gure. I n the 1st group there are four
adjacent 1s. From row wi se C D i s common to these 4 adjacent squares. From col umn wi se
no vari abl e i s common to al l the four squares. So these four squares resul t i n C D. I n the
2nd group there are two 1-squares. From row wi se CD i s common to them. From col umn
wise A i s common to both. So these two squares gi ve ACD. The si mpl i fi ed expressi on i s
Y = ACD + C D
Example 11. Fi gure 4.26 represents a Bool ean functi on on a four vari abl e Karnaugh
map. Fi nd the Bool ean functi on.
Fig. 4.26 Karnaugh map for Exampl e 11.
LOGI C DESI GN 4.33
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Two 1-squares at the l eft edge and two 1-squares at the ri ght-edge are consi dered
adjacent because the map i s treated as a cyl i ndri cal map wi th l eft and ri ght edges touchi ng
each other. Thi s group of four squares corresponds to the term DB. Agai n one square at the
top and one at the bottom i s grouped together as the map i s al so treated as top and bottom
edges touchi ng each other. Thi s group of two squares corresponds to the term
ABD
. The
si mpl i fi ed Bool ean functi on i s gi ven by
Y = ABD + DB
Example 12. Fi gure 4.27 represents a Bool ean functi on on a four vari abl e Karnaugh
map. Fi nd the Bool ean functi on.
Fig. 4.27 Karnaugh map for Exampl e 12.
Seei ng the map row wi se, the vari abl e
D
i s common to al l the four squares. Seei ng the
map col umn wi se, the vari abl e
B
i s common to al l the four squares. Therefore, B i s common
to al l the four squares. The si mpl i fi ed Bool ean functi on i s gi ven by
Y = B D
Example 13. Fi gure 4.28 represents a Bool ean functi on on a four vari abl e Karnaugh
map. Fi nd the Bool ean functi on.
4.34 COMPUTER FUNDAMENTALS
Fig. 4.28 Karnaugh map for Exampl e 13.
There are two possi bl e groups of 1-squares as shown i n Fi gs. 4.28(a) and (b). Correspond-
i ng to Fi g. 4.28(a) the si mpl i fi ed Bool ean functi on i s
Y = ABC + BCD +ACD
Correspondi ng to Fi g. 4.28(b) the si mpl i fi ed Bool ean functi on i s
Y = A BC + A BD + ACD
Thus we see that the Bool ean functi on obtai ned from a Karnaugh map may not be uni que.
4.3.3 Prime Implicant
I n a sum of products expressi on each product term i s known as implicant. On a Karnaugh
map each i mpl i cant rel ates to a si ngl e 1-square or a group of adjacent 1-squares. I n other
words on a Karnaugh map an i mpl i cant i s denoted by an encl osure contai ni ng adjacent 1-
squares or a si ngl e 1-square. A prime implicant i s an i mpl i cant whi ch cannot be whol l y
encl osed by a l arger i mpl i cant on a Karnaugh map. A nonessenti al pri me i mpl i cant can be
removed wi thout l eavi ng any 1-square unencl osed. Fi g. 4.29 shows pri me and nonpri me
i mpl i cants. Fi g. 4.30 shows essenti al and nonessenti al pri me i mpl i cants.
Fig. 4.29 Pri me and nonpri me i mpl i cant.
LOGI C DESI GN 4.35
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Fig. 4.30 Essenti al and nonessenti al pri me i mpl i cant.
4.3.4 Labelling of Karnaugh Map Squares
The squares of a Karnaugh map can be numbered as shown i n Fi g. 4.31. These numbers
are equal to the bi nary equi val ent of the l ogi c val ues of the correspondi ng mi nterm vari abl es.
The number i n the 3rd col umn of the 1st row i s 12. Thi s square i s for the mi nterm AB CD.
The l ogi c val ues of ABC D are 1100 whi ch i s equal to the deci mal number 12. I f posi ti ons
of AB and CD are i nterchanged as shown i n Fi g. 4.32, the numberi ng of square wi l l al so
change. I n thi s di agram the mi nterm ABC D i s i n 3rd row and 1st col umn. The l ogi c val ues
for the 3rd row, 1st col umn are 1100, i .e. 12 (deci mal ).
Fig. 4.31 Numberi ng of 4-vari abl e Karnaugh map squares.
4.36 COMPUTER FUNDAMENTALS
Fig. 4.32 Label l i ng of 4-vari abl e Karnaugh map squares.
Si mi l arl y, 3-vari abl e Karnaugh map can al so be numbered as shown i n Fi gs. 4.33(a) and
(b). The mi nterm for the 1st row, 3rd col umn of Fi g. 4.33(a) is ABC . The l ogi c val ues of
vari abl es of thi s mi nterm are 110 (i .e. 6 deci mal ). Si mi l arl y, for 1st row, 4th col umn, the
mi nterm i s AB C . The l ogi c val ues of the vari abl es of thi s mi nterm are 100 (i .e. 4 deci mal ).
Fig. 4.33 Numberi ng of squares of 3-vari abl e Karnaugh map.
LOGI C DESI GN 4.37
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4.3.5 Alternative Way of Representing Sum of Products Expression
The fol l owi ng exampl es wi l l i l l ustrate the procedure:
Example 14. Consi der the fol l owi ng Bool ean functi on:
Y = A BC + ABC + ABC
Thi s can al so be represented as
Y (A, B, C) = (2, 6, 7) or m (2, 6, 7), where m stands for mi nterm.
The above expressi on means that the mi nterm correspondi ng to squares 2, 6 and 7 of
the Karnaugh map are present i n the gi ven Bool ean functi on. The squares 2, 6 and 7 wi l l
be marked by 1 and other squares of the map by 0 as shown i n Fi g. 4.34.
Fig. 4.34 Karnaugh map for Exampl e 14.
Example 15. Draw the Karnaugh map for the fol l owi ng Bool ean functi on:
Y (A, B, C, D) = m (4, 5, 10, 11, 15)
or (4, 5, 10,1 1, 15)
The Karnaugh map of the above Bool ean functi on i s as shown i n Fi g. 4.35.
Fig. 4.35 Karnaugh map for Exampl e 15.
4.38 COMPUTER FUNDAMENTALS
4.3.6 Realization of Product of Sums Expression from Karnaugh Map
To real i ze a product of sums expressi on from a Karnaugh map groups of 0-squares are
made, and fi rst a sum of products of compl ementary functi on i s obtai ned. Then appl yi ng
Demorgans l aw the product of sums expressi on i s obtai ned.
Example 16. Fi nd the mi ni mum product of sums expressi on from the Karnaugh map
shown i n Fi g. 4.36.
Groups of 0-squares are made as shown i n Fi g. 4.36. The compl ementary functi on wi l l be
F
(A, B, C, D) =
AB + A C C D +
Fig. 4.36 Karnaugh map for Exampl e 16.
Appl yi ng Demorgans l aw, the fol l owi ng mi ni mum product of sums i s obtai ned
F (A, B, C, D) =
(AB + A C C D) +
= (A B) (A C) (C D) + + +
This final expression can also be written directly by applying the technique given in Sec. 4.3.7.
The squares contai ni ng 0s of Fi g. 4.36 can al so be represented as
F (A, B, C, D) = (0, 1, 4, 5, 8, 12, 13, 14, 15)
or M (0, 1, 4, 5, 8, 12, 13, 14, 15)
where M represents maxterm.
Example 17. Fi nd the mi ni mum product of sums from the Karnaugh map shown i n Fi g.
4.37.
Groups of 0-squares are made as shown in Fig. 4.37. The complementary function is given by
F
(A, B, C) =
A C BC +
Appl yi ng Demorgans l aw, we have
F (A, B, C) =
(A C BC) +
=
(A C) (B C) + +
LOGI C DESI GN 4.39
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Thi s expressi on can al so be wri tten di rectl y by appl yi ng the techni que gi ven i n Sec 4.3.7.
Fig. 4.37 Karnaugh map for Exampl e 17.
4.3.7 Karnaugh Map for Product of Sums Expression
I n thi s case we have to see that the sum term for a parti cul ar square of a Karnaugh
map shoul d be 0. Consi der the Karnaugh map shown i n Fi g. 4.38. The 1st row and 1st col umn
wi l l be 0, if A + B + C = 0. I n other words the sum term for the 1st row, 1st col umn i s (A
+ B + C). Si mi l arl y, the sum terms for the 1st row, 4th col umn wi l l be
A
+ B + C. Agai n,
the sum term for the 2nd row, 4th col umn wi l l be
A
+ B + C . Appl yi ng thi s rul e a Karnaugh
map for a gi ven product of sums expressi on can be drawn.
Fig. 4.38 Karnaugh map showi ng sum terms.
Example 18. Represent the fol l owi ng product of sums expressi on on Karnaugh map and
si mpl i fy:
Y = (A + B + C ) (A + B + C) (A + B + C)
or Y(A, B, C) = M(0, 1, 3) or si mpl y (0, 1, 3)
Fig. 4.39 Karnaugh map for Exampl e 18.
4.40 COMPUTER FUNDAMENTALS
Fi gure 4.39 shows the Karnaugh Map of Exampl e 18. Two groups of adjacent 0-squares
have been made as shown i n the fi gure. Whi l e si mpl i fyi ng the product of sums expressi ons
by Karnaugh map method, the common vari abl es whi ch have 0-l ogi c are taken as they are,
but the vari abl es whi ch have 1-l ogi c are compl emented.
The verti cal two 0-squares have common vari abl es A and B wi th 0-l ogi c. There i s no
common vari abl e from rowsi de. So thei r sum (A + B) i s taken. Agai n the 2nd encl osure
contai ni ng two hori zontal 0-squares has C common wi th l ogi c 1, so i ts compl ement i s taken.
From col umn si de A wi th 0 l ogi c i s common and so A i s taken. Thei r sum i s (A + C ). The
resul t obtai ned from these two encl osures i s mul ti pl i ed to obtai n the si mpl i fi ed Bool ean
functi on. The si mpl i fi ed functi on i s
Y = (A + B) (A +
C
)
Example 19. Represent the fol l owi ng Bool ean functi ons on Karnaugh map, and si mpl i fy
i t:
Y = (A + B + C + D) (A + B + C + D) (A + B + C + D)
or Y(A, B, C, D) = M(6, 7, 15)
Fi gure 4.40 shows the Karnaugh map of the above Bool ean functi on. The two groups of
adjacent 0-squares have been made as shown i n the fi gure. For the encl osure I col umn wi se,
the vari abl e B wi th 1-l ogi c i s common, so i t i s compl emented, i .e.
B
i s taken. Row wi se CD
wi th 1-l ogi c i s common, so (C + D) i s to be consi dered. The sum term for the I encl osure wi l l
be (B + C + D). For the encl osure I I col umn wi se, vari abl es are A wi th 0-l ogi c and B wi th
1-l ogi c. So (A + B) i s to be taken. Row wi se the common vari abl e i s C wi th 1-l ogi c, so
C
i s
to be taken. The sum term for I I encl osure wi l l be
(A + B + C)
. The si mpl i fi ed Bool ean
functi on i s gi ven by
Y = (A + B + C) (B + C + D)
Fig. 4.40 Karnaugh map for Exampl e 19.
LOGI C DESI GN 4.41
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4.3.8 Dont-care Conditions
Bool ean expressi ons descri be the behavi our of l ogi c networks. Each square of a Karnaugh
map represents the response (i .e., output) of the network correspondi ng to a combi nati on of
l ogi c val ues of the i nput vari abl es. Someti mes, certai n i nput combi nati ons never occur. I n
such si tuati ons the output of the l ogi c network (i .e., mi nterms on the Karnaugh map) are not
speci fi ed. These si tuati ons are referred to as dont-care condi ti ons. A dont-care condi ti on i s
i ndi cated by a dash or cross on a Karnaugh map. The squares on the Karnaugh map wi th
dash entri es are known as dont-care squares. A dont-care square may be assumed ei ther as
a 1-square or 0-square as desi red whi l e formi ng the groups of squares for si mpl i fi cati on. Any
one of such squares or some of them-may be i ncl uded or may not be i ncl uded whi l e formi ng
groups.
The Karnaugh map shown i n Fi g. 4.41(a) wi th dont care condi ti ons can al so be repre-
sented as
F (A, B, C, D) = m (0, 2, 3, 6, 7, 12, 13, 14) + d (1, 4, 11, 15)
where d denotes dont-care condi ti ons
The above expressi on i s for sum of product expressi on.
The K-map shown i n Fi g. 4.41(b) wi th dont-care condi ti ons for product of sums expres-
si on can al so be wri tten as
F (A, B, C, D) = M (5, 8, 9, 10). d (1, 4, 11, 15).
Example 20. Fi g. 4.41 shows a Karnaugh map wi th dont-care condi ti ons. Fi nd Bool ean
expressi on (a) i n sum of products form, and (b) i n product of sums form.
Fi gure 4.41(a) shows groupi ngs for sum of product expressi on. The si mpl i fi ed Bool ean
functi on i s gi ven by
Y(A, B, C, D) =
A B + AC + AB
4.42 COMPUTER FUNDAMENTALS
Fig. 4.41 Karnaugh map wi th Dont care Condi ti ons for Exampl e 20.
Fi gure 4.41(b) shows groupi ngs for product of sums expressi on. The si mpl i fi ed Bool ean
expressi on wi l l be
Y(A, B, C, D) = (A + C +
D
) (A + B)
4.3.9 Quine-McCluskey Method
Thi s i s a tabul ar method of si mpl i fi cati on. Thi s i s appl i cabl e to any number of vari abl es.
I t i s an al gori thmi c method and programs have been devel oped to i mpl ement i t on a computer.
The mai n ai m of thi s book i s to descri be computer organi zati on. Chapters on di gi tal devi ces
and l ogi c desi gn are background chapters. The i nterested readers can refer to the books
menti oned i n references 17, 18, 19 for thi s method of si mpl i fi cati on of Bool ean expressi ons.
4.4 COMBINATIONAL AND SEQUENTIAL CIRCUITS
There are two types of l ogi c ci rcui tscombi nati onal and sequenti al . A combi nati onal
ci rcui t i s one i n whi ch the state of the output at any i nstant i s enti rel y determi ned by the
states of the i nputs at that ti me. Combi nati onal ci rcui ts are those l ogi c ci rcui ts whose
operati ons can be compl etel y descri bed by a truth tabl e/Bool ean expressi on. A combi nati onal
ci rcui t i s real i zed usi ng AND, OR and NOT gates (or NAND or NOR gates). Exampl es of
combi nati onal ci rcui ts are: adders, subtractors, di gi tal comparators, code converters, decod-
ers, encoders, di gi tal mul ti pl exers/sel ectors, demul ti pl exers, pari ty checker-generators, pro-
grammabl e l ogi c arrays, ROMs, etc.
A sequenti al ci rcui t consi sts of a combi nati onal l ogi c and storage el ements. The output
of a sequenti al ci rcui t i s not onl y a functi on of the present i nputs but al so of past i nputs. The
state of the storage el ements depends upon the precedi ng i nputs and the precedi ng states of
the el ements. Therefore, the output of a sequenti al ci rcui t becomes a functi on of both the
present i nputs and the present i nternal states of the sequenti al ci rcui t. To real i ze sequenti al
ci rcui ts i n addi ti on to AND, OR and NOT gates, fl i p-fl ops are al so requi red. Exampl es of
LOGI C DESI GN 4.43
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sequenti al ci rcui ts are: regi sters, shi ft-regi sters, counters, etc. The two major uses of sequen-
ti al ci rcui ts i n di gi tal systems are:
1. as memori es to store i nformati on whi l e processi ng.
2. as control ci rcui ts to generate control si gnal s whi ch are essenti al to sel ect and
enabl e a sequence of data transfer or data processi ng steps i n the executi on of
mul ti step tasks.
The sequenti al ci rcui ts whi ch empl oy cl ock are cal l ed synchronous sequenti al ci rcui ts.
I n a synchronous sequenti al ci rcui t al l memory el ements are cl ocked l atches or cl ocked fl i p-
fl ops. The desi gn and operati on of sequenti al ci rcui ts i s greatl y si mpl i fi ed by the use of cl ock
si gnal s. Hence, the sequenti al ci rcui ts encountered i n di gi tal systems are mostl y synchronous
sequenti al ci rcui ts. The sequenti al ci rcui ts whi ch do not empl oy cl ock are known as uncl ocked
or asynchronous sequenti al ci rcui ts. Uncl ocked sequenti al ci rcui ts are di ffi cul t to desi gn and
therefore, they are rel ati vel y uncommon.
4.5 ARITHMETIC CIRCUITS
Ari thmeti c operati ons, such as addi ti on, subtracti on, mul ti pl i cati on, di vi si on etc. are
performed by a di gi tal computer, cal cul ator or other di gi tal system. Logi c ci rcui ts for some
i mportant ari thmeti c operati ons are di scussed i n the fol l owi ng secti ons.
4.5.1 Half-Adder
A l ogi c-ci rcui t whi ch performs addi ti on of two bi nary bi ts i s cal l ed a hal f-adder. Tabl e 4.20
i s the truth tabl e for the addi ti on of two bi nary bi ts.
Table 4.20 Truth Table for Half-Adder
I nputs Outputs
A B Sum Carry
S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From Tabl e 4.20 i t i s concl uded that the sum i s equal to A XOR B. I t means that the
outputs of an EXCLUSI VE-OR gate wi l l gi ve the sum. The carry i s equal to A AND B. The
output of an AND gate wi l l gi ve the carry. Fi g. 4.42(a) shows the l ogi c ci rcui t for a hal f-adder
and Fi g. 4.4.2(b) i ts symbol . The expressi on for the sum and carry are as fol l ows:
S = AB + AB
= A B
C = AB
4.44 COMPUTER FUNDAMENTALS
Fig. 4.42 Hal f adder (a) Logi c ci rcui t (b) Symbol .
4.5.2 Full-Adder
When two n-bi t numbers are added, there may be a carry from one stage to the next
stage. The carry comi ng out from one stage i s to be added to the next stage. A hal f-adder
cannot add 3 bi ts as i t has onl y 2 i nput termi nal s. A l ogi c ci rcui t whi ch can add 3 bi ts i s
requi red. The l ogi c ci rcui t whi ch can add 3 bi nary bi ts i s known as ful l -adder. Tabl e 4.21 i s
the truth tabl e for a ful l -adder.
Table 4.21. Truth Table for a Full-Adder
I NPUTS OUTPUTS
A
n
B
n
C
n1
SUM CARRY
S
n
C
n
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
A ful l -adder can be bui l t usi ng two hal f-adders and an OR gate as shown i n Fi g. 4.43.
A l ogi c ci rcui t to behave accordi ng to the truth tabl e gi ven i n Tabl e 4.21 can be real i sed.
The sum of product expressi on for SUM and CARRY for Truth Tabl e 4.21 can be wri tten as
fol l ows:
I t wi l l be easy to wri te l ogi c expressi on i f we assume A
n
= A, B
n
= B, C
n1
= C. We wri te
the product terms when l ogi c val ue of S
n
or C
n
i s equal to 1 .
SUM (S
n
) = A BC + AB C + A B C + ABC
=
A B C + B C) + A B C + BC) ( (
=
A B C) + A B C) ( (
= A B C
= A
n
B
n
C
n1
LOGI C DESI GN 4.45
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CARRY (C
n
) =
ABC + A B C ABC ABC + +
Thi s expressi on can easi l y be reduced by Karnaugh map method. I t can al so be reduced
by al gebrai c method as fol l ows:
Fig. 4.43 A ful l -adder real i zed from two hal f-adders
Fig. 4.44 Ful l -Adder (a) Logi c ci rcui t; (b) Symbol
I f we add two more ABC terms we have,
C
n
= ABC ABC ABC + ABC ABC ABC + + + +
= ABC ABC ABC + ABC ABC ABC + + + +
4.46 COMPUTER FUNDAMENTALS
=
BC(A A) AC(B B) AB(C C) + + + + +
= AB + BC + AC
= A
n
B
n
+ B
n
C
n1
+ A
n
C
n1
A l ogi c ci rcui t for ful l -adder can be real i zed as shown i n Fi g. 4.44(a). I ts symbol i c
representati on i s shown i n Fi g. 4.44(b).
4.5.3 n-Bit Adder
To obtain n-bit adder n number of ful l -adders are connected as shown i n Fi g. 4.45. I n
the l east si gni fi cant stage a hal f-adder i nstead of a ful l -adder can be empl oyed. The sum of
an n-bi t adder i s of n bi ts as the stori ng capaci ty of the regi ster i s onl y of n bi ts. Therefore,
the carry out of the l ast stage i ndi cates overfl ow.
Fig. 4.45 n-bi t adder.
4.5.4 Adder-Subtracter
I n a computer the same ci rcui t performs addi ti on as wel l as subtracti on. The subtracti on
i s performed usi ng 2s compl ement. An adder-subtractor ci rcui t consi sts of a control l ed i n-
verter and n number of ful l -adders. A control l ed i nverter i s shown i n Fi g. 4.46. When
I NVERT termi nal i s l ow, the control l ed i nverter transmi ts the n-bi t i nput to the output.
When I NVERT si gnal i s hi gh, i t transmi ts the 1s compl ement of the i nput. To obtai n 2s
compl ement 1 i s added to 1s compl ement.
Fig. 4.46. Control l ed i nverter.
LOGI C DESI GN 4.47
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An adder-subtracter ci rcui t i s shown i n Fi g. 4.47. I t i ncl udes control l ed i nverter and n
number of ful l adders. For addi ti on A
0
and B
0
are added to gi ve S
0
, A
1
and B
1
are added to
gi ve S
1
and so on. So B
0
, B
1
, ..... B
n
shoul d be appl i ed to ful l adders. For thi s, I NVERT si gnal
of the control l ed i nverter porti on of the ci rcui t has to be l ow. I n Fi g. 4.47, thi s i s marked as
SUB. Thi s l ow si gnal i s al so appl i ed to the carry-i n termi nal of the ful l -adder of the LSB
stage. The ful l adders perform addi ti on of A
n
and B
n
. Thus addi ti on i s performed when SUB
i s l ow.
To perform subtracti on SUB si gnal i s made hi gh. So the control l ed i nverter porti on of
the ci rcui t i nverts B
n
. So 1s compl ement of B
n
i s obtai ned. The SUB si gnal i s al so appl i ed
to the carry-i n termi nal of the ful l -adder of the LSB stage. As SUB i s hi gh, 1 i s added to the
sum of A
0
and B
0
. I t i s a step to make 2s compl ement of B
n
. The ful l adders add A
n
and the
2s compl ement of B
n
. Thus subtracti on i s performed when SUB i s hi gh.
Fig. 4.47 Bi nary adder-subtracter.
4.5.5 High-Speed Addition and Subtraction
Adders and subtracters descri bed so far have consi derabl e amount of del ay because
they are basi cal l y ri ppl e-carry adders and subtracters. At each stage the carry out of the
previ ous stage i s requi red. So unl ess the operati on of the previ ous stage i s performed the
carry bi t i s not avai l abl e. To al l evi ate thi s del ay i n determi nati on of the carry bi ts, each
carry bi t can be determi ned di rectl y from A
n
and B
n
bi ts of i nput numbers and some l ower
order carry. The ci rcui t whi ch generates each carry bi t C
n
shoul d be abl e to see beyond the
i ntermedi ate carry bi ts and work di rectl y wi th the i nputs A
n
, B
n
and some l ower order carry
bi t. The adders and subtracters based on such a scheme for generati ng carry bi ts are known
as l ook-ahead-carry adders and subtracters. For detai l ed anal ysi s and desi gn refer to the
books i n Ref. 12 and 13.
4.48 COMPUTER FUNDAMENTALS
4.5.6. Multiplication of Binary Numbers
Suppose we want to mul ti pl y a
2
a
1
a
0
by b
2
b
1
b
0
. Thi s i s performed as fol l ows:
a
2
a
1
a
0
b
2
b
1
b
0
a
2
b
0
a
1
b
0
a
0
b
0
a
2
b
1
a
1
b
1
a
0
b
1
a
2
b
2
a
1
b
2
a
0
b
2
P
5
P
4
P
3
P
2
P
1
P
0
I n Fi g. 4.4(a) AND gates are shown to obtai n the products of a
i
b
j
. These gates can be
connected as shown i n Fi g. 4.48(b). The mul ti pl i er ci rcui t made of ful l -adders i s shown i n Fi g.
4.48(c). P
5
P
4
P
3
P
2
P
1
P
0
i s the product of a
2
a
1
a
0
and b
2
b
1
b
0
. I f the number of bi ts
i ncreases i n the numbers to be mul ti pl i ed, the si ze of the array of ful l -adders al so i ncreases.
Thi s wi l l i ncrease the del ay through the array. There are i mproved methods of rearrangi ng
the adders to reduce the del ay. For detai l s of vari ous types of mul ti pl i cati on and other
ari thmeti c ci rcui ts refer to the book i n Ref. 12.
LOGI C DESI GN 4.49
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Fig. 4.48 A 3-bi t mul ti pl i er made of ful l -adders.
PROBLEMS
1. Explain AND and OR operati ons wi th sui tabl e exampl es of l ogi c statements and el ectri cal
swi tches. Does AND operati on perform mul ti pl i cati on? Does OR operati on perform addi ti on?
2. What i s the di fference between EXCLUSI VE-OR and I NCLUSI VE-OR?
3. Expl ai n Bool ean vari abl es, Bool ean operati ons and Bool ean expressi ons.
4. What are Bool ean postul ates?
5. What are truth tabl es? Expl ai n wi th sui tabl e exampl es.
6. Fi nd the truth tabl es of the fol l owi ng functi ons:
(a)
XY XY +
(b)
XY X Y +
(c) XY + YZ
[Ans. The val ues i n order wi l l be:
(a) 0, 1, 1,0;
(b) 1, 0, 0, 1 and
(c) 0, 0, 0, 1, 0, 0, 1, 1]
7. What are Bool ean theorems? Di scuss thei r useful ness.
8. Show that:
(a) X + XY = X
(b) X + XY = X + Y
(c)
X. Y X Y = +
(d) (Z + X) (Z + X + Y) = (Z + X) (Z + Y)
9. Si mpl i fy the fol l owi ng l ogi c expressi ons:
(a)
AB A B AB AB + + +
4.50 COMPUTER FUNDAMENTALS
(b)
AC BC A C B C + + +
(c)
ABC ABC ABC AB C + + +
(d)
ABC A BC AB C A B C + + +
[Ans. (a) 1, (b) C, (c) A and (d) B ]
10. Si mpl i fy the fol l owi ng Bool ean expressi ons
(a)
ABC ABC ABC ABC + + +
(b)
ABC A BC ABC A B C + + +
(c)
A BC ABC ABC ABC + + +
(d)
ABC ABC AB C A B C + + +
[Ans. (a) B, (b) A , (c) C and (d) C ]
11. Si mpl i fy the fol l owi ng Bool ean functi ons:
(a)
AB AB BC + +
(b)
A B BA C + + +
(c)
(A B C)ABC + +
(d)
(A B BA)D + +
[Ans. (a) B, (b) 1, (c) 0, (d) D and (e) CA + CB ]
12. Si mpl i fy the fol l owi ng Bool ean functi ons:
(a)
ABC ABCD BC + +
(b)
(A B) AB A AD + + +
(c)
(A B) (A B) + +
(d) (A + B + C) (A B C) + + [Ans. (a) BC, (b) A + D, (c) A and (d) A + B]
13. Show that:
(a) XZ YX YZ XZ YX + + = +
(b)
X XY X Y + = +
(c)
ZX ZXY ZX ZY + = +
(d) (XY YX YZ) X Y XY YZ XY YZ + + + + = +
(e) X XY (X X) (X Y) + = + +
14. What i s the dual of a Bool ean expr essi on? What i s the di ffer ence between dual and
compl ement?
15. Fi nd the dual of the fol l owi ng l ogi c expressi ons:
(a)
1.X. Y Y. X.Z 0 + +
(b)
X. Y(Y Z X) X. Y + + +
(c)
XY XYZ YZ + +
LOGI C DESI GN 4.51
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(d)
(X Y Z) (X Y Z)(X Y Z) + + + + + +
(e)
XY (Y YZ) XZ + +
[Ans. (a) (0 + X + Y)
(Y X Z).1 + +
(b) (X + Y + XYZ) (X + Y )
(c) (X + Y ) (X + Y + Z) (Y + Z)
(d) XYZ + X YZ + XY Z
(e)
[ X + Y + Y(Y + Z)] (X + Z)
16. Fi nd the dual of the fol l owi ng expressi ons:
(a)
(XY + YZ + XYZ) XYZ
(b)
(XZ + YZ) (ZY + XY)
(c)
XY(YX + YZ) + YZ + XY
(d)
(X + Y) (YX + YZ) + YZ
[Ans. (a)
(X + Y) (Y + Z) (X + Y + Z) + X + Y + Z
(b)
(X + Z) (Y + Z) + (Z + Y) (X + Y)
(c)
[ X + Y + (Y + X) (Y + Z)] (Y + Z) (X + Y)
(d)
[ XY + (Y + X) (Y + Z)] (Y + Z)
17. Fi nd the compl ement of the fol l owi ng l ogi c expressi ons:
(a)
X. Y + X.Z
(b)
1. X + Y. Z + 0
(c)
XY (Y + Z) + XY
(d)
X (Y + YZ) + YZ
[Ans. (a) (X + Y) (X + Z)
(b) (0 + X) (Y + Z).1
(c) (X + Y + YZ) (X + Y)
(d) [ X + Y.(Y + Z)] (Y + Z)]
18. What are (a) sum of products form, and (b) product of sums form of l ogi c expressi ons?
Expl ai n wi th sui tabl e exampl es.
19. What i s the canoni cal form of l ogi c expressi ons? Expl ai n mi nterms and maxterms.
20. Expl ai n (a) mi nterm canoni cal form or standard sum of products, and (b) maxterm canoni cal
form or standard product of sums.
21. Convert the fol l owi ng l ogi c expressi ons i nto canoni cal form:
(a)
A + AB
(b)
A + BC
(c) AB + BC
(d) AB + ABC + BCD
[Ans. (a) AB + AB + AB
(b)
ABC + ABC + ABC + AB C + A BC
(c) ABC + ABC + ABC
(d) ABCD + ABCD + ABCD + ABCD + AB CD + ABCD + AB C D
4.52 COMPUTER FUNDAMENTALS
22. Convert the fol l owi ng l ogi c expressi ons i nto canoni cal form:
(a)
(A + B) (B + C)
(b)
B (A +C)
(c)
(A + B) (A + B + D)
(d) A (A + B + C)
[Ans. (a)
(A B C) (A B C)(A B C)(A B C) + + + + + + + +
(b)
(A + B + C) (A B C) (A B C)(A B C)(A B C) (A + B + C) + + + + + + + +
(c)
(A + B + C + D) (A B C D) (A B C + D)(A B C + D) + + + + + + +
(A B C + D) (A + B + C + D) + +
(d)
(A + B + C) (A + B + C) (A + B + C) (A + B + C)
23. Real i ze (a) an AND-OR l ogi c network and (b) NAND network for the fol l owi ng Bool ean
functi on:
Z = BC + AD
[Ans. See (a) Fi g. 4.49, (b) Fi g. 4.50.]
Fig. 4.49 AND-OR Network for probl em 23(a).
Fig. 4.50 NAND Network for probl em 23(b).
24. Real i ze (a) an AND-OR network and (b) NAND network for the fol l owi ng Bool ean functi on:
Z = XYZ + XYZ + YZ
[Ans. See (a) Fi g. 4.51 and (b) Fi g. 4.52]
LOGI C DESI GN 4.53
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Fig. 4.51 AND-OR Network for probl em 24(a).
Fig. 4.52 NAND Network for probl em 24(b).
25. Real i ze (a) an OR-AND network and (b) NOR network for the fol l owi ng Bool ean functi on:
Y = (A + B) (C + D)
[Ans. See (a) Fi g. 4.53 and (b) Fi g. 4.54]
Fig. 4.53 OR-AND Network for probl em 25(a).
Fig. 4.54 NOR Network for probl em 25(b).
4.54 COMPUTER FUNDAMENTALS
26. Si mpl i fy the fol l owi ng expressi ons by Karnaugh map method:
(a) ABC + ABC + ABC + ABC + AB C + A B C
(b) ABC + ABC + AB C + ABC + A BC + ABC
(c) ABC + ABC + A B C
(d)
ABC + ABC + ABC
[Ans. (a)
B C +
, ( ) b c d A C, ( ) AB + A C and ( ) BC + AC] +
27. Draw Karnaugh map and si mpl i fy the fol l owi ng Bool ean expressi ons:
(a) ABCD AB C D ABCD AB CD + + +
(b) A B CD A B CD A BCD A BCD + + +
(c)
A B C D A B CD A BCD A BCD + ABCD + + +
(d)
A B C D ABCD AB CD ABCD + ABCD + ABCD + + +
[Ans. ( ) ) a b c d AC, ( ) A B, ( A B + ACD and ( ) BD + ABD]
28. How are the squares of a Karnaugh map l abel l ed? How are the sum of product form of l ogi cal
expressi ons are wri tten i n (N
1
, N
2
, .....) form?
29. Draw Karnaugh map and si mpl i fy the fol l owi ng Bool ean expressi ons:
(a) Y(A, B, C) = (2, 3, 4, 6, 7)
(b) Y(A, B, C) = (0, 1, 3, 4, 5)
(c) Y(A, B, C, D) = (3, 4, 5, 6, 7, 11, 12, 13, 14, 15)
(d) Y (A, B, C, D) = (0, 2, 4, 6, 8, 10, 12, 14, 15)
[Ans. ( ) a b c d B AC, ( ) B + AC, ( ) B + CD and ( ) D + ABC] +
30. Expl ai n the fol l owi ng terms:
(a) Pri me i mpl i cant
(b) Nonpri me i mpl i cant
(c) Essenti al pri me i mpl i cant
(d) Nonessenti al pri me i mpl i cant
31. Draw Karnaugh map and si mpl i fy the fol l owi ng Bool ean functi ons:
(a) Y (A, B, C, D) = m (0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
(b) Y (A, B, C, D) = m (0, 1, 2, 3, 4, 6, 8, 9, 10, 11, 12, 13, 14 and 15)
[Ans. ( ) a A + D +AC + A B]
Hint: make the encl osures as fol l ows:
Encl osure I : 8, 9, 10, 11, 12, 13, 14 and 15.
Encl osure I I : 1, 3, 5, 7, 9, 11, 13 and 15.
Encl osure I I I : 2, 3, 6 and 7.
Encl osure I V: 0, 1, 2 and 3.
There are other al ternati ves al so.
[Ans.
( ) b B + A + AD]
LOGI C DESI GN 4.55
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Hint: make the encl osures as fol l ows:
Encl osure I : 0, 1, 2, 3, 8, 9, 10 and 11.
Encl osure I I : 8, 9, 10, 11, 12, 13, 14 and 15.
Encl osure I I I : 0, 2, 4 and 6.
32. Draw Karnaugh map and si mpl i fy the Bool ean functi on:
Y(A, B, C, D) = M(l , 5, 7, 8, 9, 10, 11, 12, 13, 14, 15) [Ans. A(B + D C + D)] )(
Hint: make the fol l owi ng encl osures:
Encl osure I : 8, 9, 10, 11, 12, 13, 14 and 15.
Encl osure I I : 5, 7, 13 and 15.
Encl osure I I I : 1, 5, 9, 13.
33. Expl ai n what you understand by dont care condi ti ons.
34. Fi nd the si mpl i fi ed Bool ean functi on (a) i n sum of products form and (b) i n product of sums
form for the Karnaugh map represented by
Y (A, B, C, D) = m (0, 3, 7, 8, 9, 11, 12, 13) + d (1, 4, 14, 15)
or M (2, 5, 6, 10) + d(l , 4, 14, 15) [Ans. (a) CD CD AC + + ]
Hint: make groupi ngs of squares contai ni ng 1s as fol l ows:
Group I : 0, 4, 8 and 12, assume 4 to contai n 1.
Group I I : 3, 7, 11 and 15, assume 15 to contai n 1.
Group I I I : 8, 9, 12 and 13. [Ans. (b) (A B C) (C D) + + + ]
Hint: make groupi ngs of squares contai ni ng 0s as fol l ows:
Group I : 2, 6, 10 and 14.
Group I I : 4 and 5.
35. What i s a hal f-adder? Wri te truth tabl e for a hal f-adder and devel op i ts l ogi c ci rcui t.
36. What i s a ful l -adder? How i s a ful l -adder bui l t usi ng hal f-adders?
37. Wri te the truth tabl e for a ful l -adder and devel op i ts l ogi c network.
38. How is an n-bi t adder real i zed usi ng n ful l -adders? Draw the l ogi c network.
39. How i s an adder-subtracter network bui l t usi ng ful l -adders? Draw i ts l ogi c network. What
i s the functi on of a control l ed i nverter?
40. How i s mul ti pl i cati on per for med usi ng ar r ays of ful l -adder s? Expl ai n wi th a sui tabl e
exampl e.
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5
CHAPTER CHAPTER
CEMTPAL PPOCESSIMS UMIT
(CPU)
5.1 INTRODUCTION
The central processi ng uni t (CPU) i s the brai n of a computer. I ts pri mary functi on i s to
execute programs. The program, whi ch i s to be executed, i s stored i n the mai n memory. A
program i s a sequence of i nstructi ons to perform a speci fi ed task. The CPU fetches i nstruc-
ti on codes from the memory and decodes them. The necessary data for the executi on of an
i nstructi on may be i n regi sters of the CPU or i n the memory. The CPU al so reads data from
the memory, whi ch are requi red for i nstructi on executi on. When the requi red data for the
executi on of an i nstructi on i s at hand, the CPU executes the i nstructi on. When al l the
i nstructi ons of a program are executed, the CPU gi ves the resul t. The resul t i s pl aced i n the
memory or sent to an output devi ce accordi ng to the i nstructi on gi ven i n the program.
Besides executing programs, the CPU also controls input devices, output devices and other
components of the computer. I t controls input and output devices to receive and send data. Under
its control programs and data are stored in the memory and displayed on the CRT screen.
The CPU of a smal l computer i s a mi croprocessor. The CPU of a l arge computer contai ns
a number of mi croprocessors. They work i n paral l el to execute a program. Thi s makes
computer more powerful and faster. Each mi croprocessor i n a l arge central processi ng uni t
performs a speci fi ed task.
5.2 CPU ORGANIZATION
The fol l owi ng are the mai n secti ons of a CPU:
(i) Ari thmeti c and l ogi cal uni t (ALU).
(ii) Control uni t.
(iii) Accumul ator and general and speci al purpose regi sters.
5.2.1 Arithmetic and Logic Unit (ALU)
The functi on of an ari thmeti c and l ogi c uni t i s to perform ari thmeti c and l ogi c opera-
ti ons. Usually an ALU performs the fol l owi ng ari thmeti c and l ogi c operati ons:
(i) Addition
(ii) Subtracti on
(iii) Mul ti pl i cati on
(iv) Di vi si on
5.1
5.2 COMPUTER FUNDAMENTALS
(v) Logical AND
(vi) Logi cal OR
(vii) Logi cal EXCLUSI VE-OR
(viii) Compl ement (l ogi cal NOT)
(ix) I ncrement (i.e., addi ti on of 1)
(x) Decrement (i.e., subtracti on of 1)
(xi) Left or ri ght shi ft (the content of the accumul ator can be shi fted l eft or ri ght by
one bi t)
(xii) Cl ear (the content of the accumul ator or carry fl ag can be made zero).
Other mathemati cal operati ons such as exponenti al , l ogari thmi c, tri gonometri c and fl oat-
i ng-poi nt operati ons are not performed by ALU. These operati ons are performed by speci al
purpose math processor cal l ed fl oati ng-poi nt uni t (FPU). Modern mi croprocessors contai n an
FPU on the mi croprocessor chi p i tsel f (i .e., an on-chi p FPU). Some cheaper mi croprocessors
whi ch are used for si mpl e automati c control appl i cati ons may not contai n on-chi p FPU. Such
processors use ei ther software for above menti oned mathemati cal operati ons or empl oy a
math processors I C (or math coprocessor) i n the mi croprocessor-based system. The use of
software for such mathemati cal operati ons makes executi on sl ower. Math processors speed
up program executi on and reduce programmi ng compl exi ty. The choi ce depends on actual
requi rement and cost i nvol ved i n a parti cul ar appl i cati on.
5.2.2 Control Unit
The control uni t of a CPU control s the enti re operati on of the computer. Thi s very
secti on of the CPU real l y acts as the brai n of the computer. I t al so control s al l other devi ces
such as memory, i nput and output devi ces connected to the CPU. I t fetches i nstructi on from
the memory, decodes the i nstructi on, i nterprets the i nstructi on to know what tasks are to
be performed and sends sui tabl e control si gnal s to other components to perform further
necessary steps to execute the i nstructi on. I t mai ntai ns order and di rects the operati on of the
enti re system. I t gi ves order to ALU what operati ons are to be performed. I t generates ti mi ng
and control si gnal s, and provi des them for al l operati ons. I t control s the data fl ow between
CPU and peri pheral s (i ncl udi ng memory). I t provi des status, control and ti mi ng si gnal s that
the memory and I /O devi ces requi re.
Under the control of the control uni t the i nstructi ons are fetched from the memory one
after another for executi on unti l al l the i nstructi ons are executed. I n a Von Neumann type
processor such as I ntel 8085, for fetchi ng and executi ng an i nstructi on the fol l owi ng steps are
performed under i ts control :
(i) The address of the memory l ocati on where i nstructi on l i es, i s pl aced on the address
bus.
(ii) I nstructi on i s read from the memory.
(iii) The i nstructi on i s sent to the decodi ng ci rcui try for decodi ng.
(iv) Addresses and data requi red for the executi on of the i nstructi on are read from the
memor y.
(v) These data/addresses are sent to the other secti on for processi ng.
(vi) The resul ts are sent to the memory or kept i n some regi ster.
CENTRAL PROCESSI NG UNI T (CPU) 5.3
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(vii) Necessary steps are taken to fetch next i nstructi on. For thi s the content of the
program counter i s i ncremented.
5.2.3 Registers
A CPU contai ns a number of regi sters to store data temporari l y duri ng the executi on of
a program. The number of regi sters di ffers from processor to processor. Some processor
contai ns more regi sters, some l ess. Regi sters are cl assi fi ed as fol l ows:
General Purpose Registers. These regi sters store data and i ntermedi ate resul ts duri ng
the executi on of a program. They are accessi bl e to users through i nstructi ons i f the users are
worki ng i n assembl y l anguage.
Accumulator. I t i s the most i mportant general -purpose resi ster havi ng mul ti pl e functi ons.
I t i s most effi ci ent i n data movement, ari thmeti c and l ogi cal operati on. I ts functi ons depend on
the desi gn of the processor whether the processor i s an accumul ator-based processor or general -
purpose regi sters-based processor (Refer to Secti on 5.3.3 for more detai l s). I t has some speci al
features that the other general -purpose regi sters do not have. I n a accumul ator-based processor
desi gn, the accumul ator hol ds one of the operands of ari thmeti c and l ogi cal operati on. After the
executi on of ari thmeti c and l ogi cal i nstructi ons, the resul t i s pl aced i n the accumul ator. Al l data
transfer between the CPU and devi ce/port are performed through the accumul ator.
Special Purpose Registers. A CPU contai ns a number of speci al purpose regi sters for
di fferent purposes. These are:
(i) Program Counter (PC)
(ii) Stack Poi nter (SP)
(iii) Status Regi ster
(iv) I nstructi on Regi ster (I R)
(v) I ndex Regi ster
(vi) Memory Address Regi ster (MAR)
(vii) Memory Buffer Regi ster (MBR) or Data Regi ster (DR)
Al l CPUs do not contai n al l of these speci al regi sters. A powerful CPU contai ns most of
them. The bri ef descri pti on of these regi sters i s gi ven bel ow:
Program Counter (PC). The Program counter keeps track of the address of the i nstructi on
whi ch i s to be executed next. So i t hol ds the address of the memory l ocati on, whi ch contai ns
the next i nstructi on to be fetched from the memory. I ts content i s automati cal l y i ncremented
after an i nstructi on has been fetched assumi ng that i nstructi ons are normal l y executed
sequenti al l y. I n case of a jump i nstructi on i ts contents are modi fi ed, and program jumps to
the memory l ocati on whi ch contai ns the desi red i nstructi on to be executed next. The processors
whi ch employ Von Neumann archi tecture contai n a program counter. The processors whi ch
use data fl ow archi tecture do not contai n program counter (Refer to Secti ons 1.19 and 5.18.1
for more detai l s).
Stack Pointer (SP). The stack i s a sequence of memory l ocati on defi ned by the user. I t
i s used to save the contents of a regi ster i f i t i s requi red duri ng the executi on of a program.
The stack poi nter hol ds the address of the l ast occupi ed memory l ocati on of the stack. Thus
i t i ndi cates upto what memory l ocati ons the stack i s al ready fi l l ed up. I n other words i t
i ndi cates from whi ch memory l ocati on onward the stack i s vacant for further storage. The
stack wi l l be di scussed i n detai l i n Secti on 8.4.
5.4 COMPUTER FUNDAMENTALS
Status Register (or Flag Register). A fl ag regi ster contai ns a number of fl ags ei ther to
i ndi cate certai n condi ti ons ari si ng after ari thmeti c and l ogi cal operati ons or to control certai n
operati ons. The fl ags whi ch i ndi cate condi ti ons are known as condi ti on fl ags. The fl ags whi ch
are used to control certai n operati ons are cal l ed control fl ags. A fl ag i s a fl i p-fl op whi ch i s set
or reset by the processor to i ndi cate certai n condi ti ons or set/reset by the programmer to
control certai n operati ons.
A si mpl e mi croprocessor l i ke I ntel 8085 contai ns the fol l owi ng condi ti on fl ags:
Carry fl ag I t i ndi cates whether there i s carry or not after an ari thmeti c or
l ogi cal operati on.
Zero fl ag I t i ndi cates whether the resul t of an ari thmeti c or l ogi cal operati on
i s zero or nonzero.
Si gn fl ag I t i ndi cates whether the resul t i s posi ti ve or negati ve.
Pari ty fl ag I t i ndi cates whether the resul t contai ns odd number of 1s or even
number of 1s.
Auxi l i ary carry (or Hal f carry) i.e., carry from the 3
rd
bi t to 4
th
i s al so i ndi cated.
The I ntel 8085 does not contai n any control fl ag.
The I ntel 8086 mi croprocessor contai ns si x condi ti on fl ags and three control fl ags (Refer
to Secti on 5.13.2 for detai l s)
I nstruction Register. I t hol ds an i nstructi on unti l i t i s decoded. Some computers have two
i nstructi on regi sters, and so they can fetch and save the next i nstructi on whi l e the executi on
of the previ ous i nstructi on i s goi ng on.
I ndex Register. I ndex regi sters are used for addressi ng. One or more regi sters are
desi gnated as i ndex regi sters. The address of an operand i s the sum of the contents of the
i ndex regi ster and a constant. I nstructi ons i nvol vi ng i ndex regi ster contai n constant. Thi s
constant i s added to the contents of i ndex regi ster to form the effecti ve address, i .e. the
address of the operand. Usual l y, speci al i nstructi ons are provi ded to i ncrement or decrement
an i ndex regi ster so as to access the entri es of a tabl e i n a successi ve manner. Al ternati vel y,
some computers have the faci l i ty of auto-i ndexi ng by whi ch the i ndex regi ster i s automati cal l y
i ncremented or decremented.
Memory Address Register (MAR). I t hol ds the address of the i nstructi on or data to be
fetched from the memory. The CPU transfers the address of the next i nstructi on from the
program counter (PC) to the memory address regi ster. From MAR i t i s sent to the memory
through the address bus. Someti mes i t i s cal l ed si mpl y address regi ster (AR).
Memory Buffer Register (MBR) or Data Register (DR). I t hol ds the i nstructi on code or
data recei ved from or sent to the memory. I t i s connected to data bus. The data, whi ch are
wri tten i nto the memory, are hel d i n thi s regi ster unti l the wri te operati on i s compl eted. I t
i s al so cal l ed data regi ster (DR). Thus the fl ow of data from the CPU to the memory or from
the memory to CPU i s al ways through MBR. I t i s wi thi n CPU.
5.3 INSTRUCTION
An i nstructi on i s a command gi ven to the computer to perform a speci fi ed operati on on
gi ven data. Each i nstructi on consi sts of two parts: an opcode (operati on code) and an operand.
The fi rst part of an i nstructi on, whi ch speci fi es the operati on to be performed, i s known as
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opcode. The second part of an i nstructi on cal l ed operand i s the data on whi ch computer
performs the speci fi ed operati on. I mportant i nstructi ons of I ntel 8085 are gi ven i n secti on
5.3.1 and those of I ntel 8086 i n secti on 5.13.9.
5.3.1 Intel 8085 Instructions
I ntel 8085 i s an 8-bi t mi croprocessor, very popul ar i n I ndi a. Mi croprocessor ki ts based on
I ntel 8085 are wi del y used i n l aboratori es for students trai ni ng. I ntel 8085 has one 8-bi t
accumul ator desi gnated as A. I t has si x 8-bi t general -purpose regi sters: B, C, D, E, H and L.
Two 8-bi t regi sters can be combi ned to form a regi ster-pai r, whi ch can handl e 16-bi t data. The
val i d regi ster pai rs of I ntel 8085 are: B-C, D-E and H-L. Speci al purpose regi ster are: one 16-
bi t program counter (PC), one 16-bi t stack poi nter (SP) and an i nstructi on regi ster. I t does
not have a status regi ster, but contai ns a set of fl i p-fl ops to store status fl ags. The combi nati on
of the bi nary bi ts, whi ch i ndi cate status fl ags i s cal l ed program status word (PSW). Fi ve bi ts
of PSW show status fl ags, 3-bi ts are undefi ned. PSW and the accumul ator are treated as a
16-bi t uni t for stack operati on. I n addi ti on to these regi sters i t al so contai ns a temporary
regi ster, address buffer and data buffer.
Some of i nstructi ons of 8085 are descri bed here as they are requi red to expl ai n a few
topi cs i n the subsequent secti ons.
MOV r
1
, r
2
. The contents of regi ster r
2
are transferred to regi ster r
1
. For exampl e, the
i nstructi on MOV A, B transfers the contents of regi ster B to regi ster A. The i nstructi on MOV
B, A transfers the contents of regi ster A to regi ster B.
MOV r, M. The contents of the memory l ocati on M whose address i s i n H-L pai r, are
transferred to the regi ster r. For exampl e, MOV A, M wi l l transfer the contents of the
memory l ocati on M speci fi ed by H-L pai r, to the accumul ator.
MVI r, data. The data speci fi ed i n the i nstructi on wi l l be transferred to the regi ster r.
For exampl e, MVI B, 08 wi l l transfer 08 to regi ster B.
LXI rp, data 16-bit. 16-bi t data speci fi ed i n the i nstructi on wi l l be transferred to the
regi ster pai r rp. For exampl e, the i nstructi on LXI H, 2500H transfers 2500 to H-L pai r.
LDA addr. The contents of the memory address speci fi ed i n the i nstructi on are trans-
ferred to the accumul ator. For exampl e, the i nstructi on LDA 2200 wi l l transfer the contents
of the memory l ocati on 2200 to the accumul ator.
STA addr. The contents of the accumul ator are transferred to the memory l ocati on
whose address i s speci fi ed i n the i nstructi on. For exampl e, the i nstructi on STA 2000 wi l l
transfer the contents the accumul ator to the memory l ocati on 2000.
ADD r. The contents of the regi ster r are added to the contents of the accumul ator and
the resul t i s pl aced i n the accumul ator. For exampl e, the i nstructi on ADD C wi l l add the
contents of the regi ster C to the contents of the accumul ator, and the resul t i s pl aced i n the
accumul ator.
ADD M. The contents of the memory l ocati on, whose address i s i n H-L pai r, are added
to the contents of the accumul ator and the resul t i s pl aced i n the accumul ator. For exampl e,
ADD M wi l l add the contents of the memory l ocati on speci fi ed by H-L pai r, to the contents
of the accumul ator, and the resul t i s pl aced i n the accumul ator.
ADI, data. The data i n the i nstructi on are added to the contents of the accumul ator,
and the resul t i s pl aced i n the accumul ator. For exampl e, ADI , 05 wi l l add 05 to the contents
of the accumul ator, and the resul t i s pl aced i n the accumul ator.
5.6 COMPUTER FUNDAMENTALS
SUB r. The contents of the regi ster r are subtracted from the contents of the accumu-
l ator, and the resul t i s pl aced i n the accumul ator.
RAL. The contents of the accumul ator are rotated l eft one bi t through carry.
IN port address. The i nstructi on transfers data from the i nput devi ce or i nput port to
the accumul ator.
OUT port address. Thi s i nstructi on transfers the contents of the accumul ator to the
output devi ce or output port.
HLT. Thi s i nstructi on i s hal t. After the executi on of thi s i nstructi on the mi croprocessor
stops.
5.3.2 Intel 8085 Instruction Format or Instruction Word Size
As a computer understands i nstructi ons onl y i n the form of 0 and 1, i nstructi ons and data
are fed i nto the computer i n bi nary form. They are wri tten i n bi nary codes known as machine
codes. For the conveni ence of the user the codes can be wri tten i n hexadeci mal form.
As there are di fferent ways of speci fyi ng data the bi nary codes of al l i nstructi ons are not
of the same l ength. I nstructi ons are cl assi fi ed i nto the fol l owi ng three types accordi ng to thei r
word l ength (i.e., l ength of the bi nary code):
(i) Si ngl e-byte i nstructi on
(ii) Two-byte i nstructi on
(iii) Three-byte i nstructi on
The fi rst byte of an i nstructi on i s the opcode of the i nstructi on. Other bytes may be
ei ther data or address.
Single-Byte I nstruction. I n a si ngl e-byte i nstructi on, the bi nary code of the i nstructi on
i s of one byte. For exampl e, MOV A,B; ADD B; RAL etc. are si ngl e-byte i nstructi ons. The
machi ne codes for these i nstructi ons are: 78H, 80H and 17H respecti vel y. H denotes hexa-
deci mal .
Two-Byte I nstruction. I n a two-byte i nstructi on, the machi ne code i s of two bytes. For
exampl e, MVI A, 05 i s a two-byte i nstructi on. I ts machi ne code i s 3E, 05. The fi rst byte, i .e.,
3E i s the opcode of the MVI A i nstructi on, 05 i s the data whi ch i s to be transferred to regi ster
A. As a memory l ocati on stores onl y one byte, the two bytes are stored i n two consecuti ve
memory l ocati ons.
Another exampl e of a two-byte i nstructi on i s I N 01. I n coded form i t i s wri tten as DB,
01. DB i s the operati on code. The second byte 01 i s the address of an i nput devi ce.
Three-Byte I nstruction. I n a three-byte i nstructi on the fi rst byte i s the opcode of the
i nstructi on. The 2nd and 3rd bytes are ei ther data or address. Some exampl es are:
(i) LXI H, 2500H : Load H-L pai r wi th 16-bi t data 2500H.
21,00,25 : The i nstructi on LXI H, 2500 i n code form.
The fi rst byte 21 i s the opcode of the i nstructi on LXI H. The second byte 00 i s 8 LSBs
of the data 2500H. 8 LSBs are l oaded i nto regi ster L. The thi rd byte 25 i s 8 MSBs of the data.
I t i s l oaded i nto regi ster H.
(ii) LDA 2400H : Load accumul ator wi th the contents of the memory l ocati on 2400H.
3A, 00,24 : The i nstructi on LDA 2400H i n the code form.
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The fi rst byte 3A i s the opcode of the i nstructi on LDA. The second byte 00 i s 8 LSBs
of memory address 2400H. The thi rd byte 24 i s the 8 MSBs of memory address 2400H.
5.3.3 Alternative Way of Classification of Instructions
I nstructi ons can al so be cl assi fi ed dependi ng upon the number of operand addresses they
contai n. Such a cl assi fi cati on i s as fol l ows:
(1) 0-address i nstructi on
(2) 1-address i nstructi on
(3) 2-address i nstructi on
(4) 3-address i nstructi on
Shorter i nstructi ons are faster and they can reduce the overal l cost.
0-Address Instruction
The 0-address type i nstructi ons do not contai n any operand address. The operand ad-
dresses are i mpl i ed.
1-Address Instruction
I n 1-address i nstructi ons onl y one operand address i s speci fi ed i n the i nstructi on. The
other operand address i s i mpl i ed. The other operand i s i n the accumul ator. The resul t i s
pl aced i n the accumul ator.
2-Address Instruction
I n 2-address i nstructi ons both operand addresses are speci fi ed. The resul t i s pl aced i n
one of the speci fi ed addresses.
3-Address Instruction
I n 3-address i nstructi ons two addresses are speci fi ed for the two operands and one
address for the resul t.
5.3.4 Classification of Processors/Computers
Faster ari thmeti c, l ogi cal and compari son i nstructi ons make a processor faster and more
powerful . Two or three address machi nes are faster and more powerful as compared to zero-
address and one-address machi nes. Dependi ng on the number of addresses gi ven i n ari th-
meti c, compari son and l ogi cal i nstructi ons, processors (or computers) are cl assi fi ed as fol l ows:
(1) One-Address Machine or Accumul ator- Based machi nes
(2) Two or Three-Address Machi nes or General -Purpose Regi sters Based Machi nes.
(3) 0-Address Machi nes or Stack Machi nes.
One-Address Machines or Accumulator-Based Machines
Ari thmeti c, l ogi cal and compari son i nstructi ons of accumul ator-based machi nes contai n
the address of onl y one operand. I t i s i mpl i ed that the other operand i s i n the accumul ator.
The resul t of the operati on i s pl aced i n the accumul ator. I t i s the desi gn feature of the
processor. The fi rst-generati on computers were accumul ator-based machi nes. Al so, the fi rst
generati on of mi ni computers (DECs PDP-8, HP 2116, etc) and the fi rst generati on of 8-bi t
mi croprocessors (MC 6800, MC 6809, I ntel 8080, I ntel 8085, etc) had accumul ator-based
archi tecture.
5.8 COMPUTER FUNDAMENTALS
Two or Three-Address or General-Purpose Registers Based Machines
Machi nes of thi s type contai n a set of general -purpose regi sters whi ch al so act as accu-
mul ator for ari thmeti c, l ogi cal and compari son operati ons. Thei r i nstructi ons contai n two or
three addresses. I n case of two addresses processors the addresses for both operands are
speci fi ed i n the i nstructi on. The resul t i s pl aced i n one of the speci fi ed addresses. Thi s type
of archi tecture was desi gned for the second generati on of computers and mi croprocessors
such as I BM 360/370, DECs PDP-11, I ntel 8086, Z8000, Motorol a, 68000, etc. Exampl es of
three address machi nes are : Cyber-170, CDC 6600, etc. Two or three-address machi nes are
faster and more powerful than accumul ator-based machi nes.
0-Address or Stack Machines
Stack ori ented machi nes do not contai n any accumul ator or general -purpose regi sters. Al l
operati ons except data transfer are performed on the operands whi ch are at or near the top
of the stack. A stack-ori ented machi ne contai ns onl y a stack-poi nter (SP), whi ch poi nts to the
stacktop. An ari thmeti c i nstructi on ADD does not requi re any address. The ADD i nstructi on
pops two operands from the stack, adds them and pushes the resul t back i nto the stack. But
the data transfer i nstructi ons of a stack-ori ented machi ne contai n operand address. For ex-
ampl e, the LOAD and STORE i nstructi ons have an operand address. The LOAD X i nstructi on
fetches operand from the memory l ocati on X, and pushes i t i nto the stack. Si mi l arl y, STORE
X i nstructi on pops operand from the stack, and stores i n the memory l ocati on X.
I n stack machi nes ari thmeti c, l ogi cal and compari son i nstructi ons do not requi re any
operand address. Hence, they are cal l ed 0-address machi nes. The computi ng power of a
machi ne depends on the performance of ari thmeti c, l ogi cal and compari son i nstructi on. These
i nstructi ons are the deci di ng factors, not the data transfer and some other types of i nstruc-
ti ons. Exampl es of stack-ori ented machi nes are : Burroughs B5000, 5500 and 6700 (mai n-
frame computers), and HP 3000 (mi ni computers). Many cal cul ators empl oyed stack-ori ented
processors. Thi s type of archi tecture i s not sui tabl e for current RI SC and CI SC processors,
whi ch have i ntensi ve paral l el i sm. Modern processors contai n several operands i n l arge reg-
i ster set for hi gh performance.
5.4 ADDRESSING MODES
Each i nstructi on needs data on whi ch i t has to perform the speci fi ed operati on. The
operand (data) may be i n the accumul ator, general purpose regi ster or i n some speci fi ed
memory l ocati on. Therefore, there are vari ous ways to speci fy data. The techni ques of
speci fyi ng the address of the data are known as addressi ng modes. The i mportant addressi ng
modes are as fol l ows:
(i) Di rect (or absol ute) addressi ng
(ii) Regi ster addressi ng
(iii) Regi ster i ndi rect addressi ng
(iv) I mmedi ate addressi ng
(v) I mpl i ci t addressi ng
(vi) I ndexed addressi ng
(vii) Based addressi ng
(viii) Based i ndexed addressi ng
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(ix) Rel ati ve addressi ng
(x) Rel ati ve i ndexed addressi ng
(xi) Page addressi ng
(xii) Stack addressi ng
I ntel 8085 uses addressi ng modes onl y from (i) to (v). I n addi ti on to (i) to (v) addressi ng
modes other addressi ng modes are al so used by other mi croprocessors. Addressi ng modes of
I ntel 8086 wi th exampl es are gi ven i n Secti on 5.13.10. Exampl es of addressi ng modes gi ven
i n Secti ons 5.4.1 to 5.4.5. are for I ntel 8085.
5.4.1 Direct (or Absolute) Addressing
I n di rect addressi ng the address of the data (operand) i s speci fi ed wi thi n the i nstructi on
i tsel f. Exampl es of di rect addressi ng are:
(i) STA 2500H : Store the contents of the accumul ator i n the memory l ocati on 2500H.
(ii ) LDA 2500H : Load accumul ator wi th the contents of the memory l ocati on 2500H.
I n exampl e (i) above, 2500H i s the memory address where data are to be stored. The
memory address 2500H i s gi ven i n the i nstructi on i tsel f. I n thi s case i t i s understood that the
source of data i s accumul ator.
(i i i ) IN 01 : Read data from an i nput devi ce whose address i s 01.
I n thi s i nstructi on 01 i s the address of an i nput devi ce from where data are to be read.
I n thi s i nstructi on i t i s i mpl i ed that the data wi l l be transferred from the i nput devi ce to the
accumul ator.
5.4.2 Register Addressing
I n regi ster addressi ng the operands are l ocated i n general -purpose regi sters. I n other
words the contents of a regi ster i s the operand. Therefore, onl y the names of the regi sters
are to be speci fi ed i n the i nstructi on. Exampl es of regi ster addressi ng are:
(i) MOV A, B : Transfer the contents of regi ster B to regi ster A.
The opcode of thi s i nstructi on i s 78H. I n addi ti on to the operati on to be performed, the
opcode al so speci fi es the addresses of the regi sters menti oned i n the i nstructi on. The opcode
78H i n bi nary from i s 01111000. The fi rst two bi ts 01 denote MOV operati on, the next three
bi ts 111 are the bi nary code of regi ster A and the l ast three bi ts 000 are the bi nary code of
regi ster B of I ntel 8085.
(ii ) ADD B : Add the contents of the regi ster B to the contents of the accumul ator.
The opcode of thi s i nstructi on i s 80H. I n the bi nary form the code i s 10000000. The fi rst
fi ve bi ts 10000 speci fy the operati on to be performed, i.e., ADD. The l ast three bi ts 000 are
the bi nary code of regi ster B.
5.4.3 Register Indirect Addressing
I n regi ster i ndi rect addressi ng the address of the operand i s gi ven i ndi rectl y. The con-
tents of a regi ster or a regi ster-pai r are the address of the operand. Compare thi s wi th the
regi ster addressi ng where the content of the regi ster i s the operand. Exampl es are:
5.10 COMPUTER FUNDAMENTALS
(i) LXI H, 2400H : Load H-L pai r wi th 2400H.
MOV A, M : Move the content of the memory l ocati on, whose address i s i n
H-L pai r (i.e., 2400H), to the accumul ator.
I n thi s exampl e MOV A, M i s an exampl e of regi ster i ndi rect addressi ng. For MOV A, M
i nstructi on the operand i s i n a memory l ocati on whose address i s not di rectl y gi ven i n thi s
i nstructi on. The address of the memory l ocati on i s stored i n H-L pai r, whi ch has been
speci fi ed by the earl i er i nstructi on i n the program, i.e., LXI H, 2400H.
(ii ) LXI H, 2200H : Load H-L pai r wi th 2200H.
ADD M : Add the contents of the memory l ocati on, whose address i s i n
H-L pai r, to the contents of the accumul ator.
I n thi s exampl e the i nstructi on ADD M i s an exampl e of regi ster i ndi rect addressi ng.
5.4.4 Immediate Addressing
I n i mmedi ate addressi ng the operand i s gi ven i n the i nstructi on i tsel f. The exampl es of
i mmedi ate addressi ng are:
(i) MVI A, 06 : Move 06 to the accumul ator.
(ii) ADI 05 : Add 05 to the content of the accumul ator.
(iii) LXI H, 2500H : Load H-L pai r wi th 2500H.
5.4.5 Implicit (or Implied) Addressing
Thi s mode of addressi ng i s al so cal l ed i mpl i ed addressi ng or i nherent addressi ng. Some
i nstructi ons operate on onl y one operand, whi ch i s i n the accumul ator. So address need not
be speci fi ed. Such addressi ng i s known as i mpl i ci t addressi ng. Exampl es are:
(i) RAL : Rotate the contents of the accumul ator l eft through carry
(ii) RLC : Rotate the contents of the accumul ator l eft.
(iii) CMA : Take compl ement of the contents of the accumul ator.
Many i nstructi ons use two operands. For one of the operands they use i mpl i ci t address-
i ng whi l e for the other operand they empl oy any one of the other addressi ng modes.
Definitions of Certain Terms Related to Addressing Modes
Before di scussi ng other addressi ng modes, certai n terms are to be defi ned. A l arge
memory i s di vi ded i nto segments. The memory address of an operand consi sts of two com-
ponents: the starti ng address of the segment and an offset. The starti ng address of the
segment i s suppl i ed by the processor. The operand i s pl aced at an offset wi thi n the segment
wi th reference to the starti ng address of the segment. The offset i s determi ned by addi ng any
combi nati on of three offset address el ements: di spl acement, base and i ndex. The combi nati on
depends on the addressi ng mode of an i nstructi on to be executed. The offset i s al so cal l ed
effective address. The memory address of an operand i s gi ven by
The memory address of an operand = Starti ng address of the memory segment + offset
Displacement. I t i s an 8-bi t or 16-bi t i mmedi ate val ue gi ven i n the i nstructi on.
Base. I t i s the content of the base regi ster.
Index. I t i s the content of the i ndex regi ster.
The addressi ng modes descri bed i n secti ons 5.4.6 to 5.4.12 are for I ntel 8086 and other
mi croprocessors. They are not for I ntel 8085. The addressi ng modes of I ntel 8086 wi th
exampl es are gi ven i n secti on 5.13.10.
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5.4.6 Indexed Addressing
The operands offset i s determi ned by addi ng an 8-bi t or 16-bi t di spl acement (gi ven i n the
i nstructi on) to the content of the i ndex regi ster.
5.4.7 Based Addressing
I n thi s mode of addressi ng the operands offset i s the sum of the content of the base
regi ster and the 8-bi t or 16-bi t di spl acement gi ven i n the i nstructi on.
5.4.8 Based Indexed Addressing
I n based i ndexed addressi ng the contents of the base regi ster and the contents of the
i ndex regi ster are added together to form the effecti ve address. The base regi ster contai ns
a base address and the i ndex regi ster contai ns an i ndex.
5.4.9 Relative Addressing
I n rel ati ve addressi ng a si gned di spl acement i s added to the current val ue of the program
counter to form the effecti ve address. Thi s mode of addressi ng i s commonl y used i n branch
(or jump) i nstructi ons. The di spl acement i s a si gned quanti ty so as to al l ow ei ther a forward
or a backward jump from the l ocati on poi nted out by the program counter. Thi s mode of
addressi ng i s al so known as PC relative addressing. The effecti ve address speci fi es memory
l ocati on i n rel ati on to the current val ue of the program counter.
5.4.10 Relative Indexed Addressing
I n thi s mode of addressi ng the contents of the program counter and the contents of the
i ndex regi ster are added together to form the effecti ve address.
5.4.11 Page Addressing
I n paged mode of addressi ng the memory i s di vi ded i nto a number of equal l ength pages.
The page si ze i s 256 bytes for 8-bi t mi croprocessors and 4KB for 16-bi t mi croprocessors. The
mi croprocessor contai ns a page regi ster to hol d page number. The i nstructi on contai ns an
offset. The offset i ndi cates the address wi thi n the page wi th reference to the starti ng address
of the page. The numberi ng of pages i s done i n such a way that i n case of 16-bi t memory
address, the 8-bi t page number contai ned i n the page regi ster i ndi cates 8 MSBs of the operand
address. The advantage of thi s mode of addressi ng i s that a fewer bi ts i n the i nstructi on are
requi red to i ndi cate the memory address. Thi s resul ts i n shorter i nstructi on and faster
executi on.
0 Page Addressing
Some mi croprocessors provi de paged addressi ng i n the l i mi ted form wi thout empl oyi ng
a page regi ster. I n such a case the paged addressi ng i s restri cted onl y to the fi rst 256 memory
l ocati ons. The 8 MSBs of the address of these 256 memory l ocati ons are zero and thi s part
of the memory space i s cal l ed 0-page (or base page). Such mode of addressi ng i s cal l ed 0-page
addressing.
5.4.12 Stack Addressing
I n thi s mode of addressi ng the address of the operand i s speci fi ed by the stack poi nter
(SP). The l ength of i nstructi on i s shortest because i t does not i ncl ude any address of the
memory l ocati on or menti on any regi ster (just l i ke i mpl i ed mode of addressi ng). The contents
of SP are automati cal l y i ncremented or decremented after each stack operati on. PUSH
5.12 COMPUTER FUNDAMENTALS
i nstructi on i s used to save the contents of a regi ster pai r i nto the stack. The POP i nstructi on
i s used to transfer the contents from the stack to the regi ster-pai r. SP contai ns the address
of the memory l ocati on of the stack from (or to) whi ch data are to be transferred.
The stack addressi ng i s empl oyed i n the fol l owi ng cases:
(i) When PUSH and POP i nstructi ons are used i n a program by the programmer.
(ii) When CALL i nstructi on i s used to cal l a subrouti ne. Before a program jumps from
the mai n program to a sub-routi ne the contents of the PC are saved. When program
goes back from the subrouti ne to the mai n program the contents of PC are restored.
For thi s RET i nstructi on i s used at the end of a subrouti ne. Thi s uses stack addressi ng.
(iii) When i nterrupt occurs the contents of i mportant regi sters are saved i nto the stack.
For thi s stack addressi ng i s used.
5.4.13 Use of Segment Registers
I n case of very l arge memory, i t i s parti ti oned i nto secti ons cal l ed segments. To faci l i tate
the memory addressi ng segment regi sters are empl oyed. A segment regi ster poi nts out the
starti ng address of a memory segment (i .e., segment base address). The memory address for
an operand i s gi ven by:
Segment base address + offset wi thi n the segment
The effecti ve address i s an offset wi thi n the segment wi th reference to the starti ng
address of the segment (segment base address). I t depends on the addressi ng mode. The
effecti ve address (i .e. offset wi thi n the segment) i s computed usi ng di spl acement, base, i ndex,
scal e etc dependi ng upon the addressi ng mode empl oyed. See detai l s how to cal cul ate the
effecti ve address (offset) i n case of I ntel 8086 and I ntel 80486 i n Secti ons 5.13.9 and 5.15.3
respecti vel y. These mi croprocessors empl oy segment regi sters. The I ntel 8086, 80486 etc. use
segment regi sters. The i ntel 8085 does not use segment regi sters.
5.5 INTERRUPTS AND EXCEPTIONS
When data ar e r eady an I /O devi ce can i nter r upt CPU. After compl eti ng the cur r ent
i nstr ucti on at hand the CPU attends to the I /O devi ce. The CPU enter s i nto a subr outi ne
known as interrupt service subroutine (I SS) to tr ansfer data fr om the devi ce. Each CPU
has i nter r upt l i nes thr ough whi ch I /O devi ce can be connected to the CPU. Sl ow I /O
devi ces ar e connected thr ough i nter r upt l i nes. When data tr ansfer i s over the CPU
r etur ns to the pr ogr am i t was executi ng. Thi s i s di scussed i n detai l i n the chapter deal i ng
wi th I /O devi ces.
An i nterrupt caused by an external si gnal appl i ed to an i nterrupt i nput l i ne of a CPU
is known as hardware interrupt.
Enabling of Interrupts
When i nterrupts are to be used they are enabl ed (made effecti ve) usi ng i nstructi on EI
(i t i s an 8085 i nstructi on) i n the mai n program.
Disabling of Interrupts
When the mi croprocessor i s performi ng certai n i mportant task i t may be desi red to
prevent the occurrence of i nterrupts duri ng that peri od. Thi s i s achi eved usi ng DI i nstructi on.
The use of DI i nstructi on i n the program prevents occurrence of al l the i nterrupts.
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Masking of Interrupts
I n certai n si tuati ons i t may be desi red that some of the several i nterrupts shoul d not
occur whi l e mi croprocessor i s performi ng some i mportant task. Thi s i s done by maski ng
techni que. Certai n i nterrupts can be masked off (made i neffecti ve) by software techni que. The
i nterrupt that can be masked off i s cal l ed maskable interrupt.
Software Interrupts
The normal program executi on of a mi croprocessor can be i nterrupted by a speci al
i nstructi on i n the program. Thi s i s known as software i nterrupt. A speci al i nstructi on i s
i ncl uded i n the program for thi s type of i nterrupt. I n the 8085 there are RST n i nstructi ons
for thi s purpose. I f an RST n i nstructi on i s i nserted i n a program, the program i s executed
up to the poi nt where RST n has been i nserted. Then mi croprocessor stops. Thi s i s used i n
checki ng a program. By thi s process one checks whether the program runs correctl y upto
certai n poi nt. Then the program i s checked by i nserti ng RST n at another poi nt and so on.
The 8086 used I NT i nstructi on for software i nterrupt.
Exceptions
The i nternal events, whi ch cause the processor to go out of i ts normal processi ng
sequence, are cal l ed exceptions.
The defi ni ti on of i nterrupts and excepti ons di ffers from l i terature to l i terature. Accordi ng
to I ntel handbooks the external events caused by external I /O devi ces, whi ch prevent the
further processi ng are cal l ed interrupts. I nterrupts handl e external asynchronous events.
Excepti ons handl e i nternal abnormal or unusual condi ti ons, whi ch prevent further processi ng.
The processor treats software i nterrupts as excepti ons.
Accordi ng to Motorol a, excepti ons i ncl ude i nterrupts, traps and reset. The trap i ncl udes
excepti onal condi ti ons, program faul ts and hardware faul ts.
5.6 PIN CONFIGURATION OF INTEL 8085
Fi g. 5.1 shows the pi n confi gurati on of I ntel 8085. I t i s a 40 pi n I C. Pi n descri pti ons are
as fol l ows:
A
8
A
15
(output). These are address l i nes. They form the address bus. They carry 8
MSBs of the memory address or the 8 bi ts of I /O address.
AD
0
AD
7
(input/output). These are address/data l i nes. They form ti me-mul ti pl exed
address/data bus, i .e., they serve dual purpose. They carry 8 LSBs of the memory address or
I /O address duri ng the fi rst cl ock cycl e of a machi ne cycl e. Agai n they are used to carry data
duri ng the second and thi rd cl ock cycl es.
ALE (output). I t i s an address l atch enabl e si gnal . I t goes hi gh duri ng the fi rst cl ock
cycl e of a machi ne cycl e and enabl es 8 LSBs of the address to get l atched i nto the on-chi p
l atch of peri pheral s.
IO/
M
(output). I t i s a status si gnal to i ndi cate whether the address sent by the mi cro-
processor i s for a memory or an I /O devi ce. When i t i s hi gh the address on the address bus
i s for an I /O devi ce. When i t i s l ow the address on the address bus i s for the memory.
S
0
and S
1
(output). These are status si gnal s i ssued by the mi croprocessor to i denti fy
the vari ous types of operati ons gi ven i n Tabl e 5.1.
5.14 COMPUTER FUNDAMENTALS
Fig. 5.1 Pi n confi gurati on of I ntel 8085.
Table 5.1 Status codes for Intel 8085
S
1
S
0
Operations
0 0 HALT
0 1 WRI TE
1 0 READ
1 1 FETCH
RD
(output). I t i s a control si gnal sent by the mi croprocessor to control read operati on.
The sel ected memory or I /O devi ce i s read when
RD
i s l ow.
WR
(Output). I t i s a control si gnal i ssued by the mi croprocessor to control wri te
operati on. The data on the data bus are wri tten i nto the sel ected memory or I /O devi ce when
WR i s l ow.
HOLD (input). When an external devi ce wants to use the address and data bus, i t sends
HOLD si gnal to the mi croprocessor. Havi ng recei ved the HOLD si gnal the mi croprocessor
compl etes i ts current i nstructi on at hand, and then rel i nqui shes the control of buses to al l ow
the external devi ce to use them.
HLDA (output). I t i s a HOLD acknowl edgement si gnal . I t i s sent by the mi croprocessor
to the external devi ce to i ndi cate that the HOLD request has been recei ved. On the compl e-
ti on of data transfer, the external devi ce removes the HOLD request. The HLDA goes l ow
after the removal of HOLD request. The CPU takes over the control of buses hal f cycl e after
HLDA goes l ow.
INTR (input). I t i s an i nterrupt si gnal of the l owest pri ori ty.
INTA (output). I t i s an i nterrupt acknowl edgement si gnal . I t i s i ssued by the mi cropro-
cessor after I NTR i s recei ved.
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RST 5.5, 6.5, 7.5 and TRAP (input). These are i nterrupts. The TRAP i s a nonmaskabl e
i nterrupt and has the hi ghest pri ori ty. Others are maskabl e i nterrupts. The order of pri ori ty
is TRAP, RST 7.5, RST 6.5 and RST 5.5.
RESET IN (input). When thi s si gnal i s appl i ed the CPU i s brought to reset condi ti on.
The contents of the program counter becomes zero.
RESET OUT (output). Thi s si gnal i ndi cates that the CPU i s bei ng reset.
READY (input). I t i s an i nput si gnal to the mi croprocessor. I t i s sent by a peri pheral
devi ce to i ndi cate whether i t i s ready to transfer data or not. The mi croprocessor exami nes
READY si gnal before data are transferred. I f READY i s hi gh i t shows that peri pheral s are
ready to transfer data. I f READY i s l ow the mi croprocessor wai ts ti l l READY becomes hi gh.
The status of READY i s exami ned i n the second cl ock cycl e of the machi ne cycl e.
X
1
and X
2
(input). An external crystal osci l l ator i s connected to these termi nal s to
suppl y cl ock for the mi croprocessor. The crystal osci l l ator dri ves an i nternal ci rcui try whi ch
i s wi thi n the mi croprocessor to produce a sui tabl e cl ock for the operati on of the mi cropro-
cessor.
CLK (output). The cl ock i s al so requi red by some other I Cs of the computer. Hence,
CLK i s a cl ock output from the mi croprocessor, whi ch can be uti l i zed for the operati on of
other I Cs.
SID (input). I t i s an i nput l i ne for seri al data. The data recei ved from thi s are l oaded
i nto the 7th bi t of the accumul ator when RI M i nstructi on i s executed.
SOD (output). I t i s an output l i ne for seri al data. The 7th bi t of the accumul ator i s sent
through thi s l i ne when SI M i nstructi on i s executed.
5.7 GENERATION OF SOME SPECIAL CONTROL SIGNALS FOR MEMORY AND
I/O DEVICES
The control si gnal
RD
i s used for both readi ng memory as wel l as readi ng an i nput
devi ce. Therefore, i t i s essenti al to produce two separate read si gnal s: one for the memory
and the other for the i nput devi ce. Si mi l arl y, two separate wri te si gnal s are generated. These
speci al control si gnal s are as fol l ows:
MEMR. I t i s a memory read si gnal . I t i s obtai ned by ORi ng RD wi th I O/M as shown
i n Fi g. 5.2. The memory read operati on i s performed when both I O/M and RD are l ow.
MEMR wi l l be l ow onl y when both I O/M and RD are l ow. The l ogi c gates shown i n the fi gure
are equi val ent to OR gates. Thi s symbol i s used where the output requi red i s acti ve l ow wi th
both i nputs l ow.
Fig. 5.2 Read/wri te control si gnal s for memory and I /O.
5.16 COMPUTER FUNDAMENTALS
MEMW. I t i s a memory wri te si gnal . I t wi l l be l ow when both I O/
M
and
WR
are l ow.
IOR. I t i s an I /O read si gnal . I t i s used to read an i nput devi ce. I O/M i s i nverted and
then appl i ed to an OR gate. Therefore,
I OR
wi l l be l ow when I O/M is high and RD l ow.
IOW. I t i s an I /O wri te si gnal . I t wi l l be l ow when I O/M i s hi gh and WR l ow.
5.8 INSTRUCTION CYCLE
The mai n functi on of a CPU i s to execute programs. A program consi sts of a sequence
of i nstructi ons to perform a parti cul ar task. Programs are stored i n memory. I n a Von
Neumann type processor such as I ntel 8085, the CPU fetches one i nstructi on at a ti me from
the memory and executes i t. Fi rst of al l the CPU fetches the fi rst i nstructi on of the program
and executes i t. Then i t fetches the next i nstructi on to execute i t. The CPU repeats thi s
process ti l l i t executes al l the i nstructi ons of the program. Thereafter, i t may take another
program i f any, to execute.
The necessary steps that the processor has to carry out for fetchi ng an i nstructi on from
the memory and executi ng i t, consti tute an instruction cycle. An i nstructi on cycl e consi sts of
two partsa fetch cycle and an execute cycle. I n fetch cycl e the CPU fetches the machi ne code
of the i nstructi on (opcode) from the memory. The necessary steps that are carri ed out to fetch
an opcode from the memory consti tute a fetch cycle. I n execute cycl e an i nstructi on i s
executed. The necessary steps, whi ch are carri ed to execute an i nstructi on, consti tute an
execute cycle.
5.8.1 Fetch Operation
To fetch an opcode from a memory l ocati on the fol l owi ng steps are performed:
(i) The program counter pl aces the address of the memory l ocati on i n whi ch the
opcode i s stored, on the address bus.
(ii) The CPU sends the requi red memory control si gnal s so as to enabl e the memory
to send the opcode.
(iii) The opcode stored i n the memory l ocati on i s pl aced on the data bus and transferred
to the CPU.
Al l the above steps requi re three cl ock cycl es. I f memory i s sl ow the ti me taken may
be more. I n that case the CPU has to wai t for some ti me ti l l the memory transfers the opcode
to the CPU. The extra cl ock cycl es for whi ch the CPU wai ts are known as wait cycles. Most
of the mi croprocessors have ci rcui try to i ntroduce wai t cycl es to cope wi th sl ow memori es.
5.8.2 Execute Operation
The opcode whi ch i s fetched from the memory i s pl aced fi rst of al l i n the data regi ster,
DR (data/address buffer i n case of I ntel 8085). Thereafter i t goes to the i nstructi on regi ster,
I R. From the i nstructi on regi ster i t goes to the decoder ci rcui try, whi ch i s wi thi n the CPU.
The decoder ci rcui try decodes the opcode. After the opcode i s decoded the CPU comes to know
what operati on i s to be performed, and then executi on begi ns. I f the operand i s i n a general
purpose regi ster, the executi on i s i mmedi atel y performed. I n such a si tuati on the ti me
requi red for decodi ng and executi ng the i nstructi on i s onl y one cl ock cycl e. I f the requi red
data or operand address i s sti l l i n the memory, the CPU reads them from the memory. For
readi ng data or the operand address from the memory the CPU performs read operati on. The
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read cycl e i s si mi l ar to an opcode fetch cycl e. I n a read cycl e the quanti ty recei ved from the
memory i s data or address i nstead of opcode. After recei vi ng data from the memory, CPU
performs execute operati on. Some i nstructi ons may requi re wri te operati on. I n wri te cycl e
data are transferred from the CPU to the memory or an output devi ce. Thus we see that an
execute cycl e may i nvol ve one or more read or wri te cycl es or both.
5.8.3 Machine Cycle and State
The necessary steps, whi ch are carri ed out to access a memory or I /O devi ce, consti tute
a machi ne cycl e. I n other words necessary steps, whi ch are carri ed out to perform a fetch,
read or wri te operati on, consti tute a machine cycle. An i nstructi on cycl e consi sts of a number
of machi ne cycl es. I n one machi ne cycl e onl y one operati on such as opcode fetch, memory
read, memory wri te, I /O read or I /O wri te i s performed. The fi rst machi ne cycl e of an
i nstructi on cycl e i s an opcode fetch cycl e. The si ngl e-byte i nstructi ons are executed i n onl y
one machi ne cycl e. Two-byte and three-byte i nstructi ons need more machi ne cycl es, as ad-
di ti onal machi ne cycl es are requi red for readi ng/wri ti ng data from/i nto the memory or I /O
devi ces.
A state (or T-state) i s one subdi vi si on of an operati on performed i n one cl ock peri od.
These subdi vi si ons are i nternal states synchroni zed wi th the system cl ock. So one cl ock cycl e
of the system cl ock i s referred to as a state.
5.9 INSTRUCTION AND DATA FLOW
Two types of words: i nstructi on word (opcode) and data word are processed duri ng an
i nstructi on cycl e. At the begi nni ng of a fetch cycl e the contents of the program counter (i.e.,
the next memory address) are sent to the memory address regi ster, MAR, (Fi g. 5.3). From
MAR the memory address i s pl aced on the address bus so as to transfer i t to the memory.
Fig. 5.3 Address transfer to memory.
A read control i s sent by the CPU to the memory. Havi ng recei ved the address, the
memory pl aces the opcode on the data bus. Then the opcode i s recei ved i n the data regi ster
DR (Fi g 5.4). From DR the opcode i s sent to the i nstructi on regi ster, I R. Thereafter the
opcode i s decoded by the decoder ci rcui try and then executed.
Any data (or address) read from the memory i s al so recei ved i n data regi ster. From the
data regi ster the data are transferred to the accumul ator or any other general purpose
regi ster dependi ng on the i nstructi on, as shown i n Fi g 5.5. I f any data are sent to the memory
from the CPU, that data al so fl ow through DR.
5.18 COMPUTER FUNDAMENTALS
Fig. 5.4 Fl ow of i nstructi on word (Opcode).
Fig. 5.5 Fl ow of data word.
5.10 TIMING DIAGRAM
The ti mi ng di agram i s the graphi cal representati on of the necessary steps, whi ch are
performed i n a parti cul ar machi ne cycl e. The ti mi ng di agram for opcode fetch, memory read,
memory wri te, I /O read and I /O wri te of I ntel 8085 i s di scussed i n thi s secti on.
5.10.1 Timing Diagram for Opcode Fetch Operation
I n a fetch operati on the CPU fetches the opcode of an i nstructi on from the memory. Fi g.
5.6 shows the ti mi ng di agram for an opcode fetch operati on. T
1
, T
2
, T
3
and T
4
represent cl ock
cycl es. The sequence of the operati on i s gi ven bel ow:
(1) A l ow I O/M si gnal i s sent out by the mi croprocessor to i ndi cate that i t wants to
communi cate wi th the memory.
(2) Mi croprocessor sends out hi gh status si gnal s S
0
and S
1
to i ndi cate that fetch
operati on wi l l be performed.
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Fig. 5.6 Ti mi ng di agram for opcode fetch operati on.
(3) Mi croprocessor sends out the address of the memory l ocati on where the opcode i s
stored. The 16-bi t memory address i s sent over the address bus A (A
8
A
15
) and
address/data bus AD (AD
0
AD
7
) duri ng the fi rst cl ock cycl e (T
1
) of a machi ne cycl e.
The 8 MSBs of the address are transmi tted through A-bus and 8 LSBs of the
address through AD-bus.
(4) As the AD-bus i s requi red for data transfer duri ng subsequent cl ock cycles T
2
and
T
3
, i t has to be made avai l abl e for thi s purpose. Therefore, the 8 LSBs of the
address have to be l atched i nto peri pheral . The mi croprocessor sends out an ALE
si gnal to l atch the 8 LSBs of the address i nto peri pheral so that compl ete 16-bi t
address i s avai l abl e i n the subsequent cl ock cycl es. 8 LSBs of the address remai n
on AD bus onl y for T
1
state.
AD bus i s a ti me-mul ti pl exed bus, i.e., i t serves dual purpose. Duri ng the fi rst cl ock cycl e
i t carri es 8 LSBs of the address, and duri ng the second and thi rd cl ock cycl es i t carri es data.
(5) The AD-bus becomes avai l abl e to carry data duri ng T
2
.
(6) A control si gnal RD sent out by the mi croprocessor goes l ow duri ng T
2
to enabl e
the memory for read operati on.
(7) The memory pl aces the opcode on the data bus.
(8) The opcode i s recei ved by the mi croprocessor through the data bus.
(9) The opcode i s pl aced i nto data regi ster, DR. From DR i t goes to I R.
5.20 COMPUTER FUNDAMENTALS
(10) RD goes hi gh duri ng T
3
. When RD goes hi gh the memory i s di sabl ed.
(11) I n T
4
the opcode i s sent to decodi ng ci rcui try from I R. The opcode i s decoded i n
T
4
.
(12) I f the i nstructi on i s of si ngl e-byte, the executi on i s al so compl eted i n T
4
, as operands
are i n the general -purpose regi sters. Decodi ng and executi on are compl eted i n T
4
.
Exampl es of si ngl e-byte i nstructi ons are: MOV r
1
, r
2
; SUB r, ADD r, RAL etc.
(13) I f the i nstructi ons are of 2- or 3-bytes, more machi ne cycl es are requi red. The fi rst
machi ne cycl e M
1
i s for fetchi ng the opcode from the memory. Subsequent machi ne
cycl es M
2
, M
3
etc. are requi red ei ther to read data or address from the memory
or I /O devi ces (or to wri te data i nto memory or I /O devi ces).
5.10.2 Timing Diagram for Memory Read Operation
I n a memory read operati on the CPU reads ei ther data or address from the memory. The
data are recei ved i n DR and then go to the accumul ator or any other regi ster of the CPU
accordi ng to the i nstructi on. Let us take an exampl e of a two-byte i nstructi on.
MVI A, 08 : Move 08 i n the accumul ator
3E, 08 : The above i nstructi on i n the coded form.
Fig. 5.7 Ti mi ng di agram for memory read operati on.
3E i s the opcode for MVI A i nstructi on and 08 i s the data. Thi s i nstructi on needs two
machi ne cycl es M
1
and M
2
. The fi rst machi ne cycl e M
1
i s to fetch the opcode 3E from the
memory. The ti mi ng di agram for opcode fetch operati on was shown i n Fi g. 5.6. The second
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machi ne cycl e M
2
i s for readi ng the data, 08 from the memory as shown i n Fi g. 5.7. The
memory read cycl e i s si mi l ar to opcode fetch cycl e except that the status si gnal s S
0
and S
1
are 0 and 1 respecti vel y for read operati on. Al l other descri pti ons gi ven for fetch cycl e are
al so true for a read cycl e. The memory address sent by the mi croprocessor i n thi s case i s the
address of the memory l ocati on where the data 08 are stored.
Now l et us take an exampl e of a si ngl e-byte i nstructi on, whi ch requi res a memory read
cycl e i n addi ti on to opcode fetch cycl e:
(1) ADD M : Add the content of the memory l ocati on whose address i s i n
H-L pai r, to the content of the accumul ator.
86 : The i nstructi on i n the coded form.
Thi s i nstructi on requi res two machi ne cycl es. I n the fi rst machi ne cycl e the opcode 86
i s fetched from the memory. The second machi ne cycl e i s a memory read cycl e i n whi ch the
contents of the memory l ocati on, whose address i s i n H-L pai r, are brought i nto the CPU.
Thereafter the addi ti on operati on i s al so performed i n the second machi ne cycl e.
(2) MOV A, M : Move the content of the memory l ocati on, whose address i s i n
H-L pai r, to the accumul ator.
7E : The i nstructi on i n the coded form.
Thi s i nstructi on requi res two machi nes cycl es. I n the fi rst machi ne cycl e the opcode 7E
i s fetched from the memory. The second machi ne cycl e i s a memory read cycl e i n whi ch the
contents of the memory l ocati on, whose address i s i n H-L pai r, are moved to the accumul ator.
(3) Let us now consi der three-byte i nstructi ons:
(i) LXI H, 2400H : Load H-L pai r wi th 2400H
21, 00, 24 : The above i nstructi on i n the coded form.
Thi s i nstructi on needs three machi ne cycl es: one opcode fetch cycl e and two consecuti ve
memory read cycl es. I n the fi rst machi ne cycl e M
1
, the CPU fetches the opcode, 21. I n the
second machi ne cycl e M
2
, the CPU reads 8 LSBs (i .e., 00) of the data 2400H. I n the thi rd
machi ne cycl e M
3
, the CPU reads 8MSBs (i.e., 24) of the data 2400.
(ii) LDA 2500H : Load accumul ator wi th the contents of the memory l ocati on
2500H.
3A, 00,25 : The above i nstructi on i n the coded form
Thi s i nstructi on requi res 4 machi ne cycl es. The fi rst machi ne cycl e i s the fetch cycl e i n
whi ch the opcode 3A i s fetched from the memory. The second machi ne cycl e i s a memory read
cycl e i n whi ch the 8 LSBs (i.e., 00) of the memory address 2500H are read. The thi rd machi ne
cycl e i s a memory read cycl e i n whi ch 8 MSBs (i.e., 25) of the memory address 2500H are
read. The fourth machi ne cycl e i s al so a memory read cycl e i n whi ch the CPU reads the
content of the memory l ocati on 2500H and pl aces i t i n the accumul ator.
5.10.3 I/O Read Operation (IOR)
I n an I /O read operati on the CPU reads data from the i nput devi ce or i nput port. The
data are pl aced i n the accumul ator. Read operati on i s not performed wi th an output devi ce.
The termi nol ogy I OR or I /O i s used because i nput/output (I /O) are used together i n the
l i terature. An I /O read cycl e i s si mi l ar to memory read cycl e except that I O/M si gnal i s hi gh
i n case of I /O read operati on. I n the ti mi ng di agram for I /O read cycl e al l other si gnal s remai n
same as shown i n Fi g. 5.7. A hi gh I O/M si gnal i ndi cates that the address on the address bus
5.22 COMPUTER FUNDAMENTALS
i s for an i nput devi ce or i nput port. An I /O devi ce or an I /O port has address onl y 8-bi t l ong,
and hence the I /O address i s dupl i cated on A and AD-buses. I n case of an I /O read operati on
the external l atchi ng of 8 LSBs of the I /O address i s not requi red because the I /O address
i s avai l abl e on the A-bus ti l l the end of the I /O read cycl e. I N i nstructi on i s used for I /O read
operati on.
Example:
IN 02 : Read data from i nput devi ce whose address i s 02.
DB,02 : The above i nstructi on i n the coded form.
Thi s i nstructi on i s 2-byte l ong. I t takes three machi ne cycl es. I n the fi rst machi ne cycl e
the opcode DB i s fetched from the memory. The second machi ne cycl e i s a memory read cycl e
to read the address (i .e., 02) of i nput devi ce from the memory. The thi rd machi ne cycl e i s an
I /O read cycl e i n whi ch the CPU reads data from the i nput devi ce whose address i s 02.
5.10.4 Memory Write Operation
I n a memory wri te operati on data are transferred from the CPU to the memory. The
data are transferred from the accumul ator or any other general -purpose regi ster to the
memory dependi ng on the i nstructi on. Fi g. 5.8 shows the ti mi ng di agram for memory wri te
cycl e. The I O/M si gnal i s l ow to i ndi cate that the CPU wi l l communi cate wi th memory. The
status si gnal S
0
and S
1
are 1 and 0 respecti vel y for wri te operati on to be performed. The CPU
sends 16-bi t memory address through A and AD-buses. The ALE si gnal i s sent i n T
1
state to
l atch 8 LSBs of the memory address. During T
2
the AD-bus i s not di sabl ed as i t i s done i n
the case of memory read operati on. Rather data to be transferred to the memory from the
accumul ator or any other regi ster are pl aced on the AD-bus. The control si gnal for wri te
operati on WR goes l ow duri ng T
2
to enabl e the memory for wri te operati on. The data sent
by the CPU are stored i n the memory l ocati on whose address was sent by the CPU. WR goes
hi gh duri ng T
3
. When WR goes hi gh the memory i s di sabl ed.
Example 1
STA 2400H : Store the content of accumul ator i n the memory l ocati on 2400H
32,00,24 : The i nstructi on i n the coded form.
Thi s i nstructi on needs four machi ne cycl es. The fi rst machi ne cycl e i s opcode fetch cycl e
to read opcode, 32 from the memory. The second machi ne cycl e i s a memory read cycl e to
read 00, 8 LSBs of the memory address. The thi rd machi ne cycl e i s al so a memory read cycl e
to read 24, the 8 MSBs of the memory address. The fourth machi ne cycl e i s a memory wri te
cycl e i n whi ch CPU sends data to store i n the memory l ocati on 2400H.
Example 2
MOV M, A : Move the content of the accumul ator to the memory l ocati on,
whose address i s i n H-pai r.
77 : The i nstructi on i n the coded form.
Thi s i s a si ngl e-byte i nstructi on. I t requi res 2 machi ne cycl es. The fi rst machi ne cycl e
i s an opcode fetch cycl e to fetch 77 from the memory. The second machi ne cycl e i s a memory
wri tes cycl e i n whi ch the contents of the accumul ator are transferred to the memory l ocati on,
whose address i s i n H-L pai r.
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Fig. 5.8 Ti mi ng di agram for memory wri te operati on.
5.10.5 I/O Write Operation (IOW)
I n an I /O wri te operati on the CPU transfers data from the accumul ator to an i nput
devi ce of i nput port. An I /O wri te cycl e i s si mi l ar to a memory wri te cycl e except that the
control si gnal I /OM i s hi gh i n case of I /O wri te operati on. I n the ti mi ng di agram for
I /O wri te cycl e al l other si gnal s remai n same as shown i n Fi g. 5.8 As the address of an
I /O devi ce i s of onl y 8 bi ts, i t i s dupl i cated on A and AD-bus. I n case of an I /O wri te operati on
the external l atchi ng of 8 LSBs of the I /O address i s not requi red because i t i s avai l abl e
on the A-bus ti l l the end of the I /O wri te cycl e. OUT i nstructi on i s used for I /O wri te
oper ati on.
Example
OUT 01 : Transfer the contents of the accumul ator to an output devi ce
whose address i s 01.
D3, 01 : The i nstructi on i n the coded form.
I t i s a 2-byte i nstructi on. I t requi res 3 machi ne cycl es. I n the fi rst machi ne cycl e the
opcode D3 i s fetched from the memory. The second machi ne cycl e i s a memory read cycl e
i n whi ch the address of the output devi ce, 01 i s read from the memory. The thi rd machi ne
cycl e i s an I /O wri te cycl e i n whi ch the content of the accumul ator i s transferred to the output
devi ce whose address i s 01.
5.24 COMPUTER FUNDAMENTALS
5.11 MICROPROCESSORS
Mi croprocessors of I ntel , AMD (Advanced Mi cro Devi ces). Motorol a and SUN are popul ar
i n I ndi a. Some i mportant mi croprocessors of these manufacturers are descri bed i n thi s and
subsequent secti ons.
8-Bit Microprocessors. I mportant 8-bi t mi croprocessors are: I ntel 8085, Motorol a 6809,
Zi l og Z80, Zi l og Z800 etc.
I ntel 8088 has i ts data bus of 8-bi ts but i ts i nternal archi tecture i s of 16-bi ts.
16-Bit Microprocessors. I mportant 16-bi t mi croprocessors are: I ntel 8086, I ntel 80286,
Motorol a 68000, Zi l og 8000 etc.
32-Bit Microprocessors. I mportant 32-bi t mi croprocessor are: I ntel 486, Penti um, Penti um
Pro, Penti um I I , Cel eron, Penti um I I I , Penti um 4, AMDs Athl on, Power PC 601, 603, 604,
740 and 760, etc.
64-Bit Microprocessors. 64-bi t mi croprocessors are DECs Al pha 21264, Power PC 620,
SUNs ULTRASPARC, MI PS-12000, I ntel s Penti um 4EE, I tani um, HPs PA8500 etc.
5.12 INTEL 8085
I t i s an 8-bi t mi croprocessor. I t i s i mpl emented i n NMOS technol ogy. I t i s a 40-pi n LSI
chi p. I t empl oys 5 Vd.c. suppl y for i ts operati on. 3, 5 and 6 MHz cl ocks are empl oyed for the
di fferent versi ons of 8085. I t has 80 basi c i nstructi ons and 246 opcodes.
I ts pi n confi gurati on, regi ster organi zati on, i mportant i nstructi ons, i nstructi on format,
addressi ng modes, ti mi ng di agram etc. have al ready been di scussed i n the previ ous secti ons
of thi s chapter. I t i s wi del y used i n mi croprocessor ki ts i n the l aboratory for trai ni ng students.
I ts descri pti on gi ves a cl ear i dea of mai n features of a CPU, and i t i s si mpl e to understand
for begi nners. Due to these reasons i t i s taught i n detai l i n the fi rst course on mi croproces-
sors i n El ectri cal , El ectroni cs and Computer Engi neeri ng. Once a student understands 8085,
i t becomes easy to understand other more compl ex mi croprocessors. 8-bi t mi croprocessor-
based system and 8-bi t mi crocontrol l ers are wi del y used i n si mpl e i ndustri al control , equi p-
ment control , i nstrumentati on etc.
5.13 INTEL 8086
I t i s a 16-bi t, N-channel , HMOS mi croprocessor. I t i s bui l t i n 40-pi n I C package. I t
empl oys 5 Vd.c. suppl y for i ts operati on. I t was i ntroduced i n 1978. I t contai ns a ci rcui try of
29000 transi stors. I t has 20 address l i nes. I t can di rectl y address up to 1 MB memory. I ts data
bus i s 16-bi t wi de. I ts address l i nes are ti me mul ti pl exed. 16 l ow order address l i nes are
mul ti pl exed wi th data l i nes and 4 hi gh order address l i nes are mul ti pl exed wi th status si gnal s.
I t performs ari thmeti c operati ons i n bi nary or deci mal i ncl udi ng mul ti pl i cati on and di vi si on.
I ts cl ock rates are: 5, 8 and 10 MHz for i ts di fferent versi ons. I t can be i nterfaced wi th 8087
numer i c data copr ocessor for fast mathemati cal computati on. The knowl edge of 8086
mi croprocessor i s essenti al as i t forms the basi s of other I ntel s mi croprocessors. 16-bi t
processor-based system and 16-bi t mi crocontrol l ers are used i n i ndustri al , commerci al and
equi pment control appl i cati ons, i nstrumentati on etc. The 8086-mi croprocessor ki ts are used
i n the l aboratory for engi neeri ng students trai ni ng.
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5.13.1 Operating Modes of 8086
I t has two operati ng modes: the mi ni mum mode and the maxi mum mode. The mi ni mum
mode of operati on i s for a si mpl e system, whi ch empl oys onl y one CPU and has a few
peri pheral s. The maxi mum mode of operati on i s used when 8086 operates i n mul ti processor
envi ronment. I t i s equi pped wi th a strap pi n MN/MX whi ch defi nes i ts modes of operati on.
When MN/MX i s hi gh i t operates i n the mi ni mum mode. When MN/MX i s l ow i t operates
i n the maxi mum mode. Two di fferent sets of si gnal s are i ssued by the processor through the
pi ns 24 to 31. One set of si gnal s are i ssued by the mi croprocessor through these pi ns when
i t operates i n the mi ni mum mode. The second set of si gnal s are i ssued through the same pi ns
when i t operates i n the maxi mum mode.
5.13.2 Register Organization
The 8086 has fourteen 16-bi t regi sters as shown i n Fi g. 5.9A. They are cl assi fi ed i nto the
fol l owi ng groups:
(i) General purpose regi sters
(ii) Poi nter and i ndex regi sters
(iii) Segment regi sters
(iv) I nstructi on poi nter and status regi ster.
General Purpose Registers
There are four 16-bi t general purpose regi sters: AX, BX, CX, and DX. Each general
purpose regi ster consi sts of two 8-bi t regi sters. For exampl e, AX consi sts of AH and AL. AH
i s an 8-bi t hi gh-order regi ster and AL i s an 8-bi t l ow order regi ster. Si mi l arl y, BX consi sts of
BH and BL, and so on as shown i n Fi g. 5.9A. AX serves as an accumul ator. BX, CX and DX
are used as general purpose regi sters. Besi des servi ng as general purpose regi sters these
regi sters al so serve as speci al purpose regi sters. BX serves as a base regi ster for the com-
putati on of effecti ve memory address. CX i s al so used as a counter. DX i s cal l ed data regi ster.
Some I /O i nstructi ons move data between an i denti fi ed I /O port and the memory l ocati on
addressed by regi ster DX.
Pointer and Index Registers
Poi nter and i ndex regi sters as shown i n Fi g. 5.9A are as fol l ows:
(i) Stack poi nter, SP
(ii) Base poi nter, BP
(iii) Source i ndex, SI
(iv) Desti nati on i ndex, DI
SP acts as a stack poi nter as di scussed i n case of 8085. BP, SI and DI are empl oyed i n
the cal cul ati on of memory address.
Segment Registers
The 8086 has the fol l owi ng segment regi sters:
(i) Code segment regi ster, CS
(ii) Data segment regi ster, DS
(iii) Stack segment regi ster, SS
(iv) Extra segment regi ster, ES
5.26 COMPUTER FUNDAMENTALS
The segment regi sters poi nt to the starti ng address of the vari ous memory segments.
See detai l s i n Sec. 5.13.6.
Instruction Pointer
I t acts as a program counter. I t poi nts to the next i nstructi on to be executed. The content
of the code segment regi ster i s added to the content of i nstructi on poi nter to compute the
address of next i nstructi on.
Fig. 5.9A I ntel 8086 regi ster organi sati on.
Status Flags
The 8086 has a 16-bi t status regi ster. I t has 9 status fl ags as shown i n Fi g. 5.10. The
O fl ag i ndi cates overfl ow. The fl ag D i s di recti on fl ag. When i t i s 1, the i ndex regi sters SI and
DI are decremented resul ti ng i n the access of stri ngs from the hi ghest memory address down
the l owest memory address. I f the di recti on status i s 0, the i ndex regi sters SI and DI are
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i ncremented resul ti ng i n the access of stri ngs from the l owest memory address. The trap
status T i s a debuggi ng ai d for si ngl e step operati on of 8086. The i nterrupt status, I enabl es
or di sabl es i nterrupts. When i t i s 1, the i nterrupts are enabl ed. When I i s 0, the i nterrupts
are di sabl ed. Al l other fl ags are si mi l ar to those of 8085. D, T and I fl ags are control fl ags
and others are condi ti on fl ags. Fi g. 5.9B shows the bl ock di agram of I ntel 8086.
Fig. 5.9B Bl ock Di agram of I ntel 8086.
5.13.3 Pin Configuration of 8086
Fi g. 5.11 shows the pi n di agram of 8086. For pi n descri pti on see Appendi x 2. The
si gnal s shown by the si de of pi ns 24 to 31 are for the maxi mum mode of operati on. The
si gnal s shown i n the brackets agai nst the pi ns 24 to 31 are for the mi ni mum mode of
operati on. I n Fi g. 5.11 the di recti on shown for si gnal s at pi n 30 and 31 are for RQ/GT0
and
RQ/GT1
i n the maxi mum mode of oper ati on. I n the mi ni mum mode of oper ati on the
di recti on of HOLD wi l l be i nward and that for HLDA outward. The 8288, a bus control l er
i s desi gned to be used wi th 8086 i n the maxi mum mode of operati on. I t generates control
si gnal s for memory and I /O devi ces such as memory read, memory wri te, I /O read, I /O
wri te, i nterrupt acknowl edge, etc.
5.28 COMPUTER FUNDAMENTALS
Fig. 5.10 Status fl ags of I ntel 8086.
Fig. 5.11 Pi n di agram of 8086.
5.13.4 Operating Principle
The i nternal archi tecture of 8086 i s parti ti oned l ogi cal l y i nto two processi ng uni ts: a bus
interface unit (BI U) and an execution unit (EU). The memory and I /O devi ces connected to
the 8086 are handl ed by BI U. I ts functi on i s to transfer i nstructi on and data between the
processor and peri pheral s. The functi on of the executi on uni t (EU) i s to decode and execute
i nstructi ons.
The BI U fetches opcodes from the memory, and mai ntai ns a 6-byte queue for the
opcodes. Besi des opcode fetchi ng and mai ntai ni ng a queue i ts other functi ons are address
rel ocati on, operand fetchi ng and stori ng, and resul t stori ng. When EU desi res I /O or memory
access, i t makes bus access request to BI U. I f BI U i s not currentl y busy, i t acknowl edges
the request. The EU sends un-rel ocated operand address to BI U. The EU recei ves operand
through BI U.
The EU recei ves the opcode from the queue, decodes and executes i t. The queue i s a
fi rst-i n-fi rst-out (FI FO) buffer. The queue i s al ways fi l l ed-up by the BI U when at l east two
bytes of the queue fal l vacant. The operati on of BI U and EU are i ndependent of each other,
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but they can i nteract i f requi red. Whi l e EU i s executi ng i nstructi ons, the BI U fetches opcodes
from the memory. The overl appi ng of executi on of i nstructi ons and fetchi ng of i nstructi ons
makes 8086 a faster processor. Fetchi ng of next i nstructi on whi l e the current i nstructi on i s
bei ng executed i s cal l ed pipelining. Fi g. 5.9B shows the bl ock di agram of I ntel 8086.
5.13.5 Interrupts
The 8086 has two hardware i nterrupts: I NTR and NMI . The NMI i s a nonmaskabl e
i nterrupt. I t has hi gher pri ori ty than I NTR. The I NTR i s a maskabl e i nterrupt. On recei pt
of I NTR, the 8086 i ssues an acknowl edgement I NTA. On the occurrence of i nterrupts; CS,
I P and status fl ags are saved i nto stack. I f necessary, the programmer can al so save other
regi sters i nto the stack. The I NTR can be masked by cl eari ng i nterrupt fl ag I . The i nterrupt
fl ag i s cl eared by executi ng CLI i nstructi on. The i nterrupt fl ag i s automati cal l y cl eared when
an i nterrupt i s recogni zed. The fl ag can be reset on the return from an i nterrupt servi ce
subrouti ne by executi ng I RET i nstructi on. I t can al so be set expl i ci tl y by executi ng the
i nstructi on STI .
The maskabl e hardware i nterrupt I NTR i s used by I /O devi ces. I t can be shared by a
number of external devi ces. Each external i nterrupti ng devi ce has i ts own I SS. When an
i nterrupt occurs the CPU sends an acknowl edgement. Duri ng the i nterrupt acknowl edge
sequence the i nterrupti ng external devi ce suppl i es an 8-bi t vector. Thi s 8-bi t vector poi nts to
an entry of a l ook-up tabl e stored i n the memory. The l ook-up tabl e contai ns the starti ng
addresses for I SS. Thi s l ook-up tabl e i s known as interrupt vector table. I t contai ns 256
entri es. Each entry contai ns 4-byte quanti ty consi sti ng of two 16-bi t addresses, whi ch provi des
the address of the next i nstructi on to be executed. These addresses are l oaded i nto CS and
I P to update them. Before updati ng CS, I P and fl ags are saved i n the stack on the occurrence
of an i nterrupt.
There are I NT and I NTO i nstructi ons to generate software i nterrupts.
The 8086 generates an i nterrupt when di vi sor i s zero i n case of di vi si on operati on.
For checki ng a program, i t can be executed step by step. I n one step one i nstructi on i s
executed. Thi s process i s known as si ngl e steppi ng or traci ng. The 8086 has a hardware
feature to control si ngl e step operati on. I t i s done by the trap fl ag, T. When T fl ag i s set to
1, an i nterrupt i s generated.
5.13.6 Memory Organization of 8086
The 8086 has 20 address l i nes. I t can di rectl y address upto 1 MB memory. The 16 address
lines AD
0
AD
15
are mul ti pl exed wi th data l i nes. When they carry address they can be
abbrevi ated as A
0
A
15
. When they carry data they can be abbrevi ated as D
0
D
15
. The address
l i nes A
16
A
19
are al so mul ti pl exed wi th status si gnal s (for detai l s see Appendi x 2).
The memory used wi th 8086 i s di vi ded i nto 4 segments:
(i) Code segment
(ii) Data segment
(iii) Stack segment
(iv) Extra segment
The capaci ty of each segment may be upto 64 KB. A segment regi ster poi nts to the
starti ng address of a parti cul ar memory segment. For exampl e, the code segment regi ster
poi nts to the starti ng address of the code segment, data segment regi ster i ndi cates the
5.30 COMPUTER FUNDAMENTALS
starti ng address of the data segment, and so on. The memory address i s computed usi ng the
contents of a segment regi ster and an effecti ve memory address. The effecti ve memory
address i s computed through a vari ety of addressi ng modes. The i nstructi on codes resi de i n
the code segment. I f any stack i s used i n the program, i t resi des i n the stack segment. Local
data, vari abl es and constants resi de i n the data segment. External (gl obal ) data resi de i n the
extra segment.
Physi cal l y, the memory i s organi zed i nto two banks of 512 K bytes (maxi mum si ze of
each bank) as shown i n Fi g. 5.12. The l ow order memory bank uses D
0
D
7
l i nes for data
transfer. D
8
D
15
are used by hi gh order memory banks. A
0
and BHE are used as memory
chi p sel ect si gnal s. When both A
0
and BHE are l ow a word i s transferred. When A
0
i s l ow
and BHE i s hi gh a byte from/to even memory address i s transferred. When BHE i s l ow and
A
0
hi gh, a byte from/to odd memory address i s transferred. Any two consecuti ve bytes i n the
memory form a word. The address of the l east si gni fi cant byte forms the word address. A
word can start ei ther from an even address or from an odd address. To transfer a word the
BI U requi res 1 or 2 memory cycl es dependi ng on whether the starti ng byte of the word i s
an even or odd address respecti vel y. Consequentl y, for transferri ng a word the performance
can be opti mi zed i f data start from even addresses. Thi s i s speci al l y a useful techni que for
stack handl i ng.
Fig. 5.12 Memory organi sati on of 8086 for word and byte addressi ng.
5.13.7 Semaphore
I n a ti me shared system common resources may be used by more than one user. A
pri nter can be taken as an exampl e of a common resource. Suppose, one user i s pri nti ng hi s
resul t. As the computer gi ves onl y 20 mi l l i second ti me to each user, hi s turn i s over before
hi s pri nti ng work i s compl eted. Now the turn of the second user comes. Suppose, he al so
wants to pri nt hi s resul t. Hi s turn al so may be over before hi s pri nti ng work i s compl eted.
Thus the pri nti ng of both users are mi xed. To overcome thi s di ffi cul ty semaphore i s used. I t
i s a software techni que. I t i s a fl ag. When a user i s usi ng a common resource, the semaphore
i s set to 1. When i t i s set to 1, the common resource can not be used by any other user. On
the compl eti on of the work the semaphore i s set to 0.
5.13.8 Lock
I t i s an i nstructi on prefi x. I t prevents another processor from taki ng control over the
buses whi l e the next i nstructi on i s bei ng executed.
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I n a mul ti processor system each mi croprocessor has i ts own l ocal buses and memory.
The mi croprocessors are connected through the system bus so that each mi croprocessor can
access the common resources when needed. When a mi croprocessor i s executi ng certai n
cri ti cal i nstructi on usi ng system bus, any other processor shoul d not take over the control
of the system bus. Thi s i s achi eved usi ng LOCK i nstructi on as prefi x before the cri ti cal
i nstructi on. I t prevents any other processor from taki ng control over the system bus when
one processor i s i n the mi ddl e of a cri ti cal i nstructi on whi ch uses the system bus. The
LOCK i nstructi on acti vates the pi n
LOCK
whi ch i s acti ve l ow and connected to the bus
contr ol l er. When
LOCK
i s l ow, the other pr ocessor i s not gr anted r equest to take the
control over the system bus.
5.13.9 Intel 8086 Instructions
Detai l ed di scussi on of I ntel 8086 i nstructi ons i s beyond the scope of the book. Onl y a few
i mportant i nstructi ons are descri bed i n thi s secti on.
5.13.9.1 MOV Instructions
By MOV i nstructi on data can be transferred from regi ster to regi ster, from regi ster to
memory or from memory to regi ster. But data transfer from memory to memory i s not
al l owed. By MOV i nstructi on i mmedi ate data can al so be transferred to regi ster or memory.
Exampl es are:
(i) MOV AX, BX ; the contents of BX regi ster i s transferred to AX regi ster,
16-bi t data transfer.
(ii) MOV DX, CX ; [DX] [CX]. The content of CX i s moved to DX.
(iii) MOV BL, CL ; the content of CL regi ster i s transferred to BL regi ster,
8-bit data transfer.
(iv) MOV [0301H], AX ; the content of AX regi ster i s transferred to the memory
l ocati on 0301 H and 0302H, 16-bi t data transfer.
(v) MOV [0301], CL ; the content of CL regi ster i s transferred to the memory
l ocati on 0301H; 8-bi t data transfer.
(vi) MOV AL , [BX] ; 8-bi t data transfer from the memory l ocati on addressed by
BX regi ster to AL regi ster.
(vii) MOV AX, [BX] ; 16-bi t data transfer from two consecuti ve memory l ocati ons
addressed by BX regi ster to the regi ster AX.
(viii) MOV AL, 65H ; i mmedi ate data 65H i s transferred to AL regi ster, 8-bi t
data transfer.
(ix) MOV CX , 3456H ; 16-bi t data transfer. 3465H i s transferred to CX regi ster.
5.13.9.2 ADD Instructions
By ADD i nstructi on the fol l owi ng operati ons are al l owed:
(a) Add regi ster to regi ster
(b) Add regi ster to memory
5.32 COMPUTER FUNDAMENTALS
(c) Add memory to regi ster
(d) Add i mmedi ate data to regi ster
(e) Add i mmedi ate data to memory
Examples are:
(i) ADD AL, CL ; the content of CL i s added to the content of AL and the
resul t i s pl aced i n AL.
(ii) ADD CL, AL ; the content of AL i s added to the content of CL and the
resul t i s pl aced i n CL.
(iii) ADD AX, BX ; the content of BX i s added to the content of AX and the
resul t i s pl aced i n AX.
(iv) ADD BX , AX ; the content of AX i s added to the content of BX and the
resul t i s pl aced i n BX.
(v) ADD AX, [0301H] ; the contents of memory l ocati ons 0301H and 0302H are
added to the contents of AX ; the resul t i s pl aced i n AX.
(vi) ADD [0301H], AX ; the contents of AX i s added to the contents of two consecu-
ti ve memory l ocati ons 0301H and 0302H; resul t i s pl aced
i n the memory l ocati ons 0301H and 0302H.
(vii) ADD AL, [0201H] ; the content of the memory l ocati on 0201H i s added to the
content of AL. The resul t i s pl aced i n AL.
(viii) ADD [0201H], AL ; [0201H][0201H] + [AL]
(ix) ADD AL, [BX] ; the content of the memory l ocati on addressed by BX reg-
i ster i s added to the content of AL regi ster. The resul t i s
placed in AL regi ster
(x) ADD [BX], AL ; The content of AL regi ster i s added to the content of
memory l ocati on addressed by BX regi ster and the resul t
i s pl aced i n the memory l ocati on addressed by BX regi ster.
(xi) ADD AX, [BX] ; The content of memory l ocati ons addressed by BX regi ster
i s added to the content of AX regi ster and the resul t i s
placed in AX regi ster.
(xii) ADD [BX], AX ; The content of AX regi ster i s added to the content of memory
l ocati ons addressed by BX regi ster and the resul t i s pl aced
i n the memory l ocati ons addressed by BX regi ster.
(xiii) ADD AX, 3594H ; Add 3594H to the content of AX regi ster. Pl ace the resul t
in AX.
(xiv) ADD CL, 59H ; Add 59H to the content of CL regi ster. Pl ace resul t i n CL
r egi ster.
5.13.9.3 Multiplication Instructions
There are two types of mul ti pl i cati on i nstructi on:
(i) MUL reg or memory. Thi s i nstructi on i s for the mul ti pl i cati on of two unsi gned
numbers. Mul ti pl i cati on of an 8-bi t number by an 8-bi t number or 16-bi t number
by 16-bi t number i s al l owed.
(ii) IMUL reg or memory. Thi s i nstructi on i s for the mul ti pl i cati on of two si gned
numbers.
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MUL reg or memory. I n thi s i nstructi on both operands are unsi gned operands. The
resul t i s an unsi gned number. For 8-bi t mul ti pl i cati on one operand i s i n AL regi ster and the
other operand i s i n any other 8-bi t regi ster or a memory l ocati on. The resul t i s stored i n AX
regi ster. For 16-bi t mul ti pl i cati on one operand i s i n AX regi ster and the other operand i s i n
any other 16-bi t regi ster or two consecuti ve memory l ocati ons. The resul t i s stored i n DX and
AX regi sters. The l ow-order 16 bi ts are stored i n AX regi ster and the hi gh-order 16 bi ts are
stored i n DX regi ster. Exampl es are:
(i) MUL CL ; one operand i s i n AL. The content of AL i s mul ti pl i ed
by the content of CL. The resul t i s i n AX.
(ii) MUL CX ; one operand i s i n AX. The content of AX i s mul ti pl i ed
by the content of CX. The resul t i s i n DX : AX.
(iii) MUL BYTE PTR [BX] ; the content of AL i s mul ti pl i ed by the memory l oca-
ti on addressed by BX regi ster. BYTE PTR i s a prefi x
used i n assembl y l anguage for 8-bi t mul ti pl i cati on.
The resul t i s i n AX.
(iv) MUL WORD PTR [BX] ; the content of AX i s mul ti pl i ed by the content of two
consecuti ve memory l ocati ons addressed by BX regi s-
ter. WORD PTR i s a prefi x to i ndi cate 16-bi t operati on.
The resul t i s i n DX : AX.
IMUL reg or memory. I n thi s i nstructi on both operands are si gned numbers. The
resul t i s a si gned number. Mul ti pl i cati on of an 8-bi t number by an 8-bi t number or 16-bi t
number by a 16-bi t number i s al l owed. For 8-bi t mul ti pl i cati on one operand i s hel d i n AL
regi ster and the other operand i s i n any other 8-bi t regi ster or a memory l ocati on. The resul t
i s stored i n AX regi ster. For 16-bi t mul ti pl i cati on one operand i s i n AX regi ster and the other
operand i n any other 16-bi t regi ster or two consecuti ve memory l ocati ons.. The resul t i s
stored i n DX and AX regi sters. The 16 LSBs are stored i n AX regi ster and 16 MSBs are stored
i n DX regi ster. Exampl es are:
(i) I MUL CL ; The content of AL i s mul ti pl i ed by the content of CL.
The resul t i s in AX.
(ii) I MUL CX ; Mul ti pl y [AX] by [CX]. The resul t i s i n DX : AX.
(iii) I MUL BYTE PTR [BX] ; Mul ti pl y [AL] by [BX]. The resul t i s i n AX.
(iv) I MUL WORD PTR [BX] ; Mul ti pl y [AX] by [BX]. The resul t i s i n DX : AX.
5.13.9.4 Division Instructions
There are two types of di vi si on i nstructi on:
(i) DIV reg or mem. Thi s i nstructi on i s used to di vi de an unsi gned number by an
unsi gned number.
(ii) IDIV reg or memory. Thi s i nstructi on i s used to di vi de a si nged number by a
si gned number.
DIV reg or mem. Thi s i nstructi on al l ows to di vi de a 32-bi t unsi gned number by a 16-
bi t unsi gned number or to di vi de a 16-bi t unsi gned number by an 8-bi t unsi gned number. The
32-bi t di vi dend i s hel d i n DX and AX regi sters. The 16-bi t di vi sor i s hel d i n a 16-bi t regi ster
or two consecuti ve memory l ocati ons. The 16-bi t quoti ent i s stored i n AX regi ster and the 16-
bi t remai nder i s stored i n DX regi ster. I f the di vi dend i s of 16-bi t, i t i s hel d i n AX regi ster.
The 8-bi t di vi sor i s hel d i n an 8-bi t regi ster or a memory l ocati on. The 8-bi t quoti ent i s stored
in AL regi ster and the 8-bi t remai nder i s stored i n AH regi ster. The exampl es are:
5.34 COMPUTER FUNDAMENTALS
(i) DI V CL ; thi s i nstructi on di vi des the content of AX regi ster by
the content of CL regi ster.
(ii) DI V CX ; thi s i nstr ucti on di vi des the content of DX : AX
regi sters by the content of CX regi ster.
(iii) DI V BYTE PTR [BX] ; thi s i nstructi on di vi des the content of AX regi ster by
the content of the memory l ocati on addressed by BX
r egi ster.
(iv) DI V WORD PTR [BX] : thi s i nstr ucti on di vi des the content of DX : AX
regi sters by the content of two consecuti ve memory
l ocati ons addressed by BX regi ster.
IDIV reg or mem. Thi s i nstructi on al l ows to di vi de a 32-bi t si gned number by a 16-bi t
si gned number or to di vi de a 16-bi t si gned number by an 8-bi t si gned number. The 32-bi t
di vi dend i s hel d i n DA : AX regi sters. The 16-bi t di vi sor i s hel d i n a 16-bi t regi ster or two
consecuti ve memory l ocati ons. The 16-bi t quoti ent i s stored i n AX regi ster and the 16-bi t
remai nder i s stored i n DX regi ster. I f the di vi dend i s of 16-bi t, i t i s hel d i n AX regi ster. The
8-bi t di vi sor i s hel d i n an 8-bi t regi ster or a memory l ocati on. The 8-bi t quoti ent i s stored i n
AL regi ster and the 8-bi t remai nder i s stored i n AH regi ster. The exampl es are:
(i) I DI V CL
(ii) I DI V CX
(iii) I DI V BYTE PTR [BX]
(iv) I DI V WORD PTR [BX]
5.13.10 Addressing Modes of Intel 8086
I ntel 8086 i s provi ded wi th a total of 8 addressi ng modes. Two addressi ng modes are
provi ded for i nstructi ons whi ch operate on the content of a regi ster or i mmedi ate operands.
These two addressi ng modes are:
Register Addressing. I n thi s mode of addressi ng the operand i s pl aced i n one of the
8 or 16-bi t general -purpose regi sters. Exampl es are:
(i) MOV AX, BX ; Move the content of BX regi ster to AX regi ster.
(ii) ADD AL, CH ; ADD the content of CH regi ster to the content of
AL regi ster.
(iii) ADD CX, DX ; Add the content of DX regi ster to the content of
CX regi ster.
Immediate Addressing. I n thi s mode of addressi ng the operand i s gi ven i n the i nstruc-
ti on i tsel f. Exampl es are:
(i) MOV AL, 64H ; Move 64H to AL regi ster.
(ii) MOV BX, 0493H ; Move 0493H to BX regi ster.
(iii) MOV [offset address], data ; Thi s i nstructi on wi l l move 92H to the memory
or MOV [0300], 7892H l ocati on 0300H and 78 to the memory l ocati on
0301H.
(iv) ADD AX, 0286H ; Add 0286H to the content of AX regi ster.
The remai ni ng 6 addressi ng modes are for speci fyi ng l ocati on of an operand i n the
memory. To understand these addressi ng modes see the defi ni ti ons of di spl acement, base,
i ndex and offset i n the Secti on 5.4.5. These addressi ng modes are as fol l ows:
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Direct Addressing. I n thi s mode of addressi ng the operands offset or effecti ve address
i s gi ven i n the i nstructi on i tsel f. Exampl es are:
MOV AL, [0400H] ; Move the content of the effecti ve address 0400H to AL regi ster.
MOV [0301 H], AX ; Move the content of AL to 03101H and the content of AH to 0302H.
Register Indirect Addressing. The operands offset i s i n one of the regi sters: BX, BP,
SI or DI . Exampl es are:
ADD AX, [BX] ; Add the contents of memory l ocati ons addressed by BX regi ster to the
contents of AX regi ster.
Suppose, the BX regi ster contai ns 0401H. The content of 0401H i s 95H and the content
of the next memory l ocati on 0402H i s 63H. Now 6395H wi l l be pl aced i n AX.
Based Addressing. I n thi s mode of addressi ng the operands offset (or effecti ve address)
i s the sum of the contents of the base regi ster (BX or BP) and an 8-bi t or 16-bi t di spl acement.
Offset (or Effecti ve address) = [BX + 8-bi t or 16-bi t di spl acement]. Exampl es are:
(i) ADD AL, [BX+05]; I t i s a case of an 8-bi t di spl acement. Suppose, BX regi ster contai ns
0401H. Hence, the effecti ve address (or offset) i s 0401+5 = 0406H. The content of
0406H wi l l be added to the content of AL, and the resul t wi l l be pl aced i n AL.
(ii) ADD AL, [BX+1045H]; I t i s a case of 16-bi t di spl acement.
Indexed Addressing. I n thi s mode of addressi ng the operands offset (or effecti ve
address) i s the sum of an 8-bi t or 16-bi t di spl acement and the contents of an i ndex regi ster
SI or DI .
Offset = [SI or DI + 8-bi t or 16-bi t di spl acement]
Exampl es are:
(i) ADD AX, [SI + 05]
(ii) MOV AX, [SI + 1239H]
Based Indexed Addressing. The operands offset (or Effecti ve Address) i s the sum of
the contents of a base regi ster and an i ndex regi ster.
Offset (or Effecti ve Address) = [BX or BP] + [SI or DI ]
Exampl es are:
(i) MOV AX, [BX+SI ]
(ii) ADD CX, [BX+SI ]
Based Indexed with Displacement. I n thi s mode of addressi ng the operands offset
(or effecti ve address) i s determi ned by addi ng a base regi sters contents, an i ndex regi sters
contents and an 8-bi t or 16-bi t di spl acement.
Offset (or Effecti ve Address] = [BX or BP] + [SI or DI ] + Di spl acement. Exampl es are:
(i) MOV AX, [BX + SI + 05H]
(ii) ADD AX, [BX + SI + 1085H]
5.14 BRIEF DESCRIPTION OF INTEL MICROPROCESSORS
We have al ready descri bed I ntel 8085 and I ntel 8086 mi croprocessors i n detai l as thei r
knowl edge i s necessary to understand the basi c pri nci pl es of computer technol ogy. I n thi s
5.36 COMPUTER FUNDAMENTALS
secti on we want to di scuss some mi croprocessors whi ch were popul ar i n the past. The
mi croprocessors whi ch are popul ar now wi l l be descri bed i n the subsequent secti ons. Though
the 486, Penti um and Pentium Pro are not used today, they wi l l be di scussed i n the subse-
quent secti ons i n detai l as they gi ve the background to understand current I ntel mi cropro-
cessors. The l atest I ntel s mi croprocessors are Penti um 4 and I tani um whi ch wi l l be descri bed
i n the subsequent secti ons.
5.14.1 Intel 8088
Shortl y after the i ntroducti on of 8086 (year 1978), I ntel i ntroduced the 8088 i n the year
1980. The 8088 had exactl y the same i nstructi on set and i nternal archi tecture as those of
I ntel 8086. The mai n di fference between the two processors was the wi dth of thei r external
data buses; the 8086 had 16-bi t data bus; on the other hand the 8088 had onl y 8-bi t wi de data
bus. I t contai ned 16-bi t regi sters and 16-bi t i nternal data path. I ts address bus was 20-bi t wi de.
I ts computi ng power was of a 16-bi t mi croprocessor because i ts i nternal archi tecture was of
a 16-bi t mi croprocessor. As i t had 8-bi t wi de data bus, i t used 8-bi t i nput/output devi ces whi ch
were cheaper than 16-bi t i nput/output devi ces. Personal computers bui l t around I ntel 8088
mi croprocessor were cheaper than personal computers bui l t around I ntel 80286. Low-cost
personal computer PC/XT usi ng 8088 as CPU were very popul ar and wi del y used i n 1980s.
PC stands for personal computer and XT for extended technol ogy. I t coul d be i nterfaced wi th
8087 math coprocessor for fast mathemati cal computati on.
5.14.2 Intel 80286
The 80286 i ntroduced i n 1982, was an enhanced versi on of I ntel 8086. I t was desi gned
wi th mul ti user and mul ti taski ng capabi l i ty. I t contai ned i ntegrated memory management
system, four-l evel memory protecti on and supports for vi rtual memory and operati ng system.
I t coul d di rectl y address up to 16 MB memory. I t coul d manage up to 1 GB of vi rtual memory.
I t contai ned an el ectroni c ci rcui try of 1,30,000 transi stors. I t coul d be i nterfaced wi th I ntel
80287 math coprocessor for fast mathemati cal computati on. Personal computers, PC/AT, bui l t
around 80286 were very popul ar and wi del y used i n 1980s. They were costl i er than PC/XT
whi ch was bui l t around 8088. AT stands for advanced technol ogy. They used 16-bi t i nput/
output devi ces.
5.14.3 Intel 80186 and Intel 80188
Intel 80186. I t i s hi ghl y i ntegrated 16-bi t mi croprocessor. Besi des CPU, i t al so contai ns
a number of commonl y used computer components on a si ngl e chi p. I t contai ns an 8086-2
CPU (an enhanced versi on of 8086), a programmabl e i nterrupt control l er, two i ndependent
DMA channel s, three programmabl e 16-bi t ti mers/counters, a cl ock generator, programmabl e
memory and peri pheral chi p-sel ect l ogi c, programmabl e wai t-state generator, l ocal bus con-
trol l er, etc. I ts i mproved versi ons are 80C186, 80C186EB, etc. I t can be i nterfaced wi th 8087
math coprocessor for fast mathemati cal computati on. The ai m behi nd the devel opment of
80186 was to make i t possi bl e to bui l d a computer wi th smal l er number of I Cs compared to
an equi val ent 8086-based computer. Thi s made 80186 an attracti ve mi croprocessor for embed-
ded control appl i cati ons such as test i nstruments, i ndustri al robots, tel ephone swi tchi ng
systems etc. I t di d not become popul ar for general -purpose mi crocomputers.
Intel 80188. I t i s a hi ghl y i ntegrated mi croprocessor wi th 8-bi t wi de data bus and 16-bi t
i nternal archi tecture. I t contai ns 8088-2 CPU (an enhanced versi on of 8088), a programmabl e
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i nterrupt control l er, two i ndependent hi gh speed DMA channel s, three programmabl e 16-bi t
ti mers/counters, a cl ock generator, programmabl e memory and peri pheral chi p-sel ect l ogi c,
programmabl e wai t-state l ogi c, l ocal bus control l er, etc. I ts i mproved versi on are : 80C188,
80C188EB etc. These processors are sui tabl e for l ow-cost embedded control appl i cati ons. They
di d not become popul ar for l ow-cost general -purpose mi crocomputers. I t can be i nterfaced to
8087 math coprocessor for fast mathemati cal computati on.
5.14.4 Intel 80386
I n short, the I ntel 80386 i s wri tten as I ntel 386. I t was I ntel s popul ar 32-bi t mi cropro-
cessor. I t was i ntroduced i n 1985 and wi del y used i n 32-bi t general -purpose computer before
the i ntroducti on of 486 mi croprocessor. The 386DX versi on had 32-bi t address bus and 32-bi t
data bus. I t coul d di rectl y address up to 4 GB of physi cal (real ) memory. I ts memory man-
agement uni t (MMU) coul d manage up to 64TB of vi rtual memory. I t contai ned an el ectroni c
ci rcui try of 2,75,000 transi stors. I ts general -purpose regi sters and ALU were of 32-bi ts. I t
contai ned MMU and protecti on mechani sm on the processor chi p i tsel f.
The 386SL versi on was devel oped i n 1990 for l aptop (notebook) computers. I t contai ned
a 32-bi t CPU, memory control l er, cache control l er, power management uni t etc on the chi p
i tsel f. I t had onl y 24-bi t address bus and 16-bi t data bus. I ts i nternal archi tecture was of 32
bi ts. I t was desi gned to consume l ess power. An I /O subsystem 82360SL was devel oped to
bui l d a personal computer wi th 386SL mi croprocessor. The 82360SL contai ned two 8237 DMA
control l ers, two 8259 i nterrupt control l ers, two 8254 programmabl e ti mer/counters, two 16450
compati bl e seri al port control l ers, one 8-bi t paral l el port, I SA bus l ogi c, etc.
The 386SX versi on had 32-bi t i nternal archi tecture but onl y 24 address l i nes and 16 data
l i nes. I t was a 32-bi t entry-l evel processor. The computers bui l t around thi s CPU were
cheaper and l ess powerful compared to the computers bui l t around 386DX.
5.15 INTEL 486 (INTEL 80486)
The 486 (80486) i s an advanced hi gh performance 32-bi t CHMOS mi croprocessor. I t was
i ntroduced i n the year 1989. I t contai ns a 32-bi t CPU, a fl oati ng-poi nt coprocessor, 8 KB or
16 KB cache and a memory management uni t on the chi p. I ts CPU has al l the features of
386 mi croprocessor wi th enhancements to i mprove i ts speed and computi ng power. The 8KB
cache i s uni fi ed for both codes as wel l as data. The math coprocessor contai ned i n the 486
mi croprocessor i s same as 80387 math coprocessor, but i t i s i ntegrated on the 486 chi p i tsel f.
The 486 contai ns a ci rcui try of 1.2 mi l l i on transi stors. I t i s CI SC processor. I t i s hi ghl y
pi pel i ned. I t executes frequentl y used i nstructi ons i n one cl ock cycl e.
The avai l abl e versi ons of the 486 mi croprocessor are: 486SX, 486DX, 486DX2 and 486DX4.
The 486SX operates at 25 MHz, the 486DX at 33 MHz, the 486DX2 at 66 MHz and 486DX4
at 100 Mz. The 486DX4 contai ns 16KB cache whereas other versi ons contai n onl y 8KB cache.
The 486SX versi on doesnt contai n math coprocessor on the chi p. The math coprocessor I ntel
487SX i s an opti onal . Al l other versi ons of 486 mi croprocessor contai n math coprocessor on
the chi p. Al l other features are same for the 486SX and other versi ons of 486 mi croprocessor.
The 486SX i s packed i n a 168-pi n gri d array or 196-l ead pl asti c quad fl at package. The 486DX
i s packed i n a 168-pi n (17 17) gri d array package. I ts computi ng power i s 54 and 80 MI PS
at 66 MHz and 100 MHz respecti vel y. Correspondi ng data transfer rates are 212 and 320 MB/
sec respecti vel y.
5.38 COMPUTER FUNDAMENTALS
The 486 operates in two modes: real and virtual (or protected) modes. I n real mode its
memory addressing capacity is 1 MB. I n this mode paging is not allowed. 8086 application
programs are run in this mode. The primary aim of the real mode is to set up the 486 microprocessor
in the protected mode. I n the protected mode memory management and protection facilities are
available. The 486 can directly address 4 GB of memory. The memory management unit can
manage 64TB virtual memory per task. I n the protected mode virtual 8086 environment is
available. I n virtual 8086 environment 8086 programs are run with protection. Paging facility is
also available. Memory addressing capacity is 1 MB. The 486 microprocessor can run 8086
programs and 486 programs simultaneously in the protected mode of operation.
5.15.1 Functional Unit of Intel 486
The I ntel 486 contai ns the fol l owi ng functi onal uni ts:
(i) Bus i nterface uni t
(ii) Code prefetch uni t
(iii) I nstructi on decodi ng uni t
(iv) Control and protecti on test uni t
(v) Executi on uni t
(vi) Fl oati ng-poi nt coprocessor
(vii) Segmentati on uni t
(viii) Pagi ng uni t
(ix) Cache uni t
Fi g. 5.13A and Fi g. 5.13B show the bl ock di agram of I ntel 486. The bus i nterface uni t
connects I /O devi ces and memory chi ps to the 486 mi croprocessor. On the recei pt of request
from the code prefetch uni t for fetchi ng i nstructi ons and transferri ng data, the processor
generates address and control si gnal s for current bus cycl es.
The bus i nterface uni t gi ves hi gher pri ori ty to data transfer over i nstructi on fetchi ng.
The code prefetch uni t fetches i nstructi on code from cache memory and stores them i n a 32-
byte code queue. The i nstructi on decodi ng uni t gets i nstructi on codes from 32-byte code
queue and decodes them. The decoded i nstructi ons are fi rst sent to the control and protecti on
test uni t. Before the executi on of an i nstructi on, protecti on test i s performed. The protecti on
test uni t checks segment vi ol ati ons. To execute an i nstructi on the 486 mi croprocessor ex-
ecutes a sequence of mi croi nstructi ons cal l ed mi croprogram. The bi nary code for a mi croi n-
structi on i s cal l ed mi crocode. The control ROM (shown i n Fi g. 5.13A) stores mi crocodes. The
executi on uni t executes mi crocodes correspondi ng to an i nstructi on. I t contai ns an ALU,
regi ster fi l e and barrel shi fter. The barrel shi fter i s a speci al type of shi ft regi ster whi ch can
perform mul ti pl e number of shi fts i n a si ngl e operati on.
The segmentati on uni t cal cul ates the l i near address from the l ogi cal address. I t al so
provi des four-l evel of protecti on for i sol ati ng and protecti ng tasks and the operati ng system
from each other. The pagi ng uni t provi des pagi ng faci l i ty wi thi n a segment. I t transl ates l i near
address i nto physi cal address. The memory management uni t consi sts of segmentati on uni t and
pagi ng uni t. The 8 KB or 16 KB cache memory i s a uni fi ed cache for code as wel l as data.
5.15.2 Register Organization of Intel 486
The basi c regi ster set of I ntel 486 mi croprocessor i s shown i n Fi g. 5.14. I t contai ns ei ght
32-bi t general purpose regi sters: EAX, EBX, ECX, EDX, ESI , EDI , EBP and ESP. The l ow-
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5.40 COMPUTER FUNDAMENTALS
order 16-bi ts of general purpose regi ster are used for 16-bi t operati on. They can be accessed
separatel y. The names of the l ow-order 16-bi t regi sters are: AX, BX, CX, DX, SI , DI , BP and
SP. Further, AL, BL, CL, DL, AH, BH, CH and DH can be accessed separatel y for 8-bi t
operati on.
There are si x 16-bi t segment regi sters i n the 486 mi croprocessor. They are: CS, DS, SS,
ES, FS and GS. DS, ES, FS and GS are data segment regi sters. These data segment regi sters
have been provi ded to access four di fferent data areas i n the memory to permi t programs to
get di fferent types of data structures. The i nstructi on poi nter EI P i s a 32-bi t regi ster. I t acts
as a program counter. I t hol ds the effecti ve address (offset) of the next i nstructi on to be
executed. The offset i s al ways rel ati ve to the starti ng address of the code segment, whi ch i s
contai ned i n CS. The 486 contai ns a 32-bi t EFLAGS. Fi g. 5.15 shows the status fl ags of I ntel
486 mi croprocessor. I t contai ns 14 fl ags. Out of 14 fl ags si x fl ags are condi ti onal fl ags and
remai ni ng fl ags are control and system fl ags. Si x condi ti on fl ags are: carry fl ag (CF), pari ty
fl ag (PF), auxi l i ary fl ag (AF), zero fl ag (ZF), si gn fl ag (SF) and overfl ow fl ag (OF). The control
and system fl ags are: di recti on fl ag (DF), i nterrupt fl ag (I F), trap or trace fl ag (TF), vi rtual
8086 mode fl ag (VM), al i gnment check fl ag (ACF), resume or restart fl ag (RF), nested task
fl ag (NTF) and i nput/output pri vi l ege-l evel fl ag (I OPL). The l ow-order 16-bi ts of EFLAGS are
used for 16-bi t operati on. They are useful for executi ng 8086 and 80286 i nstructi ons. The fl ag
regi ster for 16-bi t operati on i s cal l ed FLAGS.
Fig. 5.13B Si mpl i fi ed Bl ock Di agram of I ntel 486.
Other regi sters of I ntel 486 are: three control regi sters - CR1, CR2 and CR3 (CR1 i s
reserved for future I ntel mi croprocessors); four system address regi sters - GDTR (gl obal
descri ptor tabl e regi ster), I DTR (i nterrupt descri ptor tabl e regi ster), LDTR (l ocal descri ptor
tabl e regi ster) and TR (task state segment); seven debug regi sters - DR0-DR7 (DR4 and DR5
reserved for future mi croprocessors); fi ve test regi sters, fl oati ng-poi nt regi sters and segment
descri ptor cache regi sters. A segment descri ptor cache regi ster i s associ ated wi th each seg-
ment regi ster. I t hol ds 32-bi t base address for the segment, 32-bi t segment l i mi t and other
necessary segment attri butes. Segment descri ptor cache regi ster are i nvi si bl e (not accessi bl e)
to users whereas segment regi sters are vi si bl e to users.
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Fig. 5.14 Basi c Regi ster Set of I ntel 486.
5.42 COMPUTER FUNDAMENTALS
Fig. 5.15 Status fl ags of I ntel 486.
5.15.3 Addressing Modes of Intel 486
The 486 mi croprocessor has 11 addressi ng modes. Two addressi ng modes are to speci fy
regi ster or i mmedi ate operand. They are as fol l ows:
Register Addressing. The operand i s contai ned i n one of the 8, 16 or 32-bi t general
purpose regi sters.
Immediate addressing. The operand i s i ncl uded i n the i nstructi on i tsel f. I t i s a part
of an i nstructi on.
The remai ni ng 9 addressi ng modes are used to access memory. They speci fy the l ocati on
of an operand i n the memory. The linear address i s the sum of the starti ng address (base
address) of the segment and the operands offset (effecti ve address) wi thi n the segment. The
fol l owi ng four address el ements are used to determi ne operands offset.
Displacement. I t i s an 8, 16, or 32-bi t i mmedi ate data fol l owi ng the i nstructi on.
Base. The contents of any general purpose regi ster can be used as a base address to
determi ne an offset. I n other words any general purpose regi ster can be used as a base
r egi ster.
Index. The contents of any general purpose regi ster except ESP can be used as i ndex.
The i ndex regi sters are general l y used to contai n i ndex. The i ndex i s used to access the
el ements of an array or a stri ng of characters. I n other words any general purpose regi ster
except ESP can be used as an i ndex regi ster.
Scale. The contents of an i ndex regi ster can be mul ti pl i ed by a scal e factor such as 1,
2, 4 or 8. For accessi ng arrays or structures the scal ed i ndex addressi ng i s very useful .
The effecti ve address i s an offset wi thi n the segment wi th respect to the starti ng address
(base address) of the segment.
The effecti ve address or offset i s computed as fol l ows:
Effective Address or Offset = [Base reg.] + [I ndex Reg. Scal i ng] + Di spl acement.
The remai ni ng 9 addressi ng modes are as fol l ows:
Direct Addressing Mode. The operands offset i s contai ned i n the i nstructi on i tsel f as
an 8-, 16- or 32-bi t di spl acement.
Register Indirect Addressing Mode. I n thi s mode of addressi ng any general purpose
regi ster can be used to hol d the effecti ve address (offset) of the operand.
Based Addressing Mode. The operands offset i s determi ned by addi ng di spl acement
to the contents of a base regi ster.
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Index Addressing Mode. The operands offset i s determi ned by addi ng di spl acement to
the contents of an i ndex regi ster.
Scaled Index Addessing Mode. The contents of an i ndex regi ster i s mul ti pl i ed by a
scal e factor such as 1, 2, 4 or 8, and the resul t i s added to a di spl acement to determi ne
operands offset.
Based Index Addressing Mode. The contents of an i ndex regi ster i s added to the
contents of a base regi ster to obtai n operands offset.
Based Scaled Index Addressing Mode. To get the operands offset the contents of an index
register is multiplied by a scale factor and the result is added to the contents of a base register.
Based Index Addressing with Displacement. I n thi s addressi ng mode three address
el ements: the contents of an i ndex regi ster, the contents of a base regi ster and a di spl acement
are added to form operands offset.
Based Scaled Index Addressing with Displacement. The contents of an i ndex regi ster
i s mul ti pl i ed by a scal e factor and the resul t i s added to the contents of a base regi ster and
a di spl acement to form operands offset.
5.15.4 Memory Organization of Intel 486
The 486 handl es a byte, a word and a doubl e word. The memory i s parti ti oned i n bytes.
A word (16-bi t quanti ty) i s stored i n two consecuti ve bytes. A dword (doubl e word, a 32-bi t
quanti ty) i s stored i n 4 consecuti ve bytes. The address of word or doubl e word i s the address
of i ts l ow order byte. Memory for I ntel 486 can be organi zed i nto segments. I n real mode the
segment i s of fi xed si ze of 64 KB. I n protected mode the segment si ze i s of vari abl e l ength
(1 byte to 4 GB). The memory can al so be organi zed i nto 4 KB pages. The segmentati on and
pagi ng can be combi ned to get the advantages of both techni ques.
The address gi ven i n a program i s known as logical address. The memory (RAM and
ROM) actual l y present i n a computer system i s cal l ed physical memory or real memory.
The segmentati on uni t transl ates l ogi cal address i nto 32-bi t linear address. The l i near address
i s the sum of the starti ng address (base address) of the segment and the operands offset
(effecti ve address) wi thi n the segment. The pagi ng uni t transl ates l i near address i nto physi cal
address. I n real mode pagi ng i s not provi ded and therefore, the physi cal address are same as
the l i near address. The memory i s addressed by a poi nter consi sti ng of a 16-bi t sel ector and
a 32-bi t offset. I n other words l ogi cal address consi sts of a 16-bi t sel ector and a 32-bi t offset. The
selector is contained in a segment register. The offset is obtained by combining address components
base, i ndex and di spl acement. Thi s combi nati on depends on the types of addressi ng modes.
The 16-bi t sel ector and 32-bi t offset are empl oyed for memory addressi ng i n both real and
protected modes. I n real mode the segmentati on uni t shi fts sel ector (the contents of a
segment regi ster) by 4-bi ts l eft and adds 16-bi t offset to the resul t to get 20-bi t l i near address.
I n protected mode, the contents of a segment regi ster does not gi ve the base address of the
segment di rectl y. Rather i t poi nts to a descri ptor stored i n a tabl e i n the memory cal l ed
descriptor table (l ocal descri ptor tabl e, LDT or gl obal descri ptor tabl e, GDT) whi ch gi ves
a 32-bi t base address and other i nformati on about the segment.
I n real mode of operati on onl y 20 address l i nes are used for memory addressi ng. Usi ng
20 address l i nes, 2
20
bytes = 1 MB memory can be addressed. I n protected mode 32 address
l i nes are used for memory address. Usi ng 32 address l i nes, 2
32
bytes = 4 GB memory can
be addressed. The maxi mum capaci ty of physi cal memory of a 486-based system may be 4 GB.
Thi s capaci ty i s used i n the protected mode of operati on.
5.44 COMPUTER FUNDAMENTALS
A memory model i n whi ch segmentati on i s el i mi nated and the enti re memory space i s
used i n a si ngl e bl ock, i s cal l ed flat memory model.
Memory Management Unit (MMU) and Protection. I n a mul ti user/mul ti taski ng
system tasks must be i sol ated from each other and operati ng system to avoi d i nterference.
Each user i s assi gned speci fi c memory area for hi s use. The user i s not al l owed to wri te (or
read) i nto (or from) memory area assi gned to other users and the operati ng system. Thi s
feature i s cal l ed protecti on. I t i s provi ded by MMU. I n addi ti on to protecti on MMU al so
computes l i near address from the l ogi cal address and physi cal address from the l i near ad-
dress. The 486 mi croprocessor contai ns a hardware mechani sm wi thi n the chi p i tsel f to
provi de protecti on and address transl ati on. Thi s hardware uni t i s cal l ed MMU. The MMU
consi sts of memory segmentati on uni t and the pagi ng uni t. The segmentati on uni t provi des
4 l evel s of protecti on. The protecti on i s avai l abl e onl y i n the protected mode, not i n the real
mode.
Swapping and Virtual Memory. The MMU can provi de more memory space than the
actual exi sti ng physi cal memory to a program by swappi ng techni que. When a program
requi res very l arge memory si ze, a part of the program currentl y needed for executi on i s
brought i nto the memory from the hard di sk. Si mi l arl y, the part of the program whi ch i s not
requi red i s pushed back i nto the hard di sk. Thi s to and fro movements of the parts of a
program between the mai n (physi cal ) memory and the secondary memory (hard di sk) i s cal l ed
swapping. By thi s techni que 64TB (tera bytes) memory space can be provi ded by the MMU
of the a 486 mi croprocessor. The 64TB memory space i s the vi rtual memory space of a 486
based system. The maxi mum memory space whi ch can be provi ded by MMU of a system i s
called virtual memory.
5.15.5 Interrupt and Exception of Intel 486
The i nterrupti on of normal program executi on of a mi croprocessor caused by external
events i s cal l ed interrupt. When an I /O devi ce wants to transfer data, i t i nforms mi cropro-
cessor by sendi ng a si gnal to the mi croprocessor. Thus the mi croprocessor i s i nterrupted by
an external devi ce. The mi croprocessor can al so be i nterrupted by i nternal abnormal condi -
ti ons. An i nterrupt caused by an abnormal condi ti on i s cal l ed exception. Further, the mi cro-
processor can al so be i nterrupted by i nserti ng a speci al i nstructi on i n a program. Thi s type
of i nterrupti on i s cal l ed software interrupt. A software i nterrupt i s treated as an excepti on
by the mi croprocessor. The i nterrupti on caused by external devi ces i s al so cal l ed hardware
interrupt. After an i nterrupt/excepti on occurs, the mi croprocessor compl etes i ts current
i nstructi on at hand and then i t attends the i nterrupti ng devi ce or takes necessary steps i n
case of i nternal abnormal condi ti ons as speci fi ed by the system desi gner. For each i nterrupti ng
devi ce or abnormal condi ti on there i s a subrouti ne whi ch i s executed by the mi croprocessor
after the occurrence of an i nterrupt/excepti on. Thi s subrouti ne i s cal l ed interrupt service
subroutine (ISS). When an I /O devi ce i nterrupts mi croprocessor, the mi croprocessor executes
an I SS to transfer data or to perform any other task as desi red by the programmer. I n the
case of i nternal abnormal condi ti on (or software i nterrupt), the mi croprocessor executes an
I SS to perform the desi red operati on predetermi ned by the computer desi gner. I nterrupts are
al so used to perform si ngl e step-operati on and basi c I /O operati on (BI OS).
The 486 mi croprocessor has two i nterrupt l i nes: NMI and I NTR. NMI i s a nonmaskabl e
i nterrupt. I t i s not avai l abl e to users. I t i s used by the mi croprocessor for certai n speci fi c
operati on. I NTR i s a maskabl e i nterrupt. I t i s avai l abl e to user. A number of I /O devi ces can
be connected to the mi croprocessor through an i nterrupt control l er.
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I n a 486-based system an i denti fi cati on number i s assi gned to an i nterrupt/excepti on.
Thi s i denti fi cati on number i s cal l ed interrupt type or interrupt vector. A 486 system can
entertai n up to 256 i nterrupts/excepti ons. The i nterrupt control l er sends an 8-bi t vector to
the mi croprocessor i n response to i nterrupt acknowl edge si gnal . The 8-bi t vector i denti fi es
the i nterrupti ng I /O devi ce.
5.15.6 Pins and Signals of Intel 486
The 486 i s packaged i n a 168-pi n PGA (pi n gri d array) package. Fi g. 5.16 shows the pi n
di agram for I ntel 486. Fi g. 5.17 shows the si gnal s of 486. BE
0
# BE
3
#are byte enabl e si gnal s.
They are acti ve-l ow si gnal s. They i ndi cate whi ch data bytes are to be accessed duri ng read
and wri te operati on. PCHK#i ndi cates pari ty error. LOCK#i ndi cates that the current bus
cycl e i s l ocked. When 64-bi t or 128-bi t read/wri te operati on i s to be performed, PLOCK#
i ndi cate that the current bus transacti on requi res more than one bus cycl e for compl eti on.
AHOLD i s an address hol d request. I t al l ows another bus master to access the address bus
of the 486 to perform cache i nval i dati on. BS16#i s the bus si ze 16 si gnal . When i t i s asserted
16-bi t data are transferred per cycl e. I t i s asserted by an external devi ce whi ch cannot send
or accept 32-bi t data i n a si ngl e cycl e. BS8#i s bus si ze 8-si gnal . KEN#i s cache enabl e si gnal .
EADS#i s used i n cache i nval i dati on cycl e.
Fig. 5.16 Pi n package of I ntel 486.
5.46 COMPUTER FUNDAMENTALS
Fig. 5.17 Si gnal s of I ntel 486.
PWT control s the wri te operati on of the external cache memory. PCD control s on-chi p
cache memory. FERR#i ndi cates fl oati ng-poi nt error. For more detai l s see I ntel mi croproces-
sor hand book.
Before the i ntroducti on of Penti um processor, the 486 was wi del y used CPU for 32-bi t
general -purpose computers.
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5.16 PENTIUM PROCESSOR
The Penti um i s I ntel s 32-bi t superscal ar CI SC mi croprocessor. I t was i ntroduced i n 1993.
The term superscalar i s used for the processor whi ch contai ns mul ti pl e ALUs to execute
more than one i nstructi on si mul taneousl y i n paral l el per cl ock cycl e. The Penti um contai ns
two ALUs and can execute two i nstructi ons per cl ock cycl e. Besi des two ALUs, i t al so contai ns
one on-chi p FPU (Fl oati ng-Poi nt Uni t) and two 8 KB cache memory (one for i nstructi on and
the other for data). FPU i s a math processor whi ch can cal cul ate tri gonometri c, l ogari thmi c,
exponenti al etc and can hadl e fl oati ng-poi nt numbers. The Penti um has a 32-bi t address bus
and 64-bi t data bus. The data bus used i s of 64-bi t wi th a vi ew to suppl y data at faster rate
to meet the need of two ALUs. I ts operati ng cl ock frequency for i ts di fferent versi ons was 60
MHZ to 233 MHZ.
Fig. 5.18 Bl ock Di agram of Penti um Processor.
I t contai ned an el ectroni c ci rcui try of 3.3 mi l l i on transi stors and used 0.35 mi cron process
technol ogy. One micron i s equal to 10
6
metre. 0.35 mi cron process technol ogy means that
the di stance between two components (transi stors etc) i n the I C i s 0.35 mi cron. I t operates
at 3.3 Vd.c. I t uses 7 stage pi pel i ne. I t was wi del y used i n desktop computers before the
5.48 COMPUTER FUNDAMENTALS
devel opment of Penti um Pro and Penti um I I processors. Fi g 5.18 shows the bl ock di agrams
of Penti um processor. TLB i s transl ati on l ook-asi de buffer. I ts functi on i s to keep most
recentl y accessed pages. The functi on of control ROM i s to store mi cro-codes of i nstructi ons.
API C i s advanced programmabl e i nterrupt control l er. The Penti um processor i s provi ded wi th
branch predi cti on capabi l i ty to predi ct whi ch set of i nstructi ons i s to be executed next. The
pi pel i nes are kept ful l accordi ngl y.
5.17 PENTIUM MMX PROCESSOR
Penti um MMX processor i s Penti um processor wi th MMX technol ogy. MMX stands for
Mutl i -Medi a extensi on. Penti um wi th MMX technol ogy has been devel oped to handl e
mul ti medi a computer. A mul ti medi a computer accepts i nput i n the form of text, graphi cs,
i mages and sound. Si mi l arl y, i t produces output i n the form of text, graphi cs, i mages and
sound. The Penti um wi th MMX technol ogy contai ns one addi ti onal pi pel i ne to handl e
mul ti medi a. Thi s pi pel i ne i s cal l ed MMX pi pel i ne. The MMX pi pel i ne i s i n addi ti on to two
i nteger pi pel i nes and one fl oati ng-poi nt pi pel i ne. The MMX pi pel i ne uses i ntensi ve paral l el
processi ng of data so that i t can handl e graphi cs, vi deo, speech, i mage, etc. I t empl oys SI MD
(Si ngl e I nstructi on Mul ti pl e Data) technol ogy for fast data processi ng. Mul ti pl e data are
handl ed si mul taneousl y usi ng SI MD. I ntel s Penti um wi th MMX contai ns 4.5 mi l l i on transi stors,
has operati ng vol tage 3.3 V, operati ng frequency 200 MHz, two cache memory : 16 KB each,
one for i nstructi on and one for data, etc. The Cel eron, Penti um I I , Penti um I I I and Penti um
4 al so use MMX technol ogy. The Penti um wi th MMX was wi del y used before the i ntroducti on
of these processors.
5.18 PENTIUM PRO
The Penti um Pro, a 32-bi t CI SC processor, i ntroduced i n 1995, has data fl ow archi tec-
ture. The data fl ow archi tecture i s qui te di fferent than the archi tecture of I ntel s earl i er
mi croprocessors such as Penti um, Penti um wi th MMX, 486, 386, 8086, etc. The Penti um Pro
contai ns a second-l evel cache memory of 256 KB or 512 KB i n addi ti on to the fi rst-l evel two
caches (8 KB each, one for i nstructi on and one for data). I t al so contai ns a cache control l er
and an advanced programmabl e i nterrupt control l er. I ts fi rst-l evel i nstructi on cache i s wri te-
through cache. The fi rst-l evel data cache may be wri te-back or wri te-through. The Penti um
Pro i s provi ded wi th 36 address l i nes whi ch can di rectl y address up to 64 GB memory. I t i s
packed i n a 387-pi n PGA (Pi n Gri d Array) package. I t operates at 200 MHz and vol tage
3.3 V. I t contai ns 21 mi l l i on transi stors, i ncl udi ng L2 cache. I t was used before the i ntroducti on
of Penti um I I . I t uses 0.35 mi cron process technol ogy.
5.18.1 Data Flow and Von Neumann Architecture
The Penti um Pro uses data fl ow archi tecture whereas earl i er I ntel mi croprocessors used
Von Neumann archi tecture. In Von Neumann Architecture the CPU executes i nstructi ons
i n a sequenti al order. The program i s stored i n the memory. The CPU fetches one i nstructi on
from the memory, decodes i t and then gets data from the memory, i f any. After recei vi ng data
i t executes the i nstructi on. Then i t fetches the next i nstructi on from the memory for executi on.
Unl ess i t executes the i nstructi on at hand, i t does not fetch the next i nstructi on. Thus i t
executes i nstructi on i n a sequenti al order. I t uses a program counter to i mpl ement the sequenti al
order. The program counter poi nts to the address of the next i nstructi on to be executed.
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In data flow architecture, the processor (fetch and decode uni t of the processor)
fetches several i nstructi ons (say 2030 i nstructi ons) from the i nstructi on cache, decodes them
and keeps thei r mi crocodes i n an instruction pool. Then the processor (di spatch/execute
uni t of the processor) checks the fi rst i nstructi on of the i nstructi on pool , whether i ts necessary
data are avai l abl e for i ts executi on. Suppose, i ts data are not avai l abl e i n the data cache.
There i s a cache mi ss. Now the processor does not wai t for data and hence, i t does not waste
i ts preci ous ti me. Then i t checks the second i nstructi on. Suppose, i t requi res the resul t of
the fi rst i nstructi on for i ts executi on. Now, processor checks the thi rd i nstructi on whi ch can
be executed. The processor executes i t and then goes to the fourth i nstructi on whi ch can al so
be executed. The processor wi l l execute the fourth i nstructi on. I n thi s way the processor
checks up al l the i nstructi ons whi ch are i n the i nstructi on pool . Thus we see that the
processor executes onl y those i nstructi ons for whi ch data are avai l abl e. The i nstructi ons
whi ch are not executed due to non-avai l abi l i ty of data, are executed i n the next round of
checki ng of i nstructi ons i n the i nstructi on pool . When data becomes avai l abl e, the remai ni ng
i nstructi ons are executed. Thus i t i s seen that i n data fl ow archi tecture, the processor does not
wai t, when data are not avai l abl e i n data cache for some i nstructi ons. Thi s techni que i ncreases
the speed of the processor. Penti um Pro, Penti um I I and Penti um I I I are data fl ow processors.
5.18.2 Functional Units of Pentium Pro
Fi g 5.19 shows the functi onal uni ts of Penti um Pro. The fetch and decode uni t recei ves
i nstructi ons from the i nstructi on cache and decodes them. I t sends mi cro-opcodes of the
decoded i nstructi ons to the i nstructi on pool . The i nstructi on pool i s a content addressabl e
memory (i.e., associ ati ve memory). The di spatch uni t checks the status of mi cro-opcodes
whi ch are i n the i nstructi on pool . I t sel ects and recei ves those mi cro-opcodes of the i nstruc-
ti ons from the i nstructi on pool , whi ch can be executed. The di spatch uni t sends executabl e
mi cro-opcodes to the executi on uni t. The executi on uni t contai ns two i nteger uni ts (ALU) and
one FPU (fl oati ng-poi nt uni t). I t can process two i nteger i nstructi ons and one fl oati ng-poi nt
i nstructi on si mul taneousl y. After the executi on of an i nstructi on, i ts resul t i s kept i n the
i nstructi on pool temporari l y for processi ng. The di spatch and execute uni t sel ects and ex-
ecutes i nstructi ons i n an out of order fashion, not i n the sequenti al order. The reti re uni t
checks the status of the mi cro-opcodes of the i nstructi ons i n the i nstructi on pool . I t l ooks for
the mi cro-opcodes that have been executed and can be removed from the i nstructi on pool . I t
does not onl y remove executed i nstructi ons but al so gi ves fi nal resul t i n the same order i n
whi ch the i nstructi ons were wri tten ori gi nal l y by the programmer. The reti re uni t can
remove three executed i nstructi ons per cl ock cycl e. Fi g. 5.20 shows the i nterface of Penti um
Pro to the system bus.
Fig. 5.19 Functi onal Uni ts of Penti um Pro.
5.50 COMPUTER FUNDAMENTALS
Fig. 5.20 I nterfaci ng of Penti um Pro to System Bus.
5.19 PENTIUM II AND PENTIUM II XEON
The Penti um I I processor i s a mul ti medi a 32-bi t CI SC processor. I t was i ntroduced i n the
year 1997. I t i s bui l t around Penti um Pro archi tecture. I t i ncl udes on-chi p MMX pi pel i ne to
i mpl ement MMX technol ogy. The MMX technol ogy enabl es the processor to add mul ti medi a
feature. The Penti um I I has 57 MMX i nstructi ons. I t contai ns two fi rst-l evel on-chi p cache
memory 16 KB each, one for i nstructi ons and the other for data. I t operates at 3.3 V and uses
0.25 mi cron process technol ogy. I ts cl ock frequency for i ts di fferent versi ons are i n the range
of 233 MHz700 MHz. I t contai ns 7.5 mi l l i on transi stors (Excl udi ng L2 cache). The second-
l evel cache memory i s of 512 KB. I t i s not an on-chi p cache. I t i s a separate I C. Both I Cs i.e.,
processor I C and second-l evel cache I C are packed i n a si ngl e package. Penti um I I was wi del y
used i n desktop computers before the i ntroducti on of Penti um I I I processor.
Pentium II Xeon processor i s a versi on Penti um I I havi ng a l arger second-l evel cache
memory of 1 MB or 2 MB. I t i s sui tabl e for workstati ons and servers.
Mobile Pentium II processor for portabl e computers was al so devel oped.
5.20 CELERON PROCESSOR
The Cel eron i s a l ow-cost superscal ar CI SC 32-bi t processor. I t was i ntroduced i n the year
1999 by I ntel Corporati on. I t i s bui l t around Penti um Pro archi tecture. I t contai ns one
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addi ti onal pi pel i ne to i mpl ement MMX technol ogy, whi ch enabl es the processor to handl e
mul ti medi a. I t contai ns two fi rst-l evel on-chi p cache memory, 16 KB each (one for i nstructi ons
and the other for data). I t al so contai ns an on-chi p 128 KB second-l evel cache memory. I ts
cl ock frequency for i ts di fferent versi ons was gradual l y i ncreased from 266 MHz to 2.60
GHz. Earl i er, i t was bui l t around Penti um I I core. Later on, when Penti um I I I was devel oped,
i ts new versi ons were bui l t around Penti um I I I core. The new versi ons used 0.18 mi cron
process technol ogy. They used I nternet streami ng SI MD i nstructi ons whi ch are to enhance
mul ti medi a performance on the I nternet such as advanced i magi ng, streami ng audi o and
vi deo, 3-D si mul ati ons, ani mati on, speech recogni ti on etc. The Cel eron uses 810E, 810E2,
815EP, 815E, 845GL, 845GV etc chi psets to i nterface peri pheral s. The system bus frequenci es
are 100 MHZ and 400 MHZ. The Cel eron processor i s used i n cheaper desktop computers.
The recent versi on of Cel eron i s cal l ed Celeron D. I t uses 90 nm process technol ogy and
has the second-l evel cache of 256 KB capaci ty. I t runs on 533 MHZ bus frequency. I ts some
model s are avai l abl e for the LGA 775 sockets. LGA stands for Land Gri d Array. The LGA
type of socket i s found on motherboards supporti ng I ntel s new chi psets i.e., the 915 and
925.
5.21 PENTIUM III PROCESSOR
The Penti um I I I processor i s I ntel s 32-bi t superscal ar CI SC processor. I t was i ntroduced
i n the year 1999. I t i ncl udes on-chi p MMX pi pel i ne to have mul ti medi a features. I t al so
i ncl udes 70 addi ti onal i nstructi ons to enhance mul ti medi a performance on I nternet. These
i nstructi ons are cal l ed I nternet Streami ng SI MD (Si ngl e I nstructi on Mul ti pl e Data) I nstruc-
ti ons. These i nstructi ons are known as I nternet SSE (I nternet Streami ng SI MD extensi ons).
These i nstructi ons enhance mul ti medi a performance on I nternet such as streami ng audi o and
vi deo, ani mati on, 3-D si mul ati on, advanced i magi ng, speech recogni ti on etc.
The Penti um I I I empl oys data fl ow archi tecture of Penti um Pro processor. I t contai ns
36 address l i nes and 64 data l i nes. Usi ng 36 address l i nes i t can address up to 64 GB
memory. The 64 data l i nes are used to suppl y data at very fast rate to meet the need of
two ALUs, one FPU, MMX pi pel i ne etc. The Penti um I I I contai ns about 40 mi l l i on transi stors
and uses 0.18 mi cron process technol ogy. I t operates at 3.3 vol ts. I t contai ns two on-chi p
fi rst-l evel cache memory, 16 KB each (one for i nstructi ons and the other for data). I t al so
contai ns on-chi p 256 KB or 512 KB second-l evel cache memory. The chi psets desi gned for
Penti um I I I are 810, 815 and 820. Exampl es of some versi ons of Penti um I I I are: Coppermi ne,
Katmai etc. The bl ock di agram of Penti um I I I processor i s same as those shown i n Fi g. 5.19
and Fi g. 5.20. I t was wi del y used i n desktop computers before the i ntroducti on of Penti um
4. The cl ock frequency for i ts di fferent versi ons was gradual l y i ncreased from 650 MHZ to
1.2 GHz.
Mobi l e versi on of Penti um I I I was al so devel oped. The operati ng vol tages for mobi l e
versi ons were: 0.975 V, 1.10 V and 1.70 V. The power consumpti on of mobi l e Penti um I I I was
1/2 watt to 1 watt. I t used 0.13 mi cron process technol ogy. Tual ati n named Penti um I I I mobi l e
was al so avai l abl e for notebook computers. The mobi l e versi on of Penti um I I I i s wri tten as
Pentium III M. M stands for mobi l e. Penti um M i s for notebook computers.
Pentium III Xeon uses l arger si ze of second-l evel cache memory of 1 MB or 2 MB. I t
i s sui tabl e for workstati ons and servers.
5.52 COMPUTER FUNDAMENTALS
5.22 PENTIUM 4 PROCESSOR
The Penti um 4 processors are avai l abl e i n 32-bi t as wel l as 64-bi t versi ons.
5.22.1 32-bit Pentium 4
The Penti um 4 i s I ntel s 32-bi t superscal ar CI SC processor. I t was i ntroduced i n the year
2000. I t i s an i mproved versi on of Penti um I I I processor. I t has 144 I nternet Streami ng SI MD
I nstructi ons, whereas the Penti um I I I contai ns onl y 70 such i nstructi ons. These i nstructi ons
are cal l ed I nternet SSE2 (Streami ng SI MD Extensi on 2) I nstructi ons. These i nstructi ons
enhance mul ti medi a performance on I nternet such as streami ng vi deo and audi o, ani mati on,
3-D si mul ati ons, advanced i magi ng, speech recogni ti on, etc.
The 32-bi t Penti um 4 empl oys data fl ow archi tecture of Penti um Pro processor. I t con-
tai ns 36 address l i nes and 64 data l i nes. Usi ng 36 address l i nes i t can address up to 64 GB
memory. The 64 data l i nes are used to suppl y data at faster rate to meet the need to two
ALUs, one FPU, MMX pi pel i ne etc. The 32-bi t Penti um 4 contai ns 55 mi l l i on transi stors and
uses 0.13 mi cron process technol ogy. I t operates at 3.3 V. I t has 423 pi ns and uses PGA (Pi n
Grid Array) package. I t has two fi rst-l evel cache (one for i nstructi on and the other for data).
The capaci ty of the data cache i s 8 KB. The i nstructi on cache i s al so known as trace cache.
I ts capaci ty i s 12 KB. The i nstructi on cache i n 32-bi t Penti um 4 processor i s pl aced after the
fetch and decode uni t. The fetch and decode uni t fetches i nstructi ons from L2 (second-l evel )
cache. The trace cache (i nstructi on cache) recei ves decoded i nstructi ons i n mi cro-ops. Thi s
resul ts i n more effi ci ent use of cache storage space and hi gh vol ume of i nstructi on del i very
to the processors executi on uni t. On the other hand, the fetch and decode uni t of Penti um
I I I processor i s pl aced after the i nstructi on cache. Consequentl y, the fetch and decode uni t
fetches i nstructi ons from the i nstructi on cache. The Penti um 4 uses second-l evel cache
memory of 256 KB or 512 KB.
A 20-stage pi pel i ne i s used i n 32-bi t Penti um 4 processor whereas the Penti um I I I
processor empl oys a 10-stage pi pel i ne, and Penti um processor uses a 5-stage pi pel i ne. The
cl ock frequency for the di fferent versi ons of Penti um 4, was gradual l y i ncreased from 1.2 GHz
to 3.2 GHz. The system bus frequenci es avai l abl e are: 800 MHz, 500 MHz and 400 MHz. The
chi psets used are: 865P, 850, 850E, 845E, 845PE, 845G, 845GE and 845GV. RDRAM (Rambus
DRAM) i s used wi th Penti um 4 processor. I t i s very fast and i ts data transfer rate 1.6 GB per
second.
32-bit Pentium 4 Xeon processor uses a l arger second-l evel cache memory of 1 MB
4 MB capaci ty. I t i s sui tabl e for workstati ons and servers.
Pentium 4 Mobile. Mobi l e versi on of 32-bi t Penti um 4 processor i s al so avai l abl e. I t i s
used i n portabl e computers. The chi pset 845MP i s used wi th mobi l e 32-bi t Penti um 4
pr ocessor.
5.22.2 64-Bit Pentium 4
I ntel has al so devel oped 64-bi t Penti um 4 processors. They are 6XX seri es of Penti um
4 processors. Penti um 4 Exteme Edi ti on i.e., Penti um 4 EE i s al so a 64-bi t processor. I ts bus
frequency i s 1066 MHz. The bus frequency of 6XX seri es i s 800 MHz. The cl ock frequency
range for 64-bi t processors i s 3 GHz3.8 GHz. These processors have L2 cache of 2 MB
capaci ty. They use new motherboards usi ng 915 and 925 chi psets. The 6XX seri es i ncl udes
630, 640, 650 and 660 seri es of Penti um 4 processors.
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I ntel has al so devel oped dual core processor, Pentium Exteme Edition 840, Intel
Xeon Processor MP etc. Dual core processors have l ess heati ng probl em and are effi ci ent
i n mul ti taski ng. I n dual core processor two processors are bui l t on a si ngl e si l i con chi p. They
are packed i n a si ngl e I C uni t. I n future more than two processors wi l l be bui l t on a si ngl e
si l i con chi p. The two processors execute i nstructi ons i ndependentl y. The program i s spl i t i nto
two sequence of i nstructi ons. One sequence of i nstructi ons i s executed by one processor.
Penti um EE 840 has 2 MB of L2 cache and runs at 3.2 GHz. I t uses 955 chi pset.
Intel Xeon Processor MP i s a dual core processor. I t i s a 64-bi t processor sui tabl e for
l arger general -purpose upto mi d-si ze database computi ng tasks.
5.23 ITANIUM PROCESSOR
The I tani um i s I ntel s 64-bi t EPI C (Expl i ci tl y Paral l el I nstructi on Computi ng) processor.
I t was i ntroduced i n the year 2001. I t i s joi ntl y desi gned and devel oped by I ntel Corporati on
and HP (Hewl ett Packard). The EPI C archi tecture i s qui te di fferent than CI SC and RI SC
desi gn. I ts desi gn i s based on the fol l owi ng techni ques:
(i) I nstructi on-l evel paral l el i sm
(ii) Long or very l ong i nstructi on words (LI W or VLI W)
(iii) Branch predi cati on (not the same thi ng as branch predi cti on)
The I tani um processor fetches several bundl es of i nstructi ons at a ti me to i mpl ement
i nstructi on-l evel paral l el i sm. Mul ti pl e bundl es are exami ned to deci de whi ch i nstructi ons can
be executed i n paral l el . The compi l er reorders these i nstructi ons to keep them i n conti guous
bundl es. Such i nstructi ons are i ndependent and can be executed i n paral l el .
I n EPI C archi tecture several paral l el executi on uni ts are used to i ncrease the processi ng
speed of the processor. Many work whi ch are done by hardwares i n conventi onal RI SC and
CI SC desi gn, are done by software i n expl i ci t paral l el i sm approach of desi gn. The compi l er
stati cal l y schedul es i nstructi ons at compi l e ti me, rather than processor doi ng schedul i ng
dynami cal l y at run ti me. The i nstructi ons whi ch can be executed i n paral l el are reordered
and checked for dependenci es by the compi l er. The compi l er al so makes sure whether the
functi onal uni ts needed for the executi on of i nstructi ons are avai l abl e. Si nce the compi l er i s
doi ng al l such work, the processor hardware becomes much si mpl er.
Predi cati on i s a techni que to el i mi nate condi ti onal branches. After a condi ti onal branch,
i nstructi on sets for both the condi ti ons are executed. But at the ti me of reti rement the resul t
for correct condi ti on i s kept and the undesi red resul t i s di scarded. Unl i ke CI SC and RI SC
processors, whi ch general l y have 32 or l ess regi sters, the I tani um has 128 64-bi t regi sters for
i nteger, l ogi cal and general -purpose use; 128 64-bi t regi sters for fl oati ng-poi nt and graphi c
use, 64 1-bi t predi cate regi sters, i nstructi on poi nter, etc. Thus i t i s seen that i t has much
more number of regi sters as compared to a RI SC or CI SC processor. I t uses mul ti pl e 10-stage
pi pel i nes for executi on of mul ti pl e i nstructi ons si mul taneousl y. I t contai ns 4 i nteger uni ts, 4
fl oati ng-poi nt uni ts, 4 MMX uni ts, 2 l oad/store uni ts etc. I t has two fi rst-l evel cache memory,
16 KB each, the second-l evel cache of 256 KB and thi rd-l evel cache 6MB/4MB/2MB. I t contai ns
325 mi l l i on transi stors (25 mi l l i on for CPU and 300 mi l l i on for cache memory). I t uses 0.13
mi cron process technol ogy. I t has 64-bi t address and uses RDRAM having 1.6 GB/S data
transfer rate. I ts operati ng frequency i s 1.3 GHz, 1.4 GHz and 1.5 GHz. I ts system bus
frequency i s 400 MHz. The chi psets used are 460GX, E8870 etc.
5.54 COMPUTER FUNDAMENTALS
The I tani um i s sui tabl e for servers. I t performs best on sci enti fi c appl i cati ons wi th l arge
data sets and l ots of compl ex fl oati ng-poi nt math. I t al so has good performance on transacti on
processi ng and other hi gh-end busi ness appl i cati ons. I t works on di fferent operati ng system
l i ke MS-Wi ndows, Li nux and Uni x.
5.24 POWERPC MICROPROCESSOR
PowerPC mi croprocessors are joi ntl y devel oped by I BM, Motorol a and Appl e. They are
hi gh performance, superscal ar, RI SC processors. The term superscal ar i s used for the archi -
tecture whi ch uses more than one pi pel i ne for the executi on of i nstructi ons.
5.24.1 Versions of PowerPC
The di fferent versi ons of PowerPC are : 601, 602, 603, 604, 620, 740, 750, 760 and 970.
Al l of these mi croprocessors except 620 are 32-bi t mi croprocessors. They have 32-bi t address
bus, 64-bi t data bus, 32 general purpose regi sters (each 32-bi t) and 32 fl oati ng-poi nt regi sters
(each 64-bi t). 32-bi t PowerPC processors use 32-bi t address for physi cal memory and 52-bi t
address for vi rtual memory. The PowerPC620 i s a 64-bi t mi croprocessor. I t has a 64-bi t
address bus, a 64-bi t data bus, 32 general purpose regi sters (each 64-bi t) and 32 fl oati ng-poi nt
regi sters (each 64-bi t).
PowerPC mi croprocessors are desi gned to work i n mul ti processor system. Al l PowerPC
mi croprocessors contai n fl oati ng-poi nt math processor and memory management uni t on the
chi p.
The PowerPC601 i s a entry-l evel general -purpose mi croprocessor. I t i s sui tabl e for desk-
top computers and l ow-end workstati ons. I t operates at 3.6 vol ts, and i t i s avai l abl e at 66, 80
and 100 MHz. I t contai ns 2.8 mi l l i on transi stors. I t has a 32 KB uni fi ed i nstructi on and data
cache. I ts performance rati ngs at 80 MHz are 105 SPECi nt92 and 115 SPECfp92. I t executes
three i nstructi ons per cl ock cycl e.
The PowerPC602 i s a 32-bi t, 66 MHz mi croprocessor. I t contai ns an on-chi p fl oati ng-poi nt
processor. I t i s desi gned wi th superscal ar archi tecture. I t i s sui tabl e for graphi cal , mul ti me-
di a, voi ce-recogni ti on/synthesi s and other functi ons that are requi red i n new entertai nment,
educati on and i nformati on devi ces.
The PowerPC603 has been desi gned for l ow-power consumpti on. I t consumes 1.2 watts
of power whereas the 601 consumes 4 watts. I t i s sui tabl e for portabl e computers such as
notebook, l aptop, and personal di gi tal assi stant (PDA) computers. I t operates at 3.3 vol ts and
i t i s avai l abl e at 66, 80 and 100 MHz. I t contai ns 2.6 mi l l i on transi stors. I t has a 8 KB
i nstructi on cache and 8 KB data cache. I ts performance rati ngs at 80 MHz are 75 SPECi nt92
and 85 SPECfp92. I t executes three i nstructi ons per cl ock cycl e. I t i s smal l er and cheaper
than PowerPC601.
The PowerPC604 i s a hi gh performance 32-bi t RI SC mi croprocessor. I t i s desi gned wi th
superscal ar archi tecture. I t i s more powerful than PowerPC601. I t i s a general purpose
mi croprocessor sui tabl e for desktop, server and workstati on computers. I t operates at 3.3
vol ts, and i t i s avai l abl e at 80, 100, 120 and 133 MHz. I ts performance rati ng at 133 MHz i s
200 SPECi nt92. I t contai ns 3.6 mi l l i on transi stors. I t has a 16 KB i nstructi on cache and 16
KB data cache.
The Power PC620 i s a 64-bi t RI SC mi croprocessor. I t operates at 133 MHz. I ts performance
rati ng i s 225 SPECi nt92 and 300 SPECfp92. I t i s desi gned wi th a 64-bi t address bus, 64-bi t
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data bus, 32 general purpose regi sters (each 64-bi t), 32 fl oati ng-poi nt regi sters (each 64-bi t),
32 KB i nstructi on cache and 32 KB data cache. I t has 64-bi t effecti ve memory addressi ng
capaci ty and 80-bi t vi rtual memory addressi ng capaci ty. I t executes 4 i nstructi ons per cycl e.
Power PC G4, G5 etc have al so been devel oped whi ch are 64-bi t processor. G4 and G5 stand
for fourth and fi fth generati on respecti vel y. Earl i er, Power PC processors were used i n
computers of I BM, Appl e and some other compani es. Today they are used i n embedded
appl i cati ons, and network computers etc.
The 603e and 604e were l ow-power processors. The l atest l ow-power processors are : 740
and 750. They are sui tabl e for notebooks, mobi l e and desktop. The operati ng frequency i s 400
and 450 MHz.
5.24.2 Addressing Modes of PowerPC Processors
The PowerPC processors bei ng RI SC processors have a few si mpl e addressi ng modes for
processi ng/computi ng. Al l i nstructi ons except LOAD/STORE i nstructi ons use regi ster or i mme-
di ate addressi ng. Onl y LOAD/STORE i nstructi ons use memory addressi ng. They are as fol l ows:
(i) Regi ster I ndi rect Addressi ng
(ii) Based I ndi rect Addressi ng wi th Di spl acement
(iii) Based I ndi rect Addressi ng wi th I ndex.
Di rect memory addressi ng i s not used by PowerPC processors.
5.24.3 Register Organization of PowerPC Processors
The 32-bi t PowerPC processors contai n the fol l owi ng regi sters:
General Purpose Registers
PowerPC processors contai n 32 general purpose regi sters (each 32-bi t). They are asso-
ci ated wi th the i nteger uni t of the processor. These regi sters are avai l abl e for i nteger ari th-
meti c cal cul ati on and address computati on.
Floating-Point Registers
PowerPC processors contai n 32 fl oati ng-poi nt regi sters (each 64-bi t). They are associ ated
wi th fl oati ng-poi nt executi on uni t. They are avai l abl e for fl oati ng-poi nt ari thmeti c i nstruc-
ti ons.
The next cl ass of regi sters i ncl udes the status and control regi sters. Thei r bri ef descri p-
ti ons are as fol l ows:
Condition Register
There i s one 32-bi t condi ti on regi ster i n the PowerPC archi tecture. I t stores the status
of resul t of an i nstructi on executi on. These status determi ne the di recti on of a branch. I n
other words the status deci des where the program wi l l jump or whi ch i s the next i nstructi on
to be executed.
Fixed-Point Exception Register
A PowerPC processor i s provi ded wi th a 32-bi t fi xed-poi nt excepti on regi ster. I t i s al so
known as i nteger excepti on regi ster. Thi s regi ster stores i nformati on regardi ng excepti onal
condi ti ons whi ch ari se duri ng the executi on of an i nteger i nstructi on. Thi s regi ster al so stores
the carry bi t out of most si gni fi cant bi t, whi ch ari ses duri ng the executi on of certai n ari th-
meti c operati on.
5.56 COMPUTER FUNDAMENTALS
Floating-Point Status and Control Register
A 32-bi t fl oati ng-poi nt status and control regi ster i s provi ded i n the archi tecture of a
PowerPC processor. Thi s regi ster i s used to record excepti onal condi ti ons that ari se duri ng
the executi on of a fl oati ng-poi nt i nstructi on. I t i s al so used to control the fl oati ng-poi nt
processi ng uni t.
Link Register (LR)
A 32-bi t l i nk regi ster i s associ ated wi th the branch i nstructi ons. I t i s used for subrouti ne
l i nkage. The subrouti ne l i nkage address i s automati cal l y l oaded i nto the l i nk regi ster. The
subrouti ne l i nkage address i s the return address associ ated wi th a subrouti ne cal l .
Count Register (CTR)
A 32-bi t count regi ster i s provi ded wi th PowerPC. I t i s associ ated wi th branch i nstruc-
ti ons. When a l oop i nstructi on i s to be executed, the count i s l oaded i nto thi s regi ster. Thi s
regi ster i s automati cal l y decremented and tested whether the count has reached zero.
Segment Registers
There are si xteen 32-bi t segment regi sters provi ded i n the archi tecture of PowerPC
processors. These regi sters are used for memory management.
I n addi ti on to above regi sters there are a number of speci al purpose regi sters such as
18 data storage i nterrupt status regi sters (DSI SR), 19 data address regi sters (DAR), 22
decrementors (DEC), 26 machi ne status save restore regi sters 0 (SRR0), machi ne state regi ster
(MSR), 27 machi ne status save restore regi sters 1 (SRR1), etc.
Registers for 64-Bit PowerPC Processors
The regi sters for 64-bi t PowerPC processors are same as those for 32-bi t PowerPC
processors, but al l of them are 64-bi t regi sters.
5.24.4 Memory Organization
32-bi t PowerPC processors use 32-bi t address bus for memory addressi ng. Usi ng 32-bi t
address bus, up to 4 GB of physi cal memory can be addressed. The MMU uses 52-bi t address
for vi rtual memory addressi ng. The vi rtual memory capaci ty i s 2
52
bytes whi ch i s equal to
4 2
50
bytes (4PB). Memory i s di vi ded i nto segments. The capaci ty of each segment i s 256 MB
(2
28
bytes). Vi rtual memory i s spl i t i nto 2
24
segments (2
52
bytes = 2
24
2
28
= 2
24
256 MB).
Each segment has been spl i t i nto 2
16
4 KB (2
16
4 2
10
bytes = 2
28
bytes).
Fi nal l y, 12-bi t (4 KB = 2
12
) offset i s used to address a memory l ocati on whi ch contai ns
a byte.
A 32-bi t effecti ve address i s used by the programmer to access memory. The upper-order
4 bi ts of the effecti ve address are used to access one of 16 segment regi sters of the processor.
Each segment regi ster contai ns a 24-bi t i denti fi cati on number correspondi ng to one 256 MB
segment. The next 16 bi ts of the effecti ve address i denti fy the page wi thi n the segment whi ch
i s to be accessed. The remai ni ng 12 bi ts i n the effecti ve address i denti fy the bytes wi thi n the
page bei ng accessed.
64-bi t PowerPC processors use 64-bi t address bus. Usi ng 64-bi t address bus, 2
64
bytes of
physi cal memory can be addressed. 64-bi t PowerPC processors use 80-bi t address for vi rtual
memory addressi ng.
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5.24.5 Interrupts
PowerPC processors are enabl ed by excepti on-handl i ng mechani sm to change state and
react to program requests, si gnal s, errors, or external events. The bi ts i n the machi ne state
regi ster (MSR) of the processor sel ect supervi sor mode, enabl e and di sabl e some i nterrupts
and determi ne how the processor reacts to some system events. Two i nterrupts of parti cul ar
i nterest to the assembl y l anguage programmer are: system cal l i nterrupt and program i nter-
rupt. When a programmer wants to use some operati ng system faci l i ty, he can use a system
cal l i nstructi on. Such an i nstructi on causes a system cal l i nterrupt. The system cal l i nstructi on
i s a subrouti ne cal l to an operati ng system subrouti ne. The program i nterrupt can be caused
by a trap i nstructi on. A trap i nstructi on checks for an error condi ti on and then traps (causes
a program i nterrupt) i f such an error occurs. From that poi nt, the operati ng system may try
to fi x the error.
5.25 MIPS MICROPROCESSORS
MI PS (brought out by Si l i con Graphi cs) company has devel oped a number of 64-bi t
RI SC processor such as R4000, R4400, R5000 R10,000 and R12,000. R4400 i s a l ow-power
processor sui tabl e for desktop computers. MI PS 10,000 contai ns 32 KB i nstructi on cache,
32 KB data cache, 5 i ndependent functi onal uni ts, thi rty-two 64-bi t general purpose regi sters,
thi r ty-two 64-bi t fl oati ng-poi nt r egi ster s, etc. I t contai ns 6.4 mi l l i on tr ansi stor s. I ts
performance rati ngs at 200 MHz are: 300 SPECi nt92 and 600 SPECfp92. MI PS 12000 i s the
l atest 64-bi t RI SC processor.
These processors are al so used i n embedded appl i cati ons. They are parti cul arl y suc-
cessful i n vi deo game consol es and networki ng appl i cati ons. They are used i n Sony pl ay
Stati on, Sonys 3-D graphi cs engi nes, Ni netendo 64 game consol e, hi gh-speed routers i n
I nternet etc.
5.26 DECS ALPHA MICROPROCESSORS
The Di gi tal Equi pment Corporati on (DEC) has devel oped 64-bi t RI SC processor: Al pha
21064, 21164, and 21264. The operati ng frequency gradual l y i ncreased from 200 MHz to
1000 MHz for i ts di fferent versi ons. The Al pha 21164 contai ns 8 KB i nstructi on cache and
8 KB data cache, 96 KB second-l evel cache, 4 functi onal uni ts, thi rty-two 64-bi t general -
purpose regi sters, thi rty two 64-bi t fl oati ng-poi nt regi sters, etc. I t contai ns 9 mi l l i on transi stors.
I ts performance rati ngs at 300 MHz are: 330 SPECi nt92 and 500 SPECfp92. The Al pha 21164
was al so devel oped at 600 and 622 MHz. The l atest Al pha processor i s 21264 whi ch operates
at 700 MHz and 1000 MHz and uses 0.25 mi cron process technol ogy. DEC company has been
aqui red by Compaq company i n the year 1998.
5.27 CYRIX MICROPROCESSORS
Cyri x was competi tor of I ntel corporati on. I t has devel oped 32-bi t mi croprocessors: 586,
686, 6X86MX. etc. The 586 was devel oped to compete wi th I ntel s Penti um. The 6X86MX
competes wi th Penti um I I . I t was desi gned by Cyri x and manufactured by I BM. I t outperforms
Penti um I I . Cyri x mi croprocessors are cheaper than I ntel s mi croprocessors. Nati onal Semi -
5.58 COMPUTER FUNDAMENTALS
conductors purchased Cyri x i n the year 1997. I n the year 1999, Nati onal Semi conductors sol d
some parts of Cyri x to Via Technol ogy. I t kept some parts whi ch can be used by Nati onal Semi
Conductors i n i ts si ngl e-chi p embedded sol uti ons.
5.28 AMD (ADVANCED MICRO DEVICES) PROCESSORS
AMD i s the competi tor of I ntel Corporati on. I t has devel oped 32-bi t processors:
K5, K6, K6-MMX, K6-2, K6-3 and K7. The K5 was devel oped to compete wi th Penti um.
The K6-MMX i s a mul ti medi a processor. I t i s cheaper than Penti um I I . I t i s sui tabl e for server
computer. I t i s used for hi gh-end engi neeri ng, sci enti fi c, and graphi cs appl i cati ons. I t works wi th
al l l eadi ng operati ng systems. I t used 0.25 mi cron process technol ogy. K6-2 operates at 475
MHz, K6-3 at 500 MHz and K7 at 700 MHz, 800 MHz and 1.1 GHz. The K6-3 contai ns 256 KB
L2 (second-l evel ) cache and 2 MB L3 (thi rd-l evel ) cache memory. The K7 wi l l compete wi th
Penti um I I I . K7 i s now cal l ed Athl on. 1.1 GHz Athl on uses copper wi res, rather than al umi ni um,
to connect ci rcui ts. I t contai ns 22 mi l l i on transi stors. I ts bus frequency i s 200 MHz. The code
name of the next generati on Athl on chip is Thunderbi rd. I t wi l l operate at 1 GHz and 1.1 GHz.
K7 i s a CI SC processor. After thi s, AMD produced Athl on XP and Sempron processors. AMD has
al so produced 64-bi t processor-Athl on 64, Athl on 64FX, Optiron and Athl on 64 X2 seri es of
processors. The processors of FX seri es are Athl on 64 FX51, Athl on 64 FX55, Athl on 64 FX57
etc. Whenever a new processor i n FX seri es comes, the ol der FX i s renamed, for exampl e, The
previ ous FX53 i s now cal l ed Athl on 64 4000 + . The AMDs Optiron and Athl on 64 X2 are a
64-bi t dual core processors.
5.29 SUNS ULTRASPARC MICROPROCESSOR
The SUNs ULTRASPARC processor i s a 64-bi t RI SC processor. SPARC stands for Scal abl e
Processor Archi tecture. I t contai ns 9 i ndependent functi onal uni ts, 16KB on-chi p i nstructi on
cache, 16 KB on-chi p data cache, etc. I t contai ns 3.8 mi l l i on transi stors. I t can i ssue 4
i nstructi ons per cl ock cycl e. I ts performance rati ngs at 167 MHz are : 275 SPECi nt92 and 305
SPECfp92. I ts l atest versi on i s ULTRASPARC I I I . I t contai ns 29 mi l l i on transi stors. I t operates
at 750 and 900 MHZ. I t i s used i n servers, workstati ons and supercomputers. I t i s sui tabl e
for mul ti processor envi ronment.
5.30 NATIONAL SEMICONDUCTORS MICROPROCESSORS
32-bi t mi croprocessors devel oped by Nati onal Semi conductors are : NS 32032, NS32332,
NS32C532, M2 300, etc. The NS 32332 uses 32-bi t address bus, ALU wi th barrel shi fter, 20
bytes i nstructi on queue, dynami cal l y confi gurabl e bus-wi dth of 8,16, or 32 bi ts dependi ng upon
the memory or I /O area addressed, burst mode of bus transacti ons, etc. I ts l atest 32-bi t
processors M2 operates at 300 MHz and can outperform I ntel s Cel eron. I t i s to be manufac-
tured by Nati onal s contract manufacture I BM.
5.31 MOTOROLA MICROPROCESSORS
Motorol a i ntroduced i ts fi rst 8-bi t mi croprocessor 6800 i n 1974. I t was wi del y used i n
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i ndustry for control l i ng equi pment i n 1970s. I t was fol l owed by an advanced 8-bi t mi cropro-
cessor 6809. The 6809 i s faster and more powerful than 6800.
I n 1979, Motorol a i ntroduced an advanced powerful 16-bi t mi croprocessor 68000. Though
i ts data bus i s 16-bi t wi de i ts i nternal archi tecture i s of 32 bi ts. I t can di rectl y address upto
16 MB memory. I t i s a hybri d computer between 16-bi t and 32-bi t archi tecture. I t was very
popul ar and wi del y used.
Motorol a i ntroduced 68008 mi croprocessor i n 1982. I t i s si mi l ar to 68000 but i t has onl y
8-bi t data bus so that i t can use 8-bi t I /O devi ces. Thi s was devel oped to bui l d cheaper
computers usi ng 8-bi t I /O devi ces. I t was not wi del y used.
I n 1983, Motorol a i ntroduced 68010 mi croprocessor an i mproved versi on of 68000. The
68010 contai ned hardware features to support vi rtual memory. I ts di rect memory addressi ng
capaci ty i s 16 MB. Agai n i n 1983 Motorol a devel oped 68012 si mi l ar to 68010 but i ts memory
addressi ng capaci ty i s more, i.e., 2 GB.
I n 1984, Motorol a i ntroduced 68020, an advanced 32-bi t mi croprocessor. I ts data bus i s
32-bi t wi de. I ts di rect memory addressi ng capaci ty i s 4 GB. I t has on-chi p i nstructi on cache.
I t was wi del y used.
Motorol a i ntroduced 68030, an advanced 32-bi t mi croprocessor i n 1987. I t contai ns 68020
pl us a MMU on the chi p i tsel f. Besi des i nstructi on cache i t al so contai ns data cache. I t was
wi del y used i n mi ni computers.
I n 1989, Motorol a i ntroduced 68040, an advanced mi croprocessor. I t contai ns a CPU,
MMU, fl oati ng-poi nt coprocessor and cache memory. I t contai ns a ci rcui try of 1.2 mi l l i on
transi stors. The 68040 was sui tabl e to be the CPU of a mi ni computer.
Motorol a 680X0 seri es of mi croprocessors were si mi l ar from programmers poi nt of vi ew.
An i mproved new machi ne of thi s seri es can run the software of i ts predecessor of the seri es.
I n 1980s the 680X0 seri es of processors were used i n desktop and server computers. They are
no l onger used i n desktop computers or servers. But they are used for embedded appl i cati ons.
I n mi d 1990s the l atest member of thi s seri es was 68060. I t i s desi gned for embedded
appl i cati ons. For embedded appl i cati ons Col dFi re processors and 68300 mi crocontrol l er have
al so been devel oped. These products are used i n l aser pri nters, network equi pment, commu-
ni cati on devi ces, etc.
5.32 TRANSMETA CORPORATIONS CRUSOE CHIPS
The Crusoe chi ps have been desi gned and devel oped for handhel ds, notebooks, Net
appl i cati ons etc. These chi ps consume much l ess power but they are l ess powerful than other
chi ps for si mi l ar appl i cati ons. These chi ps are desi gned to emul ate the functi ons of I ntel s
X86 mi croprocessors. I n mi croprogrammed approach, new i nstructi ons can be i ntroduced by
wri ti ng new mi croprograms. I nstructi ons for any other computer can be executed. Thi s
pr ocess i s known as emulation. The softwar e cal l ed code-mor phi ng conver ts I ntel s
computi ng i nstructi ons i nto VLI W (Very Long I nstructi on Word) i nstructi on to speed up
computi ng by executi ng several si mpl e i nstructi ons i n paral l el . The TM3120 chi p i s used i n
handhel d computers, WebPad-l i ke i nformati on appl i ances and Web browsers. The TM5400
chi p i s used i n l aptop computers and runs MS-Wi ndows operati ng system. The Crusoe chi ps
consume 1-2 watts power as compared to 25 watts power consumed by conventi onal processors
of I ntel and AMD.
5.60 COMPUTER FUNDAMENTALS
5.33 VIAS C3 PROCESSOR
The C3 processor i s desi gned for desktop computers. I t consumes much l ess power (onl y
8.5 watts) compared to I ntel s Cel eron (21 watts at 800 MHZ) and AMDs mobile Athl on
processor (22 watts at 850 MHZ). I ts performance i s acceptabl e i n i nteger operati ons but
l ackl usture i n fl oati ng-poi nt ones. I ts fi rst-l evel cache memory i s of 128 KB and the second-
l evel cache memory of 64 KB. I t uses 133 MHZ fast seri al bus (FSB).
5.34 ARM MICROPROCESSORS
ARM (Advanced RI SC Machi nes) mi croprocessors were devel oped i n 1980s for smal l
computers. The ARM does not manufacture chi ps, i t gi ves desi gns and i ssues l i cense to other
chi p manufacturi ng compani es such as I ntel , Hewl ett-Packard, Texas I nstruments, Di gi tal
Equi pment etc. ARM mi croprocessors are fast and consume l ess power. They are desi gned for
portabl e computer, cel l ul ar phones, communi cati on modems, automoti ve engi nes, network
appl i ances and other embedded appl i cati ons. They are l ow-cost processors for l ow-power
appl i cati ons. They are 32-bi t processors, can address 4 GB memory and contai n 3-stage
pi pel i ne. The di fferent versi ons of an ARM processor are: ARM 7, 9 and 10. Today many
products by di fferent compani es based on ARM processors are i n the market.
5.35 CELL PROCESSORS
The Cel l processor i s bei ng joi ntl y devel oped by Sony, Toshi ba and I BM. I t i s a mul ti -
core processor whi ch contai ns 8 processors on a si ngl e si l i con chi p. I ts cl ock speed i s 4.6 GHz
and i ts operati ng vol tage 1.3 vol t. I t contai ns 234 mi l l i on transi stors. I ts computi ng power i s
256 GFLOPS whereas that of Penti um 4 at 3 GHz i s onl y 6 GFLOPS. I t supports mul ti pl e
operati ng systems. The Cel l processor i s bui l t for hi gh performance, vector-based di stri buted
computi ng. Each processor i n the Cel l processor i s a vector processor.
5.36 RISC, CISC AND EPIC MACHINES
RI SC i s an abbrevi ati on for reduced i nstructi on set computer. The exampl es of RI SC
machi nes are DECs Al pha, PowerPC, ULTRASPARC, etc. CI SC i s an abbrevi ati on for compl ex
i nstructi on set computer. The exampl es of CI SC machi nes are: I ntel 80486, Penti um, Penti um
I I , Cel eron, Penti um I I I , Penti um 4, AMDs Athl on etc.
The ai m of empl oyi ng RI SC desi gn i s to i ncrease the computi ng speed by reduci ng the
executi on ti me of i nstructi ons. I t i s seen that usual l y 80% of a computers i nstructi ons are
used l ess frequentl y, onl y for 20% of the ti me. The 20% of the i nstructi ons are used more
frequentl y, for 80% of the ti me. The phi l osophy of RI SC machi ne i s based on the fact that
frequentl y used 20% of the i nstructi ons are i mpl emented i n the hardwi red ci rcui try of the
chip itself i.e., by hardware techni que. The remai ni ng 80% of the i nstructi ons are i mpl e-
mented by computers software. Al most al l computati ons are performed usi ng si mpl e i nstruc-
ti ons. Usual l y, a RI SC machi ne i s 5 to 10 ti mes faster than a CI SC machi ne.
The i mportant features of a RI SC mi croprocessor are as fol l ows:
(i) There are few i nstructi on types and few addressi ng modes.
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(ii) I nstructi on set i s si mpl er so that the processor runs faster. RI SC machi nes have
fi xed and easi l y decoded i nstr ucti on for mats. All i nstr ucti ons ar e decoded by
hardware.
(iii) Most i nstructi ons are executed i n a si ngl e cycl e.
(iv) Most RI SC i nstructi ons i nvol ve onl y regi ster-to-regi ster operati ons. Memory access
i s l i mi ted onl y to l oad and store i nstructi ons.
(v) Several general -purpose regi sters and l arge cache memori es are empl oyed.
(vi) Hardwi red control s are used. Mi croprogrammi ng i s not used. I n other words
mi crocodes are not empl oyed to generate i nstructi ons.
The CI SC machi nes use mi croprogrammi ng. Wi th the hel p of mi croprograms hi ghl y
compl ex i nstructi on set i s generated. Compl ex i nstructi ons l ead to a number of compl i cati ons
i n both hardware and software desi gn. I n sci enti fi c computati ons i f there are more fl oati ng-
poi nt operati ons CI SC machi nes are l i kel y to gi ve better performance. CI SC machi nes are
more compl ex and l ess effi ci ent.
The earl i est di gi tal computers were very si mpl e. They empl oyed few i nstructi ons and few
addressi ng modes. The I BM 360 seri es was i ntroduced i n 1964 whi ch empl oyed mi croprogram-
mi ng. The mi croprogrammi ng techni que l eads to a compl ex i nstructi on set. Wi thi n a few
years even mi ni computers were desi gned wi th 200 i nstructi ons and a dozen of addressi ng
modes. To sol ve the probl em of compl exi ty and comparati vel y sl ow speed of CI SC machi nes
computer i ndustry i s now produci ng si mpl e and fast RI SC machi nes. EPI C (Extensi vel y
Paral l el I nstructi ons Computi ng) processors have been devel oped by I ntel . For detai l s Refer
to Secti on 5.23.
PROBLEMS
1. Di scuss the functi on of a CPU. What are the mai n secti ons of a CPU ? Di scuss the
functi on of each secti on.
2. What operati ons are performed by an ALU ?
3. Di scuss the rol e of the ti mi ng and control uni t of a computer.
4. What i s the purpose of provi di ng regi sters i n a CPU? Descri be vari ous regi sters whi ch are
usual l y provi ded i n a mi croprocessor ?
5. Expl ai n the requi rements of a program counter, a stack poi nter and status fl ags i n a
mi croprocessor.
6. What status fl ags are normal l y provi ded i n a mi croprocessor ?
7. Di scuss the functi on of an i ndex regi ster, memory address regi ster (MAR) and memory buffer
regi ster (MBR).
8. Expl ai n i nstructi on format. What are the vari ous types of i nstructi on formats ? Di scuss
them wi th sui tabl e exampl es.
9. Di scuss the vari ous types of addressi ng modes whi ch are usual l y provi ded i n a mi croprocessor.
Gi ve sui tabl e exampl es.
10. Expl ai n what you understand by i nterrupts. Di scuss enabl i ng, di sabl i ng and maski ng of
i nterrupts.
11. Expl ai n the terms hardware i nterrupts and software i nterrupts. What do you understand
by excepti ons ?
5.62 COMPUTER FUNDAMENTALS
12. Expl ai n i nstructi on cycl es, machi ne cycl es and states.
13. What are fetch cycl es and execute cycl es ?
14. Draw and expl ai n the ti mi ng di agram for opcode fetch cycl e for I ntel 8085.
15. Draw and expl ai n the ti mi ng di agram for memroy read cycl e for I ntel 8085.
16. Draw and expl ai n the ti mi ng di agram for memory wri te cycl e for I ntel 8085.
17. Draw and expl ai n the ti mi ng di agram for I /O read cycl e for I ntel 8085.
18. Draw and expl ai n ti mi ng di agram for I /O wri te cycl e for I ntel 8085.
19. Draw and expl ai n the ti mi ng di agram for MOV r
1
, r
2
for I ntel 8085.
20. Draw and expl ai n the ti mi ng di agram for MVI A, data for I ntel 8085.
21. What are the vari ous regi sters provi ded i n I ntel 8086 ? Di scuss thei r functi on.
22. What do you understand by pi pel i ni ng ? How i s i t achi eved i n I ntel 8086 ?
23. Di scuss the memory organi zati on of I ntel 8086.
24. What i s the purpose of semaphore and LOCK provi ded i n I ntel 8086 ?
25. Expl ai n what are Von Neumann and data fl ow archi tectures of processors.
26. I n what way operati ng pri nci pl e of Penti um Pro, Penti um I I , Penti um I I I and Penti um 4
di ffer from earl i er mi croprocessors such as Penti um or 486 processor ?
Di scuss the operati ng pri nci pl e of Penti um Pro i n detai l .
27. What i s MMX? Di scuss i ts need and appl i cati ons.
28. Di scuss the advantage of a RI SC processor over CI SC processor.
29. Gi ve some exampl e or 32-bi t and 64-bi t mi croprocessors whi ch are manufactured by compani es
other than I ntel .
30. Di scuss the operati ng pri nci pl e of Penti um 4.
31. Di scuss the operati ng pri nci pl e of I tani um.
6
CHAPTER CHAPTER
-4;
Memory i s an essenti al component of a di gi tal computer. I t i s a stori ng devi ce. I t stores
programs, data, resul ts etc. At present the fol l owi ng three ki nds of memory are commonl y
used i n modern computers:
(i) Semi conductor memory
(ii) Magneti c memory
(iii) Opti cal memory
The semi conductor memory i s faster, compact and l i ghter. I t consumes l ess power. The
semi conductor memory i s stati c devi ce. There i s no rotati ng part i n i t. The magneti c and
opti cal memory are sl ow compared to semi conductor memory. But they are cheaper than
semi conductor memory. They are not stati c devi ces. They are ei ther i n the form of rotati ng
di sk or tape.
6.1 MAIN MEMORY, SECONDARY MEMORY AND BACKUP MEMORY
Al l computers except very smal l computers contai n both semi conductor as wel l as mag-
neti c memory. The semi conductor memory i s empl oyed as the main memory (or primary
memory) of the computer. I t stores programs and data whi ch are currentl y needed by the
CPU. The magneti c memory i s used as secondary (or auxiliary) memory. The i nformati on
whi ch i s not bei ng currentl y processed resi des i n the secondary memory. The i nformati on
whi ch i s needed by the CPU for current processi ng i s transferred from the secondary memory
to the mai n memory. The si ze of the mai n memory i s comparati vel y much smal l er than that
of the secondary memory because of i ts hi gh cost. The CPU communi cates di rectl y wi th the
mai n memory. As the CPU empl oys semi conductor technol ogy and has very hi gh speed, i ts
matchi ng memory must be very fast. Onl y semi conductor devi ces can provi de the matchi ng
speed. Thus the mai n memory al so must empl oy semi conductor technol ogy. RAM and ROM
I Cs are used as the mai n memory of the computer. RAMs are vol ati l e, i.e., thei r contents are
erased when power goes off.
The secondary memory i s empl oyed for bul k storage (mass storage) of programs, data
and other i nformati ons. I t has much l arger capaci ty than mai n memory. I t stores system
software, assembl ers, compi l ers, useful packages, l arge-data fi l es etc. The secondary memory
shoul d not be of vol ati l e nature. I t must store i nformati on permanentl y. The magneti c
memory has thi s property. I t retai ns the i nformati on once stored i n i t. The magneti c memo-
ri es such as hard di sks are the most common secondary memori es used i n computers.
6.1
6.2 COMPUTER FUNDAMENTALS
Fig. 6.1 Memory hi erarchi es (a) wi thout cache memory (b) wi th cache memory.
The two most common memory hi erarchi es are shown i n Fi g. 6.1. Fi g. 6.1 (a) shows a
computer system whi ch has onl y mai n and secondary memori es but no cache memory. Fi g.
6.1(b) shows a system whi ch i ncl udes a cache memory.
Backup memory i s used to store the copy of the i mportant programs such as operati ng
system, compi l ers etc.These programs are general l y avai l abl e i n the secondary memory but
thei r copi es are al so kept i n the backup memory so that they can be rel oaded i nto the
secondary memory i n case the programs stored i n the secondary memory are l ost acci dental l y
or due to any other reason. Fl oppy di sks, opti cal di sks, and magneti c tapes can be used as
backup storage.
6.2 CACHE MEMORY
The word cache i s pronounced as cash. The cache memory i s pl aced i n between CPU and
mai n memory. The processor i s connected to the cache memory through a cache control l er.
I t i s a semi conductor memory. I t consi sts of stati c RAMs. I ts access ti me i s about 10 ns
(nanosecond). 1 nanosecond = 10
9
second. whi ch i s much l ess than that of the mai n memory.
The access ti me of the mai n memory i s about 50 ns. The capaci ty of the cache memory i s
2 to 3 percent of that of the mai n memory. I t stores i nstructi on codes and data, whi ch are
to be currentl y executed by the CPU. I t i s used to reduce the average access ti me for
i nstructi ons and data, whi ch are normal l y stored i n the mai n memory. A cache memory al so
needs a cache control l er. Cache control l er I Cs are avai l abl e.
The modern 32-bi t and 64-bi t mi croprocessors operate at very hi gh speed. Thei r cl ock
rates are usual l y i n the range of 1GHz3.8GHz. The memory matchi ng wi th hi gh-speed
mi cr opr ocessor must be ver y fast. But ver y fast memor y i s ver y expensi ve. I f a fast
MEMORY 6.3
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mi croprocessor operates wi th conventi onal mai n memory, i t has to operate wi th several wai t
states. Thi s wi l l reduce the speed of the computer. A compromi se i s made, and a hi gh-speed
cache memory i s used to suppl y currentl y needed i nstructi ons and data to CPU. The mai n
memory stores program and data, whi ch i s to be processed by the CPU. The currentl y needed
i nstructi ons and data of the program are l oaded i nto the cache from the mai n memory.
There are two types of cache schemes: write-through and write-back. I n a wri te
through cache the mai n memory i s updated each ti me the CPU wri tes i nto the cache. The
advantage of the wri te-through cache i s that the mai n memory al ways contai ns the same data
as the cache contai ns. Thi s characteri sti c i s desi rabl e i n a system whi ch uses di rect memory
access (DMA) scheme of data transfer. The I /O devi ces communi cati ng through DMA recei ve
the most recent data. I n a wri te-back cache, onl y the cache memory i s updated duri ng a wri te
operati on. The updated l ocati ons i n the cache are marked by fl ags so that l ater on when the
word i s removed from the cache, i t i s copi ed i nto the mai n memory. The words are removed
from the cache ti me to ti me to make room for a new bl ock of words. The contents of updated
cache memory l ocati ons are copi ed i nto the mai n memory when there are free processor
cycl es. Thi s requi res addi ti onal hardware support, but i mproves performance, si nce the ex-
changes between cache and the mai n memory are fewer and better ti med. The wri te-back
scheme i ncreases performance by reduci ng the uti l i zati on of buses and preventi ng unneces-
sary bottl enecks i n the system. Thi s scheme i s faster and hence i t i s preferred.
The techni que of accessi ng a cache memory di ffers from that of the mai n memory. To
access mai n memory the CPU sends an address to i t. I n response of thi s the mai n memory
sends data contai ned at the speci fi ed memory address. On the other hand cache memory uses
paral l el searchi ng of the requi red data. I t fi rst compares the i ncomi ng address to the ad-
dresses present i n the cache. I f the address matches, i t i s sai d that a hit has occurred. Then
the correspondi ng data i s read by the CPU. I f the address does not match, i t i s sai d that a
miss has occurred. When a mi ss occurs, the data i s read from the mai n memory. The data
read from the mai n memory i s al so wri tten to the cache memory, so that when thi s speci fi c
address i s accessed next ti me a hi t occurs. Usual l y, hi t rati o i s above 90 per cent. The hi t
rati o i s defi ned as the rati o of the number of hi ts to the total number of read requests sent
to the cache memory by the CPU. Usual l y, setassoci ati ve cache memory i s used i n a computer.
The memory i n whi ch paral l el search of the requi red data i s done, i s known as associ ati ve
memory. Set associ ati ve memory i s a ki nd of associ ati ve memory.
Cache memory i s pl aced at two or three l evel s. They are cal l ed fi rst-l evel cache (L1),
second-l evel cache (L2), and thi rd-l evel cache (L3). Some mi croprocessors contai n L1 and L2
wi thi n the mi croprocessors. Some mi croprocessors contai n L1, L2 and L3 wi thi n the mi cro-
processor. Cache wi thi n the mi croprocessor i s cal l ed i nternal cache. The cache outsi de the
processor i s cal l ed external cache.
I n a wri te-through cache the mai n memory i s to be updated each ti me the CPU wri tes
i nto the cache. I f CPU wai ts for wri te operati on of the mai n memory, i t i s sl owed down.
Moreover, the CPU does not need the resul t of the wri te operati on i mmedi atel y. Therefore,
i t i s not necessary for the CPU to wai t for the wri te operati on to be compl eted. Hence, to
i mprove performance a write buffer can be i ncl uded for temporary storage for wri te requests.
The CPU keeps each wri te request i nto thi s buffer, and executes the next i nstructi on. The
i nformati on from the wri te buffer i s sent to the mai n memory whenever the memory i s not
respondi ng to read requests. I n case of wri te-back cache al so a wri te buffer may be i ncl uded.
I t hol ds temporari l y the fl ag marked bl ocks of data, whi ch are to be removed from the cache
and to be stored i n the mai n memory. The read operati on from the mai n memory for a new
bl ock of data needed by the CPU must be performed i mmedi atel y. The CPU shoul d not wai t
6.4 COMPUTER FUNDAMENTALS
ti l l the room i s made i n cache by removi ng a bl ock and then to perform read operati on to
get the new bl ock of data from the mai n memory. For thi s purpose al so the buffer i s needed.
6.2.1 Cache Controllers
When the CPU sends an address of i nstructi on code or data, the cache control l er exam-
i nes whether the content of the speci fi ed address i s present i n the cache memory. I f the
i nstructi on code or data i s avai l abl e i n the cache memory, the cache control l er enabl es the
cache memory to send the addressed code/data to the CPU. I f the addressed i nstructi on code
or data i s not present i n the cache memory the cache control l er enabl es the control l er of the
mai n memory to send the addressed code/data from the mai n memory. The mai n memory
outputs the addressed code/data on data bus. From the data bus the code/data i s sent to the
CPU as wel l as cache memory.
Cache Controllers, Intel 82496, 82497 and 82498
These cache control l ers have been devel oped to control the second-l evel cache memory
i n Penti um-based computers. They can i mpl ement wri te-back cache for mul ti -processi ng
support. Dual ported buffers and regi sters al l ow them to concurrentl y handl e CPU bus,
memory bus and i nternal cache operati on for maxi mum performance. They have the features
of synchronous, asynchronous and strobed memory bus operati on, sel ectabl e bus wi dth and
the l i ne si zes, transfers and burst orders. The 82496 and 82497 support 32, 64 and 128-bi t
wi de memory bus; and 16, 32 and 64-byte l i ne si zes. They support 256KB and 512KB cache
memory wi th pari ty. The 82498 supports 64 and 128-bi t wi de memory bus; and 32, 64-byte
l i ne si zes. Cache memory i s arranged i n l i nes of data. The enti re l i ne i s transferred to or from
the memory at a ti me. The 82498 supports 1M bytes to 2M bytes cache memory. The 82496,
82497 and 82498 cache control l ers control 82491, 82492 and 82493 SRAM cache memory
respecti vel y. 1KB = 1 Ki l o Bytes = 2
10
Bytes. 1MB = 1 Mega Bytes = 2
20
Bytes.
I n Penti um Pro, Penti um I I , Penti um I I I and Penti um 4, the second-l evel cache memory
and i ts control l er are wi thi n the processor i tsel f.
6.3 REAL (OR PHYSICAL) AND VIRTUAL MEMORY
The real or physi cal memory i s the actual mai n memory provi ded i n the system. I t i s
di rectl y addressed by the CPU. The address of a l ocati on of the physi cal memory i s cal l ed
physical address.
The techni que whi ch al l ows a program to use mai n memory more than what a computer
real l y has i s known as virtual memory technique. I t gi ves the programmers an i l l usi on that
they have mai n memory avai l abl e more than what i s physi cal l y provi ded i n the computer.
The enti re program and i ts data are not pl aced i n the mai n memory. Onl y the i nstructi ons
and data whi ch are to be currentl y executed are brought from the secondary memory i nto
the mai n memory. The remai ni ng part of the program resi des i n the secondary memory.
When the part of the program whi ch i s i n the mai n memory has been executed, i t i s sent
back to the secondary memory. Thereafter another part i s brought i nto the pri mary memory
for i ts executi on. The to and fro movements of the parts of a program between the mai n
memory (physi cal or real memory) and the secondary memory (hard di sks) i s cal l ed swapping.
Usi ng swappi ng techni que a program requi ri ng much l arger capaci ty than that of the mai n
memory can be executed. Thi s techni que i s cal l ed vi rtual memory techni que. The vi rtual
memory space i s much l arger than the physi cal memory (mai n memory) space. For exampl e
MEMORY 6.5
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the 80386 can di rectl y address 4 GB of physi cal memory. I ts vi rtual memory addressi ng
capaci ty i s 64 TB. The capaci ty of vi rtual memory depends on the desi gn aspects of a
processor. (Terabytes). 1 Tera = 2
40
.
The addresses whi ch are used i n a program are cal l ed logical addresses. These addresses
i ndi cate the posi ti ons of i nstructi ons and data i n the program. The l ogi cal addresses are
transl ated i nto physi cal addresses by memory management uni t, MMU. The MMU i s pl aced
i n between the processor and mai n memory. The CPU generates l ogi cal address whi l e execut-
i ng the program. The MMU recei ves a l ogi cal address from the processor and determi nes
whether the l ogi cal address i s present i n the physi cal memory (i .e., mai n memory). I f i t i s
present i n the mai n memory, the MMU determi nes the correspondi ng physi cal address. I f the
l ogi cal address i s not present i n the physi cal memory, the MMU i nterrupts CPU. The CPU
executes a servi ce routi ne to bri ng the requi red i nformati on from the secondary memory to
the physi cal memory. Thereafter the MMU determi nes the correspondi ng physi cal address.
The detai l s of MMU wi l l be di scussed l ater on i n thi s chapter. The l ogi cal address i s al so
called virtual address i n a system whi ch has provi si on for vi rtual memory.
6.4 SEMICONDUCTOR MEMORY
Semi conductor memori es are of two types: RAM (random access memory) and ROM (read
onl y memory). The vari ous ki nds of RAMs and ROMs are as descri bed bel ow.
6.4.1 RAM
The read and wri te memory (R/W memory) of a computer i s cal l ed RAM. The users can
wri te i nformati on i nto RAM and read i nformati on from i t. I t i s accessi bl e to users. The user
enters hi s program and data i nto RAM. I t possesses random access property. I n a random
access memory any memory l ocati on can be accessed i n a random manner wi thout goi ng
through any other memory l ocati on. The access ti me i s same for each memory l ocati on. RAM
i s a vol ati l e memory. The i nformati on wri tten i nto i t i s retai ned i n i t as l ong as the power
suppl y i s on. As soon as the power suppl y goes off (or i nterrupted) i ts stored i nformati on i s
l ost. The programmer has to rel oad hi s program and data i nto the RAM when the power
suppl y i s resumed.
RAM i s not the correct name of R/W memory because both RAM and ROM possess
random access property. But R/W memory has been cal l ed RAM si nce l ong and i n practi ce
i t has become an establ i shed name. Thus R/W memory i s commonl y cal l ed RAM.
There are two i mportant types of RAMs: stati c RAM and dynami c RAM. Stati c RAMs
retai n stored i nformati on onl y as l ong as the power suppl y i s on. But a dynami c RAM l oses
i ts stored i nformati on i n a very short ti me (a few mi l l i seconds) even though the power suppl y
i s on. I n a dynami c RAM a bi nary state i s stored on the gate to source stray capaci tor of a
transi stor of the MOS memory ci rcui t. The presence of charge on the stray capaci tor repre-
sents 1, and the absence of charge on the stray capaci tor represents 0. The charge on these
capaci tors l eak away as a resul t of normal l eakage i n a few mi l l i seconds. Therefore, dynami c
RAMs have to be refreshed peri odi cal l y, general l y every 2 mi l l i seconds. The dynami c RAMs
are cheaper and have hi gh packi ng densi ty and moderate speed. They consume l ess power.
They are used where l arge capaci ty of memory i s needed. Stati c RAMs are costl i er and
consume more power. They do not need refreshi ng ci rcui try. They have hi gher speed than
dynami c RAMs. Stati c RAM and dynami c RAM are al so wri tten as SRAM and DRAM respec-
ti vel y.
6.6 COMPUTER FUNDAMENTALS
Dynami c RAM bei ng cheaper i s used for mai n memory. Stati c RAM bei ng faster i s used
i n cache memory. Both stati c and dynami c RAMs use CMOS technol ogy. CMOS devi ces
consume l ess power. Stati c RAMs hol d i nformati on i n a fl i p-fl op.
Stati c RAMs hol d i nformati on i n a fl i p-fl op ci rcui t consi sti ng of two cross-coupl ed i nvert-
ers. I n a RAM the memory cel l must be associ ated wi th read and wri te faci l i ty. Si x transi stors
are needed per memory cel l i n a stati c RAM. Dynami c RAMs requi re l ess number of tran-
si stors per memory cel l because i nformati on i s stored on stray capaci tors. Onl y one transi stor
i s needed to form a memory cel l of the dynami c RAM. Thi s resul ts i n hi gh packi ng densi ty
of the dynami c RAM compared to stati c RAM.
EDO (Extended Data Output) RAM. I n an EDO RAM any memory access (i ncl udi ng
refresh) stores 256 bytes of data i nto l atches. The l atches hol d next 256 bytes of i nformati on,
so that i n most programs whi ch are sequenti al l y executed, the data are avai l abl e wi thout wai t
states.
SDRAM(Synchronous DRAM) and SGRAM (Synchronous Graphics RAM). These
RAM chi ps use the same cl ock rate as the CPU uses. As a resul t the memory chi ps remai n
ready to transfer data when the CPU expects them to be ready. They run at the processor-
memory bus wi thout i mposi ng wai t states. SDRAM i s mai nstream mass memory choi ce, and
WRAM or SGRAM the hi gh-end graphi cs memory choi ce.
DDR SDRAM. The abbrevi ati on DDR i s for doubl e data rate. SDRAM transfers data
onl y on the ri si ng edge of the cl ock, whereas the DDR SDRAM transfers data on both edges
of the cl ock. Thi s resul ts i n doubl e data transfer rate. I mproved versi ons of DDR are DDR2
and DDR3. The data transfer rate of DDR3 i s 1066 mbps. DDR SDRAM has been devel oped
by the company Samsung. The company Rambus has devel oped XDR RAM (eXtreme Data
Rate dynami c RAM).
RDRAM (Rambus DRAM). I t i s the fastest semi conductor memory avai l abl e, 1.6 GB/
S. Rambus DRAM (RDRAM) I Cs have been devel oped by the company Rambus. Several
RDRAMs are connected through a speci al bus i nterface.
Dual-Ported DRAM. Thi s type of RAM al l ows to access two memory l ocati ons si mul -
taneousl y. I t has been provi ded wi th two ports for readi ng data. Someti mes, i t i s al so cal l ed
vi deo RAM (or VRAM). WRAM (WI NDOWS RAM) i s a speci al versi on of VRAM whi ch i s
opti mi zed for the types of access whi ch are common i n PCs runni ng WI NDOWS and WI N-
DOWS appl i cati ons.
SIMM and DIMM. They stand for Si ngl e I nl i ne and Doubl e I nl i ne Memory Modul es.
These are smal l pri nted ci rcui t cards, on whi ch several DRAM memory chi ps are pl aced. Such
cards are pl ugged i nto the system board of the computer. The SI MM ci rcui t cards contai n
several memory chi ps wi th contacts pl aced on onl y one edge of the pri nted ci rcui t card. The
compl ete modul e i s organi zed as a byte-wi de memory modul e. I n DI MM ci rcui t cards memory
chi ps and contacts are pl aced on both edges of the pri nted ci rcui t card.
Bit, Nibble and Byte-Oriented Memory Chips
The capaci ti es of memory chi ps are gi ven i n the form of m n bi ts. For exampl e, the
capaci ty of a RAM i s 256 M 1 bi ts, i t means that i ts each bi t can be addressed i ndi vi dual l y.
One bi t can be read from or wri tten i nto the memory at a ti me. Such a memory i s cal l ed
bit-oriented memory. I n a nibble-oriented memory four bi ts i .e., a ni bbl e, are read from
or wri tten i nto the memory at a ti me. Each ni bbl e of data can be addressed i ndi vi dual l y. The
rati ng of ni bbl e-ori ented memory chi p i s gi ven as K (or M) 4 bi ts, exampl e 256 K 4 bi ts.
MEMORY 6.7
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I n a byte-oriented memory a byte of data can be read from or wri tten i nto the memory at
a ti me. Each byte of data can be addressed i ndi vi dual l y. Exampl e i s 4M 8 bi ts. I f a pari ty
bi t i s used, the rati ng i s gi ven as 4M 9 bi ts; 8 bi ts are for data and 1 bi t for pari ty.
The memory system of a processor uses a number of memory banks i n i ts memory
system. Each bank i s byte-ori ented. The Penti um processor has 32 address l i nes, whi ch can
address up to 4GB of memory. I t contai ns 64 data l i nes, and hence i ts memory system
empl oys 8 numbers of byte-ori ented memory banks of DRAM chi ps (whi ch may be arranged
i n SI MM or DI MM). The capaci ty of each bank i s 512 MB. The total memory capaci ty i s
4 GB. The Penti um Pro has 36 address l i nes whi ch can di rectl y address up to 64 GB of
memory. I t has 64 data l i nes, and hence, i ts memory system al so empl oys 8 numbers of byte-
ori ented memory banks. The capaci ty of each bank i s 4 GB. Total memory capaci ty i s 64 GB.
6.4.2 ROM
ROM stands for Read Onl y Memory. I t i s nonvol ati l e memory, i .e., the i nformati on
stored i n i t i s not l ost even i f the power suppl y goes off. I t i s used for permanent storage of
i nformati on. I t al so possesses random access property. ROMs are much cheaper compared to
RAMs when produced i n l arge vol umes. The stored i nformati on can onl y be read from ROMs
at the ti me of operati on. I nformati on can not be wri tten i nto a ROM by the users/program-
mers. I n other words ROMs are not accessi bl e to users. The contents of ROMs are deci ded
by the manufacturers. The contents are permanentl y stored i n a ROM at the ti me of manu-
facture. From programmi ng mode poi nt of vi ew the ROMs are pl aced i n broad categori es:
masked-programmed and user-programmed. ROMs i n whi ch contents are wri tten at the ti me
of I C manufacture are cal l ed mask-programmed ROMs. PROM, EPROM, E
2
PROM or any
other ki nd of PROM are user-programmabl e ROMs. I f we si mpl y wri te or say ROM i t means
masked programmed ROM because user programmabl e ROMs are cal l ed PROM, EPROM,
EEPROM etc.
ROMs store i nformati on whi ch i s not subject to change. They store fi xed programs. I n
mi croprocessor-based systems whi ch are used for i ndustri al control s, ROMs store moni tor,
assembl er, debuggi ng package, functi on tabl es such as si ne, cosi ne, l ogari thm, square root,
exponenti al and code conversi on tabl es, etc. An exampl e of a ROM i s Toshi ba Mask ROM, TCS
534000, 512 K 8 bi ts.
6.4.3 PROM
PROM i s a programmabl e ROM. I ts contents are deci ded by the user. The user can store
permanent programs, data or any other ki nd of i nformati on i n a PROM. A speci al equi pment
cal l ed PROM programmer i s avai l abl e for the programmi ng of PROMs. Wi th the hel p of
PROM programmer the user stores hi s programs i n a PROM. PROMs are once program-
mabl e, i .e., the user can wri te hi s i nformati on i n a PROM onl y once. PROMs are more cost
effecti ve i f smal l number of chi ps are to be produced to store certai n fi xed programs. An
exampl e of PROM i s 74S287.
6.4.4 EPROM
An EPROM i s an erasabl e PROM. The stored data i n EPROMs can be erased by exposi ng
i t to hi gh i ntensi ty short wave ul travi ol et l i ght for about 20 mi nutes. An UV source of 2537
wavel ength can be used for the purpose. The techni que of erasi ng contents i s not easy and
conveni ent because the EPROM I C has to be removed from the computer for the exposure
to the ul travi ol et l i ght. When an EPROM i s exposed to ul travi ol et l i ght the enti re data are
6.8 COMPUTER FUNDAMENTALS
erased. The user cannot erase the contents of certai n sel ected memory l ocati ons. EPROMs
are cheap, rel i abl e and hence they can be used.
EPROMs are used to store programs whi ch are permanent but need updati ng. The
permanent programs whi ch are at the research and devel opment stage al so need to be stored
i n EPROM because they are modi fi ed several ti mes. Where updati ng or changes i n the
programs at the devel opment stages are requi red, EPROMs are far more economi cal than
PROMs because they can be reused.
EPROMs empl oy MOS technol ogy. They store 1 or 0 as the charge or no charge on the
i nsul ated fl oati ng-gate of the transi stor. The UV l i ght causes the stored charge to l eak off.
Thus the data are erased and i t al l ows the user to reprogram the EPROM. For programmi ng
i t requi res hi gh vol tage, 30 V or hi gher. But i ts operati ng vol tage, i .e., the vol tage for read
operati on i s onl y 5 V.
Exampl es of EPROMS are: I ntel s 87C257, 256K (32K 8) CHMOS EPROM; I ntel s
27C010, 1M (128K 8) Byte-wi de Hi gh-speed CMOS EPROMs; .Toshi ba, TC571000, 128
K 8 EPROM. I ntel produces EPROMs i n the range of 16K to 4M bi t. I ntel 27C040 i s a 4M
(512 K 8) CHMOS EPROM and 27C240 i s a 4M(256 K 16) CHMOS EPROM.
6.4.5 EEPROM (or E
2
PROM)
EEPROM i s an el ectri cal l y erasabl e PROM. I t i s al so known as EAPROM (El ectri cal l y
Al terabl e PROM). The chi p can be erased and reprogrammed on the board easi l y on a byte
by byte basi s. Ei ther a si ngl e byte or the enti re chi p can be erased i n one operati on. I t
requi res much shorter ti me, a few mi l l i seconds for erasi ng as compared to 1020 mi nutes for
EPROM. There i s a l i mi t on the number of ti mes the EEPROMs can be reprogrammed,
usual l y 10,000 ti mes. I t need not be removed from the computers board for erasi ng. Com-
pared to RAMs E
2
PROMs take much l onger ti me for both wri ti ng and erasi ng a byte. But the
access ti me for readi ng RAMs, ROMs, PROMs and EEPROMs are comparabl e.
I ntel 2816A i s a 16K (2K 8) EEPROM. The access ti me for i ts vari ous versi ons l i es i n
the range of 200 ns450 ns. Any byte can be erased i n 9 mi l l i seconds wi thout affecti ng the
data i n any other byte. Al ternati vel y, the enti re memory can be erased i n 9 mi l l i seconds. I t
takes 915 ms for wri ti ng a byte. The I ntel s 2817A i s al so an 16K (2K 8) E
2
PROM. I t
possesses automati c byte-erase faci l i ty before wri te operati on. I t takes 20 mi l l i seconds for a
combi ned erase/wri te operati on.
E
2
PROM requi res 21 vol t pul ses for wri ti ng or erasi ng and 5 V for read operati on. Some
EEPROM chi ps requi re external hi gh vol tage pul se for erase/wri te operati on, for exampl e
I ntel 2816. But some do not requi re because hi gh vol tage pul ses for erasi ng and wri ti ng are
generated by on-chi p ci rcui try, for exampl e, I ntel 2816A.
6.4.6 Flash Memory
I t i s el ectri cal l y erasabl e and programmabl e permanent type memory. Unl i ke EEPROM,
the fl ash memory uses one transi stor memory cel l resul ti ng i n hi gh-packi ng densi ty, l ow
power consumpti on, l ower cost and hi gher rel i abi l i ty. I ts enti re contents can be erased i n one
operati on. I t i s not byte by byte al terabl e l i ke EEPROM. Some new fl ash memory chi ps
provi de bl ock erasure of i ts contents. I t can be erased and reprogrammed on the system board
i tsel f. I t has the feature of qui ck pul se programmi ng. The enti re uni t or the enti re bl ock i s
erased and reprogrammed as a whol e at a ti me. The name Fl ash Memory has been gi ven
due to fast reprogrammi ng capabi l i ty. I t i s sui tabl e for stori ng fi rmware (codes) whereas
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conventi onal EEPROMs are sui tabl e for stori ng parameters. When codes are updated the
enti re codes are rewri tten to avoi d errors. For updati ng fi rmware codes, fl ash memory i s
qui ck and economi cal as compared to EEPROM. I n case of parameter updati ng they are to
be rewri tten i ndi vi dual l y on-l i ne byte by byte. Hence, EEPROMS (whi ch are byte by byte
erasabl e and programmabl e) are best sui ted for parameter updati ng.
Due to l ow power consumpti on fl ash memory i s used i n battery dri ven di gi tal devi ces
such as handl ed computers, cel l phones, di gi tal cameras, MP3 pl ayers etc. Fl ash memory chi p
upto 1 Gbyte has been devel oped. I n many cases a si ngl e fl ash memory chi p may not provi de
suffi ci ent storage capaci ty. For such appl i cati ons l arger fl ash memory modul es consi sti ng of
a number of fl ash memory chi ps have been devel oped. Fl ash memory modul es upto 4 GBytes
capaci ty are avai l abl e. The modul es are avai l abl e as fl ash cards and fl ash dri ves. Fl ash cards
can be conveni entl y pl ugged i nto a sl ot. Fl ash dri ves can repl ace smal l er hard di sk dri ves i n
some appl i cati ons. They are stati c and faster but they are costl i er.
6.4.7 Nonvolatile RAM
I BM has recentl y devel oped a magneto-resi sti ve nonvol ati l e RAM. I t uses magneti zati on
to store i nformati on. The capaci ty of the fi rst magneto-resi sti ve RAM (MRAM) whi ch was a
prototype uni t, was 16 Mbi t.
6.5 MEMORY CONTROLLERS
A dynami c RAM (DRAM) requi res refreshi ng ci rui try to refresh i ts contents peri odi cal l y
every 2 mi l l i seconds or l ess. For thi s purpose I ntel and some other compani es have devel oped
DRAM control l ers to refresh several DRAMs i n a system. Some of them wi l l be descri bed i n
thi s secti on. Chi psets whi ch are used to i nterface memory and I /O devi ces, contai n memory
control l ers. Al so, some recent processors contai n memory control l ers on the processor chi p
i tsel f. Error detecti on and correcti on uni t has al so been descri bed.
6.5.1 Intel 8203
The I ntel 8203 i s 64K DRAM control l er. I t i s a 40 pi n I C; uses +5 V suppl y. I t provi des
al l si gnal s requi red to control 64K or 16K DRAMs i n a mi crocomputer system. I t i s capabl e
of di rectl y addressi ng and dri vi ng up to 64 devi ces wi thout external dri vers. I t provi des
mul ti pl exed addresses, address strobes, refresh l ogi c and refresh/access arbi trati on. I t i s ful l y
compati bl e wi th 8080A, 8085A, I ntel 8088 and I ntel 8086 fami l y of mi croprocessors. I t contai ns
refresh ti mer and refresh counter. I t has two modes of operati on; one for 64K DRAM and the
other for 16K DRAM.
The 8203 can accept the fol l owi ng two types of memory read requests:
1. Normal read vi a RD i nput.
2. Advanced read, empl oyi ng S
1
and ALE i nputs (the advanced read capabi l i ty i s onl y
for 16K mode).
The advanced read cycl es are requested by pul si ng ALE when S
1
i s acti ve (hi gh). I f S
1
i s i nacti ve (l ow), ALE i s i gnored.
The user can sel ect the desi red read request.
Refresh Cycle: Refresh cycl es can be started ei ther i nternal l y or external l y. An on-chi p
refresh ti mer generates i nternal refresh. The REFRQ i nput i s used for external refresh.
6.10 COMPUTER FUNDAMENTALS
6.5.2 Intel 8207
The 8207 i s a dual -port DRAM control l er. I t can i nterface 16K, 64K and 256K DRAMs.
I t i s a 68-pi n I C. I t can di rectl y address and dri ve up to 2 MB wi thout external dri vers. A dual -
port i nterface permi ts two di fferent buses to access memory i ndependentl y. When used wi th
error detecti on and correcti on uni t (EDCU), 8206, i t provi des the necessary l ogi c to di rectl y
control 8206. Thi s hel ps desi gni ng of a l arge error-corrected memory. The combi nati on of
8206 and 8207 provi des automati c memory i ni ti al i zati on and memory error scrubbi ng (cor-
recti ng errors i n memory duri ng refresh). When a correctabl e error i s detected duri ng
refresh, the RAM refresh cycl e i s l engthened sl i ghtl y to al l ow 8206 to correct error and for
the corrected word to be wri tten i nto the memory. I f uncorrected errors are detected duri ng
scrubbi ng, they are i gnored. The 8207 i s capabl e of i nterfaci ng fast or sl ow RAMs. I ts i nternal
ti mi ngs are adjusted and opti mi zed as programmed ei ther for fast or sl ow RAMs.
6.5.3 Intel 82C08
The 82C08 i s a CHMOS DRAM control l er. I t i s avai l abl e i n 48 pi n pl asti c DI P or 68 pi n
PLCC. I t can i nterface 64K and 256K DRAMs to I ntel and other mi croprocessors. I t can
di rectl y address up to 1 MB wi thout external dri vers. I n case of power fai l ure the 82C08 i s
capabl e of performi ng the task of memory refreshi ng empl oyi ng battery backup. The power
fai l ure i s to be detected by some other devi ce and a si gnal i s to be sent to 82C08. A cl ock
for the operati on of 82C08 i s to be suppl i ed by the system duri ng power fai l ure.
The status si gnal s of the CPU are connected to the control si gnal s of 82C08. The 82C08
decodes-these si gnal s recei ved from the CPU and produces read and wri te si gnal s i t requi res.
Most of the ti me CPUs wi l l be abl e to read a byte or word from DRAMs wi thout any WAI T
states bei ng requi red. I f the 82C08 happens to be i n mi ddl e of a refresh cycl e when the CPU
attempts to read a DRAM l ocati on, the 82C08 wi l l hol d i ts AACK si gnal hi gh and force the
CPU to i nsert a WAI T state. I n such a si tuati on the CPU has to wai t one cycl e whi l e the
82C08 i s compl eti ng i ts refresh cycl e before i t can access the DRAM.
6.5.4 Error Detection and Correction in RAMs
One of the sources of errors i s a noi se pul se. I n case of DRAM al pha parti cl es and some
other radi ati ons al so cause errors. Such radi ati ons cause charge on the ti ny capaci tors to
change. These charges on ti ny capaci tors i n DRAM represent data. I n l arge memory chances
of errors are more.
One si mpl est techni que of error detecti on i s to use pari ty bi t. When data i s wri tten, the
pari ty of a data word i s determi ned. A pari ty bi t i s generated such that the overal l pari ty of
the data bi ts pl us the pari ty bi t i s al ways odd. The generated pari ty bi t i s al so wri tten i n.
When the data word and the pari ty bi t are read out, the pari ty i s checked. I f the pari ty of
the resul t i s not odd, i t means that there i s somewhere an error. The drawback of the si mpl e
pari ty check i s that two errors may cancel each other. Another drawback of the si mpl e pari ty
checki ng i s that i t does not i ndi cate whi ch bi t of the data word i s i ncorrect. More compl ex
error detecti ng/correcti ng codes are used i n detecti ng and correcti ng errors i n RAMs. One of
such codes i s Hammi ng code. I t can detect si ngl e-bi t and mul ti pl e-bi t errors and correct at
l east si ngl e-bi t errors.
When the data word i s wri tten to the memory the several encodi ng bi ts are generated
by the error detecti ng and correcti ng ci rcui try. The encodi ng bi ts are al so stored i n the
memory. I n case of Hammi ng codes the encodi ng bi ts for di fferent data bi ts are di fferent as
shown in Tabl e 6.1.
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Table 6.1 Encoding Bits
Data Word Bits Number of Encoding Bits
8 5
16 6
32 7
64 8
80 8
The encodi ng bi ts are not si mpl y pl aced at the one end of the data bi t. They are
i nterspersed i n the data word. When data words are read from the memory, the encodi ng bi ts
for the read out data word are recal cul ated by the detecti ng and correcti ng ci rcui try. These
encodi ng bi ts are excl usi ve-NORed wi th the encodi ng bi ts whi ch were stored i n the memory.
The word obtai ned from thi s operati on i s cal l ed syndrome word. The val ue of the syndrome
word tel l s whi ch bi t i s i ncorrect i n the data word. The correcti on i s made by si mpl y i nverti ng
the i ncorrect bi t. There are several di fferent schemes for thi s purpose from hardware cost
consi derati on. Several I Cs are avai l abl e for automati c detecti on and correcti on, such as I ntel
8206 etc.
Intel 8206
The I ntel 8206 i s an error detecti on and correcti on uni t. I t i s bui l t i n 68-pi n gri d array
package. I t uses +5 V si ngl e suppl y. I t i s a hi gh speed devi ce and uses HMOS technol ogy. I t
provi des error detecti on and correcti on for stati c and dynami c RAMs. I t can detect and correct
al l si ngl e bi t errors. I t i s al so capabl e of detecti ng al l doubl e bi t and hi gher mul ti pl e bi t errors.
I t i nterprets odd mul ti pl e bi t errors as si ngl e bi t errors, for exampl e 5-bi t error. I t i nterprets
even mul ti pl e bi t errors (e.g. 4-bi t error) as no error, but detects most of them as doubl e bi t
error. The 8206-1 takes 35 ns for error detecti on and 67 ns for correcti on. The 8206 uses
modi fi ed Hammi ng code for error detecti on and correcti on. I t i s abl e to handl e 8 or 16 data
bi ts and 8 check bi ts. Detecti on and correcti on can be provi ded up to 80 bi t of data usi ng 8206
i n cascaded connecti on. I ts other features are: abi l i ty to handl e bytes wri tes, memory i ni ti al -
i zati on and error l oggi ng. I t supports read wi th and wi thout correcti on, wri tes, parti al (bytes)
wri te and readmodi fy-wri tes.
6.6 MAGNETIC MEMORY
Magneti c memory i s a permanent type memory. I t i s not vol ati l e. I t i s used as secondary
and backup memory. Di gi tal data 1 or 0 i s stored on the magneti c coati ng (fi l m) appl yi ng
el ectri c pul ses of sui tabl e pol ari ty to the magneti zi ng coi l of a wri te head. Fi g 6.2 shows a
read/wri te head. The bi nary di gi t 1 or 0 depends on the di recti on of magneti zati on of a very
smal l area of the magneti c fi l m, whi ch comes under the wri te head. There are two techni ques
of data recordi ng: l ongi tudi nal recordi ng and verti cal recordi ng. I n the l ongi tudi nal recordi ng
the magneti c regi ons are ori ented paral l el to the di sk surface al ong the track. I n the verti cal
recordi ng the magneti zed regi ons are verti cal to the di sk surface. The verti cal recordi ng
stores many ti mes more data as compared to l ongi tudi nal recordi ng. To read data a separate
read head, posi ti oned for the conveni ence cl ose to the wri te head, i s used. The read head i s
a magnetoresi sti ve (MR) sensor. The el ectri cal resi stance of the magnetoresi sti ve materi al
depends on the di recti on of magneti zati on of the medi um movi ng under i t. By passi ng current
through the MR sensor, resi stance changes are detected as vol tage si gnal s for read operati on.
6.12 COMPUTER FUNDAMENTALS
I n l ow-capaci ty di sks and ol der hard di sks a si ngl e wri te/read head i s empl oyed. I n other
words the same head acts as a wri te head duri ng wri te operati on, and as a read head duri ng
read operati on. I n case of si ngl e head system, duri ng read operati on, the movement of the
magneti c fi el d rel ati ve to the coi l of the head, produces el ectri c pul ses across the coi l . The
pol ari ty of the pul ses depends the di recti on of magneti zati on of a very smal l area of the
magneti c fi l m whi ch was created whi l e recordi ng the i nformati on i n terms of 1s and 0s. The
pul ses produced across the coi l are uti l i zed for read operati on.
Fig. 6.2 Read/Wri te head for a magneti c di sk.
A modern computer uses the fol l owi ng types of magneti c memory:
(i) Magneti c Di sks : Hard di sks and fl oppy di sks,
(ii) Magneti c tapes.
6.6.1 Magnetic Disks
Magneti c di sks i ncl ude hard di sks and fl oppy di sks. Worki ng pri nci pl e i s same for both
hard di sks and fl oppy di sks. A magneti c di sk i s a surface devi ce. I t stores data on i ts surface.
I ts surface i s di vi ded i nto ci rcul ar concentri c tracks, and each track i s di vi ded i nto sectors,
as shown i n Fi g. 6.3. I n the confi gurati on of a magneti c di sk as shown i n Fi g. 6.3 (a), al l
tracks have same number of sectors. The number of bytes stored i n each sector i s kept same.
Therefore, al l tracks store the same amount of data. Thi s resul ts hi gher bi t densi ty i n i nner
tracks than that of the outer tracks. Si nce the same number of bytes i s stored i n each sector,
the si ze of the i nner sectors deci des the storage capaci ty for al l other sectors on the di sk. Due
to thi s reason some storage space remai ns unused on the outer tracks. To uti l i ze thi s unused
space, the di sk surface i s di vi ded i nto zones. I n a zone the number of sectors i n each track
i s same, but i t i s di fferent than the number of sectors i n a track of the other zone. I n outer
zones the number of sectors per track i s more than that i n i nner zones, as shown i n Fi g.
6.3(b). Thus storage capaci ty of the di sk i s i ncreased by thi s techni que.
Magneti c di sks are semi random devi ces. A track on a di sk i s sel ected i n random fashi on,
but data i s wri tten to or read from a sector i n seri al fashi on. The di sks are mounted on a
rotary dri ve (D.C. motor) to rotate the di sk. After the read/wri te head i s moved to the
addressed track, i t remai ns stati onary whi l e the di sk rotates to bri ng the starti ng posi ti on of
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the addressed sector under the read/wri te head. Afterwards, the di sk conti nues to rotate, and
i nformati on i s read from or wri tten to the addressed sector. The ti me requi red to move the
read/wri te head to the addressed sector i s known as access time. Access ti me i s the sum of
seek time and latency time. The ti me requi red to move the read/wri te head to the addressed
track i s cal l ed seek ti me. The l atency ti me (or search ti me) i s the ti me requi red to bri ng the
starti ng posi ti on of the addressed sector under the read/wri te head.
Disk Controller. Magneti c di sk dri ves requi re control l er. The control l er converts i n-
structi ons recei ved from software to el ectri cal si gnal s to operate di sks. The functi ons of a di sk
control l er are:
(i) To i nterface a di sk dri ve system to the CPU.
(ii) Di sk dri ve sel ecti on, because a computer uses more than one di sk dri ve.
(iii) Track and sector sel ecti on.
(iv) To i ssue commands to the di sk dri ve system to perform read/wri te operati on.
(v) Data separati on.
(vi) Seri al -to-paral l el and paral l el -to-seri al conversi on.
(vii) Error detecti on, etc.
Fig. 6.3 Tracks and Sectors (a) Al l tracks have same number of sectors
(b) Outer tracks have more sectors than i nner tracks.
Data processed by the CPU or stored i n the mai n memory i s i n the byte form. The bytes
to be stored on a magneti c di sk must be converted i nto seri al format. Data read from a
magneti c di sk i s i n the seri al format, whi ch has to be converted to paral l el format so that
i t can be sent to the CPU for processi ng or to the mai n memory for storage. Data recorded
on a magneti c di sk i s combi ned wi th ti mi ng si gnal (i t i s done for encodi ng purpose). There-
fore, data read from a magneti c di sk must be separated from the ti mi ng si gnal (i.e., cl ock).
Hard di sk control l er and fl oppy di sk control l er are avai l abl e i n I C form. A few of them wi l l
be descri bed l ater on i n thi s chapter.
6.14 COMPUTER FUNDAMENTALS
6.6.2 Hard Disk
Hard di sks are on-l i ne storage devi ces. The term on-l i ne means that the devi ce (hard
di sks) i s permanentl y connected to the computer system. When computer i s on, the devi ce
(hard di sks) i s avai l abl e to store i nformati on or to gi ve i nformati on. Hard di sks are used as
secondary memory for mass (bul k) storage of i nformati on permanentl y. They store programs,
data, operati ng system, compi l ers, assembl ers, appl i cati on programs, database, etc.
A hard di sk i s made of al umi ni um (or other metal or metal al l oy) wi th a thi n coati ng
of magneti c materi al (i ron oxi de) over i t. Standard si ze of hard di sks i s 3.5 i nch. The 2.5 i nch
di sks are used i n portabl e computers. Hard di sks and read/wri te heads are kept i n a seal ed,
ai r fi l tered encl osure. Thi s techni que i s known as Winchester techni que. Hard di sks to-
gether wi th read/wri te heads, access mechani sm and dri vi ng motor consti tute an uni t cal l ed
hard disk drive uni t. The whol e uni t i s fi xed. I t i s not removabl e. A hard di sk i s al so cal l ed
a platter. I t cannot be removed or i nserted i nto a hard di sk dri ve uni t. Hard di sk dri ve uni t
under di scussi on i s of l arge capaci ty, and i s used as secondary memory. Recentl y removabl e
hard di sks and external hard di sks of smal l er capaci ty for backup memory have al so been
devel oped, whi ch wi l l be di scussed l ater on.
To i ncrease the storage capaci ty several hard di sks (pl atters) are mounted on common
dri ve to consti tute a di sk pack, as shown i n Fi g. 6.4. The set of al l tracks at the same di stance
from the spi ndl e on the recordabl e surfaces of the di sk pack wi l l l i e on the surface of an
i magi nary cylinder. Al l the tracks whi ch l i e on a cyl i nder have same number. For exampl e,
track-10 of each recordabl e surface of the pack wi l l l i e on the cyl i nder whi ch i s numbered as
cyl i nder-10. The di sks are addressed by dri ve number (because more than one dri ves are
used i n a computer), cyl i nder number (i.e., track number), surface number and sector number.
Fig. 6.4 Hard di sk pack.
Speed and Capacity. A fl oppy di sk stretch and swel l wi th changes i n termperature and
humi di ty. Hard di sks do not or at l east they do not as much. Due to thi s fact the read/wri te
heads used for hard di sk are much smal l er as compared to those for fl oppy di sks. Thi s al l ows
more tracks and sectors on a hard di sk resul ti ng i n more storage capaci ty. A hard di sk uses
MEMORY 6.15
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several thousand tracks per surface and hundreds of sectors per track. The capaci ty of hard
di sk dri ves whi ch are used i n notebooks, desktop, workstati on and servers vari es i n the range
of 40 GB = 750 GB. 1 GB = 1 Gi ga bytes = 2
30
bytes. The access ti me i s i n the range of 5
ms10 ms (mi l l i second). The capaci ty of si ngl e a di sk upto 133 GB i s possi bl e. A 400 GB hard
dri ve of Seagate company uses onl y 3 di sks. The speed of hard di sks vari es from 5400 rpm
to 15000 rpm. The l arge capaci ty di sk dri ves provi de SATA (seri al ATA) i nterface. Seagates
500 GB hard di sk dri ve provi des SATA i nterface havi ng 3 GB/s data transfer rate. The hard
di sk dri ves of smal l er capaci ty (1 GB5 GB) are al so avai l abl e for smal l er system. Such
mi crodri ves are used as external dri ve. They are connected to the computer through USB 2.0
i nterface. The di ameter of mi cro hard di sks may be of 1 i nch to 2.5 i nch, dependi ng upon thei r
capaci ty. Mi cro dri ves are al so used i n some di gi tal equi pment. Recentl y, 2.5 i nch hard di sk
dri ves of 40 GB, 80 GB and 150 GB have al so been devel oped.
Disk Cache. Semi conductor RAM memor y i s much faster than magneti c di sk memor y.
Hence, di sk access i s much sl ower than that of the mai n memor y whi ch i s semi conductor
DRAMs. To sol ve the pr obl em of mi smatch i n data tr ansfer r ate, a semi conductor memor y,
cal l ed di sk cache i s pl aced i n between the mai n memor y and har d di sk memor y. The
capaci ty of the di sk cache i s a few megabytes. The di sk cache stor es i nfor mati on whi ch
ar e needed for the executi on of the cur r ent pr ogr am. I t enhances the per for mance of the
har d di sk dr i ve. Other mass storage devi ces may al so be provi ded wi th thi s type of cache
memor y.
RAID System. I n Redundant Arrays of I ndependent Di sks (RAI D) system mul ti pl e di sks
operate i n paral l el and store the same i nformati on. I t i mproves storage rel i abi l i ty. I t el i mi -
nates the ri sk of data l oss when one of the mul ti pl e di sk fai l s. Furthermore, a l arge fi l e i s
stored i n several di sk uni ts by breaki ng the fi l e up i nto a number of smal l er pi eces and
stori ng these pi eces on di fferent di sks. Thi s i s cal l ed data stri ppi ng. When fi l e i s accessed for
read operati on, al l di sks del i ver data i n paral l el . Thus total fi l e transfer ti me i s reduced. To
i mprove rel i abi l i ty of storage system, some i nformati on can al so be stored on addi ti onal di sk
uni ts. Such system i s economi cal on a l arge computer system.
Air Cushion between Head and Hard Disk. The hi gh speed of hard di sks creates a
thi n ai r cushi on of about 10 mi croi nch between the rotati ng di sk and the head. When di sk
i s rotati ng the head fl oats on ai r cushi on and remai ns 10 mi croi nch off the di sk surface. The
head does not make any physi cal contact wi th the di sk surface. Hard di sk must be kept i n
dust free envi ronment because the di ameter of the dust parti cl e may be as many as 10 ti mes
the thi ckness of the ai r cushi on. Any dust parti cl es or any other contami nati on present i n the
seal ed contai ner, wi l l cause the heads to crash i nto the di sks. I t i s known as head crash.
I n head crash the coati ng of the magneti c materi al on the di sk surface i s damaged where
head stri kes. The data of that porti on of di sk surface i s l ost.
Removable and External Hard Disk. Removabl e hard di sks have al so been devel -
oped. They are used as backup memory. They can use ei ther EI DE or SCSI i nterface. A
docki ng bay can be added to PC for removabl e hard di sk. The docki ng bay connects i nternal l y
to PCs power suppl y and al so to ei ther an EI DE or a SCSI host adapter. Exampl es of
removabl e hard di sks are: SyQuest syjet 1.5 GB, I omega Jaz 1 GB and 2 GB, etc. External
hard di sk dri ves of 1 GB30 GB have been devel oped, whi ch can be i nterfaced to I EEE 1394
seri al bus or USB 2.0.
IDE, SCSI, ATA and ATAPI. Actual l y, I DE and SCSI are not control l ers, rather they
ar e host adapter s. The contr ol l er s ar e bui l t i nto the dr i ve uni t i tsel f. I DE stands for
6.16 COMPUTER FUNDAMENTALS
I ntegrated Dri ve (or Devi ce) El ectroni c, and SCSI stands for Smal l Computer System I nterface.
I t i s a hi gh-speed, i ntel l i gent pathway to connect peri pheral s to the computer. I DE i s a
standard accordi ng to whi ch I DE i nterface i s made.
The enhanced I DE (EI DE) standard i s avai l abl e. I t i s al so cal l ed i mproved I DE or new
I DE. EI DE i s al most uni versal on new PCs. I t can i nterface hard di sk dri ve, fl oppy di sk dri ve,
opti cal di sk dri ve and tape dri ve. I t provi des up to four channel s. Two EI DE devi ces can be
connected to each channel . Thus a total of up to 8 EI DE devi ces can be i nterfaced to a PC.
No commerci al motherboards support more than two channel s, but one can add pl ug-i n cards
on the I SA bus to support one or two addi ti onal channel s. I DE or EI DE dri ves offer great ease
of use, one can just pl ug them i n to work.
A PC motherboard has two connectors for EI DE i nterface, as shown i n Fi g 6.5. From
each connector one fl at cabl e runs to provi de an EI DE channel . Two devi ces can be connected
to each channel . For each pai r of devi ces on the same cabl e, one i s set as a master devi ce
and the other as a sl ave devi ce. I t dose not matter whi ch one (master or sl ave) i s at the end
of the cabl e.
Fig. 6.5 EI DE i nterface.
ATA and ATAPI are al so the names of standards. ATA is AT Attachment, and ATAPI i s
AT Attachment Packet I nterface. ATAPI is an extension of ATA. ATA and ATAPI are specifications
for EI DE. These are publ i shed by Smal l Form Factor (SFF) Commi ttee. Data transfer rate
of I DE or EI DE i s much l ess than that of SCSI . A typi cal val ue i s 5.5 MB/s.
SCSI. I t i s an i ntel l i gent adapter. I t medi ates between the acti vi ty on the SCSI bus and
that on the PCs I /O bus. SCSI has a separate I /O bus cal l ed SCSI bus. Some PCs have SCSI
host adapters bui l t i nto thei r motherboards, but much more common practi ce i s to use an
opti onal ci rcui try on a pl ug-i n card. As the data transfer rate for SCSI i nterface i s hi gh, the
SCSI host adapter i s connected to a fast i nput/output bus. Today the most popul ar choi ce i s
PCI bus. The l atest versi on of SCSI cal l ed SCSI -3 can connect up to 15 devi ces. Each devi ce
connected to SCSI bus i s assi gned an i denti fi cati on number. The hi ghest I D (i denti fi cati on)
number i s used by the host adapter. SCSI devi ces may be hard di sk dri ve, opti cal di sk dri ve,
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ZI P dri ves, pri nter, i mage scanner, graphi cs tabl et, mouse, etc. The data transfer rate for
SCSI -3 i s 80 MB/s. Even hi gher data transfer rate can be achi eved usi ng opti cal fi ber l i nk.
Western Di gi tal has announced ULTRA 160 SCSI wi th data transfer rate of 160 MB/s.
Fi g. 6.6 shows how SCSI devi ces are connected to SCSI bus (i t i s known as dai sy-chai n
connecti on). SCSI bus consi sts of 50 wi res. A fl at cabl e runs from the SCSI control l er card
to the SCSI devi ces. The cabl e i s termi nated at the end i .e., the l ast devi ce on the dai sy chai n
must have a termi nator i nstal l ed on the connector that i s not bei ng used. The SCSI control l er
sends I D number of the devi ce i t wants to communi cate.
Fig. 6.6 SCSI i nterface.
SCSI devi ces have thei r own control l ers and SCSI i nterface. The control l ers are si ngl e-
chi p mi crocomputer. Hard di sks and fl oppy di sks are very i mportant devi ces. The functi ons
of thei r control l ers have al ready been di scussed i n the Secti on 6.6.1 under the subheadi ng
Magneti c Di sk Control l ers. SCSI devi ces can be moved from a host adapter of one computer
to another, except hard di sk dri ve wi th data. I t i s treated as a new di sk. Thi s probl em i s not
there i n case of CD-ROMs, CD-R and removabl e hard di sks. I n these cases the devi ce dri ver
software whi ch supports thei r use has been provi ded wi th features needed for such move-
ment. SCSI system has hi gh rate of data transfer and i t i s a costl y system. I t i s used on
servers and other powerful computer. Desktop computers use, I DE or EI DE i nterface.
6.6.3 Floppy Disk
Fl oopy di sks are made of Myl ar (a pl asti c materi al ) coated wi th magneti c materi al (i ron
oxi de or bari um ferri te). The di sk i s not a hard pl ate, rather i t i s very thi n pi ece of fl exi bl e
pl asti c, and hence, i t i s cal l ed fl oppy di sk. Fl oppy di sks are al so cal l ed diskette. They are
removabl e di sks. A fl oppy di sk i s i nserted i nto the computer system when needed. I t i s an
i nexpensi ve storage devi ce and i t i s used as backup memory. Users al so store thei r programs,
documents and other i mportant i nformati on on fl oppy di sks. The si ze of fl oppy di sks i s 3.5
i nch di ameter. A fl oppy di sk rotates at 360 rpm. I ts average access ti me i s 150250 ms.
3.5 Inch Floppy Disks
Fi g. 6.7 shows the schemati c di agram of a 3.5 i nch fl oppy di sk. On a 3.5 i nch fl oppy di sk
the read/wri te head wi ndow i s covered wi th a sl i di ng metal cover i .e., a metal shi el d. The di sk
dri ve pushes the cover asi de when a di sk i s i nserted i nto the dri ve uni t. There i s a hol e at
the centre for the dri ve spi ndl e. There i s a wri te protect notch to protect the stored i nformati on.
6.18 COMPUTER FUNDAMENTALS
I t uses a sl i di ng pl asti c button, whi ch can sl i de to ei ther of the two posi ti ons. One posi ti on
al l ows readi ng, wri ti ng and erasi ng. The other posi ti on al l ows onl y readi ng. The button sl i des
i n a track. When l i ght i s vi si bl e through the track, then onl y the di sk i s wri te protected. The
protecti ve cover of a 3.5 i nch fl oppy i s hard pl asti c. I t i s permanentl y seal ed, and contai ns
l ubri cants and cl eani ng agents that prol ong the l i fe of the di sk. The stori ng capaci ty of a 3.5-
i nch hi gh densi ty fl oppy i s 1.44 MB. I t uses 80 tracks per surface, 135 TPI (tracks per i nch),
18 sectors per track, 360 rpm and stores 512 bytes per sector. Both si des of the di sk store
i nformati on. The data transfer rate i s about 40 KB/s. Wi th the advent of opti cal di sks, the
use of fl oppy di sks i s di mi ni shi ng day by day.
Fig. 6.7 3.5 i nch fl oppy di sk.
Cautions in Handling Floppy Disks
A fl oppy di sk shoul d al ways be kept i n a pl asti c box when i t i s not i n use. I t shoul d be
kept i n verti cal posi ti on. One shoul d not touch the exposed area of the di sk surface wi th
fi ngers. Sharp and hard-poi nt pen such as a dot pen (bal l -poi nt-pen) shoul d not be used for
wri ti ng l abel . A fel t-ti pped pen such as an art pen shoul d be used for wri ti ng l abel . Fl oppy
di sks shoul d be kept away from magneti c fi el ds such as that created by tel evi si ons, tape
recorders, el ectri c radi os, el ectri c motors, tel ephones and other el ectri cal appl i ances. Heat,
moi sture and dust al so damage fl oppy di sks, and therefore, they shoul d be kept away from
excessi ve heat produced by di rect sun or any other radi ati on. They shoul d be kept i n dust
and moi sture free envi ronment. A di sk shoul d not be removed whi l e dri ve i s runni ng. The
di sk shoul d not be bent.
Floppy Disk Controllers
The functi on of a magneti c di sk control l er has al ready been descri bed i n Secti on 6.6.1
under the subheadi ng Magneti c Di sk Control l ers. I ntel has devel oped 82078, 82077AA and
82077SL fl oppy di sk control l ers. The 82077AA, i s a CHMOS si ngl e-chi p fl oppy di sk control l er.
I t can dri ve up to four fl oppy di sks. I t can support both tape and fl oppy di sk dri ves. I t has
been provi ded wi th i ntegrated tape dri ve support. I t has capaci ty to i nterface di rectl y perpen-
di cul ar recordi ng 4 MB fl oppy dri ves. The 82077SL, i s a superset of 82077AA wi th addi ti onal
feature of power management that makes i t sui tabl e for portabl e computer. The 82078, i s an
enhanced fl oppy di sk control l er. I t supports standard 5 V as wel l l ow-vol tage 3 V system. I ts
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data transfer rate i s 2Mbps, whi ch i s doubl e of the data rate of earl i er versi ons. I t i s provi ded
wi th enhanced power management.
6.6.4 Formatting of Magnetic Disks
Magneti c di sks are speci al l y prepared before they are used fi rst ti me. The speci al prepa-
rati on i s known as formatting of the di sk. When a new bl ank di sk i s formatted the tracks
and sectors are marked on the di sk. Each sector i s numbered, goi ng round each track, from
outermost track. I n addi ti on to data, several other i nformati ons are al so recorded on the di sk
for correct data transfer between the di sk and the mai n memory. The outermost tracks
contai n di sks mai n di rectory, i nformati on about di sk space al l ocati on, etc. I n the begi nni ng
of each sector there are some bytes of i nformati on, whi ch are used by the di sk dri ve system.
These are address of the sector. I t i ndi cates where on the di sk thi s sector i s l ocated. Then
comes the data secti on of the sector, whi ch i s 512 bytes of space to record data. Each sector
has a few bytes space to record CRC val ue or ECC bytes.
6.6.5 Error Checking in Magnetic Disk Memory
When data are read from a magneti c di sk, i t i s checked whether the data are the same,
whi ch were wri tten. Error detecti ng codes are used to detect errors. The Cycl i c Redundancy
Checki ng (CRC) method i s most popul ar and wi del y used. I n thi s method al l data bytes of a
sector of a track are treated as a si ngl e l arge number. Thi s bi nary number i s di vi ded by a
constant number. The 16-bi t remai nder i s recorded as CRC bytes after the data bytes. When
data are read, the data bytes as wel l CRC bytes are read out. The CRC bytes are subtracted
from the read out data. The resul t i s di vi ded by the ori gi nal constant. I f the remai nder i s
zero, the read out data i s correct; otherwi se data read out i s not correct. I f an error i s found
i n CRC checki ng, the checki ng i s repeated a few ti mes. I n case of an error, the di sk control l er
and operati ng system decl are a fai l ure of the sector, and prevent users from usi ng damaged
data.
Fl oppy di sks use CRC techni que for error checki ng Hard di sks use ECC (Error Correc-
ti on Codes) for error detecti on and correcti on. ECC al l ows not onl y to detect errors, but al so
i ndi cates where and what the error i s. Each bi t must be ei ther 0 or 1. I f one knows exactl y
whi ch bi ts are wrong, they can be corrected by reversi ng those i ndi vi dual bi ts. Error detecti on/
correcti on i s done by the control l er.
6.6.7 Magnetic Tapes
Magneti c tapes are used for backup memory. They are sequenti al access devi ce whereas
a di sk dri ve i s a di rect access devi ce. I n di sk dri ve system the head moves to the posi ti on
of the desi red record. But i n the case of tape dri ve system, the head moves sequenti al l y. I t
has to move through the adjacent records unti l i t reaches the desi red record. However,
recentl y Exabyte company has devel oped a technol ogy usi ng whi ch the heads can read data
from the physi cal l ocati on on the tape, wi thout havi ng to fol l ow tracks from begi nni ng to end.
Thi s breakthrough gi ves a boost to rel i abi l i ty and data retri eval . The magneti c tape i s made
of fl exi bl e pol yster coated wi th magneti zabl e materi al . Tape wi dth vari es from 3 mm to 12.7
mm. Most of the tapes are avai l abl e i n cartri dge form. Tape dri ves may contai n mul ti pl e
cartri dges. The capaci ty vari es from a few hundred megabytes to a few hundred gi gabytes.
The manufacturi ng compani es are: I BM, HP, Quantum, Sony, Exabyte, etc. Some trade
names of tapes are: LTO-Ul tri um (LTO i s Li near Tape Open), DLT (Di gi tal Li near Tape), DDS
(Di gi tal Data Storage), DAT (Di gi tal Audio Tape), AI T (Advanced I ntel l i gent Tape) etc. Some
6.20 COMPUTER FUNDAMENTALS
typi cal capaci ti es are: 20 GB (40 GB compressed), 40 GB (140 GB compressed), 80 GB (160 GB
compressed), 100 GB, 200 GB, 400 GB (800 GB compressed) etc.
Modern magneti c tapes contai n a number of paral l el tracks runni ng l engthwi se. Earl i er
tapes used 9 tracks. Modern tapes use 18 or 36 tracks. A 9 track system stores 1 byte of data
on 8 tracks and a pari ty bi t on the 9th track. I n case of 18 and 36 track systems 2 bytes and
4 bytes of data and correspondi ng pari ty bi ts are stored respecti vel y. I f the recordi ng of data
on al l the tracks i s done si mul taneousl y usi ng mul ti pl e heads, i t i s cal l ed paral l el recordi ng.
But modern tape system use seri al recordi ng. A typi cal seri al recordi ng cal l ed serpenti ne
recordi ng i s used. I n thi s techni que the fi rst set of bi ts are recorded on a track l engthwi se.
When the end of the tape i s reached, the heads are reposi ti oned on the next track. Now the
recordi ng i s done i n the reverse di recti on. I n thi s way recordi ng conti nues back and fourth,
unti l the tape becomes ful l . To i ncrease the speed, readi ng/wri ti ng can be performed on a
number of adjacent tracks (typi cal l y 2 to 8 tracks) si mul taneousl y. Data are sti l l recorded
seri al l y on the i ndi vi dual tracks. But the bl ocks i n sequence are stored on the adjacent tracks,
as shown i n Fi g. 6.8.
Fig. 6.8 Bl ock Layout for a tape system to record 4 tracks si mul taneousl y.
The data on the tape i s organi zed i n the form of records separated by gaps. A gap
between two consecuti ve records i s cal l ed inter-block gap (IBG).
A hal f-i nch magneti c tape i s di vi ded i nto hori zontal rows cal l ed tracks or channel and
verti cal col umns cal l ed frames. For paral l el recordi ng a 9-track tape dri ve system i s provi ded
wi th 9 read/wri te heads. 9 bi t are wri tten/read i n a verti cal col umn si mul taneousl y. 8 bi ts are
for the bi nary code of a character and the 9th bi t i s the pari ty bi t for error checki ng. A pari ty
bi t detects onl y si ngl e-bi t errors. I t cannot detect mul ti bi t errors. To detect mul ti bi t errors
a second pari ty bi t cal l ed longitudinal parity bit i s i ntroduced. After recordi ng character
bi ts i n a number of col umns, one col umn i s used to record l ongi tudi nal pari ty bi ts. Usi ng both
verti cal and l ongi tudi nal pari ty check bi ts, both types of errors; si ngl e-bi t and mul ti -bi t errors
are detected and corrected.
When a number of records are stored i n a tape an i nterrecord gap i s provi ded between
two adjacent records. Some porti on of the tape at one end i s l eft unrecorded for threadi ng
purpose. A refl ecti ve marker cal l ed load point shows the begi nni ng of the usabl e tape. There
i s al so a si mi l ar marker at the end of the usabl e tape, known as end of reel marker. At the
begi nni ng of the tape, after the l oad poi nt marker, there i s a header control label to i denti fy
the tape contents and to store other control i nformati on. At the end of the tape there i s a
transfer control l abel , whi ch contai ns the number of records i n the fi l e. There i s al so a speci al
one-character record to si gnal the end of a fi l e. Al l these l abel s and markers are shown i n
Fi g. 6.9 (a).
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I f the records are of smal l er l engths, due to presence of i nterrecord gaps onl y a smal l
percentage of the tape i s uti l i zed. To i mprove the effi ci ency of the tape uti l i zati on a number
of records can be grouped together i n a block and bl ock i s recorded as si ngl e uni t on the tape.
There are sui tabl e programs to separate records wi thi n a bl ock for processi ng.
Fig. 6.9 Magneti c tape (a) markers and l abel s, (b) mul ti pl e record bl ock.
6.7 OPTICAL DISKS
Opti cal di sks are used for backup memory. I nformati on i s wri tten to or read from an
opti cal di sk usi ng l aser beam. I t has very hi gh stori ng capaci ty as compared to magneti c
fl oppy di sks. Wi th the advent of opti cal di sks, the use of magneti c fl oppy di sk i s di mi ni shi ng
day by day. The capaci ty of opti cal di sks vari es from 650 MB to 17 GB. DVDs of 15, 25, 30
and 50 GB capaci ty are expected soon. I t has very l ong l i fe. An opti cal di sk i s a di rect access
devi ce. I t can be randoml y accessed for musi c, vi deo, a fi l e or any other i nformati on. I t i s
costl i er than magneti c fl oppy di sk, but i t i s not expensi ve. As i ts read/wri te head does not
touch the di sk surface, there i s no di sk wear and probl em of head crash. El aborate error
checki ng codes can be used as there i s no probl em of space because of i ts hi gh storage
capaci ty. The greatest drawback of an opti cal di sk dri ve system i s i ts l arge access ti me as
compared to magneti c hard di sk dri ve. I n case of a hard di sk dri ves system the read/wri te
head i s a ti ny magnet whereas i n an opti cal di sk system the dri ve has to move on a si zabl e
opti cal assembl y across the di sk surface. Thi s resul ts i n an i ncreased access ti me. There are
the fol l owi ng types of opti cal di sks:
(i) CD (Compact Di sk) or CD-ROM
(ii) CD-R (CD Recordabl e)
(iii) CD-RW (CD-Read/Wri te)
(iv) DVD (Di gi tal Versati l e Di sk)-ROM
6.22 COMPUTER FUNDAMENTALS
(v) DVD-R
(vi) DVD-RW
The di ameter of CD di sks are 12 cms. DVDs come i n 8 cm di ameter as wel l as 12 cm
di ameter. The capaci ty of CDs may be 650 MB or 700 MB. The capaci ty of DVDs i s 4.7 GB,
8.5 GB or 17 GB. The i nformati on wri tten on opti cal di sks are stored permanentl y.
6.7.1 CD Technology
The bottom l ayer of a CD di sk i s pol ycarbonate pl asti c. I t acts as a cl ear gl ass base. The
surface of the pol ycarbonate substrate i s coated wi th a refl ecti ng materi al usual l y al umi ni um.
The al umi ni um surface i s then coated wi th a protecti ve acryl i c l ayer. Fi nal l y, there i s the
topmost l ayer to have l abel . Fi g 6.10 shows the di fferent l ayers of a CD. The CD di sk has
a si ngl e spi ral track for recordi ng data. The spi ral track can store more data as compared to
concentri c ci rcul ar tracks. To wri te i nformati on i n terms of 1s and 0s l aser beam i s used. To
wri te 1 the l aser beam i s turned on, whi ch burns a pit upto the refl ecti ng l ayer. The l aser
beam i s focussed from pol ycarbonate surface si de. The l aser source and the photodetector are
posi ti oned bel ow the pol ycarbonate pl asti c. The emi tted l aser beam travel s through the
pol ycarbonate pl asti c, refl ected back from the al umi ni um l ayer and comes back towards
photodetector. To wri te 0, the l aser beam i s not turned on and hence, no pi t i s burnt. The
surface where there i s no pi t i s cal l ed land.
Fig. 6.10 Di fferent Layers of a CD-ROM or CD
Fig. 6.11 Spi ral track of an opti cal di sk.
Fi g. 6.11 shows a spi ral track of an opti cal di sk. The track i s di vi ded i nto sectors of the
same si ze as shown i n the fi gure. The outsi de sectors near the outer edge of the di sk are of
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the same l ength as that of the i nsi de sectors. The pi ts and l ands are read by the l aser at
constant l i near vel oci ty. I n other word the i nformati on i s read at the same constant rate. An
opti cal di sk i s rotated at a vari abl e rotati onal speed so that pi ts/l ands are read by the l aser beam
at constant l i near speed. The di sk rotates more sl owl y near the outer edge than near the center.
6.7.2 CD-ROM and Audio CD
From audi o CD and CD-ROM prerecorded i nformati on are read out. Both use si mi l ar
technol ogy. I f CD stores di gi tal audi o and vi deo data, some errors i n data can be tol erated
because they are unl i kel y to affect the reproduced sound and i mage i n a percepti bl e way. But
i f a CD stores data for computer appl i cati ons, errors are not acceptabl e. Therefore, CD meant
for computer appl i cati ons store addi ti onal bi ts al so, for error detecti on and correcti on. CD-
ROM pl ayers/computers al so have to store error detecti on and correcti on programs. CD whi ch
stores computer data are cal l ed CD-ROM. The CDs whi ch are used for audi o/vi deo are cal l ed
audi o CD/vi deo CD.
The capaci ty of a CD-ROM i s 650 MB, di ameter 5.25 i nch and speed 360 r.p.m. I ts data
transfer rate i s nx, where x = 150 KB/S and n i s a factor. I f a CD-ROM has speci fi ed speed
52x, i ts data transfer rate i s 52 150 KB/S = 7.8 MB/S. 650 MB can store about 3 l acs pages
of pri nted text. A 650 MB audi o CD can store musi c of 75 mi nutes. CD-ROMs are wi del y used
for appl i cati on programs, l arge texts, vi deo games, di stri buti on of softwares, data bases, etc.
To wri te data on CDs, hi gh-i ntensi ty l aser i s used whereas to read data, l aser beam of
l ess i ntensi ty i s empl oyed. CDs are mass manufactured. I nformati on on read-onl y CDs are
recorded at the ti me of manufacture. Data are recorded usi ng hi gh-power l aser beam and a
master di sk i s prepared. Then a di e i s made from the master di sk. From the di e copi es of
the master di sk are produced on mass scal e.
6.7.3 CD-R (CD-Recordable)
CD-R i s used when a si ngl e copy or a few copi es of a set of data i s needed. I t i s a wri te-
once read-many ti mes (WORM) type CD. The user can wri te data on CD-R onl y once, as i t i s
done i n case of a semi conductor PROM. A CD-R has a spi ral track on the di sk. There i s a
photosensi ti ve organi c dye on the track. To write 1s, l aser beam i s focused to create pi ts i nto
the organi c dye on the track. To write 0s, the l aser beam i s not turned on. I n thi s case l and
i s formed. CD-R i s used for the storage of documents and fi l es. The wri tten data are stored
permanentl y. Di fferent l ayers of a CD-R are shown i n Fi g. 6.12. The stori ng capaci ty i s 700 MB.
Fig. 6.12 Di fferent Layers of a CD-R
6.24 COMPUTER FUNDAMENTALS
6.7.4 CD-RW (CD-Rewritable)
CD-RW i s a read/wri te opti cal di sk. The user can erase the recorded data of a CD-RW
and rewri te new data i n that space. The capaci ty of a CD-RW i s 700 MB. Now peopl e use CD-
RW i nstead of magneti c fl oppy di sk as i t has hi gh storage capaci ty, more rel i abl e and has
l onger l i fe. The constr ucti on of a CD-RW opti cal di sk i s si mi l ar to the that of a
CD-R. I nstead of an organi c dye i n the recordi ng l ayer the CD-RW contai ns an al l oy of si l ver,
i ndi um, anti mony and tel l uri um. Thi s al l oy has two states: crystal l i ne state and amorphous
(non-crystal l i ne) state. The crystal l i ne state al l ows l i ght to pass through i t. The amorphous
state absorbs l i ght. Usi ng l aser beam the structure of the al l oy materi al can be changed from
one state to another. Thi s technol ogy i s cal l ed phase change technology. I n normal state
the al l oy has crystal l i ne nature. When the al l oy i s heated above 500 degree C usi ng hi gh-
power l aser beam and then cool ed down, the al l oy becomes amorphous. Thi s state refl ects
l i ght poorly and corresponds to a pit to represent bit 1. The Crystalline state represents 0 bit.
To erase data, the alloy is heated to about 200 degree C and this temperature is maintained for
an extended period. This process is called annealing. The annealing process brings amorphous
material back to crystalline state. The CD-RW drive employs laser beam of three different power.
A high-power laser beam is used to record pits to represent 1s. The middle-power laser beam is
used to erase data and to bring material back to crystalline state. A low-power laser beam is used
to read information from the disk. A CD-RW drive is also capable to read CD-ROM and read/write
CD-R. The CD-RW drives provide EI DE, SCSI and USB interface. With the advent of CD-RW, the
use of magnetic floppy disk is diminishing day by day. CD-RWs are used for backup purposes.
As CD-RWs have made CD-Rs l ess i mportant as they are superi or to CD-Rs.
6.7.5 DVD (Digital Versatile Disks)
DVDs have much more storage capaci ty as compared to CDs. They use l aser beam of
shorter wavel ength as compared to the wavel ength of l aser beam used i n CDs. Pi ts i n DVDs
are much smal l er and tracks are pl aced cl oser together. Thi s gi ves 4.7 GB storage capaci ty
for a si ngl e l ayer si ngl e si ded DVD. Doubl e l ayer si ngl e si ded di sk has a capaci ty of 8.5 GB
and doubl e l ayer doubl e si ded di sks have capaci ty 17 GB.
The structure of a si ngl e l ayer si ngl e si ded DVD i s al most the same as that for a CD-
ROM shown i n Fi g. 6.10. The data transfer rate of DVDs i s nx, where x = 1.38 MB/S and n
i s a factor. The access ti me of DVDs i s al so l ow and si mi l ar to CDs. But the data transfer
rate i s much hi gher than that of CDs, because of hi gher densi ty of pi ts.
Fig. 6.13 Dual Layer DVD
Fi g. 6.13 shows a dual l ayer DVD. I n dual l ayer di sk, the fi rst l ayer contai ns a trans-
l ucent materi al (semi refl ector) i nstead of al umi ni um refl ecti ng al umi ni um materi al . A ful l y
refl ecti ng materi al i s provi ded at the top of the second l ayer. By foucssi ng the l aser beam on
MEMORY 6.25
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the desi red l ayer, the i nformati on can be read. When the l aser beam i s focused on the fi rst
l ayer, suffi ci ent l i ght i s refl ected back by the semi refl ecti ng (transl ucent) l ayer to detect pi ts
and l ands correspondi ng to the data stored on thi s l ayer. When the l aser beam i s focussed
on the second l ayer, the ful l y refl ecti ng l ayer, whi ch i s at the top of the second l ayer, refl ects
the l aser beam to detect the pi ts and l ands correspondi ng to the stored data on thi s l ayer.
I n both cases, the l ayer on whi ch the l aser beam i s not focussed, refl ects much l ess amount
of l aser beam, whi ch i s fi l tered by detecti ng el ectroni c ci rcui try.
The next generati on of DVDs wi l l have two competi ng formats: Bl ue-ray and HD-DVD.
The Bl ue-ray consorti um i s headed by Sony. Bl ue-ray DVDs of 25 GB and 50 GB capaci ty are
expected soon. The HD-DVD consortium is Toshi ba. HD-DVDs of 15 GB and 30 GB are
expected very soon. These di sks wi l l be l ess costl y than Bl ue-ray di sks. HD-DVDs wi l l soon
be produced at near DVDs pri ces.
There are the fol l owi ng types of DVDs:
(i) DVD-ROM
(ii) DVD-R
(iii) DVD-RW
DVD-ROM. The structure of a DVD-ROM i s si mi l ar to that of a CD-ROM as shown i n
Fi g. 6.10. I ts bottom l ayer i s pol ycarbonate pl asti c. I t forms the base of the di sk. The next
l ayer i s a refl ecti ng l ayer, usual l y al umi ni um. Then there i s a protecti ve acri l i c l ayer. The
topmost l ayer i s for l abel . The capaci ty of a si ngl e l ayer si ngl e si ded di sk i s 4.7 GB, doubl e
l ayer si ngl e si ded di sk 8.5 GB and dual l ayer doubl e si ded di sk 17 GB. DVDs of 15, 25, 30 and
50 GB capaci ty are expected soon.
DVD-R or DVD-Writable. The structure of a DVD-R i s si mi l ar to that of a CD-R. I ts
di fferent materi al l ayers are as shown i n Fi g. 6.12. Pi ts are formed i n the dye materi al . Users
can wri te i nformati on on a DVD-R onl y once and read as many ti mes as they want. I t i s used
where a si ngl e copy or a few copi es of i nformati on i s desi red. The capaci ty of a CD-R i s 4.7 GB.
DVD-RW or DVD-RAM or DVD-Rewritable. The structure of a DVD-RW i s si mi l ar
to that of a CD-RW. I nstead of an organi c dye materi al , i ts recordi ng l ayer i s an al l oy. The
al l oy consi sts of si l ver, i ndi um, anti mony and tel l uri um. I t uses phase change technology
for data recordi ng. Thi s technol ogy has al ready been expl ai ned whi l e di scussi ng CD-RW. The
capaci ty of a DVD-RW i s 4.7 GB and 9.4 GB. CD-RWs are used as backup memory to store
a l arge amount of data. DVD-RW uses l aser beam of di fferent power for wri ti ng, erasi ng and
readi ng. Hi gh power l aser beam for wri ti ng, mi ddl e power l aser for erasi ng and l ow power
l aser for readi ng are used. EI DI , SCSI and USB i nterface can be used for a DVD-RW.
6.8 CCD (CHARGE COUPLED DEVICES)
CCD i s a semi conductor memory devi ce. I t i s fabri cated i n the form of a l ong shi ft
regi ster to act as seri al shi ft regi ster. Extremel y hi gh densi ty shi ft regi ster and seri al memo-
ri es can be constructed wi th CCDs. When l i ght fal l s, charge i s created proporti onal to l i ght
i ntensi ty. The charge i s converted to di gi tal si gnal by anal og to di gi tal converter. Because
seri al memori es have l i mi ted use as compared to RAMs. CCDs are not wi del y used memori es
i n di gi tal computers. Appl i cati ons of CCDs, however, are encountered i n i mage processi ng and
di gi tal si gnal processi ng system, where hi gh densi ty seri al nature of the devi ce i s desi rabl e
feature. CCD memory i s used for computers vi si on, i n di gi tal camera, i n robots, etc.
6.26 COMPUTER FUNDAMENTALS
6.9 DIRECT ACCESS STORAGE DEVICES (DASDs)
The onl i ne secondary storage whi ch i s al ways avai l abl e to a processor i s cal l ed di rect
access storage devi ce (DASD). The commonl y used DASDs are magneti c di sks. The opti cal
di sks, i f i ncorporated i n a system are al so DASDs. Thi s term DASD i s i n the context of
permanent type di rectl y accessi bl e l ong term storage devi ce (i.e., di rectl y accessi bl e secondary
storage). As far as the term di rect access i s concerned al l semi conductor memori es RAMs,
ROMs, PROMs are di rectl y accessi bl e and have random access property. Out of these RAMs are
for users and they have been categori zed as pri mary memory. I n the l i terature DASDs are al so
cal l ed random access memory. Earl i er, we have di scussed random access property wi th respect
to memory l ocati ons. From memory l ocati ons poi nt of vi ew a di sk memory i s semi random
memory whereas RAMs, ROMs and PROMs are random access memory. There i s another poi nt
of consi derati on, i .e., fi l e storage consi derati on. Fi l es can be stored/read on random basi s on
disks. But they cannot be stored on random basis on a magnetic tape. From this consideration
disks are random access memory and tapes are sequential memory. I n case of a magnetic tape
the entire tape has to be read and processed to update the sequentially organized records in a
file. The tape is a offline device. Recently some tape drives have provision to access files directly.
A di sk can al so be used to record fi l es of sequenti al records. I f fi l es are to be processed
sequenti al l y, i t can be stored on a di sk i n that very order. I n such a case, the fi rst fi l e i s
accessed on random basi s but al l other fi l es are accessed sequenti al l y. The random access
capabi l i ty of di sks i s then not uti l i zed.
6.10 DESTRUCTIVE AND NONDESTRUCTIVE READOUT
I f in the reading operation the contents of a memory is destroyed, it is called destructive
readout. I n case of destructive readout memory every read operation must be followed by a write
operati on. The dynami c RAM i s an exampl e of destructi ve readout memory. I f the readi ng
operation does not change the contents of a memory, it is called nondestructive readout. Examples
of nondestructive readout memory are: static RAM, magnetic disk, magnetic tape etc.
6.11 PROGRAM AND DATA MEMORY
These terms are used i n the context wi th si ngl e chi p mi crocomputers, i.e., mi crocontrol l ers
whi ch are used for dedi cated appl i cati ons. I n i ndustri al appl i cati ons or some other dedi cated
appl i cati ons the programs are usual l y fi xed, al ready devel oped i n the l aboratory or i ndustry, and
tested for the desi red appl i cati ons. These fi xed programs are wri tten i nto a PROM, EPROM or
fl ash memory. The memory of a mi crocontrol l er, whi ch stores programs i s cal l ed program
memory. PROM or EPROM or fl ash memory i s used as a program memory i n a mi crocontrol l er
to store the fi xed program. The memory of a mi crocontrol l er, whi ch stores data duri ng process-
ing, i s cal l ed data memory. A RAM i s used as a data memory i n a mi crocontrol l er to store data.
I n some cases EPROM i s wi thi n the mi crocontrol l er I C. I n some cases there i s no EPROM i n
the I C; an external EPROM i s used. But RAM i s wi thi n the I C.
6.12 MEMORY MANAGEMENT UNIT (MMU)
The functi on of a memory management uni t i s to convert l ogi cal memory address i nto
actual physi cal (real ) memory address and provi de protecti on. The MMU i s a hardware
MEMORY 6.27
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component pl aced i n between the processor and the mai n memory. Some modern CPUs
contai n on-chi p MMU such as 80286, 80386, 80486, Penti um fami l y of processors, 68030,
68040, 68060, powerPCs etc. The CPU whi ch does not contai n on-chi p MMU uses external
MMU. The MMU i s used i n a mul ti programmi ng or mul ti user system. The tasks whi ch are
performed by MMU can be performed by the operati ng system. Then the operati ng system wi l l
not get suffi ci ent ti me for program executi on and i ts other tasks. The MMU reduces the burden
of the operati ng system. The memory addresses used i n a program are logical addresses. They
i ndi cate the l ogi cal posi ti on of i nstructi ons and data i n the program. A l ogi cal address i s the
l ocati on of an i nstructi on or data rel ati ve to the begi nni ng of the program. For exampl e, the
i nstructi on JNZ LOOP. The l abel LOOP represents a l ogi cal address to whi ch the program wi l l
jump i f the zero fl ag i s not set. When a program i s compi l ed each l ogi cal address i s represented
by a memory poi nter consi sti ng of two components. I n a segment ori ented system the two
components are: segment sel ector and offset. I n a page ori ented system the two components
are: page address and page offset. I n other words a l ogi cal address i s represented by a page
number and a page offset (i.e., a rel ati ve address wi thi n the page).
The modern MMU provi des the faci l i ty of virtual memory to provi de very l arge memory
space to users. Vi rtual memory i s a techni que whi ch al l ows programmers to use more
memory than what a computer actual l y has. The mai n memory whi ch i s actual l y present i n
a computer system i s known as physical or real memory. The processor executes a program
whi ch resi des i n the mai n memory. By vi rtual memory techni que a programmer can make
a program whi ch uses more memory than the actual capaci ty of the mai n memory. Hi s
program i s stored i n the secondary memory, usual l y di sks. The MMU transfers a part of the
pr ogr am fr om the secondar y memor y to the mai n memor y, whi ch i s cur r entl y needed.
Si mi l arl y, i t sends back those parts of the program from the mai n memory to the secondary
memory, whi ch are not bei ng currentl y used. Thi s to and fro movement of i nstructi ons and
data between mai n and secondary memory i s known as swapping.
To expl ai n how MMU manages more memory than the actual capaci ty of the mai n
memory, we shal l take the exampl e of 80286. I t has 24 address l i nes. Wi th 24 address l i nes
onl y 16 MB memory can be addressed. But i ts vi rtual memory capaci ty i s 1 GB. I n i ts vi rtual
mode of operati on the memory poi nter consi sts of 16-bi t segment sel ector and a 16-bi t offset.
The segment sel ector has 14 address bi ts and 2 pri vi l ege-l evel bi ts. The segment sel ector
speci fi es an i ndex i nto the memory resi dent tabl e (descri ptor tabl e) cal l ed descriptor. The
descri ptor gi ves a 24-bi t segment address. The physi cal address i s obtai ned by addi ng the 16-
bi t offset to the 24-bi t segment address. Thi s computati on of physi cal address from a l ogi cal
address i s carri ed out by MMU.
Wi th the hel p of 14 address bi ts the segment sel ector can sel ect any one of 16384 (2
14
)
descri ptors. As the offset component of the l ogi cal address i s of 16-bi ts, each segment wi l l
contain 64 KB. As there is one descriptor for each segment, the total logical address will be 64
KB 16384, about 1 GB. Thus the MMU can manage 1 GB of memory by virtual memory
technique. Now the question is How are 1 GB addresses managed with only 16 MB of real
memory? This is managed by keeping only the currently used segments in the physical memory.
When the CPU sends a l ogi cal address to MMU, i t checks whether the segment contai ni ng
thi s l ogi cal address i s present i n the physi cal memory. I f the segment i s present i n the
physi cal memory, the MMU cal cul ates physi cal address correspondi ng to the suppl i ed l ogi cal
address. When the segment correspondi ng to the suppl i ed l ogi cal address i s not present i n
the physi cal memory, the MMU i nterrupts the CPU. On recei pt of an i nterrupt from MMU,
the CPU reads the desi red code or data segment from the di sk (i.e., secondary memory). The
6.28 COMPUTER FUNDAMENTALS
MMU then cal cul ates the requi red physi cal address. 1 GB l ogi cal addresses (i n case of 80286)
avai l abl e to users consti tute virtual memory and correspondi ng l ogi cal addresses are cal l ed
virtual addresses. The term vi rtual refers to somethi ng whi ch appears to be present but
actual l y i t i s not.
The advantage of a segmented memory i s that i t offers a si mpl e handl i ng techni que for
growi ng data structures. When i t i s not known how l arge a parti cul ar data structure wi l l
become, i t i s not necessary to make a guess. The data structure can be assi gned i ts own
segment. The operati ng system wi l l expand or shri nk i t as requi red. Another advantage i s
that a few descri ptors are requi red for l arge programs or data spaces. I n segment ori ented
system the si ze of the segments whi ch are swapped i n and out of physi cal memory i s qui te
l arge. Thei r l oadi ng i nto the memory i s a ti me consumi ng process. The pagi ng techni que
overcomes thi s di ffi cul ty.
6.12.1 Demand-Paged Virtual Memory Scheme
I n page ori ented memory, the memory i s di vi ded i nto pages. A page has a fi xed l ength,
4 KB or 4 MB l ength. The l ogi cal address i s represented by the page address and the page
offset. The page address poi nts to a descri ptor tabl e. The page address i s just l i ke the sel ector
i n the case of memory segment scheme. The functi on of a descri ptor i s same as that i n case
of a memory segment scheme. When the demanded page i s not present i n the physi cal
memory, a page faul t i s tri ggered. Thi s i nforms the operati ng system to swap i n the desi red
page. The swappi ng operati ons are much easi er due to the smal l er and fi xed l ength of the
pages. Duri ng the program executi on a parti cul ar l ogi cal page can be stored i n di fferent
physi cal pages as a page i s swapped i n and out several ti mes. At any ti me onl y a few pages
of any program (or process) are kept i n the memory. Therefore, more programs (or processes)
i n a mul ti -programmi ng system can be mai ntai ned i n the memory. Thus i t becomes possi bl e
that a program or process can be l arger than the actual capaci ty of the memory. Thi s memory
management scheme i s cal l ed demand-paged virtual memory scheme. As the unused pages
are not to the swapped i n and out of the memory there i s appreci abl e ti me savi ng.
The modern approach i s to store the descri ptors for currentl y used segments or pages
i n the cache memory i nstead of mai n memory. Thi s makes the access of descri ptors much
faster. Some systems have combi ned memory mappi ng scheme empl oyi ng both segmentati on
as wel l as pagi ng techni ques, e.g. 80386. I n thi s techni que each segment contai ns a number
of pages. A l ogi cal address has three components: segment, page and page offset. A segment
component speci fi es the desi red segment. The page component speci fi es the page wi thi n a
segment. The page offset component speci fi es a word wi thi n a page.
6.12.2 Protection
I n a mul ti user system users shoul d not i nterfere wi th each other. The operati ng system
al so shoul d not be i nterfered by the users. The MMU provi des necessary protecti on so that
these condi ti ons are ful fi l l ed. Take an exampl e of 80286. The 16-bi t segment sel ector contai ns
14 bi ts for address and 2 bi ts for pri vi l ege-l evel checki ng. The pri vi l ege-l evel checki ng i s done
for the protecti on. The 2 bi ts i n the segment sel ector represent the pri vi l ege-l evel of a porti on
of a program, whi ch i s maki ng a request to access a segment. There are al so 2 speci al bi ts
for pri vi l ege-l evel i n the descri ptor. The MMU compares the pri vi l ege-l evel of the segment
sel ector wi th the pri vi l ege l evel of the descri ptor. I f a segment sel ector contai ns same or
hi gher pri vi l ege-l evel , then onl y the memory access i s al l owed by MMU. I f the pri vi l ege-l evel
of the segment sel ector i s l ower than that of the descri ptor, the CPU i s i nterrupted by the
MEMORY 6.29
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MMU, whi ch i ndi cates a pri vi l ege-l evel vi ol ati on. Thi s mechani sm i s uti l i zed to protect oper-
ati ng system from users.
6.12.3 MC68851
I t i s memory management uni t of Motorol a. I t uses pagi ng techni que of memory di vi si on.
I t i s used wi th those mi croprocessors of Motorol a whi ch do not have on-chi p MMU. Thi s chi p
i s popul ar and wi del y used wi th 68000 fami l y of mi croprocessors.
6.13 PCMCIA OR WPCMCIA CARDS AND SLOTS
PCMCI A stands for Personal Computer Memory Card I nternati onal Associ ati on. I t i s a
standard for cards for peri pheral s whose si ze i s that of a credi t card. PCMCI A cards are
becomi ng standard features on portabl e and desktop machi nes. These cards are someti mes
cal l ed PC cards. These are smal l cards approxi matel y 2 i nches wi de and 3.5 i nches l ong. The
thi ckness vari es from 1/8 i nch to 1.5 i nch, dependi ng on i ts type. Ori gi nal l y, the standards
were devel oped for removabl e memory cards for portabl e computers. Today, the standards
have been devel oped for extremel y di verse devi ces such as fax, modem, SCSI adapter, an
Ethernet adapter, di sk dri ves, etc. The standards speci fy the physi cal desi gn of the cards, the
physi cal desi gn of the connector, the el ectri cal i nterface to cards, etc. PCMCI A sl ots (socket)
are provi ded on notebooks and other portabl e computers. Today these are al so avai l abl e on
desktop computers. For data exchange purpose, the desktop PCMCI A sl ots are often desi gned
to fi t i nto fl oppy dri ve mounti ng bays. These sl ots can be used for exchangi ng data between
a mobi l e computer system and a desktop computer usi ng PCMCI A cards. Wi th the PCMCI A
storage, data can easi l y be saved i nto a PCMCI A card (wi th fl oppy) on a portabl e computer,
and then the card can be taken out and i nserted di rectl y i nto the desktop machi ne. A PCMCI A
sl ot supports hot i nserti on whi ch means that devi ces can be pl ugged and unpl ugged wi thout
swi tchi ng off the power suppl y to the computer.
There are di fferent types of PCMCI A cards: Type I , Type I I , Type I I I and Type I V. Type
I cards are 3.3 mm thi ck and have 34-pi n connector. These are memory cards. Type I I cards
are 5 mm thi ck and have 68-pi n connector. These are for fax, cel l ul ar modem, LAN adapter,
wi rel ess LAN adapter, SCSI adapter, etc. Type I I I cards are 10.5 mm thi ck and have 68-pi n
connector. These are for hard di sk dri ve up to 1 GB. Type I V cards are 16 mm thi ck and have
been devel oped by Toshi ba for removabl e hard di sks.
Wi rel ess PCMCI A cards are al so avai l abl e. They are cal l ed WPCMCI A cards. These cards
are requi red to i nterface wi rel ess devi ces to PC.
PROBLEMS
1. What i s the functi on of memory i n a computer?
2. What ar e the di ffer ent types of memor y? Di scuss thei r mer i ts, demer i ts and ar ea of
appl i cati ons.
3. What are the vari ous types of semi conductor memory? Di scuss thei r meri ts, demeri ts and
area of appl i cati ons.
4. Descr i be RAM, ROM and nonvol ati l e RAM wi th thei r mer i ts, demer i ts and ar ea of
appl i cati ons.
5. What are stati c and dynami c RAMs? Di scuss thei r meri ts, demeri ts and area of appl i cati ons.
6.30 COMPUTER FUNDAMENTALS
6. Descri be ROM, PROM, EEPROM and fl ash memory wi th thei r meri ts, demeri ts and area
of appl i cati ons.
7. What are mai n, secondary and backup memory?
8. What i s the functi on of a cache memory? Expl ai n the terms cache hi t and cache mi ss. What
i s the rol e of a cache control l er?
9. Di scuss real and vi rtual memory? Expl ai n the term swappi ng. What i s l ogi cal address and
physi cal address?
10. What i s memory control l er? For what type of semi conductor memory i s i t used? What are
i ts functi ons?
11. Di scuss the error detecti on and correcti on techni ques whi ch are used for RAMs.
12. What are the di fferent types of magneti c memory? Descri be them bri efl y.
13. What are the advantages of magneti c di sk memory over magneti c tape memory? What are
the advantages of hard di sks over fl oppy di sks?
14. Descri be the constructi on and worki ng pri nci pl e of 3.5 i nch fl oppi es.
15. Descri be the constructi on and worki ng pri nci pl e of hard di sks. What do you understand by
head crash?
16. What precauti ons are to be taken i n handl i ng fl oppy di sks?
17. What do you understand by formatti ng of magneti c di sks?
18. Di scuss error checki ng techni ques whi ch are used for magneti c di sk memory.
19. Di scuss the functi ons of fl oppy di sk and hard di sk control l ers. Gi ve some exampl e of
control l er I Cs.
20. What i s an opti cal di sk? Di scuss thei r advantages and di sadvantages as compared to
magneti c di sks. What are the di fferent types of opti cal di sks? Di scuss thei r area of appl i cati ons.
21. What i s CCD memory?
22. What are di rect access storage devi ces? What are thei r advantage over sequenti al memory?
23. What do you understand by destructi ve and nondestructi ve read out?
24. What are program and data memory?
25. Di scuss the rol e of a memory management uni t. Di scuss how the MMU generates more
l ogi cal memory addresses than the actual l y exi sti ng physi cal addresses.
26. Di scuss the meri ts and demeri ts of segment ori ented memory system and page ori ented
memory system.
27. Di scuss the demand-paged vi rtual memory scheme of memory management.
28. What i s protecti on? How i s i t achi eved?
29. What are SCSI and EI DE adapters? Di scuss thei r appl i cati ons.
30. What are DVD-ROM, DVD-R and DVD-RAM? I n what way they di ffer from CD-ROM, CD-
R and CD-RAM?
31. What are PCMCI A and WPCMCI A cards and sl ots? Di scuss thei r appl i cati ons.
7
CHAPTER CHAPTER
7.1
I/O DEVICES, MICPOCOMTPOL-
LEPS, I/O PPOCESSOPS AMD
APITHMETIC PPOCESSOPS
The i nput/output (I /O) devi ces and secondary storage uni ts of a computer are cal l ed
peripherals. The term peri pheral i s used i n a wi der sense, i t al so i ncl udes i nterfaci ng devi ces
such as I /O port, programmabl e peri pheral i nterface, programmabl e i nterrupt control l er,
DMA control l er, communi cati on i nterface, counter/i nterval ti mer, CRT control l er, memory
control l er, fl oppy di sk control l er, hard di sk control l er, keyboard i nterface etc. Some of these
control l ers have al ready been di scussed i n Chapter 6. I /O devi ces, remai ni ng i nterfaci ng
devi ces, I /O processors, ari thmeti c processors etc. wi l l be di scussed i n thi s chapter.
7.1 INPUT DEVICES
Data and i nstructi ons are entered i nto a computer through i nput devi ces. An i nput devi ce
converts i nput data and i nstructi ons i nto sui tabl e bi nary form whi ch can be accepted by the
computer. The commonl y used i nput devi ce i s a keyboard. A number of i nput devi ces have
al so been devel oped whi ch do not requi re typi ng for i nputti ng i nformati on. Exampl es are:
mouse, l i ght pen, graphi c tabl et, joy sti ck, track bal l , touch screen etc. Each of these devi ces
permi ts the user to sel ect somethi ng on CRT screen by poi nti ng to i t. Therefore, these
devi ces are cal l ed poi nti ng devi ces. Voi ce i nput systems have al so been devel oped. A mi cro-
phone i s used as an i nput devi ce.
7.1.1 Keyboards
Programs and data are entered i nto a computer through a keyboard whi ch i s attached
to a mi crocomputer or the termi nal of a server or supercomputer. A keyboard i s si mi l ar to
the keyboard of a typewri ter. I t contai ns al phabets, di gi ts, speci al characters, functi ons and
some control keys. When a key i s pressed an el ectroni c si gnal i s produced whi ch i s detected
by an el ectroni c ci rcui t cal l ed keyboard encoder. A keyboard encoder may be speci al I C or a
si ngl e-chi p mi crocomputer used as encoder. The functi on of an encoder i s to detect whi ch key
has been pressed and to send a bi nary code (correspondi ng to the pressed key) to the
computer. The bi nary code may be an ASCI I , EBCDI C or HEX code.
I n some computer systems the keyboard encoder sends si mpl y a scan code to i ndi cate
whi ch key has been pressed. There i s a computer program cal l ed keyboard translation pro-
gram to assi gn the meani ng of the scan code. The program wi l l gi ve the desi red bi nary code
correspondi ng to the pressed key. Thi s approach i s known as soft keys. Thi s approach makes
possi bl e to change the meani ng associ ated wi th vari ous keys on the keyboard.
7.2 COMPUTER FUNDAMENTALS
A si ngl e chi p mi crocomputer used as encoder contai ns a l ookup tabl e i n a ROM. The
bi nary code i s obtai ned from the l ookup tabl e. By changi ng the l ookup tabl e i n the ROM the
output code can be changed. For exampl e, the keyboard system whi ch previ ousl y was outputti ng
ASCI I , can be made to output EBCDI C or any other codes by changi ng l ookup tabl e i n the
ROM.
The codes from the encoder may be transmi tted to the computer usual l y i n seri al mode.
I n seri al transmi ssi on number of connecti ng wi res i s reduced and data i s sent one bi t at a
ti me. Computers use standard keyboards havi ng QWERTY type l ayout of characters, whi ch
i s commonl y used i n mechani cal typewri ters. For faster typi ng keys are rearranged to gi ve
a di fferent l ayout known as Dvorak keyboard. I t i s avai l abl e at extra cost as an opti onal .
Fi g. 7.1 shows key arrangement of a QWERTEY type keyboard. I t i s cal l ed QWERTY type
keyboard because the l etters i n the word QWERTY are the fi rst si x l etters of the thi rd row
from the top of the keyboard. The keyboard contai ns the fol l owi ng major categori es of keys:
(i) Alphabet Keys. There are 26 l etters of Engl i sh al phabets. When an al phabet key i s
pressed, smal l l etter i s typed. Keepi ng Shi ft key pressed, when an al phabet key i s
pressed, capi tal l etter i s typed. Keyboard of other l anguages are al so avai l abl e.
(ii) Digit Keys. There are 10 keys for di gi ts 0 to 9. Di gi t keys are on the second row
from the top of the keyboard. There i s one addi ti onal set of di gi t keys, cal l ed
numeri c key pad, at the l ower ri ght si de of the keyboard. I t i s for faster entry of
numbers.
(iii) Special Character Keys. These are for ful l stop, comma, :, ; , ?, /, \, &, %, @, #,
$, !, ^, *, + , =, -, _, <, >, {, [, (, }, ], ), , , etc.
(iv) Control Keys. These are: Esc (Escape), Backspace, Enter (Return), I ns (I nsert), Del
(Del ete), Arrows keys, Tab, Shi ft, Ctrl , Al t, PgUp (Page up), PgDn (Page down),
Home, End, PrtSc (Pri nt Screen), Wi ndows, etc.
(v) Function Keys. Functi on keys from Fl to F12 are on the fi rst row of the keyboard.
The functi ons of some control keys are as fol l ows:
Enter Key. When Enter (Return) key i s pressed, the cursor comes i n the begi nni ng of
the next l i ne. Thi s key i s pressed at the end of a l i ne typi ng to go to the next l i ne.
Home Key. I t al l ows users to move cursor to the begi nni ng of l i ne. Keepi ng Ctrl pressed
when Home i s pressed, cursor goes i n the very begi nni ng of the screen.
End Key. I t bri ngs the cursor at the end of the l i ne of the text. Keepi ng Ctrl pressed, when
End i s pressed, the cursor goes at the end of the text (or any other stored i nformati on).
PgUp (Page Up). I t al l ows users to move one page of the text (or any other stored
i nformati on) upward at a ti me on the screen.
PgDn (Page Down). I t al l ows users to move one page of the text (or any other stored
i nformati on) downward at a ti me.
Arrow keys: They can move cursor, up, down, l eft or ri ght as desi red.
Del (Delete) Key. I t al l ows to erase character.
I ns (I nsert) Key. I t al l ows to i nsert characters.
PrtSc (Print Screen) Key. I n DOS operati ng system, when thi s key i s pressed, the text
or any other i nformati on whi ch i s on the screen, i s sent to the pri nter for pri nti ng. I n
WI NDOWS operati ng system, thi s key i s used to obtai n Screen Capture.
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Tab Key. I t moves cursor to the next tab stop.
Backspace Key. When thi s key i s pressed, the cursor comes to the previ ous characters
posi ti on and the current character i s del eted.
Shift Key. Keepi ng thi s key pressed, when an al phabet key i s pressed, capi tal l etter i s
typed. I n case of di gi t and some other keys, the symbol s whi ch are wri tten at the top of the
key, i s pri nted.
Ctrl Key. I t i s a control key. I t i s used i n the combi nati on of other keys ei ther a l etter
or number. Keepi ng thi s key pressed, when certai n key i s pressed, some control acti on i s
performed. Exampl es are:
Ctrl + B Add or remove bol d formatti ng.
Ctrl + P Pri nt
Ctrl + S Save
Ctrl + U Add or remove underl i ne
Ctrl + Z Undo l ast command
Alt (Alternate) Key. I t gi ves al ternate functi on of any other key. Keepi ng thi s key pressed,
some other key i s pressed to get some speci al functi on. The speci al functi on depends on the
appl i cati on software under whi ch certai n speci al functi on i s to be performed. For exampl e,
when F4 i s pressed after pressi ng Al t, appl i cati on program i s cl osed.
Functi ons of functi on keys depends on the software whi ch i s bei ng used currentl y. A
functi on key i nvokes certai n program whi ch i s stored i n the computer. When F1 i s pressed,
Hel p i s acti vated. Whi l e worki ng i n an appl i cati on, pressi ng thi s key bri ngs up the appl i ca-
ti on hel p menu. I f there i s no appl i cati on, F1 opens WI NDOWS Hel p.
Someti mes someone can type some words, and then he real i zes that the Caps Lock key
was mi stakenl y swi tched on. So everythi ng i s i n capi tal l etters. To convert i t to smal l l etters,
sel ect the text and press Shi ft + F3.
Windows Key. There are two Windows keys in the bottom row of the keyboard. There is a
Windows logo on the Windows key. When it is pressed, Start Menu is displayed. Holding the
Windows key down, when certain keys are pressed, some actions are performed. An example is:
Wi ndows + F1 Di spl ays Wi ndows Hel p
Application Key. Thi s i s i n the bottom row of the keyboard. I t has an i mage of mouse
poi nter on a menu. I t performs the same functi on as the ri ght-button cl i cki ng of a mouse.
Symbol * i n the second row i s for mul ti pl i cati on. The symbol ^ i n thi s very row i s for
rai se to the power, for exampl e, i f we wri te 2 ^ 3, i t means 2 rai se to the power 3. I ts val ue
i s 2 2 2 = 8.
I n a mul ti medi a keyboard buttons for vol ume control , CD pl ayers control , sl eep, cut,
copy, paste, rotate, cl ose DOS, etc. have al so been provi ded. Wi rel ess l aser keyboards, wi re-
l ess radi o frequency operated keyboards, i l l umi nated keyboards, keyboards wi th adjustabl e
wri st rest for ergonomi c comfort, keyboards speci al l y desi gned for pol l uted i ndustri al envi ron-
ment, waterproof keyboards, keyboards speci al l y desi gned for games, di sabl e persons etc. are
al so avai l abl e.
7.4 COMPUTER FUNDAMENTALS
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Construction of the Keys
Mechanical Keyswitches. Thi s type of key swi tches are mechani cal type swi tches. When
a key i s pressed two metal l i c pi eces make contact. The swi tch el ements are usual l y made of
phosphor-bronze al l oy. When a key i s pressed an el ectri cal si gnal i s produced. Mechani cal type
keys suffer from contact bounce. A pressed key may make and break the contact several ti mes
before i t makes a perfect contact. They may become di rty or oxi di zed. Thi s makes thei r contact
i mperfect and they are no l onger rel i abl e. The l i fe of hi gh qual i ty mechani cal keys i s about 1
mi l l i on keystrokes.
Capacitive Keyswitches. A capaci ti ve type keyswi tch uses pl ates: one movabl e and two
fi xed. When a key i s pressed, the movabl e pl ate comes cl oser to the fi xed pl ates. Thi s causes
a change i n the capaci tance between the two fi xed pl ates. An el ectroni c ci rcui try detects thi s
change and produces a si gnal . I t i s better and more rel i abl e than mechani cal swi tches, but
i t requi res speci al ci rcui try to detect the change i n the capaci tance. I ts l i fe i s more than
mechani cal type keyswi tches, 20 mi l l i on keystrokes.
Hall Effect Keyswitches. I n thi s type of keyswi tches a current i s passed between two
opposi te faces of a semi conductor crystal . Thi s current acts as a reference. A magnet i s moved
to provi de magneti c fi el d. When a key i s pressed, a smal l magnet moves. Thi s produces a
smal l vol tage across the other two opposi te faces of the crystal . Such keyboards are expensi ve
but more rel i abl e. Thei r l i fe i s 100 mi l l i on or more keystrokes.
Two-Key Lockout
When more than one keys are pressed si mul taneousl y a probl em ari ses that the pro-
cessor shoul d not perform wrong operati on. I n the techni que of two-key l ockout a si ngl e key
pressi ng i s recogni zed. Addi ti onal key cl osure i s i gnored unti l the previ ous key i s rel eased.
Onl y after the rel ease of the previ ous key, next one i s recogni zed.
Two-Key Rollover
When two keys are pressed si mul taneousl y or at nearl y the same ti me, each one i s
recogni zed. The ASCI I code for the fi rst key and a strobe si gnal for i t i s sent out. Then the
ASCI I code for the second one and a strobe si gnal for i t i s sent out.
N-Key Rollover
When N-keys are pressed at a ti me each key i s treated i ndependentl y. The i nformati on
of al l the key cl osures i s stored i n some i nternal buffer. The operati ons are performed i n a
sequence.
7.1.2 Light Pen
A l i ght pen i s a poi nti ng devi ce. I t i s used to sel ect a di spl ayed menu opti on on the CRT.
I t i s a photosensi ti ve penl i ke devi ce. I t i s capabl e of sensi ng a posi ti on on the CRT screen
when i ts ti p touches the screen. When i ts ti p touches the screen surface, i ts photocel l sensi ng
el ement detects the l i ght comi ng from the screen and the correspondi ng si gnal s are sent to
the processor. The menu i s a set of programmed choi ces offered to the user. The user
i ndi cates hi s choi ce by touchi ng l i ght pen agai nst a desi red descri pti on of the menu. The
si gnal s sent by the l i ght pen to the processor i denti fi es the menu opti on.
7.6 COMPUTER FUNDAMENTALS
A l i ght pen can al so be used for graphi cs work. A user can draw di rectl y on the CRT
screen wi th the l i ght pen i f the computer system i s provi ded wi th CAD package. The user
can sel ect vari ous col ours and l i ne thi cknesses, can add or erase l i nes and can enl arge or
reduce the si ze of the drawi ngs.
7.1.3 Mouse (Puck)
A mouse is a device to move the cursor on the CRT screen (video screen) of the computer
at faster rate conveniently. Besides moving the cursor of the screen, certain operations are also
performed by pressing buttons provided on the mouse. When a mouse is moved, its distance
traveled and the direction is communicated to the screen by a microcontroller which is embedded
into the mouse. When a mouse is moved, the cursor on the CRT screen moves accordingly.
Cordless mouse is also available. Scroll mouse has a scrolling feature i.e. text on the screen can
be moved up or down moving a wheel which is on the mouse. A mouse may have three or four
buttons for its operation. Modern mouse are optical mouse. An optical mouse contains camera,
light emitting diode (LED) and an embedded digital processing unit. The LED illuminates surface
area. A small area of the surface underneath is focused on a tiny digital camera. The image taken
by the digital camera is converted into digital signals which are sent to the embedded digital
processor. Any surface usually contains microscopic patterns having lines, changes in brightness,
shadows etc. The processor compares the successive images taken by the camera to determine
the distance traveled and the direction of movement of the mouse. The processor uses digital
signal processing technique to measure the distance traveled from one picture to the next picture,
and the direction of mouse movement. The camera takes more than a thousand pictures every
second. A very powerful low-cost embedded processor is used to perform intensive computation.
This type of mouse does not require any pad. I t can be moved on almost any type of surface. A
cordless mouse uses RF (Radio Frequency) signal to interface it to the computer.
Fig. 7.2 Mouse
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The opti cal mouse di scussed i n the above para i s a compl ex opti cal mouse. I n a si mpl e
opti cal mouse, there i s a l i ght sensi ti ve devi ce to sense the refl ected l i ght from the surface.
When mouse i s moved, the refl ected l i ght changes from l i ght to dark area underneath. By
counti ng such changes the di stance travel ed i s measured by the mi crocontrol l er and corre-
spondi ng si gnal s are sent to the computer.
Earl i er, a mouse was a mechani cal one. I t empl oyed smal l wheel s and was a moved on
a rubber pad. El ectri cal pul ses were generated when wheel s moved. These pul ses where
proporti onal to the i ncremental movement of the wheel . A mi crocontrol l er i s used to send
these pul ses and pl uses correspondi ng to the button pressed. The cursor moves on the CRT
screen correspondi ng to the movement of the mouse.
Mouse has al so been devel oped to gi ve i ndi cati ons i n three di mensi ons: X, Y and Z.
Such mouse i s used for 3-D si mul ati ons. Laser mouse has al so been devel oped.
7.1.4 Joystick, Pointing Stick and Track Pads
A joystick i s al so a poi nti ng devi ce. I t i s used to move the cursor posi ti on on a CRT
screen. I ts functi on i s si mi l ar to that of a mouse. A joysti ck i s a sti ck whi ch has spheri cal
bal l at i ts l ower end as wel l as at i ts upper end as shown i n Fi g. 7.3. The l ower spheri cal
bal l moves i n a socket. The joysti ck can be moved ri ght or l eft, forward or backward. The
el ectroni c ci rcui try i nsi de the joysti ck detects and measures the di spl acement of the joysti ck
from i ts central posi ti on; the i nformati on i s sent to the processor. Buttons mounted on the
sti ck or el sewhere on the joysti ck, can be pressed to execute commands. Joysti ck i s used i n
games. Potenti ometer and capaci tor are used i n the sensi ng el ement. Di gi tal joysti cks have
al so been devel oped. They use pi ezo-el ectri c sensor whi ch uses a crystal to produce an
el ectri cal si gnal when i t i s pressed. The el ectri cal si gnal i s fed to ADC (Anal og-to-Di gi tal
Converter) whi ch gi ves di gi tal output. The di gi tal val ues are processed by the computer.
Cordl ess joysti cks are al so avai l abl e.
Fig. 7.3 Joysti ck
Eraser or Pointing Stick
I t i s a poi nti ng devi ce. I t i s used on l aptops where there i s no space for conventi onal
mouse. I t l ooks l i ke a penci l eraser. I t i s embedded among G, H and B keys on a keyboard.
When a fi nger appl i es l ateral pressure to the eraser, the pressure i s passed on to the four
force-sensi ng resi stors empl oyed to sense up, down and si deways forces. A si ngl e-chi p mi cro-
computer (mi crocontrol l er) i s provi ded to measure the forces and send the i nformati on about
cursor movement on the screen.
7.8 COMPUTER FUNDAMENTALS
Track Pads
I t i s one of the l atest poi nti ng devi ces. I t l ooks l i ke a smal l , gray wi ndow, about two
i nches wi de. One merel y sl i des hi s fi nger ti p across the wi ndow to move the cursor. When
wi ndow i s tapped, i t works as the cl i cki ng of pri mary mouse button. A l arger track pad cal l ed
Power Cat has al so been devel oped. I t has a wi der wi ndow about three i nches wi de. There
i s a speci al regi on on the wi ndow. When the user taps thi s wi th hi s fi nger, i t produces the
effect of secondary mouse button cl i ck. Some area of the wi ndow i s used to scrol l up, down,
l eft or ri ght i n the document. I t has al so two pl aces for tri ggeri ng the effect of the forward
and backward buttons i n a Web browser.
7.1.5 Trackballs
Trackbal l i s al so a poi nti ng devi ce and contai ns a bal l whi ch can rotate i n any di recti on.
The user spi ns the bal l i n di fferent di recti ons to move the cursor on the CRT screen. The
associ ated el ectroni c ci rcui try detects the di recti on and speed of the spi n. The i nformati on i s
sent to the processor. I t i s used on a l aptop computer where there i s no space for conventi onal
mouse.
7.1.6 Scanners
Scanners are a ki nd of i nput devi ces. They convert pri nted text, graphi cs, pi ctures etc.
to di gi tal form. They are capabl e of enteri ng i nformati on di rectl y i nto the computer. The mai n
advantage of di rect entry of i nformati on i s that users do not have to key the i nformati on. Thi s
provi des faster and more accurate data entry. I mportant types of scanners are opti cal scan-
ners and magneti c-i nk character readers.
Optical Scanners
Flatbed scanner. I n a fl atbed scanner, the page to be scanned i s pl aced over a gl ass
pl ate. A l i ght source i s kept bel ow the gl ass pl ate, whi ch moves from l eft to ri ght hori zontal l y.
Each page i s treated as a matri x of dots. Each dot i s sensed whether i t refl ects l i ght or
absorbs l i ght. The l i ght source focuses l i ght on very thi n l i ne cal l ed scan l i ne. The dots l yi ng
on a scan l i ne i s sensed. The enti re page i s di vi ded i nto a number of scan l i nes. The scanner
senses each scan l i ne one by one. The dot (spot) whi ch refl ects l i ght are taken as 1 and the
spots whi ch do not refl ect l i ght (i .e. absorbs l i ght) are taken to represent 0. Refl ected l i ght
by dots are sensed by CCDs (Charge Conpl ed Devi ces). I n many scanner 300 hundred of CCDs
are provi ded per i nch on a hori zontal l i ne to gi ve 300 bi ts per i nch resol uti on. After scanni ng
one scan l i ne, the scanner scans the next scan l i ne. I n thi s way i t scans the enti re page. The
enti re page i s represented by matri x of bi ts. The scanned page i s stored i n the computers
memory i n bi t mapped form. I f the page contai ns pure typed text, the bi t mapped form can
be converted to ASCI I form. Bi t mapped form requi res much more storage. Another di sadvan-
tage of bi t mappi ng i s that i ndi vi dual characters are not stored and hence, i t i s not possi bl e
to search for character stri ngs. Software cal l ed opti cal character recogni zer, i s avai l abl e to
convert bi t mapped form to ASCI I form. But pi ctures, graphi cs etc. can not be converted to
ASCI I form.
Opti cal character recogni zer works on compari son pri nci pl e. I t can recogni ze texts whi ch
are typed i n standard type fonts. Handwri tten or any di fferent ki nd of fonts wi l l not be
recogni zed correctl y and effi ci entl y. At present what OCRs (opti cal character recogni zers) are
avai l abl e, do not recogni ze 100 percent correctl y. So proof readi ng has to be done and errors
are to be corrected.
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Optical Mark Reader (OMR)
Speci al marks such as square or bubbl e are prepared on exami nati on answer sheets or
questi onnai res. The users fi l l i n these squares or bubbl es wi th soft penci l or i nk to i ndi cate
thei r choi ce. These marks are detected by an opti cal mark reader and the correspondi ng
si gnal s are sent to the processor. I f a mark i s present, i t reduces the amount of refl ected
l i ght. I f a mark i s not present, the amount of refl ected l i ght i s not reduced. Thi s change i n
the amount of refl ected l i ght i s used to detect the presence of a mark. Thi s method i s used
where one out of a few number of al ternati ves i s to be sel ected and marked. For exampl e,
market survey, popul ati on survey, objecti ve type answer sheets etc. where choi ce i s restri cted
to one out of a few choi ces.
Optical Bar-Code Readers
Thi s method uses a number of bars (l i nes) of varyi ng thi ckness and spaci ng between
them to i ndi cate the desi red i nformati on. Barcodes are used on most grocery i tems. An
opti cal -bar reader can read such bars and convert them i nto el ectri cal pul ses to be processed
by a computer. The most commonl y used bar-code i s uni versal product code (UPC). The UPC
code uses a seri es of verti cal bars of varyi ng wi dth. These bars are detected as ten di gi ts. The
fi rst fi ve di gi ts i denti fy the suppl i er or manufacturer of the i tem. The second fi ve di gi ts
i denti fy i ndi vi dual product. The code al so contai ns a check di gi t to ensure that the i nforma-
ti on read i s correct or not.
A poi nt-of-sal e termi nal often contai ns an opti cal -bar reader. Such a termi nal i s used to
process the sal e transacti ons. I t i s an on-l i ne termi nal connected to a computer for process-
i ng. The opti cal -bar reader reads the bar-code of an i tem. The bar-code i s decoded and data
are sent to the computer. The computer pri nts the name of the i tem, i ts pri ce and other
necessary i nformati ons on the recei pt. The stock at hand and sal e records are al so updated.
Magnetic-Ink Character Reader (MICR)
MI CR i s wi del y used, by banks to process l arge vol umes of cheques and deposi t forms
wri tten every day. A speci al i nk cal l ed magneti c i nk (i .e. an i nk whi ch contai ns i ron oxi de
parti cl es) i s used to wri te characters on the cheques and deposi t forms whi ch are to be
processed by an MI CR. MI CR i s capabl e of readi ng characters on a paper wri tten wi th
magneti c i nk. The magneti c i nk i s magneti zed duri ng the i nput process. The MI CR reads the
magneti c pattern of the wri tten characters. To i denti fy the characters these patterns are
compared wi th speci al pattern stored i n the memory. Before cheques are i ssued to customers
the i denti fi cati on number of the bank and the deposi tors account number are pri nted on the
l ower l eft-si de of the cheques wi th the magneti c i nk. The amount i s pri nted on the l ower-
ri ght si de of the cheque by the bank empl oyee wi th the same magneti c i nk after the cheque
i s recei ved from the customer. When a cheque i s entered i nto an MI CR, i t passes through
a magneti c fi el d. The i ron oxi de parti cl es are magneti zed under the magneti c fi el d. The read
head reads the characters wri tten on the cheque wi th the magneti c i nk. I t i nterprets the
characters and sends the correspondi ng data di rectl y to the computer for processi ng. Upto
2600 cheques are processed per mi nute by an MI CR.
7.1.7 Voice Input Systems
Data entry i nto a computer manual l y usi ng keyboard i s a ti me-consumi ng and l abori ous
task. I t wi l l become very easy i f we can tal k to a computer. Attempts have been made to
devel op a computer that can l i sten to the users and tal k to them. The voi ce i nput to the
7.10 COMPUTER FUNDAMENTALS
computer i .e. voi ce recogni ti on by a computer i s much more di ffi cul t than the voi ce output. I t
i s because of the fact that the rul es for generati ng voi ce through a speaker or a tel ephone
system can easi l y be defi ned compared to the rul es for i nterpreti ng words spoken by a person.
The tones of speech, speed, accent and pronunci ati on di ffer from person to person. These
di fferences i n speech makes voi ce recogni ti on a di ffi cul t job. I n a voi ce i nput system the speech
i s converted i nto el ectri cal si gnal s empl oyi ng a mi crophone. The si gnal s are sent to a processor
for processi ng. The si gnal pattern i s compared wi th the patterns al ready stored i n the memory.
A word i s recogni sed onl y when a choi ce match i s found, and then the computer gi ves a
correspondi ng output. At present a voi ce recogni ti on system i s costl y. I n future i t i s expected
to become cost effecti ve and wi l l be wi del y used for di rect entry of data. I BM has devel oped a
Tal kwri ter wi th 6000 words. I t i s capabl e of detecti ng words wi th 95% accuracy. I t i s meant for
busi ness correspondence. A voi ce recogni ti on system can be used i n factori es at pl aces where
both hands of worker are engaged i n the job he i s doi ng and he wants to i nput some data i nto
the computer. I t can al so be used to assi st bedri dden and handi capped persons i n a number of
tasks; to control access to restri cted areas; to i denti fy a customer i n a bank etc.
7.1.8 Touch Screen
Some computers have touch screen whi ch i s sensi ti ve to users touch. One can use fi nger
to poi nt the command di spl ayed on the screen. I t i s popul ar on l aptops. Many techni ques have
been used to make the screen sensi ti ve to touch as descri bed bel ow :
(i) Capaci ti ve screen uses a devi ce whi ch can sense changes i n capaci tance when and
where the user touches the screen wi th a styl us or fi nger.
(ii) I nfrared screens empl oy l i ght-emi tti ng di odes and photo detector cel l s to cover the
screen wi th i nvi si bl e l i ght. LEDs emi t i nfrared l i ght, and photo detectors recei ve
i t. When the user touches the screen, some l i ght beams are i nterrupted, and the
computer then senses the posi ti on of the fi nger.
(iii) Pressure-sensi ti ve screens of Myl ar, separated by a smal l space are used. Each
sheet of Myl ar contai ns rows of i nvi si bl e wi res. The sheets are pl aced i n such a way
that the wi res run hori zontal l y i n one sheet and verti cal l y i n the other. When the
user appl i es pressure on the screen, the wi res at that poi nt make contact and a
ci rcui t i s cl osed. Thi s i s sensed and fed to the computer.
7.1.9 Some Other Forms of Input Devices
Mi crocomputers or mi croprocessor-based systems are now wi del y used i n i ndustry for
automati c control . Physi cal quanti ti es l i ke temperature, pressure, speed, defl ecti on, strai n,
stress, force, vi brati on etc. are measured and control l ed by mi crocomputers. An el ectri cal or
el ectroni c devi ce cal l ed transducer i s used to sense physi cal quanti ty and gi ve proporti onal
el ectri cal si gnal . The el ectri cal si gnal s are ampl i fi ed and then converted to di gi tal si gnal s. The
di gi tal si gnal s are fed to the processor for measurement, di spl ay and control purposes. Trans-
ducers, ampl i fi ers, anal og-to-di gi tal converter etc. form a ci rcui try cal l ed data acqui si ti on
system. The data acqui si ti on system acts as an i nput devi ce. El ectri cal quanti ti es l i ke vol tage,
current, frequency, power, energy etc. are al so measured, di spl ayed and control l ed by mi cro-
computers. The data acqui si ti on system for el ectri cal quanti ti es do not need transducers.
They empl oy ampl i fi ers, anal og-to-di gi tal converter, anal og mul ti pl exer, sampl e and hol d
ci rcui ts etc. Al so, i n the case of processi ng of el ectri cal quanti ti es the data acqui si ti on system
acts as an i nput devi ce. I n some cases swi tches are used to suppl y el ectri cal si gnal s to
computers for control purposes. I n those cases swi tches act as i nput devi ces.
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I n many appl i cati ons i t i s desi red that a computer shoul d be abl e to see i ts envi ron-
ment. For exampl e, a robot must be abl e to see to perform i ts job, a computer-control l ed
securi ty system must be abl e to see i ts envi ronment etc. To provi de vi si on to computers,
sensors l i ke vi deo cameras, CCD cameras, OPTI CRAM cameras etc. are empl oyed. These
cameras act as sensors to provi de si gnal proporti onal to the i ntensi ty of l i ght fal l i ng on the
var i ous spots of the i mage of an object. The computer can pr ocess these si gnal s and
recogni ze and di spl ay the i mage of the object. Such sensi ng devi ces whi ch provi de the
requi red si gnal s to computers act as i nput devi ces. Detai l s of such sensors i s di scussed i n
Chapter 9 under computer vi si on.
7.2 OUTPUT DEVICES
The output devi ces recei ve i nformati ons from the computer and provi de them to users.
The computer sends i nformati ons to the output devi ces i n bi nary coded forms. The output
devi ces convert them i nto a form whi ch can be used by users such as pri nted form or
di spl ay on a screen. I n some appl i cati ons the computers output may al so be converted by
an output uni t i n a form whi ch can be used as i nput to other devi ces, equi pment, machi nes
etc. The commonl y used output devi ces wi th general purpose computers are: CRT screen
and pri nters.
Computers or mi croprocessor-based systems are now wi del y used for automati c control
appl i cati ons i n i ndustry and other commerci al organi zati ons. I n such cases the computer
outputs el ectri cal si gnal s whi ch are sent di rectl y for control purposes. I n some cases di gi tal -
to-anal og converters are used as output devi ces to gi ve control si gnal s to control l ers, actua-
tors, rel ays etc.
There are certai n devi ces whi ch act as both i nput as wel l as output devi ces. Exampl es
are: tel epri nter termi nal , vi sual di spl ay termi nal etc. A tel epri nter termi nal contai ns a key-
board for i nput and a typewri ter l i ke pri nter for output. A vi sual (or vi deo) di spl ay termi nal
(VDT) contai ns a keyboard for i nput and a vi sual di spl ay uni t for output. The vi sual di spl ay
uni t i s cal l ed monitor or video monitor. Most VDT uni ts contai n CRT for vi sual di spl ay. Other
types of di spl ay uni ts are al so avai l abl e such as LED (l i ght emi tti ng di odes) di spl ay, LCD
di spl ay and pl asma screens. The VDT whi ch contai ns CRT for vi sual di spl ay i s al so cal l ed CRT
termi nal .
7.2.1 CRT Terminals
A CRT terminal consi sts of a CRT di spl ay uni t, a keyboard, CRT-refresh RAM, CRT
control l er and USART or UART for communi cati on wi th the computer. Modern CRT termi -
nal s contai n one or more bui l t-i n mi crocontrol l ers to control and co-ordi nate keyboard, CRT
di spl ay uni t and data transmi ssi on from the termi nal to the computer and vi ce-versa. The
data are entered i nto the computer through the keyboard. Each entered character i s al so
di spl ayed on the CRT screen, so that the user can see what he has typed. When data are
keyed i n, they are hel d i n a smal l memory cal l ed a buffer, wi thi n the termi nal i tsel f. The data
are not transmi tted to the computer unti l the user presses an enter key on the keyboard.
A smal l square poi nter on the screen, cal l ed a cursor i ndi cates the spot on the screen where
the next character to be keyed wi l l be di spl ayed. To correct keystroke errors the cursor i s
moved to the posi ti on where the correcti on i s to be made. Then the key for the correct
7.12 COMPUTER FUNDAMENTALS
character i s pressed. Si nce the termi nal s are used for i nteracti on wi th operators, fast data
transmi ssi on i s not requi red. Therefore, usual l y data are transmi tted from the termi nal to
the computer and vi ce versa i n a seri al mode i .e. one bi t at a ti me.
7.2.2 CRT Display Unit
A CRT (Cathode Ray Tube) di spl ay uni t i s a commonl y used output devi ce. I t di spl ays the
data or i nformati on recei ved from the computer. I t can di spl ay al phanumeri c characters and
graphs. Though the CRT i s basi cal l y an output devi ce i t can perform l i mi ted i nput functi on
when used i n conjuncti on wi th a l i ght pen. The CRT screen i s si mi l ar to a TV screen. A CRT
i s a vacuum tube. An el ectron beam i s produced by the el ectron gun l ocated at the back
porti on of the tube. The el ectron beam i s di rected towards the front of the CRT (i .e. CRT
screen). A coati ng of phosphor materi al i s made on the i nner surface of the screen. The
phosphor emi ts l i ght when i t i s struck by el ectron beam. The col our of the emi tted l i ght
depends on the phosphor substance used. A CRT di spl ay may be ei ther monochrome (i .e. onl y
one col our) or col our (i .e. mul ti col our). Monochrome di spl ays are avai l abl e i n green, bl ue,
orange, yel l ow, pi nk, amber, red, and whi te dependi ng on the type of the phosphor materi al
used. Col our di spl ays are produced on CRT screen on the same pri nci pl e as they are produced
on colour TV screen. To produce col our di spl ay three phosphors: red, bl ue, and green are
used. The coati ng of these phosphor materi al s i s made i n such a way that dots of these three
phosphors i n a tri angul ar pattern are spread over the enti re screen. The three dots of the
three col ours pl aced on a tri angul ar spot are so cl ose that they appear as a si ngl e dot. Three
separate el ectron beams are empl oyed to i l l umi nate the dots of three di fferent phosphors. By
varyi ng the i ntensi ty of the three el ectron beams the i ntensi ty of red, bl ue and green dots
i s vari ed. Thi s gi ves the appearance of a tri angul ar spot (consi sti ng of red, bl ue and green
dots) of the desi red col our. Bl ack and whi te col ours can al so be obtai ned. When al l the three
beams are off the spot wi l l be a bl ack one. When red i s 30%, green 59% and bl ue 11%, the
spot wi l l become whi te. By turni ng on and off the di fferent combi nati ons of red, bl ue and
green beams 16 types of col our can be produced. A much wi der vari ety of col ours can be
obtai ned by control l i ng the i ntensi ty of red, bl ue and green el ectron beams empl oyi ng di gi tal -
to anal og (D/A) converters.
Raster Scan and Vector Scan Method of Display
Characters or graphi cs di spl ayed on the CRT screen are formed of a number of dot
poi nts. The dot poi nts are arranged on hori zontal scan l i nes on the screen. I n the raster scan
method the el ectron beam i s fi rst di rected at the top l eft-hand corner of the screen and then
i t i s moved al ong the fi rst hori zontal scan l i ne. The beam i l l umi nates the sel ected dots al ong
the fi rst hori zontal scan l i ne, whi ch are needed to produce characters or graphi cs. When the
beam reaches ri ght end of the fi rst scan l i ne, i t i s turned off (bl anked) and retraced rapi dl y
l eft si de to the starti ng poi nt of the second scan l i ne. Now i t moves al ong the second scan
l i ne and i l l umi nates the requi red dots on i t. Thi s process i s repeated and al l the scan l i nes
of the screen are i l l umi nated to di spl ay i mages, characters or graphi cs on the screen. When
the beam reaches at the end of the l ast l i ne i t i s bl anked and retraced back to the starti ng
poi nt of the fi rst scan l i ne agai n and the enti re process i s repeated agai n to refresh the
i l l umi nati on of the desi red dots so that one can al ways see the di spl ay due to persi stence of
vi si on. I n thi s method the beam i s scanned over the enti re screen.
I n many appl i cati ons we want onl y to draw an array of strai ght l i nes. I n such cases i t
wi l l be wasteful to move the el ectron beam al ong al l the scan l i nes over the enti re screen.
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Moreover, the di agonal l i nes di spl ayed by raster techni que l ook l i ke stai r steps. I n vector scan
(or random scan) method defl ecti ng pl ates are used to defl ect the beam l eft or ri ght, up or
down. The beam can be di rected to any poi nt on screen di rectl y. Thi s techni que i l l umi nates
the sel ected dots on the screen di rectl y. Strai ght l i nes can be drawn connecti ng any two
poi nts on the screen. By appl yi ng the proper anal og vol tage to hori zontal and verti cal defl ect-
i ng pl ates the el ectron beam can be di rected to any desi red spot. D/A converters are used i n
the ci rcui try of defl ecti ng pl ates to gi ve appropri ate anal og vol tages. The vector scan method
i s qui te sui tabl e to di spl ay graphi cs consi sti ng of strai ght l i nes. But i t i s not sui tabl e to di spl ay
curves.
Display of Characters on CRT Screen
A character i s di spl ayed on the screen by l i ght dots. A matri x of dots i s used for thi s
purpose. To di spl ay a character the si ze of the dot-matri x may be 5 7, 7 9 or 7 12. The
desi red dots are l i ghted to di spl ay a character. A ROM cal l ed character generator ROM, stores
the dot pattern for the di spl ay of each character. The ASCI I or EBCDI C codes of the character
of a text to be di spl ayed at a ti me on the screen, are stored i n a RAM, cal l ed display RAM
or video RAM or display refresh RAM. When new text i s to be di spl ayed the contents of the
RAM are changed accordi ngl y. A CRT screen di spl ays 25 l i nes (rows), each l i ne (row) contai n-
i ng 80 characters. So 2KB (25 80 bytes) di spl ay RAM i s requi red for thi s purpose. A row
counter and a character counter are empl oyed to address the ASCI I code of a character i n the
di spl ay RAM.
Each row of the dot matri x i s cal l ed dot row. Therefore, to di spl ay one row of characters
(i .e. one l i ne of the text) 9 dot rows wi l l be needed, i f 7 9 dot-matri x i s used. The dot-rows
of the same characters-row form scan lines. A dot-row of dot-matri x i s a secti on of the scan
l i nes as shown i n Fi g. 7.4. A schemati c di agram to expl ai n the pri nci pl e of di spl ayi ng a
character i s shown i n Fi g. 7.5. The ASCI I codes of the character to be di spl ayed on the screen
are stored i n the di spl ay RAM. By setti ng the row counter and character counter the address
of the fi rst character of the fi rst character-row i s appl i ed to the di spl ay RAM. The di spl ay RAM
gi ves an output, i .e. ASCI I code of the fi rst character of the fi rst character-row. Thi s code i s
appl i ed to the char acter gener ator ROM whi ch contai ns the dot-matr i x patter n of the
char acter.
A dot matri x has 9 dot-rows. At a ti me one dot-row i s taken up for scanni ng by the
el ectron beam. A dot-row counter i s al so empl oyed to count the dot-rows of a character (or
scan l i nes of the characters). The output of thi s counter control s the character generator
ROM. So the ROM wi l l gi ve the dot pattern of the fi rst scan l i ne of the fi rst character. Thi s
output i s appl i ed to a shi ft-regi ster. The functi on of the shi ft regi ster i s to convert the paral l el
i nput to seri al output because the scanni ng of dots of a dot-row i s to be done one dot at a
ti me. The output of the shi ft regi ster i s ampl i fi ed and then used to l i ghten the requi red dots
of the fi rst scan l i ne of the fi rst character (i .e. the dots on ab). The ei ghth bi t of the data i nput
of the shi ft regi ster i s grounded. Thi s gi ves one dark dot or undot between adjacent charac-
ters. After thi s the fi rst scan l i ne of the second character of the fi rst character row (i .e. cd)
i s taken up. Si mi l arl y, fi rst scan l i ne for al l 80 characters i s taken up. Then the el ectron beam
i s banked and retraced to the starti ng poi nt of the second scan l i ne of the fi rst row of
characters. I n thi s way al l 9 scan l i nes are taken up one by one for the fi rst row of characters.
After thi s the second row of the characters (i .e. second l i ne of the text) wi l l be taken up. Thi s
process wi l l be repeated to take up al l the 25 character-rows. When the el ectron beam
reaches at the ri ght end of the l ast scan l i ne of l ast character row, i t i s retraced back to the
7
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Fig. 7.4 Character di spl ay by dot-matri x.
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starti ng poi nt of the fi rst scan l i ne of fi rst character row. The enti re process of scanni ng i s
agai n repeated to refresh the characters di spl ayed on the screen. The refreshi ng i s done 60
ti mes per second.
I n some arrangements the ASCI I codes of the characters are stored i n al ternate memory
l ocati ons of the di spl ay RAM. Associ ated wi th each character an attri bute byte i s al so stored.
The attri bute byte speci fi es the qual i ty of the character, such as underl i ne, i ncreased or
decreased i ntensi ty, whether i t i s bl i nki ng and so on. I n some cases two RAMs are empl oyed.
One stores codes of the characters whi l e the other stores attri butes.
Fig. 7.5 Schemati c di agram of character di spl ayi ng ci rcui t.
Bit-Mapped Raster Scan Method
Thi s techni que i s used to di spl ay graphi cs or pi ctures. The screen i s not treated as 25
rows of characters and each row contai ni ng 80 characters. The enti re screen i s treated as a
matri x of dots. Each dot i s programmed whether i t wi l l be on or off. There i s no di spl ay RAM
and character generator ROM. The dot pattern for each 8 dots of a scan l i ne i s stored i n
successi ve memory l ocati ons. A byte i s read from the memory and appl i ed di rectl y to the shi ft
regi ster whi ch gi ves seri al output. The desi red dot pattern for a secti on of the scan l i ne i s
di spl ayed on the screen. Then next byte from the memory i s taken up. The process of the
raster scan i s fol l owed and the dots of the enti re screen are scanned. Each dot i s cal l ed a
pi cture el ement or i n short pixel or pel. Thi s method i s very fl exi bl e. I t has two major
drawbacks. I t requi res l arger RAM capaci ty, i .e. 16 KB compared to 2 KB i n character di spl ay
method. To produce col our graphi cs sti l l more memory l ocati ons are requi red. I n thi s tech-
ni que tremendous amount of copyi ng i s requi red. I t needs a very fast CPU or speci al hard-
ware for control l i ng pi xel s qui ckl y.
Programmi ng of each pi xel i s a very tedi ous work. To make programmi ng easy graphi cs
programs are avai l abl e. One has to l earn how to use these programs. I n graphi cs program
subrouti nes are avai l abl e to draw l i nes, ci rcl es, arcs etc. usi ng whi ch compl ex drawi ngs can
be drawn and pri nt out can be obtai ned. A mouse i s very hel pful i n prepari ng such drawi ngs.
A bit-map terminal can support displays having a number of windows. A window is defined
as an area of the screen used by one program. The facility of multiple windows allows to run
several programs at the same time. Each program displays its results independent of the others.
7.16 COMPUTER FUNDAMENTALS
Some vi deo termi nal s have both faci l i ti es: they can work ei ther as a bi t-map termi nal
or a character-map termi nal .
7.2.3 CRT Controllers
A CRT control l er contai ns the necessary el ectroni c ci rcui try to control CRT di spl ay.
Several control l er I Cs are avai l abl e. A few of them are descri bed bel ow.
Intel 8275
I t i s a si ngl e chi p programmabl e CRT control l er to i nterface CRT raster scan di spl ays.
I t i s compati bl e wi th 8085, 8086 and 8088 I ntel mi croprocessors. I ts basi c functi on i s to di spl ay
characters and refresh the di spl ay. I t al so has graphi cs capabi l i ty. I t contai ns a row counter,
a character counter, a scan l i ne counter, a raster ti mi ng ci rcui try and vi deo control uni t. I t
al so contai ns two 80-byte buffers, one to hol d the ASCI I codes of characters of the row to be
di spl ayed and the other to hol d the ASCI I codes of characters of the next row. The ASCI I codes
of characters of a page to be di spl ayed are stored i n the mai n memory of the computer. Whi l e
the contents of one 80-byte buffer of 8275 are bei ng used to refresh the di spl ay, the other
80-byte buffer i s fi l l ed up wi th the ASCI I codes for the next row usi ng DMA techni que.
Character generator ROM and shi ft regi ster are external chi ps. The 8275 has capabi l i ty of 4
types of cursor control . I t i s al so provi ded wi th l i ght pen detecti on capabi l i ty. I t has program-
mabl e screen and character format. I t possesses 6 i ndependent vi sual fi el d attri butes.
Intel 8276
I t i s smal l system CRT control l er. I t i s meant to i nterface CRT raster scan di spl ays wi th
I ntel 8085, 8086, 8088 mi croprocessors and 8051 si ngl e chi p mi crocomputer. I t has 4 types of
cur sor contr ol , pr ogr ammabl e scr een and char acter for mat, 6 i ndependent vi sual fi el d
attri butes. I t contai ns al l necessary counters, buffers, raster ti mi ng ci rcui try and vi deo con-
trol , etc.
Intel 82706
I t i s an I ntel vi deo graphi cs array (VGA) compati bl e di spl ay control l er for I BM PC/XT/
AT and PS/2. Al l vi deo moni tors devel oped for I BM PS/2 system are provi ded wi th VGA
control l er. The 82706 can support 256 KB vi deo memory. I t i s desi gned to be compati bl e wi th
80286 and 80386 and other mi croprocessors. I t has EGA/CGA/MDA BI OS compati bi l i ty. I t acts
as CRT control l er and vi deo memory control l er.
Intel 82716
I t i s a vi deo storage and di spl ay devi ce. I t i s a l ow cost, hi ghl y i ntegrated vi deo control l er.
I t di spl ays texts and graphi cs. I t can manage upto 16 di spl ay objects on the screen at any
ti me. I t can sel ect upto 16 col ours from a range of 4096. I t contai ns on-chi p DRAM control l er
and on-chi p D/A converters. I t can support upto 512 KB of di spl ay memory. I t i s compati bl e
wi th 8- and 16-bi t mi croprocessors and mi crocontrol l ers.
Motorola 6845
I t i s a CRT control l er. I t i s used i n both a monochrome moni tor and a col our/graphi cs
moni tor. I t uses 2 external 2KB memory: one to store ASCI I codes of characters and the other
to stor e an attr i bute code for each char acter. Char acter gener ator and shi ft r egi ster s
empl oyed are external . A mul ti pl exer i s used to al l ow ei ther the CPU or CRT control l er to
access the di spl ay-refresh RAMs. I t can address upto 16 KB of di spl ay and attri bute memory.
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7.2.4 Non-CRT Displays
Non-CRT di spl ays i ncl ude LED, LCD and pl asma di spl ays. LED di spl ays are used i n
mi croprocessor-based i ndustri al control s, i nstruments etc. where onl y a smal l amount of data
are to be di spl ayed. CRT screen di spl ay i s used where a l arge amount of data are to be
di spl ayed. I n portabl e battery powered i nstruments usual l y LCD di spl ays are used because
they consume l ess power. Non-CRT di spl ays have been descri bed bel ow i n bri ef.
Liquid Crystal Display (LCD)
I n LCDs a l i qui d crystal l i ne materi al i s sandwi ched between two gl ass or pl asti c pl ates.
The front pl ate i s transparent and the back pl ate i s refl ecti ve. There i s a coati ng of thi n
fi l m on the front pl ate. The coati ng i s transparent and conducti ve. I ts secti ons (segments)
are i n the shape of desi red characters. An el ectri cal l y conducti ve fi l m or backpl ane i s put
on the back pl ate. A vol tage i s appl i ed between a segment and the back pl ate to create
el ectri c fi el d i n the regi on under the segment. The el ectri c fi el d makes a change i n the
transmi ssi on of l i ght through the regi on under the segment. Commonl y avai l abl e LCDs are
of two types: dynami c scatteri ng type and fi el d effect type. I n dynami c scatteri ng type the
mol ecul es ar e al i gned i n one di r ecti on under the segment wher e fi el d i s pr esent. The
crystal l i ne mol ecul es refl ect more l i ght i n thi s condi ti on and thi s produces etched-gl ass
l ooki ng l i ght characters on a dark background. I n fi el d effect type, mol ecul es are pol ari zed
to absorb l i ght where el ectri c fi el d i s present. Thi s produces dark characters on a si l ver-
gray background. LCDs do not emi t thei r own l i ght. Therefore, a l i ght source i s to be used.
LCDs si mpl y change the refl ecti on of avai l abl e l i ght. Today, most LCDs used are of the type
that pr oduce dar k i mages on a si l ver backgr ound. The col our di spl ays have al so been
devel oped. Monochrome and col our di spl ays are expected to grow rapi dl y i n future. D.C.
vol tage i s not used i n case of LCDs as i t wi l l damage them. A square wave si gnal of
frequency 30150 Hz i s used for the purpose. A 23 V i s requi red between the backpl ate
and segment.
Screen type LCDs have al so been devel oped. For screen type LCDs the l i qui d crystal
el ements are arranged i n a l arge X-Y matri x of dots. The el ements of each row are connected
together for dri vi ng purpose. Si mi l arl y, the el ements of each col umn are al so connected
together. An i ndi vi dual el ement i s energi zed by energi zi ng both the row and the col umn
whi ch contai n the el ement. Thi s type of di spl ay has a probl em of l ow resol uti on. The reso-
l uti on i s the abi l i ty to di sti ngui sh thi ngs whi ch are cl ose together. LCDs are l i ghtwei ght and
consume l i ttl e power whi ch make them attracti ve for portabl e computers.
TFT LCD Monitor
At present TFT LCD moni tors are wi del y used i n notebooks. TFT stands for Thi n Fi l m
Transi stors. A matri x of ti ny swi tchi ng transi stors cal l ed TFT i s pl aced on a gl ass substrate
whi ch control s on/off state of each pi xel (dot or spot) dependi ng on the si gnal appl i ed. The
advantages of LCD screen i s that i t i s sl i m, l i ght wei ght and has l ow eye-strai n compared
to a CRT moni tor. A best-of-cl ass LCD comes wi th USB port, wi descreen format screen si ze
from 1730 i nches, bui l t-i n TV tuner, memory card readers etc. CRT moni tors are known
to emi t harmful radi ati on, whereas LCD moni tors do not. Nowadays good qual i ty LCD
moni tors are avai l abl e. A major weak poi nt of LCD moni tor i s i ts response ti me, whi ch i s
the ti me taken for a pi xel to swi tch off compl etel y from whi te to bl ack. The greater l ag i s
not desi rabl e i n fast movi ng vi deos.
7.18 COMPUTER FUNDAMENTALS
OLED (Organic Light Emitting Diode) Displays
OLED i s a sol i d state devi ce. I t contai ns a coupl e of organi c materi al l ayers. I t i s thi ner,
l i ghter, fl exi bl e and consumes l ess power. I t i s better than l i qui d crystal di spl ays and LEDs.
I t emi ts bri ghter and more coherent l i ght. The di sadvantages of OLEDs are: shorter l i fe and
hi gh cost. There i s anode and cathode across whi ch vol tage i s appl i ed. I n between anode and
cathode, there are two organi c l ayers. The pri nci pl e of emi ssi on of l i ght i s whenever an
el ectron moves i nto a hol e, energy i s rel eased. Thi s energy i s i n the form of l i ght. The col our
of l i ght depends on the type of organi c mol ecul es used and the i ntensi ty depends on the
amount of current fl owi ng i n the di ode. I n an organi c l ayer hol es are created, el ectrons move
from the cathode. El ectrons move i nto hol es i n an organi c l ayer. I n an acti ve-matri x OLED,
there is Thi n Film Transi stors (TFT) matri x as a part of the ci rcui try whi ch deci des whi ch
pi xel i s to be turned on.
Plasma Displays
I n pl asma di spl ays i oni zed gas i s sandwi ched between two gl ass pl ates. A number of
paral l el wi res run hori zontal l y as wel l as verti cal l y. A smal l amount of current i s passed
through one hori zontal and one verti cal wi re to cause the gas to gl ow at a spot at the
i ntersecti on of the wi res. The probl ems encountered wi th LCDs are el i mi nated i n pl asma
di spl ays. Unl i ke LCD, pl asma di spl ay i s bri ghter. I t can be seen from a wi de angl e, 160
degrees. Gas pl asma di spl ay screen can easi l y be made l arger than 40 i nches (di agonal ). LCD
screen can not be bui l t i n thi s si ze. A pl asma screen uses si mpl i fi ed ci rcui ts. Bei ng l ess
expensi ve i t i s sui tabl e for hi gh-vol ume producti on. I n case of pl asma di spl ay, phosphor
materi al i s used for each cel l . For col our di spl ay red, bl ue and green phosphors are used i n
three adjacent cel l s.
Light Emitting Diode (LED) Displays
Three types of LED di spl ays as shown i n Fi g. 7.6 are avai l abl e. A 7-segment di spl ay i s
very si mpl e and i t i s used to di spl ay onl y di gi ts and hexadeci mal l etters. To di spl ay numbers
and enti re al phabets 18-segment di spl ays or dot-matri x di spl ays can be used.
The 7-segment di spl ays bei ng si mpl e are wi del y used. Dri vers/decoders for 7-segment
di spl ays are avai l abl e i n I C form. The di spl ays are i nterfaced to mi croprocessors through
dri vers/decodes. Such di spl ays wi th buffers can al so be connected di rectl y to the processor
through ports. There are bi nary codes to di spl ay di gi ts and some sel ected al phabets. These
codes are stored i n memory. For more detai l s i ncl udi ng i nterfaci ng Ref. 1 may be consul ted.
7.2.5 Display and Keyboard Interfacing Chip, Intel 8279
The 8279 i s a programmabl e keyboard/di spl ay devi ce. The data i nput and di spl ay i s the
basi c requi rement of many mi croprocessor-based systems. The 8279 can i nterface a keyboard
and LED di spl ays to 8-bi t mi croprocessors. I t rel i eves CPU from the burden of scanni ng
keyboard and refreshi ng di spl ays. I t has two secti ons: a keyboard secti on and a di spl ay
secti on. The keyboard secti on i s capabl e of i nterfaci ng a regul ar typewri ter styl e keyboard or
random toggl e or thumb swi tches. I t acts as a keyboard encoder for 8 x 8 keyboard. I t can
provi de i nterface to 64-contact key matri x or to an array of sensors or strobed i nterface
keyboard, such as the Hal l Effect and ferri te vari ety. I t has 2-key l ockout or N-key rol l over
wi th contact debounce features. I t has been provi ded wi th 8-character keyboard FI FO to store
keyboard i nformati on.
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Fig. 7.6 LED di spl ay (a) 7-segment di spl ay, (b) 18-segment di spl ay, (c) 5 7 dot matri x di spl ay.
I ts di spl ay secti on dri ves al phanumeri c di spl ays or i ndi cator l i ghts. I t can i nterface LED,
i ncandescent and other popul ar di spl ays. I t control s di spl ay and refreshi ng upto 16 characters.
I t contai ns 16 8 di spl ay RAM whi ch can be l oaded by the CPU. Both readi ng and wri ti ng
of the di spl ay RAM can be made wi th auto-i ncrement of the di spl ay RAM address.
7.3 PRINTERS
Pri nters are commonl y used output devi ces. They provi de i nformati on i n a permanent
readabl e form. They produce pri nted output of resul ts, programs and data. Pri nters whi ch are
used wi th computers are cl assi fi ed as fol l ows:
7.20 COMPUTER FUNDAMENTALS
(i) Character pri nters
(ii) Li ne pri nters
(iii) Page pri nters
A character pri nter pri nts one character of the text at a ti me. A l i ne pri nter pri nts one
l i ne of the text at a ti me. A page pri nter pri nts one page of the text at a ti me.
The pr i nter s have been cl assi fi ed above as to how they pr i nt. Ther e i s one mor e
cl assi fi cati on whi ch depends on the technol ogy used i n thei r manufacture. Accordi ng to thi s
consi derati on the pri nters are cl assi fi ed i nto the fol l owi ng two broad categori es:
(i) I mpact pri nters
(ii) Noni mpact pri nters
I mpact pri nters use el ectromechani cal mechani sm that causes hammers or pi ns to stri ke
agai nst a ri bbon and paper to pri nt the text. Non-i mpact pri nters do not use el ectromechani cal
pri nti ng head to stri ke agai nst ri bbon and paper. They use thermal , chemi cal , el ectrostati c,
l aser beam or i nkjet technol ogy for pri nti ng the text. Usual l y, a noni mpact type pri nter i s
faster than an i mpact type pri nter. The di sadvantage of noni mpact type pri nters i s that they
produce si ngl e copy of the text whereas i mpact pri nters produce mul ti pl e copi es of the text.
To sol ve thi s shortcomi ng of the noni mpact pri nters the manufacturers have devel oped
noni mpact type pri nters that can be used as offl i ne devi ces to produce addi ti onal copi es of
computer prepared output. For thi s purpose the pri nter accepts data from magneti c tape and
produce the output.
7.3.1 Character Printers
Character pri nters pri nt one character at a ti me. They are l ow-speed pri nters. Thei r
pri nti ng speed l i es i n the range of 30600 characters per second dependi ng upon the type of the
pri nter. They are used wi th personal computers for l ow vol ume pri nti ng work. Characters to
be pri nted are sent seri al l y to the pri nter. A modern pri nter has i ts own mi crocontrol l er. The
mi crocontrol l er control s the posi ti oni ng of the pri nt head or deci des whi ch pi ns are to be
empl oyed to form the desi red character. I t al l ows pri nter to recei ve the next set of characters
to be pri nted from the computer whi l e pri nti ng of the current set i s goi ng on. Two types of
i mpact character pri nters are avai l abl e: dot-matri x pri nters and l etter qual i ty pri nters.
7.3.2 Dot-Matrix Impact Type Character Printers
A character i s pri nted by pri nti ng the sel ected number of dots from a matri x of dots.
Fi g. 7.7 shows how a character i s pri nted. The formati on of a character has been shown usi ng
7-dot rows and 5-dot col umns. Thi s pattern i s cal l ed 5 7 dot-matri x. The pri nt head contai ns
a verti cal array of 7, 9, 14, 18 or even 24 pi ns. A character i s pri nted i n a number of steps.
One dot-col umn of the dot-matri x i s taken up at a ti me. The sel ected dots of a col umn (i .e.
the col umn of dot-matri x) are pri nted by the pri nt head at a ti me as i t moves across a l i ne.
A dot-matri x pri nter i s faster than a l etter qual i ty pri nter. I ts pri nti ng speed l i es i n the range
of 30600 cps (character per second).
Dot-matri x pri nters are very fl exi bl e. They do not have fi xed character font. The term
font i s used to refer to a character set of a pri nter. As the fonts are not fi xed a dot-matri x
pri nter can pri nt any shape of a character by the software. Thi s permi ts for many speci al
characters such as , , , , z etc; vari ous si zes of pri nt, bol d or expanded characters, i tal i c,
character of any l anguage and provi des the abi l i ty to pri nt graphi cs. To pri nt graphi cs the dot
pattern for each col umn of dots are sent out to the pri nt head from the memory. The pri nci pl e
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i s si mi l ar to that used i n bi t mapped raster scan graphi cs di spl ay on CRT. Fi g. 7.7 shows how
characters are pri nted by a dot matri x pri nter. Wi th the advent of i nkjet and l aser pri nters,
the use of dot-matri x pri nters has di mi ni sed much. They are used i n certai n appl i cati ons such
as banks, rai l ways etc.
Fig. 7.7 Character pri nti ng by dot-matri x pri nter.
7.22 COMPUTER FUNDAMENTALS
7.3.3 Ink-Jet Printers
An i nk-jet pri nter uses dot-matri x approach to pri nt text and graphi cs. Most i nk-jet
pri nters use mul ti pl e jets verti cal l y al i gned on a cartri dge, whi ch moves hori zontal l y across
a page. The i nk cartri dges contai n a col umn of ti ny heaters. When a heater i s acti vated a
drop of i nk i s expl oded onto the paper. The pri nt head contai ns an i nk cartri dge whi ch i s made
up of a number of i nk-fi l l ed fi ri ng chambers, each attached to a nozzl e thi nner than a human
hai r. When an el ectri c current i s passed through a resi stor, the resi stor heats a thi n l ayer
of i nk at the bottom of the chamber. The bottom i nk l ayer of the chamber i s heated up to
900 degree Fahrenhei t for a fracti on of a second. Thi s causes the i nk to boi l and form a
vapour bubbl e. The vapour bubbl e expands and pushes i nk through the nozzl e to form a
dropl et at the ti p of the nozzl e. The pressure of vapour bubbl e forces the dropl et to move to
the paper. When the resi stor cool s down, the bubbl e col l apses. Thi s resul ts i n a sucti on whi ch
pul l s fresh i nk from the reservoi r i nto the fi ri ng chamber.
A colour ink-jet printer empl oys four i nk cartri dges : one each for cyan (bl ue-green),
yel l ow, magenta (purpl e-red) and bl ack. Thi s system of col our i s cal l ed CYMK (K stands for
bl ack). Unl i ke col our l aser pri nters and col our thermal pri nters, col our i nk-jet pri nters do not
need mul ti pl e passes over the same sheet of paper for col our pri nti ng. The i nk of desi red
col our can be pl aced at any desi red poi nt of the page, i n a si ngl e pass.
Photo Quality Colour Ink-Jet Printers
Pri nters can gi ve output that matches the cl ari ty, gl oss and sharpness of conventi onal
photographs from studi os. These true-to-l i fe i mages are known as photo-qual i ty pri nts. Tra-
di ti onal l y, dye subl i mati on pri nters have been used for photo-qual i ty pri nts. They can achi eve
photo-qual i ty resul ts even at resol uti ons as l ow as 200 dpi . But cost per uni t wi th these
pri nters turns out to be very hi gh. Today, i nk-jet pri nters have been devel oped to gi ve photo-
qual i ty pri nts.
A col our i nk-jet pri nter uses four pri mary col ours CYMK. I t can produce dots of these
four pri mary col ours. When several dots of di fferent col ours are pl aced cl ose enough and
vi ewed from a di stance, they bl end to produce a new col our. Thi s techni que i s cal l ed half-
toning. Ordi nary i nk-jet pri nters use four pri mary col ours, and pl ace two drops of di fferent
i nk i n each dot. I n thi s way they can produce dots of ei ght col ours. Further shades are
obtai ned by hal f-toni ng.
There i s another techni que cal l ed layering to get wi der range of shades. Hewl ett-
Packard photo-qual i ty pri nters use thi s techni que. I n thi s techni que several i nk drops are
pl aced i n each dot. Thi s gi ves better col ours wi thout hal f-toni ng. I t can gi ve 250 col our shades
per dot by l ayeri ng 16 drops of i nk per dot. Epson uses si x col our cartri dges i n i ts photo-
qual i ty i nk-jet pri nters to get wi der range of col ours. Extra col ours are l ow-densi ty magenta
and l ow-densi ty cyan (m and c), whi ch are di ffi cul t to obtai n. Epson al so empl oys vari abl e-si ze
dropl et technol ogy, whi ch can produce dots of di fferent i ntensi ty from the same nozzl e.
7.3.4 Laser Printers
Laser pri nters are page pri nters. An enti re page i s processed at a ti me. They use l aser
beam to produce an i mage of the page contai ni ng text/graphi cs, on a photosensi ti ve drum.
The drum i s coated wi th negati vel y charged photo-conducti ve materi al . A i n-bui l t computer
control s the l aser beam to turn i t on and off when i t i s sent to the drum. The page i mage
i s produced on raster scan pri nci pl e as i t i s produced on a CRT. The poi nts where l aser beam
stri kes become posi ti vel y charged. The l aser beam causes a negati vel y charged fi l m (usual l y,
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made of zi nc oxi de and other materi al on the surface of the drum) to change i ts negati ve
charge to posi ti ve charge. The areas of the drum surface where l aser beam does not stri ke,
retai n thei r negati ve charge. Negati vel y charged i nk powder cal l ed toner i s used i n a l aser
pri nter for pri nti ng. The l aser-exposed areas of the drum attract toner. Paper i s posi ti vel y
charged when i t passes through the pri nter. The posi ti ve charge on the paper i s stronger than
the posi ti ve charge on the l aser-exposed surface of the drum. The paper charge bei ng more
posi ti ve, pul l s the toner off the drum and puts i t on the paper. The paper then moves to a
fusi ng stati on where toner i s permanentl y fused on the paper wi th heat and pressure. After
thi s the drum i s di scharged and cl eaned. Now the drum i s ready to process the next page.
I n thi s case bl ack l etters are wri tten on whi te paper. The surface of the drum whi ch does not
attract toner, gi ves whi te areas on the paper. Pri nters wri ti ng bl ack i mage on whi te paper
are called write-black printers. Low-speed l aser pri nters pri nt 810 pages per mi nute.
Hi gh-speed l aser pri nters pri nt 200 pages per mi nute.
A write-white printer pri nts whi te characters on bl ack background. I n such a pri nter
l aser-beam creates negati ve charge on the surface of the drum, where i t stri kes. Toner i s
negati vel y charged. Posi ti vel y charged photoconducti ve materi al i s used for the coati ng of the
drum surface. The surface area of the drum, whi ch i s not exposed to l aser-beam, remai ns
posi ti vel y charged. Toner i s attracted by the area of the drum whi ch i s not exposed to l aser-
beam. Paper i s posi ti vel y charged but more stronger. I t attracts toner, and a whi te pri nt
agai nst bl ack background i s obtai ned.
Col our l aser pri nters are al so avai l abl e. They use toner of di fferent i nks, and they make
mul ti pl e passes over the same sheet of paper for col our pri nti ng. A col our l aser pri nter has
abi l i ty to provi de the most preci se detai l s, but i t i s sl ow, compl i cated and expensi ve. I t needs
four separate pri nt engi nes whi ch must take thei r turn to appl y col oured toner to the page.
The di fference between a xerox machi ne and a l aser pri nter i s that i n a xerox machi ne
the page i mage i s formed on the photosensi ti ve drum wi th a camera l ens, whereas i n a l aser
pri nter page i mage i s formed by scanni ng l aser beam usi ng computer control .
A l aser pri nter contai ns a powerful embedded si ngl e-chi p mi crocomputer or a mi cro-
processor-based system to handl e very l arge amount of pi xel s i nvol ved i n the page pri nti ng.
7.3.5 Dye-Sublimation Type Printer
A dye-subl i mati on type pri nter gi ves photo-qual i ty pri nt. I t uses speci al paper that
accepts pri nters col our. Paper sheet i s pl aced on a drum. I t uses a rol l of pl asti c fi l m whi ch
contai ns cyan, magenta, yel l ow and bl ack dyes i n bands. Each band has the same wi dth and
hei ght as those of the paper sheet. The adjacent bands are of di fferent col ours. There are a
number of heati ng el ements whi ch can cause the dye to subl i mate. The sol i d i nk when
subl i mates becomes gaseous and absorbed i nto the fi ber of the paper. The i nk does not go
i nto l i qui d state. Each heati ng el ement can produce 256 di fferent temperatures. The amount
of dye that i s subl i mated depends on the temperature. More the temperature, more the dye
i s subl i mated and transferred to the paper. Thi s gi ves di fferent shades of a parti cul ar col our.
By thi s techni que 16 mi l l i on col ours can be producted wi thout mi xi ng di fferent col ours as i t
i s done i n case other type of pri nters.
After the pri nti ng of one col our i s compl eted, the drum reverse i ts di recti on and the
papers returns to i ts starti ng posi ti on. Then the pri nti ng process for the other col our i s
repeated. The enti re process i s repeated for al l the four col ours. I n other words the paper
sheet goes through mul ti pl e passes for mul ti col our pri nt. A dye-subl i mati on pri nter produces
300 dpi .
7.24 COMPUTER FUNDAMENTALS
I n case of dye subl i mati on type pri nter, dots are not of the same si ze i.e. they are of
vari abl e si ze. A heati ng el ement whi ch i s at l ower temperature, produces a smal l er dot than
that prdouced by the heati ng el ement whi ch i s at comparati vel y hi gher temperature.
7.3.6 MFDs (Multi Function Devices)
Mul ti functi on devi ces can perform the functi on of a pri nter, copi er, scanner and fax
machi ne. An MFD may be ei ther l aser-based or i nkjet-based machi ne.
7.4 PLOTTERS
Pl otters are output devi ces. They are used to produce preci se and good qual i ty graphi cs
and drawi ngs under computers control . They use i nk pen or i nk-jet to draw graphi cs or
drawi ngs. Ei ther si ngl e col our or mul ti col our pens can be empl oyed. The pens are dri ven by
motor. Drawi ngs can be prepared on paper, vel l um or myl ar (pol yster fi l m). Col our trans-
parency can al so be prepared.
Pen pl otters are sl ow devi ces. The graphi cs and drawi ngs produced by pen pl otters are
uni form and preci se, and they are of very good qual i ty. They are used for l ow to medi um
vol ume job. A pen pl otter can take from several seconds (for si mpl e drawi ngs) to several
mi nutes (for compl ex drawi ngs) to produce a drawi ng. But i t takes much l ess ti me as com-
pared to tradi ti onal hand methods of produci ng drawi ngs. A compl ex drawi ng whi ch can take
about a month by tradi ti onal hand method can be produced i n l ess than an hour usi ng
pl otters.
The pen pl otters may be cl assi fi ed i nto the fol l owi ng types:
Drum Plotters
A drum pl otter contai ns a l ong cyl i nder and a pen carri age. The paper i s pl aced over the
drum (i .e. cyl i nder). The drum rotates back and forth to gi ve up and down movement. The
pen i s mounted hori zontal l y on the carri age. The pen moves hori zontal l y al ong wi th the
carri age l eft to ri ght or ri ght to l eft on the paper to produce drawi ngs. Under the computer
control both the drum and the pen move to produce the desi red drawi ngs. Several pens wi th
i nk of di fferent col ours can be mounted on the carri age for mul ti col our drawi ngs. Si nce each
pen i s program sel ectabl e, a mul ti col oured drawi ng can be produced.
Microgrip Plotters
Such pl otters do not use drums. The paper or any other medi um i s hel d (gri pped) on both
si des at the edges by pi nch wheel s whi ch gi ve back and forth paper movement. Wi th such
pl otters hi gh performance i s attai ned at a l ow cost.
Flat-Bed Plotters
Such pl otters use hori zontal fl at surface on whi ch paper, vel l um, myl ar or any other
medi um can be fi xed. The pen moves al ong both axes: the X axi s and Y axi s. The pen carri age
i s control l ed by computer i n both the axes.
Inkjet Plotters
Some pl otters empl oy i nk-jets i n pl ace of i nk pens. The paper i s pl aced on a drum and
the i nk-jets wi th di fferent col oured i nk are mounted on a carri age. Such pl ottors are capabl e
of produci ng mul ti col our l arge drawi ngs.
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7.4.1 Hard Copy Devices for Fast Plotting of Drawings
I n thi s techni que the drawi ng i s fi rst di spl ayed on a CRT screen. The hard copy devi ce
copi es the drawi ng from the CRT screen and prepares a hard copy i .e. copy on a paper. I t i s
l ess expensi ve and i t produces output much more qui ckl y. Whatever i s on the CRT screen
i s copi ed by si mpl y a touch of a button. I t i ncl udes any combi nati on of graphi c and nongraphi c
(text) di spl ay. The enti re process takes onl y a few seconds. Qual i ty of drawi ngs i s not as good
as those produced by pen pl otters.
The techni ques used are el ectrostati c method, photo pl otter, i nk-jet process etc. Dot-
matri x pri nters al so produce hard copy of the drawi ngs di spl ayed on the CRT screen. The
raster approach i s used to produce the drawi ngs. The output i s i n the dot-matri x form.
7.5 OTHER FORMS OF OUTPUT DEVICES
7.5.1 Computer Output on Microfilm and Microfiche
A techni que has been devel oped to record computer output on a mi crofi l m as mi croscopi c
fi l m i mages. The i nformati on recorded on the mi crofi l m can be read wi th the ai d of a
mi crofi l m vi ewi ng system. The computer output i s fi rst di spl ayed on the CRT screen. I t i s
reduced i n si ze 48 ti mes or more and then recorded on a rol l or sheet of mi crofi l m. A hi gh-
speed camera takes the photographs of the i nformati on di spl ayed on the CRT. Thi s i s very
fast, 10 to 20 ti mes faster than hi gh-speed pri nters. The photograph can be taken at the speed
upto 32000 l i nes/ mi nute. As i t i s very costl y system, i t i s sui tabl e for a very l arge vol ume
job. The fi l m storage i s l ess costl y than to keep pri nted i nformati on on paper.
A mi crofi che i s a 4 by 6 i nch fi l m sheet. The word fi che i s pronounced as fi sh. I t i s a
French word whi ch means card. A mi crofi che can store upto 270 pages of i nformati on. Some
ul trafi che can store upto 1000 standard pages of i nformati on i n the same space. I t i s easi er
to read a mi crofi che as compared to a mi crofi l m. I t i s al so easi er to send mi crofi ches from
one pl ace to another.
7.5.2 Voice Response
Voi ce recogni ti on (voi ce i nput) by a computer i s a di ffi cul t probl em whi l e voi ce response
(voi ce out) i s very si mpl e. As the rul es for produci ng voi ce through a speaker or a tel ephone
system can easi l y be for mul ated, a voi ce r esponse system can easi l y be desi gned and
devel oped. The banks are the l argest user of voi ce response techni ques. The bank computer
gi ves voi ce response to tel ephone, enqui ry of customers regardi ng the present posi ti on of
thei r bank accounts. The voi ce response system usual l y i s consi dered for appl i cati ons requi r-
i ng l ow-speed human-machi ne i nteracti on. Audi o response system i s i nexpensi ve. Such sys-
tems can be used wi th PCs. The Texas I nstrument Co. has devel oped a Speak and Spel l
system to teach chi l dren to spel l and pronounce over 200 el ementary words. The sel ected
sounds to be used for an audi o response can be synthesi zed empl oyi ng a l ow cost si ngl e I C.
A mul ti medi a computer gi ves output i n the form of text, graphs, i mages and sound.
7.6 INPUT AND OUTPUT PORT
I nput and output devices can not be interfaced to a microprocessor directly because they are
not provided with necessary logic circuitry needed for direct interfacing to the processor buses.
They are usually interfaced to the processor buses through electronic circuitry called I /O ports.
An I /O port is supposed to contain device selection logic, bus drivers, data buffers, status register,
7.26 COMPUTER FUNDAMENTALS
control lines etc. Standard I /O ports in I C forms are available. Fig. 7.8 shows the interfacing of
I /O devices through I /O ports. An input device is connected to the processor through an input
port. The port is the place for loading or unloading data. The input device unloads data into an
input port. Then the microprocessor reads the data from the input port. Similarly, an output
device is connected to the processor through an output port. The microprocessor unloads data
into an output port. Then the output device receives data from the output port.
An I /O port may be programmabl e or nonprogrammabl e. A nonprogrammabl e port i s
permanentl y connected to the processor to behave ei ther as i nput port or output port. I f a
port i s connected as an i nput port, i t wi l l al ways act as an i nput port. Si mi l arl y, i f a port
has been connected as an output port, i t wi l l al ways act as an output port. The operati ng
mode to act as i nput port or an output port can not be al tered by the user. A programmabl e port
i s al so permanentl y connected to the processor. But i t can be made to act ei ther as i nput
port or output port by software techni que. The same port can be programmed as an i nput
port for one probl em and as an output port for another probl em. When i t has been pro-
grammed to act as i nput port, an i nput devi ce wi l l be connected to i t. When i t has been
programmed to act as an output port, an output devi ce i s connected to i t.
Fig. 7.8 I nterfaci ng of I /O devi ce through I /O port
7.6.1 Intel 8212
I t i s a nonprogrammabl e 8-bi t I /O port. I t can be used ei ther as i nput port or output
port. Once an 8212 I C i s connected as i nput port, i t wi l l al ways work as i nput port. When
i t i s connected as an output port, i t wi l l al ways work as an output port. Suppose we requi re
one i nput port and two output ports i n a parti cul ar system. I n thi s case three 8212 I Cs wi l l
be used. One uni t wi l l be connected as an i nput port and two uni ts as output ports.
7.6.2 Programmable Peripheral Interface
A programmabl e peri pheral i nterface i s a mul ti port devi ce. I ts ports can be programmed
i n a vari ety of ways as requi red by the user. I t i s very useful devi ce for i nterfaci ng i nput/
output devi ces. Some manufacturers use the term Peri pheral I nterface Adapter or Versati l e
I nterface Adapter.
Intel 8255A, 82C55A
The 8255A i s a programmabl e peri pheral i nterface (PPI ). Fi g. 7.9 shows i ts schemati c
di agram. I t contai ns three 8-bi t programmabl e ports, Port A, Port B and Port C. The Port
C can further be di vi ded i nto two 4-bi t ports: Port C
upper
and Port C
l ower
.
The 8255A operates i n three modes: Mode 0, Mode 1 and Mode 2. I n mode 0 al l the three
ports operate as si mpl e I /O ports. I n Mode 1 the Port A and Port B operate i n strobed i nput/
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output mode. Pi ns of the Port C are used for thei r control (for handshaki ng si gnal s, i nterrupt
etc.). The combi nati on of Mode 1 and Mode 0 i s al so possi bl e. For exampl e, the Port A can
operate i n Mode 1 and Port B i n Mode 0. I n Mode 2 onl y Port A operates. When the Port
A operates i n Mode 2, the Port B may operate i n Mode 1 or Mode 0. Mode 2 i s a strobed
bi di recti onal mode of operati on.
Fig. 7.9 I ntel 8255
When the 8255A i s programmed i n Mode 1 or Mode 2, the Port C sends or accepts hand
shaki ng si gnal s. The contents of Port C permi t programmer to test and veri fy the status of
each peri pheral devi ce and change the program fl ow accordi ngl y. Pi ns of Port C are al so used
to i nterrupt the CPU. See detai l s of 8255A gi ven i n I ntel s Handbook.
The 82C55A i s the CHMOS versi on of 8255A.
The programmer makes a control word that defi nes whi ch port wi l l act as an i nput or
output and what i s i ts mode of operati on. The 8255A provi des paral l el ports. See more detai l s
i n Ref. 1 and I ntel s Handbook.
7.6.3 Parallel and Serial Ports
Computers have a few bui l t i n i nterfaces cal l ed ports. Peri pheral devi ces are i nterfaced
to the computer through these ports. Data fl ow i n and out through these ports. Ports are of
two types: paral l el and seri al . A paral l el port al l ows the transfer of al l the bi ts of a word
si mul taneousl y. I n paral l el i nterface there are mul ti pl e l i nes to connect the peri pheral to the
port. A paral l el i nterface i s used to transfer data at faster rate for hi gh-speed peri pheral s such
as di sk and tape. A paral l el i nterface i s al so known as Centroni cs i nterface as i t was fi rst
popul ari zed for i nterfaci ng pri nters manufactured by Centroni cs. Wi thi n the computer data
i s transferred i n paral l el so that the computer works at hi gh speed.
A seri al port al l ows seri al data transfer. I n seri al data transfer one bi t of data i s trans-
ferred at a ti me. I n seri al i nterface onl y one l i ne or a pai r of l i nes i s used to transmi t data.
I t i s used for sl ow-speed peri pheral s such as termi nal s. Pri nters empl oy ei ther seri al i nterface
or paral l el i nterface. The di sadvantage of a seri al /paral l el port i s that onl y one devi ce can be
connected to a port. From practi cal consi derati on there i s l i mi tati on to have onl y two of each
on a PC. USB has no such l i mi tati on.
7.28 COMPUTER FUNDAMENTALS
7.7 SERIAL DATA TRANSFER
Over l ong di stance data can not be transmi tted i n paral l el mode as i t requi res too many
wi res resul ti ng i n hi gh cost of transmi ssi on. The seri al data transmi ssi on i s economi cal i n
such a si tuati on. I n seri al data transfer onl y one bi t i s transmi tted at a ti me. As i t requi res
onl y one wi re or a pai r of wi res, i t i s l ess costl y. I t reduces the cost and compl exi ty of i nterface
components. I t al so mi ni mi zes the effect of noi se. Seri al data can be transmi tted ei ther i n
asynchronous mode or synchronous mode. The term asynchronous means that the transmi s-
si on of data i s not based on a predefi ned ti mi ng pattern. The asynchronous seri al data transfer
i s commonl y used. The term synchronous means that the transmi ssi on of data i s based on a
standard ti mi ng si gnal . The synchronous seri al data transfer i s not commonl y used.
I n asynchronous seri al data transmi ssi on one character of data i s transmi tted at a ti me.
Each data character has a bi t to i denti fy i ts start and 1 or 2 bi ts to i denti fy i ts end. Thus a
character i s preceded by a start code and fol l owed by a stop code. As each character i s
i ndi vi dual l y i denti fi ed, characters can be sent at any ti me (asynchronousl y). I n other words
characters are sent i ndependentl y. Characters can be transmi tted at nonuni form rate. Thi s
method i s not effi ci ent because of the overhead for sendi ng start bi t, stop bi ts and pari ty bi t.
I n sendi ng an 8-bi t ASCI I character, four extra bi ts have al so to be sent. Thi s makes an
overhead of 50%.
I n synchronous seri al data transmi ssi on bl ocks of characters or bi ts are transmi tted at
constant rate wi thout start and stop codes. Thi s i s more effi ci ent compared to asynchronous
data transmi ssi on.
The seri al data transfer can be cl assi fi ed i nto the fol l owi ng three types:
Simplex Mode
I n thi s method of seri al data transmi ssi on data are transmi tted onl y i n one di recti on. For
exampl e the transfer of data from a computer to a remote pri nter.
Half-duplex
I n thi s method the communi cati on can take pl ace i n ei ther di recti on between the two
systems usi ng a si ngl e l i nk. But data are transmi tted onl y i n one di recti on at a ti me.
Full-duplex
I n thi s method each system can transmi t and recei ve i nformati on at the same ti me. I t
requi res two seri al l i nks: one for each di recti on. The transfer of i nformati on takes pl ace i n
both di recti ons si mul taneousl y and i ndependentl y.
7.7.1 Baud Rate
The term baud rate speci fi es the rate at whi ch seri al data are transmi tted. I t i s equal
to 1/(the ti me for a bi t cel l ). I f the ti me for one bi t cel l i s 9.01 ms, the baud rate = 1/9.01 ms
= 110 bd (baud). The baud rate i s not the same thi ng as bi ts per second because 2 to 4 actual
data bi ts are encoded wi thi n one transmi tted bi t cel l . Commonl y used baud rates are: 110,
300, 1200, 2400, 4800, 9600, 19200 and 38,400 Bd.
7.7.2 USART or UART
As a computer processes data i n paral l el , the data to be sent out usi ng seri al data
transfer techni que must be converted from paral l el to seri al . Si mi l arl y, seri al data recei ved
must be converted i nto paral l el for processi ng by the computer. A paral l el -i n-seri al out shi ft
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regi ster and a seri al -i n-paral l el out shi ft regi ster can perform thi s task. I n some cases hand
shaki ng si gnal s are al so needed. Thei r purpose i s to make sure that a transmi tter shoul d not
send data faster than i t can be recei ved by the recei ver. Several programmabl e I Cs are
avai l abl e for seri al data transfer. These devi ces contai n al l necessary ci rcui try requi red for
seri al data transfer. Nati onal I NS 8250 has been devel oped for asynchronous seri al data
tr ansfer. I t i s known as universal asynchronous receiver-transmitter (UART). I ntel has
devel oped 8251, a universal synchronous-asynchronous receiver-transmitter (USART) whi ch i s
capabl e of transmi tti ng data ei ther i n synchronous or asynchronous mode.
7.7.3 Current Loop or Voltage Signal Approach
I n current loop approach of sending data from the transmitting USART to the receiving
USART, a current is used to represent 1 in the signal line and no current to represent 0. To
isolate and protect such data transfer from electrical noise and disturbances produced by inter-
ference from AC lines, radio systems and other electrical appliances, opto-couplers are employed.
I n vol tage si gnal approach l i ne dri vers are i ncl uded i n the output ci rcui t of USART to
produce a vol tage si gnal to represent 1.
7.7.4 Modem, DCE and DTE
The tel ephone l i nes are conveni ent and l ess costl y means for seri al data transfer. But
thei r bandwi dth i s onl y about 300 to 3000 Hz. Therefore, di gi tal si gnal s can not be transmi t-
ted over these l i nes di rectl y. To sol ve thi s probl em, di gi tal si gnal s are converted to audi o
frequency tones whi ch can be transmi tted over tel ephone l i nes. A modem i s a devi ce whi ch
converts the di gi tal si gnal s to audi o-frequency tones. At the recei vi ng end a modem converts
transmi tted tones back to di gi tal i nformati on. The term modem i s the short form of modu-
l ator-demodul ator.
Data communi cati on equi pment (DCE) i ncl udes modems and some other equi pment
whi ch are used to transmi t seri al data over l ong di stances. Computers and termi nal s whi ch
are used to send or recei ve seri al data are cal l ed data termi nal equi pment (DTE). A pri nter
i s consi dered as DTE.
7.7.5 The RS-232C
The RS-232C i s a standard for seri al data transfer. I t was devel oped by El ectroni c I ndustri es
Associ ati on (EI A). I t speci fi es standard for 25 si gnal s and handshake si gnal s whi ch are used
between DCE and DTE. The vol tage l evel s, maxi mum bi t rate, ri se and fal l ti mes, i mpedance
l evel s and maxi mum capaci tance for these si gnal l i nes are al so descri bed i n thi s standard.
The standard RS-232C i nterface i s usual l y provi ded i n computers for seri al data transfer. The
DTE connector i s a mal e and DCE connector a femal e accordi ng to thi s standard. The DB-
25P mal e and DB-25S femal e connectors are mostl y used. A vol tage between 3 V and 15
V under l oad (25 V no l oad) i s used for a hi gh l ogi c or mark. A vol tage between +3 V and
+15 V under l oad (+25 V for no l oad) i s used for a l ow l ogi c or space. A vol tage suppl y 12 V
i s commonl y used to get a l ow and hi gh l ogi c. Termi nati on by a resi stor i s not necessary at
the i nput or output end. The vol tage l evel s are not TTL compati bl e. Manufacturers have
devel oped speci al I Cs for RS-232C to TTL conversi on and vi ce versa. For exampl e, MC1488
converts RS-232C si gnal s l evel to TTL l evel . MC1489 converts TTL si gnal l evel to RS 232C
l evel . The RS-232C i nterface i s sui tabl e for transmi tti ng data rel i abl y onl y upto 50 feet (16.4
m). The baud rate i s l i mi ted onl y upto 20 K Bd. I ts l i mi tati on i s due to the use of a si ngl e-
ended l i ne. The si ngl e-ended l i ne uses one l i ne to carry the si gnal . The vol tage reference i s
wi th respect to ground. The l i ne i s open, i t i s not termi nated through resi stance at the end.
Such a l i ne i s affected by el ectromagneti c i nterference. Tabl e 7.1 gi ves RS-232C pi n names
and si gnal descri pti ons.
7.30 COMPUTER FUNDAMENTALS
Table 7.1 RS-232C Pin Names and Signal Descriptions
Pin Common RS-232 C Signal Description
number name name direction
on DCE
1 AA _ PROTECTI VE GROUND
2 TXD BA I N TRANSMI TTED DATA
3 RXD BB OUT RECEI VED DATA
4
RTS
CA I N REQUEST TO SEND
5
CTS
CB OUT CLEAR TO SEND
6
DSR
CC OUT DATA SET READY
7 GND AB SI GNAL GROUND (COMMON
RETURN)
8
CD
CF OUT RECEI VED LI NE SI GNAL DETEC-
TOR
9 (RESERVED FOR DATA SET
TESTI NG)
10 (RESERVED FOR DATA SET
TESTI NG)
11 UNASSI GNED
12 SCF OUT SECONDARY RECEI VED LI NE
SI GNAL DETECTOR
13 SCB OUT SECONDARY CLEAR TO SEND
14 SBA I N SECONDARY TRANSMI TTED
DATA
15 DB OUT TRANSMI SSI ON SI GNAL ELE-
MENT TI MI NG (DCE SOURCE)
16 SSB OUT SECONDARY RECEI VED DATA
17 DD OUT RECEI VER SI GNAL ELEMENT
TI MI NG (DCE SOURCE)
18 UNASSI GNED
19 SCA I N SECONDARY REQUEST TO
SEND
20
DTR
CD I N DATA TERMI NAL READY
21 CG OUT SI GNAL QUALI TY DETECTOR
22 CE OUT RI NG I NDI CATOR
23 CH/CI I N/OUT DATA SI GNAL RATE SELECTOR
24 DA I N TRANSMI T SI GNAL ELEMENT
TI MI NG (DTE SOURCE)
25 UNASSI GNED
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7.7.6 Other Standards for Serial Data Transfer
RS-422A
The RS-422A i s a newer standar d for ser i al data tr ansfer. I n RS-422A i nter face two
wi r es ar e used. Each si gnal i s sent di ffer enti al l y over the two l i nes. The di ffer enti al l i nes
ar e ter mi nated by r esi stor s. Di ffer enti al si gnal s ar e pr oduced by di ffer enti al l i ne dr i ver s,
such as MC 3487. Di ffer enti al l i ne r ecei ver s ar e al so used (MC 3486). Suppose the i nter -
face uses di ffer enti al l i nes A and B. When a l ogi c hi gh i s tr ansmi tted the l i ne B i s mor e
posi ti ve than A. When a l ogi c l ow i s tr ansmi tted the l i ne A i s mor e posi ti ve than B. The
vol tage di ffer ence between the two l i nes i s mor e than 0.4 V and l ess than 12 V. The r ange
for the common-mode vol tage on the si gnal l i nes i s 7 V to +7 V. The di ffer enti al l i ne
r ecei ver r ejects any common-mode el ectr i cal noi se i nduced i n the two l i nes. RS-422A
al l ows a data tr ansfer r ate upto 10 MBd for a di stance of 50 ft (16.4 m) or 100 KBd for
a di stance of 4000 ft (1220 m). I C chi ps ar e avai l abl e for RS-422A to TTL conver si on and
vi ce ver sa.
RS-423A
The RS-423A i s another standard for seri al data transfer. The RS-423A i nterface al l ows
a l ow-i mpedance si ngl e-ended si gnal to be transmi tted. The l ow i mpedance si gnal can be
transmi tted over 50 ohms coaxi al cabl es. To prevent refl ecti ons the cabl e i s termi nated at
the recei vi ng end. The data transfer rate i s 300 Bd upto 4000 ft or 300 KBd for a di stance
of 40 ft.
RS-449 and RS-366
The connector pi n number and handshake si gnal s have not been speci fi ed i n RS-422A
and RS-423A standards. Rs-449 i s an addi ti onal EI A standard whi ch gi ves these speci fi cati ons.
I t gi ves speci fi cati ons for 37 si gnal pi ns on a mai n connector and 9 addi ti onal pi ns on an
opti onal connector. As the RS-449 si gnal s are a superset of the RS-232C si gnal s, RS-232C
equi pment can be i nterfaced wi th RS-449 equi pment.
RS-366 i s another standard whi ch i ncl udes si gnal s for automati c tel ephone di al i ng wi th
modems.
7.7.7 Intel 8251A, a Serial Interface Device
The 8251 A i s a pr ogr ammabl e communi cati on i nter face for ser i al data tr ansmi ssi on.
I t i s a uni ver sal synchr onous/asynchr onous r ecei ver /tr ansmi tter (USART). I t accepts data
i n par al l el for mat fr om the CPU and conver ts them i nto a conti nuous ser i al str eam for
tr ansmi ssi on. Si mul taneousl y, i t can r ecei ve ser i al data str eams and conver t them i nto
par al l el data. The data so conver ted i nto par al l el for mat ar e sent to the CPU for pr ocess-
i ng. Fi g. 7.10 shows the schemati c di agr am of I ntel 8251 A. I t sends a si gnal to the
pr ocessor whenever i t can accept a new char acter for tr ansmi ssi on or whenever i t has
r ecei ved a data char acter for the pr ocessor. The pr ocessor sends data to or r eads data
fr om the 8251A on an i nter r upt basi s or on a pol l ed basi s. The i mpor tant si gnal s of 8251
ar e as fol l ows:
7.32 COMPUTER FUNDAMENTALS
C/D (Control /data). When i t i s l ow data can be transmi tted on the data bus.
When i t i s hi gh control si gnal s can be transmi tted on the data bus.
WR
(Wri te). When i t i s l ow the processor can wri te data i nto 8251A.
RD
(Read). When i t i s l ow the processor can read data from 8251 A.
T RDY Transmi tter ready
T C
Transmi tter cl ock
T D Li ne for seri al data transmi ssi on
T E Transmi tter empty
R RDY Recei ver ready
R D Li ne for recei vi ng data
R C
Recei ver cl ock
DTR
Data termi nal ready
DSR
Data set ready
RTS
Request to send
CTS
Cl ear to send
Fig. 7.10 USART I ntel 8251
Befor e star ti ng the data tr ansmi ssi on or r ecepti on, a set of contr ol wor ds ar e for med.
These contr ol wor ds ar e l oaded i nto the 8251 by the CPU. Ther e ar e two i mpor tant
contr ol wor ds: mode wor d and command wor d. The mode wor d sel ects the oper ati ng
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mode: synchr onous or asynchr onous mode of oper ati on. Ther e ar e two for mats for thi s
pur pose: one for asynchr onous mode and the other for synchr onous mode. The command
wor d contr ol s the actual oper ati on of 8251. Besi des these two contr ol wor ds, ther e i s one
mor e contr ol wor d cal l ed status wor d. The pr ogr ammer can r ead the status of 8251 at any
ti me dur i ng oper ati on. The status of T RDY, R RDY, T E, SYNDET/BRKDET etc.
can be r ead.
The T RDY i s connected to i nterrupt pi n of the processor or 8259A, an i nterrupt
control l er. By maki ng T RDY hi gh the 8251 i nforms the processor that i t can accept data.
When data are recei ved from the processor, thi s l i ne goes l ow. The recei ved data i s con-
verted i nto seri al form and transmi tted through T D l i ne. The rate of seri al data trans-
mi ssi on i s control l ed by the cl ock i nput at
T C
pi n. The 8251A i s doubl e buffered. I t
means that one data character i s bei ng shi fted out of the transmi t shi ft regi ster whi l e
another data character can be l oaded i nto a hol di ng buffer. When the hol di ng buffer be-
comes empty, T RDY goes hi gh and then another char acter i s tr ansfer r ed fr om the
processor. When both the hol di ng buffer and the transmi t shi ft regi ster become empty, the
T E goes hi gh. I n other words T E goes hi gh when the 8251A has no character to send
out.
Seri al data i s recei ved on R D l i ne. The R RDY i s normal l y l ow. When the 8251A
contai ns a data character whi ch i s to be sent to the processor, the R RDY becomes hi gh.
I t can be connected to an i nterrupt l i ne of the processor or 8259A.
DTR DSR RTC and CTS , , are standard modem control si gnal s. I f a modem has been
i ncl uded i n the system, these control si gnal s are connected to the correspondi ng modem pi ns.
DTR goes l ow when the 8251A has to transmi t seri al data. I f modem i s al so ready to accept
data and transmi t i t onward, i t i nforms 8251A by maki ng DSR l ow. When the 8251A and
modem both are ready to transmi t data, the 8251A sends a l ow si gnal RTC to the modem
to i ni ti al i ze the data transmi ssi on. Then the modem makes CTS l ow. A l ow l ogi c on CTS
enabl es the transmi ssi on l ogi c ci rcui try of 8251 A. I f due to any reason data transmi ssi on has
to be stopped, the CTS i s made hi gh.
SYNDET i s SYNC Detect and BRKDET i s Break Detect. The SYNDET/BRKDET l i ne
goes hi gh i f there i s i ntenti onal break i n data transmi ssi on (for asynchronous mode onl y). I n
synchronous mode i t goes hi gh i f a speci fi ed sync. character (s) i s found i n the i ncomi ng stri ng
of data bi ts.
7.8 PROGRAMMABLE INTERVAL TIMER/COUNTER
7.8.1 INTEL 8254
I ntel 8254 i s a programmabl e i nterval ti mer/counter. I t has been devel oped to sol ve the
common ti mi ng control probl ems i n mi crocomputer system. I t i s compati bl e wi th al l I ntel and
most other mi croprocessors. I t uses HMOS technol ogy wi th a si ngl e +5 V suppl y and i s
packed i n 24-pi n pl asti c or CERDI P package. I ts cl ock rates are 5, 8, and 10 MHz for i ts
di fferent versi ons. I t contai ns three i ndependent 16-bi t counters. As these counters are pro-
grammabl e the user can l oad a count i nto them, start them and stop them wi th i nstructi ons
7.34 COMPUTER FUNDAMENTALS
i n the program. I t has si x operati ng modes. I t can be used to produce accurate del ay, to act
as programmabl e one-shot, rate generator, to generate square waves, software tri ggered
strobe and hardware tri ggered strobe. I ts modes are as fol l ows:
Mode 0: I nterrupt on termi nal count
Mode 1: Hardware retri ggerabl e one-shot
Mode 2: Rate generator
Mode 3: Square wave mode
Mode 4: Software tri ggered strobe
Mode 5: Hardware tri ggered strobe
Control Word
By defi ni ng the bi ts of the control format one can sel ect one of the counters, mode of
operati on, bi nary counti ng or BCD counti ng etc. I t i s often desi rabl e to read the contents of
the counter whi l e counti ng i s i n progress wi thout di sturbi ng the counti ng operati on. For thi s
purpose a counter l atch command i s gi ven. There i s al so a control word for thi s propose.
7.8.2 Intel 8253
I ntel 8253 i s al so a programmabl e i nterval ti mer/counter. The 8254 i s a superset of 8253.
The 8254 and 8253 are pi n to pi n compati bl e. They are nearl y i denti cal i n functi on. The 8253
operates at l ower frequency, 2.6 MHz. I t i s compati bl e wi th 8085 mi croprocessor. I t al so
operates i n 6 modes as menti oned i n the case of 8254. I t al so contai ns three 16-bi t program-
mabl e counters. Those who are i nterested i n more detai l s and want to program 8253, may
consul t Ref. 1.
7.9 CHIPSETS
A chi pset i s a set of two I Cs whi ch i nterface memory, i nput/output devi ces etc. to the
CPU of a computer. I t i s pl aced on the motherboard of a computer. I t provi des a hi gh-speed
bus to connect memory, PCI or PCI Express and I SA bus sl ots for i nput/output and other
peri pheral s. Chi psets of I ntel corporati on are: 845, 865, 875, 915, 915G, 915GV, 925 etc. The
915, 925 and thei r vari ants come wi th an on-board I ntel Graphi cs Medi a Accel erator. Nvi di a
chi psets are: nForce chi psets and GeForce chi psets. The nForce chi psets are for motherboards.
The Geforce i s graphi cs chi psets. Vi as chi psets are K8T800 and K8M800. The K8M800 chi pset
has i ntegrated graphi cs capabi l i ty.
7.10 DATA TRANSFER SCHEMES
I n a computer data transfer takes pl ace between two devi ces such as CPU and memory,
CPU and I /O devi ces, and memory and I /O devi ces. Usual l y, memory i s compati bl e wi th
mi croprocessor whi l e i nput and output devi ces are not. A computer i s i nterfaced wi th a
number of i nput/output devi ces of di fferent speed. I n such a si tuati on a sl ow I /O devi ce may
not be ready to transfer data when mi croprocessor i ssues i nstructi on for thi s purpose. To
sol ve the probl em of speed mi smatch a number of data transfer schemes have been devel oped.
The data transfer schemes are cl assi fi ed i nto the fol l owi ng two broad categori es:
1. Programmed data transfer schemes
2. Di rect memory access (DMA) data transfer scheme
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Programmed Data Transfer Schemes
I n a programmed data transfer scheme the data transfer takes pl ace between the CPU
and an I /O devi ce under the control of a program whi ch resi des i n the memory. The program
i s executed by the CPU. The data are transferred when the I /O devi ce i s ready for the same.
The programmed data transfer scheme i s used when smal l amount of data i s to be trans-
ferred. There are the fol l owi ng three i mportant types of programmed data transfer scheme:
(i) Synchronous data transfer scheme
(ii) Asynchronous data transfer scheme
(iii) I nterrupt dri ven data transfer scheme
DMA Data Transfer Scheme
I n DMA data transfer data are di rectl y transferred from an I /O devi ce to the memory
or vi ce versa wi thout goi ng through the mi croprocessor. The mi croprocessor (CPU) does not
parti ci pate i n thi s type of data transfer. Thi s scheme i s used when bul k data are to be
transferred. I f bul k data are transferred through mi croprocessor, i t wi l l be a ti me consumi ng
process. The mi croprocessor hol ds on when data transfer takes pl ace between an I /O devi ce
and memory usi ng DMA techni que. The I /O devi ce whi ch uses DMA techni que of data
transfer sends a HOLD si gnal to the mi croprocessor. Havi ng recei ved a HOLD request from
an I /O devi ce the mi croprocessor rel i nqui shes the use of buses (i .e. the mi croprocessor gi ves
up the control of the buses) as soon as the current cycl e i s compl eted. I t sends HLDA (an
HOLD acknowl edgement si gnal ) to the I /O devi ce to i ndi cate that HOLD request has been
recei ved, and the data and address buses has been rel i eved. I n other words the mi croprocessor
transfers the control of the buses to the I /O devi ce. Now the I /O devi ce gai ns control over
the buses and transfers data di rectl y to or from the memory wi thout i nvol vi ng CPU. Thus
data transfer takes pl ace at very hi gh speed. Thi s scheme i s used to transfer data from mass
storage devi ces l i ke hard di sks, opti cal di sks or hi gh speed pri nters etc. When data transfer
i s compl eted the CPU regai ns the control over the system buses.
When data are bei ng transferred from I /O devi ce to the memory or vi ce versa usi ng
DMA techni que, the mi croprocessor i s not doi ng anythi ng and i t i s i n the hol d state. The
mi croprocessor can come out of thi s state onl y after the DMA request i s wi thdrawn by the
I /O devi ce. The durati on of the hol d state depends on the speed of the I /O devi ce, speed of
the memory and the number of data bytes to be transferred. The DMA data transfer i n
whi ch the I /O devi ce rel i nqui shes the control of the system buses onl y after al l data bytes
have been transferred, i s cal l ed burst mode data transfer. I n thi s mode a bl ock of data i s
transferred. Thi s type of DMA data transfer i s used by magneti c di sk dri ves where data
transmi ssi on can not be stopped or sl owed down wi thout l oss of the data and hence bl ock
transfer i s a must. The bl ock data transfer may requi re the CPU to remai n i nacti ve for
rel ati vel y l onger peri od. Another DMA data transfer scheme cal l ed cycle stealing al l ows the
DMA control l er to use the system bus to transfer one or perhaps several data bytes, after
whi ch i t must return the control of buses to the CPU. I n thi s techni que a l ong bl ock of data
can be transferred by a sequence of DMA bus transacti ons i nterspersed wi th CPU bus
tr ansacti on. Though thi s method r educes the maxi mum I /O data tr ansfer r ate, i t al so
reduces the i nterference by the DMA control l er i n the CPUs acti vi ti es. The i nterference
can be el i mi nated compl etel y by desi gni ng DMA i nterface i n such a way that bus cycl es are
stol en onl y when the CPU i s actual l y not usi ng the system bus. Thi s i s known as Trans-
parent DMA.
7.36 COMPUTER FUNDAMENTALS
The cycle stealing techni que can al so be used for sl ow I /O devi ces. I n thi s scheme the
I /O devi ces request the processor for DMA data transfer. When DMA i s granted the I /O
devi ce transfers one or two bytes of data and then wi thdraws the DMA request. After some
ti me when the I /O devi ce becomes agai n ready, i t sends DMA request. I t transfers one or
two bytes agai n when DMA i s granted. Thi s process i s repeated ti l l al l the data bytes are
transferred.
The burst mode of data transfer i s used when successi ve data bytes are transferred at
short regul ar i nterval s. The cycl e steal i ng i s used when there i s si gni fi cant ti me del ay
between the transfer of two successi ve data bytes.
I n DMA data transfer scheme data transfer takes pl ace under the control of an I /O devi ce
and therefore, the I /O devi ce must contai n i ts own regi sters to store memory address and
byte count. I t must al so contai n el ectroni c ci rcui try to generate control si gnal s requi red for
DMA data transfer. General l y, I /O devi ces are not equi pped wi th such faci l i ti es. To sol ve thi s
probl em manufacturers have devel oped si ngl e chi p programmabl e DMA control l er to i nterface
I /O devi ces to the mi croprocessor for DMA data transfer. Such chi ps are: I ntel 8237A,
82C37A-5 etc. These control l ers are descri bed i n subsequent secti ons.
7.10.1 Synchronous Data Transfer Scheme
When the processor and the I /O devi ces match i n speed, thi s type of data transfer
scheme can be used. The data can be transferred from or to the I /O devi ces usi ng sui tabl e
i nstructi ons such as I N and OUT i nstructi ons. The I N i nstructi on i s used to transfer data
from an i nput devi ce or an i nput port to the processor. Si mi l arl y, the OUT i nstructi on i s
used to send data from the processor to an output devi ce or an output port. As I /O devi ces
and the processor match i n speed, I /O devi ces are ready to transfer data when the processor
i ssues I N and OUT i nstructi ons. The I /O devi ces wi th known ti mi ng characteri sti cs or
speed-compati bi l i ty wi th pr ocessor ar e usual l y not avai l abl e. Ther efor e, thi s scheme i s
rarel y used al one for I /O devi ces. I t i s usual l y used wi th the other schemes di scussed i n
subsequent secti ons. However, thi s scheme i s i nvar i abl y used wi th compati bl e memor y
devi ces.
7.10.2 Asynchronous Data Transfer Scheme
Thi s type of data transfer scheme i s used when the speeds of I /O devi ces and the
mi croprocessor do not match and ti mi ng characteri sti c of the I /O devi ces i s not predi ctabl e.
I n thi s method of data transfer the processor i ni ti ates the devi ce to get ready and then goes
on checki ng the status of the devi ce. Thus the mi croprocessor wai ts ti l l the devi ce becomes
ready to transfer data. When the devi ce becomes ready, the processor i ssues i nstructi ons for
data transfer. Fi g. 7.11 shows a schemati c di agram of asynchronous data transfer. Thi s
method i s used when I /O devi ces are sl ow as compared to mi croprocessor. I n thi s method the
preci ous ti me of the processor i s wasted i n wai ti ng. From thi s consi derati on i t i s an i neffi ci ent
method of data transfer.
I n thi s method two si gnal s are used before the actual data transfer takes pl ace. The
mi croprocessor sends an i ni ti al i zi ng (or starti ng or get ready) si gnal to the I /O devi ce. When
data are ready the I /O devi ce sends si gnal to the processor. Thi s type of si gnal s are cal l ed
handshake signals and thi s mode of data transfer i s cal l ed handshake mode of data transfer.
The handshaki ng si gnal s prevent the processor from wri ti ng new data before the devi ce has
accepted the previ ous data and become ready to accept new data.
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Fig. 7.11 Asynchronous data transfer
Fig. 7.12 Asynchronous data transfer scheme for an A/D converter
We can take an exampl e of asynchronous data transfer scheme for an A/D (anal og to
di gi tal ) converter. Fi g. 7.12 shows the schemati c di agram for the scheme. Fi rst of al l the
mi croprocessor sends a start of conversi on pul se to the A/D converter. The A/D converter
takes some ti me to convert an anal og si gnal to di gi tal si gnal . I t i s sl ow as compared to
mi croprocessor. The mi croprocessor has to wai t ti l l the task of conversi on i s over. When
conversi on i s compl eted and data are ready, the A/D converter gi ves an end of conversi on
si gnal (E/C) to the processor. The program i s prepared i n such a way that the processor i s
kept i n a l oop to check the end of conversi on si gnal E/C agai n and agai n unti l E/C becomes
hi gh. When E/C becomes hi gh, i ndi cati ng that conversi on i s compl eted, the processor i ssues
i nstructi ons for data transfer.
I n the above paragraph asynchronous data transfer has been di scussed usi ng software
approach. The asynchronous data transfer scheme can al so be i mpl emented usi ng hardware
approach. I n hardware approach READY pi n (i nput) of the processor i s used. The devi ce status
i s connected to the READY pi n of the processor. The mi croprocessor checks READY pi n before
the data are transferred. I f READY i s l ow the mi croprocessor i ntroduces wai t cycl es. The state
of the READY si gnal i s checked by the mi croprocessor i n T
2
state of a machi ne cycl e. The
mi croprocessor remai ns i n wai t state ti l l the READY si gnal becomes hi gh. Asynchronous data
transfer scheme usi ng READY si gnal i s general l y empl oyed for sl ow memory devi ces.
7.38 COMPUTER FUNDAMENTALS
Some very si mpl e I /O devi ces do not have status i ndi cati ng si gnal s. I n such a si tuati on
the mi croprocessor i s kept i n a l oop to check whether data are avai l abl e at the port. A si mpl e
keypad i nterfaced to the processor through a port may form an exampl e of thi s type of
asynchronous data transfer scheme.
7.10.3 Interrupt Driven Data Transfer Scheme
I n thi s method of data transfer scheme the processor fi rst i ni ti ates an I /O devi ce to get
ready and then goes on executi ng i ts ori gi nal program i nstead of wasti ng i ts ti me i n conti nu-
ousl y checki ng the status of the I /O devi ce. Whenever the I /O devi ce becomes ready to send
or recei ve data, i t i nforms the processor through a speci fi c control l i ne cal l ed i nterrupt l i ne.
Havi ng recei ved an i nterrupt the processor compl etes the executi on of the current i nstructi on
at hand. Thereafter, i nstead of executi ng the next i nstructi on of the program whi ch i t was
executi ng, i t takes necessary steps to transfer data to or from the I /O devi ce. Fi rst of al l i t saves
the contents of program counter i n the stack. Then the processor enters a subrouti ne cal l ed
interrupt service subroutine (ISS). The I SS saves the status of the processor i n the stack and
then performs data transfer from the I /O devi ce whi ch has i nterrupted the processor. After
compl eti ng the data transfer i t restores the processor status. Then the processor returns back
to the ori gi nal program whi ch i t was executi ng before the i nterrupt si gnal was recei ved.
We can take an exampl e of an A/D (anal og to di gi tal ) converter to i l l ustrate the pri nci pl e
of an i nterrupt dri ven data transfer, (Fi g. 7.13). Fi rst of al l the processor sends a start of
conversi on (S/C) si gnal to the converter. After i ni ti ati ng the A/D converter the processor
conti nues the executi on of the mai n program. The A/D converter takes some ti me to convert
anal og si gnal to di gi tal si gnal . When the task of conversi on i s compl eted the A/D converter
gi ves an end of conversi on si gnal (E/C) to the mi croprocessor. The E/C si gnal i s connected to
an i nterrupt l i ne I NTR of the processor. On recei vi ng an i nterrupt si gnal the processor wi l l
take al l necessary steps to transfer data from the A/D converter. On the compl eti on of data
transfer the processor wi l l return to execute the mai n program agai n.
Fig. 7.13 I nterrupt dri ven data transfer scheme for an A/D converter
I nterrupt dri ven data transfer scheme i s used to i nterface rel ati vel y sl ow I /O devi ces
such as character pri nters, A/D converters etc. I n the i nterrupt dri ven data transfer scheme
the ti me of the processor i s effi ci entl y uti l i zed as compared to asynchronous method of data
transfer. I n thi s method of data transfer the val uabl e ti me of the processor i s not wasted i n
wai ti ng whi l e I /O devi ces are getti ng ready or prepari ng data for the processor. The processor
uti l i zes i ts ti me effi ci entl y i n executi ng i ts program. When data become ready and the
processor i s i nterrupted by the I /O devi ce, i t executes I SS to transfer the data.
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Device Polling
When a number of I /O devi ces are to be connected to a si ngl e i nterrupt l i ne of the
processor, they can be connected through an OR ci rcui t. When an I /O devi ce i nterrupts the
processor, i t has to be ascertai ned whi ch I /O devi ce has i nterrupted. The processor must
check each devi ce i n turn whether i t has i nterrupted or not. Thi s method of checki ng i s cal l ed
device polling. There i s l i kel i hood that more than one devi ce may i nterrupt the processor at
the same ti me. To sol ve thi s probl em pri ori ty may be assi gned to the devi ces. The processor
may pol l the devi ces one by one i n turn i n the gi ven pri ori ty order. The devi ce pol l i ng scheme
i s a ti me consumi ng process and hence sl ow. The method of pol l i ng may be done ei ther by
software approach or hardware approach.
Vectored Interrupt
When a processor has several i nterrupt l i nes and one I /O devi ce i s connected to each
i nterrupt l i ne, there i s no questi on of ambi gui ty regardi ng whi ch devi ce has i nterrupted.
When a devi ce i nterrupts the processor, the processor i mmedi atel y comes to know whi ch
devi ce has i nterrupted and i t executes i ts I SS. Thi s type of i nterrupt scheme i s cal l ed vectored
interrupt.
There may be a scheme whi ch can empl oy vectored i nterrupt as wel l as pol l i ng. When
a l arge number of I /O devi ces are to be connected to a few i nterrupt l i nes, a group of I /O
devi ces i s connected to each i nterrupt l i ne. When an i nterrupt occurs, the processor i mme-
di atel y knows whi ch group has i nterrupted. Then i t checks by pol l i ng whi ch devi ce of that
group has i nterrupted.
7.10.4 Programmable Interrupt Controllers (PIC)
When several I /O devi ces are to be connected to the same i nterrupt l i ne of the processor,
they can be connected through an i nterrupt control l er. An i nterrupt control l er operates as an
overal l manager i n an i nterrupt dri ven system. I t accepts i nterrupt si gnal s from I /O devi ces
and determi nes whi ch of the i nterrupti ng devi ces i s of the hi ghest pri ori ty. Each I /O devi ce
has a speci al program or subrouti ne to i mpl ement i ts data transfer. Thi s i s known as I SS
(i nterrupt servi ce subrouti ne). Havi ng deci ded the pri ori ty, the control l er i nterrupts the
processor through i ts I NT l i ne. The mi croprocessor sends acknowl edgement through I NTA
l i ne. Then the control l er sends necessary i nformati on to the processor so that the processor
executes the I SS for the i nterrupti ng devi ce. The i nformati on contai ns the starti ng address
of the I SS.
Intel 8259A
The I ntel 8259A i s a programmabl e i nterrupt control l er. I t can handl e upto 8 vectored
pri ori ty i nterrupts for the CPU. I t uses NMOS technol ogy and requi res a si ngl e +5 V suppl y.
I t i s packed i n a 28-pi n DI P or 28-l ead PLCC package. Fi g. 7.14 shows the schemati c di agram
of I ntel 8259A. Fi g. 7.15 shows the i nterfaci ng of 8259A chi ps to a mi croprocessor.
I NTA
from
the mi croprocessor goes to
I NTA
pi ns of al l 8259 chi ps. I f there i s onl y one 8259A chi p, i ts
I NT wi l l be di rectl y connected to I NTR pi n of the mi croprocessor.
I ts i mportant si gnal s are as fol l ows:
IR
0
IR
7
I nterrupt requests. An I /O devi ce sends i nterrupt si gnal s through one of
these l i nes. The i nterrupti ng devi ce makes I R
n
hi gh and keeps i t hi gh
unti l i t i s acknowl edged. These are asynchronous i nputs.
7.40 COMPUTER FUNDAMENTALS
D
0
D
7
Bi di recti onal data bus. Control , status and i nterrupt vector i nformati on
i s transmi tted through these l i nes.
CS
Chi p sel ect.
WR
Wri te. When WR i s l ow the 8259 accepts command word from the CPU.
RD
Read. When RD i s l ow the 8259 sends vari ous status si gnal s on the data
bus for the CPU.
INT I nterrupt. The 8259 i nterrupts CPU through thi s l i ne.
Fig. 7.14 Programmabl e i nterrupt control l er I ntel 8259A.
Fig. 7.15 I nterfaci ng of 8259A to mi croprocessor
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INTA.
I nterrupt acknowl edge. The CPU sends acknowl edgement through thi s
l i ne to 8259. Thi s enabl es 8259 to send necessary i nformati on to CPU.
CAS
0
CAS
2
. Cascade l i nes.
A
0
. Address l i ne. Thi s pi n acts i n conjuncti on wi th CS WR , and RD.
SP EN. /
Sl ave program/enabl e buffer.
The 8259A i s compati bl e wi th 8086, 8088 and 8085 mi croprocessors. I ts ci rcui try i s stati c,
requi ri ng no cl ock i nput. The 8259A chi ps can be cascaded to handl e 64 vectored pri ori ty
i nterrupts wi thout addi ti onal ci rcui try. I ts other versi ons are: 8259A-2 and 8259A-8.
Intel 82C59A-2
I t i s a hi gh per for mance CHMOS ver si on of I ntel 8259A-2. I t i s compati bl e wi th
80C86/88, 8086/88 and 8080/8085 mi croprocessors.
7.10.5 Programmable DMA Controllers
The basi c pri nci pl e of DMA data transfer has al ready been di scussed i n the begi nni ng of
the secti on 7.10. The necessi ty of DMA control l er has al so been expl ai ned. The DMA data
transfer scheme i s used where bul k data transfer i s requi red di rectl y from an I /O devi ce to
memory and vi ce versa. I n thi s secti on some DMA control l ers are descri bed.
Intel 8237A, 8237A-4, 8237A-5
The 8237A i s a hi gh performance programmabl e DMA control l er. I t has 4 i ndependent
DMA channel s. I t has the feature of i ndependent autoi ni ti al i zati on of al l channel s. Each
channel can be i ndi vi dual l y programmed to autoi ni ti al i ze to i ts ori gi nal condi ti ons fol l owi ng
an end of process
(EOP)
. Each channel has a ful l 64 K address and word count capabi l i ty.
Memory-to-memory data transfer capabi l i ty i s provi ded. Data upto 1.6 MB/sec can be trans-
ferred at 5 MHz by 8237A-5. I t can be expanded to any number of channel s by cascadi ng
addi ti onal control l er chi ps. I t has the abi l i ty of address i ncrement and decrement. I t has al so
the feature of software DMA requests. I t i s compati bl e to 8086, 8088, and 8085 processors.
I t uses NMOS technol ogy. I t i s avai l abl e i n 40-pi n l ead cerdi p and pl asti c packages.
Fi g. 7.16 shows the schemati c di agram of 8237A. I ts i mportant si gnal s are as fol l ows:
DREQ
0
DREQ
3
. DMA request. An I /O devi ce uses one of these l i nes to send i ts DMA
request. DREQ shoul d be mai ntai ned hi gh unti l correspondi ng DACK
goes acti ve.
DACK
0
DACK
3
. DMA acknowl edge. When DMA i s granted the I /O devi ce i s i nformed
by 8237A through thi s l i ne.
DB
0
DB
7
Bi di recti onal 3-state data bus l i nes. Duri ng DMA cycl es they carry 8
MSBs of memory address whi ch are to be l atched i n an external l atch.
The address bi ts are transferred i n the begi nni ng of the DMA cycl e. The
bus i s then rel eased to carry data duri ng the rest of the DMA cycl e.
A
0
A
3
These are 4 bi di recti onal LSBs of the address l i nes. I n i dl e cycl e these
are i nputs and are used by the CPU to address the regi ster to be
l oaded or read. I n acti ve cycl e they are outputs and carry the l ower
4 bi ts of the output address.
7.42 COMPUTER FUNDAMENTALS
Fig. 7.16 Programmabl e DMA control l er 8237A
A
4
A
7
These are 4 MSBs address l i nes. They gi ve 3-state outputs. These are
enabl ed onl y duri ng DMA cycl e.
HRQ Hol d request. The 8237A sends hol d request to the CPU through thi s
l i ne.
HLDA Hol d acknowl edge. The CPU sends acknowl edgement to the 8237A
through thi s l i ne. I t i ndi cates that the CPU has rel i nqui shed the
control of the system buses.
MEMR
Memory read. I t i s l ow when data are transferred from memory to the
I /O devi ce.
MEMW
Memory wri te. I t i s l ow when data are transferred form the I /O devi ce
to the memory.
IOR
I /O read. I t i s l ow when data are transferred from the I /O devi ce to
the memory.
IOW
I /O wri te. I t i s l ow when data are transferred from memory to the
I /O devi ce.
AEN Address enabl e. I t performs several tasks. I t enabl es 8-bi t l atch con-
tai ni ng upper 8 address bi ts onto the system address bus. I t di sabl es
other system bus dri vers duri ng DMA transfer.
ADSTB Address strobe. I t i s acti ve hi gh. I t i s used to l atch the upper 8 address
bi ts i nto an external l atch.
EOP
End of process. When the transfer of programmed number of bytes i s
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compl eted the 8237A makes EOP l ow. I t unasserts i ts hol d request to
the processor and makes AEN l ow to r el ease buses back to the
pr ocessor.
READY Ready. I t i s an i nput used to extend the memory read and wri te pul ses
from 8237A to accommodate sl ow memori es or I /O devi ces.
The 8237A has a number of i nternal regi sters. I t stores the memory address, byte count
etc. i n i nternal regi sters. When the CPU grants DMA data transfer to some I /O devi ce, i t
l oads the devi ce number, memory address, byte count, di recti on of data transfer and other
necessary i nformati on i nto the regi sters of 8237A. For data transfer from the memory to the
I /O devi ce MEMR and I OW are made l ow. For the data transfer from the I /O devi ce to the
memory MEMW and I OR are made l ow. The 8237A sends 8 MSBs of the memory address
over DB-bus. These 8 MSBs of the address are l atched i nto an external l atch. The 8 LSBs
of the address are sent on A
0
A
7
l i nes. As the 8237A does not have 20 address l i nes, so i t
sets up the bus address l i nes usi ng some dedi cated l atches. When the processor 8086 suppl i es
memory addresses, those are 20-bi t addresses. The address bi ts A
16
A
19
remai n l atched i n
external l atches. These bi ts are avai l abl e and they are uti l i zed by 8237A duri ng DMA data
transfer. EOP goes l ow when al l programmed bytes of data are transferred. I n fi xed pri ori ty
DREQ
0
has the hi ghest pri ori ty and DREQ
3
has the l owest pri ori ty.
Some terms used i n DMA data transfer are as fol l ows:
Idle Cycle
When there i s no request from any channel , the 8237A enters the i dl e cycl e. I n thi s cycl e
the control l er sampl es the DREQ l i nes every cl ock cycl e to detect i f any channel i s requesti ng
a DMA cycl e. The control l er al so sampl es
CS
to check whether the mi cr opr ocessor i s
attempti ng to wri te or read i nternal regi sters of the control l er.
Active Cycle
When the control l er gets DMA request, i t outputs an HRQ to the mi croprocessor and
enters the acti ve cycl e. DMA data transfer takes pl ace i n the acti ve cycl e.
The operati ng modes of 8237A are as fol l ows:
Single Transfer Mode
I n thi s mode the devi ce i s programmed to perform one transfer onl y. The word count
i s decremented and the address i ncremented or decremented after each transfer.
Block Transfer Mode
I n thi s mode the 8237A i s acti vated by DREQ to conti nue data transfer duri ng the servi ce
unti l a TC (termi nal count) caused by word count or an external end of process (EOF) i s
encountered. DREQ need onl y be hel d acti ve unti l DACK becomes acti ve. An autoi ni ti al i zati on
occurs at the end of the servi ce i f the control l er i s programmed for i t.
Demand Transfer Mode
I n thi s mode the devi ce i s programmed to conti nue data transfer unti l a TC or external
EOP
i s encountered or unti l DREQ goes i nacti ve. Thus the data transfer may conti nue unti l
the I /O devi ce exhausts i ts data capaci ty.
7.44 COMPUTER FUNDAMENTALS
Cascade Mode
I n thi s mode more than one 8237A are cascaded as shown i n Fi g. 7.17. Thi s permi ts the
DMA requests of the addi ti onal 8237A uni ts to propagate through the pri ori ty network
ci rcui try of the precedi ng uni t.
Fig. 7.17 Cascade connecti on of 8237A uni ts.
Intel 82C37A-5
I t i s CHMOS versi on of 8237A-5. I t i s pi n to pi n compati bl e wi th NMOS 8237A-5.
Intel 8257/8257-5
I t i s a 4-channel DMA control l er. The 8257-5 i s compati bl e wi th 8085 processors. Each
channel generates a sequenti al memory address whi ch permi ts the I /O devi ce to transfer data
to or from the memory. Each channel contai ns two 16-bi t regi sters: DMA address regi ster and
byte count regi ster. These regi sters are i ni ti al i zed before a channel i s enabl ed. I ni ti al l y, the
DMA address regi ster i s l oaded wi th the address of the fi rst memory l ocati on to be accessed.
Duri ng DMA operati on i t stores the next memory l ocati on to be accessed i n the next DMA
cycl e. Fourteen LSBs of the byte count regi ster store the number of bytes to be transferred;
2
14
= 16384 bytes of data can be di rectl y transferred to or from the memory.
I ts operati ons are si mi l ar to those expl ai ned i n case of 8237A. Pi ns are al so si mi l ar. Thi s
chi p contai ns
DACK DACK
0 3

pi ns and a termi nal count pi n, TC. TC becomes hi gh when


al l programmed bytes are transferred. The mai n features of 8257 are: pri ori ty DMA request
l ogi c, auto l oad mode, channel i nhi bi t l ogi c, etc.
7.10.6 Multifunction VLSI Chips
Wi th the rapi d advancement i n VLSI technol ogy i t has become possi bl e to bui l d several
functi ons on a si ngl e chi p I C. DMA control l er, i nterrupt control l er, programmabl e ti mer/
I /O DEVI CES, MI CROCONTROLLERS, I /O PROCESSORS AND ARI THMETI C PROCESSORS 7.45
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counters, system power management, DRAM control l er, etc. can be pl aced on a si ngl e-chi p.
Today a handful of I Cs are used on the motherboard. VLSI chi ps for several functi ons are
avai l abl e today, and they are used i n a di gi tal computer, for exampl e, I ntel 915, 915G, 915GV,
925 etc. These are for Penti um 4 based computers.
7.11 SINGLE-CHIP MICROCOMPUTERS (MICROCONTROLLERS) AND
EMBEDDED MICROPROCESSORS
7.11.1 Single-Chip Microcomputers
Wi th the devel opment of VLSI technol ogy i t became possi bl e to fabri cate a di gi tal com-
puter on a si ngl e I C chi p. A di gi tal computer fabri cated on a si ngl e I C chi p i s cal l ed single-
chip microcomputer. Si ngl e-chi p mi crocomputers are wi del y used i n i ndustri al control ,
process control , consumer and home appl i ances control , i nstrumentati on, etc. Si nce a si ngl e-
chi p mi crocomputer i s used for control appl i cati ons, i t i s al so cal l ed microcontroller. I t i s
very smal l and compact. I t forms a part of the devi ce or equi pment whi ch i s to be control l ed.
A si mpl e mi crocontrol l er contai ns a CPU, memory (RAM and ROM/EEPROM/Fl ash memory)
and I /O l i nes. A powerful mi crocontrol l er may contai n a few other components (whi ch are
needed for i ndustri al and other control appl i cati ons) such as A/D converter, D/A converter,
DMA channel s, pul se-wi dth modul ator, watch-dog ti mer, hi gh-speed i nput/output system, wave
generator, i nterrupt processor, etc.
I ntel i ntroduced 8048 seri es of si ngl e-chi p 8-bi t mi crocomputers i n 1976. I ts fami l y members
were : 8048, 8748, 8042, 8049, etc. I n 1980, I ntel devel oped more powerful 8-bi t mi cro-
control l ers, I ntel 8051 seri es. Mi crocontrol l ers of thi s seri es are faster, have enhanced i n-
structi on set i ncl udi ng i nstructi ons for mul ti pl i cati on and di vi si on, ful l dupl ex seri al port,
power savi ng modes, etc. I ts fami l y members are : 80C51BH, 80C31BH, 87C51, 8X52/54/58,
8XC51FX, 8XL52/54/58, 8XL51FA/FB/FC, 8XC51RA/RB/RC, 8XC51GB, 8XC51SL, 8XC152JA/
JB/JC, etc. X = 0 for ROMl ess versi on, X = 3 for versi ons wi th ROM, and X = 7 for versi ons
wi th EPROM or OPT (one ti me programmabl e). I ts di fferent versi ons have di fferent features
desi gned for speci fi c appl i cati ons. Speci fi c features such as A/D conversi on, pul se-wi dth modu-
l ati on, seri al communi cati on faci l i ty, etc. are needed by certai n appl i cati ons. I ntel has al so
devel oped 8XC151 and 8XC251 seri es of mi crocontrol l ers. These are more powerful and faster
than 8051 seri es of mi crocontrol l ers. 8-bi t mi crocontrol l ers are used for si mpl e i ndustri al
control appl i cati ons, consumer appl i ances, counti ng events, measurement of el ectri cal and
physi cal quanti ti es, i nstrumentati on, etc.
Other compani es have al so devel oped mi crocontrol l ers. Exampl es are : Texas I nstru-
ments 4-bi t mi crocontrol l er - TMS1000, Motorol as 8-bi t mi crocontrol l er - 6801 and MCS68HC11,
Zi l ogs Z8, NECs 7800 seri es, etc.
I n 1983, I ntel i ntroduced 16-bi t mi crocontrol l ers, 8096 seri es. Mi crocontrol l ers of thi s
seri es are more powerful and faster than 8-bi t mi crocontrol l ers. They are used i n sophi sti -
cated i ndustri al control , i ntel l i gent computer peri pheral s, i nstrumentati on, etc. Exampl es
are : control of l arge horse power el ectri c motors, robots, gui dance and control of mi ssi l es,
etc. I ntel devel oped i mproved versi ons of 16-bi t mi crocontrol l ers, 80196 seri es. I ts fami l y
members are : 80C194, 83C194, 8XC198, 8XC196KB/KC/KD/KR/KQ/JR/JQ/KT/NT/NP/NU/
MC/MD/MH, 80296SA, etc.
Motorol a has devel oped 32-bi t RI SC mi crocontrol l er, MPC505. I t i s used i n advanced
communi cati on devi ces, speech pr ocessi ng system, automoti ve modul es, etc. I BM has
7.46 COMPUTER FUNDAMENTALS
devel oped 32-bi t RI SC embedded mi crocontrol l er, 403GA. I t i s used i n offi ce automati on
equi pment (pr i nter s, copi er s, fax machi nes, etc.), consumer el ectr oni cs, vi deo games,
tel ecommuni cati on, networki ng, personal di gi tal assi stant (PDA), etc.
7.11.2 Intel 8044 Microcontroller with Communication Controller
The 8044 i s based on the 8051 core. The 8044 repl aces 8051s seri al port wi th seri al
i nterface uni t, SI U. The SI U i s an i ntel l i gent hi gh performance HDLC/SDLC seri al commu-
ni cati on control l er. HDLC stands for hi gh-l evel data l i nk control and SDLC for synchronous
data l i nk control . The CPU and SI U operate concurrentl y. The 8044 fami l y has the fol l owi ng
member s:
(i) 8344AH: An 8051 mi crocontrol l er wi th SI U.
(ii) 8044AH: An 8344 wi th 4K bytes on-chi p ROM program memory.
(iii) 8744AH: An 8344 wi th 4K bytes on-chi p EPROM program memory.
Thi s fami l y i s al so known as RUPI -44 fami l y. I t i s used for sophi sti cated real -ti me control
appl i cati ons such as i nstrumentati on, i ndustri al control , and i ntel l i gent computer peri pheral s.
The major features are:
(i) A powerful 8-bi t CPU.
(ii) Two 16-bi t ti mer/counters.
(iii) Fi ve source i nterrupt capabi l i ty wi th two programmabl e pri ori ty l evel s. Any one of
the pri ori ty l evel s can be used.
(iv) The CPU executes most i nstructi ons i n 1 sec. I t can perform 8 8 mul ti pl i cati on
i n 4 sec.
(v) I t contai ns a Bool ean processor.
(vi) 4K bytes ROM program memory and 192 bytes RAM data memory.
(vii) 64K bytes program memory address space. The l ower 4K bytes of the 64 KB program
memory address space i s fi l l ed by i nternal (on-chi p) ROM or EPROM. The remai ni ng
i s for external program memory. The program memory uses 16-bi t address.
(viii) 64 KB external data memory address space. The external data memory can use
ei ther 8 or 16-bi t address. The i nternal data memory use 8-bi t address, whi ch
provi de 256 addresses. The l ower 192 addresses are for on-chi p RAM. There are 35
speci al functi on regi sters whi ch use vari ous l ocati ons i n the upper address space.
(ix) 32 programmabl e I /O l i nes.
(x) The SI U supports data rates upto 2.4 MB/sec when external l y cl ocked and 375 KB/
sec. when sel f cl ocked.
(xi) 40-pi ns, 12 MHz cl ock and +5 V suppl y.
7.11.3 Embedded Microprocessors
There are certai n control appl i cati ons whi ch requi re l arge amount of data handl i ng. For
such an appl i cati on a mi croprocessor-based system i s used i nstead of a mi crocontrol l er. Embedded
mi croprocessors have been devel oped for data control appl i cati ons. A mi croprocessor-based
system whi ch i s used for data control appl i cati on, uses embedded mi croprocessors. Memory
requi rement for data control appl i cati ons di ffers from appl i cati on to appl i cati on, and therefore,
memory i s not i ncl uded on the embedded processor chi p. Dependi ng upon the requi rement
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external memory chi p i s used i n the embedded processor based system. Data control appl i cati ons
requi re mul ti functi on control such as DMA control , data processi ng, data formatti ng, I /O control ,
etc. Embedded processors have been desi gned to meet such requi rements.
I ntel has devel oped 16-bi t and 32-bi t embedded processors for data control appl i cati ons.
32-bi t embedded processors are : 80960 (or i 960), embedded versi ons of 486 and 386 proces-
sors, 80376, etc. 16-bi t embedded processors are : 80186 and 80188. The 80986 i s a powerful
embedded processor and i t i s wi del y used for sophi sti cated appl i cati ons whi ch requi re l arge
data processi ng. Exampl es are : l aser pri nters, compl ex i ndustri al automati on, i mage process-
i ng, graphi cs, networki ng, etc.
Embedded versi ons of 486 are : 486GX, 486SX, etc. The embedded versi ons of 386 are:
386CXSA, 386CXSB, 386EX and 386SXSA. The 80186 i s a 16-bi t hi ghl y-i ntegrated processor.
I t contai ns a CPU, i nterrupt control l er, DAM channel s, cl ock generator, RAM refresh control
uni t, etc. I ts versi ons are : 80C186, 80C186XL/EA/EB/EC, etc. The 80188 i s al so an i ntegrated
chi p and i t has onl y 8 data l i nes whereas 80186 has 16 data l i nes. I ts di fferent versi ons are:
80C188, 80C188XL/EA/EB/EC.
7.12 DSP (DIGITAL SIGNAL PROCESSOR)
The processors speci al l y desi gned to process di gi tal si gnal s i s cal l ed DSP. I t recei ves
di gi ti sed si gnal s, performs some mathemati cal operati ons and sends resul t to an output
devi ce or a host mi croprocessor. Most of DSP systems accept anal og si gnal usi ng ADC (Ana-
l og-to-Di gi tal Converter), process them usi ng DSP and send the resul t to a D/A converter or
a host mi croprocessor. DSPs i mpl ement i ntegrati on, di fferenti ati on, compl ex Fast Fouri er
Transform etc. usi ng hardware. Many compani es make DSP chi ps; for exampl e, Texas I nstru-
ments TMS32025, NECPD7281, Motorol a MC56000, Nati onal LM32900, Matsushi ta MN1900,
Fuji tsu MB8764, etc.
Earl i er DSP chi ps al so contai ned anal og mul ti pl exer, anal og demul ti pl exer, A/D con-
verter, D/A converter, etc. The l ater DSP chi ps excl uded anal og i nput and anal og output
secti ons because they can be best i mpl emented wi th di fferent types of technol ogy. I nstead
they concentrated on i ncreasi ng processi ng speed, i ncreasi ng RAM and ROM capaci ty, i mprov-
i ng bi t mani pul ati ng capaci ty and addi ng fl oati ng-poi nt processi ng capabi l i ty. A DSP system
empl oys other I Cs for anal og i nput and anal og output secti ons. The i nput secti on i ncl udes an
anal og mul ti pl exer, fi l ters, sampl e and hol d, and A/D converter. The output secti on i ncl udes
D/A converter, demuti pl exer, fi l ters, ampl i fi ers, etc.
7.13 I/O PROCESSOR
A mi crocontrol l er or a mi croprocessor-based system whi ch i s used to control an i nput/
output devi ce i s cal l ed I /O processor. I t rel i eves CPU from the task of i nput/output operati ons.
A modern computer has several I /O devi ces. Some of them are very fast devi ces. To perform
I /O operati ons I /O programs are to be executed. I f CPU i s kept busy i n executi ng I /O
programs, i ts appreci abl e ti me i s wasted i n i t and i t gets l ess ti me to perform i ts own task
of data processi ng. Therefore, to make a modern computer effi ci ent and faster, i mportant
I /O devi ces are provi ded wi th I /O processors. For exampl e, a keyboard contai ns a mi crocontrol l er
whi ch scans the pressed key and gi ves i ts ASCI I code (or any other bi nary code). The code
i s stored i n the memory of the mi crocontrol l er. When certai n number of keys are pressed or
7.48 COMPUTER FUNDAMENTALS
after certai n ti me i nterval s the mi crocontrol l er i nterrupts the CPU and sends ASCI I codes of
the pressed keys to the CPU for processi ng. An another exampl e i s a l aser pri nter. I t i s a
fast devi ce. I t uses a mi croprocessor-based system. I ntel s 960, a fast embedded mi croproces-
sor i s used for thi s purpose. A l aser pri nter has to handl e a l arge amount of data (i .e. data
for pi xel s) to pri nt a page. The CPU l oads i nformati on whi ch i s to be pri nted i nto the memory
of i 960-based I /O processor. Now I /O processor performs the task of data handl i ng for pri nti ng
the i nformati on. When pri nti ng work i s over, i t i nterrupts CPU and asks for more i nforma-
ti on, i f any for pri nti ng.
General purpose I /O processor cal l ed uni versal peri pheral i nterface has al so been devel oped
such as UPI -452. I t i s a sl ave I /O processor. A sl ave processor works on the di recti on of the
CPU. An UPI contai ns i nterfaci ng ci rcui t besi des a mi crocontrol l er. The i nterfaci ng ci rcui t
connects i t to the host CPU.
7.13.1 UPI-452
The UPI -452 (uni versal peri pheral i nterface) i s a CHMOS programmabl e I /O processor.
I t i s a general purpose sl ave I /O processor. Actual l y the UPI -452 i s a sl ave mi crocontrol l er.
I t i ncorporates an 80C51 (a si ngl e-chi p mi crocomputer) wi th doubl e program and data memory,
a sl ave i nterface whi ch permi ts the connecti on of UPI -452 di rectl y to the host system bus as
a peri pheral , a FI FO buffer modul e, a two channel DMA control l er and a fi fth I /O port.
Fi g. 7.18 shows the functi onal bl ock di agr am of UPI -452. I ts mai n featur es i ncl ude
256 8-bi t i nternal RAM, 8-KB ROM/EPROM, two 16-bi t ti mers/counters, Bool ean processor,
bi t addressabl e RAM, 8 i nterrupt sources, programmabl e ful l dupl ex seri al channel , 34 addi -
ti onal speci al functi on regi sters, 40 programmabl e I /O l i nes, 128-byte bi di recti onal FI FO sl ave
i nterface, two DMA i ndependent channel s, 64K program memory space, 64K data memory
space, 68-pi n PGA and PLCC package, software compati bl e wi th the MCS-51 fami l y of si ngl e-
chi p mi crocomputers etc.
Fig. 7.18 Functi onal di agram of UPI -452
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The on-chi p DMA control l er permi ts hi gh speed data transfer between any of the three
wri tabl e memory spaces: i nternal data memory, external l ocal expansi on bus data memory
and the speci al functi on regi ster array. The speci al functi on regi ster array i s treated as a set
of uni que dedi cated memory addresses whi ch can be used as ei ther the source or desti nati on
address of a DMA transfer. Each DMA channel can be i ndependentl y programmed. For thi s
purpose there are dedi cated speci al functi on regi sters for mode, source and desti nati on
addresses and byte count to be transferred. Upto 64 KB can be transferred i n a si ngl e DMA
operati on. Each DMA channel may operate i n ei ther bl ock mode or demand mode. I n bl ock
mode of data transfer there are two techni ques: burst mode or al ternate cycl e mode. I n burst
mode processor hal ts i ts executi on and DMA data transfer takes pl ace. I n al ternate cycl e
mode DMA cycl e and i nstructi on cycl e take pl ace al ternatel y. The demand mode data transfer
may be of two types: (i) FI FO or seri al channel demand mode and (ii) external demand mode.
I n demand mode, a DMA data transfer takes pl ace when i t i s demanded. Demand can be
accepted from an external devi ce (through external i nterrupt pi ns) or from ei ther the seri al
channel or FI FO fl ags. I n these cases the DMA data transfer can be synchroni zed to an
external devi ce, the FI FO or the seri al port.
7.13.2 UPI-41, 42
These are general purpose uni versal peri pheral i nterfaces to control I /O devi ces. They
are essenti al l y sl ave mi crocontrol l ers wi th i nterface i ncl uded on the chi p. They contai n
mi crocontrol l ers 8041AH, 8042AH, 8741AH or 8742AH. The UPI 41 operates at 6 MHz and
UPI -42 at 12 MHz. They are compati bl e wi th al l I ntel and most other mi croprocessors. They
contai n 8-bi t CPU pl us ROM/EPROM, RAM, I /O, Ti mer/Counter, and DMA wi th i nterrupt or
pol l ed operati on support i n a si ngl e package. UPI -42 has 8042AH or 8742AH mi crocontrol l er.
UPI -4I contai ns 8041AH or 8741AH mi crocontrol l er. The ROM/EPROM i n di fferent versi ons
are as shown i n Tabl e 7.2.
Table 7.2 UPI-41, 42 Family
UPI device ROM bytes EPROM bytes RAM bytes
8042 AH 2K 256
8742 AH 2K 256
8041 AH 1K 128
8741 AH 1K 128
Other i mportant features are: 8-bi t ti mers/counters, 18 programmabl e I /O l i nes, one 8-
bi t status and two data regi sters for asynchronous sl ave-to-master i nterface, expandabl e
I /O, sync, mode avai l abl e, over 90 i nstructi ons, i ntel l i gent programmi ng al gori thm, avai l abl e
i n 40-l ead cerdi p, 40-l ead pl asti c and 44-l ead pl asti c l eaded chi p carri er packages, etc.
7.14 ARITHMETIC PROCESSORS
General purpose mi croprocessors such as 8086, 8088, 80286, 80386 etc. are not opti mi zed
to perform compl ex numeri cal cal cul ati ons, CRT graphi cs mani pul ati ons or word processi ng.
For these purposes speci al i zed coprocessors have been devel oped. For exampl e, the 8087 i s
a numeri c data coprocessor for numeri cal cal cul ati on, and 82786 i s a graphi c coprocessor.
These coprocessors operate i n paral l el wi th CPUs. Powerful 32-bi t and 64-bi t processors such
as I ntel 486, Penti um fami l y of processors, etc. contai n FPU (math processor uni t) on the
processor chi p i tsel f.
7.50 COMPUTER FUNDAMENTALS
Ther e ar e two ways to i nter face an ar i thmeti c pr ocessor to a CPU. I n one appr oach
i t i s tr eated as a per i pher al devi ce. Such uni ts ar e cal l ed per i pher al pr ocessor. The CPU
sends data and i nstr ucti ons for pr ocessi ng to such an uni t and r ecei ves r esul ts fr om i t.
Exampl es of per i pher al ar i thmeti c pr ocessor s ar e AMD 9511/12, I ntel 8231A, etc. I n an-
other appr oach the ar i thmeti c pr ocessor i s connected as an extensi on of the CPU. The
i nstr ucti ons and r egi ster s of ar i thmeti c pr ocessor ar e extensi ons to those of the CPU. The
i nstr ucti on set of the CPU i ncl udes a speci al subset of opcodes r eser ved for ar i thmeti c
pr ocessor. Ar i thmeti c pr ocessor of thi s type i s cal l ed coprocessor. Unl i ke a per i pher al
pr ocessor, a copr ocessor i s desi gned for a par ti cul ar CPU fami l y, wher eas a per i pher al
pr ocessor can be used wi th any host CPU. Each CPU i s desi gned wi th a copr ocessor
i nter face that contai ns speci al contr ol ci r cui tr y to l i nk CPU wi th the copr ocessor, and
speci al i nstr ucti ons for copr ocessor. Exampl es of numer i c data copr ocessor s ar e I ntel
8087, 80287, 80387 etc.
7.14.1 Intel 8087
I t i s a hi gh performance numeri c data coprocessor. I ts other versi ons are 8087-1 and
8087-2. I t uses HMOS I I I technol ogy and i s packed i n 40-pi n package. Cl ock rates for 8087
are 5 MHz, for 8087-2, 8 MHz and for 8087-1, 10 MHz. I t has been desi gned to work wi th
8086, 8088, 80186 and 80188 mi croprocessors. I t has 68 numeri c processi ng i nstructi ons
whi ch are added to 8086/8088 i nstructi ons set. The 8087 i ncl udes the standard 8086/8088
i nstructi on set for general data mani pul ati on and program control . I ts 68 numeri c i nstruc-
ti ons ar e for extended pr eci si on i nteger, fl oati ng-poi nt, tr i gonometr i c, l ogar i thmi c and
exponenti al functi ons. I t i ncl udes i nstructi ons for ari thmeti c operati ons. I t contai ns ei ght
80-bi t regi sters whi ch are added to the regi ster set of the CPU. I t can handl e 16, 32 and
64-bi t i ntegers; 64, 80-bi t fl oati ng-poi nt and 18-di gi t BCD operands. I t al so provi des the
capabi l i ty to contr ol r ound off, under fl ow, and over fl ow er r or s i n each cal cul ati on. The
tri gonometri c, l ogari thmi c and exponenti al functi ons are bui l t i nto the coprocessor hard-
ware. At hardware l evel i t i s treated as the extensi on to the CPU, provi di ng regi ster, data
types, control and i nstructi on capabi l i ti es. As a coprocessor to 8086 or 8088 the 8087 i s
connected i n paral l el wi th the CPU. At the programmers l evel the 8087 and the CPU are
treated as a si ngl e uni fi ed processor. The 8087 executes i nstructi ons as a coprocessor to a
maxi mum mode CPU.
7.14.2 Intel 80287, 80C287A
The 80287 i s a HMOS numeri c processor extensi on for 80286 mi croprocessor. I t has
80-bi t i nternal archi tecture. I ts vari ous versi ons are 80287-3, 80287-6, 80287-8 and 80287-10
to operate at di fferent cl ock rates. I t has over 50 i nstructi ons whi ch are added to the
i nstructi on set of 80286. I t i s object code compati bl e wi th 8087. I t executes i nstructi ons i n
paral l el wi th an 80286. I t di rectl y extends 80286 i nstructi on set to tri gonometri c, l ogari thmi c,
exponenti al and ari thmeti c i nstructi ons for al l data types. The data types i ncl ude 32, 64 and
80-bi t fl oati ng poi nt; 32, 64-bi t i ntegers and 18-di gi t BCD operands. I t can perform ful l -range
transcendental operati ons for si ne, cosi ne, tangent, arctangent and l ogari thm. I t contai ns 8
80-bi t i ndi vi dual l y addressabl e numeri c regi ster stack. Protected mode operati on compl etel y
conforms to the 80286 memory management and protecti on. I t i s packed i n 40-pi n cerdi p
package.
The 80C287A i s a CHMOS I I I math coprocessor desi gned for hi gher speed and l ow power
consumpti on.
I /O DEVI CES, MI CROCONTROLLERS, I /O PROCESSORS AND ARI THMETI C PROCESSORS 7.51
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7.14.3 Intel 80387 DX
I t i s a hi gh performance 80-bi t CHMOS I V numeri c processor extensi on for 80386 DX
mi croprocessor. I t has 80-bi t i nternal archi tecture. I ts performance i s 5 to 9 ti mes more than
that of 8087 and 80287. I t handl es 32, 64 and 80-bi t fl oati ng-poi nt; 32 and 64-bi t i ntegers and
18-bi t BCD operands. I t di rectl y extends 80386 DX CPU i nstructi on set to i ncl ude tri gonomet-
ri c, l ogari thmi c, exponenti al and ari thmeti c i nstructi ons for al l data types. I t i s upward object-
code compati bl e wi th 8087 and 80287. I t has bui l t-i n excepti on handl i ng. I t effecti vel y extends
the regi sters and i nstructi on set of 80386 mi croprocessor. I t adds over 70 mnemoni cs to 80386
DX i nstructi on set. I t i s packed i n 68-pi n PGA package. Programmers may use the regi sters
of 80387 DX i n addi ti on to the regi sters of 80386 DX mi croprocessor.
Intel 80387 SX
I t i s a hi gh performance 80-bi t numeri c processor extensi on for 80386SX mi croprocessor.
I ts i nternal archi tecture i s of 80-bi ts. I ts performance i s 23 ti mes more than that of 8087
and 80287. I t i s compati bl e wi th 80387 DX. I t i s upward object-code compati bl e wi th 8087 and
80287. I t can handl e 32, 64 and 80-bi t fl oati ng-poi nt; 32, 64-bi t i nteger and 18-di gi t BCD
operands. I t di rectl y extends 80386SX CPU i nstructi ons set to tri gonometri c, l ogari thmi c,
exponenti al and ari thmeti c i nstructi ons for al l data types. I t adds over seventy mnemoni cs
to the i nstructi on set of 80386SX mi croprocessor. I t has bui l t-i n excepti on handl i ng. I t i s
avai l abl e i n 68-pi n PLCC package. Programmers may use the regi sters of 80387SX i n addi ti on
to those of 80386SX mi croprocessor.
7.14.4 Motorola MC68881
I t i s a fl oati ng-poi nt coprocessor of Motorol a. I t contai ns ei ght 80-bi t general /purpose
regi sters, and 3 status and control regi sters. I t contai ns a number i n extended-preci si on
format wi th si gn, 15-bi t exponent, and 64-bi t manti ssa.
7.15 GRAPHICS PROCESSORS
Several graphi cs chi ps speci al l y desi gned for graphi cs/vi deo have been devel oped. Thei r
functi on i s to generate pi xel s and process them and di spl ay them. The termi nol ogy used are
graphi cs processors, graphi cs coprocessor, vi deo accel erators, etc. I ntel has devel oped I ntel
740-3D graphi cs chi p. I t i s opti mi sed for I ntel s mul ti medi a processor based PCs, usi ng a
hyper-pi pel i ned 3-D archi tecture wi th addi ti onal 2-D accel erati on. Li ke most 3-D graphi cs
chi ps, I -740 wi l l be marketed i n performance, not the mai n stream category. I t wi l l go mostl y
for heavy mul ti medi a uses such as games and movi es. Other graphi cs processors are: I BMs
8514/A, Texas I nstruments TMS34010 and TMS34020. I ntel i 860, a 64-bi t processor has
graphi cs hardwares to i mpl ement 3-D graphi cs. Earl i er I n