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--------------Dem ma Gray 4 bit--------------library IEEE;

use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------entity Gray4bit is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable: in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0)
);
end Gray4bit;
---------------------------------------------architecture behavioral of Gray4bit is
signal m1 : std_logic;
signal x : std_logic_vector(3 downto 0) :="1111";-- nghich
--signal x : std_logic_vector(3 downto 0) :="0000";-- thuan
begin
process(clk,rst,enable)
begin
if rst ='1' then
x<="1111";--dem nghich
else
if rising_edge(clk) then
if (enable = '1') then
if (x="0000") then x<="1111";
else
x<=x-1;--giam dan
end if;
end if;
end if;
end if;
--process(clk,rst,enable)
--begin
-if rst ='1' then
-x<="0000";--dem thuan
-else
-if rising_edge(clk) then
-if (enable = '1') then
-if (x="1111") then x<="0000";
-else
-x<=x+1;--tang dan
-end if;
-end if;
-end if;
-end if;
case x is
when "1111" =>Q<="1000";
when "1110" =>Q<="1001";
when "1101" =>Q<="1011";
when "1100" =>Q<="1010";
when "1011" =>Q<="1110";
when "1010" =>Q<="1111";
when "1001" =>Q<="1101";
when "1000" =>Q<="1100";
when "0111" =>Q<="0100";
when "0110" =>Q<="0101";
when "0101" =>Q<="0111";

when
when
when
when
when
end case;
end process;
end behavioral;

"0100"
"0011"
"0010"
"0001"
others

=>Q<="0110";
=>Q<="0010";
=>Q<="0011";
=>Q<="0001";
=>Q<="0000";