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8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.


2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2
REV

1
ECN

DESCRIPTION OF REVISION

CK
APPD
DATE
2012-02-23

SCHEM,MLB,J13
2/23/12

(.csa)

Page
TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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14
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18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

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2
3
4
5
7
8
9
10
11
12
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14
16
17
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19
20
21
22
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24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
45
46
47
49
50
51
52
53

Contents
Table of Contents

Date

Sync

(.csa)

Page

07/27/2011

TABLE_TABLEOFCONTENTS_HEAD

11/10/2011

TABLE_TABLEOFCONTENTS_ITEM

J30_MLB

System Block Diagram

J13_MLB_NON_POR
11/10/2011

Revision History

J13_MLB_NON_POR
07/27/2011

Revision History

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

J30_MLB
07/27/2011

TABLE_TABLEOFCONTENTS_ITEM

07/29/2011

TABLE_TABLEOFCONTENTS_ITEM

Power Aliases

07/29/2011

TABLE_TABLEOFCONTENTS_ITEM

K21_MLB
TABLE_TABLEOFCONTENTS_ITEM

Signal Aliases

11/10/2011
J13_MLB_NON_POR
10/17/2011

TABLE_TABLEOFCONTENTS_ITEM

BOM Configuration

J30_MLB

Functional Test / No Test

K21_MLB

CPU DMI/PEG/FDI/RSVD

J13_MLB_NON_POR

CPU CLOCK/MISC/JTAG

J30_MLB

CPU DDR3 INTERFACES

J30_MLB

CPU POWER

07/27/2011

TABLE_TABLEOFCONTENTS_ITEM

07/27/2011

TABLE_TABLEOFCONTENTS_ITEM

11/10/2011

TABLE_TABLEOFCONTENTS_ITEM

J13_MLB_NON_POR

CPU GROUNDS

07/27/2011

TABLE_TABLEOFCONTENTS_ITEM

10/03/2011

TABLE_TABLEOFCONTENTS_ITEM

07/29/2011

TABLE_TABLEOFCONTENTS_ITEM

07/27/2011

TABLE_TABLEOFCONTENTS_ITEM

07/27/2011

TABLE_TABLEOFCONTENTS_ITEM

11/10/2011

TABLE_TABLEOFCONTENTS_ITEM

J30_MLB

CPU DECOUPLING-I

J11_MLB

CPU DECOUPLING-II

K21_MLB

PCH SATA/PCIe/CLK/LPC/SPI
PCH DMI/FDI/PM/Graphics
PCH PCI/USB/TP/RSVD
PCH GPIO/MISC/NCTF
PCH POWER

J30_MLB
J30_MLB
J13_MLB_NON_POR
09/16/2011

TABLE_TABLEOFCONTENTS_ITEM

J11_MLB
09/30/2011

TABLE_TABLEOFCONTENTS_ITEM

07/27/2011

TABLE_TABLEOFCONTENTS_ITEM

10/03/2011

TABLE_TABLEOFCONTENTS_ITEM

10/17/2011

TABLE_TABLEOFCONTENTS_ITEM

J11_MLB

PCH GROUNDS

J30_MLB

PCH DECOUPLING

J11_MLB

CPU & PCH XDP

J13_MLB_NON_POR
11/10/2011

USB HUB & MUX


Clock (CK505) and Chipset Support
CPU Memory S3 Support
DDR3 DRAM CHANNEL A (0-31)
DDR3 DRAM CHANNEL A (32-63)

J13_MLB_NON_POR
07/29/2011

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

K21_MLB
11/10/2011
J13_MLB_NON_POR
07/28/2011

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

K21_MLB
07/28/2011

TABLE_TABLEOFCONTENTS_ITEM

07/28/2011

TABLE_TABLEOFCONTENTS_ITEM

K21_MLB

DDR3 DRAM CHANNEL B (0-31)

K21_MLB

DDR3 DRAM CHANNEL B (32-63)

K21_MLB

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73

54
55
56
57
61
62
69
70
71
72
73
74
75
76
77
78
79
90
94
97
100
101
102
103
105
106
108
109

Date

Contents

Sync

10/17/2011

High Side Current Sensing

J13_MLB_NON_POR
08/03/2011

Thermal Sensors

J11_MLB
07/28/2011

Fan

K21_MLB
11/10/2011

IPD / KBD Backlight

J13_MLB_NON_POR
07/28/2011

SPI ROM

K21_MLB
09/30/2011

AUDI0: SPEAKER AMP

J11_MLB

DC-In & Battery Connectors

J13_MLB_NON_POR

PBus Supply & Battery Charger

11/10/2011
J13_MLB_NON_POR

System Agent Supply

J13_MLB_NON_POR

11/10/2011

10/17/2011

5V / 3.3V Power Supply

10/17/2011
J13_MLB_NON_POR

1.5V DDR3 Supply

J11_MLB

CPU IMVP7 & AXG VCore Regulator

J11_MLB

CPU IMVP7 & AXG VCore Output

10/17/2011
J13_MLB_NON_POR

CPU VCCIO (1.05V) Power Supply

10/17/2011
J13_MLB_NON_POR

Misc Power Supplies

K21_MLB

Power FETs

K21_MLB

Power Control 1/ENABLE

11/10/2011
J13_MLB_NON_POR
07/28/2011

12/02/2011
10/14/2011

07/28/2011
07/28/2011

Internal DisplayPort Connector

K21_MLB
10/03/2011

Thunderbolt Connector A

J11_MLB

LCD Backlight Driver

K21_MLB

07/28/2011
01/11/2012

CPU Constraints

J13_CONSTRAINTS
01/11/2012

Memory Constraints

J13_CONSTRAINTS
01/11/2012

PCH Constraints 1

J13_CONSTRAINTS
01/11/2012

PCH Constraints 2

J13_CONSTRAINTS
01/11/2012

Thunderbolt Constraints

J13_CONSTRAINTS
01/11/2012

SMC Constraints

J13_CONSTRAINTS
01/11/2012

Project Specific Constraints

J13_CONSTRAINTS
01/11/2012

PCB Rule Definitions

J13_CONSTRAINTS

07/28/2011
08/04/2011

FSB/DDR3/FRAMEBUF Vref Margining

J11_MLB

DDR3 Bypassing/Termination

K21_MLB

SecureDigital Card Reader

11/10/2011
J13_MLB_NON_POR

Thunderbolt Host (1 of 2)

J11_MLB

Thunderbolt Host (2 of 2)

J11_MLB

07/28/2011

09/30/2011
10/04/2011

TBT Power Support

11/10/2011
J13_MLB_NON_POR

X21 WIRELESS CONNECTOR

J11_MLB

SSD CONNECTOR

J13_MLB_NON_POR

External A USB3 Connector

J11_MLB

10/11/2011
10/17/2011

Left I/O (LIO) Connector


SMC

09/30/2011
11/10/2011
J13_MLB_NON_POR
10/17/2011
J13_MLB_NON_POR
11/10/2011

SMC Support

J13_MLB_NON_POR
09/08/2011

LPC+SPI Debug Connector

J11_MLB

SMBus Connections

J11_MLB

Voltage & Load Side Current Sensing

J11_MLB

10/04/2011
12/02/2011

TABLE_TABLEOFCONTENTS_ITEM

DRAWING TITLE

SCHEM,MLB,J13
DRAWING NUMBER

Schematic / PCB #s
PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

051-9277

SCHEM,MLB,J13

SCH

CRITICAL

820-3209

PCBF,MLB,J13

PCB

CRITICAL

Apple Inc.

BOM OPTION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING
ABBREV=DRAWING
LAST_MODIFIED=Thu Feb 23 17:52:06 2012

2.8.0

TITLE=MLB

051-9277

REVISION

BRANCH
PAGE

1 OF 109

SHEET

1 OF 73

SIZE

J2500
U1000
J9000

EDP

EDP
CONN

DP0, x1

INTEL CPU

EDP

PG 10

U3100-U3130
U3200-U3230

IVY BRIDGE 2C-35W

PG 9

PG 63

CPU
XDPPG 23CONN

JTAG

MEMORY
x8

AXG=GT2, ULV, 1023P

PCI-E
PG 9

MEMORY

PCIE1

FDI

DMI

PG 9

PG 9

PCIE0

PG 29,30

DUAL Channel
DDR3-1600MHZ
64-bit

U2900-U2930
U3000-U3030

MEMORY
x8

PG 11

J6950,U7000

CHARGER

PG 27,28
J4501

U4510

POWER CIRCUIT

SATA

PG 54-60

MUX

Conn

PG 52,53

PG 38

HDD

PG 38

U5510

CPU TEMP SENSOR

32KHz

PG 47

RTC

FDI

DMI

GPIOs

PG 16

PG 17

PG 17

PG 19

U5410

TBT/MLBBOT/INLET TEMP SENSOR


PG 46,47

VOLTAGE/CURRENT SENSOR
PG 45,46

CLK

U2700

J5600

FAN CONN

BUFFER

SYSTEM
CLOCK

Misc

PG 48

25MHz
PG 19

PG 25

25MHz
Xtal

PG 16
U6100

SMB_5

SMB_1

SMB_3

ADC

FAN0

KBD DRIVER

PG 16

DPMLO
PG 64

MUX

PA_AUX

TMDS OUT

PA_DPSRC_1

HDMI OUT

PA_DPSRC_3

PG 64

PG 41

SERIAL PORT
SMB_2

PG 43

LPC

PM_SLP S3/S4

1017P

AUXIO

/ TBT

LPC+SPI
CONN

U1800

LVDS OUT

LID

J5100

PANTHER POINT - MPCH

RGB OUT

DISPLAY PORT

SMC

INTEL

U3600
U9420

USB

PG 16

DVI OUT

SNK0

x4

DPB

SNK1

x4

DPC

DP OUT
J5700

J3500

SD CARD
CONN

PWR
CTRL

PA_LSTX/LSRX

TRACKPAD
PG 49

PG 35
PG 17

PCIe x4

PA_CIO1

PG 17

PA_CIO0

U3500

9
37

PG 49

Bluetooth
(ON AP)
PG 37

2
1

J4600

U4650

MOJO SMC

EXTERNAL
USB A

DEBUG MUX

J4001

X21
WIRELESS
CONN

PG 24

USB
PCI-E

PG 16

UP TO 8 LANES

PG 18

PG 34

(UP TO 10 DEVICES)

EEPROM

USB HUB

U2600

U3690

PG 39
PG 39

PG 16

SMBUS
PG 16

PCI

HDA

PG 18

PG 16

3
2
1

JTAG

PG 18

PG 37

USB 3

USB MUX

PG 35

PG 34,35

J4001

U5700

SD CARD
CONTROLLER
SPI

PG 49

PG 49

UP TO 6

J9400

KBD CONN

KBDLED

SATA

TBT Host

J5715

U5750

PG 50

PG 16

SATA0

U4900

SPI
Boot ROM

SPI

U2660
U4700

XHCI/EHCI2
MUX

USB3
Re-DRIVER

J6903

U6210

SPEAKER
AMP

PG 24
PG 40

PG 51

RIGHT SPEAKER
CONN
PG 52

J2550

PCH
XDP CONN
PG 23

J4700

HDA

USB CAMERA

SPK

LEFT USB EXTB

LEFT L/O CONN

I2C
LID

PG 40

U6201

PG 7

U6620

SPEAKER LINE IN
FILTER
AMP
PG 10

U4730

USB PORT B
(LEFT PORT)

I2C

J4750

THERMAL
SENSOR

HALL
EFFECT

PG 7

PG 7

PG 6

HEADPHONE
Filter

PG

SYNC_MASTER=J13_MLB_NON_POR

J6701

J6700

LEFT SPEAKER
CONN

HEADPHONE/
LINE IN JACK
PG 11

System Block Diagram

LIO BOARD

DRAWING NUMBER

Apple Inc.

MIC
CONN

051-9277

REVISION

2.8.0

PG 11

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/10/2011

PAGE TITLE

PG 9

J6702

PG 11

J4610

CAMERA +ALS CONN

PG

I2C

J4720

Audio Codec

BRANCH
PAGE

2 OF 109

SHEET

2 OF 73

SIZE

J13 POWER SYSTEM ARCHITECTURE

D6905

PPVIN_G3H_P3V42G3H

PPDCIN_G3H_OR_PBUS

ENABLE

Q5310
SMC_GFX_VSENSE

R0954

PP5V5_CHRG_VDDP

PP5V5_CHAR_VDDP

LT3470A

U7090

AC

CPUVCCIOS0_EN

ISL95870
U7600

EN

21

F7040

(PAGE 59)

(PAGE 36)

VIN

VIN

PPVBAT_G3H_CHRG_RET

ISL6259HRTZ

SMC_DCIN_ISENSE

24

PBUS SUPPLY/
BATTERY CHARGER

R7050

SMC_RESET_L

MAX15120

R7550
SMC_GFX_ISENSE

U7400

CPUIMVP_VR_ON

VR_ON

VOUT

PPVCORE_S0_AXG_REG

(PAGE 57)

(PAGE 53)

26

25-1

CPUIMVP_PGOOD

PGOOD

Q7055

COUGAR-POINT
(PCH) PWRBTN#

CPUIMVP_AXG_PGOOD

PGOODG

PPVBAT_G3H_CHGR_R

(6 TO 8.4V)

PPVBATT_G3H_CONN

Q5300
SMC_PBUS_VSENSE

VIN
DDRREG_EN

S5

DDRVTT_EN

R7350

VLDOIN

1.5V

VOUT1

S3

0.75V

SMC

PM_SYSRST_L

RSMRST#

PM_RSMRST_L

U1800 DPWROK
PM_PCH_PWRGD

SMC_DELAYED_PWRGD

16-1

PGOOD

27

16

PPDDR_S3_REG

PPVTT_S0_DDR_LDO

VOUT2

TPS51916
U7300

PM_S0_PGOOD

Q7801

DDRREG_PGOOD

PLTRST#

U2760

PROCPWRGD
DRAMPWROK

ALL_SYS_PWRGD

(PAGE 16~21)

RC

P60

P3V3S5_EN

(PAGE 41)

EN

CPU_VCCSA_VID<1>

SLP_S5#(E4)

(PCH)

11

(PAGE 54)

CPU_VCCSA_VID<0>
VID0

SLP_SUS#

U7940
RC

P5V_3V3_SUS_EN

P3V3S3_EN

PG62

RC

DDRREG_EN

PG62

DELAY

13

USB_PWR_EN

U1800

13-1
7

PG61

DELAY

PG62

P5VS3_EN
EN1

13-2

VOUT1

PM_SLP_S4_L

PG 17

13

PP5V_S0_FET
PP3V3_S5

(PAGE 55)
PGOOD

P5VS0_EN

PP5V_S0_KBDLED
SMC_SYS_KBDLED

14-1
9

10-3
PP3V3_SUS_FET

SLP_S3#(F4)

14

(PAGE 16~21)

TPS720105

U7740

(PAGE 9~13)

P5VS3_PGOOD

KBDLED_ANPDE
PVCCSA_PGOOD

EN

SMC
ALL_SYS_PWRGD

25

PP3V3_S0_VMON
S5_PWRGD

R7962

RSMRST_IN(P13)

U7960

V2MON

ISL88042IRTEZ

PP1V5_S3RS0_VMON

IMVP_VR_ON(P16)

V4MON
P17(BTN_OUT)

(PAGE 62)

14-1

SLP_S5_L(P95)

PM_SLP_S4_L

RST*

CPUIMVP_VR_ON

26

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

6-1
4

SLP_S4_L(P94)

Q7810

PM_SLP_S3_L
SLP_S3_L(P93)

16

PP3V3_S0

Q5300

PM_RSMRST_L

99ms DLY
PWR_BUTTON(P90)

SYSRST(PA2)

PM_SLP_S5_L

10

PM_DSW_PWRGD

12
RSMRST_OUT(P15)

V3MON

VOUT
PP3V3_S3_FET

P15

PWRGD(P12)

SMC_ONOFF_L

VDD
PP5V_S0_VMON

PPVOUT_SW_LCDBKLT

PG62

RESET*

CPUVCCIOS0_PGOOD

U5750
MIC2292

PP1V05_S0_VMON

U9701
(PAGE 65)

R7978

VIN

10-4

P5V_3V3_SUS_EN

EN

UNCOREPWRGOOD

P3V3S5_PGOOD

PP1V05_SUS_LDO

(PAGE 60)

Q7820

VIN
LP8550
BKL_EN

23-1

PAGE49

LCD_BKLT_EN

CPU
U1000

OUT

P5VS3_PGOOD

Q9706

SM_DRAMPWROK

23

15

VOUT2

(R/H)

&& BKLT_PLT_RST_L
PM_SLP_S3_L PG 17

PVCCSA_PGOOD
Q7860

PP5V_S3_REG
PP3V3_S5_REG

3.3V
EN2

P3V3S5_PGOOD
SLP_S4#(H4)

P1V8S0_PGOOD

(L/H)

P3V3S5_EN

15
3A 32V

PPVCCSA_S0_REG

PGOOD

14

VIN
5V

TPS51980
U7201

F9700
P5VS3_EN

R7140
VOUT

PPVIN_S5_P5VP3V3

10-1

PM_SLP_SUS_L

ISL95870AH
U7100

VID1

R5430

COUGAR-POINT

28

VCC

PVCCSA_EN

22
PG 17

CPU_PWRGD

PM_MEM_PWRGD

PP1V5_S3RS0_FET
PP5V_S0_VCCSA

PM_SLP_S5_L

29

PLT_RERST_L

P1V5CPU_EN

DELAY

SMC_PM_G2_EN

PM_DSW_PWRGD

30

(PAGE 56)

U4900

PM_PWRBTN_L

SYS_RERST#

U2750

CHGR_BGATE

TBT_PWR_EN

PPVCORE_S0_CPU_REG

CPU VCORE

SMC_BATT_ISENSE

J6950

25

VOUT

VOUT

PP1V05_TBTCIO_FET

EN

R7510

IN

2S3P

TPS22920

U3816/U3820

SMC_CPU_ISENSE

A
4

22-1

CPUVCCIOS0_PGOOD

PGOOD

PPBUS_G3H

U7000

22

PPCPUVCCIO_S0_REG
SMC_CPU_FSB_ISENSE

R7020

DCIN(14.5V)

ADAPTER

1.05V VOUT

VCC

SMC_RESET_L

R7640

VIN

PP5V_S0_CPUVCCIOS0.

(PAGE 53)

F6901
6A FUSE

15

ENABLE

SMC POWER
SN0903048
U5010
(PAGE 42)

(PAGE 52)

D7005

J6900

PP3V42_G3H_REG

LT3470A
U6990

R6906

3.425V G3HOT

R6905

P3V3S3_EN

P1V8S0_PGOOD
U4900
(PAGE 41)

SMC_PBUS_VSENSE
PM_SLP_S3_R_L
P1V8_S0_EN

PP5V_SUS_FET
PBUSVSENS_EN

Q7840

10-2

17

ISL8014A
EN

U7720

PP1V8_S0_REG

(PAGE 60)

18
19

P5V_3V3_SUS_EN

RC

CPUVCCIOS0_EN

DELAY

RC

PVCCSA_EN

21
21
22

Q3880
1V05_S0_LDO_EN

P5VS0_EN

P3V3S0_EN

DELAY

RC

P1V5S0_EN

19

DELAY

RC

P1V8S0_EN

DELAY

PBUSVSENS_EN

14-1
14-1
14-1

TBTBST_EN_UVLO

VIN
LT3957

Q7830

SYNC_DATE=11/10/2011
PAGE TITLE

VOUT

PP15V_T29_REG

T29_PWR_EN

TPS22924
EN

DRAWING NUMBER

U3810

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

R4599
PP3V3_S0_SSD_R

051-9277

REVISION

2.8.0

(PAGE 36)

Apple Inc.

PP3V3_T29_FET

PP1V5S0_EN

Revision History

PP1V5_S0_REG

(PAGE 60)
EN

R7831

U3890

14

PP1V05_S0_LDO.

U7770

P3V3S0_EN

U7780

TPS72015

T29_A_HV_EN

(PAGE 36)

17

TPS720105
EN

(PAGE 60)

EN/UVLO

1V05_S0_LDO_EN

BRANCH
PAGE

3 OF 109

SHEET

3 OF 73

SIZE

BOM Variants
BOM NAME

BOM OPTIONS

PART NUMBER

TABLE_BOMGROUP_ITEM

085-3939

J13 MLB DEVELOPMENT BOM

J13_DEVEL:ENG
TABLE_BOMGROUP_ITEM

607-9090

CMN PTS,PCBA,MLB,J13

J13_COMMON
TABLE_BOMGROUP_ITEM

639-3552

PCBA,MLB,1.7GHZ,SA 4GB,J13

J13_CMNPTS,EEEE:DYRQ,CPU:1.7GHZ,DDR3:SAMSUNG_4GB
TABLE_BOMGROUP_ITEM

639-3553

PCBA,MLB,1.5GHZ,SA 4GB,J13

J13_CMNPTS,EEEE:DYRM,CPU:1.5GHZ,DDR3:SAMSUNG_4GB
TABLE_BOMGROUP_ITEM

639-3554

PCBA,MLB,1.5GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:DYRN,CPU:1.5GHZ,DDR3:HYNIX_4GB
TABLE_BOMGROUP_ITEM

639-3555

PCBA,MLB,1.5GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:DYRL,CPU:1.5GHZ,DDR3:HYNIX_8GB
TABLE_BOMGROUP_ITEM

PCBA,MLB,1.7GHZ,HY 8GB,J13

639-3556

J13_CMNPTS,EEEE:DYRK,CPU:1.7GHZ,DDR3:HYNIX_8GB
TABLE_BOMGROUP_ITEM

639-3557

PCBA,MLB,1.7GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:DYRP,CPU:1.7GHZ,DDR3:HYNIX_4GB

639-3645

PCBA,MLB,1.5GHZ,EL 8GB,J13

J13_CMNPTS,EEEE:F0TC,CPU:1.5GHZ,DDR3:ELPIDA_8GB

639-3644

PCBA,MLB,1.7GHZ,EL 8GB,J13

J13_CMNPTS,EEEE:F0TD,CPU:1.7GHZ,DDR3:ELPIDA_8GB

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

639-3760

PCBA,MLB,1.8GHZ,SA 4GB,J13

J13_CMNPTS,EEEE:F25Q,CPU:1.8GHZ,DDR3:SAMSUNG_4GB
TABLE_BOMGROUP_ITEM

639-3761

PCBA,MLB,1.8GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:F25T,CPU:1.8GHZ,DDR3:HYNIX_8GB
TABLE_BOMGROUP_ITEM

639-3762

PCBA,MLB,1.8GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:F25Y,CPU:1.8GHZ,DDR3:HYNIX_4GB
TABLE_BOMGROUP_ITEM

PCBA,MLB,1.8GHZ,EL 8GB,J13

639-3763

J13_CMNPTS,EEEE:F25P,CPU:1.8GHZ,DDR3:ELPIDA_8GB
TABLE_BOMGROUP_ITEM

639-3764

PCBA,MLB,2.0GHZ,SA 4GB,J13

J13_CMNPTS,EEEE:F25N,CPU:2.0GHZ,DDR3:SAMSUNG_4GB
TABLE_BOMGROUP_ITEM

639-3765

PCBA,MLB,2.0GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:F25W,CPU:2.0GHZ,DDR3:HYNIX_8GB
TABLE_BOMGROUP_ITEM

639-3766

PCBA,MLB,2.0GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:F25R,CPU:2.0GHZ,DDR3:HYNIX_4GB
TABLE_BOMGROUP_ITEM

639-3767

PCBA,MLB,2.0GHZ,EL 8GB,J13

Bar Code Labels / EEEE #s

TABLE_BOMGROUP_HEAD

BOM NUMBER

J13_CMNPTS,EEEE:F25V,CPU:2.0GHZ,DDR3:ELPIDA_8GB

DESCRIPTION

REFERENCE DES

825-7670

QTY
1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DYRK]

CRITICAL
CRITICAL

BOM OPTION
EEEE:DYRK

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DYRL]

CRITICAL

EEEE:DYRL

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DYRM]

CRITICAL

EEEE:DYRM

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DYRN]

CRITICAL

EEEE:DYRN

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DYRP]

CRITICAL

EEEE:DYRP

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DYRQ]

CRITICAL

EEEE:DYRQ

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F0TC]

CRITICAL

EEEE:F0TC

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F0TD]

CRITICAL

EEEE:F0TD

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F25N]

CRITICAL

EEEE:F25N

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F25P]

CRITICAL

EEEE:F25P

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F25Q]

CRITICAL

EEEE:F25Q

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F25R]

CRITICAL

EEEE:F25R

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F25T]

CRITICAL

EEEE:F25T

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F25V]

CRITICAL

EEEE:F25V

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F25W]

CRITICAL

EEEE:F25W

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F25Y]

CRITICAL

EEEE:F25Y

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F27Q]

CRITICAL

EEEE:F27Q

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F27R]

CRITICAL

EEEE:F27R

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F27T]

CRITICAL

EEEE:F27T

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F27V]

CRITICAL

EEEE:F27V

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F27W]

CRITICAL

EEEE:F27W

825-7670

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_F27Y]

CRITICAL

EEEE:F27Y

TABLE_BOMGROUP_ITEM

639-3790

PCBA,MLB,1.7GHZ,SA 8GB,J13

J13_CMNPTS,EEEE:F27V,CPU:1.7GHZ,DDR3:SAMSUNG_8GB
TABLE_BOMGROUP_ITEM

639-3791

PCBA,MLB,1.8GHZ,SA 8GB,J13

J13_CMNPTS,EEEE:F27Q,CPU:1.8GHZ,DDR3:SAMSUNG_8GB
TABLE_BOMGROUP_ITEM

639-3792

PCBA,MLB,2.0GHZ,SA 8GB,J13

J13_CMNPTS,EEEE:F27R,CPU:2.0GHZ,DDR3:SAMSUNG_8GB
TABLE_BOMGROUP_ITEM

639-3793

PCBA,MLB,1.7GHZ,EL 4GB,J13

J13_CMNPTS,EEEE:F27W,CPU:1.7GHZ,DDR3:ELPIDA_4GB
TABLE_BOMGROUP_ITEM

639-3794

PCBA,MLB,1.8GHZ,EL 4GB,J13

J13_CMNPTS,EEEE:F27Y,CPU:1.8GHZ,DDR3:ELPIDA_4GB
TABLE_BOMGROUP_ITEM

639-3795

PCBA,MLB,2.0GHZ,EL 4GB,J13

J13_CMNPTS,EEEE:F27T,CPU:2.0GHZ,DDR3:ELPIDA_4GB

Sub BOM
PART NUMBER

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

PAGE TITLE

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

Revision History

BOM OPTION

085-3939

J13 MLB DEVELOPMENT

DEVEL

CRITICAL

DEVEL_BOM

607-9090

CMN PTS,PCBA,MLB,J13

CMNPTS

CRITICAL

J13_CMNPTS

DRAWING NUMBER

Apple Inc.

051-9277

REVISION

2.8.0

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH
PAGE

4 OF 109

SHEET

4 OF 73

SIZE

J13 BOM GROUPS

Module Parts
TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

J13_COMMON

ALTERNATE,COMMON,J13_MISC,J13_DEBUG:ENG,J13_PROGPARTS,USBHUB2514B,EDP:YES,PCH_C1

J13_MISC

CPUMEM_SLG:NO,HUB_3NONREM,TBT,MPM5:YES,PP5V5_DCIN:NO,TPAD_PCH:NO,SKIP_5V3V3:INAUDIBLE,BTPWR:S4,TBTHV:P15V,LVDDR3_HW:YES,AXG_ACOUSTIC:NO

PART NUMBER

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

J13_PROGPARTS

BOOTROM_PROG,SMC_PROG,TBTROM:PROG

J13_DEVEL:ENG

ALTERNATE,BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

J13_DEVEL:PVT

LPCPLUS,XDP_CONN

J13_DEBUG:ENG

DEVEL_BOM,MOJO:YES,XDP

J13_DEBUG:PVT

DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

J13_DEBUG:PROD

BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

DDR3:HYNIX_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

DDR3:HYNIX_8GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

DDR3:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

DDR3:SAMSUNG_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

DDR3:ELPIDA_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

DDR3:ELPIDA_4GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

DESCRIPTION

REFERENCE DES

337S4197

QTY
1

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

U1000

CRITICAL
CRITICAL

BOM OPTION
CPU:1.5GHZ

337S4299

IVB,QC55,QS,L0,1.7,17W,2+2,1.0,3M,ULVBGA

U1000

CRITICAL

CPU:1.7GHZ

337S4298

IVB,QC54,QS,L0,1.8,17W,2+2,1.1,3M,ULVBGA

U1000

CRITICAL

CPU:1.8GHZ

337S4296

IVB,QC52,QS,L0,2.0,17W,2+2,1.1,4M,ULVBGA

U1000

CRITICAL

CPU:2.0GHZ

337S4198

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

U1000

CRITICAL

CPU:1.5GHZTDP

337S4236

IVB,QBQF,ES2,K0,1.7,17W,2+2,1.0,4M,ULV,TDP

U1000

CRITICAL

CPU:1.7GHZTDP

337S4165

IC,PCH,PPT-MB,SFF,ES1

U1800

CRITICAL

PCH_ES1

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

337S4180

IC,PCH,PPT-MB,SFF,ES2,B0

U1800

CRITICAL

PCH_ES2

337S4235

IC,PCH,PPT-MB,SFF,P-QS,C0

U1800

CRITICAL

PCH_C0

337S4275

IC,PCH,PPT-MB,QS77,C1,QS

U1800

CRITICAL

PCH_C1

338S1047

IC,TBT,CR-4C,ES1,288 FCBGA,12X12MM

U3600

CRITICAL

TBT

333S0622

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FPGA

U2900,U2910,U2920,U2930

CRITICAL

DRAM_TYPE:HYNIX_4GB

333S0622

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA

U3000,U3010,U3020,U3030

CRITICAL

DRAM_TYPE:HYNIX_4GB

333S0622

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FGBA

U3100,U3110,U3120,U3130

CRITICAL

DRAM_TYPE:HYNIX_4GB

333S0622

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA

U3200,U3210,U3220,U3230

CRITICAL

DRAM_TYPE:HYNIX_4GB

333S0625

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA

U2900,U2910,U2920,U2930

CRITICAL

DRAM_TYPE:HYNIX_8GB

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Programmable Parts
PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

335S0865

IC,SERIAL SPI EEPROM,256KBIT,20MHZ,MLP8

U3690

CRITICAL

TBTROM:BLANK

333S0625

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FPGA

U3000,U3010,U3020,U3030

CRITICAL

DRAM_TYPE:HYNIX_8GB

341S3475

IC,EEPROM,CR,V24.1,J11/J13

U3690

CRITICAL

TBTROM:PROG

333S0625

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FGBA

U3100,U3110,U3120,U3130

CRITICAL

DRAM_TYPE:HYNIX_8GB

338S1098

IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA

U4900

CRITICAL

SMC_BLANK

333S0625

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA

U3200,U3210,U3220,U3230

CRITICAL

DRAM_TYPE:HYNIX_8GB

338S1065

IC,SMC12,40MHZ/50DMIPS MCU, 9X9,157BGA

U4900

CRITICAL

SMC_BLANK

333S0623

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

U2900,U2910,U2920,U2930

CRITICAL

DRAM_TYPE:SAMSUNG_4GB

341S3433

IC,SMC,V2.1A43,Proto1B,J13

U4900

CRITICAL

SMC_PROG

333S0623

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

U3000,U3010,U3020,U3030

CRITICAL

DRAM_TYPE:SAMSUNG_4GB

335S0809

64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix

U6100

CRITICAL

BOOTROM_BLANK

333S0623

IC,SDRAM,2GBIT,DDR3-1600,78P FGBA,D-DIE

U3100,U3110,U3120,U3130

CRITICAL

DRAM_TYPE:SAMSUNG_4GB

335S0803

64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx

U6100

CRITICAL

BOOTROM_BLANK

333S0623

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

U3200,U3210,U3220,U3230

CRITICAL

DRAM_TYPE:SAMSUNG_4GB

341S3482

IC,EFI ROM,PROTO1B,J13 J11

U6100

CRITICAL

BOOTROM_PROG

333S0642

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

U2900,U2910,U2920,U2930

CRITICAL

DRAM_TYPE:SAMSUNG_8GB

333S0642

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

U3000,U3010,U3020,U3030

CRITICAL

DRAM_TYPE:SAMSUNG_8GB

333S0642

IC,SDRAM,4GBIT,DDR3-1600,78P FGBA,C-DIE

U3100,U3110,U3120,U3130

CRITICAL

DRAM_TYPE:SAMSUNG_8GB

333S0642

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

U3200,U3210,U3220,U3230

CRITICAL

DRAM_TYPE:SAMSUNG_8GB

333S0629

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

U2900,U2910,U2920,U2930

CRITICAL

DRAM_TYPE:ELPIDA_8GB

333S0629

IC,SDRAM,4GBIT,DDR3L-1600,REV B.78P FBGA

U3000,U3010,U3020,U3030

CRITICAL

DRAM_TYPE:ELPIDA_8GB

333S0629

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FGBA

U3100,U3110,U3120,U3130

CRITICAL

DRAM_TYPE:ELPIDA_8GB

333S0629

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA

U3200,U3210,U3220,U3230

CRITICAL

DRAM_TYPE:ELPIDA_8GB

333S0628

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

U2900,U2910,U2920,U2930

CRITICAL

DRAM_TYPE:ELPIDA_4GB

333S0628

IC,SDRAM,2GBIT,DDR3L-1600,REV D.78P FBGA

U3000,U3010,U3020,U3030

CRITICAL

DRAM_TYPE:ELPIDA_4GB

333S0628

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FGBA

U3100,U3110,U3120,U3130

CRITICAL

DRAM_TYPE:ELPIDA_4GB

333S0628

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

U3200,U3210,U3220,U3230

CRITICAL

DRAM_TYPE:ELPIDA_4GB

Alternate Parts
TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:
TABLE_ALT_ITEM

376S0855

376S0613

ALL

Diodes alt to Toshiba

376S0977

376S0859

ALL

Diodes alt to Toshiba

TABLE_ALT_ITEM

TABLE_ALT_ITEM

376S0972

376S0612

ALL

Rohm alt to Toshiba


TABLE_ALT_ITEM

138S0676

138S0691

ALL

Murata alt to Samsung

371S0709

371S0652

ALL

NXP alt to NXP

TABLE_ALT_ITEM

TABLE_ALT_ITEM

138S0671

138S0673

ALL

Taiyo alt to Murata

376S0790

376S0928

ALL

TI alt to Fairchild

TABLE_ALT_ITEM

TABLE_ALT_ITEM

152S1462

152S1295

ALL

Toko alt for NEC inductor

152S1085

152S1307

ALL

Toko alt for Cyntec

138S0703

138S0648

ALL

Murata alt to Taiyo Yuden

138S0684

138S0660

ALL

Murata alt to Taiyo Yuden

152S1493

152S1300

ALL

Coilcraft alt to Murata

353S3238

353S1428

ALL

Intersil alt to OPA2333

372S0186

372S0185

ALL

NXP alt to Diodes

376S1053

376S0604

ALL

Diodes alt to Fairchild

376S0855

376S0613

ALL

Diodes alt to Toshiba

376S0903

376S0796

ALL

Fairchild alt to Siliconix

197S0431

197S0432

ALL

Epson alt to NDK

337S4198

337S4197

ALL

TDP 1.5GHZ alt to Nominal

337S4236

337S4196

ALL

TDP 1.7GHZ alt to Nominal

371S0713

371S0558

ALL

Diodes alt to ST Micro

128S0333

998-4435

ALL

Sanyo alt to Kemet

128S0357

998-4435

ALL

Sanyo alt to POS caps

998-4715

998-4435

ALL

Kemet_Rect alt to POS caps

998-4716

998-4435

ALL

Kemet_.0045 Flute alt to POS caps

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

353S2929

IC,ISL6259,BATCHARGER,3%,4X4MM,QFN28

U7000

CRITICAL

946-3115

MLB,DYMAX UV EB 0.22GRAM,K21

GLUE

CRITICAL

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PD Module Parts

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

DRAM CFG CHART

TABLE_ALT_ITEM

TABLE_ALT_ITEM

VENDOR

CFG 1

CFG 0

TABLE_ALT_ITEM

HYNIX

CAN,T29,J11/J13

TBTFENCE

CRITICAL

806-3215

CAN,COVER,T29,J11/J13

TBTCOVER

CRITICAL

806-3214

CAN,TOPSIDE,J11/J13

TBTTOPSIDE_1P

CRITICAL

806-3706

CAN,TOPSIDE_2Piece_Cover,J11/J13

TBTTOPSIDE_2P_COVER

CRITICAL

806-3705

CAN,TOPSIDE_2Piece_Fence,J11/J13

TBTTOPSIDE_2P_FENCE

CRITICAL

806-3216

CAN,MDP,J11/J13

MDPCAN

CRITICAL

806-3083

SHLD,USB,MLB,J11/J13

USBCAN

CRITICAL

806-2377

K78, mDP Spring

MDPSPRING

CRITICAL

TABLE_ALT_ITEM

TABLE_ALT_ITEM

806-3142

SAMSUNG
1

TABLE_ALT_ITEM

MICRON

ELPIDA

NOSTUFF

TABLE_ALT_ITEM

SIZE

CFG 2

DIE REV

SYNC_MASTER=J30_MLB

CFG 3

SYNC_DATE=07/27/2011

PAGE TITLE

BOM Configuration
4GB

8GB

DRAWING NUMBER

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

2.8.0

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-9277

REVISION

BRANCH
PAGE

5 OF 109

SHEET

5 OF 73

SIZE

3
FUNC_TEST

(Need 5 TPs)
PP3V3_S0_SSD_FLT
SATA_SSD_D2R_P
SATA_SSD_D2R_N
SMC_OOB1_RX_L
SMC_OOB1_TX_L
PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
PCIE_SSD_R2D_P<1>
PCIE_SSD_R2D_N<1>
PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_N<1>
SATA_SSD_R2D_N
SATA_SSD_R2D_P
SSD_CLKREQ_L
SATA_PCIE_SEL
SSD_P3V3S0_EN
SSD_RESET_L
(Need to add 6 GND TPs)

TRUE

J4001: AirPort / BT Connector


TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

J5600: Fan Connector


(Need 5 TPs)

37 42

TRUE
TRUE

37 41 42

TRUE

37 69

48
48

FUNC_TEST

37 68
37 68

PP3V3_S3RS4_BT_F

TRUE

I624

16 37 69

TRUE

16 37 69

TRUE

17 37

TRUE

37

TRUE

37

TRUE
TRUE

37

TRUE

TRUE
TRUE

I623

FUNC_TEST

TRUE

7 48

J5700: IPD Flex Connector

16 37 69

J5715: KB BKLT CONNECTOR

I626

=PP5V_S0_FAN
FAN_RT_TACH
FAN_RT_PWM

16 37 69

TRUE

TRUE

TRUE

(Need to add 1 GND TP)

37 69

(Need to add 8 GND TPs)

I627

TRUE

FUNC_TEST

PP3V3_WLAN_F
WIFI_EVENT_L
PCIE_AP_R2D_N
PCIE_AP_R2D_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
USB_BT_CONN_P
USB_BT_CONN_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_WAKE_L
AP_RESET_CONN_L
AP_CLKREQ_Q_L

PP3V3_TPAD_CONN
PP5V_TPAD_FILT
=PP3V42_G3H_TPAD
USB_TPAD_CONN_P
USB_TPAD_CONN_N
=I2C_TPAD_SDA
=I2C_TPAD_SCL
SMC_ONOFF_L
SMC_LID
SMC_TPAD_RST_L
SMC_PME_S4_WAKE_L

49

TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I671

TRUE

I672

TRUE

I673

TRUE

I674

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE

=PP3V42_G3H_ONEWIRE
=PP3V3_S0_AUDIO
=PP3V3R1V5_S0_AUDIO
SYS_ONEWIRE
SMC_BC_ACOK
=USB_PWR_EN
SMC_LID
=I2C_LIO_SDA
=I2C_LIO_SCL
=I2C_MIKEY_SCL
=I2C_MIKEY_SDA
AUD_IPHS_SWITCH_EN
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
AUD_GPIO_3
SPKRAMP_INR_N
SPKRAMP_INR_P
USB_EXTB_N
USB_EXTB_P
USB3_EXTB_TX_C_N
USB3_EXTB_TX_C_P
USB3_EXTB_RX_RC_N
USB3_EXTB_RX_RC_P
USB_CAMERA_N
USB_CAMERA_P
HDA_SDOUT
HDA_BIT_CLK
HDA_SDIN0
USB_EXTB_OC_L
HDA_RST_L
HDA_SYNC

7 40
7 40

TRUE
TRUE
TRUE
TRUE

TRUE
40 41

TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

I676

TRUE

TRUE
7 49

TRUE

I681

68
68
44 49
44 49

I683

TRUE

I684

TRUE

I682

TRUE

38 68
38 41
38 41 42

MAKE_BASE=TRUE

16 38 66

NC_CPU_THERMDA

TRUE

TP_EDP_TX_P<0..3>

TRUE

TP_EDP_TX_N<0..3>

TRUE

TP_EDP_AUX_P

TRUE

TP_EDP_AUX_N

TRUE

TP_CPU_THERMDA

MAKE_BASE=TRUE
16 38 66

NC_CPU_THERMDC

38 66

MAKE_BASE=TRUE

38 66

NC_CPU_RSVD<30..45>

TRUE

TP_CPU_THERMDC

TRUE

TP_CPU_RSVD<30..45>

TRUE

TP_CPU_RSVD<8..27>

MAKE_BASE=TRUE
8 38 66

NC_CPU_RSVD<8..27>
MAKE_BASE=TRUE

8 38 66

TRUE

NC_PEG_R2D_CP<15..2>

38 68

=PEG_R2D_C_P<15..2>

MAKE_BASE=TRUE
38 68

NC_PEG_R2D_CN<15..2>

16 38

MAKE_BASE=TRUE

NC_PEG_D2RP<15..2>

38

TRUE

=PEG_R2D_C_N<15..2>

TRUE

=PEG_D2R_P<15..2>

TRUE

=PEG_D2R_N<15..2>

MAKE_BASE=TRUE
38

NC_PEG_D2RN<15..2>

25 38

MAKE_BASE=TRUE

J6900: DC-In Connector


FUNC_TEST

42 49

=PP18V5_DCIN_CONN
=PP5V_S3_LIO_CONN

TRUE

41 42 49

TRUE

7 52

(Need 6 TPs)

7 52

(Need to add 5 GND TPs)

SPKRAMP_ROUT_P
SPKRAMP_ROUT_N
(Need to add 3 GND TPs)

NO_TEST Nets

51 52 72
51 52 72

PPVBAT_G3H_CONN
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SYS_DETECT_L

52 53

I667

TRUE

I668

TRUE

I669

TRUE

I670

TRUE

44 52

TP_CRT_IG_RED

40 44

17

TP_CRT_IG_DDC_CLK

40 44

17

TP_CRT_IG_DDC_DATA

44 52
52

(Need to add 4 GND TPs near


J6950 and 1 for shield)

40 44

40 44

17

TP_CRT_IG_HSYNC

17

TP_CRT_IG_VSYNC

FUNC_TEST
18 40

TRUE
18 40

TRUE
40 51

TRUE
40 51 72

TRUE
40 51 72

TRUE
24 40 68

TRUE
24 40 68

TRUE
40 68

TRUE
40 68

TRUE
40 68

TRUE
40 68

TRUE
18 40 68

TRUE
18 40 68

TRUE
16 40 69

TRUE
16 40 69

TRUE
16 40 69

TRUE
TRUE
16 40 69

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5N

54

TP_PCIE_CLK100M_PE5P

54

TP_PCIE_CLK100M_PE6N

54

TP_PCIE_CLK100M_PE6P

PPVOUT_SW_LCDBKLT
PP3V3_SW_LCD
I2C_TCON_SDA_R
I2C_TCON_SCL_R
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
DP_INT_HPD_CONN
DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_C_P
DP_INT_ML_F_P<0>
DP_INT_ML_F_N<0>
DP_INT_ML_F_P<1>
DP_INT_ML_F_N<1>

TP_PCIE_CLK100M_PE7P
NC_CRT_IG_BLUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TP_PSOC_P1_3
NC_CRT_IG_GREEN

TP_SATA_B_D2RN

NC_CRT_IG_RED
TP_SATA_B_D2RP
TP_SATA_B_R2D_CN

J9000: Internal DP Connector

25 40

TP_PCIE_CLK100M_PE4N

16

TP_PCIE_CLK100M_PE7N

17

6 40 41 42 49

16

54

NO_TEST

TP_CRT_IG_GREEN

TRUE

VCCSAS0_SREF
VCCSAS0_SET1_R
VCCSAS0_SET0
VCCSAS0_SET1

(Need 4 TPs)

17

39 40 62

63 65
63

(Need 2 TPs)
(Need 2 TPs)

TP_SATA_B_R2D_CP
NC_CRT_IG_DDC_DATA
16

NC_CRT_IG_HSYNC

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

TP_PCH_LVDS_VBG

63 65

16

TP_HDA_SDIN1

63 65

16

TP_HDA_SDIN2

63 65

16

TP_HDA_SDIN3

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TP_SATA_D_D2RP

16

TP_SATA_D_R2D_CN

16

TP_SATA_D_R2D_CP
TP_SATA_E_D2RN

16

TP_SATA_E_D2RP

16

TP_SATA_E_R2D_CN

16

TP_SATA_E_R2D_CP

16

TP_SATA_F_D2RN

NC_HDA_SDIN1

16

TP_SATA_F_D2RP

NC_HDA_SDIN2

16

TP_SATA_F_R2D_CN

NC_HDA_SDIN3

16

TP_SATA_F_R2D_CP

63 65
63 65

TP_SATA_D_D2RN

16

16

NC_LVDS_IG_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_PCH_LVDS_VBG
TRUE
MAKE_BASE=TRUE

TP_LVDS_IG_CTRL_DATA

63

NC_CRT_IG_DDC_CLK

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TP_LVDS_IG_CTRL_CLK

63

63
18

TP_PCI_PME_L

18

TP_PCI_CLK33M_OUT3

63 66

33
33
33
33
33

=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
LPC_AD<3..0>
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
TP_SMC_TRST_L
TP_SMC_MD1
SMC_TX_L
LPC_CLK33M_LPCPLUS
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
LPCPLUS_GPIO

7 43
7 43
16 41 43 69
43
43
16 41 43 69
17 41 43
41 42 43
25 43 69
41 42 43
43
43
41 42 43
25 43 69
19 43 50
43
43
16 41 43
17 25 41 43
41 42 43
41 42 43
41 42 43 53
42 43
41 42 43
19 43

TRUE

I629

TRUE

I630

TRUE

I631

TRUE

I632

TRUE

I633

TRUE

I634

TRUE

I636

TRUE

I635

TRUE

I638

TRUE

I637

TRUE

I639

TRUE

I641

TRUE

I640

TRUE

I643

TRUE

I642

TRUE

I644

TRUE

I646

TRUE

I645

TRUE

I648

TRUE

I647

TRUE

I649

TRUE

I650

TRUE

I651

TRUE

I653

TRUE

I652

TRUE

I654

TRUE

I655

TRUE

I657

TRUE

I656

TRUE

I685
I686
I687
I688
I689
I690

NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
NC_PSOC_P1_3
NC_SATA_B_D2RN
NC_SATA_B_D2RP

NC_SATA_B_R2D_CN
NC_SATA_B_R2D_CP

NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP

TP_PCH_TP18

TRUE
MAKE_BASE=TRUE

NC_PCH_TP18

TP_PCH_TP17

TRUE
MAKE_BASE=TRUE

NC_PCH_TP17

63 66

TP_PCH_TP16

TRUE
MAKE_BASE=TRUE

NC_PCH_TP16

TP_PCH_TP15

TRUE
MAKE_BASE=TRUE

NC_PCH_TP15

TP_PCH_TP14

TRUE
MAKE_BASE=TRUE

NC_PCH_TP14

TP_PCH_TP13

TRUE
MAKE_BASE=TRUE

NC_PCH_TP13

TP_PCH_TP12

TRUE
MAKE_BASE=TRUE

NC_PCH_TP12

TP_PCH_TP10

TRUE
MAKE_BASE=TRUE

NC_PCH_TP10

TP_PCH_TP9

TRUE
MAKE_BASE=TRUE

NC_PCH_TP9

7 52

TP_PCH_TP8

TRUE
MAKE_BASE=TRUE

NC_PCH_TP8

7 36

TP_PCH_TP7

TRUE
MAKE_BASE=TRUE

NC_PCH_TP7

16

TP_CLINK_CLK

16

TP_CLINK_DATA

16

TP_CLINK_RESET_L

66
66

16

TP_PCIE_CLK100M_PEBN

16

TP_PCIE_CLK100M_PEBP

NC_CLINK_CLK

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_CLINK_DATA
NC_CLINK_RESET_L
NC_PCIE_CLK100M_PEBN

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

PPBUS_G3H
PPVIN_SW_TBTBST
PPBUS_S5_HS_COMPUTING_ISNS
PPDCIN_G3H
PP3V42_G3H
PPVRTC_G3H
PP5V_S5
PP5V_SUS
PP3V3_S5
PP3V3_SUS
PP3V3_S3
PP1V8_S0
PP3V3_S0
PP1V5_S3
PP1V5_S3RS0
PP1V5_S0
PP1V05_S0
PPVTTDDR_S3
PP0V75_S0_DDRVTT
PPVCCSA_S0_CPU
PP1V05_SUS
PP15V_TBT
PP3V3_TBTLC
PP1V05_TBTLC
PP1V05_S0_PCH_VCCADPLL
PPVCORE_S0_CPU
PPVCORE_S0_AXG
PP1V5_S3_CPU_VCCDQ
PP1V05_S0_CPU_VCCPQE
PP1V8_S0_CPU_VCCPLL_R
PP1V05_TBTCIO
PPBUS_S5_HS_OTHER_ISNS
PPDCIN_G3H_ISOL
PP5V_S3
PP5V_S0
PP3V3_S4

I593

TRUE

XDP_PCH_AP_PWR_EN

TP_PCH_TP6

TRUE
MAKE_BASE=TRUE

NC_PCH_TP6

I592

TRUE

XDP_PCH_USB_HUB_SOFT_RST_L

TP_PCH_TP5

TRUE
MAKE_BASE=TRUE

NC_PCH_TP5

I595

TRUE

XDP_PCH_SDCONN_STATE_RST_L

TP_PCH_TP4

TRUE
MAKE_BASE=TRUE

NC_PCH_TP4

TP_PCH_TP3

TRUE
MAKE_BASE=TRUE

NC_PCH_TP3

TP_PCH_TP2

TRUE
MAKE_BASE=TRUE

NC_PCH_TP2

TP_PCH_TP1

TRUE
MAKE_BASE=TRUE

I594

TRUE

XDP_PCH_ENET_PWR_EN

I596

TRUE

XDP_PCH_SDCONN_DET_L

I597

TRUE

XDP_PCH_S5_PWRGD

23

7 72

23

I598

TRUE

XDP_PCH_PWRBTN_L

I599

TRUE

XDP_PCH_ISOLATE_CPU_MEM_L

I600

TRUE

XDP_FW_CLKREQ_L

I601

TRUE

XDP_AP_CLKREQ_L

7 72

I602

TRUE

XDP_PCH_AUD_IPHS_SWITCH_EN

7 67

I566

TRUE

PCH_VSS_NCTF<1>

I567

TRUE

PCH_VSS_NCTF<2>

I568

TRUE

PCH_VSS_NCTF<5>

I570

TRUE

PCH_VSS_NCTF<9>

7 67

I571

TRUE

PCH_VSS_NCTF<11>

I569

TRUE

PCH_VSS_NCTF<12>

7
7

17 TP_SDVO_TVCLKINN
17 TP_SDVO_TVCLKINP

7
7

17 TP_SDVO_STALLN

17 TP_SDVO_STALLP

7
7

17 TP_SDVO_INTN
17 TP_SDVO_INTP

7 36

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_SDVO_STALLN
NC_SDVO_STALLP
NC_SDVO_INTN

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

TP_LVDS_IG_B_CLKP

TP_XDP_PCH_OBSFN_A<0..1>

23

23

TP_XDP_PCH_OBSFN_B<0..1>

23

TP_XDPPCH_HOOK2

23

TP_XDPPCH_HOOK3

23

TP_XDP_PCH_OBSFN_D<0..1>

23

TP_XDP_PCH_HOOK4

23

TP_XDP_PCH_HOOK5

16

TP_PCH_GPIO64_CLKOUTFLEX0

16

TP_PCH_GPIO65_CLKOUTFLEX1

16

TP_PCH_GPIO66_CLKOUTFLEX2

16

TP_PCH_GPIO67_CLKOUTFLEX3

7
7
7
7

NC_PCH_TP1

I500

TRUE

PCH_VSS_NCTF<15>

I499

TRUE

PCH_VSS_NCTF<17>

I501

TRUE

PCH_VSS_NCTF<19>

I502

TRUE

PCH_VSS_NCTF<19>

I503

TRUE

PCH_VSS_NCTF<21>

I504

TRUE

PCH_VSS_NCTF<25>

I505

TRUE

PCH_VSS_NCTF<27>

I506

TRUE

PCH_VSS_NCTF<29>

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM

NC_SDVO_INTP
SMC_BS_ALRT_L

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_A<0..1>

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

NC_TP_XDP_PCH_OBSFN_B<0..1>

NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM

TRUE
MAKE_BASE=TRUE

7
7

NC_SDVO_TVCLKINP

(Need to add 27 GND TPs)

NC_SATA_D_D2RN

NC_PCIE_CLK100M_PE5N

63 66

(Need to add 5 GND TPs)

I628

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4P

NC_PCI_CLK33M_OUT3

FUNC_TEST
33

NC_PCIE_CLK100M_PE4N

NC_PCI_PME_L

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

63 66

Misc Voltages & Control Signals

PP3V3_SW_SD_PWR
SD_CLK
SD_CMD
SD_D<7..0>
SD_CD_L
SD_WP

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

63 65

16 40 69

(Need to add 6 GND TPs)

38 68

41 42 49
6 40 41 42 49

TP_CRT_IG_BLUE

TRUE

FUNC_TEST

TRUE

TRUE

17

40 41 42

J5100: LPC+SPI Connector

TRUE

I675

FUNC_TEST

7 40

(Need to add 2 GND TPs)

TRUE

I677

TRUE

J6950: Battery Connector

(Need 2 TPs)

J4800: SD Card Connector

TRUE

TRUE

POWER SIGNALS

FUNC_TEST
TRUE

TRUE

I678

TRUE

(Need to add 5 GND TPs)

I679

49

FUNC_TEST

TRUE

I680

TRUE

NC_EDP_TXP<0..3>
MAKE_BASE=TRUE
NC_EDP_TXN<0..3>
MAKE_BASE=TRUE
NC_EDP_AUXP
MAKE_BASE=TRUE
NC_EDP_AUXN

38

FUNC_TEST
TRUE

TRUE

TRUE

J6903: Speaker Connector

49

J4700: LIO Connector

TRUE

TRUE

I658

49

(Need to add 2 GND TP)

TRUE

I659

(Need to add 5 GND TPs)

KBDLED_FB
KBDLED_ANODE

J4501: SATA SSD Connector

Functional Test Points


FUNC_TEST

NC_SMC_BS_ALRT_L

SYNC_MASTER=K21_MLB

Functional Test / No Test

NC_TP_XDPPCH_HOOK3

DRAWING NUMBER

NC_TP_XDP_PCH_OBSFN_D<0..1>

Apple Inc.

NC_TP_XDP_PCH_HOOK4
NC_TP_XDP_PCH_HOOK5

NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3

SYNC_DATE=07/29/2011

PAGE TITLE

NC_TP_XDPPCH_HOOK2

051-9277

REVISION

2.8.0

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH
PAGE

7 OF 109

SHEET

6 OF 73

SIZE

"G3Hot" (Always-Present) Rails


53

=PPBUS_G3H

PPBUS_G3H

6 52

55

=PP3V3_S5_REG

PPVIN_SW_TBTBST
VOLTAGE=12.8V

=PPBUS_S0_LCDBKLT
=PPBUS_S0_VSENSE
=PPVIN_SW_TBTBST
=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_HS_OTHER_ISNS_R

65
45
36
8
46

46

PPBUS_S5_HS_OTHER_ISNS

=PPVIN_S5_P5VP3V3

=PPVIN_S5_HS_COMPUTING_ISNS

55

PPBUS_S5_HS_COMPUTING_ISNS

60
61

=PP1V8_S0_REG

52 6

=PP18V5_DCIN_CONN

59

PPDCIN_G3H

61

2A max supply

61
26

54

42
20 22
25
62
62
56

=PPDDR_S3_REG

61

=PP18V5_DCIN_ISOL

=PP3V3_SUS_FET

61
61

PPDCIN_G3H_ISOL

=PPDCIN_S5_CHGR_ISOL
=PPDCIN_S5_VSENSE

53
45

C
=PP3V42_G3H_REG

PP3V42_G3H

25

=PPVRTC_G3_OUT

61

=PP3V3_S3_FET

6 49
42
25

PPVRTC_G3H

16 17 20

5V Rails
PP5V_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S5_P1V5DDRFET
=PP5V_S5_P5VSUSFET
=PP5V_S5_TPAD

61

=PP5V_SUS_FET

PP5V_SUS

61

61

=PP3V3_S0_FET

55

=PP5V_S3_REG

PP5V_S3

22

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S3_AUDIO_AMP
=PP5V_S3_DDRREG
=PP5V_S3_MEMRESET
=PP5V_S3_P5VS0FET
=PP5V_S3_RTUSB
=PP5V_S3_LIO_CONN

61

=PP5V_S0_FET

PP5V_S0

51
56
26
61
39
6 52

=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN
=PP5V_S0_LPCPLUS
=PP5V_S0_VCCSA
=PP5V_S0_PCH
=PP5V_S0_VMON
=PP5V_S0_KBDLED

42
20 22
16 17 18 19

65
57
59
6 48
6 43
54
22 25
62
49

16 19

PP1V05_TBTLC

6 36

25
34 35 36

=PP1V05_TBTLC_FET

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

61
56
31

=PP1V05_TBTCIO_FET

=PP1V05_TBTLC_RTR

35

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_TBTCIO_RTR

10 12 15 26

35

1V05 S0 LDO

62

PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_LDO

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCADPLL

22

=PP3V3R1V5_S0_AUDIO
=PP3V3R1V5_S0_PCH_VCCSUSHDA

20 22 25

PPVTTDDR_S3

6 40

Chipset "VCore" Rails

50
20 22

58

=PPVTT_S3_DDR_BUF

=PPVCORE_S0_CPU_REG

PPVCORE_S0_CPU

=PPVTT_S0_DDR_LDO

=PPVCORE_S0_CPU
=PPCPUVCORE_S0_VSENSE

PP0V75_S0_DDRVTT

58

=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP

37
33
26

=PPVCORE_S0_AXG_REG

54

=PPVCCSA_S0_REG

26

PPVCCSA_S0_CPU

24
31

=PPVCORE_S0_CPU_VCCAXG
=PPGFXVCORE_S0_VSENSE

9 12 15
45

15 12

=PPVCCSA_S0_CPU

12 15

=PPVCCSA_S0_VSENSE

45

=PP1V5_S3_CPU_VCCDQ

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

37
46

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

32

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.9V
MAKE_BASE=TRUE

24

45

PPVCORE_S0_AXG

32

44
44

9 12 14

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

14 12

=PP1V05_S0_CPU_VCCPQE

PP1V05_S0_CPU_VCCPQE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

18 25
46
52
24
60

=PP1V05_SUS_LDO

6 72

VOLTAGE=3.3V
MAKE_BASE=TRUE

PP1V05_SUS

14 12

=PP1V8_S0_CPU_VCCPLL_R

PP1V8_S0_CPU_VCCPLL_R

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

63

PP3V3_S0

=PP3V3_S0_SSD
=PP3V3_S0_HDDISNS
=PP3V3_S0_VMON
=PP3V3_S0_P1V5S0
=PP3V3_S0_TBTPWRCTL
=PP3V3_S0_P1V05S0LDO
=PP3V3_S0_IMVPISNS
=PP3V3_S0_XDP
=PP3V3_S0_BKLTISNS
=PP3V3_S0_SYSCLKGEN
=PP3V3_S0_SATAMUX
=PP3V3_S0_SAISNS
=PP3V3_S0_3V3S0ISNS
=PP3V3_S0_CPU_VCCIO_SEL
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_STRAPS

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

36

6 67

PP1V5_S0

=PPVDDIO_TBT_CLK
=PP3V3_TBTLC_RTR
=PP3V3_TBT_PCH_GPIO

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

56

=PP3V3_S0_CPUVCCIOISNS
=PP3V3_S0_AUDIO
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_HS_COMPUTING_ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_DP_DDC
=PP3V3_S0_FAN
=PP3V3_S0_P3V3TBTFET
=PP3V3_S0_P1V8S0
=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_HS_OTHER_ISNS
=PP3V3_S0_PCH_VCC3_3
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SB_PM
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMC

49

27 28 32
29 30 32

34 35 36

PP3V3_S3

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM

61

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_SUS_PCH

=PP1V5_S0_REG

60

64

=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_WLANISNS
=PP3V3_S3_BMON_ISNS
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_1V5S3ISNS
=PP3V3_S3_DBGLEDS
=PP3V3_S3_USBMUX
=PP3V3_S3_LCD

6 40

=PPVRTC_G3_PCH

=PP5V_S5_LDO

60

26

22

VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S3_BT
=PP3V3_S3_CARDREADER
=PP3V3_S3_MEMRESET
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMBUS_SMC_MGMT

39

60

60

62

64

PP3V3_TBTLC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

6 67

20 22

62
44

PP1V5_S3RS0

=PP1V5_S3_CPU_VCCDDR
=PP1V5_S3RS0_VMON

PP3V3_SW_TBTAPWR

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

53

=PP3V3_TBTLC_FET

25

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S4_TBT

41 42

=PP1V5_S3RS0_FET

37

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
6 43

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE

55

61

49

56 31

=PP3V3_S4_TBTAPWR

=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_CHGR
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3H_SYSCLK
=PP3V42_G3H_ONEWIRE

36
20

33

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.42V
MAKE_BASE=TRUE

60

36

42

=PPHV_SW_DPAPWRSW
=PPHV_SW_TBTAPWRSW

19 20 22

VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_SUS_PCH_VCCSUS
=PP3V3_SUS_GPIO
=PP3V3_SUS_PCH
=PP3V3_SUS_PWRCTL
=PP3V3_SUS_P1V05SUSLDO
=PP3V3_SUS_SMC
=PP3V3_SUS_PCH_VCC_SPI
=PP3V3_SUS_PCH_GPIO
=PP3V3_SUS_ROM
=PP3V3_SUS_PCH_VCCSUS_USB

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE

52

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=17.8V
MAKE_BASE=TRUE

14

=PP1V8_S0_PCH_VCC_DFTERM
=PP1V8_S0_P1V05S0LDO
=PP1V8R1V5_S0_PCH_VCCVRM
=PPVDDIO_S0_SBCLK
=PP1V8_S0_P1V5S0
PP1V5_S3

=PP1V5_S3_MEMRESET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_P1V5S3RS0_FET
=PPVIN_S0_DDRREG_LDO
=PPDDR_S3_MEMVREF

19

PP3V3_SUS
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

53

PP15V_TBT

=PP15V_TBT_REG

MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

64

=PP3V3_S4_BT

=PPDCIN_S5_CHGR

36

=PP1V8_S0_CPU_VCCPLL

25

=PP3V3_S4_SD_HPD
=PP3V3_S4_SMC
=PP3V3_S4_TPAD

58

17

PP3V3_S4
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE

52

=PP3V3_S4_FET

PP1V8_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

57 58
56

TBT Rails (off when no cable)


23

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.4V
MAKE_BASE=TRUE

=PPVIN_S0_CPUIMVP
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
=PPVIN_S0_VCCSAS0
=PPVIN_S0_CPUAXG

6 72

=PP3V3_S5_PCH_VCCDSW
=PP3V3_S5_SYSCLK
=PP3V3_S5_VMON
=PP3V3_S5_PWRCTL
=PP3V3_S4_TBTAPWRSW
=PP3V3_S5_P3V3SUSFET
=PP3V3_S4_P3V3S4FET
=PP3V3_S5_PCH_GPIO

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.4V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S5_XDP
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S5_PCH
=PP3V3_S5_PCHPWRGD
=PP3V3_S5_SMCBATLOW

=PPVIN_S5_HS_OTHER_ISNS

4
1.8V/1.5V/1.2V/1.05V Rails

PP3V3_S5
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.4V
MAKE_BASE=TRUE

36 6

5
3.3V Rails

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V05_SUS_PCH_JTAG

23

PP1V05_S0

45
6 40
65

59

=PPCPUVCCIO_S0_REG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

? mA

46

=PP1V05_S0_CPU_VCCIO
=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCASW

47
8
48
36
60
16 22

9 10 12 14
16 22
20 22
17
16 22
20 22

16 17 18 19 25 36

=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_VMON
=PPVCCIO_S0_CPUIMVP
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCC_DMI
=PPVCCIO_S0_XDP
=PPVCCIO_S0_SMC
=PP1V05_S0_P1V05TBTFET

46
20 22
22
62
25
25
44
44
44
42

20 22
62
57
16 20 22
20 22
20 22
20 22
23
42
36

38
46
62
60
36

SYNC_MASTER=K21_MLB

60

SYNC_DATE=07/29/2011

PAGE TITLE

Power Aliases

45
23

DRAWING NUMBER

46

Apple Inc.

25
38

051-9277

REVISION

2.8.0

45

NOTICE OF PROPRIETARY PROPERTY:

45

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12
22

BRANCH
PAGE

8 OF 109

SHEET

7 OF 73

SIZE

Unused PPT

Plated Board Slot


SL0900
TH-NSP

IN

PCIE_CLK100M_ENET_N

16

IN

PCIE_CLK100M_ENET_P

IN

PCIE_CLK100M_FW_N

IN

PCIE_CLK100M_FW_P

16

IN

PCIE_CLK100M_EXCARD_N

16

16

IN

PCIE_CLK100M_EXCARD_P

69 16

IN

PEG_CLK100M_N

69 16

IN

PEG_CLK100M_P

IN

PCIE_ENET_D2R_N

16

IN

PCIE_ENET_D2R_P

16

IN

PCIE_ENET_R2D_C_N

IN

PCIE_ENET_R2D_C_P

IN

PCIE_FW_D2R_N

16

SL-2.3X3.9-2.9X4.5

16

16

16

CPU Heat Sink Mounting Bosses


Z0913

Z0910

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

16

IN

PCIE_FW_D2R_P

16

IN

PCIE_FW_R2D_C_N

16

IN

PCIE_FW_R2D_C_P

16

IN

PCIE_EXCARD_D2R_N

IN

PCIE_EXCARD_D2R_P

16

IN

PCIE_EXCARD_R2D_C_N

16

IN

PCIE_EXCARD_R2D_C_P

16

Z0911

Z0912

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

67 11

4x 860-1327

NC_PCIE_CLK100M_ENET_N
MAKE_BASE=TRUE
NC_PCIE_CLK100M_ENET_P
MAKE_BASE=TRUE
NC_PCIE_CLK100M_FW_N
MAKE_BASE=TRUE
NC_PCIE_CLK100M_FW_P
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARD_P
MAKE_BASE=TRUE
NC_PEG_CLK100M_N
MAKE_BASE=TRUE
NC_PEG_CLK100M_P
MAKE_BASE=TRUE
NC_PCIE_ENET_D2R_N
MAKE_BASE=TRUE
NC_PCIE_ENET_D2R_P
MAKE_BASE=TRUE
NC_PCIE_ENET_R2D_C_N
MAKE_BASE=TRUE
NC_PCIE_ENET_R2D_C_P
MAKE_BASE=TRUE
NC_PCIE_FW_D2R_N
MAKE_BASE=TRUE
NC_PCIE_FW_D2R_P
MAKE_BASE=TRUE
NC_PCIE_FW_R2D_C_N
MAKE_BASE=TRUE
NC_PCIE_FW_R2D_C_P
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE

67 11

MAKE_BASE=TRUE

16

CPU signals

NO_TEST=TRUE

16

NO_TEST=TRUE
NO_TEST=TRUE

MEMVTT_EN

26

=DDRVTT_EN

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

67 11

MAKE_BASE=TRUE

16

NO_TEST=TRUE
16

NO_TEST=TRUE
16

NO_TEST=TRUE
NO_TEST=TRUE

X21 Boss

Z0905

Z0914

Z0915

STDOFF-4.5OD1.9H-SM

STDOFF-4.5OD1.9H-SM

860-1327

860-1327

860-1327

2.2K

NO_TEST=TRUE

5%
1/20W
MF
201

NO_TEST=TRUE
NO_TEST=TRUE

USB/SD Card Pogo

CRITICAL

CRITICAL

ZS0905

ZS0906

POGO-2.0OD-3.6H-K86-K87

POGO-2.0OD-3.6H-K86-K87

SM

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

17

NO_TEST=TRUE

17

TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA

19

ENET_LOW_PWR_PCH

16

SATARDRVR_EN

VOLTAGE=0V
MIN_NECK_WIDTH=0.075MM
MIN_LINE_WIDTH=0.6MM

16

TP_MEM_A_CLKP<1>
TP_MEM_A_CLKN<1>

470K
1%
1/20W
MF
201

TP_MEM_B_CLKP<1>
TP_MEM_B_CLKN<1>

SL-1.1X0.4-1.4X0.7

DPLL_REF_CLK_N
MAKE_BASE=TRUE

SL-1.1X0.45-1.4X0.75

470K

1%
1/20W
MF
201

SL-1.1X0.4-1.4X0.7

DP_TBTSNK1_HPD

DPA_IG_HPD

DP_TBTSNK0_HPD

69 34

DP_TBTSNK0_AUXCH_C_P

69 34

DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_P

69 34

DP_TBTSNK1_AUXCH_C_N

69 34

DP_TBTSNK1_ML_C_P<3..0>

34 69
34 69
34 69
34 69
34 69
34 69

34

34

DPA_IG_AUX_CH_P

17

DPA_IG_AUX_CH_N

17

DPB_IG_AUX_CH_P

17

DPB_IG_AUX_CH_N

17

69 34

DP_TBTSNK1_ML_C_N<3..0>

TP_DP_IG_C_MLP<3..0>

17

TP_DP_IG_C_MLN<3..0>

69 34

DP_TBTSNK0_ML_C_P<3..0>

17

TP_DP_IG_B_MLP<3..0>

17

TP_DP_IG_B_MLN<3..0>

17

MAKE_BASE=TRUE
17

0.01

65

10 66

1
3

PPBUS_SW_LCDBKLT_PWR
MAKE_BASE=TRUE

DPLL_REF_CLKP

MAKE_BASE=TRUE

R0910

19 23

10 66
72 46

OUT

ISNS_LCDBKLT_P

72 46

OUT

ISNS_LCDBKLT_N

0.5%
1W MF
0612-1

MAKE_BASE=TRUE

2
4

69 34

DP_TBTSNK0_ML_C_N<3..0>

70 34

DP_TBTPB_ML_C_P<1>

MAKE_BASE=TRUE

PPBUS_SW_BKL
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE

OUT

MAKE_BASE=TRUE
70 34

DP_TBTPB_ML_C_N<1>

NC_DP_TBTPB_ML_C_N<1>

70 34

DP_TBTPB_ML_C_P<3>

NC_DP_TBTPB_ML_C_P<3>

70 34

DP_TBTPB_ML_C_N<3>

NC_DP_TBTPB_ML_C_N<3>

MAKE_BASE=TRUE

=PPBUS_SW_BKL

65

IN

USB_EXTC_P

IN

USB_EXTC_N

19

2
4

=PPVIN_S5_HS_COMPUTING_ISNS

72 46

OUT

ISNS_HS_COMPUTING_N

72 46

OUT

ISNS_HS_COMPUTING_P

1%
1W MF

70 34

DP_TBTPB_AUXCH_C_P

NC_DP_TBTPB_AUXCH_C_P

70 34

DP_TBTPB_AUXCH_C_N

NC_DP_TBTPB_AUXCH_C_N

MAKE_BASE=TRUE

1
3

0612

=PPVIN_S5_HS_COMPUTING_ISNS_R

IN

MAKE_BASE=TRUE

70 34

IN

TBT_B_R2D_C_N<0>

70 34

IN

TBT_B_R2D_C_P<0>

IN

TBT_B_R2D_C_N<1>

IN

TBT_B_R2D_C_P<1>

IN

TBT_B_D2R_P<0>

IN

TBT_B_D2R_N<0>

IN

TBT_B_D2R_P<1>

IN

TBT_B_D2R_N<1>

MLB_RAMCFG3
MLB_RAMCFG2

70 34

MLB_RAMCFG1

70 34

MLB_RAMCFG0

70 34

NC_USB_EXTC_P

70 34

MAKE_BASE=TRUE

NO_TEST=TRUE

RAMCFG3:L 1

NC_USB_EXTC_N
MAKE_BASE=TRUE

IN

USB3_EXTC_RX_P

18

IN

USB3_EXTC_RX_N

18

IN

USB3_EXTC_TX_P

IN

USB3_EXTC_TX_N

18

IN

USB3_EXTD_RX_P

18

IN

USB3_EXTD_RX_N

18

IN

USB3_EXTD_TX_P

5%
1/20W
MF
201

NO_TEST=TRUE

NC_USB3_EXTC_RX_N
NO_TEST=TRUE

1RAMCFG0:L

R0952

R0953
10K

5%
1/20W
MF
201

5%
1/20W
MF
201

5%
1/20W
MF
201

10K

70 34

NO_TEST=TRUE

34

NC_USB3_EXTD_RX_P
NC_USB3_EXTD_RX_N
MAKE_BASE=TRUE

IN

USB3_EXTD_TX_N

IN

USB_EXTD_EHCI_N

IN

USB_EXTD_EHCI_P

NO_TEST=TRUE

NO_TEST=TRUE

TP_LVDS_IG_B_CLKP
TP_LVDS_IG_B_CLKN
MAKE_BASE=TRUE

NC_USB_EXTD_EHCI_P

NO_TEST=TRUE

NC_TBT_B_D2R_P<1>
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_D2R_N<1>
NO_TEST=TRUE

MAKE_BASE=TRUE

TBT_B_CIO_SEL
34
DP_TBTPB_HPD
TBT_B_CONFIG2_RC
TBT_B_CONFIG1_BUF
TBT_B_LSRX
1

R0916

R0917

R0918

R0919

R0914

10K

10K

10K

10K

5%
1/20W
MF
201

5%
1/20W
MF
201

5%
1/20W
MF
201

5%
1/20W
MF
201

5%
1/20W
MF
201

10K

LVDS_IG_B_CLK_N

LVDS_IG_A_DATA_P<3>

P1V5S3RS0_RAMP_DONE

IN

61

65

DDRREG_PGOOD

IN

56

63

MAKE_BASE=TRUE

LCD_BKLT_PWM

34

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE

LVDS_IG_B_DATA_N<0..3>

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE

LVDS_IG_B_DATA_P<0..3>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<0..3>

NO_TEST=TRUE

Unused PGOOD signal


TP_P1V5S3RS0_RAMP_DONE

NO_TEST=TRUE

NC_TBT_B_D2R_N<0>
MAKE_BASE=TRUE

LVDS_IG_B_CLK_P

NC_LVDS_IG_B_DATAP<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_D2R_P<0>
MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_USB_EXTD_EHCI_N
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_R2D_C_P<1>
MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_USB3_EXTD_TX_N
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_R2D_C_N<1>
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_TX_P

18

34

LVDS Aliases

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_TBT_B_R2D_C_P<0>
MAKE_BASE=TRUE

34

NC_USB3_EXTC_TX_N
MAKE_BASE=TRUE

NC_TBT_B_R2D_C_N<0>
MAKE_BASE=TRUE

34

NO_TEST=TRUE

MAKE_BASE=TRUE

18

2x TBT pin diodes

1 RAMCFG1:L

10K

NC_USB3_EXTC_TX_P
MAKE_BASE=TRUE

18

R0951

10K

NC_USB3_EXTC_RX_P
MAKE_BASE=TRUE

1RAMCFG2:L

R0950

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

70 34

19

NC_DP_TBTPB_ML_C_P<1>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

IN

TBT_B_LSTX

NC_TBT_B_LSTX
MAKE_BASE=TRUE

LVDS_IG_A_DATA_N<3>

NO_TEST=TRUE

NO_TEST=TRUE

LVDS_IG_BKL_PWM

17

LVDS_IG_PANEL_PWR

17

LVDS_IG_BKL_ON

17

MAKE_BASE=TRUE

LCD_IG_PWR_EN
MAKE_BASE=TRUE

65

LCD_BKLT_EN
MAKE_BASE=TRUE

SATA Aliases

2x MDP Connector

SL0907
TH-NSP
1

2x TBT chip

SMC Aliases

Unused SATA ODD Signals


IN

SATA_ODD_R2D_C_P

16

IN

SATA_ODD_R2D_C_N

16

OUT

SATA_ODD_D2R_P

OUT

SATA_ODD_D2R_N

16

Unused SMC Signals

NC_SATA_ODD_R2DCP
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_ODD_R2DCN
MAKE_BASE=TRUE

NO_TEST=TRUE

41

IN

SMC_SYS_LED

NO_TEST=TRUE

41

IN

IR_RX_OUT_RC

NC_SATA_ODD_D2RP
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_IR_RX_OUT_RC
MAKE_BASE=TRUE

NC_SATA_ODD_D2RN
MAKE_BASE=TRUE

NC_SMC_SYS_LED
MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

SYNC_MASTER=J13_MLB_NON_POR

SL0908
TH-NSP
SL-1.1X0.4-1.4X0.7

DPB_IG_HPD

17

17

0.002

34 69
34 69

MAKE_BASE=TRUE

SSD PCIE Signals


SL0904
TH-NSP

34 69

PCIE_TBT_D2R_P<0>
PCIE_TBT_D2R_P<1>
MAKE_BASE=TRUE
PCIE_TBT_D2R_P<2>
MAKE_BASE=TRUE
PCIE_TBT_D2R_P<3>
MAKE_BASE=TRUE
PCIE_TBT_D2R_N<0>
MAKE_BASE=TRUE
PCIE_TBT_D2R_N<1>
MAKE_BASE=TRUE
PCIE_TBT_D2R_N<2>
MAKE_BASE=TRUE
PCIE_TBT_D2R_N<3>
MAKE_BASE=TRUE

17

69 34

DPA_IG_DDC_DATA

16 23

SL0906
TH-NSP

SL-1.1X0.45-1.4X0.75

34 69

MAKE_BASE=TRUE

DPA_IG_DDC_CLK

DP_TBTSNK0_DDC_DATA

34 69

MAKE_BASE=TRUE

R0954

16

MAKE_BASE=TRUE

34 69

MAKE_BASE=TRUE

CRITICAL

DPLL_REF_CLKN

DPLL_REF_CLK_P
MAKE_BASE=TRUE

TP_PCH_CLKOUT_DPP

TP_DDRREG_PGOOD

SL-1.1X0.4-1.4X0.7

MAKE_BASE=TRUE

34 69
34 69

MAKE_BASE=TRUE

MAKE_BASE=TRUE

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

MAKE_BASE=TRUE

SL0905
TH-NSP

DP_TBTSNK0_DDC_CLK

64

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

TP_PCH_CLKOUT_DPN

SL0902
TH-NSP
1

MAKE_BASE=TRUE

34 69

TBT DP Ports

CRITICAL

18

Can Slots

MAKE_BASE=TRUE

34 69

MAKE_BASE=TRUE

R09241 R09251

MAKE_BASE=TRUE

GND

SL-1.1X0.4-1.4X0.7

16

=PP3V3_S0_DP_DDC

8 7

MAKE_BASE=TRUE

18

17 16

870-1938

Digital Ground

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<0>
PCIE_TBT_R2D_C_P<1>
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_R2D_C_P<3>
PCIE_TBT_R2D_C_N<0>
PCIE_TBT_R2D_C_N<1>
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_R2D_C_N<3>

MAKE_BASE=TRUE

18

SL0903
TH-NSP

17 16

MAKE_BASE=TRUE

18

SL-1.1X0.4-1.4X0.7

16

DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
DP_IG_D_CTRL_CLK
MAKE_BASE=TRUE
DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

NC_PCIE_5_D2RP
NC_PCIE_6_D2RP
NC_PCIE_7_D2RP
NC_PCIE_8_D2RP
NC_PCIE_5_D2RN
NC_PCIE_6_D2RN
NC_PCIE_7_D2RN
NC_PCIE_8_D2RN

NO_TEST=TRUE

Unused USB

16
16

MAKE_BASE=TRUE

NO_TEST=TRUE

19

SL0901
TH-NSP

2.2K
5%
1/20W
MF
201

MAKE_BASE=TRUE

MAKE_BASE=TRUE

19

5%
1/20W
MF
201

MAKE_BASE=TRUE

NO_TEST=TRUE

SM

870-1938

2.2K

16

5%
1/20W
MF
201

16

NO_TEST=TRUE

EMI I/O Pogo Pins


DisplayPort Pogo

2.2K

NC_PCIE_5_R2D_CP
NC_PCIE_6_R2D_CP
NC_PCIE_7_R2D_CP
NC_PCIE_8_R2D_CP
NC_PCIE_5_R2D_CN
NC_PCIE_6_R2D_CN
NC_PCIE_7_R2D_CN
NC_PCIE_8_R2D_CN

MAKE_BASE=TRUE

R09201 R09211 R09221 R09231

NO_TEST=TRUE

64

16

16

NO STUFF NO STUFF

NO_TEST=TRUE

SSD Boss

STDOFF-4.5OD1.8H-SM

16

=PP3V3_S0_DP_DDC

8 7

MAKE_BASE=TRUE

Fan Boss

26 56

MAKE_BASE=TRUE

MAKE_BASE=TRUE
67 11

16

SYNC_DATE=11/10/2011

PAGE TITLE

2x USB Connector

IN

=PEG_D2R_P<1..0>

IN

=PEG_D2R_N<1..0>

IN

=PEG_R2D_C_P<1..0>

IN

=PEG_R2D_C_N<1..0>

PCIE_SSD_D2R_P<1..0>
MAKE_BASE=TRUE
PCIE_SSD_D2R_N<1..0>
MAKE_BASE=TRUE
PCIE_SSD_R2D_C_P<1..0>
MAKE_BASE=TRUE
PCIE_SSD_R2D_C_N<1..0>
MAKE_BASE=TRUE

17

OUT

6 38 66

OUT

6 38 66

OUT

38 66

OUT

38 66

TP_DP_IG_D_HPD

Signal Aliases

DP_IG_D_HPD

DRAWING NUMBER

MAKE_BASE=TRUE

Apple Inc.

R09091
100K

5%
1/20W
MF
201 2

051-9277

REVISION

2.8.0

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH
PAGE

9 OF 109

SHEET

8 OF 73

SIZE

3
NOTE:

OMIT_TABLE
66

IN

66 17

IN

66 17

14 12 10 9 7

IN

66 17

IN

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

66 17

OUT

24.9 2
1%
1/20W
MF
201

N3
P7
P3
P11

DMI_RX_0
DMI_RX_1
DMI_RX_2
DMI_RX_3

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

K1
M8
N4
R2

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>

W6
V4
Y2
AC9

FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>

U6
W10
W3
AA7

FDI0_TX_0
FDI0_TX_1
FDI0_TX_2
FDI0_TX_3

FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>

W7
T4
AA3
AC8

FDI1_TX_0
FDI1_TX_1
FDI1_TX_2
FDI1_TX_3

66 17

OUT

66 17

OUT

66 17

OUT

66 17

IN

66 17

IN

FDI_FSYNC<0>
FDI_FSYNC<1>

66 17

IN

FDI_INT

IN

66 17

IN
66

AA11
AC12
U11

FDI_LSYNC<0>
FDI_LSYNC<1>
EDP_COMP

66 63
66 63

66 63
6
6
6
66 63
6

6
6

EDP_HPD_L

FDI0_TX_0*
FDI0_TX_1*
FDI0_TX_2*
FDI0_TX_3*
FDI1_TX_0*
FDI1_TX_1*
FDI1_TX_2*
FDI1_TX_3*

FDI0_FSYNC
FDI1_FSYNC
FDI_INT

AA10
AG8

FDI0_LSYNC
FDI1_LSYNC

AD2
AF3

EDP_ICOMPO
EDP_COMPIO

PLACE_NEAR=U1000.AF3:12.7MM

DMI_TX_0
DMI_TX_1
DMI_TX_2
DMI_TX_3

U7
W11
W1
AA6

OUT

66 17

K3
M7
P4
T3

AG11

DP_INT_AUX_CH_N
DP_INT_AUX_CH_P

AG4
AF4

BGA
(1 OF 9)

DMI_TX_0*
DMI_TX_1*
DMI_TX_2*
DMI_TX_3*

FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>

66 17

=PP1V05_S0_CPU_VCCIO

R1030

IN

66 17

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

IVY-BRIDGE
2C-35W

EDP_HPD
EDP_AUX*
EDP_AUX

DP_INT_ML_N<0>
TP_EDP_TX_N<1>
TP_EDP_TX_N<2>
TP_EDP_TX_N<3>

AC3
AC4
AE11
AE7

EDP_TX_0*
EDP_TX_1*
EDP_TX_2*
EDP_TX_3*

DP_INT_ML_P<0>
TP_EDP_TX_P<1>
TP_EDP_TX_P<2>
TP_EDP_TX_P<3>

AC1
AA4
AE10
AE6

EDP_TX_0
EDP_TX_1
EDP_TX_2
EDP_TX_3

Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating


even if internal Graphics is disabled since they are
shared with other interfaces.

NOTE: The EDP_HPD processor input is a low voltage active low signal.
Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device
to low voltage signals for the processor
(refer to latest Processor EDS for DC specifications).
If HPD is disabled while eDP interface is still enabled,
connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.
This signal can be left as no-connect if entire eDP interface is disabled.

66 23 9
66 23 9
66 23 9
66 23 9
66 23 9

23 9

CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<2>
NOSTUFF

R1042
1K

=PP1V05_S0_CPU_VCCIO

CRITICAL

1%
1/20W
MF
201

PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*
PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
=PEG_D2R_P<12>
=PEG_D2R_P<13>
=PEG_D2R_P<14>
=PEG_D2R_P<15>

PEG_TX_0*
PEG_TX_1*
PEG_TX_2*
PEG_TX_3*
PEG_TX_4*
PEG_TX_5*
PEG_TX_6*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<15>

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

R1064

IN

49.9

49.9

IN

IN

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

IN

IN

IN

IN

IN

Note. VOLTAGE=1.05V

IN

Note. VOLTAGE=0V

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

PLACE_NEAR=U1000.H43:50.8MM
PLACE_SIDE=BOTTOM

=PPVCORE_S0_CPU
1

1 NOSTUFF

R1070

2
PLACE_NEAR=U1000.H45:50.8MM
PLACE_SIDE=BOTTOM
Note. VOLTAGE=1.25V
Note. VOLTAGE=0V

NOSTUFF

R1065

IN

66 23 9

IN

66 23 9

IN

66 23 9

IN

66 23 9

IN

66 23 9

IN

66 23 9

IN

66 23 9

IN

66 23

IN

66 23

IN

66 23

IN

66 23

IN

23
66
66 23

IN

66 23

IN

66 23

IN

23 9

IN

23

IN

7 12 15

IN

R1071
49.9

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

NOTE:

CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17

U1000

BGA
(5 OF 9)
RESERVED

H43 VCC_VAL_SENSE
K43 VSS_VAL_SENSE

CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N

H45 VAXG_VAL_SENSE
K45 VSSAXG_VAL_SENSE

TP_CPU_VCC_DIE_SENSE

F48 VCC_DIE_SENSE

72 47

OUT

72 47

OUT

CPU_THERMD_P
CPU_THERMD_N

H48 RSVD_6
K48 RSVD_7

Intel does not recommend to use

BA19 RSVD_8
this alnalog sense due to accuracy concern.NC
2
AV19 RSVD_9
PLACE_NEAR=U1000.K45:50.8MM
NC
AT21 RSVD_10
PLACE_SIDE=BOTTOM

NC
BB21
NC
BB19
NC
AY21
NC
BA22
NC
AY22
NC
AU19
NC
AU21
NC
BD21
NC
BD22
NC
BD25
NC
BD26
NC
BG22
NC
BE22
NC
BG26
NC
BE26
NC
BF23
NC
BE24
NC

PLACE_NEAR=U1000.K43:50.8MM
PLACE_SIDE=BOTTOM

NOTE: Intel validation sense lines per


doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27

PPCPU_MEM_VREFDQ_A
PPCPU_MEM_VREFDQ_B

SA_DIMM_VREFDQ BE7
SB_DIMM_VREFDQ BG7

CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N

1 NOSTUFF

49.9

66 23 9

7 12 14

=PPVCORE_S0_CPU_VCCAXG

NOSTUFF

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V

7 9 10 12 14

RSVD_30
RSVD_31
RSVD_32
RSVD_33

N42
NC
L42
NC
L45
NC
L47

RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38

M13
NC
M14
NC
U14
NC
W14
NC
P13

CPU_CFG<3>
CPU_CFG<1>
9 CPU_CFG<0>

66 23 9
66 23

14 12 10 9 7

31

OUT

31

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V

NC

NC

RSVD_39 AT49
NC
RSVD_40 K24 NC
RSVD_41
RSVD_42
RSVD_43
RSVD_44

AH2
NC
AG13
NC
AM14
NC
AM15

NC

RSVD_45 N50 NC

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

A4
TP_CPU_DC_TEST_A4
C4
CPU_DC_TEST_C4_D3
D3
D1
TP_CPU_DC_TEST_D1
A58 TP_CPU_DC_TEST_A58
A59 CPU_DC_TEST_C59_A59
C59
A61 CPU_DC_TEST_C61_A61
C61
D61 TP_CPU_DC_TEST_D61
BD61 TP_CPU_DC_TEST_BD61
BE61 CPU_DC_TEST_BE59_BE61
BE59
BG61 CPU_DC_TEST_BG59_BG61
BG59
BG58 TP_CPU_DC_TEST_BG58
BG4
TP_CPU_DC_TEST_BG4
BG3
CPU_DC_TEST_C4_BE3_BG3
BE3
BG1
CPU_DC_TEST_C4_BE1_BG1
BE1
BD1
TP_CPU_DC_TEST_BD1

=PP1V05_S0_CPU_VCCIO
PLACE_NEAR=U1000.AG11:12.7MM

R1031

1K

EDP:YES

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

R1044

R1045

R1046

R1047

R1040

R1041

R1043

R1049

1K

1K

1K

1K

1K

1K

1K

1K

5%

5%

5%

5%

5%

5%

5%

5%

5%

1/16W

1/16W

1/16W

1/16W

1/16W

1/16W

1/16W

1/16W

MF-LF

MF-LF

MF-LF

MF-LF

MF-LF

MF-LF

MF-LF

MF-LF

402

402

402

402

402

402

402

5%
1/20W
MF
2 201

402

EDP_HPD_L

D 3

2
63

DP_INT_HPD

SYNC_MASTER=J13_MLB_NON_POR

Q1031

1
G

CPU DMI/PEG/FDI/RSVD

SOT-523-3

S 2

EDP:YES

DRAWING NUMBER

CFG [7] :PEG DEFER TRAINING

Apple Inc.

CR SFF Intel doc #460452


Rise/Fall time <6ns

FOR IVYBRIDGE PROCESSOR

SYNC_DATE=10/17/2011

PAGE TITLE

2N7002TXG

These can be Placed close to J2500 and Only for debug access

051-9277

1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB

CFG [6:5] :PCIE BIFURCATION

11 = 1 X16 (DEFAULT)
1 = DISABLED

CFG [3] :PCIE x4 LANE REVERSAL

1 = NORMAL OPERATION

0 = LANES REVERSED

CFG [2] :PCIE x16 LANE REVERSAL

1 = NORMAL OPERATION

0 = LANES REVERSED

10 = 2 X8

NOTICE OF PROPRIETARY PROPERTY:

0 = WAIT FOR BIOS

01 = RSVD

00 = X8, X4, X4

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

0 = ENABLED

SIZE

REVISION

2.8.0

CFG [4] :eDP ENABLE/DISABLE

OUT

CPU_CFG<16>

MF-LF

OMIT_TABLE

66 23 9

1/16W

402

24.9

PLACE_NEAR=U1000.G3:12.7MM

PEG_ICOMPI G3
PEG_ICOMPO G1
PEG_RCOMPO G4

PCI EXPRESS BASED INTERFACE SIGNALS

IN

66 17

U1000

DMI

66 17

DMI_RX_0*
DMI_RX_1*
DMI_RX_2*
DMI_RX_3*

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

IN

M2
P6
P1
P10

EMBEDDED DISPLAY PORT

IN

66 17

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

CPU_PEG_COMP

Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

R1010

CRITICAL
66 17

2C-35W

IVY-BRIDGE

BRANCH
PAGE

10 OF 109

SHEET

9 OF 73

D
OMIT_TABLE

=PP1V05_S0_CPU_VCCIO

CRITICAL

NOSTUFF

1K

5%
1/20W
MF
201

NC
19

66 41

66 42 19

R1103
66 57 42 41

26 15 12 7

BI

CPU_PROCHOT_L

56

PLACE_NEAR=R1121.2:1MM

R11201

CPU_PROC_SEL_L

OUT

CPU_CATERR_L

66 42 19

OUT

200

1%
1/20W
MF
201 2

C
66 26 17

IN

66 17

R1121

PM_MEM_PWRGD

130

A48 PECI

66 23 19

C45 PROCHOT*

PM_THRMTRIP_L

D45 THERMTRIP*

IN

PM_SYNC

C48 PM_SYNC

IN

CPU_PWRGD

B46 UNCOREPWRGOOD

PLACE_NEAR=U1000.BE45:12.7MM

PM_MEM_PWRGD_R

1%
1/20W
MF
201

BE45 SM_DRAMPWROK

PLT_RESET_LS1V1_L
26

OUT

D44 RESET*

=MEM_RESET_L

AT30 SM_DRAMRST*
66
66
66

14 12 10 9 7

CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>

BF44 SM_RCOMP_0
BE43 SM_RCOMP_1
BG43 SM_RCOMP_2

=PP1V05_S0_CPU_VCCIO
1

4.99K

R1112 1R1113 1R1114

75

1%
1/20W
MF
201 2
25 23

IN

BCLK_ITP N59
BCLK_ITP* N58

IN

16 66

IN

16 66

DPLL_REF_CLKP
DPLL_REF_CLKN

IN

8 66

IN

8 66

ITPCPU_CLK100M_P
ITPCPU_CLK100M_N

IN

16 66

IN

16 66

140

25.5

200

1%
1/20W
MF
201

1%
1/20W
MF
201

1%
1/20W
MF
201

(IPU)
(IPU)

PRDY* N53
PREQ* N55

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

(IPU)
(IPU)
(IPU)

TCK L56
TMS L55
TRST* J58

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

(IPU)

TDI M60
TDO L59
DBR* K58

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*

G58
E55
E59
G55
G59
H60
J59
J61

OUT

23 66

IN

23 66

IN

23 66

IN

23 66

IN

23 66

XDP_CPU_TDI
XDP_CPU_TDO

IN

23 66

OUT

23 66

XDP_DBRESET_L

OUT

23 25 66

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

BI

23 66

BI

23 66

BI

23 66

BI

23 66

BI

23 66

BI

23 66

BI

23 66

BI

23 66

NOSTUFF

R1115

R11261

DPLL_REF_CLK AG3
DPLL_REF_CLK* AG1

DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

C49 CATERR*

CPU_PECI

BI

C57 PROC_DETECT*
F49 PROC_SELECT*

CPU_PROCHOT_R_L

5%
1/20W
MF
201

=PP1V5_S3_CPU_VCCDDR

OUT

BCLK J3
BCLK* H2

BGA
(2 OF 9)

5%
1/20W
MF
2 201

JTAG & BPM

62

IVY-BRIDGE
2C-35W

1K

5%
1/20W
MF
201
2

THERMAL

R1101

51

5%
1/20W
MF
201 2

PWR MGMT

NOSTUFF

R1104 1R1102

CLOCKS

NOSTUFF

R11001

U1000

DDR3 MISC

14 12 10 9 7

1%
1/20W
MF
201

PLACE_NEAR=U1000.B46:12.7MM

R1111
10K
5%
1/20W
MF

2 201

R1125

CPU_RESET_L

43.2
1%
1/20W
MF
201

PLACE_NEAR=U1000.BF44:12.7MM
PLACE_NEAR=U1000.BE43:12.7MM
PLACE_NEAR=U1000.BG43:12.7MM

Intel Doc 460452 ChiefRiver SFF DG rev1.0 section 2.7.11 recommendation R1115.

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

PAGE TITLE

CPU CLOCK/MISC/JTAG
DRAWING NUMBER

Apple Inc.

051-9277

NOTICE OF PROPRIETARY PROPERTY:

2.8.0

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION
BRANCH
PAGE

11 OF 109

SHEET

10 OF 73

OMIT_TABLE

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 27

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 28

BI

67 32 28 27

OUT

67 32 28 27

OUT

67 32 28 27

OUT

67 32 28 27

OUT

67 32 28 27

OUT

67 32 28 27

OUT

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>

BD37
BF36
BA28

SA_BS_0
SA_BS_1
SA_BS_2

MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L

BE39
BD39
AT41

SA_CAS*
SA_RAS*
SA_WE*

U1000
BGA
(3 OF 9)

2C-35W

67 27

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

IVY-BRIDGE

BI

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

CRITICAL
SA_CK_0 AU36
SA_CK_0* AV36

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

SA_CKE_0 AY26

MEM_A_CKE<0>

SA_CK_1 AT40
SA_CK_1* AU40
SA_CKE_1 BB26
SA_CS_0* BB40
SA_CS_1* BC41
SA_ODT_0 AY40
SA_ODT_1 BA41

MEMORY CHANNEL A

BI

67 27

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

OMIT_TABLE

CRITICAL
67 27

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_ODT<1>

SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

OUT

27 28 32 67

67 29

BI

OUT

27 28 32 67

67 29

BI

67 29

OUT

27 28 32 67

BI

OUT

8 67

OUT

8 67

OUT

27 28 32 67

67 29

BI

67 29

BI

67 29

BI

67 29

BI

67 29

BI

67 29

BI

OUT

27 28 32 67

67 29

BI

OUT

27 28 32 67

67 29

BI

67 29

BI

OUT

27 28 32 67

67 29

BI

OUT

27 28 32 67

67 29

BI

67 29

BI

BI

27 67

67 29

BI

BI

27 67

67 29

BI

BI

27 67

67 29

BI

BI

27 67

67 29

BI

BI

28 67

67 29

BI

BI

28 67

67 29

BI

BI

28 67

67 29

BI

BI

28 67

67 29

BI

67 29

BI

BI

27 67

67 29

BI

BI

27 67

67 29

BI

BI

27 67

67 29

BI

BI

27 67

67 29

BI

BI

28 67

67 29

BI

BI

28 67

67 29

BI

BI

28 67

67 29

BI

BI

28 67

67 29

BI

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

OUT

27 28 32 67

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 30

BI

67 32 30 29

OUT

67 32 30 29

OUT

67 32 30 29

OUT

67 32 30 29

OUT

67 32 30 29

OUT

67 32 30 29

OUT

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

BG39
BD42
AT22

SB_BS_0
SB_BS_1
SB_BS_2

MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L

AV43
BF40
BD45

SB_CAS*
SB_RAS*
SB_WE*

U1000

BGA
(4 OF 9)

IVY-BRIDGE
2C-35W

MEMORY CHANNEL B

SB_CK_0 BA34
SB_CK_0* AY34

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

SB_CKE_0 AR22

MEM_B_CKE<0>

SB_CK_1 BA36
SB_CK_1* BB36

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

SB_CKE_1 BF27

MEM_B_CKE<1>

SB_CS_0* BE41
SB_CS_1* BE47
SB_ODT_0 AT43
SB_ODT_1 BG47

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

8 67

OUT

8 67

OUT

29 30 32 67

MEM_B_CS_L<0>
MEM_B_CS_L<1>

OUT

29 30 32 67

OUT

29 30 32 67

MEM_B_ODT<0>
MEM_B_ODT<1>

OUT

29 30 32 67

OUT

29 30 32 67

SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

BI

29 67

BI

29 67

BI

29 67

BI

29 67

BI

30 67

BI

30 67

BI

30 67

BI

30 67

BI

29 67

BI

29 67

BI

29 67

BI

29 67

BI

30 67

BI

30 67

BI

30 67

BI

30 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

OUT

29 30 32 67

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

PAGE TITLE

CPU DDR3 INTERFACES


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

12 OF 109

SHEET

11 OF 73

15 12 9 7

=PP1V05_S0_CPU_VCCIO

(NOT controlled by VCCIO_SEL)


Fixed at 1.05V

AG48
AG50

AB50 VAXG_3
AB51 VAXG_4
AB52 VAXG_5

AG51
AJ17

AB53 VAXG_6
AB55 VAXG_7

AJ21

AB56 VAXG_8
AB58 VAXG_9
AB59 VAXG_10

AA14

VCCIO_50
VCCIO_51

W16

AK50
AK51
AL15
AL16

AD50 VAXG_14
AD51 VAXG_15
AD52 VAXG_16

AL20
AL22

AD53 VAXG_17
AD55 VAXG_18

AL26

AD56 VAXG_19
AD58 VAXG_20
AD59 VAXG_21

AL14

AL45
AL48

AE46 VAXG_22
N45 VAXG_23
P47 VAXG_24

AM16
AM17
AM21
AM47
AN20

P48 VAXG_25
P50 VAXG_26
P51 VAXG_27

AN42
AN45

P52 VAXG_28
P53 VAXG_29

AN48

P55 VAXG_30
P56 VAXG_31
P61 VAXG_32

AM43

AA15
AB17
AC13
AD16

T61 VAXG_36
U46 VAXG_37
V47 VAXG_38

AD18
AD21
AE15
AF16
AF20
AG15
AG17
AG20

=PP3V3_S0_CPU_VCCIO_SEL
NOSTUFF

R13201

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU_VCCAXG

VCCIO_SEL

BC22

CPU_VCCIO_SEL

VCCPQE_1
VCCPQE_2

AM25

=PP1V05_S0_CPU_VCCPQE

R1300

130

1% PLACE_NEAR=U1000.C44:2.54mm
1/20W
MF
43
2 201

R1310

201 1/20W

2 5%

B43
C44

CPU_VIDALERT_L_R
CPU_VIDSCLK_R
CPU_VIDSOUT_R

VCC_SENSE
VSS_SENSE

F43
G43

CPU_VCCSENSE_P
CPU_VCCSENSE_N

100

PLACE_NEAR=U1000.F45:50.8mm
PLACE_SIDE=BOTTOM

CPU_VIDALERT_L

R1311

201 1/20W

A44

R1370

1%
1/20W
MF
201

MF

201 1/20W

0 1

2 5%

CPU_VIDSCLK

MF

R1312

IN

1%
1/16W
MF-LF
2 402

57 66

66 57

OUT

57 66

OUT

66 57

OUT

CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
14 7

2 5%

CPU_VIDSOUT

MF

BI

100

PLACE_NEAR=U1000.F43:50.8mm 1%
PLACE_SIDE=BOTTOM1/16W
MF-LF
402

R1371

7 9 10 12 14

PLACEMENT NOTE:
OUT

Note. VOLTAGE=0V
Note. VOLTAGE=1.05V

PLACE_NEAR=U1000.G45:50.8mm
PLACE_SIDE=BOTTOM

100

1%
1/16W
MF-LF
402

Note. VOLTAGE=0V

Please place all sense line resistors on BOTTOM side.

57 66

OUT

57 66

OUT

59 66

OUT

59 66

AN30
AN34
AN38
AR26
AR28
15 12 7

AR30
AR32
AR34
26 15 12 10 7

AR36

=PPVCCSA_S0_CPU

=PP1V5_S3_CPU_VCCDDR

R13821

AR40
AV41

100

1%
PLACE_NEAR=U1000.U10:50.8mm
1/20W
MF
1
201

AW26

R1380

BA40
BB28

PLACE_NEAR=U1000.BC43:50.8mm 100
1%
PLACE_SIDE=BOTTOM
1/20W
MF
201 2

BG33

=PP1V5_S3_CPU_VCCDQ

7 15

AN26

BA43

CPU_VDDQ_SENSE_P
Note.
CPU_VDDQ_SENSE_N

VCCSA_SENSE

U10

CPU_VCCSASENSE

VCCSA_VID_0
VCCSA_VID_1

D48
D49

CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>

VOLTAGE=1.05V

Note. VOLTAGE=0V
OUT

OUT

CPU_DDR_VREF
12
VOLTAGE=0.75V

AY43

54

54
54

R13811

1 1

1%
PLACE_NEAR=U1000.BA43:50.8mm
1/20W
PLACE_SIDE=BOTTOM
MF
201 2

R1313
10K

2 2

5%
1/20W
MF
201

PLACEMENT NOTE:

Please place all sense line resistors on BOTTOM side.

F45 VAXG_SENSE
G45 VSSAXG_SENSE
BB3 VCCPLL_1
BC1 VCCPLL_2

26 15 12 10 7

=PP1V5_S3_CPU_VCCDDR

R1330

1K
5%

PLACE_NEAR=U1000.AY43:2.54mm 1/20W

MF
201 2

CPU_DDR_VREF

=PPVCCSA_S0_CPU

PLACE_NEAR=U1000.AN16:50.8mm
PLACE_SIDE=BOTTOM

Note. VOLTAGE=1.25V

AM36
AM40

5%
1/20W
MF
201

W55 VAXG_52
W56 VAXG_53
W61 VAXG_54

BC4 VCCPLL_3

R1362
1%
1/16W
MF-LF
402

Note. VOLTAGE=0V

=PP1V8_S0_CPU_VCCPLL_R

100

Note. VOLTAGE=1.05V

15 12 7

7 9 12 14

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

R1360

AM33

Y48 VAXG_55
Y61 VAXG_56

57 66

=PPVCORE_S0_CPU
=PP1V05_S0_CPU_VCCIO
1

AL38
AL42

10K

PLACE_NEAR=U1000.A44:38mm

7 14

AN22

VIDALERT*
VIDSCLK
VIDSOUT

75

AL34

W52 VAXG_50
W53 VAXG_51

PLACE_NEAR=U7400.17:2.54mm
1

R1302

IVB supports 1.05V VCCIO.


VCCIO_SEL can be NC.

AN17

15 12 9 7

7 9 10 12 14

10K

5%
1/20W
MF
201 2

AJ40
AL30

R1314

V59 VAXG_47
W50 VAXG_48
W51 VAXG_49

AJ33
AJ36

100

V55 VAXG_44
V56 VAXG_45
V58 VAXG_46

AG16

AN16

VDDQ_SENSE
VSS_SENSE_VDDQ

BC43

SM_VREF

V51 VAXG_41
V52 VAXG_42
V53 VAXG_43

AF18

W17

AM28

(IPU)

V48 VAXG_39
V50 VAXG_40

AE14

AJ15

VCCDQ_1
VCCDQ_2

(IPU)

T48 VAXG_33
T58 VAXG_34
T59 VAXG_35

AB20

AG21
AJ14

AJ28

AC61 VAXG_11
AD47 VAXG_12
AD48 VAXG_13

AJ47

GRPHICS

VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCIO_46
VCCIO_47
VCCIO_48
VCCIO_49

AJ25
AJ43

=PP1V5_S3_CPU_VCCDDR
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26

DDR3-1.5V RAILS

AF46

BGA
(7 OF 9)

QUIET
RAIL

VCCIO_1
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8
VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29

VCCIO_SENSE
VSS_SENSE_VCCIO

CRITICAL

U1000

AA46 VAXG_1
AB47 VAXG_2

SENSE
LINE

2C-35W

CORE SUPLLY

PEG AND DDR

IVY-BRIDGE

BGA
(6 OF 9)

QUIET
RAIL

U1000

SVID

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76

OMIT_TABLE

SENSE
LINE

CRITICAL
A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

=PPVCORE_S0_CPU_VCCAXG

1.8V
RAIL

OMIT_TABLE

SENSE
LINES

14 12 9 7

=PPVCORE_S0_CPU

2C-35W

IVY-BRIDGE

L17 VCCSA_1
L21 VCCSA_2

R13311

N22 VCCSA_5
P17 VCCSA_6
P20 VCCSA_7
R16 VCCSA_8
R18 VCCSA_9

1K

PLACE_NEAR=U1000.AY43:2.54mm

N16 VCCSA_3
N20 VCCSA_4

5%
1/20W
MF
201 2

SA RAIL

12

C1330
0.1UF
10%
16V

2 X5R-CERM
0201

PLACE_NEAR=U1000.AY43:2.54mm

R21 VCCSA_10
U15 VCCSA_11
V16 VCCSA_12
V17 VCCSA_13
V18 VCCSA_14
V21 VCCSA_15
W20 VCCSA_16

R13611

100

1%
1/16W

PLACE_NEAR=U1000.G43:50.8mm MF-LF
PLACE_SIDE=BOTTOM
402

R1363
100

1%
1/16W
MF-LF

PLACE_NEAR=U1000.AN17:50.8mm
PLACE_SIDE=BOTTOM

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

PAGE TITLE

2 402

CPU POWER
DRAWING NUMBER

PLACEMENT NOTE:

Apple Inc.

Please place all sense line resistors on BOTTOM side.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

13 OF 109

SHEET

12 OF 73

OMIT_TABLE

CRITICAL
OMIT_TABLE

BG21 VSS
BG24 VSS
BG28 VSS

BG37 VSS
BG41 VSS
BG45 VSS
BG49 VSS
BG53 VSS

U1000

BGA
(9 OF 9)
VSS

IVY-BRIDGE
2C-35W

BG13 VSS
BG17 VSS

C29 VSS
C35 VSS
C40 VSS
D4 VSS
D6 VSS
D10 VSS
D14 VSS
D18 VSS
D22 VSS
D26 VSS
D29 VSS
D35 VSS
D40 VSS
D43 VSS
D46 VSS
D50 VSS
D54 VSS
D58 VSS
E3 VSS
E25 VSS
E29 VSS
E35 VSS

E40 VSS
F13 VSS
F15 VSS
F19 VSS
F29 VSS
F35 VSS
F40 VSS
F55 VSS
G6 VSS
G48 VSS
G51 VSS
G61 VSS
H4 VSS
H10 VSS
H14 VSS
H17 VSS
H21 VSS
H53 VSS
H58 VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9 VSS
A13 VSS

M11
M15

A17 VSS
A21 VSS
A25 VSS

M58
N1
N17

A28 VSS
A33 VSS
A37 VSS

N21
N25

A40 VSS
A45 VSS

N28
N33
N36

A49 VSS
A53 VSS
AA1 VSS

N40
N43
N47

AA8 VSS
AA13 VSS
AA50 VSS

N48
N51
N52

AA51 VSS
AA52 VSS
AA53 VSS

N56
N61

AA55 VSS
AA56 VSS

P9
P14
P16

AB16 VSS
AB18 VSS
AB21 VSS

P18
P21
P58

AB48 VSS
AB61 VSS
AC6 VSS

P59
R4
R17

AC10 VSS
AC14 VSS
AC46 VSS

R20
R46

AD4 VSS
AD17 VSS

T1
T47
T50

AD20 VSS
AD61 VSS
AE8 VSS

T51
T52
T53

AE13 VSS
AF1 VSS
AF17 VSS

T55
T56
U8

AF21 VSS
AF47 VSS
AF48 VSS

U13
V20

AF50 VSS
AF51 VSS

V61
W8
W13

AF52 VSS
AF53 VSS
AF55 VSS

W15
W18
W21

AF56 VSS
AF58 VSS
AF59 VSS

W46
Y4
Y47

AG7 VSS
AG10 VSS
AG14 VSS

Y58
Y59

AG18 VSS
AG47 VSS

J1 VSS
J49 VSS
J55 VSS

AG52 VSS
AG61 VSS
AH4 VSS

K8 VSS
K11 VSS
K21 VSS

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

K51 VSS
L16 VSS
L20 VSS
L22 VSS
L26 VSS
L30 VSS
L34 VSS
L38 VSS
L43 VSS
L48 VSS
L61 VSS
M4 VSS
M6 VSS

AH58 VSS
AJ7 VSS
AJ13 VSS

A5
A57
BC61
BD3

AJ16 VSS
AJ20 VSS
AJ22 VSS

BD59
BE4

AJ26 VSS
AJ30 VSS

BE58
BG5
BG57

AJ34 VSS
AJ38 VSS
AJ42 VSS

C3
C58
D59

AJ45 VSS
AJ48 VSS
AK1 VSS

E1
E61

AK52 VSS
AL10 VSS
AL13 VSS
AL17 VSS
AL21 VSS
AL25 VSS
AL28 VSS
AL33 VSS
AL36 VSS
AL40 VSS
AL43 VSS
AL47 VSS
AL61 VSS
AM4 VSS

AM13 VSS
AM20 VSS
AM22 VSS
AM26 VSS
AM30 VSS

U1000
BGA
(8 OF 9)
VSS

IVY-BRIDGE
2C-35W

CRITICAL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AM34
AM38
AM42
AM45
AM48
AM58

AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP7
AP10
AP51
AP55
AR7
AR13
AR17
AR21
AR41
AR48
AR61
AT4
AT14
AT19
AT36

AT45
AT52
AT58
AU1
AU7
AU11
AU28
AU32
AU51
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW7
AW13
AW43
AW61
AY4
AY9
AY14
AY19
AY30
AY36
AY41
AY45

AY49
AY55
AY58
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC5
BC13
BC57
BD8
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

PAGE TITLE

CPU GROUNDS

BD56
BE5
BG9

DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

14 OF 109

SHEET

13 OF 73

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

Processor Load Line : -2.9 mOhms

CPU VCORE DECOUPLING


Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

12 9 7

=PPVCORE_S0_CPU

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1

C1600

1UF

1UF

20%
2 6.3V
X5R
0201

C1601

1UF

20%
2 6.3V
X5R
0201

20%
2 6.3V
X5R
0201

CRITICAL CRITICAL

C1616

1UF

20%
6.3V
2 X5R
0201

C1602 1 C1603 1 C1604 1 C1605 1 C1606


1UF

1UF

20%
2 6.3V
X5R
0201

1UF

20%
2 6.3V
X5R
0201

1UF

20%
2 6.3V
X5R
0201

C1607

20%
6.3V
0201

2 X5R

1UF

20%
6.3V
0201

2 X5R

2 X5R

C1608

20%
6.3V
0201

2 X5R

1UF

C1609

20%
6.3V
0201

2 X5R

1UF

CRITICAL

C1610

20%
6.3V
0201

2 X5R

1UF

C1617
1UF

C1618 C1619 C1620 C1621 C1622


1

1UF

20%
2 6.3V
X5R
0201

1UF

20%
6.3V
2 X5R
0201

1UF

20%
2 6.3V
X5R
0201

1UF

20%
6.3V
2 X5R
0201

1UF

20%
2 6.3V
X5R
0201

C1623

1UF

20%
6.3V
2 X5R
0201

C1624
1UF

20%
6.3V
2 X5R
0201

20%
2 6.3V
X5R
0201

C1625
1UF

20%
2 6.3V
X5R
0201

20%
6.3V
0201

2 X5R

1UF

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL


1

CRITICAL

C1611

C1626
1UF

20%
6.3V
2 X5R
0201

20%
6.3V
0201

2 X5R

1UF

CRITICAL
1

CRITICAL CRITICAL

C1612

C1627

1UF

20%
6.3V
0201

2 X5R

1UF

20%
6.3V
0201

2 X5R

C1628

C1629 C1630

20%
6.3V
0201

2 X5R

1UF

20%
6.3V
2 X5R
0201

CRITICAL CRITICAL

C1640

20%
6.3V
0201

2 X5R

1UF

C1641

20%
6.3V
0201

2 X5R

1UF

C1642
1UF

20%
6.3V
0201

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

1UF

20%
6.3V
2 X5R
0201

C1615
1UF

CRITICAL CRITICAL

1UF

20%
2 6.3V
X5R
0201

1UF

CRITICAL

CRITICAL CRITICAL

C1613 1 C1614

C1631
1UF

20%
6.3V
2 X5R
0201

20%
2 6.3V
X5R
0201

C1632
1UF

20%
6.3V
2 X5R
0201

C1633
1UF

20%
6.3V
2 X5R
0201

C1634
1UF

20%
6.3V
2 X5R
0201

C1635

1UF

C1636

1UF

20%
6.3V
2 X5R
0201

C1637
1UF

20%
2 6.3V
X5R
0201

20%
6.3V
2 X5R
0201

C1638
1UF

20%
6.3V
2 X5R
0201

C1639
1UF
20%

2 6.3V
X5R

0201

PLACEMENT_NOTE (C1655-C1666):
Place close to U1000 on top side.

CRITICAL
1

CRITICAL

C1655

10UF

CRITICAL

C1656

10UF

20%
2 6.3V
CERM-X5R
0402-1

CRITICAL

C1657

10UF

20%
2 6.3V
CERM-X5R
0402-1

C1658
10UF

20%
2 6.3V
CERM-X5R
0402-1

CRITICAL
1

CRITICAL

C1659

10UF

20%
2 6.3V
CERM-X5R
0402-1

C1660
10UF

20%

20%

2 6.3V
CERM-X5R

0402-1

C1667
10UF

20%

2 6.3V
CERM-X5R

0402-1

CRITICAL

C1666
10UF

20%

2 6.3V
CERM-X5R

0402-1

CRITICAL

C1665
10UF

20%

2 6.3V
CERM-X5R

0402-1

CRITICAL

C1664
10UF

20%

2 6.3V
CERM-X5R

0402-1

CRITICAL

C1663
10UF

20%

2 6.3V
CERM-X5R

0402-1

CRITICAL

C1662
10UF

20%

2 6.3V
CERM-X5R

0402-1

CRITICAL

C1661
10UF

20%

2 6.3V
CERM-X5R

CRITICAL
1

2 6.3V
CERM-X5R

0402-1

0402-1

CRITICAL
1

C1668
10UF
20%

2 6.3V
CERM-X5R

0402-1

CRITICAL
1

C1669
10UF
20%

2 6.3V
CERM-X5R

0402-1

CRITICAL
1

C1670

10UF
20%

2 6.3V
CERM-X5R

0402-1

PLACEMENT_NOTE (C1667-C1679):

PLACEMENT_NOTE (C1640-C1645):

C1680

270UF

C1681

270UF

20%
2 2V
TANT
CASE-B2-SM

C1682

270UF

20%
2 2V
TANT
CASE-B2-SM

C1683
270UF

20%
2 2V
TANT
CASE-B2-SM

20%
2 2V
TANT
CASE-B2-SM

C1679
270UF

20%
TANT
CASE-B2-SM

2 2V

CPU VCCIO/VCCPQ DECOUPLING


CPU VCCPLL DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

PLACEMENT_NOTE (C1684-C167F):

PLACEMENT_NOTE (C1646-C1671):
12 10 9 7

=PP1V05_S0_CPU_VCCIO

Place on bottom side of U1000


U100.
Place near U1000 on top side

C1684

1UF

C1685

1UF

10%
2 10V
X5R
402

C1686

1UF

10%
2 10V
X5R
402

C1687

1UF

10%
2 10V
X5R
402

C1688

1UF

10%
2 10V
X5R
402

C1689

1UF

10%
2 10V
X5R
402

C1690

1UF

10%
2 10V
X5R
402

C1691

1UF

10%
2 10V
X5R
402

C1692

1UF

10%
2 10V
X5R
402

C1693

1UF

10%
2 10V
X5R
402

C1694

1UF

10%
2 10V
X5R
402

C1695

1UF

10%
2 10V
X5R
402

C1696
1UF

10%
2 10V
X5R
402

10%
2 10V
X5R
402

R1600
7

=PP1V8_S0_CPU_VCCPLL

5%
1/16W
MF-LF
402

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

C1697

1UF

C1698

1UF

10%
2 10V
X5R
402

C1699

1UF

10%
2 10V
X5R
402

C169A

1UF

10%
2 10V
X5R
402

C169B

1UF

10%
2 10V
X5R
402

C169C

1UF

10%
2 10V
X5R
402

C169D

1UF

10%
2 10V
X5R
402

C169E

1UF

10%
2 10V
X5R
402

C169F

1UF

10%
2 10V
X5R
402

C161A
1UF

10%
2 10V
X5R
402

10%
2 10V
X5R
402

C161B
1UF

10%
2 10V
X5R
402

C161C
1UF

10%
2 10V
X5R
402

=PP1V8_S0_CPU_VCCPLL_R

7 12

2
1

C160X
1UF

10%
2 10V
X5R
402

C160Y
1UF

10%
2 10V
X5R
402

C160Z

PLACE_NEAR=U1000.BC2:5mm

270UF

20%
2V
2 TANT
CASE-B2-SM

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

C161D
1UF

CPU VCCPLL Low pass filter

10%
2 10V
X5R
402

PLACEMENT_NOTE (C1672-C1681):
Place near U1000 on bottom side

C161E

10UF

C167D
270UF

C167E
270UF

C162A

10UF

20%
2 6.3V
CERM-X5R
0402-1

20%
2 2V
2
TANT
CASE-B2-SM

C161F
10UF

20%
2 6.3V
CERM-X5R
0402-1

C167G
270UF

20%
20%
2V
2 2V
TANT
TANT
CASE-B2-SM
CASE-B2-SM

C162B
10UF

20%
2 6.3V
CERM-X5R
0402-1

20%
2 6.3V
CERM-X5R
0402-1

C162C
10UF

20%
2 6.3V
CERM-X5R
0402-1

C162D
10UF

20%
2 6.3V
CERM-X5R
0402-1

C162E
10UF

20%
2 6.3V
CERM-X5R
0402-1

C167A
10UF

20%
2 6.3V
CERM-X5R
0402-1

C167B
10UF

20%
2 6.3V
CERM-X5R
0402-1

C167C
10UF

20%
2 6.3V
CERM-X5R
0402-1

C167H
270UF

20%
2 2V
TANT
CASE-B2-SM
SYNC_MASTER=J11_MLB

SYNC_DATE=10/03/2011

PAGE TITLE

CPU DECOUPLING-I

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

DRAWING NUMBER

R1601
0.0102

=PP1V05_S0_CPU_VCCPQE

1%
1/4W
MF
0603

Apple Inc.

7 12

NOTICE OF PROPRIETARY PROPERTY:

1UF

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Note:The smallest 10mOhm available in the library are 0805s

SIZE

2.8.0

C167F

10%
2 10V
X5R
402

051-9277

REVISION
BRANCH
PAGE

16 OF 109

SHEET

14 OF 73

VAXG DECOUPLING

Graphics Load Line : -3.9 mOhms

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)
12 9 7

PLACEMENT_NOTE (C1700-C1710):

=PPVCORE_S0_CPU_VCCAXG

Place on bottom side of U1000


U100.

CRITICAL

CRITICAL

C1700

C1701

1UF

1UF

10%
10V
X5R
402

CRITICAL
1

C1705

1UF

10%
10V
X5R
402

CRITICAL
1

C1704

1UF

10%
10V
X5R
402

CRITICAL
1

C1703

1UF

10%
10V
X5R
402

CRITICAL
1

C1702

1UF

10%
10V
X5R
402

CRITICAL
1

C1706
1UF

10%
10V
X5R
402

CRITICAL
1

CRITICAL
1

C1707
1UF

10%
10V
X5R
402

CRITICAL
1

C1708
1UF

10%
10V
X5R
402

C1709

CRITICAL
1

1UF

10%
10V
X5R
402

C1710
1UF

10%
10V
X5R
402

10%
10V
X5R
402

PLACEMENT_NOTE (C1711-C1716):

CRITICAL
1

CRITICAL
1

C1711
10UF

20%
6.3V

CERM-X5R

0402-1

CRITICAL
1

10UF

20%
6.3V

CERM-X5R

0402-1

C1715

10UF

20%
6.3V

CERM-X5R

0402-1

CRITICAL
1

C1714

10UF

20%
6.3V

CERM-X5R

CRITICAL
1

C1713

10UF

20%
6.3V

CRITICAL
1

C1712

CERM-X5R

0402-1

C1716
10UF

0402-1

20%
6.3V
CERM-X5R
0402-1

PLACEMENT_NOTE (C1717-C1722):

AXG_ACOUSTIC:NO

C1717

AXG_ACOUSTIC:NO
1

22UF

20%
6.3V
X5R-CERM1
0603

AXG_ACOUSTIC:NO

C1718

22UF

AXG_ACOUSTIC:NO

C1719

22UF

20%
6.3V
X5R-CERM1
0603

C1720

AXG_ACOUSTIC:NO
1

22UF

20%
6.3V
X5R-CERM1
0603

C1721

AXG_ACOUSTIC:NO
1

22UF

20%
6.3V
X5R-CERM1
0603

AXG_ACOUSTIC:YES

C1722

20%
6.3V
X5R-CERM1
0603

C1727

AXG_ACOUSTIC:YES

22UF

22UF

AXG_ACOUSTIC:YES

22UF

20%
4V

20%
6.3V
X5R-CERM1
0603

C1728

22UF

20%
4V

2 X5R

20%
4V

2 X5R

402

C1729

C1730
22UF
20%
4V

2 X5R

402

AXG_ACOUSTIC:YES

2 X5R

402

402

AXG_ACOUSTIC:YES

C1731
22UF
20%
4V

2 X5R
402

AXG_ACOUSTIC:YES

C1732
22UF
20%
4V

2 X5R
402

PLACEMENT_NOTE (C1723-C1724):

C1723
270UF

C1724
270UF

20%

20%

2 2V

TANT
CASE-B2-SM

C1725

270UF
20%

2 2V

TANT
CASE-B2-SM

2 2V

TANT
CASE-B2-SM

CPU VDDQ/VCCDQ DECOUPLING


Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF
PLACEMENT_NOTE (C1738-C1747):
26 12 10 7

=PP1V5_S3_CPU_VCCDDR
Place on bottom side of U1000
U100.

C1738

CPU VCCSA DECOUPLING


1

C1739

C1740

C1741

C1742

C1743

C1744

C1745

C1746

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

C1747

1UF

PLACEMENT_NOTE (C1758-C1762):

12 7

=PPVCCSA_S0_CPU

Place on bottom side of U1000


U100.

Place close to U1000 on bottom side

C1748

C1751

C1752

C1753

1 C1754

C1755

10UF

10UF

10UF

10UF

10UF

10UF

10UF

20%
6.3V

20%
6.3V

20%
6.3V

20%
6.3V

20%
6.3V

20%
6.3V

20%
6.3V

20%
6.3V

CERM-X5R
0402-1

1 C1750

C1749

10UF

CERM-X5R
0402-1

CERM-X5R
0402-1

CERM-X5R
0402-1

CERM-X5R
0402-1

CERM-X5R
0402-1

CERM-X5R
0402-1

CERM-X5R

C1756
20%
2V
TANT
CASE-B2-SM

C1759

C1760
1UF

1UF

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

C1761

1UF

10%
10V
X5R
402

C1763

R1702

C1764

C1765

C1762
1UF

10UF

10UF

10UF

20%
6.3V

20%
6.3V

20%
6.3V

20%
6.3V

CERM-X5R

CERM-X5R
0402-1

CERM-X5R
0402-1

C1766

10UF

0402-1

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

10%
10V
X5R
402

C1767
10UF

CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

C1768
270UF

0.010
1

1UF

0402-1

270UF

C1758

=PP1V5_S3_CPU_VCCDQ

7 12

1%

20%
2V
TANT
CASE-B2-SM

1/4W
MF

0603

C1757
1UF
10%
10V

X5R
402

SYNC_MASTER=K21_MLB

SYNC_DATE=07/29/2011

PAGE TITLE

CPU DECOUPLING-II
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

17 OF 109

SHEET

15 OF 73

OMIT_TABLE

U1800

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

RTC_RESET_L

F19 RTCRST*

16

PCH_SRTCRST_L

A23 SRTCRST*

16

PCH_INTRUDER_L

K22 INTRUDER*

16

PCH_INTVRMEN_L

C21 INTVRMEN

HDA_BIT_CLK_R

H35 HDA_BCLK

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_FRAME_R_L

(IPU) LDRQ0* H40


LDRQ1*/GPIO23 F37
(IPU)

69 16

N1 SPKR
(IPD-PLTRST#)

PCH_SPKR

IHDA

16

H37 HDA_SYNC
(IPD-BOOT)

HDA_SYNC_R

F35 HDA_RST*

HDA_RST_R_L

IN

16

IN

16

=PP3V3_S0_PCH

16
16

R1820
10K

OUT

5%
1/20W
MF
2 201

25

LPC_SERIRQ

BI

OUT

OUT

7 22

69 37 6

IN

69 37 6

IN

69 37

OUT

69 37

OUT

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AN3
AN1
AU3
AU1

SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AN6
AN8
AR3
AR1

SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P

PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P

BJ33
BL33
BB30
AY30

PERN1
PERP1
PETN1
PETP1

PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P

BJ35
BL35
BB33
AY33

PERN2
PERP2
PETN2
PETP2

PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P

BH36
BK36
BF33
BD33

PERN3
PERP3
PETN3
PETP3

PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P

BJ37
BL37
BD35
BF35

PERN4
PERP4
PETN4
PETP4

BJ39
BL39
AY35
BB35

IN

IN

38 68

IN

IN

38 68

OUT

OUT

38 68

OUT

OUT

38 68
8

IN

IN

IN

IN

OUT

OUT

OUT

OUT

PERN5
PERP5
PETN5
PETP5

NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP

BH40
BK40
BD37
BF37

PERN6
PERP6
PETN6
PETP6

NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP

BJ41
BL41
AY37
BB37

PERN7
PERP7
PETN7
PETP7

BJ43
BL43
AY40
BB40

PERN8
PERP8
PETN8
PETP8

8
69 40 6

IN
6
6
6

D36
B36
C35
A35

HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

(IPD)
(IPD)
(IPD)
(IPD)

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AD4
AD2
AL3
AL1

TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP

8
8
8

34 16
16

OUT
IN

HDA_SDOUT_R

K37 HDA_SDO (IPD-BOOT)

JTAG_ISP_TMS
ENET_MEDIA_SENSE_RDIV

K35 HDA_DOCK_EN*/GPIO33
M35 HDA_DOCK_RST*/GPIO13

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA

69 25 16

AD8
AD6
AG3
AG1

TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP

69 23

69 23

IN
IN
OUT

M17 JTAG_TCK (IPD)

XDP_PCH_TCK

M15 JTAG_TMS (IPU)

XDP_PCH_TMS

U12 JTAG_TDI (IPU)

XDP_PCH_TDI

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

M12 JTAG_TDO

XDP_PCH_TDO

AD12 SPI_CLK

69 43

OUT

SPI_CLK_R

69 43

OUT

SPI_CS0_R_L

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

JTAG

69 23

IN

AB8 SPI_CS0*

SATA3RCOMPO AF10
SATA3COMPI AF12
SATA3RBIAS AH4

AB6 SPI_CS1*

TP_SPI_CS1_L

TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP

AC3
AC1
AJ3
AJ1

SATAICOMPO AB10
SATAICOMPI AB12

SPI

69 23

6
6

=PP1V05_S0_PCH_VCCIO_SATA

7 22
8

PLACE_NEAR=U1800.AB10:2.54mm

TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
68

NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP

6
6

R1830
37.4

1%
1/20W
MF
201

8
8
8

=PP1V05_S0_PCH

NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP

SPI_MOSI_R

W8 SPI_MOSI (IPD-BOOT)

IN

SPI_MISO

Y2 SPI_MISO (IPU)

SATALED* W10

PCH_SATAICOMP

R1831

1%
1/20W
MF
2 201

SATA0GP/GPIO21 M2
(IPU) SATA1GP/GPIO19 R1

R1800

16

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
XDP_DC3_PCH_GPIO19_SATARDRVR_EN

OUT

23

R1832

OUT

8 23

1%
1/20W
MF
2 201

330K
5%
1/20W
MF
201

R1801
1M

5%
1/20W
MF
201

16

RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L

C1802

1.0UF

16
16

16
16

16

C1803

69 16

69 16

20%

69 16

2 6.3V
X5R

0201-MUR

69 25 16

33
HDA_BIT_CLK_R
R1810
PLACE_NEAR=U1800.H35:1.27mm
33
HDA_SYNC_R
R1811
PLACE_NEAR=U1800.H37:1.27mm
33
HDA_RST_R_L
R1812
PLACE_NEAR=U1800.F35:1.27mm
33
HDA_SDOUT_R
R1813
PLACE_NEAR=U1800.K37:1.27mm

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L

OUT

6 41 43 69

HDA_BIT_CLK

OUT

6 40 69

HDA_SYNC

OUT

6 40 69

HDA_RST_L

OUT

6 40 69

OUT

6 40 69

BI

6 41 43 69

BI

6 41 43 69

BI

6 41 43 69

BI

6 41 43 69

5%

1/20W

MF

201

HDA_SDOUT

7 17 18 19 25 36

R1834
R1833

R1842
R1869
R1844
R1845
R1847
R1814
R1815
R1843

10K
10K
10K
10K
10K
10K
10K
10K
10K
10K

R1846
R1848
R1853
R1854
R1855

10K
10K
10K
10K
10K

R1879

10K

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

PCH_SPKR
PCH_SATALED_L

ITPCPU_CLK100M_N

FW_CLKREQ_L
AP_CLKREQ_L
EXCARD_CLKREQ_L
JTAG_DPMUXUC_TRST_L
ENET_CLKREQ_L
PEG_CLKREQ_L
TBT_CLKREQ_L
SSD_CLKREQ_L
PEGCLKRQA_L_GPIO47
PEGCLKRQB_L_GPIO56
SMBUS_PCH_ALERT_L
USB_EXTB_SEL_XHCI
USB_EXTD_SEL_XHCI
ENET_MEDIA_SENSE_RDIV

16

ITPCPU_CLK100M_P

PEGCLKRQA_L_GPIO47
TP_PCIE_CLK100M_PEGAN
TP_PCIE_CLK100M_PEGAP

16

CLKOUT_DMI_N BB24
CLKOUT_DMI_P AY24

DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P

CLKOUT_DP_N AN10
CLKOUT_DP_P AN12

TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP

OUT

OUT

CLKIN_DMI_N BD17
CLKIN_DMI_P BF17

PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P

IN

16 68

IN

16 68

OUT

10 66

OUT

10 66

IN

16 68

IN

16 68

IN

PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
EXCARD_CLKREQ_L

AA49 CLKOUT_PCIE3N
AA51 CLKOUT_PCIE3P
B8 PCIECLKRQ3*/GPIO25

OUT

TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
JTAG_DPMUXUC_TRST_L

IN
OUT

OUT

66 38 6

OUT

66 38 6

OUT
IN

CLKIN_DOT_96N M24
CLKIN_DOT_96P K24

CLKIN_SATA_N AK8
CLKIN_SATA_P AK6

REFCLK14IN J49

CLKIN_PCILOOPBACK E51
Y48 CLKOUT_PCIE4N
Y50 CLKOUT_PCIE4P
M19 PCIECLKRQ4*/GPIO26

16

XTAL25_IN W49
XTAL25_OUT W51

OUT

69 8

OUT

16

IN

NO STUFF

69 34

OUT

R1840

69 34

OUT

36 16

IN

5%
1/20W
MF
201

66 23
66 23

IN

25 69

16 69

=PP1V05_S0_PCH_VCCDIFFCLK

B
90.9
1%
1/20W
MF
201

AR12 CLKOUT_ITPXDP_N
AR10 CLKOUT_ITPXDP_P

ITPXDP_CLK100M_N
ITPXDP_CLK100M_P

PCH_CLK33M_PCIIN

R1890 1

W44 CLKOUT_PCIE7N
W46 CLKOUT_PCIE7P
H4 PCIECLKRQ7*/GPIO46
(IPU-RSMRST#)

PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P
TBT_CLKREQ_L

16 68

22 20 7

AB44 CLKOUT_PCIE6N
AB46 CLKOUT_PCIE6P
J3 PCIECLKRQ6*/GPIO45

PEG_CLK100M_N
PEG_CLK100M_P
PEG_CLKREQ_L

IN

SYSCLK_CLK25M_SB_R

PLACE_NEAR=U1800.AC49:2.54mm
PCH_XCLK_RCOMP

XCLK_RCOMP AC49
69 8

PCH_CLK14P3M_REFCLK

NC

AF40 CLKOUT_PEG_B_N
AF42 CLKOUT_PEG_B_P
C4 PEG_B_CLKRQ*/GPIO56

TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
PEGCLKRQB_L_GPIO56

16

DOES THIS NEED LENGTH MATCH???

AB40 CLKOUT_PCIE5N
AB42 CLKOUT_PCIE5P
K8 PCIECLKRQ5*/GPIO44
(IPU-RSMRST#)

PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
ENET_CLKREQ_L

16

CLKOUTFLEX0/GPIO64 H50
(IPD-PWROK)

TP_PCH_GPIO64_CLKOUTFLEX0

CLKOUTFLEX1/GPIO65 D48
(IPD-PWROK)

TP_PCH_GPIO65_CLKOUTFLEX1

CLKOUTFLEX2/GPIO66 G49
(IPD-PWROK)

TP_PCH_GPIO66_CLKOUTFLEX2

CLKOUTFLEX3/GPIO67 J51
(IPD-PWROK)

TP_PCH_GPIO67_CLKOUTFLEX3

5%
1/20W
MF
201

23 25
8

16
69 25

IN

16 37

SYSCLK_CLK25M_SB

201
1%

16

16
68 16
16
68 16

PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N

R1891
R1892

10K
10K

1
1

68 16
68 16

PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N

R1893
R1894

10K
10K

PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N

R1895
R1896

10K
10K

16
16

68 16

16

68 16

16 24
68 16

PCH_CLK14P3M_REFCLK

R1897

10K

PCH_CLKIN_GNDP1
PCH_CLKIN_GNDN1

R1870
R1871

10K
10K

16

16

16
16

SYSCLK_CLK25M_SB_R

MF
6041/20W

16 69

1.8V -> 1.1V


R1886
1K

16 36
6 16 38

R1885

PLACE_NEAR=U1800.W49:5.1mm

Unused clock terminations for FCIM Mode

16

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.


Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.

PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P

16

R1841

16

66 10

DP_AUXCH_ISOL
SATARDRVR_EN

AD40 CLKOUT_PCIE2N
AD42 CLKOUT_PCIE2P
T4 PCIECLKRQ2*/GPIO20

OUT

NO STUFF
4.7K
10K

PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
AP_CLKREQ_L

OUT

7 17 18 19

66 10

R1877
R1878

44 69

16 68

16

1.0UF

20%

6.3V
X5R
0201-MUR

=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO

16

33
33
33
33
33

44 69

16 68

69 37 6

16

R1860
R1861
R1862
R1863
R1864

OUT
BI

TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L

PEG_A_CLKRQ*/GPIO47 R8
CLKOUT_PEG_A_N AF44
CLKOUT_PEG_A_P AF46

16

IN

69 37 6

37 16

20K

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_FRAME_R_L

(IPU/IPD) CL_CLK1 L3
(IPU/IPD) CL_DATA1 J1
CL_RST1* M8

OUT

IN

R1803
16

44 69

BI

PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P

16

5%
1/20W
MF
2 201

16 24
44 69

AE49 CLKOUT_PCIE1N
AE51 CLKOUT_PCIE1P
U8 PCIECLKRQ1*/GPIO18

IN

44 69

OUT

PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
FW_CLKREQ_L

OUT

20 17 7

5%
1/20W
MF
201 2

44 69

OUT

PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1

16

20K

USB_EXTD_SEL_XHCI
SML_PCH_1_CLK
SML_PCH_1_DATA

BI

AD48 CLKOUT_PCIE0N
CLKIN_GND1_N BB26
Controlled by PCIECLKRQ5#
AD50 CLKOUT_PCIE0P
CLKIN_GND1_P AY26
M4 PCIECLKRQ0*/GPIO73

OUT

PLACE_NEAR=U1800.AF12:2.54mm

PCH_SATA3COMP
PCH_SATA3RBIAS

=PPVRTC_G3_PCH

R1802 1

SML1ALERT*/PCHHOT*/GPIO74 C9
SML1CLK/GPIO58 D12
SML1DATA/GPIO75 C11

OUT

PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
SSD_CLKREQ_L

38 16 6

750

69 43

USB_EXTB_SEL_XHCI
SML_PCH_0_CLK
SML_PCH_0_DATA

16

7 22

49.9

PCH_SATALED_L

SML0ALERT*/GPIO60 H22
SML0CLK K12
SML0DATA A9

FLEX
CLOCKS

OUT

SMBUS_PCH_ALERT_L
SMBUS_PCH_CLK
SMBUS_PCH_DATA

PLACE_NEAR=U1800.AH4:2.54mm
69 43

SMBALERT*/GPIO11 H12
SMBCLK F17
SMBDATA F10

BGA
QP8D-MM915462
(2 OF 10)

6
8

AE3
AE1
AH8
AH6

U1800

PCH-PPT-MB-SFF-ES1

6 41 43
8

VSel strap not functional (VCCVRM = 1.8V)


69 16

TP_LPC_DREQ0_L
TBT_PWR_EN_PCH

SERIRQ Y4

69 16

16

SMBUS

16

A37
A39
C39
C37
K40

PCI-E*
C-LINK

NC

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
(IPU)
FWH4/LFRAME*

CLOCKS

IN

BGA
QP8D-MM915462
(1 OF 10)

A19 RTCX1
C19 RTCX2

SYSCLK_CLK32K_RTC

RTC
LPC

69 25

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

1%
1/20W
MF
2 201

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

PAGE TITLE

PCH SATA/PCIe/CLK/LPC/SPI
DRAWING NUMBER

Apple Inc.

051-9277

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

5%

SIZE

REVISION
BRANCH
PAGE

18 OF 109

SHEET

16 OF 73

=PP3V3_SUS_PCH_GPIO
=PP1V05_S0_PCH_VCCIO_PCIE

7 16 17 18 19
7

PLACE_NEAR=U1800.BF19:12.7mm
49.9

OMIT_TABLE

1%
1/20W
MF
2 201

OMIT_TABLE

U1800

U1800

PCH-PPT-MB-SFF-ES1
66 9

IN

66 9

IN

66 9

IN

66 9

IN

66 9

IN

66 9

IN

66 9

66 9
66 9

OUT
OUT
OUT

66 9

OUT

66 9

OUT

66 9

BF22
AY22
AY19
AY17

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

OUT

66 9

BD22
BB22
BB19
BB17

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

OUT

66 9

BJ21
BJ23
BL19
BJ17

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

IN

66 9

BL21
BL23
BJ19
BL17

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

IN

66 9

OUT

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

BGA
QP8D-MM915462
(3 OF 10)

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

BK20 DMI2RBIAS

PCH_DMI2RBIAS

BL13
BJ15
BD12
BJ11
AY15
AY12
BJ9
BF10
BJ13
BL15
BF12
BL11
BB15
BB12
BL9
BD10

FDI_INT BB10

BF19 DMI_ZCOMP
BD19 DMI_IRCOMP

PCH_DMI_COMP

PCH-PPT-MB-SFF-ES1

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

IN

9 66

FDI_INT

OUT

9 66

FDI_FSYNC0 BH12
FDI_FSYNC1 BK8

FDI_FSYNC<0>
FDI_FSYNC<1>

OUT

9 66

OUT

9 66

FDI_LSYNC0 BK12
FDI_LSYNC1 BH8

FDI_LSYNC<0>
FDI_LSYNC<1>

OUT

9 66

OUT

9 66

750

1%
1/20W
MF
2 201

PCH_SUSACK_L

17

41 25

41 25 23

25

25

66 26 10

62

L1 SYS_RESET*

PM_SYSRST_L

IN

M10 SYS_PWROK

PM_PCH_SYS_PWROK

IN

M22 PWROK

IN

PM_PCH_PWROK

IN

PM_PCH_APWROK

DSWVRMEN F22
DPWROK A21

OUT

PM_MEM_PWRGD

IN

PM_RSMRST_L

IN

PM_PWRBTN_L

62 42 41

IN

SMC_ADAPTER_EN

IN

CLKRUN*/GPIO32 T2

PM_CLKRUN_L

BI

PCH_RI_L

OUT

LVDS_IG_BKL_PWM

L49 L_BKLTCTL

=PPVRTC_G3_PCH

7 16 20

R1915
390K

5%
1/20W
MF
2 201

6 17 37

SUS_STAT*/GPIO61 G6

LPC_PWRDWN_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L

6 17 41 43

L51 L_DDC_CLK
K46 L_DDC_DATA
(IPD-PLTRST#)

NC
NC

R42 L_CTRL_CLK
M40 L_CTRL_DATA

NC
NC

AH42 LVD_IBG
AH40 LVD_VBG

NC
NC

AG51 LVD_VREFH
AG49 LVD_VREFL

NC
NC

AK44 LVDSA_CLK*
AK46 LVDSA_CLK

NC
NC
NC
NC

AR46
AN49
AN44
AK40

NC
NC
NC
NC

AR44
AN51
AN46
AK42

LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

41

AH46 LVDSB_CLK*
AH44 LVDSB_CLK

R1909

OUT

6 25 41 43

OUT

42 69

OUT

17 41 62

OUT

17 26 37 41 49 62

OUT

17 26 41 62

5%
1/20W
MF
2 201

BGA
SDVO_TVCLKINN AU40
QP8D-MM915462
(IPD)
SDVO_TVCLKINP AU42
(4 OF 10)
(IPD)

NC
NC

100K

SLP_S5*/GPIO63 F6
B20 RSMRST*
SLP_S4* K10
SLP_S3* D4
C13 SUSWARN*/SUSPWRDNACK/GPIO30
SLP_A* C7
K19 PWRBTN* (IPU)
SLP_SUS* A15
H19 ACPRESENT/GPIO31
(IPD-DeepS4/S5)
PMSYNCH BB8
H10 BATLOW*/GPIO72 (IPU)
SLP_LAN*/GPIO29 A7
F12 RI*

PM_BATLOW_L

IN

M44 L_BKLTEN
M42 L_VDD_EN

5%
1/20W
MF
201 2

IN

PCIE_WAKE_L

B12 DRAMPWROK

41 23 17

100K

PM_DSW_PWRGD

G3 APWROK

PCH_SUSWARN_L

R1955

PCH_DSWVRMEN

WAKE* D8

SUSCLK/GPIO62 D3

17

42

F15 SUSACK* (IPU)

SYSTEM POWER
MANAGEMENT

R1920

OUT

LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR

OUT

PLACE_NEAR=U1800.BK20:2.54mm
1

NC
NC
NC
NC

AM50
AL49
AJ51
AH50

LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*

NC
NC
NC
NC

AM48
AL51
AJ49
AH48

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

PM_SLP_SUS_L

OUT

17 62

OUT

10 66

6
6

PM_SYNC

MEM_VDD_SEL_1V5_L

OUT

17 56

6
6

TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED

M46 CRT_BLUE
R46 CRT_GREEN
U46 CRT_RED

TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA

R49 CRT_DDC_CLK
N49 CRT_DDC_DATA

TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC

M50 CRT_HSYNC
N51 CRT_VSYNC

PCH_DAC_IREF

R51 DAC_IREF
T48 CRT_IRTN

PLACE_NEAR=U1800.R51:2.54mm
1

6
6

8
8

8
8
8

TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>

DDPC_CTRLCLK T50
DDPC_CTRLDATA U44
(IPD-PLTRST#)

8
8
8
8
8
8
8
8

DPB_IG_DDC_CLK
DPB_IG_DDC_DATA

DDPC_AUXN AU51
DDPC_AUXP AU49
DDPC_HPD BE46

8
8

DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_HPD

BC49
BC51
BD48
BD50
BF46
BF45
BE49
BE51

8
8
8
8
8
8
8
8

TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA

DDPD_AUXN AU46
DDPD_AUXP AU44
DDPD_HPD BK44

8
8

TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD

BG51
BG49
BF42
BD42
BJ47
BL47
BL45
BJ45

TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>

DDPD_CTRLCLK M48
DDPD_CTRLDATA U42
(IPD-PLTRST#)

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

DPA_IG_AUX_CH_N
DPA_IG_AUX_CH_P
DPA_IG_HPD

AY48
AY50
AY44
AY46
BB44
BB46
BA49
BA51

DPA_IG_DDC_CLK
DPA_IG_DDC_DATA

DDPB_AUXN AW51
DDPB_AUXP AW49
DDPB_HPD AY42

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

TP_SDVO_INTN
TP_SDVO_INTP

SDVO_CTRLCLK W42
SDVO_CTRLDATA R44
(IPD-PLTRST#)

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

TP_SDVO_STALLN
TP_SDVO_STALLP

SDVO_INTN AT50
(IPD)
SDVO_INTP AT48
(IPD)

TP_PM_SLP_A_L
6

TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP

SDVO_STALLN AR51
(IPD)
SDVO_STALLP AR49
(IPD)

LVDS
DIGITAL DISPLAY INTERFACE

10K

5%
1/20W
MF
201 2

R1900

CRT

DMI
FDI

R1905 1

TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>

R1951
1K

5%
1/20W
MF
2 201

19 18 17 16 7

=PP3V3_SUS_PCH_GPIO

R1983 1
10K

5%
1/20W
MF
201

PCH_SUSWARN_L

17

R1986
2

PCH_SUSACK_L

17

5%
1/20W
MF
201

=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH

7 16 17 18 19
7 16 18 19 25 36
7

R1985

1K

R1991

8.2K

R1982

10K

R1925

1K

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

R1924
R1921
R1922
R1923

100K
100K
100K
100K

2
2

1
1

1/20W

MF

PM_PWRBTN_L

17 23 41

PM_CLKRUN_L

6 17 41 43

MEM_VDD_SEL_1V5_L

17 56

PCIE_WAKE_L

6 17 37

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

SYNC_MASTER=J30_MLB

SYNC_DATE=07/27/2011

PAGE TITLE

PCH DMI/FDI/PM/Graphics
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_SLP_SUS_L

DRAWING NUMBER
17 26 41 62

Apple Inc.

17 26 37 41 49 62

17 62

NOTICE OF PROPRIETARY PROPERTY:

SIZE

2.8.0

17 41 62

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-9277

REVISION
BRANCH
PAGE

19 OF 109

SHEET

17 OF 73

OMIT_TABLE

TP_PCH_TP23

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

BH24
BK24
BH20
BK16
BH16
AN42
AN40
AR40
AR42
D20
M30
E3
AM4
AT4
AT2
AD10
B24
D24
AD44
AD46
BJ48
BL7
W40
K30

U1800

TP1
TP2 PCH-PPT-MB-SFF-ES1
BGA
TP3
QP8D-MM915462
TP4
(5 OF 10)
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
RSVD
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24

IN

68 40

IN

IN

IN

68 39

IN

68 40

IN

IN

IN

68 39

OUT

68 40

OUT

OUT

OUT

68 39

OUT

68 40

OUT

OUT

OUT

10K
10K
10K
10K

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

18

OUT

18

OUT

18

OUT

B
NO STUFF

R2054

10K

1
5%

1/20W

MF

18

IN

40 18 6

IN

34 18

IN

40 18 6

IN

26 25

R2030

10K
10K
10K
10K

2
2

5%

10K

R2069

10K

R2060
R2061
R2062
R2068

10K
10K
10K
10K

R2067

10K

1/20W

MF

201

1/20W

MF

201

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

USB3_EXTA_TX_N
USB3_EXTB_TX_N
USB3_EXTC_TX_N
USB3_EXTD_TX_N

BF26
BB28
BF28
BF30

USB3TN1
USB3TN2
USB3TN3
USB3TN4

USB3_EXTA_TX_P
USB3_EXTB_TX_P
USB3_EXTC_TX_P
USB3_EXTD_TX_P

BD26
AY28
BD28
BD30

USB3TP1
USB3TP2
USB3TP3
USB3TP4

PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L

D49
C48
C47
C45

JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
PCH_GPIO54

G46 REQ1*/GPIO50
K44 REQ2*/GPIO52
F46 REQ3*/GPIO54

PIRQA*
PIRQB*
PIRQC*
PIRQD*

OUT

69 25

OUT

18
6
18
69 25
18

USBP1N C25
USBP1P A25

USB_EXTB_XHCI_N
USB_EXTB_XHCI_P

BI

24 68

BI

24 68

USBP2N C27
USBP2P A27

USB_EXTC_N
USB_EXTC_P

BI

BI

USBP3N H28
USBP3P F28

USB_EXTD_XHCI_N
USB_EXTD_XHCI_P

BI

24 68

BI

24 68

USBP4N M26
USBP4P K26

TP_USB_4N
TP_USB_4P
TP_USB_SDN

USBP5N D28
USBP5P B28
USBP6N H26
USBP6P F26

TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
PCH_STRP_TOPBLK_SWP_L

F42 GNT1*/GPIO51
H42 GNT2*/GPIO53
D44 GNT3*/GPIO55
(IPU-PCIERST#)

BLC_GPIO
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L

A47
C41
F45
F40

PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5

USB_EXTA_N
USB_EXTA_P

TP_PCI_PME_L

H2 PME* (IPU)

PLT_RESET_L

F7 PLTRSTB*

OUT

G51
E49
H48
J43
G45

LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
(IPD)

BI

39 68

BI

39 68

Ext A (XHCI/EHCI)
Ext B (XHCI)

Ext D (XHCI) (Mobiles: Trackpad?)


Unused
RSVD: SD

TP_USB_SDP
TP_USB_WLANN

RSVD: WiFi

TP_USB_WLANP

USBP7N D32
USBP7P B32

USB_HUB_UP_N
USB_HUB_UP_P

BI

24 68

BI

24 68

USBP8N M28
USBP8P K28

USB_CAMERA_N
USB_CAMERA_P

BI

6 40 68

BI

6 40 68

USBP9N C29
USBP9P A29

USB_EXTB_EHCI_N
USB_EXTB_EHCI_P

BI

24 68

BI

24 68

USBP10N C31
USBP10P A31

USB_EXTD_EHCI_N
USB_EXTD_EHCI_P

USBP11N H33
USBP11P F33

TP_USB_BT_HSN
TP_USB_BT_HSP

RSVD: BT (HS)

USBP12N H30
USBP12P F30

TP_USB_12N
TP_USB_12P

Unused

USBP13N M33
USBP13P K33
(IPD)

TP_USB_13N
TP_USB_13P

Unused

OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14

C17
A17
A13
D16
A11
B16
C23
H15

Ext C (XHCI/EHCI)

BI

BI

68

USB Hub (All LS/FS Devices)


Camera

Ext B (EHCI)

Ext D (EHCI)

PCH_USB_RBIAS

PLACE_NEAR=U1800.A33:2.54mm
1

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

R2070
22.6

IN

18 23

IN

18 23

IN

18 23

IN

18 23

IN

23

IN

23

OUT
IN

1%
1/20W
MF
2 201

23
18 23

18

AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L

6 18 40
18 34

Redundant to pull-up on audio page


AUD_I2C_INT_L
5%

1/20W

MF

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

SYNC_MASTER=J13_MLB_NON_POR

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

1/20W

MF

PCH PCI/USB/TP/RSVD
DRAWING NUMBER

18 23

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
AP_PWR_EN

Apple Inc.

18 23
18 23

051-9277

18 23

NOTICE OF PROPRIETARY PROPERTY:

18 23

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

23 37 62

SIZE

REVISION

2.8.0

201

SYNC_DATE=11/10/2011

PAGE TITLE

6 18 40

201

2
2

JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
PCH_GPIO54
BLC_GPIO

5%

USB3RP1
USB3RP2
USB3RP3
USB3RP4

Redundant to pull-up on audio page

201

5%

NO
STUFF2
1
1

MF

1/20W

5%

NO STUFF

R2033

OUT

69 25
7 16 17 18 19 25 36

5%

10K
10K

BL25
BL27
BL31
BL29

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

USBP0N F24
USBP0P H24

USBRBIAS* C33
USBRBIAS A33

7 25

NO STUFF

R2014
R2031

USB3_EXTA_RX_P
USB3_EXTB_RX_P
USB3_EXTC_RX_P
USB3_EXTD_RX_P

7 16 17 19

USB3RN1
USB3RN2
USB3RN3
USB3RN4

201

R2016
R2017
R2018

BJ25
BJ27
BJ31
BJ29

=PP3V3_S0_PCH_GPIO

R2010
R2011
R2012
R2013

=PP3V3_SUS_PCH_GPIO
=PP3V3_S3_PCH_GPIO
=PP3V3_S0_PCH_GPIO

USB3_EXTA_RX_N
USB3_EXTB_RX_N
USB3_EXTC_RX_N
USB3_EXTD_RX_N

PCI

36 25 19 18 17 16 7

68 39

USB

BH49 TP41
BB42 TP42

AU6
AU8
AW1
AW3
AY2
AY4
AY6
AY8
BA1
BA3
BB6
BC1
BC3
BD2
BD4
BE1
BE3
BE6
BF6
BF7
BG1
BG3
BH3
BH4
BJ4
BJ5
BJ7
BK6
BL5

BRANCH
PAGE

20 OF 109

SHEET

18 OF 73

1
TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

TABLE_BOMGROUP_ITEM

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.

36 25 19 18 17 16 7

RAMCFG3:H

RAMCFG2:H

R2172 1
5%
1/20W
MF
201

U1800

PCH-PPT-MB-SFF-ES1

(TBT_CIO_PLUG_EVENT_ISOL)

19

IN

41 19

IN

19

OUT

23

IN

23

OUT

43 19 6

BI

19

OUT
34 19

41 19
23
36

OUT

TBT_SW_RESET_L

R2180

IN
OUT

19

5%
MF

1/20W
201 23

23 19

OUT

23

OUT

19 8

IN

OUT

19

OUT

23 8
50 43 19 6

OUT
BI

OUT

BGA
BMBUSY*/GPIO0
QP8D-MM915462
GPIO1
(6 OF 10)
GPIO6
GPIO7
GPIO8 (IPU-RSMRST#)
LAN_PHY_PWR_CTRL/GPIO12
GPIO15 (IPU)
SATA4GP/GPIO16
GPIO17
SCLOCK/GPIO22
GPIO24
GPIO27 (IPU-DeepS4/S5)
GPIO28 (IPU-RSMRST#)
STP_PCI*/GPIO34
GPIO35
SATA2GP/GPIO36
(IPD-PLTRST#)
SATA3GP/GPIO37
(IPD-PLTRST#)
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SATA5GP/GPIO49
GPIO57

W1
B40
C43
A45
H17
C5
K6
AA3
B44
W3
K15
C15
G1
R3
W12
W6
M6
N3
U10
U1
AA1
K17

XDP_FC1_PCH_GPIO0
FW_PME_L
DPMUX_UC_IRQ
SMC_RUNTIME_SCI_L
TP_PCH_GPIO8
WOL_EN
XDP_FC0_PCH_GPIO15
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
LPCPLUS_GPIO
ODD_PWR_EN_L
TBT_GO2SX_BIDIR
SMC_WAKE_SCI_L
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
TBT_SW_RESET_R_L

XDP_DC1_PCH_GPIO35_MXM_GOOD

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
JTAG_ISP_TDO
JTAG_ISP_TDI
FW_PWR_EN_PCH
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
SPIROM_USE_MLB

GPIO68
GPIO69
GPIO70
GPIO71

A4
A5
A48
A49
A51
BH1
BH51
BJ1
BJ3
BJ49
BJ51
BL1
BL3
BL4

K42
A43
D40
A41

8
8
8

RAMCFG1:H

10K

RAMCFG0:H

R2174 1

R2173

10K

5%
1/20W
MF
201

5%
1/20W
MF
201

R2175
10K

5%
1/20W
MF
201

MLB_RAMCFG3
MLB_RAMCFG2
MLB_RAMCFG1
MLB_RAMCFG0

PCH_A20GATE

19

NO STUFF
(IPD)

PECI AU12

R2170

PCH_PECI

43

CPU_PECI

2
5%
MF

RCIN* U6

PCH_RCIN_L

PROCPWRGD AU10

R2140

R2156

PM_THRMTRIP_L_R

390

PM_THRMTRIP_L

IN

1/20W
201

10 42 66

R2178

(IPU)

PCH_DF_TVS

(IPD-PLTRST#?)

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

VSS_NCTF

1K

5%
1/20W
MF
201

AK10
AH12
AK12
AH10

R2179
2.2K

PCH_INIT3V3_L

DF_TVS BC7

7 20 22

10 23 66

OUT

1/20W
201

5%
MF

INIT3_3V* R6

10 42 66

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PWRGD

2
5%
MF

42

BI

1/20W
201

19

PCH_PROCPWRGD

THRMTRIP* BC9

NC_1 U40

VSS_NCTF

A20GATE U3

GPIO
CPU/MISC

IN

NCTF

23 19

10K

OMIT_TABLE

19

=PP3V3_S0_PCH_GPIO

NO STUFF

5%
1/20W
MF
201

CPU_PROC_SEL_L

10

DF_TVS:DMI & FDI Term Voltage


Set to Vss when Low
Set to Vcc when High

R2130 1
1K
5%
1/20W
MF
201 2

NC

This has internal pull up and should not pulled low.


THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

BL48
BL49
BL51
C3
C49
C51
D1
D51
E1

=PP3V3_S0_PCH_GPIO
C2113 1
0.1UF

JTAG_ISP_TCK

1/20W

MF

201

1/20W

MF

201

R2150
R2155
R2194
R2192
R2193

10K
10K
10K
10K
10K
10K
100K

1
1

2
2

R2191

10K

R2111
R2195
R2112
R2198

20K
100K
10K
10K

R2116

10K

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

PCH_A20GATE
PCH_RCIN_L
WOL_EN
TBT_GO2SX_BIDIR
SPIROM_USE_MLB
SMC_WAKE_SCI_L

5%
5%

1/20W
1/20W

MF
MF

5%

1/20W

MF

5%

1/20W

MF

DPMUX_UC_IRQ
201
AUD_IPHS_SWITCH_EN_PCH
201
ODD_PWR_EN_L
201
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

1/20W

MF

G 2

=PP3V3_S0_PCH_GPIO

OUT

C2114 1

CRITICAL

6 19 43

=PP3V3_S0_PCH_STRAPS

19

0.1UF

R2199 SSM6N15AFE

19

10K

19
19

IN

19

JTAG_ISP_TDI

SOT563

5%
1/20W
MF
201

10%
16V
X5R-CERM
0201

=PP3V3_TBT_PCH_GPIO

Q2160

R2161

5%
1/20W
MF
201

JTAG_TBT_TDI

IN

TBT_CIO_PLUG_EVENT

Q2162

SSM3K15FV

19 41

R2186

19

SOD-VESM-HF

10K

23 25
19
19 23

JTAG_ISP_TDO

5%
1/20W
MF
2 201

R2166
10K

R2162

OUT

1 NO STUFF

R2167
10K

5%
1/20W
MF

2 201

SYNC_MASTER=J11_MLB
PAGE TITLE

DRAWING NUMBER

Apple Inc.

5%
1/20W
MF
2 201

JTAG_TBT_TDO

SYNC_DATE=09/16/2011

PCH GPIO/MISC/NCTF

10K

051-9277

NOTICE OF PROPRIETARY PROPERTY:


IN

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

2.8.0

NC

TBT_CIO_PLUG_EVENT_ISOL

5%
1/20W
MF
2 201

=PP3V3_TBT_PCH_GPIO

201

SOT891

NC

OUT

CRITICAL

=PP3V3_S0_PCH_STRAPS

CRITICAL

6 74LVC1G08

4
U2101
1
08

6 19 43 50

10K

19 34

OUT

ENET_LOW_PWR_PCH

JTAG_TBT_TMS

19 41

201

1
5%

TBT_SW_RESET_R_L
FW_PWR_EN_PCH

JTAG_ISP_TMS

IN

19

Must stuff R2197 when R2180 NO STUFFed.

NO STUFF

R2197
R2184

19 23

5%
1/20W
MF

2 201

G 5

5%
5%

XDP_FC1_PCH_GPIO0
FW_PME_L
SMC_RUNTIME_SCI_L
LPCPLUS_GPIO

10K

201

R2163

201

MF

G 1

MF

1/20W

1/20W

5%

5%

10K
10K
10K
100K

5%
1/20W
MF

NO STUFF

Stuff R2160 or R2574, not both


R2160
R2185
R2196
R2190

SOT563

5%
1/20W
MF
2 201

NC

10K

R2188 SSM6N15AFE
10K

OUT

=PP3V3_TBT_PCH_GPIO

Q2160

JTAG_TBT_TCK

2 201

=PP3V3_S0_PCH_STRAPS

7 16 17 18 19 25 36

SOT891

4
U2100
08
NC

R2113

CRITICAL

7 16 17 18

6 74LVC1G08

NOTE: TCK from PCH is Push-Pull CMOS


NOTE: TMS/TDI from PCH is Open Drain
NOTE: TDO from CR is Push-Pull CMOS

=PP3V3_S5_PCH_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO

CRITICAL

TBT_PWR_EN

JTAG Isolation due to glitch in and out of sleep

10%
16V
X5R-CERM
0201

TBT_PWR_EN goes high for JTAG Programming

BRANCH
PAGE

21 OF 109

SHEET

19 OF 73

22

10%
16V
X5R-CERM 2
0201

22

22 16 7

C
C2222

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

=PP1V05_S0_PCH_VCCDIFFCLK

PP1V05_S0_PCH_VCCCLKDMI_F

PLACE_NEAR=U1800.U17:2.54mm
=PP1V05_S0_PCH_V_PROC_IO
22 7

10%
16V
X5R-CERM 2
0201

VCCDIFFCLKN

22 7

=PP1V05_S0_PCH_VCCASW

=PPVRTC_G3_PCH

C2231
1UF

20%
6.3V
X5R 2
0201

VCCSUSHDA V31

AC35 VCCSSC
U17 DCPSST
AP39 VCCCLKDMI
AM17 V_PROC_IO
N16 VCCRTC

17 16 7

VCCAPLL_SATA3 AM2

VCCIO
22

0.1UF

C2232
0.1UF

10%
16V
2 X5R-CERM
0201

C2233
0.1UF

10%
16V
2 X5R-CERM
0201

PLACE_NEAR=U1800.N16:2.54mm
PLACE_NEAR=U1800.N16:2.54mm
PLACE_NEAR=U1800.N16:2.54mm

=PP5V_S0_PCH_V5REF

22

AB27
AB29
AB31
AC27
AC29
AC31
AE27
AE29
AE31
R19
U19
U21
V19
V21
V23
V25
Y21
Y23
Y25
Y27
Y29
Y31

NC NC-ed per DG
=PP3V3R1V5_S0_PCH_VCCSUSHDA

10 mA Max, 1mA Idle

AA13
AB15
AC13
AC15
AF15
AG13
AG15
AJ17
AK21
N18
R23
R25
U23
U25

=PP1V05_S0_PCH_VCCIO

AM27
N27
R27
R29
R33
R35
U33
U35

=PP3V3_SUS_PCH_VCCSUS

7 22 25

7 20 22

VCCASW
DCPSUS

VCCVRM

AR33
AU31
AU33
V13
AC39
AE19
AF17
AW18
AW21

PCH-PPT-MB-SFF-ES1
BGA
QP8D-MM915462
(7 OF 10)

VCCCORE

VCCADAC U51
VSSA_DAC V50

VCCALVDS
VSSALVDS

VCCTX_LVDS

AP19 VCCAPLLEXP

TP_1V05_S0_PCH_VCCAPLLEXP

PP3V3_S0_PCH_VCCA_DAC_F

AM21
AP27
AR15
AR23
AR25
AR27
AR29
AT13
AU23
AU25
AU27
AU29
AU35
AW34

=PP1V05_S0_PCH_VCCIO

7 22

NC
NC
NC
NC
=PP1V8R1V5_S0_PCH_VCCVRM

VCCIO

22

AF33
AG33
AC33
AE33
AF37
AG37
AG39
AJ37

AM23
AU15
AW16
VCCADMI_VRM AU21

=PP1V05_S0_PCH_VCC_DMI

7 22

VCCDMI

VCCDFTERM

AP13
VCCAFDIPLL
AP15
VCCAFDI_VRM AU19

VCC3_3

=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V8_S0_PCH_VCC_DFTERM

7 19 22

=PP3V3_SUS_PCH_VCC_SPI

7 22

7 20

AJ13
AJ15
AK15
AL13

VCCSPI Y19
22 20 7

VCCSUS3_3

U1800

CRT

V5REF N36

DCPRTC

AC37
AE37
AE39

PPVOUT_S0_PCH_DCPSST

7 22

PCI/GPIO/LPC
R15
U15

BF40 VCCADPLLA
BD40 VCCADPLLB

=PP1V05_S0_PCH_VCCSSC

22 7

AW31 VCCAPLLDMI2

PP1V05_S0_PCH_VCCADPLLA_F
PP1V05_S0_PCH_VCCADPLLB_F

55mA Max, 5mA Idle

=PP3V3_SUS_PCH_VCCSUS_USB

USB

RTC CPU

0.1UF

U27
U29

AB21
AB23
AC21
AC23
AE21
AE23
AF21
AF23
AG21
AG23
AG25
AG27
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AK29
AK31
AK33
AM33
AM35

VCC CORE
LVDS

AL24 left as NC per DG

C2210

VCCPUSB

OMIT_TABLE

=PP1V05_S0_PCH_VCC_CORE

1.44 A Max, 474mA Idle

DMI

PPVOUT_G3_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

22

FDI

PLACE_NEAR=U1800.R15:2.54mm

=PP5V_SUS_PCH_V5REFSUS

VCCIO

VCCAPLLDMI2 pin left as NC per DG


NC
PCH output, for decoupling only

R10 DCPSUSBYP

BGA
QP8D-MM915462
(8 OF 10)

SATA

TP_PPVOUT_PCH_DCPSUSBYP

V5REF_SUS M37

PCH-PPT-MB-SFF-ES1
R12 VCCDSW3_3

HDA

=PP3V3_S5_PCH_VCCDSW

22 7

U1800

AC51 VCCACLK

CLK/MISC

22 7

NC

DFT/SPI

OMIT_TABLE

VCCACLK pin left as NC per DG

NC
NC

AB19
AC19
AF6
BK28
R40
T39
U37
V37
V39

=PP1V8R1V5_S0_PCH_VCCVRM

7 20

=PP3V3_S0_PCH_VCC3_3

7 22

PP3V3_S0_PCH_VCC3_3_CLK_F

22

7 20

PCH output, for decoupling only

SYNC_MASTER=J11_MLB
PAGE TITLE

SYNC_DATE=09/30/2011

PCH POWER
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

22 OF 109

SHEET

20 OF 73

U1800

PCH-PPT-MB-SFF-ES1
BGA
QP8D-MM915462
(9 OF 10)

VSS

OMIT_TABLE

OMIT_TABLE
AA7
AA9
AA11
AA39
AA41
AA43
AA45
AB2
AB4
AB17
AB25
AB33
AB35
AB37
AB48
AB50
AC7
AC9
AC11
AC17
AC25
AC41
AC43
AC45
AE7
AE9
AE11
AE13
AE15
AE17
AE25
AE35
AE41
AE43
AE45
AF2
AF4
AF8
AF19
AF25
AF27
AF29
AF31
AF35
AF48
AF50
AG7
AG9
AG11
AG17
AG19
AG29
AG31
AG35
AG41
AG43
AG45
AH2
AJ7
AJ9
AJ11
AJ19
AJ33
AJ35
AJ39
AJ41
AJ43
AJ45
AK2
AK4
AK17
AK19
AK23
AK25
AK27
AK35
AK37
AK48
AK50
AL7
AL9
AL11
AL39
AL41
AL43
AL45
AM15
AM19
AM25
AM29
AM31
AM37

VSS

BC23
BC25
BC27
BC29
BC31
BC34
BC36
BC39
BC41
BC43
BC45
BD15
BD24
BE7
BE9
BE11
BE13
BE16
BE18
BE21
BE23
BE25
BE27
BE29
BE31
BE34
BE36
BE39
BE41
BE43
BE45
BF2
BF4
BF15
BF24
BF48
BF50
BH6
BH10
BH14
BH18
BH22
BH26
BH28
BH30
BH32
BH34
BH38
BH42
BH44
BH46
BH48
BK10
BK14
BK18
BK22
BK26
BK30
BK32
BK34
BK38
BK42
BK46
D6
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
F2
F4
F48
F50
G7
G9
G11
G13
G16
G18
G21
G23
G25
G27
G29
G31
G34
G36

AP2
AP4
AP7
AP9
AP11
AP17
AP21
AP23
AP25
AP29
AP31
AP33
AP35
AP37
AP41
AP43
AP45
AP48
AP50
AR6
AR8
AR17
AR19
AR21
AR31
AR35
AR37
AT7
AT9
AT11
AT39
AT41
AT43
AT45
AU17
AU37
AV2
AV4
AV48
AV50
AW7
AW9
AW11
AW13
AW23
AW25
AW27
AW29
AW36
AW39
AW41
AW43
AW45
AY10
B6
B10
B14
B18
B22
B26
B30
B34
B38
B42
B46
BA7
BA9
BA11
BA13
BA16
BA18
BA21
BA23
BA25
BA27
BA29
BA31
BA34
BA36
BA39
BA41
BA43
BA45
BB2
BB4
BB48
BB50
BC11
BC13
BC16
BC18
BC21

U1800

PCH-PPT-MB-SFF-ES1
BGA
QP8D-MM915462
(10 OF 10)

VSS

VSS

G39
G41
G43
J7
J9
J11
J13
J16
J18
J21
J23
J25
J27
J29
J31
J34
J36
J39
J41
J45
K2
K4
K48
K50
L7
L9
L11
L13
L16
L18
L21
L23
L25
L27
L29
L31
L34
L36
L39
L41
L43
L45
N7
N9
N11
N13
N21
N23
N25
N29
N31
N34
N39
N41
N43
N45
P2
P4
P48
P50
R17
R21
R31
R37
T7
T9
T11
T13
T41
T43
T45
U31
U49
V2
V4
V7
V9
V11
V15
V17
V27
V29
V33
V35
V41
V43
V45
V48
Y15
Y17
Y33
Y35
Y37

SYNC_MASTER=J30_MLB
PAGE TITLE

SYNC_DATE=07/27/2011

PCH GROUNDS
DRAWING NUMBER

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

051-9277

REVISION
BRANCH
PAGE

23 OF 109

SHEET

21 OF 73

1
PCH VCCIO BYPASS

L2406

16 7

16 7

10UH-0.12A-0.36OHM
R2415
0 2
2 PP1V05_S0_PCH_VCCCLKDMI_R 1
=PP1V05_S0_PCH 1
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V

0603

PCH VCCSUS3_3 BYPASS

20 19 7

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

5%
1/20W
MF
201

20

=PP3V3_SUS_PCH_VCCSUS
1

C2411

C2484

10%
2 16V
X5R-CERM
0201

(PCH USB 1.05V PWR)

20 7

C2452

=PP3V3_SUS_PCH_VCCSUS_USB

1UF

20%
2 6.3V
X5R
0201

C2446
1UF

PLACE_NEAR=U1800.U27:2.54mm

20%
2 6.3V
X5R
0201

PLACE_NEAR=U1800.AB15:2.54mm
PLACE_NEAR=U1800.AG13:2.54mm

PLACE_NEAR=U1800.R27:2.54mm

20%
2 6.3V
X5R
0201

0.1UF

0.1UF

10%
2 16V
X5R-CERM
0201

C2444
1UF

C2440

10%
2 16V
X5R-CERM
0201

PLACE_NEAR=U1800.AJ13:2.54mm

C2413

0.1UF

10UF

20%
6.3V
2 CERM-X5R
0402-2

PLACE_NEAR=U1800.AP39:2.54mm

=PP1V8_S0_PCH_VCC_DFTERM

(PCH SUSPEND USB 3.3V PWR)

22 20 7

=PP1V05_S0_PCH_VCCIO_SATA

PCH VCCSUSHDA BYPASS


(PCH HD Audio 3.3V/1.5V PWR)

PLACE_NEAR=U1800.N27:2.54mm
25 20 7

=PP3V3R1V5_S0_PCH_VCCSUSHDA
1

=PP3V3_S0_PCH_VCCADAC

C2416 1

20

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

4.7UF

0.1UF

20%
6.3V 2
X5R
402

PLACE_NEAR=U1800.AM17:2.54mm
PLACE_NEAR=U1800.AM17:2.54mm
PLACE_NEAR=U1800.AM17:2.54mm

C2417

C2450

C2451

10UF

0.1UF

10%
16V
X5R-CERM 2
0201

20%
6.3V
CERM-X5R 2
0402-2

C2455

20%
2 6.3V
X5R
0201

10%
2 16V
X5R-CERM
0201

=PP3V3_SUS_PCH_VCC_SPI
1

C2442
1UF

0.01UF

20%
6.3V
2 X5R
0201

PLACE_NEAR=U1800.Y19:2.54mm

10%
16V
X5R-CERM 2
0201

20 16 7

=PP1V05_S0_PCH_VCCDIFFCLK
1

=PP1V05_S0_PCH_VCCIO

22 20 7

C2434

=PP1V05_S0_PCH_VCC_DMI
1

20%
2 6.3V
X5R
0201

PLACE_NEAR=U1800.AJ17:2.54mm

20%
6.3V
2 X5R
0201

PLACE_NEAR=U1800.AC37:2.54mm

C2469
1UF

1UF

22 20 7

20%
2 6.3V
X5R
0201

PLACE_NEAR=U1800.R33:2.54mm

0.1UF

10%
2 16V
X5R-CERM
0201

PLACE_NEAR=U1800.U51:2.54mm
PLACE_NEAR=U1800.U51:2.54mm
PLACE_NEAR=U1800.U51:2.54mm

C2476
1UF

1UF

C2430

20 7

=PP3V3_SUS_PCH_VCCSUS

C2475

PLACE_NEAR=U1800.AC35:2.54mm

PP3V3_S0_PCH_VCCA_DAC_F

5%
1/20W
MF
201

22 20 7

=PP1V05_S0_PCH_VCCSSC

10%
2 16V
X5R-CERM
0201

=PP1V05_S0_PCH_V_PROC_IO

R2450
7

20 7

0.1UF

PLACE_NEAR=U1800.V31:2.54mm

20 7

C2441

C2419
1UF

20%
2 6.3V
X5R
0201

20 7

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S0_PCH
=PP5V_S0_PCH

PLACE_NEAR=U1800.R12:2.54mm

PCH V5REF Filter & Follower

22 20 7

16 7
25 7

1 mA

R2405
100

=PP1V05_S0_PCH_VCC_DMI

D2400

10%
16V
X5R-CERM 2
0201

PCH VCCCORE BYPASS

20 7

PP5V_S0_PCH_V5REF
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE

1UF

1UF

=PP3V3_S0_PCH_VCC3_3_CLK1

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

0603

C2453 1 VOLTAGE=3.3V

4
2
NC

22 20 7

C2429

20%
2 6.3V
X5R
0201

C2407
1UF

20%
2 6.3V
X5R
0201

C2463 C2401 1
1UF

20%
2 6.3V
X5R
0201

10UF

20%
6.3V
CERM-X5R 2
0402-2

=PP5V_SUS_PCH_V5REFSUS

=PP1V05_S0_PCH_VCCADPLL

PP1V05_S0_PCH_VCCADPLLA_F

5%
1/16W
MF-LF
402

20

PLACE_NEAR=U1800.AR25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU29:2.54mm
PLACE_NEAR=U1800.AR29:2.54mm
PLACE_NEAR=U1800.AU27:2.54mm

PCH VCCADPLLA Filter


(PCH DPLLA PWR)

R2460

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1

C2402

20

68 mA

C2461
1UF

20 7

=PP1V05_S0_PCH_VCCASW

PLACE_NEAR=U1800.BF40:2.54MM

20%
6.3V

2 X5R

0201

=PP3V3_S0_PCH_VCC3_3

C2421

0.1UF

22 20 7

PLACE_NEAR=U1800.AF6:2.54mm

20%
2 6.3V
X5R
0201
1

C2423
PLACE_NEAR=U1800.AB19:2.54mm

10%
2 16V
X5R-CERM
0201

5%
1/16W
MF-LF
402

PLACE_NEAR=U1800.BK28:2.54mm

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1

C2465
0.1UF
10%

2 16V
X5R-CERM
0201

=PP3V3_S0_PCH_VCC3_3

1UF

20%
2 6.3V
X5R
0201

1UF

20%
2 6.3V
X5R
0201

22UF

20%
6.3V
X5R-CERM1 2
0603

C2420 1
22UF

20%
6.3V
X5R-CERM1 2
0603

PCH VCCADPLLB Filter


(PCH DPLLB PWR)

R2465

C2422
0.1UF

10%
2 16V
X5R-CERM
0201

C2426 1 C2456 1 C2496 C2428 1


1UF

=PP3V3_S0_PCH_VCC3_3

0.1UF

10%
2 16V
X5R-CERM
0201

22 20 7

20%
2 6.3V
X5R
0201

NEED PWR CONSTRAINT

PLACE_NEAR=U1800.BF40:2.54MM

1UF

10%
16V
2 X5R-CERM
0201

C2414

D2400

0.1UF

22 20 7

SOT-363

PP5V_SUS_PCH_V5REFSUS

20%
10V
CERM 2
402

=PP3V3_S0_PCH_VCC3_3

10UF

20%
6.3V
CERM-X5R 2
0402-2

=PP1V05_S0_PCH_VCCIO

1UF

PLACE_NEAR=U1800.V37:2.54mm
PLACE_NEAR=U1800.V37:2.54mm

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE

0.1UF

22 20 7

C2460 1

20%
2 6.3V
X5R
0201

BAT54DW-X-G

C2438 1
PLACE_NEAR=U1800.M37:2.54mm

1UF

10%
10V
X5R 2
402

(PCH Reference for 5V Tolerance on USB)

NC

5%
1/20W
MF
201

C24861
1UF

10UF

10

C2483

L2451

PCH V5REF_SUS Filter & Follower

R2404

10UH-0.12A-0.36OHM
PP3V3_S0_PCH_VCC3_3_CLK_R 1
20 2
PP3V3_S0_PCH_VCC3_3_CLK_F

20%
6.3V
CERM-X5R 2
0402-1

1UF

20

5%
1/16W
MF-LF
402

1 mA S0-S5

C2482

PLACE_NEAR=U1800.AB21:2.54mm
PLACE_NEAR=U1800.AB21:2.54mm
PLACE_NEAR=U1800.AB21:2.54mm
PLACE_NEAR=U1800.AB21:2.54mm

R2451

=PP3V3_SUS_PCH
=PP5V_SUS_PCH

20%
2 6.3V
X5R
0201

20%
2 6.3V
X5R
0201

PLACE_NEAR=U1800.AW16:2.54mm

C2481

<1 MA

=PP5V_S0_PCH_V5REF

10%
10V 2
X5R
402

C2418

20%
2 6.3V
X5R
0201

SOT-363

C2439 1

(PCH 1.05V CORE PWR)


=PP1V05_S0_PCH_VCC_CORE

1UF

BAT54DW-X-G

NC

NC

NEED PWR CONSTRAINT

PLACE_NEAR=U1800.N36:2.54mm

0.1UF

(PCH Reference for 5V Tolerance on PCI)

5%
1/20W
MF
201

C2499 1

PLACE_NEAR=U1800.AM23:2.54mm

20

PLACE_NEAR=U1800.AB27:2.54mm
PLACE_NEAR=U1800.AB27:2.54mm
PLACE_NEAR=U1800.AB27:2.54mm
PLACE_NEAR=U1800.AB27:2.54mm
PLACE_NEAR=U1800.AB27:2.54mm

69 mA

C2466
1UF
20%

PLACE_NEAR=U1800.BD40:2.54MM

2 6.3V
X5R
0201

SYNC_MASTER=J11_MLB

PLACE_NEAR=U1800.BD40:2.54MM

SYNC_DATE=10/03/2011

PAGE TITLE

C2424
0.1UF

PLACE_NEAR=U1800.T39:2.54mm

22 20 7

10%
2 16V
X5R-CERM
0201

PCH DECOUPLING

=PP3V3_S0_PCH_VCC3_3
1

DRAWING NUMBER

C2485

Apple Inc.

0.1UF

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PLACE_NEAR=U1800.R40:2.54mm

SIZE

2.8.0

10%
2 16V
X5R-CERM
0201

051-9277

REVISION
BRANCH
PAGE

24 OF 109

SHEET

22 OF 73

4
CRITICAL
XDP_CONN

M-ST-SM1

62

1K

66 10

66 10

IN

66 10

IN

66 10

IN

66 10

IN

66 9

IN

66 9

IN

66 9

IN

66 9

IN

R2560
R2561
R2562
R2563

XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

R2564
R2565
R2566
R2567

CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>

(R2564-R2567)
XDP_CPU:CFG
0 1
2
0 1
2 5%
0 1
2 5%
5%
0 1
2
5%

R2500

1K 1
PLACE_NEAR=U1000.B46:2.54mm

IN

CPU_PWRGD

41 23 17

OUT

PM_PWRBTN_L

66 23 9

OUT

CPU_CFG<0>

OUT

PM_PCH_SYS_PWROK

R2502

0 1
PLACE_NEAR=U4900.J3:2.54mm

R2501

1K 1
PLACE_NEAR=U1000.B50:2.54mm

R2504

402
402
402
1/16W MF-LF 402

5%

PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM

66 19 10

41 25 17

(R2560-R2563)
XDP_CPU:BPM
0 1
2
0 1
2 5% 1/16W MF-LF
0 1
2 5% 1/16W MF-LF
5% 1/16W MF-LF
0 1
2

330

1/16W MF-LF
1/16W MF-LF
1/16W MF-LF
1/16W MF-LF

BI
IN

66 10

IN

66 10

IN

66 10

IN

66 10

IN

66 9

IN

66 9

IN

66

201

5%

1/20W

MF

201

XDP_CPU_CFG<0>
XDP_VR_READY

5%

1/20W

MF

201

=SMBUS_XDP_SDA
=SMBUS_XDP_SCL

5%

1/16W MF-LF 402

44 23

BI

44 23

IN
OUT

XDP SIGNALS
23

OUT

23

OUT

23

OUT

5%

OUT

R2524
R2525
R2526
R2527
R2528

33
33
33
33
33

1
1
1
1
1

2
2
2
2
2

OUT

XDP_FC1

33

XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK

R2529
R2530
R2531
R2532
R2533
R2534
R2535

33
33
33
33
33
33

1
1
1
1
1
1

2
2
2
2
2
2

XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR

R2536
R2537

33
33

1
1

2
5%
2
5%

OUT

23

OUT

23

IN

23

OUT

23

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

SDA
SCL
TCK1
TCK0

R2580
1
2

(R2520-R2537)
1/20W
5%
1/20W
5%
XDP
MF
MF
201 1K
201 1K
PCH SIGNALS
33 1
2
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
5%
1/20W
MF
201
33 1
2
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
201
33 1
2 5% 1/20W MF
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
201
33 1
2 5% 1/20W MF
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DB1_USB_EXTD_OC_EHCI_L
XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE
XDP_FC0

23

23

R2520
R2521
R2522
R2523

PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3

XDP_CPU_TCK

R2581
1
2

XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTB_OC_L
XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L

OBSDATA_B2
OBSDATA_B3

XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L

MF

66 23 10

OUT

OBSDATA_B0
OBSDATA_B1

XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>

1/20W

C
23

OBSFN_B0
OBSFN_B1

XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>

5%

XDP
1

OBSDATA_A2
OBSDATA_A3

CPU_CFG<10>
CPU_CFG<11>

66

XDP
2

OBSDATA_A0
OBSDATA_A1

XDP_BPM_L<2>
XDP_BPM_L<3>

66

XDP
2

5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%

1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W

MF

MF
MF
MF
MF
MF
MF
MF

MF

IN

18 23

IN

18 23

IN

18

IN

18

IN

18

IN

18

OUT

18 23

IN

18 23

IN

19

IN

19 23

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L OUT
201
XDP_DC1_PCH_GPIO35_MXM_GOOD OUT
201
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL OUT
201
XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT
201
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL OUT
201
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK OUT
201

10%
16V
X7R-CERM 2
0402

201

19

23
23

23
23

41 23 17

OUT

PM_PWRBTN_L

R2585

XDP
2

5%

1/20W

MF

201

XDP

1
PLACE_NEAR=U4900.J3:2.54mm

5%

1/20W

MF

201

6
6

44 23
44 23

69 23 16

5
7

10

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

34

33

36

35

38

37

40

39

42

41

44

43

46

45

48

47

50

49

52

51

54

53

56

55

58

57

60

59

63

66 23 10

XDP_CPU_TMS

R2512

51

IN

66 23 10

XDP_CPU_TCK

R2513

51

IN

66 23 10

XDP_CPU_TRST_L

R2514

51

OBSDATA_C0
OBSDATA_C1

CPU_CFG<0>
CPU_CFG<1>

IN

9 23 66

IN

9 66

OBSDATA_C2
OBSDATA_C3

CPU_CFG<2>
CPU_CFG<3>

IN

9 66

IN

9 66

OBSFN_D0
OBSFN_D1

CPU_CFG<8>
CPU_CFG<9>

IN

9 66

IN

9 66

OBSDATA_D0
OBSDATA_D1

CPU_CFG<4>
CPU_CFG<5>

IN

9 66

IN

9 66

OBSDATA_D2
OBSDATA_D3

CPU_CFG<6>
CPU_CFG<7>

IN

9 66

IN

9 66

R2515

XDP
1

ITPCLK/HOOK4 66 XDP_CPU_CLK100M_P
XDP
R2516 0 1
ITPCLK#/HOOK5 66 XDP_CPU_CLK100M_N
VCC_OBS_CD
RESET#/HOOK6 66 XDP_CPURST_L
XDP
XDP_DBRESET_L
R2505 1K 1
DBR#/HOOK7
OUT 10 23 25 66
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
XDP_CPU_TDO
TDO
IN 10 23 66
XDP_CPU_TRST_L
TRSTn
OUT 10 23 66
XDP_CPU_TDI
TDI
OUT 10 23 66
XDP_CPU_TMS
TMS
OUT 10 23 66
XDP_PRESENT#
XDP
1

C2501

23 18

OUT

23 18

OUT

23 18

IN

23 18

OUT

23 19

OUT

23 16

IN

23 19

OUT

23 19

OUT

23 19

OUT

=PP3V3_S5_XDP

5% 1/16W MF-LF 402


PLACE_NEAR=U1000.L56:2.54mm

XDP
2

5% 1/16W MF-LF 402


PLACE_NEAR=U1000.J58:2.54mm

XDP

16 66

IN

16 66

PLACE_NEAR=U1000.D44:2.54mm
2
CPU_RESET_L
IN
5% 1/20W MF
201

5% 1/16W MF-LF 402


PLACE_NEAR=U1000.L55:2.54mm

XDP

IN

5%

1/16W MF-LF 402

10 25

PCH SIGNALS

0.1UF

10%
16V
2 X7R-CERM
0402

PLACE_NEAR=R1841.1:2.54mm
2
ITPXDP_CLK100M_P
5% 1/20W MF
201
PLACE_NEAR=R1840.1:2.54mm
2
ITPXDP_CLK100M_N
5% 1/20W MF
201

Non-XDP Signals

R2590 0
R2592 0
XDP_DB2_PCH_GPIO10_AP_PWR_EN
R2596 0
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE R2597 0
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
R2570 0
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
R2572 0
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
R2575 0
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH R2576
XDP_FC1_PCH_GPIO0
R2574 1K
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

1
1
1
1
1
1
1

USB_EXTA_OC_L
USB_EXTB_OC_L

2
2

5% 1/20W MF
201
2 5% 1/20W MF
AP_PWR_EN
201
201
2 5% 1/20W MF
SDCONN_STATE_RST_L
5% 1/20W MF
201
2
ISOLATE_CPU_MEM_L
5% 1/20W MF
201
2
DP_AUXCH_ISOL
5% 1/20W MF
201
2
JTAG_ISP_TCK
5% 1/20W MF
201
2
AUD_IPHS_SWITCH_EN_PCH
5% 1/20W MF
201
2

5%

1/20W

39

IN

40

OUT

18 37 62

IN

33

OUT

26

OUT

16 25

OUT

8 19

OUT

19 25

TBT_CIO_PLUG_EVENT_ISOL

MF

IN

OUT

201

34

BI
IN
OUT

OBSDATA_A0
OBSDATA_A1

10

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

34

33

36

35

38

37

40

39

42

41

44

43

46

45

48

47

50

49

52

51

54

53

56

55

58

57

60

59

64

63

OBSDATA_A2
OBSDATA_A3
OBSFN_B0
OBSFN_B1

XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DB1_USB_EXTD_OC_EHCI_L

OBSDATA_B0
OBSDATA_B1

XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE

OBSDATA_B2
OBSDATA_B3

XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L
TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
XDP_PCH_TCK

61

OBSFN_A0
OBSFN_A1

PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0

C2580 1
0.1UF

10%
16V
X7R-CERM 2
0402

R2511

5% 1/16W MF-LF 402


PLACE_NEAR=U1000.M60:2.54mm

XDP

M-ST-SM1

62

NC

XDP

XDP_CPU_TDI

J2550

19 23

8 19

TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>

1
PLACE_NEAR=J2550.50:2.54mm

66 23 10

51

PLACE_NEAR=J2500.52:2.54mm
2

CRITICAL
XDP_CONN

8 16

OUT

XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L

23

R252x, R253x, R257x and R259x should be placed where signal path
needs to split between route from PCH to J2550
and path to non-XDP signal destination.

1K

16 23

19 23

XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTB_OC_L

23
23

R2584

6
8

CPU_CFG<16>
CPU_CFG<17>

OBSFN_C0
OBSFN_C1

PCH Micro2-XDP

19

OUT

TP_XDP_PCH_OBSFN_A<0>
TP_XDP_PCH_OBSFN_A<1>

23

ALL_SYS_PWRGD

NOTE: This is not the standard XDP pinout.


Use with 921-0133 Adapter Flex to
support chipset debug.

19 23

51

DF40RC-60DP-0.4V

- Following Intels Debug Prot Design Guid for HR and CR v1.3


doc id 404081.
Initially, stuffing both 33 and 0 ohms and validate whether
it is functional in that state, else add BOM options.
- For isolated GPIOs:
- Output non-XDP signals require pulls.
- Output PCH/XDP signals require pulls.

IN

518S0847

PCH/XDP Signal Isolation Notes:

62 52 41 25

64

0.1UF

XDP_FC1_PCH_GPIO0

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
1/20W MF
201
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
1/20W

C2500

201
201

NC

R2510

61

XDP

201

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
MF
201
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
MF
201
XDP_DB2_PCH_GPIO10_AP_PWR_EN
MF
201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
MF
201
XDP_FC0_PCH_GPIO15
MF

OBSFN_A0
OBSFN_A1

XDP_BPM_L<0>
XDP_BPM_L<1>

66

402
402
402
402

XDP
2

XDP_CPU_PREQ_L
XDP_CPU_PRDY_L

=PPVCCIO_S0_XDP

XDP

XDP_CPU_TDO

66 23 10

DF40RC-60DP-0.4V

5%
1/16W
MF-LF
402 2

1
23 7

NOTE: This is not the standard XDP pinout.


Use with 921-0133 Adapter Flex to
support chipset debug.

J2500

=PP3V3_S0_XDP
NO STUFF

R25401

66 10

CPU Micro2-XDP

=PPVCCIO_S0_XDP

23 7

518S0847

B
OBSFN_C0
OBSFN_C1

XDP_FC0
XDP_FC1

OBSDATA_C0
OBSDATA_C1

XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD

OBSDATA_C2
OBSDATA_C3

XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN

OBSFN_D0
OBSFN_D1

TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>

OBSDATA_D0
OBSDATA_D1

XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK

OBSDATA_D2
OBSDATA_D3

XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR

23
23

23
23

23
23
7

=PP1V05_SUS_PCH_JTAG

6
6
69 23 16

XDP_PCH_TDO

R2550

51

XDP
2

23
23
69 23 16

XDP_PCH_TDI

23
23

69 23 16

XDP_PCH_TMS

R2551
R2552

51
51

PLACE_NEAR=J2550.51:2.54mm
1

XDP
2

XDP
2

5% 1/20W MF
201
PLACE_NEAR=U1800.U12:2.54mm
5% 1/20W MF
201
PLACE_NEAR=U1800.M15:2.54mm
5%

1/20W

MF

201

XDP PLACE_NEAR=U1800.M17:2.54mm
TP_XDP_PCH_HOOK4
ITPCLK/HOOK4
6
1
XDP_PCH_TCK
R2556 51 2
69 23 16
ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5
6
5% 1/20W MF
201
VCC_OBS_CD
XDPPCH_PLTRST_L
RESET#/HOOK6
1K series R on PCH Support Page
IN 25
XDP_DBRESET_L
DBR#/HOOK7
OUT 10 23 25 66
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
XDP_PCH_TDO
TDO
IN 16 23 69
SYNC_MASTER=J13_MLB_NON_POR
SYNC_DATE=10/17/2011
TP_XDP_PCH_TRST_L
TRSTn
PAGE TITLE
XDP_PCH_TDI
TDI
OUT 16 23 69
XDP_PCH_TMS
TMS
OUT 16 23 69
DRAWING NUMBER
SIZE
XDP_PRESENT#
051-9277 D
XDP
Apple Inc.

CPU & PCH XDP

REVISION

C2581

10%
16V
2 X7R-CERM
0402

2.8.0

0.1UF

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH
PAGE

25 OF 109

SHEET

23 OF 73

1
TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

HUB_ALLREM

HUB_NONREM1_0,HUB_NONREM0_0

HUB_1NONREM

HUB_NONREM1_0,HUB_NONREM0_1

HUB_2NONREM

HUB_NONREM1_1,HUB_NONREM0_0

HUB_3NONREM

HUB_NONREM1_1,HUB_NONREM0_1

TABLE_BOMGROUP_ITEM

24 7

=PP3V3_S3_USB_HUB

C2602

BYPASS=U2600.5::5mm
BYPASS=U2600.34::2mm
BYPASS=U2600.23::2mm
1
1
1 BYPASS=U2600.15::2mm

4.7UF

20%
6.3V
X5R-CERM1
402

C2603

C2611

C2612

0.1UF

0.1UF

0.1UF

10%
16V
X5R-CERM
0201

10%
16V
X5R-CERM
0201

10%
16V
X5R-CERM
0201

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

NON_REM1

BYPASS=U2600.23::5mm
BYPASS=U2600.29::2mm
BYPASS=U2600.5::2mm
BYPASS=U2600.10::2mm

C2609

0.1UF

10%
16V
X5R-CERM
0201

C2610

0.1UF

10%
16V
X5R-CERM
0201

PPUSB_HUB1_CRFILT

10%
16V
X5R-CERM
0201

VOLTAGE=1.8V

Y2600

CRFILT

CRITICAL

VDD33

2.50X2.00MM-SM

24.000MHZ-50PPM-6PF
1

CRITICAL
6.0PF

HUB_NONREM1_1

HUB_NONREM0_1

R2601 1

10K
5%
1/20W
MF
201

10K

HUB_NONREM1_0

R2602

5%
1/20W
MF
201

R2630
1M

+/-0.1PF
25V
NP0-C0G-CERM
201

100

C2615

0.1UF
2

10%
16V
X5R-CERM
0201

10%
16V
X5R-CERM
0201

C2616
1UF

D
TABLE_5_HEAD

PART#

1UF
20%
6.3V
X5R
0201

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
USBHUB2512B

TABLE_5_ITEM

338S0983

IC,USB2512B,USB 2.0 HUB CNTRL,36-QFN

U2600

CRITICAL

338S0923

IC,USB2513B,USB 2.0,HUB CNTRL,3PRT,36QFN

U2600

CRITICAL

USBHUB2513B

U2600

CRITICAL

USBHUB2514B

TABLE_5_ITEM

20%
6.3V
X5R
0201

TABLE_5_ITEM

338S0824

IC,USB2514B,USB 2.0,HUB CNTRL,4PRT

11

USB_HUB_RESET_L

26

RESET*

USB_HUB1_XTAL1
USB_HUB1_XTAL2

33
32

XTALIN/CLKIN
XTALOUT

USB_HUB1_NONREM0

28

USB_HUB1_NONREM1

22

USB_HUB1_CFG_SEL0

24

USBDM_DN3/PRT_DIS_M3
SUSP_IND/LOCAL_PWR/NON_REM0
USBDP_DN3/PRT_DIS_P3
SDA/SMBDATA/NON_REM1
NC
SCL/SMBCLK/CFG_SEL0
NC

24

25

USB_HUB1_CFG_SEL1

R2604
1

R2606

10K

5%
1/20W
MF
201

TO CONNECT TP/KB TO PCH XHCI


NOSTUFF R2611 & R2615, STUFF R2621 & R2622,R2616 & R2617

QFN
USB_HUB1_TEST

5%
1/20W
MF
201

5%
1/20W
MF 201

5%
1/20W
MF
201

C2618

USB2513B

R2605
TEST

USBDM_DN1/PRT_DIS_M1 1
USBDP_DN1/PRT_DIS_P1 2

USB_BT_N
USB_BT_P

BI

37 68

BI

37 68

USBDM_DN2/PRT_DIS_M2 3
USBDP_DN2/PRT_DIS_P2 4

USB_TPAD_HUB_N
USB_TPAD_HUB_P

BI

24 68

BI

24 68

6
7

USB_SDCARD_N
USB_SDCARD_P

BI

33 68

BI

33 68

8
9

USB_SMC_N
USB_SMC_P

BI

24 41 68

BI

24 41 68

HS_IND/CFG_SEL1

10K

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V

0.1UF

DESCRIPTION
All ports are removable
Port 1 is non removable
Port 1 and 2 are non removable
Port 1, 2, and 3 are non removable

U2600

6.0PF

CRITICAL
1

SYM VER 1

C2620

HUB_NONREM0_0

10K
5%
1/20W
MF
201

R2603

+/-0.1PF
25V
NP0-C0G-CERM
201

CRITICAL

2 4

NC
NC

C2619

CRITICAL
OMIT_TABLE

C2617

PPUSB_HUB1_PLLFILT

0
1
0
1

BOM TABLE

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

0.1UF

34

C2608

5
10
15
23
29
36

20%
6.3V
X5R-CERM1
402

14

4.7UF

PLLFILT

C2607

NON_REM0

0
0
1
1

R2607
10K

PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
NC

12
16
18
20

TP_USB_HUB1_PRTPWR1
NC_USB_HUB1_PRTPWR2
NC_USB_HUB1_PRTPWR3
NC_USB_HUB1_PRTPWR4

OCS1*
OCS2*
OSC3*
NC

13
17
19
21

TP_USB_HUB1_OCS1
NC_USB_HUB1_OCS2
NC_USB_HUB1_OCS3
NC_USB_HUB1_OCS4

5%
1/20W
MF
201

IPU
IPU
IPU
IPU

RBIAS 35

BlueTooth
24 7

=PP3V3_S3_USB_HUB

Trackpad/Keyboard

TPAD_PCH:YES 1TPAD_PCH:YES
1

R2616
10K

SDCARD(NA to K78)

5%
1/20W
MF
201 2

R2617
10K

5%
1/20W
MF
201 2

TPAD_PCH:NO

68 24

=PP3V3_S3_USB_HUB

USB_TPAD_HUB_P

5%
1/20W
MF
201

TO USB HUB
7 24
68 24

BI

USB_TPAD_HUB_N

BI

R2621

USB_TPAD_R_P

68 49

TPAD_PCH:NO

R2615

TO TP/KB

0
5%
1/20W
MF
201

USB_TPAD_R_N

USB_EXTD_XHCI_P

10K

BI

TPAD_PCH:YES

18 68

TO PCH XHCI

R2622

5%
1/20W
MF
201

R2620

TPAD_PCH:YES

R2611

SMC Port

USB_EXTD_XHCI_N

BI

18 68

5%
1/20W
MF
201

5%
1/20W
MF
201

USB_HUB1_RBIAS

VBUS_DET 27

USB_HUB1_VBUS_DET

USBDM_UP 30
USBDP_UP 31

USB_HUB_UP_N
USB_HUB_UP_P

=PP3V3_S3_USB_HUB

7 24

CRITICAL

BI

18 68

BI

18 68

R2600
12K

THRM_PAD
37

NOSTUFF

R2618

1%
1/20W
MF
201

NOSTUFF

R2619

10K

10K

5%
1/20W
MF

5%
1/20W
MF

2 201

2 201

USB_SMC_P

68 41 24

68 41 24

USB_SMC_N

USB XHCI/EHCI2 PORT MUX FOR EXT B


7

=PP3V3_S3_USBMUX
7

0.1UF

PCH PORT 9 (EHCI2)

68 18
68 18

BI

10%
16V
X5R-CERM
0201
USB_EXTB_EHCI_P

BI

USB_EXTB_EHCI_N

TO LIO CONNECTOR

C2663

VCC

5 M+
4 M-

Y+ 1
Y- 2

U2660

USB_EXTB_P
USB_EXTB_N

R26121
BI

6 40 68

BI

6 40 68

10K

LIO External D

5%
1/20W
MF
201 2

PI3USB102ZLE

PCH PORT 1 (XHCI)

68 18

BI

68 18

BI

USB_EXTB_XHCI_P
USB_EXTB_XHCI_N

7 D+
6 D-

=PP3V3_S3_USB_RESET

TQFN

CRITICAL

USB_HUB_RESET_L

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE


SEL 10

8 OE*
3

GND

USB_EXTB_SEL_XHCI
IN
SEL=0 CHOOSE USB EHCI2 PORT
SEL=1 CHOOSE USB XHCI PORT

24

16

C2604

0.1UF

10%
16V
X5R-CERM
0201

PCH GPIO60

PLACE_NEAR=U2600.26:2.5MM

SYNC_MASTER=J13_MLB_NON_POR
PAGE TITLE

SYNC_DATE=11/10/2011

USB HUB & MUX


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

26 OF 109

SHEET

24 OF 73

Platform Reset Connections

System RTC Power Source & 32kHz / 25MHz Clock Generator

Unbuffered
R2781

=PPVBAT_G3H_SYSCLK

Coin-Cell:

26 18

IN

33

PLT_RESET_L

Coin-Cell & No G3Hot: 3.3V S5


No Coin-Cell:
GreenClk 25MHz Power
Powered in S0

IN

LPC_CLK33M_SMC_R

No bypass necessary

SB XTAL Power

=PPVDDIO_S0_SBCLK

13

TBT XTAL Power

=PPVDDIO_TBT_CLK

VDD_25M

+V3.3A

+3.42V

0.1UF

0.1UF

10%

10%

16V

16V

X5R-CERM

X5R-CERM

0201

1 C2702

1UF

U2700

20%

6.3V

0201

CRITICAL
VDDIO_25M_A
32KHZ_A
VDDIO_25M_B
VDDIO_25M_C
25MHZ_A
25MHZ_B
X2
25MHZ_C
X1
VDD_RTC_OUT

11
6

Ground VDDIO of unused CLK


outputs for power savings

C2705
1

69 SYSCLK_CLK25M_X2

NO STUFF

5%
5%

69 SYSCLK_CLK25M_X2_R

1/20W
1

25V
NP0-C0G-CERM

MF

Y2705

201

25.000MHZ-12PF-20PPM

1M

GND

5%
1/20W
MF

C2706

SM-3.2X2.5MM

12PF
1

R2706

69

NC
NC

0201

CRITICAL

10

14

R2705

12PF

201

LPC_CLK33M_LPCPLUS

IN

PCH_CLK33M_PCIOUT

PCH_CLK33M_PCIIN

OUT

5%
1/20W
MF
201

internally ORed to
create VDD_RTC_OUT.

25 7

SYSCLK_CLK25M_SB

OUT

16 69

OUT

34 69

=PPVRTC_G3_OUT
1

1 C2710

10%
16V
X5R-CERM
0201

20%
6.3V

BKLT_PLT_RST_L

SSD_RESET_L

5%
1/20W
MF
201

5%
1/20W
MF
201

XDPPCH_PLTRST_L

OUT

23

PCA9557D_RESET_L

OUT

31

R2789
1K

5%
1/20W
MF
201

R2771

NP0-C0G-CERM

Buffered

=PP3V3_S0_RSTBUF

6 38

XDP

0201

25 7

OUT

100K

X5R

0201

65

OUT

R2772

R2770

NOTE: 30 PPM crystal required

5%

37

OUT

PLT_RST_BUF_L
1

0.1UF

1UF

SYSCLK_CLK25M_X1

AP_RESET_L

5%
1/20W
MF
201

scrub for layout optimization

SC70-HF

C2771 1

36

OUT

MC74VHC1G08

U2771 4

For SB RTC Power

THRM
PAD

=TBT_RESET_L

5%
1/20W
MF
201

CRITICAL
5

1
SYSCLK_CLK25M_TBT

33

R2788

R2793

=PP3V3_S0_RSTBUF

NC

15

OUT

MAKE_BASE=TRUE

16 69

OUT

SDCARD_PLT_RST_L

Buffered

SYSCLK_CLK32K_RTC

41

TBT_RESET_L

to reduce VBAT draw.


12

OUT

5%
1/20W
MF
201

16 69

25V

R2773
1

R2729
22

SMC_LRESET_L

5%
1/20W
MF
201

6 43 69

OUT

available ~3.3V power

TQFN

0201

69 18

R2782

+V3.3A should be first

SLG3NB148A

X5R

LPC_CLK33M_LPCPLUS_R

PLACE_NEAR=U1800.G45:2.54MM:5.1mm

VBAT and +V3.3A are

OUT

5%
1/20W
MF
201

17

C2722

16

C2724

IN

22

2
5%
1/20W
MF
201

41 69

R2726

PLACE_NEAR=U1800.E49:5.1mm

69 18

LPC_CLK33M_SMC

2
5%
1/20W
MF
201

3.3V S5

=PP3V3_S0_SYSCLKGEN

22

PLACE_NEAR=U1800.G51:5.1mm
69 18

R2727
3.42V G3Hot

6 43 69

R2783
33

=PP3V3_S5_SYSCLK
Coin-Cell & G3Hot:

OUT

MAKE_BASE=TRUE
5%
1/20W
MF
201

No Coin-Cell: 3.42V G3Hot (no RC)


7

LPCPLUS_RESET_L

VBAT (300-ohm & 10uF RC)

5%
1/20W
MF
201

U2780

74LVC1G07
SC70
2

NO STUFF

PCH S0 PWRGD

R2750

10%
16V
X5R-CERM
0201

5%

1/20W
MF

IN
IN

ALL_SYS_PWRGD

100K

CPU_RESET_L

5%
1/20W
MF
201

7 25

10%
16V
X5R-CERM
0201

DP_AUXIO_EN Inversion

MC74VHC1G08
SC70-HF
4

5
1

PM_S0_PGOOD

MC74VHC1G08

R2762

SC70-HF

U2760

SYS_PWROK_R

3.0K
1

3
3

PM_PCH_SYS_PWROK

5%
1/20W
MF
201

R2730
OUT

17 23 41
36 19 18 17 16 7

=PP3V3_S0_PCH_GPIO 1

PLACE_NEAR=U1800.M10:5.54mm

MF

42 41 36

64

C2739

SOT563

0.1UF

PM_PCH_PWROK

MAKE_BASE=TRUE

5%
1/20W
MF
201

PM_PCH_APWROK

OUT

17 25

OUT

17

1
23 16

IN

10%
16V
X5R-CERM
0201

S 2

22 20 7

41

GPIO Glitch Prevention


25 7

43 41 17 6

IN

23 19

IN

25 17

IN

A1
B1
A2
B2

Y2

OUT

16 69

R2795
10K

5%
1/20W
MF
2 201

XDP

TBT_PWR_EN

OUT

34

AUD_IPHS_SWITCH_EN

OUT

6 40

R2796
66 23 10

IN

XDP_DBRESET_L

PM_SYSRST_L

BI

1/20W

17 41
SYNC_MASTER=K21_MLB

SYNC_DATE=07/29/2011

PAGE TITLE

201
MF

Clock (CK505) and Chipset Support

5%

DRAWING NUMBER

NO STUFF

R2797

Apple Inc.

5%
1/16W
MF-LF
2 402

SILK_PART=SYS RESET

HDA_SDOUT_R
IPD = 9-50k

S 1

10%
16V
X5R-CERM
0201

GND

5%
1/20W
MF
2 201

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.


If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

=PP3V3_S0_SB_PM

0.1UF

Y1

1K

SPI_DESCRIPTOR_OVERRIDE_L

1 C2752

08

74LVC2G08GT

IN

1
2
5
6

IN

PCH Reset Button

=PP3V3_S3_PCH_GPIO

TBT_PWR_EN_PCH
LPC_PWRDWN_L
AUD_IPHS_SWITCH_EN_PCH
PM_PCH_PWROK

R2721

D 6

SOT563

2 G

16

SPI_DESCRIPTOR_OVERRIDE

SSM6N37FEAPE

5%
1/20W
MF
2 201

5%
1/20W
MF
2 201

Q2720

10K

U2752
SOT833

100K

SPI_DESCRIPTOR_OVERRIDE_LS5V

DP_AUXCH_ISOL

R2731

CRITICAL 8
VCC

R2720

=PP3V3R1V5_S0_PCH_VCCSUSHDA

1 NO STUFF

18 7

Q2720

SSM6N37FEAPE

SSM3K15FV

=PP5V_S0_PCH

PCH ME Disable Strap


OUT

SOD-VESM-HF

201

SMC_DELAYED_PWRGD

DP_AUXIO_EN

Q2730

1/20W

22 7

CRITICAL

5%

R2760

10K

5%
1/20W
MF
201

NO STUFF

R2761
0

PLACE_NEAR=U1800.P12:7mm

10 23

OUT

VTT voltage divider on CPU page

0.1UF

CPUIMVP_PGOOD

R2780

C2760

U2750
57

62 52 41 23

0.1UF

1K

201

=PP3V3_S5_PCHPWRGD

C2750

NC

G 5

=PP3V3_S0_SB_PM

10%
16V
X5R-CERM
0201

4 S

25 7

0.1UF

=PP3V3_S5_PCHPWRGD

C2780

5%
1/20W
MF
201

25 7

0
1

PLT_RST_CPU_BUF_L
MAKE_BASE=TRUE

NC

R2763

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

27 OF 109

SHEET

25 OF 73

1V5 S0 "PGOOD" for CPU

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPUs SM_DRAMRST# output from the SO-DIMMs when necessary.
7

=PP3V3_S5_CPU_VCCDDR

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW:

15 12 10 7

CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN

= (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

MEMVTT_EN

= (ISOLATE_CPU_MEM_L + PLT_RST_L)

=PP1V5_S3_CPU_VCCDDR

PM_MEM_PWRGD
1

R2822

10 17 66

10K

* PM_SLP_S3_L

5%
1/20W
MF
2 201

R28201

CRITICAL

Q2820

27.4K

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L


62 49 41 37 26 17

PM_SLP_S4_L

IN

DMB53D0UV

1%
1/20W
MF
201 2

CPUMEM_SLG:NO

PM_MEM_PWRGD_L

R2805

10K

P1V5_S0_DIV

5%
1/20W
MF
2 201

P1V5CPU_EN
26 7

OUT

=PP3V3_S3_MEMRESET

OUT

R28211

26 61

43.2K

Q2805

1%
1/20W
MF
201 2

D 6

SSM6N37FEAPE

R2801

SOT563

100K

5%
1/20W
MF
201 2

2 G

S 1

3 D

Q2805

CRITICAL

Q2820

DMB53D0UV

SOT-563

CPUMEM_SLG:NO
CPUMEM_SLG:NO

SOT-563

2 G

NO STUFF

C2820 1
1000PF

10%
16V
X7R-CERM 2
0201

P1V5CPU_EN_L
CPUMEM_SLG:NO

Q2800

D 3

SSM6N37FEAPE
SOT563

CPUMEM_SLG:NO

SSM6N37FEAPE
SOT563

CPUMEM_SLG:NO

R2890
0

5 G

S 4

4 S

G 5

1ISOLATE_CPU_MEM_L_R

PM_SLP_S3_L IN
CPUMEM_SLG:NO

5%
1/20W
MF
201

17 26 41 62

R2810
10K

26 7

5%
1/20W
MF
2 201
26 7

MEMVTT_EN

=PP5V_S3_MEMRESET
CPUMEM_SLG:NO
CPUMEM_SLG:NO

Q2810

CPUMEM_SLG:NO

R28151

6.3V
X5R
201

D 6

2 G

CPUMEM_SLG:NO

3 D

SSM6N37FEAPE

CPUMEM_SLG:NO

PLT_RESET_L
ISOLATE_CPU_MEM_L

IN

PM_SLP_S3_L

41 37 26 17
62 49

IN

PM_SLP_S4_L

S3_EN

26 10

IN

=MEM_RESET_L

RST_IN*

MEMVTT_EN

OUT

8 26

S0_EN

VDDIO_EN

P1V5CPU_EN

OUT

26 61

RST_OUT*

MEM_RESET_LOUT

Ensures CKE signals are held low in S3

R28501
10

18 25 26
26 7

=PP5V_S3_MEMRESET
100K

Q2815

0402

MEMRESET_ISOL_LS5V_L

SSM6N37FEAPE
SOT563

1K

10%
16V

Q2850

0201

PM_SLP_S3_L

PM_SLP_S4_L

CPU_MEM_RESET_L

CPU_MEM_RESET_L

to

0 (*)

S0

CPU_MEM_RESET_L

to
S3

ISOLATE_CPU_MEM_L

PLT_RESET_L

MEM_RESET_L

MEMVTT_EN

D 3

SSM6N37FEAPE
OUT

S 1

26 27 28 29 30

IN

NO STUFF

C2851 1
1000PF

SOT563

5 G

Step

2 G

0.1UF

56 8

S0

D 6

SOT563

VTTCLAMP_EN

C2816 1

X5R-CERM

MEM_RESET_L

3 D

MAKE_BASE=TRUE

CPU_MEM_RESET_L
4

IN

=MEM_RESET_L

R2816

Q2850

SSM6N37FEAPE

5%
1/20W
MF
201 2

5%
1/20W
MF
2 201

31

26 10

=PP1V5_S3_MEMRESET

CPUMEM_SLG:NO

10%
16V
X7R-CERM

60mW max power

VTTCLAMP_L
IN

R28511

0.047UF

75mA max load @ 0.75V

5%
1/10W
MF-LF
603 2

NO STUFF
C2817 1

=PPVTT_S0_VTTCLAMP

26 27 28 29 30

G 5

PLT_RESET_L

1 S

6 D

4 S

THRM
GND PAD

SOT563

S 1

VTT_EN
9 ISOL*

IN

Q2810

MEMVTT Clamp

TQFN
1 S0_READY

26 23

SSM6N37FEAPE

SOT563

2 G

D 6

IN

G 2

SOT563

U2800

SLG4AP022

Q2815

SSM6N37FEAPE

VDD

62 41 26 17

S 1

MEMVTT_EN_L

Q2800

0.1UF
10%

26 25 18

5%
1/20W
MF
201 2

CPUMEM_SLG:NO

CPUMEM_SLG:YES

C2800 1

8 26

SOT563

100K

5%
1/20W
MF
201 2

CPUMEM_SLG:YES
OUT

SSM6N37FEAPE

R28021

100K

=PP3V3_S3_MEMRESET

10

ISOLATE_CPU_MEM_L

IN

11

26 23

10%
16V
X7R-CERM 2
0201

S 4

=DDRVTT_EN

P1V5CPU_EN

SYNC_MASTER=J13_MLB_NON_POR

CPU Memory S3 Support


DRAWING NUMBER

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

Apple Inc.

Rails will power-up as if from S3, but MEM_RESET_L will not properly assert.

NOTICE OF PROPRIETARY PROPERTY:

Software

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

051-9277

SIZE

REVISION

2.8.0

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition.

SYNC_DATE=11/10/2011

PAGE TITLE

BRANCH
PAGE

28 OF 109

SHEET

26 OF 73

MEM_A_CS_L<1> H1

67 32 28 27 11

MEM_A_CS_L<0> H2

67 32 28 27 11
67 32 28 27 11
67 32 28 27 11

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

F3
G3
H3

81
82

CS1*
CS0*

K7

MEM_A_A<13>

N3
N7

A13
A15

MEM_A_BA<0>

J7
J2

67 32 28 27 11

MEM_A_BA<1>

67 32 28 27 11

MEM_A_BA<2>

67 32 28 27 11

MEM_A_A<14>

67 32 28 27 11

MEM_A_A<15>

DQS* D3 MEM_A_DQS_N<1>

A11
A12/BC*

DM/TDQS B7
NF_TDQS* A7

A14

K8

BA0
BA1

A3

J3

BA2

79
NC 80

67 32 28 27 11

MEM_A_CLK_P<0>F7

CK

MEM_A_CLK_N<0>G7

CK*

67 32 28 27 11

MEM_A_CKE<0>

67 32 28 27 11

MEM_A_CKE<1>

G9 CKE0
F9 CKE1

67 32 28 27 11

MEM_A_CS_L<1> H1

CS1*

67 32 28 27 11

MEM_A_CS_L<0> H2

CS0*

67 32 28 27 11

MEM_A_RAS_L F3

67 32 28 27 11

MEM_A_CAS_L G3

RAS*
CAS*

67 32 28 27 11

MEM_A_WE_L

67 32 28 27 11

MEM_A_A<7>

M2

67 32 28 27 11

MEM_A_A<8>

67 32 28 27 11

MEM_A_A<9>

N8
M3

67 32 28 27 11

MEM_A_A<10>

H7

67 32 28 27 11

MEM_A_A<11>

67 32 28 27 11

MEM_A_A<12>

M7
K7

MEM_A_A<13>

N3

11 67

11 67

11 67

67 32 28 27 11

NC

67 32 28 27 11

MEM_A_A<14>

67 32 28 27 11

MEM_A_A<15>

WE*

B2

N9

L9
N1

VSS

NF_DQ5 E8 MEM_A_DQ<16>
NF_DQ6 D2 MEM_A_DQ<18>
NF_DQ7 E7 MEM_A_DQ<21>

A11
A12/BC*
A13

N7
J7

A14
BA0

MEM_A_BA<1>

J2
K8

67 32 28 27 11

MEM_A_BA<2>

J3

81

67 32 28 27 11

MEM_A_CLK_P<0>F7

CK

82

67 32 28 27 11

MEM_A_CLK_N<0>G7

CK*

67 32 28 27 11

MEM_A_CKE<0>

79
NC 80
81

67 32 28 27 11
67 32 28 27 11

MEM_A_A<0>
MEM_A_A<1>

K3
L7

67 32 28 27 11

MEM_A_A<2>

L3

A1
A2

11 67

67 32 28 27 11

MEM_A_A<3>

11 67

67 32 28 27 11

MEM_A_A<4>

K2
L8

A3
A4

11 67

67 32 28 27 11

MEM_A_A<5>

67 32 28 27 11

MEM_A_A<6>

L2
M8

A5

11 67
11 67

67 32 28 27 11

MEM_A_A<7>

M2

67 32 28 27 11

MEM_A_A<8>

67 32 28 27 11

MEM_A_A<9>

N8
M3

67 32 28 27 11

MEM_A_A<10>

H7

67 32 28 27 11

MEM_A_A<11>

67 32 28 27 11

MEM_A_A<12>

M7
K7

MEM_A_A<13>

N3

67 32 28 27 11

MEM_A_A<14>

67 32 28 27 11

MEM_A_A<15>

A6
A7

E9

C1
E2

B9

M9

K9
M1

MT41K1G4

DQ0 B3 MEM_A_DQ<28>
DQ1 C7 MEM_A_DQ<26>
DQ2 C2 MEM_A_DQ<27>
DQ3 C8 MEM_A_DQ<30>
NF_DQ4 E3 MEM_A_DQ<25>
NF_DQ5 E8 MEM_A_DQ<24>
NF_DQ6 D2 MEM_A_DQ<29>
NF_DQ7 E7 MEM_A_DQ<31>

11 67

11 67
11 67
11 67
11 67
11 67
11 67
11 67

A8
A9
A10/AP
A11
A12/BC*
A13

N7
J7

A14
BA0

DQS C3 MEM_A_DQS_P<3>

11 67

DQS* D3 MEM_A_DQS_N<3>

11 67

DM/TDQS B7
NF_TDQS* A7 NC

A15

67 32 28 27 11

MEM_A_BA<0>
MEM_A_BA<1>

J2
K8

67 32 28 27 11

MEM_A_BA<2>

J3

67 32 28 27 11

MEM_A_CLK_P<0>F7

CK

67 32 28 27 11

MEM_A_CLK_N<0>G7

CK*

67 32 28 27 11

MEM_A_CKE<0>

A3 NC

BA1
BA2

79
NC 80
81

67 32 28 27 11

G9 CKE0
MEM_A_CKE<1> F9 CKE1

MEM_A_CS_L<1> H1

CS1*

67 32 28 27 11

MEM_A_CS_L<1> H1

CS1*

MEM_A_CS_L<0>

H2

CS0*

67 32 28 27 11

MEM_A_CS_L<0> H2

CS0*

MEM_A_RAS_L

F3

RAS*

67 32 28 27 11

MEM_A_RAS_L

F3

RAS*

67 32 28 27 11

MEM_A_CAS_L

CAS*
WE*

MEM_A_CAS_L

67 32 28 27 11

G3
H3

67 32 28 27 11

MEM_A_WE_L

67 32 28 27 11

MEM_A_WE_L

G3
H3

CAS*
WE*

VSS

K1

G2
G8

D7

A0

67 32 28 27 11

82

VSSQ

A2
A9

E1

J8
VREFCA

ZQ0
ZQ1

67 32 28 27 11

67 32 28 27 11

A3 NC

MEM_A_ZQ7 H9

67 32 28 27 11

11 67

BA1
BA2

201

11 67

DQS* D3 MEM_A_DQS_N<2>

NF_TDQS* A7 NC

G9 CKE0
MEM_A_CKE<1> F9 CKE1

1/20W

RESET*

11 67

11 67

DM/TDQS B7

1%

N2

MEM_A_ZQ3 H8

11 67

DQS C3 MEM_A_DQS_P<2>

A15

MEM_A_BA<0>

VREFDQ

E2
E9

C1

B9

M9

G8
K1

G2

A9
D7

A2

J8

K9
M1

DQ2 C2 MEM_A_DQ<23>
DQ3 C8 MEM_A_DQ<20>
NF_DQ4 E3 MEM_A_DQ<22>

A9
A10/AP

67 32 28 27 11

WE*

DQ0 B3 MEM_A_DQ<19>
DQ1 C7 MEM_A_DQ<17>

A8

67 32 28 27 11

NC

67 32 28 27 11

VSSQ
L1

J1
J9

F8

D8
F2

VSS

H3

A6
A7

MF

MEM_RESET_L
2

512MX8-4GBIT-DDR3-1600

L2
M8

A5

MEM_A_A<6>

11 67

67 32 28 27 11

CAS*

E1

E9

E2

B9
C1

M1
M9

K9

G8
K1

D7
G2

A9

A2

A10/AP

67 32 28 27 11

RAS*

A8
B1

J8

E2
E9

B9
C1

M1
M9

K9

G8
K1

G2

A9
D7

A2

CK
CK*

A1

E1

MEM_A_A<12>

67 32 28 27 11

NC 80

F9 CKE1

67 32 28 27 11

67 32 28 27 11

67 32 28 27 11

79

MEM_A_CKE<0> G9 CKE0

MEM_A_CKE<1>

H7
M7

D9

67 32 28 27 11
67 32 28 27 11

MEM_A_A<11>

MEM_A_A<5>

67 32 28 27 11

11 67

240

82

VSSQ

VSS

VSSQ
D1
D9

MEM_A_CLK_N<0>G7

BA2

MEM_A_A<10>

67 32 28 27 11

67 32 28 27 11

11 67

30 29 28 27 26

R2930 1

20%
4V
CERM-X5R-1
201

OMIT_TABLE

C9

67 32 28 27 11

A3 NC

67 32 28 27 11

DQS C3 MEM_A_DQS_P<1>

MEM_A_A<4>

A3
A4

U2930

0.47UF

FBGA-9P5X11P65-COMBO

B2
B8

67 32 28 27 11

MEM_A_CLK_P<0>F7

NF_TDQS* A7 NC

BA1

M3

67 32 28 27 11

K2
L8

ODT1

N9

K8
J3

MEM_A_A<9>

MEM_A_A<3>

ODT0

MEM_A_ODT<1> F1

N1

MEM_A_BA<2>

67 32 28 27 11

11 67

A8
A9

67 32 28 27 11

11 67

MEM_A_ODT<0> G1

C2932

VDDQ

L1
L9

MEM_A_BA<1>

67 32 28 27 11

MEM_A_A<8>

A7

A2

VDD

J9

67 32 28 27 11

67 32 28 27 11

M2
N8

NF_DQ5 E8 MEM_A_DQ<13>
NF_DQ6 D2 MEM_A_DQ<11>
NF_DQ7 E7 MEM_A_DQ<9>

L3

=PP1V5_S3_MEM_A

F8
J1

A15
BA0

MEM_A_A<7>

A5
A6

MEM_A_A<2>

F2

A14

J7
J2

MEM_A_BA<0>

67 32 28 27 11

A4

67 32 28 27 11

20%
4V
CERM-X5R-1
201

32 28 27 7

B1
D8

N7

MEM_A_A<15>

M8

MEM_A_A<4>

11 67

0.47UF
2

A1
A8

MEM_A_A<14>

67 32 28 27 11

L8
L2

MEM_A_A<6>

11 67

DM/TDQS B7

A13

67 32 28 27 11

67 32 28 27 11

J8

A12/BC*

MEM_A_A<5>

67 32 28 27 11

11 67

ZQ0
MF 1% 1/20W 201 MEM_A_ZQ6 H9 ZQ1
K3 A0
28 27 11 MEM_A_A<0>
L7 A1
28 27 11 MEM_A_A<1>

D9

K7
N3

67 32 28 27 11

67 32 28 27 11
11 67

11 67

MEM_A_A<3>

67 32

RESET*

D1

MEM_A_A<13>

67 32 28 27 11
11 67

67 32
11 67

N2

MEM_A_ZQ2 H8

67 32 28 27 11

B8
C9

MEM_A_A<12>

A2
A3

11 67

MEM_RESET_L
2

C2931

0.47UF
20%
4V
CERM-X5R-1
201

67 32 28 27 11

B2

67 32 28 27 11
67 32 28 27 11

DQS* D3 MEM_A_DQS_N<0>

A1

L3
K2

DQ0 B3 MEM_A_DQ<8>
DQ1 C7 MEM_A_DQ<14>
DQ2 C2 MEM_A_DQ<15>
DQ3 C8 MEM_A_DQ<12>
NF_DQ4 E3 MEM_A_DQ<10>

240

C2930

0.47UF
20%
4V
CERM-X5R-1
201

PP0V75_S3_MEM_VREFDQ_A

OMIT_TABLE

N9

M7

L7

MEM_A_A<2>

11 67

30 29 28 27 26

R2920 1

U2920

67 31 28 27

FBGA-9P5X11P65-COMBO

N1

MEM_A_A<11>

A10/AP
A11

MEM_A_A<1>

67 32 28 27 11

11 67
11 67

201 MEM_A_ZQ5

ODT1

512MX8-4GBIT-DDR3-1600

67 32 28 27 11

A9

67 32 28 27 11

11 67

1/20W

ODT0

MEM_A_ODT<1> F1

C2922

VDDQ

L1
L9

MEM_A_A<10>

MEM_A_A<0>

1%

MEM_A_ODT<0> G1

67 32 28 27 11

=PP1V5_S3_MEM_A

VDD

J1
J9

67 32 28 27 11

DQS C3 MEM_A_DQS_P<0>

67 32 28 27 11

H9 ZQ1
K3 A0

MF

F8

67 32 28 27 11

M3
H7

ZQ0

D8
F2

N8

RESET*

20%
4V
CERM-X5R-1
201

PP0V75_S3_MEM_VREFCA_A

67 31 28 27

32 28 27 7

A1
A8

MEM_A_A<8>
MEM_A_A<9>

A7
A8

N2

MEM_A_ZQ1 H8

D9

67 32 28 27 11

NF_DQ6 D2 MEM_A_DQ<6>
NF_DQ7 E7 MEM_A_DQ<0>

C2921
0.47UF

20%
4V
CERM-X5R-1
201

67 32 28 27 11

C9
D1

MEM_A_A<7>

DQ3 C8 MEM_A_DQ<3>
NF_DQ4 E3 MEM_A_DQ<5>
NF_DQ5 E8 MEM_A_DQ<1>

D1

67 32 28 27 11

DQ0 B3 MEM_A_DQ<7>
DQ1 C7 MEM_A_DQ<4>
DQ2 C2 MEM_A_DQ<2>

MEM_RESET_L

240

0.47UF

FBGA-9P5X11P65-COMBO

ODT0
ODT1

B8

A6

30 29 28 27 26

R2910 1

MEM_A_ODT<1> F1

C2920
2

OMIT_TABLE

B2

M8
M2

MEM_A_ODT<0> G1

67 32 28 27 11

U2910

20%
4V
CERM-X5R-1
201

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

0.47UF

VDDQ

N9

MEM_A_A<6>

67 32 28 27 11

C2912

MT41K1G4

67 32 28 27 11

OMIT_TABLE

VDD

512MX8-4GBIT-DDR3-1600

MEM_A_A<5>

A4
A5

L9
N1

67 32 28 27 11

L8
L2

20%
4V
CERM-X5R-1
201

L1

MEM_A_A<4>

0.47UF
2

J1
J9

67 32 28 27 11

20%
4V
CERM-X5R-1
201

F2
F8

A3

0.47UF

C2911

D8

K2

MEM_A_ZQ0

A8
B1

MEM_A_A<3>

67 32 28 27 11

=PP1V5_S3_MEM_A
67 31 28 27

C2910

FBGA-9P5X11P65-COMBO

RESET*

67 32 28 27 11

1%

67 32 28 27 11

N2

67 32 28 27 11

MF

MEM_RESET_L

20%
4V
CERM-X5R-1
201

VDDQ

U2900

MEM_A_ODT<0> G1 ODT0
MEM_A_ODT<1> F1 ODT1

H8 ZQ0
1/20W 201 MEM_A_ZQ4 H9
ZQ1
K3 A0
MEM_A_A<0>
L7 A1
MEM_A_A<1>
L3 A2
MEM_A_A<2>

R2900 1

VDD

B8
C9

240

512MX8-4GBIT-DDR3-1600

67 32 28 27 11
67 32 28 27 11

20%
4V
CERM-X5R-1
201

32 28 27 7

0.47UF

A1

C2902

MT41K1G4

0.47UF

20%
4V
CERM-X5R-1
201

30 29 28 27 26

VREFDQ

0.47UF

C2901

VREFCA

C2900

E1

67 31 28

MT41K1G4

PP0V75_S3_MEM_VREFCA_A

27 PP0V75_S3_MEM_VREFDQ_A

VREFCA

=PP1V5_S3_MEM_A

VREFCA

32 28 27 7

VREFDQ

PP0V75_S3_MEM_VREFDQ_A

VREFDQ

67 31 28 27

67 31 28 27
67 31 28 27

B1

PP0V75_S3_MEM_VREFCA_A

67 31 28 27

A14/A15 FOR 2G/4G MONO ONLY


CS1 IS FOR 2G DDP RANK CONTROL

240

R2901 1
MF

240

R2911 1
MF

1%

1%

240

R2921 1
MF

1%

2
1/20W

2
1/20W

MEM_A_ZQ4

MEM_A_ZQ5

27

201

2
1/20W

27

201

MEM_A_ZQ6 27

SYNC_MASTER=K21_MLB

201

SYNC_DATE=07/28/2011

PAGE TITLE

DDR3 DRAM CHANNEL A (0-31)


240

R2931 1
MF

1%

2
1/20W

DRAWING NUMBER

MEM_A_ZQ7 27

Apple Inc.

201

051-9277
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0
BRANCH
PAGE

29 OF 109
SHEET

27 OF 73

SIZE

J2

MEM_A_BA<1>

67 32 28 27 11

MEM_A_BA<2>

K8
J3

67 32 28 27 11

MEM_A_CLK_P<0>F7

67 32 28 27 11

MEM_A_CLK_N<0>G7

67 32 28 27 11

MEM_A_CKE<0>

67 32 28 27 11

MEM_A_CKE<1>

A3

BA1
BA2

67 32 28 27 11
11 67

11 67

MEM_A_A<9>

M3

67 32 28 27 11

MEM_A_A<10>

67 32 28 27 11

MEM_A_A<11>

H7
M7

67 32 28 27 11

MEM_A_A<13>
MEM_A_A<14>

67 32 28 27 11

MEM_A_A<15>

81
82

G9 CKE0
F9 CKE1

67 32 28 27 11

J3

BA2

67 32 28 27 11

MEM_A_CLK_P<0>F7

67 32 28 27 11

MEM_A_WE_L

H3

CAS*
WE*

B2

N9

L9
N1

79
NC 80
81
82

CS1*

H2
MEM_A_CS_L<0>

CS0*

67 32 28 27 11

MEM_A_RAS_L

67 32 28 27 11

MEM_A_CAS_L

F3
G3

RAS*
CAS*

67 32 28 27 11

MEM_A_WE_L

H3

WE*

MEM_A_A<7>

M2

67 32 28 27 11

MEM_A_A<8>

VSS

A5
A6
A7

67 32 28 27 11

MEM_A_A<9>

N8
M3

67 32 28 27 11

MEM_A_A<10>

H7

A9
A10/AP

67 32 28 27 11

MEM_A_A<11>

67 32 28 27 11

MEM_A_A<12>

M7
K7

A11
A12/BC*

67 32 28 27 11

MEM_A_A<13>
MEM_A_A<14>

N3
N7

A13

67 32 28 27 11

MEM_A_A<15>

J7

A15
BA0

67 32 28 27 11
67 32 28 27 11

MEM_A_BA<0>

67 32 28 27 11

MEM_A_BA<1>

J2
K8
J3

67 32 28 27 11

MEM_A_BA<2>

67 32 28 27 11

MEM_A_CLK_P<0>F7

67 32 28 27 11

MEM_A_CLK_N<0>G7

11 67

67 32 28 27 11

MEM_A_A<2>

11 67

67 32 28 27 11

MEM_A_A<3>

L3
K2

67 32 28 27 11

MEM_A_A<4>

L8

67 32 28 27 11

MEM_A_A<5>

11 67

67 32 28 27 11

MEM_A_A<6>

L2
M8

11 67

67 32 28 27 11

MEM_A_A<7>

M2

67 32 28 27 11

MEM_A_A<8>

67 32 28 27 11

MEM_A_A<9>

N8
M3

11 67

DQS C3 MEM_A_DQS_P<6>

11 67

DQS* D3 MEM_A_DQS_N<6>

11 67

DM/TDQS B7

NC

A3 NC

BA1
BA2

79
NC 80
81

CK
CK*

67 32 28 27 11

MEM_A_A<12> K7

A11
A12/BC*

MEM_A_A<13> N3

A13

N7

A14

67 32 28 27 11

MEM_A_A<15> J7

A15

67 32 28 27 11

MEM_A_BA<0> J2

BA0

67 32 28 27 11

MEM_A_BA<1> K8

MEM_A_A<14>

67 32 28 27 11

MEM_A_BA<2> J3

BA1
BA2

67 32 28 27 11

F7
MEM_A_CLK_P<0>

CK

67 32 28 27 11

G7
MEM_A_CLK_N<0>

CK*

CS1*

67 32 28 27 11

H1
MEM_A_CS_L<1>

CS1*

CS0*

67 32 28 27 11

H2
MEM_A_CS_L<0>

CS0*

MEM_A_CS_L<1> H1

67 32 28 27 11

MEM_A_CS_L<0> H2

67 32 28 27 11

MEM_A_RAS_L

F3

RAS*

67 32 28 27 11

MEM_A_CAS_L

67 32 28 27 11

MEM_A_WE_L

G3
H3

67 32 28 27 11

CAS*
WE*

VSSQ

VSS

E9

E2

B9
C1

M9

M1

G8

D7
G2

K1
K9

NF_DQ5 E8 MEM_A_DQ<61>
NF_DQ6 D2 MEM_A_DQ<62>
NF_DQ7 E7 MEM_A_DQ<60>

A9
A10/AP

MEM_A_A<10> H7
MEM_A_A<11> M7

67 32 28 27 11

DQ0 B3 MEM_A_DQ<59>
DQ1 C7 MEM_A_DQ<57>
DQ2 C2 MEM_A_DQ<63>
DQ3 C8 MEM_A_DQ<56>
NF_DQ4 E3 MEM_A_DQ<58>

11 67
11 67
11 67
11 67
11 67
11 67
11 67
11 67

A8

67 32 28 27 11

67 32 28 27 11

A9

A6
A7

MEM_A_CKE<0> G9 CKE0
MEM_A_CKE<1> F9 CKE1

67 32 28 27 11

A2

J8

E1
A5

67 32 28 27 11

82

MEM_A_CKE<0> G9

A3
A4

67 32 28 27 11

67 32 28 27 11

NF_TDQS* A7 NC

A14

A2

MT41K1G4

MT41K1G4

NF_DQ5 E8 MEM_A_DQ<53>
NF_DQ6 D2 MEM_A_DQ<54>
NF_DQ7 E7 MEM_A_DQ<49>

MEM_A_ZQ11

11 67

A8

CKE0
MEM_A_CKE<1> F9 CKE1

VREFCA

VREFDQ

E2
E9

C1

B9

M9

K9
M1

G8
K1

G2

A9
D7

A2

E1

J8
VREFCA

A3
A4

512MX8-4GBIT-DDR3-1600

MEM_A_A<6>

67 32 28 27 11

67 32 28 27 11

F9 CKE1

MEM_A_CS_L<1> H1

NC
NC

VREFDQ

E9

E2

B9
C1

M1
M9

K9

G8
K1

D7
G2

A9

A2

J8

A3

VSSQ
L1

J1
J9

F8

D8
F2

A8
B1

A1

VSS

11 67

MEM_A_CKE<0> G9 CKE0

MEM_A_CKE<1>

A1

MEM_A_CAS_L

RAS*

DQS* D3 MEM_A_DQS_N<5>

NF_TDQS* A7 NC

67 32 28 27 11

L2
M8

11 67

11 67

CK
MEM_A_CLK_N<0>G7 CK*

D9

67 32 28 27 11

F3
G3

A15

MEM_A_A<5>

11 67

DQS C3 MEM_A_DQS_P<5>

DM/TDQS B7

A14

K8

67 32 28 27 11

D1

MEM_A_RAS_L

A13

J7
J2

MEM_A_BA<1>

67 32 28 27 11
67 32 28 27 11

N3
N7

MEM_A_BA<2>

67 32 28 27 11

CS1*
CS0*

A11
A12/BC*

67 32 28 27 11

67 32 28 27 11

B8
C9

67 32 28 27 11

A10/AP

67 32 28 27 11

67 32 28 27 11

MEM_A_CS_L<1> H1
MEM_A_CS_L<0> H2

MEM_A_BA<0>

K7

A8
A9

BA0
BA1

NC 80

CK
CK*

MEM_A_A<12>

67 32 28 27 11

67 32 28 27 11

79

E1

67 32 28 27 11

67 32 28 27 11

NC
NC

MEM_A_A<8>

A7

67 32 28 27 11

11 67

A2

67 32

67 32 28 27 11

MEM_A_RAS_L

F3

RAS*

67 32 28 27 11

MEM_A_CAS_L

67 32 28 27 11

MEM_A_WE_L

G3
H3

CAS*
WE*

DQS C3 MEM_A_DQS_P<7>

11 67

DQS* D3 MEM_A_DQS_N<7>

11 67

DM/TDQS B7
NF_TDQS* A7

NC

A3

NC
NC

79
NC 80
81
82

VSSQ

VSS

VSSQ
D9

MEM_A_BA<0>

67 32 28 27 11

M2
N8

L8

67 32

11 67

C9
D1

67 32 28 27 11

MEM_A_A<7>

L3
K2

MEM_A_A<4>

11 67

RESET*

H8 ZQ0
MEM_A_ZQ15 H9 ZQ1
MF 1% 1/20W
201
K3 A0
28 27 11 MEM_A_A<0>
L7 A1
28 27 11 MEM_A_A<1>

R3030 1

DQ0 B3 MEM_A_DQ<50>
DQ1 C7 MEM_A_DQ<51>
DQ2 C2 MEM_A_DQ<55>
DQ3 C8 MEM_A_DQ<48>
NF_DQ4 E3 MEM_A_DQ<52>

240

MEM_RESET_L N2

20%
4V
CERM-X5R-1
201

OMIT_TABLE

B8

NF_TDQS* A7 NC

67 32 28 27 11

11 67

DQS* D3 MEM_A_DQS_N<4>

A15
BA0

M8

MEM_A_A<3>

ODT1

67 32 28 27 11

30 29 28 27 26

0.47UF

FBGA-9P5X11P65-COMBO

B2

A14

MEM_A_A<15>

MEM_A_A<6>

NF_DQ5 E8 MEM_A_DQ<40>
NF_DQ6 D2 MEM_A_DQ<47>
NF_DQ7 E7 MEM_A_DQ<42>

MEM_A_A<2>

67 32 28 27 11

ODT0

F1
MEM_A_ODT<1>

N1
N9

N7
J7

MEM_A_A<14>

67 32 28 27 11

A5
A6

67 32 28 27 11
67 32 28 27 11

11 67
11 67

MEM_A_ODT<0> G1

C3032

VDDQ

U3030

OMIT_TABLE
67 32 28 27 11

=PP1V5_S3_MEM_A

VDD

L9

MEM_A_A<13>

DM/TDQS B7

67 32 28 27 11

A12/BC*
A13

MEM_A_A<5>

A4

11 67

J9
L1

A10/AP
A11

K7
N3

67 32 28 27 11

67 32 28 27 11
11 67

L8
L2

67 32 28 27

MEM_A_ZQ10

20%
4V
CERM-X5R-1
201

J1

M7

MEM_A_A<12>

MEM_A_A<4>

A2
A3

1%

67 32 28 27
11 67

RESET*

0.47UF

32 28 27 7

F2
F8

MEM_A_A<11>

67 32 28 27 11

MEM_A_A<3>

67 32 28 27 11
11 67

L3
K2

MF
11 67

ODT1

H8 ZQ0
1/20W 201 MEM_A_ZQ14 H9
ZQ1
K3 A0
11 MEM_A_A<0>
L7 A1
11 MEM_A_A<1>
2

20%
4V
CERM-X5R-1
201

D8

MEM_A_A<10>

67 32 28 27 11

VREFDQ

E2
E9

B9
C1

M1
M9

K9

G8
K1

G2

A9
D7

A2

67 32 28 27 11

A9

67 32 28 27 11
11 67

DQS C3 MEM_A_DQS_P<4>

M3
H7

67 32 28 27 11

11 67

MEM_A_A<2>

DQ0 B3 MEM_A_DQ<46>
DQ1 C7 MEM_A_DQ<41>
DQ2 C2 MEM_A_DQ<43>
DQ3 C8 MEM_A_DQ<44>
NF_DQ4 E3 MEM_A_DQ<45>

N2

C3031

0.47UF

FBGA-9P5X11P65-COMBO

ODT0

A8
B1

MEM_A_A<9>

67 32 28 27 11

A0
A1

240

R3020 1

MEM_RESET_L

U3020

C3030

0.47UF
20%
4V
CERM-X5R-1
201

PP0V75_S3_MEM_VREFDQ_A

67 31 28 27

A1

67 32 28 27 11

A7
A8

L7

67 32 28 27 11

30 29 28 27 26

MEM_A_ODT<1> F1

C3022

D9

N8

K3

MEM_A_ODT<0> G1

VDDQ

D1

MEM_A_A<8>

NF_DQ7 E7 MEM_A_DQ<32>

MEM_A_A<0>
MEM_A_A<1>

11 67

67 32 28 27 11

VDD

B8
C9

MEM_A_A<7>

67 32 28 27 11

A6

1/20W

67 32 28 27 11

=PP1V5_S3_MEM_A

B2

67 32 28 27 11

M8
M2

DQ3 C8 MEM_A_DQ<35>
NF_DQ4 E3 MEM_A_DQ<36>
NF_DQ5 E8 MEM_A_DQ<37>
NF_DQ6 D2 MEM_A_DQ<38>

1%

67 32 28 27 11
11 67

20%
4V
CERM-X5R-1
201

OMIT_TABLE

FBGA-9P5X11P65-COMBO

H8 ZQ0
H9 ZQ1

N9

MEM_A_A<6>

A4
A5

MF
201

11 67

MEM_A_ZQ9
MEM_A_ZQ13

0.47UF

N1

67 32 28 27 11

A3

DQ0 B3 MEM_A_DQ<39>
DQ1 C7 MEM_A_DQ<33>
DQ2 C2 MEM_A_DQ<34>

20%
4V
CERM-X5R-1
201

C3021

512MX8-4GBIT-DDR3-1600

L2

MEM_A_A<3>

R3010 1

0.47UF

32 28 27 7

L1
L9

K2
L8

MEM_A_A<5>

RESET*

240

20%
4V
CERM-X5R-1
201

J1
J9

MEM_A_A<4>

67 32 28 27 11

MEM_RESET_L N2

30 29 28 27 26

C3020

0.47UF

F8

67 32 28 27 11

67 32 28 27 11

ODT0
ODT1

PP0V75_S3_MEM_VREFDQ_A

D8
F2

MEM_A_A<2>

MEM_A_ODT<1> F1

67 31 28 27

B1

67 32 28 27 11

MEM_A_ODT<0> G1

67 32 28 27 11

C3012

PP0V75_S3_MEM_VREFCA_A

67 31 28 27

A1
A8

MEM_A_A<1>

RESET*

67 32 28 27 11

U3010

PP0V75_S3_MEM_VREFCA_A

D9

MEM_A_A<0>

67 32 28 27 11

FBGA-9P5X11P65-COMBO

VDDQ

C9
D1

67 32 28 27 11

VDD

B8

201

MEM_A_ZQ12

20%
4V
CERM-X5R-1
201

B2

1/20W

0.47UF

20%
4V
CERM-X5R-1
201

N9

H8 ZQ0
H9 ZQ1
K3 A0
L7 A1
L3 A2

OMIT_TABLE

0.47UF

67 31 28 27

=PP1V5_S3_MEM_A

MT41K1G4

1%

N2

MEM_A_ZQ8

512MX8-4GBIT-DDR3-1600

MF

MEM_RESET_L
2

20%
4V
CERM-X5R-1
201

C3011

L9
N1

240

VDDQ

C3010

L1

30 29 28 27 26

0.47UF

J1
J9

ODT1

C3002

32 28 27 7

F2
F8

ODT0

MEM_A_ODT<1> F1

PP0V75_S3_MEM_VREFDQ_A

D8

MEM_A_ODT<0> G1

PP0V75_S3_MEM_VREFCA_A

A8
B1

67 32 28 27 11

VDD

U3000

67 31 28 27

67 31 28 27

=PP1V5_S3_MEM_A

MT41K1G4

512MX8-4GBIT-DDR3-1600

20%
4V
CERM-X5R-1
201

VREFDQ

67 32 28 27 11

R3000 1

0.47UF

20%
4V
CERM-X5R-1
201

J8

C3001

0.47UF

32 28 27 7

VREFCA

C3000

E1

PP0V75_S3_MEM_VREFDQ_A

67 31 28 27

VREFCA

PP0V75_S3_MEM_VREFCA_A

67 31 28 27

A14/A15 FOR 2G/4G MONO ONLY


CS1 IS FOR 2G DDP RANK CONTROL

240

R3001 1
MF

240

R3011 1
MF

1%

240

R3021 1

1%

MF

1%

2
1/20W

2
1/20W

2
1/20W

MEM_A_ZQ12 28
201

MEM_A_ZQ13 28
201

MEM_A_ZQ14 28
201

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

PAGE TITLE
240

R3031 1
MF

1%

2
1/20W

DDR3 DRAM CHANNEL A (32-63)

MEM_A_ZQ15 28

DRAWING NUMBER

201

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

30 OF 109

SHEET

28 OF 73

67 32 30 29 11

MEM_B_CLK_P<0>F7

67 32 30 29 11

MEM_B_CLK_N<0>G7

67 32 30 29 11
67 32 30 29 11

67 32 30 29 11

MEM_B_RAS_L

67 32 30 29 11

MEM_B_CAS_L

F3
G3

67 32 30 29 11

MEM_B_WE_L

H3

MEM_B_A<9>

M3

67 32 30 29 11

MEM_B_A<10>

67 32 30 29 11

MEM_B_A<11>

H7
M7

MEM_B_A<12>

67 32 30 29 11

MEM_B_A<13>

67 32 30 29 11
67 32 30 29 11

NC
NC

MEM_B_A<14>

81
82

CS1*
CS0*

WE*

B2

N9

L9
N1

N3
N7

A13
A15

MEM_B_BA<0>
MEM_B_BA<1>

K8

BA0
BA1

67 32 30 29 11

MEM_B_BA<2>

J3

BA2

67 32 30 29 11

MEM_B_CLK_P<0>F7

67 32 30 29 11

CK
MEM_B_CLK_N<0>G7 CK*

67 32 30 29 11

MEM_B_CKE<0>

67 32 30 29 11

MEM_B_CKE<1>

11 67

A3
79
NC 80
81
82

G9 CKE0
F9 CKE1

67 32 30 29 11

MEM_B_CS_L<1> H1

CS1*

67 32 30 29 11

MEM_B_CS_L<0> H2

CS0*

67 32 30 29 11

MEM_B_RAS_L

67 32 30 29 11

MEM_B_CAS_L

F3
G3

RAS*
CAS*

67 32 30 29 11

MEM_B_WE_L

H3

WE*
VSS

NC
NC

67 32 30 29 11

MEM_B_A<5>

67 32 30 29 11

MEM_B_A<6>

L2
M8

67 32 30 29 11

MEM_B_A<7>

M2

67 32 30 29 11

MEM_B_A<8>

A3
A4
A5
A6
A7

67 32 30 29 11

MEM_B_A<9>

N8
M3

67 32 30 29 11

MEM_B_A<10>

H7

A9
A10/AP

67 32 30 29 11

MEM_B_A<11>

67 32 30 29 11

MEM_B_A<12>

M7
K7

A11
A12/BC*

67 32 30 29 11

MEM_B_A<13>
MEM_B_A<14>

N3
N7

A13

67 32 30 29 11

MEM_B_A<15>

J7

A15

67 32 30 29 11

J2
K8

BA0

MEM_B_BA<1>

67 32 30 29 11

MEM_B_BA<2>

J3

67 32 30 29 11

MEM_B_CLK_P<0>F7

67 32 30 29 11

MEM_B_CLK_N<0>G7

67 32 30 29 11

MEM_B_CKE<0>

NF_DQ5 E8 MEM_B_DQ<16>
NF_DQ6 D2 MEM_B_DQ<18>
NF_DQ7 E7 MEM_B_DQ<20>

79
NC 80
81

CK*

67 32 30 29 11

67 32 30 29 11

MEM_B_CS_L<1> H1

67 32 30 29 11

MEM_B_CS_L<0> H2

67 32 30 29 11

MEM_B_RAS_L

F3

67 32 30 29 11

MEM_B_CAS_L

67 32 30 29 11

MEM_B_WE_L

G3
H3

MEM_B_A<4>

L8

67 32 30 29 11

MEM_B_A<5>

11 67

67 32 30 29 11

MEM_B_A<6>

L2
M8

11 67

67 32 30 29 11

MEM_B_A<7>

M2

67 32 30 29 11

MEM_B_A<8>

67 32 30 29 11

11 67

67 32 30 29 11

MEM_B_A<2>

11 67

67 32 30 29 11

11 67

67 32 30 29 11

11 67

A5
A6
A7

MEM_B_A<9>

67 32 30 29 11

MEM_B_A<10>

H7

A9
A10/AP

67 32 30 29 11

MEM_B_A<11>

67 32 30 29 11

MEM_B_A<12>

M7
K7

A11
A12/BC*

N3
N7

A13

67 32 30 29 11

MEM_B_A<13>
MEM_B_A<14>

E9

C1
E2

B9

M9

K9
M1

NF_DQ5 E8 MEM_B_DQ<25>
NF_DQ6 D2 MEM_B_DQ<31>
NF_DQ7 E7 MEM_B_DQ<24>

11 67
11 67
11 67
11 67
11 67
11 67
11 67
11 67

J7

A15

MEM_B_BA<0>

J2
K8

BA0

67 32 30 29 11

MEM_B_BA<1>

J3

DQS C3 MEM_B_DQS_P<3>

11 67

DQS* D3 MEM_B_DQS_N<3>

11 67

DM/TDQS B7
NF_TDQS* A7 NC

NC

A3 NC

BA1
BA2

67 32 30 29 11

MEM_B_BA<2>

67 32 30 29 11

MEM_B_CLK_P<0>F7

CK

67 32 30 29 11

MEM_B_CLK_N<0>G7

CK*

67 32 30 29 11

MEM_B_CKE<0>

79
NC 80
81

67 32 30 29 11

CS1*

67 32 30 29 11

MEM_B_CS_L<1> H1

CS1*

CS0*

67 32 30 29 11

MEM_B_CS_L<0> H2

CS0*

RAS*

67 32 30 29 11

MEM_B_RAS_L

F3

RAS*

67 32 30 29 11

MEM_B_CAS_L

67 32 30 29 11

MEM_B_WE_L

G3
H3

CAS*
WE*

VSS

DQ0 B3 MEM_B_DQ<30>
DQ1 C7 MEM_B_DQ<29>
DQ2 C2 MEM_B_DQ<26>
DQ3 C8 MEM_B_DQ<28>
NF_DQ4 E3 MEM_B_DQ<27>

A14

G9 CKE0
MEM_B_CKE<1> F9 CKE1

CAS*
WE*

OMIT_TABLE

A8

67 32 30 29 11

MEM_B_A<15>

K1

G2
G8

D7

A3
A4

N8
M3

82

VSSQ

A2
A9

J8
VREFCA

E1

L3
K2

A2

MEM_B_A<3>

MEM_B_A<1>

67 32 30 29 11

CK

ZQ0
ZQ1
A0
A1

67 32 30 29 11

67 32 30 29 11

BA1
BA2

MEM_B_ZQ7 H9

11 67

11 67

NC

RESET*

K3
L7

11 67

A3 NC

201

MEM_B_A<0>

MT41K1G4

1/20W

67 32 30 29 11

DQS C3 MEM_B_DQS_P<2>

DM/TDQS B7

1%

N2

MEM_B_ZQ3 H8

11 67

DQS* D3 MEM_B_DQS_N<2>

NF_TDQS* A7 NC

G9 CKE0
MEM_B_CKE<1> F9 CKE1

VREFDQ

E2
E9

C1

B9

M9

MT41K1G4

MF

DQ0 B3 MEM_B_DQ<19>
DQ1 C7 MEM_B_DQ<17>
DQ2 C2 MEM_B_DQ<23>
DQ3 C8 MEM_B_DQ<21>
NF_DQ4 E3 MEM_B_DQ<22>

A14

MEM_B_BA<0>

240

R3130 1

A8

67 32 30 29 11

67 32 30 29 11

K9
M1

G8
K1

G2

A9
D7

A2

E1

J8
VREFCA

A2

ODT1

MEM_RESET_L

512MX8-4GBIT-DDR3-1600

L8

11 67

DQS* D3 MEM_B_DQS_N<1>

NF_TDQS* A7 NC

A14

L3
K2

MEM_B_A<4>

11 67

11 67

DM/TDQS B7

MEM_B_A<3>

67 32 30 29 11
11 67

DQS C3 MEM_B_DQS_P<1>

VREFDQ

E9

E2

B9
C1

M1
M9

K9

G8
K1

D7
G2

A9

A11
A12/BC*

67 32 30 29 11

MEM_B_A<15>

A2

J8

E1

A10/AP

VSSQ
L1

J1
J9

F8

D8
F2

A8
B1

A1

VSS

A8
A9

67 32 30 29 11

RAS*
CAS*

K7

A7

J7
J2

67 32 30 29 11

NC 80

CK
CK*

G9 CKE0
F9 CKE1

MEM_B_CS_L<1> H1
MEM_B_CS_L<0> H2

11 67

67 32 30 29 11

D9

MEM_B_CKE<1>

MEM_B_A<8>

67 32 30 29 11
11 67

79

D1

MEM_B_CKE<0>

67 32 30 29 11

BA2

B8
C9

67 32 30 29 11

A3

BA1

M2
N8

MEM_B_A<2>

67 32 30 29 11
11 67

67 32 30 29 11

30 29 28 27 26

20%
4V
CERM-X5R-1
201

82

VSSQ

VSS

VSSQ
D1
D9

67 32 30 29 11

K8
J3

MEM_B_A<7>

67 32 30 29 11
11 67

U3130

0.47UF

FBGA-9P5X11P65-COMBO

C9

J2

MEM_B_BA<1>
MEM_B_BA<2>

67 32 30 29 11

67 32 30 29 11

67 32
11 67

ODT0

MEM_B_ODT<1> F1

B2
B8

MEM_B_BA<0>

67 32 30 29 11

M8

11 67

DQS* D3 MEM_B_DQS_N<0>

A15
BA0

MEM_B_A<6>

NF_DQ5 E8 MEM_B_DQ<12>
NF_DQ6 D2 MEM_B_DQ<11>
NF_DQ7 E7 MEM_B_DQ<8>

11 67

ZQ0
MF 1%
1/20W
201 MEM_B_ZQ6 H9
ZQ1
K3 A0
30 29 11 MEM_B_A<0>
L7 A1
30 29 11 MEM_B_A<1>

MEM_B_ODT<0> G1

C3132

VDDQ

N9

NF_TDQS* A7 NC

MEM_B_A<15>

67 32 30 29 11

A5
A6

67 32

MEM_B_ZQ2 H8

67 32 30 29 11

=PP1V5_S3_MEM_B

VDD

N1

A14

MEM_B_A<14>

MEM_B_A<5>

67 32 30 29 11
11 67

11 67

RESET*

L1
L9

N7
J7

67 32 30 29 11

MEM_B_A<4>

DQ0 B3 MEM_B_DQ<10>
DQ1 C7 MEM_B_DQ<9>
DQ2 C2 MEM_B_DQ<15>
DQ3 C8 MEM_B_DQ<13>
NF_DQ4 E3 MEM_B_DQ<14>

240

ODT1

20%
4V
CERM-X5R-1
201

J9

MEM_B_A<13>

DM/TDQS B7

67 32 30 29 11

A12/BC*
A13

A4

MEM_B_A<3>

67 32 30 29 11
11 67

R3120 1

N2

OMIT_TABLE

FBGA-9P5X11P65-COMBO

ODT0

0.47UF

F8
J1

A10/AP
A11

K7
N3

L8
L2

67 32 30 29 11
11 67

MEM_RESET_L

20%
4V
CERM-X5R-1
201

C3131

32 30 29 7

F2

M7

MEM_B_A<12>

A2
A3

30 29 28 27 26

U3120

0.47UF

B1
D8

MEM_B_A<11>

L3
K2

67 32 30 29 11

MEM_B_ODT<1> F1

C3130

A1
A8

MEM_B_A<10>

67 32 30 29 11

VREFDQ

E2
E9

B9
C1

M1
M9

K9

G8
K1

G2

A9
D7

67 32 30 29 11
67 32 30 29 11
67 32 30 29 11

A9

L7

MEM_B_A<2>

11 67

DQS C3 MEM_B_DQS_P<0>

M3
H7

MEM_B_A<1>

67 32 30 29 11

MEM_B_ODT<0> G1

20%
4V
CERM-X5R-1
201

PP0V75_S3_MEM_VREFDQ_B

31 30 29

0.47UF

D9

MEM_B_A<9>

A7
A8

ZQ1

67 32 30 29 11
11 67

NF_DQ7 E7 MEM_B_DQ<1>

K3

A0
A1

67 32 30 29 11

DQ3 C8 MEM_B_DQ<4>
NF_DQ4 E3 MEM_B_DQ<6>
NF_DQ5 E8 MEM_B_DQ<0>
NF_DQ6 D2 MEM_B_DQ<7>

201

MEM_B_A<0>

ZQ0

67 32 30 29 11

C3122

VDDQ

D1

67 32 30 29 11

11 67
11 67

OMIT_TABLE

FBGA-9P5X11P65-COMBO

VDD

B8
C9

N8

1/20W

MEM_B_ZQ5 H9

=PP1V5_S3_MEM_B

B2

MEM_B_A<8>

1%

MEM_B_ZQ1 H8

20%
4V
CERM-X5R-1
201

N9

MEM_B_A<7>

67 32 30 29 11

A6

MF

DQ0 B3 MEM_B_DQ<2>
DQ1 C7 MEM_B_DQ<5>
DQ2 C2 MEM_B_DQ<3>

N1

67 32 30 29 11

M8
M2

R3110 1

0.47UF

512MX8-4GBIT-DDR3-1600

MEM_B_A<6>

A4
A5

RESET*

N2

20%
4V
CERM-X5R-1
201

C3121

L1
L9

67 32 30 29 11

A3

MEM_RESET_L

240

0.47UF

32 30 29 7

J1
J9

L2

30 29 28 27 26

20%
4V
CERM-X5R-1
201

F8

K2
L8

MEM_B_A<5>

ODT0
ODT1

C3120

0.47UF

D8
F2

MEM_B_A<4>

MEM_B_ODT<1> F1

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_B

31 30 29

B1

MEM_B_A<3>

MEM_B_ODT<0> G1

67 32 30 29 11

31 30 29

A1
A8

67 32 30 29 11
67 32 30 29 11
67 32 30 29 11

67 32 30 29 11

U3110

PP0V75_S3_MEM_VREFCA_B

D9

MEM_B_A<2>

RESET*

C3112

VDDQ

C9
D1

67 32 30 29 11

FBGA-9P5X11P65-COMBO

H8 ZQ0
H9 ZQ1
K3 A0
L7 A1
L3 A2

OMIT_TABLE

VDD

B8

MEM_B_A<1>

20%
4V
CERM-X5R-1
201

B2

MEM_B_A<0>

67 32 30 29 11

0.47UF

20%
4V
CERM-X5R-1
201

N9

67 32 30 29 11

0.47UF

31 30 29

=PP1V5_S3_MEM_B

MT41K1G4

MEM_B_ZQ4

512MX8-4GBIT-DDR3-1600

1/20W

N2

20%
4V
CERM-X5R-1
201

C3111

L9
N1

201

MEM_B_ZQ0

VDDQ

L1

1%

C3110

J1
J9

MF

MEM_RESET_L

0.47UF

A1

240

C3102

32 30 29 7

F2
F8

ODT1

PP0V75_S3_MEM_VREFDQ_B

D8

ODT0

MEM_B_ODT<1> F1

VDD

U3100

PP0V75_S3_MEM_VREFCA_B

A8
B1

MEM_B_ODT<0> G1

A2

J8

E1

31 30 29

31 30 29

=PP1V5_S3_MEM_B

MT41K1G4

20%
4V
CERM-X5R-1
201

67 32 30 29 11

30 29 28 27 26

67 32 30 29 11

R3100 1

0.47UF

512MX8-4GBIT-DDR3-1600

20%
4V
CERM-X5R-1
201

C3101

VREFCA

0.47UF

VREFDQ

C3100

32 30 29 7

VREFCA

PP0V75_S3_MEM_VREFCA_B

31 30 29

31 30 29 PP0V75_S3_MEM_VREFDQ_B

A14/A15 FOR 2G/4G MONO ONLY


CS1 IS FOR 2G DDP RANK CONTROL
240

R3101 1
MF

240

R3111 1
MF

1%

1%

240

R3121 1
MF

1%

2
1/20W

2
1/20W

MEM_B_ZQ4

MEM_B_ZQ5

29

201

2
1/20W

29

201

SYNC_MASTER=K21_MLB

MEM_B_ZQ6 29

SYNC_DATE=07/28/2011

PAGE TITLE

DDR3 DRAM CHANNEL B (0-31)

201

DRAWING NUMBER
240

R3131 1
MF

1%

2
1/20W

Apple Inc.

MEM_B_ZQ7 29
201

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

051-9277

REVISION
BRANCH
PAGE

31 OF 109

SHEET

29 OF 73

PP0V75_S3_MEM_VREFCA_B

MEM_B_BA<2>

A15
BA0

K8
J3

67 32 30 29 11

MEM_B_CLK_P<0>F7

67 32 30 29 11

MEM_B_CLK_N<0>G7

67 32 30 29 11

MEM_B_CKE<0>

67 32 30 29 11

MEM_B_CKE<1>

MEM_B_CS_L<1> H1

67 32 30 29 11

MEM_B_CS_L<0> H2

67 32 30 29 11

MEM_B_RAS_L

67 32 30 29 11
67 32 30 29 11

MEM_B_CAS_L
MEM_B_WE_L

F3
G3
H3

MEM_B_A<11>

H7
M7

67 32 30 29 11

MEM_B_A<12>

K7

NF_TDQS* A7 NC

67 32 30 29 11

MEM_B_A<13>

N3
N7

A13

NC
A3
NC

67 32 30 29 11

A15

MEM_B_BA<0>

J7
J2

67 32 30 29 11

MEM_B_BA<1>

K8

BA0
BA1

67 32 30 29 11

MEM_B_BA<2>

J3

BA2

11 67

67 32 30 29 11

67 32 30 29 11

79
NC 80

CK
CK*

81
82

CS1*
CS0*

WE*

B2

N9

L9
N1

NF_TDQS* A7 NC

MEM_B_CLK_P<0>F7

CK

MEM_B_CLK_N<0>G7

CK*

67 32 30 29 11

MEM_B_CKE<0>

67 32 30 29 11

MEM_B_CKE<1>

NC
A3
NC
79
NC 80

G9 CKE0
F9 CKE1

67 32 30 29 11

MEM_B_CS_L<1> H1

CS1*

67 32 30 29 11

MEM_B_CS_L<0> H2

CS0*

67 32 30 29 11

MEM_B_RAS_L

F3

67 32 30 29 11

MEM_B_CAS_L

67 32 30 29 11

MEM_B_WE_L

G3
H3

RAS*
CAS*

MEM_B_A<6>

L2
M8

67 32 30 29 11

MEM_B_A<7>

M2

67 32 30 29 11

MEM_B_A<8>

67 32 30 29 11

MEM_B_A<9>

N8
M3

67 32 30 29 11

MEM_B_A<10>

H7

67 32 30 29 11

MEM_B_A<11>

67 32 30 29 11

MEM_B_A<12>

M7
K7

MEM_B_A<13>

N3

11 67

11 67

11 67

67 32 30 29 11
67 32 30 29 11
67 32 30 29 11

MEM_B_A<14>

MEM_B_A<15>

A6
A7

MEM_B_BA<1>

J2
K8
J3

A12/BC*
A13

67 32 30 29 11

MEM_B_A<2>

L3

A2

11 67

67 32 30 29 11

MEM_B_A<3>

11 67

67 32 30 29 11

MEM_B_A<4>

K2
L8

A3
A4

11 67

67 32 30 29 11

MEM_B_A<5>

67 32 30 29 11

MEM_B_A<6>

L2
M8

A5

11 67
11 67

67 32 30 29 11

MEM_B_A<7>

M2

11 67

DQS* D3 MEM_B_DQS_N<6>

11 67

DM/TDQS B7

MEM_B_BA<2>

MEM_B_CLK_P<0>F7

CK

82

67 32 30 29 11

MEM_B_CLK_N<0>G7

CK*

67 32 30 29 11

MEM_B_CKE<0>

67 32 30 29 11

MEM_B_A<8>

67 32 30 29 11

MEM_B_A<9>

N8
M3

67 32 30 29 11

MEM_B_A<10>

H7

67 32 30 29 11

MEM_B_A<11>

67 32 30 29 11

MEM_B_A<12>

M7
K7

MEM_B_A<13>

N3

67 32 30 29 11

NF_TDQS* A7 NC

67 32 30 29 11
67 32 30 29 11

NC

A3 NC

BA1
BA2

67 32 30 29 11

79
NC 80
81

67 32 30 29 11

G9 CKE0
MEM_B_CKE<1> F9 CKE1

67 32 30 29 11

MEM_B_CS_L<1> H1

67 32 30 29 11

MEM_B_CS_L<0> H2

67 32 30 29 11

MEM_B_RAS_L

67 32 30 29 11

MEM_B_CAS_L

67 32 30 29 11

MEM_B_WE_L

MEM_B_A<14>

MEM_B_A<15>
MEM_B_BA<1>

J2
K8
J3

E9

C1
E2

B9

M9

K9
M1

NF_DQ5 E8 MEM_B_DQ<61>
NF_DQ6 D2 MEM_B_DQ<62>
NF_DQ7 E7 MEM_B_DQ<56>

A11
A12/BC*
A13

11 67

11 67
11 67
11 67
11 67
11 67
11 67
11 67

DQS C3 MEM_B_DQS_P<7>

11 67

DQS* D3 MEM_B_DQS_N<7>

11 67

DM/TDQS B7
NF_TDQS* A7 NC

A15

NC

A3 NC

BA1
BA2

67 32 30 29 11

MEM_B_BA<2>

67 32 30 29 11

MEM_B_CLK_P<0>F7

CK

67 32 30 29 11

MEM_B_CLK_N<0>G7

CK*

67 32 30 29 11

MEM_B_CKE<0>

79
NC 80
81

67 32 30 29 11

G9 CKE0
MEM_B_CKE<1> F9 CKE1

CS1*

67 32 30 29 11

MEM_B_CS_L<1> H1

CS1*

CS0*

67 32 30 29 11

MEM_B_CS_L<0> H2

CS0*

F3

RAS*

67 32 30 29 11

MEM_B_RAS_L

F3

RAS*

G3
H3

CAS*
WE*

67 32 30 29 11

MEM_B_CAS_L

67 32 30 29 11

MEM_B_WE_L

G3
H3

CAS*
WE*

VSS

DQ2 C2 MEM_B_DQ<58>
DQ3 C8 MEM_B_DQ<60>
NF_DQ4 E3 MEM_B_DQ<59>

A9
A10/AP

BA0

MEM_B_BA<0>

DQ0 B3 MEM_B_DQ<63>
DQ1 C7 MEM_B_DQ<57>

A8

A14

67 32 30 29 11

K1

G2
G8

D7

A6
A7

N7
J7

67 32 30 29 11

82

VSSQ

A2
A9

J8

E1

67 32 30 29

11 67

DQS C3 MEM_B_DQS_P<6>

A15

67 32 30 29 11

VREFCA

E2
E9

C1

B9

A11

BA0

MEM_B_BA<0>

M9

A9
A10/AP

A14

67 32 30 29 11

NF_DQ5 E8 MEM_B_DQ<49>
NF_DQ6 D2 MEM_B_DQ<54>
NF_DQ7 E7 MEM_B_DQ<52>

11 67

A8

N7
J7

67 32 30 29 11

K9
M1

G8
K1

G2

A9
D7

A2

J8
VREFCA

E1

MEM_B_A<5>

67 32 30 29 11

81

WE*
VSS

A5

67 32 30 29 11
11 67

67 32 30 29

MT41K1G4

MT41K1G4

DM/TDQS B7

A14

67 32 30 29 11

VREFDQ

E9

E2

B9
C1

M1
M9

K9

G8
K1

D7
G2

A9

J8

A2

DQS* D3 MEM_B_DQS_N<5>

A11
A12/BC*

VSSQ
L1

J1
J9

F8

D8
F2

VSS

MEM_B_A<15>

DQS C3 MEM_B_DQS_P<5>

A10/AP

67 32 30 29 11

RAS*
CAS*

MEM_B_A<14>

VREFCA

E2
E9

M1
M9

K9

G8
K1

G2

A9
D7

B9
C1

MEM_B_A<10>

BA2

A8
B1

E1
M3

67 32 30 29 11

BA1

A1

VREFDQ

MEM_B_A<9>

67 32 30 29 11

G9 CKE0
F9 CKE1

67 32 30 29 11

67 32 30 29 11

A8
A9

MEM_B_A<4>

11 67

11 67

82

VSSQ

VSS

VSSQ
D1
D9

MEM_B_BA<1>

67 32 30 29 11

A14

J7
J2

MEM_B_A<8>

A7

67 32 30 29 11

11 67

RESET*

C9

67 32 30 29 11

N7

67 32 30 29 11

M2
N8

11 67

DM/TDQS B7

A13

MEM_B_A<7>

NF_DQ5 E8 MEM_B_DQ<45>
NF_DQ6 D2 MEM_B_DQ<43>
NF_DQ7 E7 MEM_B_DQ<40>

A3
A4

DQ2 C2 MEM_B_DQ<51>
DQ3 C8 MEM_B_DQ<48>
NF_DQ4 E3 MEM_B_DQ<50>

1%

N2

MEM_B_ZQ11

B2
B8

MEM_B_A<15>
MEM_B_BA<0>

A12/BC*

67 32 30 29 11

A5
A6

K2
L8

MF

DQ0 B3 MEM_B_DQ<55>
DQ1 C7 MEM_B_DQ<53>

MEM_RESET_L

H8 ZQ0
1/20W 201 MEM_B_ZQ15 H9
ZQ1
K3 A0
11 MEM_B_A<0>
L7
MEM_B_A<1>
11
A1
2

20%
4V
CERM-X5R-1
201

OMIT_TABLE

N9

67 32 30 29 11

MEM_B_A<14>

K7
N3

11 67

A4

MEM_B_A<3>

240

N1

MEM_B_A<13>

M8

67 32 30 29 11

11 67

U3230

0.47UF

FBGA-9P5X11P65-COMBO

512MX8-4GBIT-DDR3-1600

67 32 30 29 11

L8
L2

MEM_B_A<4>

A2

ODT1

C3232

VDDQ

L1
L9

67 32 30 29 11

DQS* D3 MEM_B_DQS_N<4>

MEM_B_A<5>
MEM_B_A<6>

11 67

L3

ODT0

MEM_B_ODT<1> F1

J9

M7

MEM_B_A<12>

67 32 30 29 11
67 32 30 29 11

67 32 30 29 11
11 67

MEM_B_A<2>

MEM_B_ODT<0> G1

F8
J1

MEM_B_A<11>

A10/AP
A11

MEM_B_A<3>

67 32 30 29 11

=PP1V5_S3_MEM_B

VDD

F2

67 32 30 29 11

A9

67 32 30 29 11
11 67

67 32 30 29
11 67

A1
A8

MEM_B_A<10>

A2
A3

30 29 28 27 26

D9

67 32 30 29 11

DQS C3 MEM_B_DQS_P<4>

L3
K2

1%

67 32 30 29
11 67

20%
4V
CERM-X5R-1
201

R3230 1

D1

67 32 30 29 11

M3
H7

MEM_B_A<2>

11 67

MF
11 67

RESET*

0.47UF

67 32 30 29 11

B8
C9

N8

67 32 30 29 11

11 67

DQ0 B3 MEM_B_DQ<42>
DQ1 C7 MEM_B_DQ<41>
DQ2 C2 MEM_B_DQ<46>
DQ3 C8 MEM_B_DQ<44>
NF_DQ4 E3 MEM_B_DQ<47>

N2

MEM_B_ZQ10

C3231

20%
4V
CERM-X5R-1
201

67 32 30 29 11

B2

MEM_B_A<8>
MEM_B_A<9>

A0
A1

MEM_RESET_L

H8 ZQ0
1/20W 201 MEM_B_ZQ14 H9
ZQ1
K3 A0
11 MEM_B_A<0>
L7
MEM_B_A<1>
11
A1
2

0.47UF

32 30 29 7

OMIT_TABLE

N9

67 32 30 29 11

A7
A8

L7

240

C3230

FBGA-9P5X11P65-COMBO

N1

MEM_B_A<7>

NF_DQ6 D2 MEM_B_DQ<34>
NF_DQ7 E7 MEM_B_DQ<32>

K3

MEM_B_A<1>

30 29 28 27 26

R3220 1

U3220

31 30 29

0.47UF
20%
4V
CERM-X5R-1
201

PP0V75_S3_MEM_VREFDQ_B

MT41K1G4

A6

MEM_B_A<0>

67 32 30 29 11

ODT1

512MX8-4GBIT-DDR3-1600

M8
M2

67 32 30 29 11
11 67

ODT0

MEM_B_ODT<1> F1

C3222

VDDQ

L1
L9

MEM_B_A<6>

ZQ1

MEM_B_ODT<0> G1

J1
J9

67 32 30 29 11

ZQ0

=PP1V5_S3_MEM_B

VDD

F8

MEM_B_A<5>

A4
A5

RESET*

D8
F2

67 32 30 29 11

L8
L2

201

11 67

MEM_B_ZQ13H9

32 30 29 7

A1
A8

MEM_B_A<4>

1/20W

20%
4V
CERM-X5R-1
201

D9

67 32 30 29 11

DQ3 C8 MEM_B_DQ<33>
NF_DQ4 E3 MEM_B_DQ<38>
NF_DQ5 E8 MEM_B_DQ<37>

1%

0.47UF

20%
4V
CERM-X5R-1
201

67 32 30 29 11

C9
D1

A2
A3

DQ0 B3 MEM_B_DQ<35>
DQ1 C7 MEM_B_DQ<36>
DQ2 C2 MEM_B_DQ<39>

MF

MEM_B_ZQ9 H8

C3221

0.47UF

67 32 30 29 11

B8

K2

240

20%
4V
CERM-X5R-1
201

C3220

0.47UF

FBGA-9P5X11P65-COMBO

ODT0
ODT1

B2

MEM_B_A<3>

MEM_RESET_L N2

30 29 28 27 26

R3210 1

MEM_B_ODT<1> F1

PP0V75_S3_MEM_VREFCA_B

31 30 29

31 30 29 PP0V75_S3_MEM_VREFDQ_B

OMIT_TABLE

N9

67 32 30 29 11

A1

MEM_B_ODT<0> G1

67 32 30 29 11

U3210
512MX8-4GBIT-DDR3-1600

67 32 30 29 11

L7
L3

67 32 30 29 11

C3212

VDDQ

L9
N1

K3

MEM_B_A<2>

L1

MEM_B_A<0>

67 32 30 29 11

A2

ZQ1
A0

MEM_B_A<1>

67 32 30 29 11

J8

E1
ZQ0

67 32 30 29 11

OMIT_TABLE

=PP1V5_S3_MEM_B

VDD

J1
J9

H9
MEM_B_ZQ12

20%
4V
CERM-X5R-1
201

FBGA-9P5X11P65-COMBO

RESET*

67 32 30 29 11

67 32 30 29 11

1/20W

0.47UF

20%
4V
CERM-X5R-1
201

F2
F8

MEM_B_ZQ8 H8

0.47UF

D8

201

N2

C3211

A8
B1

1%

MEM_RESET_L

20%
4V
CERM-X5R-1
201

C3210

0.47UF

VDDQ

U3200

MEM_B_ODT<0> G1 ODT0
MEM_B_ODT<1> F1 ODT1

32 30 29 7

A1

MF

VDD

C3202

31 30 29 PP0V75_S3_MEM_VREFDQ_B

D9

240

D1

30 29 28 27 26

R3200 1

20%
4V
CERM-X5R-1
201

B8
C9

67 32 30 29 11

0.47UF
2

512MX8-4GBIT-DDR3-1600

67 32 30 29 11

=PP1V5_S3_MEM_B

MT41K1G4

0.47UF
20%
4V
CERM-X5R-1
201

C3201

VREFCA

VREFDQ

C3200

32 30 29 7

VREFDQ

PP0V75_S3_MEM_VREFCA_B

31 30 29

PP0V75_S3_MEM_VREFDQ_B

B1
D8

PP0V75_S3_MEM_VREFCA_B

31 30 29

31 30 29

B1

31 30 29

A14/A15 FOR 2G/4G MONO ONLY


CS1 IS FOR 2G DDP RANK CONTROL

240

R3201 1
MF

240

R3211 1
MF

1%

1%

240

R3221 1
MF

1%

2
1/20W

2
1/20W

2
1/20W

MEM_B_ZQ12 30
201

MEM_B_ZQ13 30
201

SYNC_MASTER=K21_MLB

MEM_B_ZQ14 30

SYNC_DATE=07/28/2011

PAGE TITLE

DDR3 DRAM CHANNEL B (32-63)

201

DRAWING NUMBER
240

R3231 1
MF

1%

2
1/20W

Apple Inc.

MEM_B_ZQ15 30
201

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

051-9277

REVISION
BRANCH
PAGE

32 OF 109

SHEET

30 OF 73

NOTE: Must not enable more than two SO-DIMM margining


7

buffers at once or VRef source may be overloaded.

=PP3V3_S3_VREFMRGN

VREFDQ:LDO_DAC

OMIT
56 7

R3318
SHORT
1

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

NONE
NONE
NONE
402

DDRVREF_DAC

C3300

C3301

DDRVREF_DAC

0.1UF

20%
6.3V
CERM
402-LF

C3303

CRITICAL

10%
16V
X5R-CERM
0201

10%
16V
X5R-CERM
0201

U3300

SCL

=I2C_VREFDACS_SDA

SDA

A0

10

A1

Addr=0x98(WR)/0x99(RD)

MSOP

VOUTA

VOUTB

VOUTC

VOUTD

PP0V75_S3_MEM_VREFDQ_A

V+

VREFDQ:LDO_DAC

U3302

B1
A2

MAX4253

R3304

UCSP

A1

A3

VREFMRGN_SODIMMA_DQ

VREFMRGN_DQ_SODIMMA_BUF

133

B4

R3360

PLACE_NEAR=R3303.2:1mm

5%
1/20W
MF
2 201

VREFMRGN_SODIMMS_CA
VREFMRGN_MEMVREG_FBVREF

PP0V75_S3_MEM_VREFDQ_B 29 30 31

NOTE: MEMVREG and FRAMEBUF share

GND

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

VREFCA:LDO_DAC

a DAC output, cannot enable

PLACE_NEAR=Q3310.3:1mm
VREFDQ:LDO_DAC

1%
1/20W
MF
201

A4

V-

27 28 31 67

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

NC

=I2C_VREFDACS_SCL

DAC5574

IN
BI

PLACE_NEAR=U2900.E1:2.54mm

DDRVREF_DAC

0.1UF

DDRVREF_DAC

VDD

44

200
1%
1/20W
MF
201

DDRVREF_DAC

2.2UF

44

R3303
1

10mA max load

PP3V3_S3_VREFMRGN_DAC

=PPVTT_S3_DDR_BUF

both at the same time!

DDRVREF_DAC

R3309

R3301

200

PLACE_NEAR=U2900.J8:2.54mm

100K
1%
1/20W
MF
201

5%
1/20W

OMIT

MF
201

C2

PP3V3_S3_VREFMRGN_CTRL

V+

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

NONE
NONE
NONE
402

16

C3302

10%
6.3V
X5R
201

Page Notes

=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA

IN

44

BI

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

A0
A1
A2

SCL
SDA
THRM

GND

PAD

PLACE_NEAR=R3309.2:1mm

PLACE_NEAR=R3309:1mm
NOSTUFF

R3361

P0
P1
P2
P3
P4
P5
P6
P7

NC

7
9

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CA_SODIMMA_EN

11

VREFMRGN_CA_SODIMMB_EN

13
14

RESET*

5%
1/20W
MF
2 201

R3305

NC

10

200

DDRVREF_DAC

PLACE_NEAR=U3100.J8:2.54mm

1%
1/20W
MF
201

R3307
100K

VREFMRGN_MEMVREG_EN

12

VREFCA:LDO_DAC

5%

PP0V75_S3_MEM_VREFCA_B

1/20W

NC
NC

DDRVREF_DAC

2 201

B1

A2

V+

15

V-

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

R3306

U3304
MAX4253

VREFMRGN_CA_SODIMMB_BUF

UCSP

133

A1
A3

29 30

VREFCA:LDO_DAC

MF

BOM options provided by this page:


DDRVREF_DAC

1%
1/20W
MF
201

1%
1/20W
MF
201

17

Addr=0x30(WR)/0x31(RD)

133

PCA9557
(OD)

44

V-

VREFMRGN_CA_SODIMMA_BUF

C4

B4

QFN

Signal aliases required by this page:

UCSP

U3301

Power aliases required by this page:

C3

27 28 67

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

R3310

C1

DDRVREF_DAC

VCC

0.1UF

- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
- =PPDDR_S3_MEMVREF

MAX4253

CRITICAL
DDRVREF_DAC

PP0V75_S3_MEM_VREFCA_A
VREFCA:LDO_DAC

U3302

B1

SHORT

DDRVREF_DAC

R3319

A4

PLACE_NEAR=R3305.2:1mm

B4

- Stuffs Apple margining circuit.

VREFDQ:LDO - LDO outputs sent to DQ inputs.


VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.

25

IN

DDRVREF_DAC

PCA9557D_RESET_L

R3315

VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.

100K

RST* on platform reset so that system

VREFCA:LDO - LDO outputs sent to CA inputs.

5%

watchdog will disable margining.

VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

1/20W
MF

2 201

NOTE: Margining will be disabled across all


soft-resets and sleep/wake cycles.
31 7

=PPDDR_S3_MEMVREF

CRITICAL
VREFDQ:M1_M3

Q3320

R3321

DDRVREF_DAC

1K

C3305

1%
1/20W
MF
2 201

DDRVREF_DAC

0.1UF
10%
16V
X5R-CERM
0201

10%
16V
X5R-CERM
0201

PP0V75_S3_MEM_VREFDQ_A

V+

DDRVREF_DAC

U3304

B1
C2

MAX4253

R3314

UCSP
C1

27 28 31 67

VREFMRGN_MEMVREG_BUF

33.2K

DDRREG_FB

OUT

PPCPU_MEM_VREFDQ_A

SOT563

C3320
0.1UF

MEMRESET_ISOL_LS5V_L

SSM6N15AFE
G

31 26

PLACE_NEAR=Q3320.6:1mm
VREFDQ:M1_M3

PLACE_NEAR=Q3320.6:2mm
VREFDQ:M1_M3

C3

VREFDQ:M1_M3
1

R3322

VB4

1K

PLACE_NEAR=R3321.2:1mm

1%
1/20W
MF
201

C4

56

PLACE_NEAR=R7315.2:1mm

NOTE: CPU DAC output step sizes:


DDR3 (1.5V)
7.70mV per step
DDR3L (1.35V) 6.99mV per step

1%
1/20W
MF
2 201

Required zero ohm resistors when no VREF margining circuit stuffed

31 7

CRITICAL
VREFDQ:M1_M3

PLACE_NEAR=Q3320.3:2mm
VREFDQ:M1_M3

Q3320

SSM6N15AFE
SOT563

5%

REFERENCE DES

RES,MF,1/20W,0.0 OHM,5,0201,SMD

R3303,R3360

CRITICAL

BOM OPTION
VREFDQ:LDO

117S0002

RES,MF,1/20W,0.0 OHM,5,0201,SMD

R3309,R3305

VREFCA:LDO

201

1%
1/20W
MF

10%

2 16V
X5R-CERM

2 201

PART NUMBER
PP0V75_S3_MEM_VREFDQ_B

VREFDQ:M1_M3
PLACE_NEAR=R3311.2:1mm

QTY

REFERENCE DES

RES,MF,1KOHM,1,1/20W,0201

R3321,R3322,R3311,R3312

CRITICAL

BOM OPTION
VREFDQ:M1_DAC

118S0303

RES,MF,332OHM,1,1/20W,0201

R3304

VREFDQ:M1_DAC

1K

MEM B VREF DQ

DESCRIPTION

118S0012

29 30 31

R3312

MEM A VREF DQ

QTY

MF

1K

DESCRIPTION

117S0002

1/20W

R3311

S
4

PPCPU_MEM_VREFDQ_B

R3313
100K

C3310
0201

PLACE_NEAR=Q3320.3:2mm
VREFDQ:M1_M3

0.1UF

MEMRESET_ISOL_LS5V_L

31 26

PART NUMBER

DDRVREF_DAC

=PPDDR_S3_MEMVREF

1%
1/20W
MF
201

MEM A VREF CA

MEM B VREF CA

MEM VREG

GPU Frame Buffer (1.8V, 70% VRef)

SYNC_MASTER=J11_MLB

SYNC_DATE=08/04/2011

PAGE TITLE

DAC Channel:

PCA9557D Pin:

Nominal value

5
1.5V (DAC: 0x3A)

1.267V (DAC: 0x8B)

Margined target:

0.300V - 1.200V (+/- 450mV)

1.000V - 2.000V (+/- 500mV)

1.056V - 1.442V (+/- 180mV)

DAC range:

0.000V - 1.501V (0x00 - 0x74)

0.000V - 3.000V (0x00 - 0x74)

0.000V - 3.300V (0x00 - 0xFF)

VRef current:

+3.4mA - -3.4mA (- = sourced)

DAC step size:

7.69mV / step @ output

-61uA (- = sourced)

Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1.51mV / step @ output

051-9277

SIZE

REVISION

2.8.0

+6.0mA - -5.0mA (- = sourced)

8.59mV / step @ output

DRAWING NUMBER

0.75V (DAC: 0x3A)

+61uA -

FSB/DDR3/FRAMEBUF Vref Margining

BRANCH
PAGE

33 OF 109

SHEET

31 OF 73

32 28 27 7

=PP1V5_S3_MEM_A

32 28 27 7

JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

=PP1V5_S3_MEM_A

C3408

2.2UF

2.2UF

20%
6.3V
2 CERM
402-LF

C3400

2.2UF

20%
6.3V
2 CERM
402-LF

C3409

C3401

20%
2 6.3V
CERM
402-LF

C3411

C3421

20%
6.3V
2 CERM
402-LF

C3431

2.2UF

20%
6.3V
2 CERM
402-LF

2.2UF

C3404

2.2UF

C3414

2.2UF

C3415

C3434

2.2UF

C3425

C3435

2.2UF

20%
2 6.3V
CERM
402-LF

2 CAPS ALONG PACKAGE EDGE

C3444

67 28 27 11

IN

67 28 27 11

IN

67 28 27 11

IN

C3454

IN

67 28 27 11

IN

67 28 27 11

IN

67 28 27 11

IN

67 28 27 11

IN

67 28 27 11

IN

C3445

C3455

20%
2 6.3V
CERM
402-LF

IN
IN

67 28 27 11

IN

67 28 27 11

IN

67 28 27 11

IN

67 28 27 11

IN
IN

67 28 27 11

IN

67 28 27 11

IN

MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_A_ODT<1>
MEM_A_RAS_L
MEM_A_A<0>
MEM_A_A<3>
MEM_A_A<12>
MEM_A_BA<1>
MEM_A_ODT<0>
MEM_A_CAS_L
MEM_A_A<5>
MEM_A_WE_L
MEM_A_A<10>
MEM_A_A<4>
MEM_A_CS_L<0>
MEM_A_A<2>
MEM_A_CS_L<1>
MEM_A_A<1>
MEM_A_BA<0>
MEM_A_A<7>

RP3401
RP3401
RP3401
RP3401
RP3402
RP3402
RP3402
RP3402
RP3405
RP3405
RP3405
RP3405
RP3403
RP3403
RP3403
RP3403
RP3404
RP3404
RP3404
RP3404

36 1
36 2
36 3
36 4
36 1
36 2
36 3
36 4
36 1
36 2
36 3
36 4
36 1
36 2
36 3
36 4
36 1
36 2
36 3
36 4
36
36
36
36

67 28 27 11

IN

67 28 27 11

IN

MEM_A_A<15>
MEM_A_A<9>
MEM_A_BA<2>

IN

MEM_A_A<11>

RP3406
RP3406
RP3406
RP3406

MEM_A_A<6>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<8>

RP3407
RP3407
RP3407
RP3407

67 28 27 11

2.2UF

IN

67 28 27 11

67 28 27 11

2.2UF

IN

67 28 27 11

67 28 27 11

20%
6.3V
2 CERM
402-LF

20%
2 6.3V
CERM
402-LF

C3416

IN

67 28 27 11

2.2UF

20%
2 6.3V
CERM
402-LF

67 28 27 11

67 28 27 11

20%
6.3V
2 CERM
402-LF

20%
6.3V
2 CERM
402-LF

2.2UF

67 28 27 11

IN

67 28 27 11

IN

67 28 27 11

IN

67 28 27 11

IN

36
36
36
36

C3428

2.2UF

20%
2 6.3V
CERM
402-LF

C3429
2.2UF

20%
2 6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

C3403
2.2UF

20%
6.3V
2 CERM
402-LF

2.2UF

20%
2 6.3V
CERM
402-LF

2 CAPS ALONG PACKAGE EDGE

C3471
2.2UF

20%
6.3V
2 CERM
402-LF

C3470

C3422

2.2UF

2.2UF

20%
2 6.3V
CERM
402-LF

C3423
2.2UF

20%
6.3V
2 CERM
402-LF

C3438

20%
6.3V
2 CERM
402-LF

2.2UF

20%
2 6.3V
CERM
402-LF

1
1

C3432

C3433
2.2UF

C3439

20%
6.3V
2 CERM
402-LF

2.2UF

20%
6.3V
2 CERM
402-LF

C3472

2.2UF

20%
2 6.3V
CERM
402-LF

C3491
2.2UF

20%
6.3V
2 CERM
402-LF

2.2UF

C3490

C3452
2.2UF

C3453
2.2UF

20%
6.3V
2 CERM
402-LF

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

2 CAPS ALONG PACKAGE EDGE

20%
6.3V
2 CERM
402-LF

C3407
2.2UF

20%
2 6.3V
CERM
402-LF

C3474
2.2UF

20%
6.3V
2 CERM
402-LF

C3475
2.2UF

20%
2 6.3V
CERM
402-LF

C3426

2.2UF

C3436
2.2UF

20%
6.3V
2 CERM
402-LF

20%
6.3V
2 CERM
402-LF

C3427

2.2UF

C3437
2.2UF

20%
6.3V
2 CERM
402-LF

20%
6.3V
2 CERM
402-LF

C3494
2.2UF

20%
6.3V
2 CERM
402-LF

C3495
2.2UF

20%
6.3V
2 CERM
402-LF

2.2UF

COLUMN OF THREE CAPS BETWEEN PACKAGES

C3456
2.2UF

20%
6.3V
2 CERM
402-LF

C3457
2.2UF

20%
6.3V
2 CERM
402-LF

R3468
3.3PF

20%
2 6.3V
CERM
402-LF

5%
25V
CERM 2
201

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN
IN
IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN
IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

67 30 29 11

IN

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

0.47UF

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

MEM_A_CLK_TERM_R

0.47UF

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

C3484

20%
2 4V
CERM-X5R-1
201

C3486
0.47UF

20%
2 4V
CERM-X5R-1
201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

20%
4V
2 CERM-X5R-1
201

4
1

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

C3488
0.47UF

C3483
0.47UF

20%
4V
2 CERM-X5R-1
201

C3485
0.47UF

20%
2 4V
CERM-X5R-1
201

C3487
0.47UF

20%
2 4V
CERM-X5R-1
201

C3493
0.47UF

20%
4V
2 CERM-X5R-1
201

C3489
0.47UF

MEM_B_CKE<0>
MEM_B_A<8>
MEM_B_CS_L<1>
MEM_B_A<1>
MEM_B_CS_L<0>
MEM_B_A<13>
MEM_B_A<15>
MEM_B_RAS_L
MEM_B_A<7>
MEM_B_CKE<1>
MEM_B_A<9>
MEM_B_CAS_L
MEM_B_A<0>
MEM_B_A<3>
MEM_B_ODT<0>
MEM_B_A<6>
MEM_B_A<12>
MEM_B_BA<1>
MEM_B_A<14>
MEM_B_A<2>
MEM_B_A<4>
MEM_B_ODT<1>

=PP0V75_S0_MEM_VTT_B

RP3413
RP3410
RP3409
RP3411

36
36
36
36

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

RP3409
RP3410
RP3408
RP3413
RP3411
RP3413
RP3411
RP3409
RP3408
RP3408
RP3409
RP3410
RP3414
RP3408
RP3410

36
36
36
36
36
36
36
36
36
36
36
36
36
36
36

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

20%
4V
2 CERM-X5R-1
201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

RP3414
RP3414
RP3413

36
36
36

1
2

30

0.47UF

0.47UF

3.3PF

67 30 29 11

MEM_B_CLK_P<0>

0.47UF

30

0.47UF

20%
4V
2 CERM-X5R-1
201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

0.47UF

C3464

0.47UF

20%
4V
2 CERM-X5R-1
201

C3465
0.47UF

MEM_B_A<5>
MEM_B_A<11>

RP3414
RP3411

36
36

3
1

RP3412
RP3412
RP3412
RP3412

36
36
36
36

5% 1/32W

4X0201

MEM_B_BA<0>
MEM_B_WE_L
MEM_B_A<10>
MEM_B_BA<2>

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

20%
4V
2 CERM-X5R-1
201

C3462

20%
2 4V
CERM-X5R-1
201

20%
4V
2 CERM-X5R-1
201

C3466
0.47UF

C3467
0.47UF

20%
4V
2 CERM-X5R-1
201

C3477
0.47UF

20%
2 4V
CERM-X5R-1
201

SYNC_DATE=07/28/2011

PAGE TITLE

DDR3 Bypassing/Termination

C3479

DRAWING NUMBER

2 MEM_B_CLK_TERM_R

Apple Inc.

VOLTAGE=0V

0.1UF
10%
X5R
201
6.3V

051-9277

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

2.8.0

5%
1/20W
MF
201

C3463

SYNC_MASTER=K21_MLB

R3479
1

C3461

20%
2 4V
CERM-X5R-1
201

5%
1/20W
MF
201

C3478 1
5%
25V
CERM 2
201

30

C3460

X5R
201
6.3V

MEM_B_CLK_N<0>

C3481

20%
4V
2 CERM-X5R-1
201

0.1UF
10%

R3478
67 30 29 11

VOLTAGE=0V

5%
1/20W
MF
201

C3482

20%
4V
2 CERM-X5R-1
201

C3469

R3469
1

MEM_A_CLK_P<0>

30

5%
1/20W
MF
201

C3468 1

2.2UF

COLUMN OF THREE CAPS BETWEEN PACKAGES

MEM_A_CLK_N<0>

C3496

5% 1/32W

4X0201

Place RC end termination after last DRAM


Place Source Cterm at neckdown at first DRAM

67 28 27 11

4X0201

5% 1/32W

MEM CLOCK TERMINATION

67 28 27 11

C3476

20%
6.3V
2 CERM
402-LF

5% 1/32W

2.2UF

IN

67 30 29 11

67 30 29 11

C3492

20%
6.3V
2 CERM
402-LF

IN

67 30 29 11

2.2UF

20%
6.3V
2 CERM
402-LF

IN

67 30 29 11

67 30 29 11

20%
2 6.3V
CERM
402-LF

67 30 29 11

C3406

4X0201

20%
4V
2 CERM-X5R-1
201

20%
4V
2 CERM-X5R-1
201

67 30 29 11

C3446

=PP1V5_S3_MEM_B

32 30 29 7

C3402

2.2UF

4X0201

5% 1/32W

20%
2 6.3V
CERM
402-LF

COLUMN OF THREE CAPS BETWEEN PACKAGES

=PP1V5_S3_MEM_B
1

5% 1/32W

30 29 7
32

C3480
0.47UF

2.2UF

20%
2 6.3V
CERM
402-LF

COLUMN OF THREE CAPS BETWEEN PACKAGES

C3451
2.2UF

2.2UF

20%
6.3V
2 CERM
402-LF

2.2UF

20%
2 6.3V
CERM
402-LF

20%
6.3V
2 CERM
402-LF

2.2UF

20%
2 6.3V
CERM
402-LF

C3424
2.2UF

20%
6.3V
2 CERM
402-LF

C3405

C3442

20%
6.3V
2 CERM
402-LF

2.2UF

20%
6.3V
2 CERM
402-LF

2.2UF

20%
6.3V
2 CERM
402-LF

2 CAPS ALONG PACKAGE EDGE

C3441

20%
6.3V
2 CERM
402-LF

C3412

C3450

20%
6.3V
2 CERM
402-LF

2.2UF

20%
6.3V
2 CERM
402-LF

=PP0V75_S0_MEM_VTT_A

2.2UF

20%
6.3V
2 CERM
402-LF

2.2UF

C3419

C3440

2.2UF

20%
2 6.3V
CERM
402-LF

1
1

C3430

2.2UF

20%
6.3V
2 CERM
402-LF

2.2UF

20%
6.3V
2 CERM
402-LF

C3418

2.2UF

20%
2 6.3V
CERM
402-LF

2.2UF

20%
6.3V
2 CERM
402-LF

C3420

2.2UF

20%
6.3V
2 CERM
402-LF

2.2UF

2.2UF

C3410

BRANCH
PAGE

34 OF 109

SHEET

32 OF 73

8
7

=PP3V3_S3_CARDREADER
BYPASS=U3500.1:16:5 mm

SDCARD_IOVDD
BYPASS=U3500.8:5BYPASS=U3500.8:5
mm
mm

C3503

1
2

SDCARD_PLLVDD

0.1UF
10%

CRITICAL

6.3V

L3500

X5R
201

0.22UH

C3502
0.1UF

10%

2 6.3V
X5R

0805-1

C3501
0.1UF

10%

2 6.3V
X5R

201

R3505 is for rail discharge. GL822 may cycle PMOS to


recover from card error. Off duration is 100ms and card
voltage must be less than 0.5V for at least 1ms per spec.

201

BYPASS=U3500.3:5:5 mm

PP3V3_S3_CARDREADER_AVDD

Keep this net short!

C3514

10%

C3507

X5R
201

4.7UF

68 24
68 24

NO STUFF1

R3507

CRITICAL
2

10K

R3506

10K
5%
1/20W
MF
201

NC

R3513

R35101

715
1%
1/20W
MF
201

GL137_RESET_L

2
GL137_RESET_L_R

201 5% 1/20W MF

PDMOD: POWER DOWN MODES


NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE
10K HIGH = REMOTE WAKE UP ENABLE

C3513

22 GPIO0
6 GPIO1
17 GPIO2
26 RSTZ*
27 TEST

(IPD)
(IPU)
(IPU)

THRM_PAD

0.22UF

6.3V
X5R
201

CRITICAL

J3500
SD-CARD-K16

Max Current = 800 mA

5%
1/20W
MF
201

F-RT-TH

R3529

1
5% 1/16W

2 0
402 MF-LF

SD_CLK_R2

R3531

2 0
6
402 MF-LF

1
5% 1/16W

D0
D1
D2
D3
D4
D5
D6
D7

13
14
9
10
18
19
20
21

SD_D_R<0>
SD_D_R<1>
SD_D_R<2>
SD_D_R<3>
SD_D_R<4>
SD_D_R<5>
SD_D_R<6>
SD_D_R<7>

R3528 1

SD_CLK
SD_WP
SD_CMD
SD_CDZ
MS_INS

2 0
402 MF-LF

1
5% 1/16W

2 0
402 MF-LF

1
5% 1/16W

R3523

2 0
402 MF-LF

1
5% 1/16W

R3526 1

2 0
402 MF-LF

2 0
402 MF-LF

1
5% 1/16W

6
6

R3522 1

2 0
402 MF-LF

1
5% 1/16W

6
6

R3524

2 0
402 MF-LF

5% 1/16W

R3521

6
6

5% 1/16W

R3525

12 SD_CLK_R R3520 1
5% 1/20W
24
R3519 1
11 SD_CMD_R
5% 1/16W
23 SDCONN_DETECT_L
25

2 0
402 MF-LF

5% 1/16W

R3527

6
6

L3504

2 33 SD_CLK_L1
MF 201

33 6

OUT

SD_CLK
SD_CMD
SD_D<0>
SD_D<1>
SD_D<2>
SD_D<3>
SD_D<4>
SD_D<5>
SD_D<6>
SD_D<7>
SD_CD_L

SD_WP

20
402

IN

VSS

VSS
CLK

5
2
7
8
9
1
10
11
12
13
14
15

0402

47NH-1.3OHM

16
4

MF-LF

33

17

NO STUFF

NC

1 C3521
10PF

C3515
10PF
5%
25V

1 C3520
10PF

NPO

201

1 C3519
10PF
2

R3505

SD_CLK_R1

20%
6.3V
2 X5R
0201

Q3500

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

47K

10%

(IPU)
(IPD)

C3505
0.1UF

20%
6.3V
X5R-CERM1
402

PMOS 15

29

R3509 1

GL822
QFN

GL137_GPIO0
GL137_GPIO1

5%
1/20W
MF
201

U3500

4 RREF

GL137_RREF

10K
5%
1/20W
MF
201

BI
BI

DVDD

3 DP
2 DM

USB_SDCARD_P
USB_SDCARD_N

IOVDD 8

AVDD 5

6.3V

PP3V3_SW_SD_PWR

C3504
0.1UF

20%
6.3V
X5R-CERM1
402

PLLVDD 28

4.7UF

1
7
16

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

5%
50V
C0G-CERM
0402

5%
50V
C0G-CERM
0402

5%
50V
C0G-CERM
0402

C3522 1

1 C3523
10PF
2

5%
50V
C0G-CERM
0402

5%
50V
C0G-CERM
NO
0402
1

10PF

5%
50V
C0G-CERM
0402

5%
50V
C0G-CERM
0402

1 C3527
10PF
2

STUFF

R3530
0

C3524 1

10PF
2

18

1 C3525
10PF

5%
1/16W
MF-LF

402

5%
50V
C0G-CERM
0402

C3526 1

19
20

CMD
DAT0
DAT1
DAT2
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN

516-0237

10PF
5%
50V
C0G-CERM
0402

SSM6N37FEAPE
SOT563

23

IN

SDCARD_PLT_RST

SDCONN_STATE_RST_L

R3590

10K

5%
1/20W
MF
2 201

Q3500

IN

SOT563

25

SSM6N37FEAPE

SDCARD_PLT_RST_L

B
SD Detect & Reset Logic
SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit
Converts SDCONN from active-low level signal to active-high pulses
RESET_IN* musts be pulled to GND if not used. SD detect logic will only function if Reset logic is low.

=PP3V3_S4_SD_HPD

DLY block is 20ms nominal


When LOW_PWR gated dessarts, RST_OUT# deassserts for >80ms, then asserts for 10ms
regardless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

VDD

U3510
SLG4AP014V
TDFN

IN

SD_CD_L
From SD CONN ->

LOW_PWR

RST_IN*

DET_IN
(IPU)

RST_OUT*

(OD)

SDCONN_STATE_CHANGE_SMCOUT

42

DET_CHNGD*
(OD)

-> To SMC & Isolation Circuit (then to PCH GPIO)


(Low active pulse signal)

SDCONN_DETECT_L

33

-> To GL822 Chip

RST
LOGIC

DLY

Connector shorts GND with Card_Detect_SW signal


when SD card inserted.

XOR

33 6

NC

OUT

GND
5

DET_OUT

THRM
PAD

SYNC_MASTER=J13_MLB_NON_POR

*** Need to confirm with SW weather LATCH is required.


(SDCONN_STATE_RST_L will be required with LATCH)

SYNC_DATE=11/10/2011

PAGE TITLE

SecureDigital Card Reader


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

35 OF 109

SHEET

33 OF 73

CRITICAL
10%
2

10%

10%

0.1UF
IN

C3604

PCIE_TBT_R2D_C_P<2>

36 35 34 7

IN

69 8

IN

PCIE_TBT_R2D_C_P<3>

C3606

IN

PCIE_TBT_R2D_C_N<3>

C3607

R36101
5%
1/20W
MF
201

=PP3V3_TBTLC_RTR

69 8

10%

3.3K
5%
1/20W
MF
201

3.3K

5%
1/20W
MF
201

(TBT_SPI_MOSI)

X5R-CERM0201

16V

X5R-CERM 0201

69
69

10%

0.1UF

16V

36

IN

1UF

3.3K

20%
6.3V
X5R
0201

8
VCC
5

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

1 S*

5%
1/20W
MF
201

CRITICAL
OMIT_TABLE

R3693

10%
16V
X5R-CERM
0201

OMIT

R3615 1

3.3K

5%
1/20W
MF
201

U3690

47

3 W*
7 HOLD*

(TBT_SPI_MISO)

70
70

VSS
4

THM
PAD
9

19 8

IN

16

IN

IN

R3625

R3629

OUT

69 34

5%
1/20W
MF
201 2

5%
1/20W
MF
2 201

69 34

69 34
69 34

69 34
69 34
69 34
69 34

69 34

69 8

IN

DP_TBTSNK0_ML_C_P<0>

69 8

IN

DP_TBTSNK0_ML_C_N<0>

C3621

DP_TBTSNK0_ML_C_P<1>

C3622

69 8

IN

C3623

IN

DP_TBTSNK0_ML_C_P<2>

C3624

IN

DP_TBTSNK0_ML_C_N<2>

C3625

DP_TBTSNK0_ML_N<0>

34 69

R3630 1

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

69 34

100K
5%
1/20W
MF
201

34 69

69 34

69 34

69 34

34 69

69 34
69 34

DP_TBTSNK0_ML_P<2>

34 69

69 34

10%
16V
X5R-CERM0201

0.1UF
69 8

OUT

10%
16V
X5R-CERM 0201

0.1UF
69 8

34 69

10%
16V
X5R-CERM 0201

0.1UF

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_P<0>

10%
16V
X5R-CERM 0201

0.1UF
IN

10%
16V
X5R-CERM 0201

0.1UF

69 8

69 34

SNK0 AC Coupling
C3620

69 34

DP_TBTSNK0_ML_N<2>

34 69

10%
16V
X5R-CERM 0201

0.1UF

69 34
69 34

69 8

IN

DP_TBTSNK0_ML_C_P<3>

C3626

IN

DP_TBTSNK0_ML_C_N<3>

C3627

BI

DP_TBTSNK0_AUXCH_C_P

BI

DP_TBTSNK0_AUXCH_C_N

C3628

C3629

DP_TBTSNK0_ML_N<3>

34 69

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_AUXCH_N

R3631 1

34 69

5%
1/20W
MF
201

70 64

OUT

70 64

IN

70 64

IN

64
64

69 8

IN

DP_TBTSNK1_ML_C_P<0>

SNK1 AC Coupling
C3630
1

IN

DP_TBTSNK1_ML_C_N<0>

C3631

IN

DP_TBTSNK1_ML_C_P<1>

C3632

IN

DP_TBTSNK1_ML_C_N<1>

C3633

69 8

IN

DP_TBTSNK1_ML_C_P<2>

C3634

IN

DP_TBTSNK1_ML_C_N<2>

IN

DP_TBTSNK1_ML_C_P<3>

C3635

C3636

IN

DP_TBTSNK1_ML_C_N<3>

C3637

BI

DP_TBTSNK1_AUXCH_C_P

C3638

BI

DP_TBTSNK1_AUXCH_C_N

C3639

0.1UF

34 69

DP_TBTSNK1_ML_N<2>

34 69

DP_TBTSNK1_ML_P<3>

34 69

DP_TBTSNK1_ML_N<3>

34 69

DP_TBTSNK1_AUXCH_P

34 69

10%
16V
X5R-CERM 0201

0.1UF
69 8

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_AUXCH_N

34 69

PETP_1
PETN_1

AD9

69

AD11

69

C3642

PCIE_TBT_D2R_C_P<1>
PCIE_TBT_D2R_C_N<1>

PETP_2
PETN_2

AD13

69

AD15

69

C3644

PCIE_TBT_D2R_C_P<2>
PCIE_TBT_D2R_C_N<2>

C3645

PETP_3
PETN_3

AD17

69

AD19

69

RSENSE

U20

TBT_RSENSE

RBIAS

W20

TBT_RBIAS

C3646

PCIE_TBT_D2R_C_P<3>
PCIE_TBT_D2R_C_N<3>

PERST_N

TBT_PWR_ON_POC_RST_L

J2

PWR_ON_POC_RSTN

AD23
AC24

W16

TP_TBT_THERM_DP

NC

U4

NC

MONOBS_P
MONOBS_N

Y7

THERMDA

TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
TBT_SPI_CLK

R4

EE_DI
EE_DO
EE_CS_N
EE_CLK

P5
AD3
W4

V1

JTAG_TBT_TDI
JTAG_TBT_TMS
JTAG_TBT_TCK
JTAG_TBT_TDO
TBT_TEST_EN
TBT_TEST_PWR_GOOD

AB3
AA6
R2
N4
AB5

DP_TBTSNK0_ML_P<3>
DP_TBTSNK0_ML_N<3>

E14

DP_TBTSNK0_ML_P<2>
DP_TBTSNK0_ML_N<2>

E16

D13

D15

DP_TBTSNK0_ML_P<1>
DP_TBTSNK0_ML_N<1>

E18

DP_TBTSNK0_ML_P<0>
DP_TBTSNK0_ML_N<0>

E20

DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N

A6

D17

D19

B5

IN
OUT

64

IN

TDI
TMS
TCK
TDO
TEST_EN
TEST_PWR_GOOD

DPSNK0_2_P
DPSNK0_2_N
DPSNK0_1_P
DPSNK0_1_N
DPSNK0_0_P
DPSNK0_0_N

DPSNK0_HPD

DP_TBTSNK1_ML_P<3>
DP_TBTSNK1_ML_N<3>

E6

DPSNK1_3_P
DPSNK1_3_N

DP_TBTSNK1_ML_P<2>
DP_TBTSNK1_ML_N<2>

E8

DP_TBTSNK1_ML_P<1>
DP_TBTSNK1_ML_N<1>

E10

DP_TBTSNK1_ML_P<0>
DP_TBTSNK1_ML_N<0>

E12

DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N

A4

D9

D11

B3
T5

TBT_A_R2D_C_P<0>
TBT_A_R2D_C_N<0>

G24

TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

G22

E24

E22

TBT_A_CONFIG1_BUF
TBT_A_CONFIG2_RC

K1
G4

TBT_A_R2D_C_P<1>
TBT_A_R2D_C_N<1>

L24

TBT_A_D2R_P<1>
TBT_A_D2R_N<1>

L22

J24

J22

TBT_A_LSTX
TBT_A_LSRX

N2
J6

DPSNK1_2_P
DPSNK1_2_N
DPSNK1_1_P
DPSNK1_1_N
DPSNK1_0_P
DPSNK1_0_N

DPSNK1_HPD

PA_CIO0_TX_P/DP_SRC_0_P
PA_CIO0_TX_N/DP_SRC_0_N
PA_CIO0_RX_P
PA_CIO0_RX_N
PA_CONFIG1/CIO_0_LSEO
PA_CONFIG2/CIO_0_LSOE
PA_CIO1_TX_P/DP_SRC_2_P
PA_CIO1_TX_N/DP_SRC_2_N
PA_CIO1_RX_P
PA_CIO1_RX_N
PA_LSTX/CIO_1_LSEO
PA_LSRX/CIO_1_LSOE

DP_TBTPA_HPD

H1

PA_DPSRC_HPD

TBT_A_HV_EN
TBT_A_CIO_SEL
TBT_A_DP_PWRDN

G2

GPIO_0/PA_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2

BI

70 64

64

64 36 34

OUT

64

OUT

64 34

OUT

F1

M3
H3

TBT_EN_LC_PWR

PA_DPSRC_1_P
PA_DPSRC_1_N
PA_DPSRC_3_P
PA_DPSRC_3_N
PA_AUX_P
PA_AUX_N

T1
Y5
U2

X5R-CERM 0201

16V

X5R-CERM 0201

PCIE_TBT_D2R_N<3>

10%

16V

X5R-CERM 0201

OUT

8 69

OUT

8 69

OUT

8 69

OUT

8 69

OUT

8 69

OUT

8 69

R3655

OUT

AD21

AA24

TMU_CLK_OUT
TMU_CLK_IN

AA4

AB23

Y3

69

NOTE: The following pins require testpoints:


0 - GPIO_13
8 - GPIO_15
1 - GPIO_1
9 - GPIO_11
2 - GPIO_2
10 - GPIO_14
3 - GPIO_3
11 - GPIO_0
4 - GPIO_5
12 - GPIO_12
5 - PCIE_RST_1_N
13 - GPIO_10
6 - PCIE_RST_2_N
14 - PB_LSTX
7 - PCIE_RST_3_N
15 - PB_LSRX

1%
1/20W
MF
201

36

=PP3V3_TBTLC_RTR
OUT

36

7 34 35 36

R3698
10K

PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N

AB21

XTAL_25_IN
XTAL_25_OUT

DPSRC_3_P
DPSRC_3_N

A14

DPSRC_2_P
DPSRC_2_N

A12

DPSRC_1_P
DPSRC_1_N

A10

IN

16 69

IN

16 69

5%
1/20W
MF
201

R3695

SYSCLK_CLK25M_TBT_R
TP_TBT_XTAL25OUT

806

SYSCLK_CLK25M_TBT

IN

1%
1/20W
MF
201

TBT_TMU_CLK_OUT
TBT_TMU_CLK_IN

36 35 34 7

DPSRC_0_P
DPSRC_0_N

A8

DPSRC_AUX_P
DPSRC_AUX_N

C2

DPSRC_HPD_OD

V3

B15

B13

TP_DP_TBTSRC_ML_CP<3>
TP_DP_TBTSRC_ML_CN<3>

R3697
100K

5%
1/20W
MF
201 2

TP_DP_TBTSRC_ML_CP<2>
TP_DP_TBTSRC_ML_CN<2>

R3699

25 69

=PP3V3_TBTLC_RTR
1

10K

R3680
10K

R3696

5%
1/20W
MF

1K

5%
1/20W
MF
201 2

5%
1/20W
MF
2 201

2 201
34
34 19

PB_CIO2_RX_P
PB_CIO2_RX_N

PB_CIO3_RX_P
PB_CIO3_RX_N
PB_LSTX/CIO_3_LSEO
PB_LSRX/CIO_3_LSOE

IN

70 64

B19

K5

PB_CIO3_TX_P/DP_SRC_2_P
PB_CIO3_TX_N/DP_SRC_2_N

F3

OUT

=TBT_CLKREQ_L

EN_LC_PWR

PB_CONFIG1/CIO_2_LSEO
PB_CONFIG2/CIO_2_LSOE

DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N

70 64

W6

PB_CIO2_TX_P/DP_SRC_0_P
PB_CIO2_TX_N/DP_SRC_0_N

BI

OUT

16V

8 69

B11

B9

D3

TP_DP_TBTSRC_ML_CP<1>
TP_DP_TBTSRC_ML_CN<1>

Y1
W2
J4
AA2
AB1
AC2
P3
M5
T3
V5

R24
N24
R22
N22
P1
H5

W24
U24
W22
U22
L6
G6

PB_DPSRC_1_P
PB_DPSRC_1_N

A20

PB_DPSRC_3_P
PB_DPSRC_3_N

A22

B21

B23

TP_DP_TBTSRC_ML_CP<0>
TP_DP_TBTSRC_ML_CN<0>
TP_DP_TBTSRC_AUXCH_CP
TP_DP_TBTSRC_AUXCH_CN

34

TBT_GO2SX_BIDIR
TBT_PWR_EN
=TBT_WAKE_L
TBT_CIO_PLUG_EVENT
=I2C_TBTRTR_SDA
=I2C_TBTRTR_SCL

IN

25

OUT

42

OUT

23

R3681
0

5%
1/20W
MF

2 201

TBT_GPIO_9
TBT_GPIO_14

IN

44

OUT

34

OUT

34

OUT

8 70

OUT

8 70

IN

8 70

IN

8 70

IN

TBT_B_R2D_C_P<1>
TBT_B_R2D_C_N<1>

OUT

8 70

OUT

8 70

IN

8 70

IN

8 70

IN

DP_TBTPB_ML_C_P<1>
DP_TBTPB_ML_C_N<1>

OUT

8 70

OUT

8 70

DP_TBTPB_ML_C_P<3>
DP_TBTPB_ML_C_N<3>

OUT

8 70

OUT

8 70

DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N

BI

8 70

BI

8 70

TBT_B_HV_EN
TBT_B_CIO_SEL
TBT_B_DP_PWRDN

18

TBT_EN_CIO_PWR_L

OUT

36

36 35 34 7

5%
1/20W
MF

2 201

64 34

R3686
10K

5%
1/20W
MF

2 201

TBT_A_DP_PWRDN
TBT_B_DP_PWRDN
TBT_A_HV_EN
TBT_B_HV_EN

R36881

R3687

10K

10K

5%
1/20W
MF
201 2

5%
1/20W
MF

2 201

SYNC_DATE=09/30/2011

PAGE TITLE

Thunderbolt Host (1 of 2)
DRAWING NUMBER

Apple Inc.

051-9277

34

OUT

OUT

34

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

OUT

SIZE

REVISION

All other port signals can be NC.

5%
1/20W
MF
201 2

SYNC_MASTER=J11_MLB

IN

=PP3V3_S4_TBT

10K

34

OUT

M1

OUT

64 36 34

TBT_B_LSTX
TBT_B_LSRX

GPIO_1/PB_HV_EN/BYP0
GPIO_11/PB_CIO_SEL/BYP1
GPIO_13/PB_DP_PWRDN/BYP2

TBT_PWR_REQ_L

34

OUT

TBT_B_D2R_P<1>
TBT_B_D2R_N<1>

10K

R36851

TBT_B_CONFIG1_BUF
TBT_B_CONFIG2_RC

DP_TBTPB_HPD

5%
1/20W
MF
201

MAKE_BASE=TRUE

TBT_B_D2R_P<0>
TBT_B_D2R_N<0>

R3682

10K

100K
5%
1/16W
MF-LF
402

1NO STUFF

R36831

R3632 1

44

34

TBT_B_R2D_C_P<0>
TBT_B_R2D_C_N<0>

K3

19 34

(TBT_EN_CIO_PWR_L)

PB_DPSRC_HPD

L4

IN

BI

TBT_GPIO_9
TBT_GPIO_14
TBT_DDC_XBAR_EN_L

D1

L2

DP_TBTSRC_HPD

PB_AUX_P
PB_AUX_N

E2

TBT_DDC_XBAR_EN_L
TBT_GO2SX_BIDIR

R3681 for CYA,


allows separation
of GPIO_2/GPIO_9
if necessary.
Stuff one of R3861/2.

34

DPSNK1_AUX_P
DPSNK1_AUX_N

A18

70 64

B17

PCIE_CLKREQ_OD_N

GPIO_2/GO2SX
(FORCE_PWR)
GPIO_3
GPIO_4/WAKE_N_OD
GPIO_5/CIO_PLUG_EVENT
GPIO_6/CIO_SDA_OD
GPIO_7/CIO_SCL_OD
GPIO_8/EN_CIO_PWR_OD*
GPIO_9/OK2GO2SX_OD*
GPIO_14
GPIO_15

DP_TBTPA_ML_C_P<3>
DP_TBTPA_ML_C_N<3>

OUT

X5R-CERM 0201

OUT

NO STUFF

A16

OUT

70 64

16V

DP_TBTPA_ML_C_P<1>
DP_TBTPA_ML_C_N<1>

70 64

N6

REFCLK_100_IN_P
REFCLK_100_IN_N

DPSNK0_AUX_P
DPSNK0_AUX_N

U6

D7

X5R-CERM 0201

8 69

Not used in host mode.


TP_TBT_PCIE_RESET0_L
TP_TBT_PCIE_RESET1_L
TP_TBT_PCIE_RESET2_L
TP_TBT_PCIE_RESET3_L

PCIE_RST_0_N
PCIE_RST_1_N
PCIE_RST_2_N
PCIE_RST_3_N

DPSNK0_3_P
DPSNK0_3_N

DP_TBTSNK0_HPD

D5

16V

OUT

1K

MONDC0
MONDC1

W18

X5R-CERM 0201

PCIE_TBT_D2R_P<3>

10%
1

16V

PCIE_TBT_D2R_N<2>

10%

0.1UF

C3647

X5R-CERM 0201

PCIE_TBT_D2R_P<2>

10%

0.1UF

16V

PCIE_TBT_D2R_N<1>

10%

0.1UF

X5R-CERM 0201

PCIE_TBT_D2R_P<1>

10%
1

16V

PCIE_TBT_D2R_N<0>

10%

0.1UF

C3643

PCIE_TBT_D2R_P<0>

10%

0.1UF

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k).

10%
16V
X5R-CERM 0201

IN

64

10%
16V
X5R-CERM 0201

0.1UF
69 8

34 69

10%
16V
X5R-CERM 0201

0.1UF
69 8

OUT

10%
16V
X5R-CERM0201

0.1UF
69 8

10%
16V
X5R-CERM 0201

0.1UF
69 8

34 69

DP_TBTSNK1_ML_N<1>

10%
16V
X5R-CERM 0201

0.1UF

70 64

70 64

DP_TBTSNK1_ML_P<1>

IN
OUT

70 64

10%
16V
X5R-CERM 0201

0.1UF
69 8

34 69

10%
16V
X5R-CERM 0201

0.1UF
69 8

DP_TBTSNK1_ML_N<0>

OUT

70 64
34 69

10%
16V
X5R-CERM 0201

0.1UF
69 8

DP_TBTSNK1_ML_P<0>

OUT

70 64

34 69

10%
16V
X5R-CERM 0201

0.1UF

TBT_PCIE_RESET_L

DP_TBTSNK1_HPD

OUT

100K

10%
16V
X5R-CERM 0201

0.1UF
69 8

10%
16V
X5R-CERM 0201

0.1UF
69 8

34 69

10%
16V
X5R-CERM 0201

0.1UF
69 8

DP_TBTSNK0_ML_P<3>

PERP_3
PERN_3

R6

Use AA8 GND ball for THERM_DN

70

TBTROM_WP_L

PERP_2
PERN_2

DEBUG: For monitoring clock

M95256-RMC6XG
MLP

TBTROM_HOLD_L

AB19

TBT_MONOBSP
TBT_MONOBSN

70

C3641

DEBUG: For monitoring current/voltage

NOSTUFF

NONE
NONE
NONE
402 2

AA18

PCIE_TBT_R2D_P<3>
PCIE_TBT_R2D_N<3>

TP_TBT_MONDC0
TP_TBT_MONDC1

C3610

R3692 1

AA16

0.1UF

0.1UF

NO STUFF1

1 C3690

C3640

PCIE_TBT_D2R_C_P<0>
PCIE_TBT_D2R_C_N<0>

X5R-CERM 0201

IN

7 34 35 36

R3691

16V

AB15

PCIE_TBT_R2D_P<2>
PCIE_TBT_R2D_N<2>

10%
1

0.1UF

R3690 1

69

0.1UF

47K

36

0.1UF

=PP3V3_S4_TBT

X5R-CERM0201

69

C3605

PCIE_TBT_R2D_C_N<2>

16V

10%

0.1UF
69 8

X5R-CERM0201

PERP_1
PERN_1

CLOCKS

69 8

16V

AB13

PCIE RESET

AA12

PCIE_TBT_R2D_P<1>
PCIE_TBT_R2D_N<1>

TRANSMIT

69

C3603

PCIE_TBT_R2D_C_N<1>

69

(SYM 1 OF 2)
69

MISC

IN

X5R-CERM0201

10%

DISPLAYPORT

69 8

16V

69

AD7

0.1UF

PCIE GEN2

0.1UF

AD5

FCBGA

PORT0

C3602

PCIE_TBT_R2D_C_P<1>

CACTUSRIDGE4C

PORT1

IN

X5R-CERM0201

PETP_0
PETN_0

U3600

JTAG/TEST PORT

69 8

16V

PERP_0
PERN_0

SOURCE PORT 0

0.1UF

AA10

PORT2

PCIE_TBT_R2D_P<0>
PCIE_TBT_R2D_N<0>

SINK PORT 0

IN

69

X5R-CERM 0201

69

C3601

PCIE_TBT_R2D_C_N<0>

16V

AB9

PORT3

0.1UF
69 8

OMIT_TABLE

PORTS

SINK PORT 1

C3600

PCIE_TBT_R2D_C_P<0>

RECEIVE

IN

EEPROM

69 8

BRANCH
PAGE

36 OF 109

SHEET

34 OF 73

=PP1V05_TBTLC_RTR

C3700

10UF

20%
6.3V
CERM-X5R
0402-1

C3710

1.0UF
2

20%
6.3V
X5R
0201-MUR

C3729

1.0UF
2

20%
6.3V
X5R
0201-MUR

C3712

1.0UF
2

20%
6.3V
X5R
0201-MUR

C3713

1.0UF
2

20%
6.3V
X5R
0201-MUR

1.0UF
2

CRITICAL

C3714
20%
6.3V
X5R
0201-MUR

J10
J12
J14
J16
J8

C3701

10UF

20%
6.3V
CERM-X5R
0402-1

C3730

1.0UF

20%
6.3V
X5R
0201-MUR

C3732

20%
6.3V
X5R
0201-MUR

1.0UF

C3718
1.0UF

20%
6.3V
X5R
0201-MUR

K17
T15
U14
V7
W8
G10
G12
G14
G16
G18
H19
K19
M19
P19
T19
V15
V19
W12
W14

G8
H9

AD1
K13
K9
L12
L16
L8
M13
M17
M9
N12
N16
N8
P13
P17
P9
R12
R16
R8
T13
T17
T9
U12
U16

U8
V9

A2
A24
AA14
AA20
AA22
AA8
AB11
AB17
AB7
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC4
AC6
AC8
B1
B7
C10
C12

C14
C16
C18
C20

VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE

U3600
CACTUSRIDGE4C
FCBGA

(SYM 2 OF 2)

VCC1P0_DPAUX
VCC1P0_DPAUX
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

=PP1V05_TBTCIO_RTR

OMIT_TABLE

VCC

???? mA (Single Port)


250 mA (Dual Port)
EDP: 1000 mA

VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0

K11

VCC3P3
VCC3P3
VCC3P3

M7

L10
L14
M11
M15

C3740

1.0UF

20%
6.3V
X5R
0201-MUR

C3741

1.0UF

20%
6.3V
X5R
0201-MUR

C3742

1.0UF

20%
6.3V
X5R
0201-MUR

C3743

1.0UF

20%
6.3V
X5R
0201-MUR

C3744

1.0UF

20%
6.3V
X5R
0201-MUR

C3745

20%
6.3V
X5R
0201-MUR

1.0UF

C3705
10UF

20%
6.3V
CERM-X5R
0402-1

N10
N14
P11
P15
R10
R14
T11
U10
V11
W10

=PP3V3_TBTLC_RTR 7 34
??? mA (Single-Port)
250 mA (Dual-Port)
EDP: 240 mA

P7
T7

VCC3P3_CIO
VCC3P3_CIO
VCC3P3_CIO

L18

VCC3P3_DP
VCC3P3_DP
VCC3P3_DP
VCC3P3_DP

H11

N18

C3770

1.0UF

20%
6.3V
X5R
0201-MUR

C3771

1.0UF

20%
6.3V
X5R
0201-MUR

C3772

1.0UF

20%
6.3V
X5R
0201-MUR

C3773

1.0UF

20%
6.3V
X5R
0201-MUR

C3774

1.0UF

20%
6.3V
X5R
0201-MUR

36

C3760
10UF

20%
6.3V
CERM-X5R
0402-1

R18

H13
H15
H17

VCC3P3_DPAUX

H7

VCC3P3_POC

K7

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

C22

C3790

C24

1.0UF

C4
C6

7 34 36

EDP: 10 mA

20%
6.3V
X5R
0201-MUR

C8
D21
D23
E4
F11
F13
F15
F17
F19
F21
F23
F5
F7

F9
G20
H21
H23
J18
J20
K21
K23
L20
M21
M23
N20
P21
P23
R20
T21
T23
U18
V13
V17
V21
V23
Y11
Y13
Y15
Y17
Y19

SYNC_MASTER=J11_MLB

Y21

SYNC_DATE=10/04/2011

PAGE TITLE

Y23

Thunderbolt Host (2 of 2)

Y9

DRAWING NUMBER

Apple Inc.

051-9277

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

2.8.0

???? mA (Single-Port)
2700 mA (Dual-Port)
EDP: 3000 mA

K15

=PP3V3_S4_TBT

GND

BRANCH
PAGE

37 OF 109

SHEET

35 OF 73

2 X5R-CERM

10UF

TBTBST_SNS1

20%
25V

0603

200K
1%
1/20W
MF
201

TBTBST_PWREN_DIV_L

VIN
TBTBST_EN_UVLO

R3881

25

EN/UVLO

28

INTVCC

U3890

150K

5%
1/20W
MF
201 2

TBTBST_INTVCC

LT3957

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

TBTBST_PWREN_L
1

TBT_A_HV_EN

IN

R3892

32

SS

34

SYNC

10%
10V
X5R
805

C3893

R3894

41.2K

3300PF

<R2>

1%
1/20W
MF
201

10%
10V
X7R-CERM
0201

NC

1%
1/16W
MF-LF
402

2
2

C3888
5%
50V
CERM
402

SGND

GND

C3889
5%
50V
CERM
402

SGND shorted to
GND inside package,
no XW necessary.

Supervisor & CLKREQ# Isolation


=PP3V3_S0_TBTPWRCTL

=PP3V3_TBTLC_RTR

SSM6N37FEAPE

R3840

Q3840
VESM

10%
16V
X5R-CERM
0201

10K
5%
1/20W
MF

G 1

SSM3K15AMFVAPE

0.1UF

SLG4AP016V

5%
1/20W
MF
201

25

=TBT_RESET_L

IN

MR*

EN
OUT

OUT

TBT_CLKREQ_L

R3887

TBT_PCIE_RESET_L

OUT

=TBT_CLKREQ_L
TBT_CLKREQ_ISOL_L

C3884

20%
25V
X5R-CERM
0603

2 25V
X5R-CERM

10UF

C3882
10UF
20%

1%
1/16W
MF-LF
402 2

C3896

C3898

20%
25V
X5R-CERM
0603

10UF

10UF

<Rb>

20%
25V
X5R-CERM
0603

0603

C3883

10UF

20%
25V
X5R-CERM
0603

C3881
10UF

C3899
0.001UF

20%

2 25V
X5R-CERM

0603

10%
50V
X7R-CERM
0402

Vout = 1.6V * (1 + Ra / Rb)

Q3888
SSM6N37FEAPE
SOT563

34

IN

IN

25 41 42

34

MAKE_BASE=TRUE

THRM
PAD

GND

20%
25V
X5R-CERM
0603

15.8K

SMC_DELAYED_PWRGD
IN

10UF

5%
1/20W
MF
201

5%
1/20W
MF
201

DLY = 60 ms +/- 20%

(OD)

Pull-up provided by SB page.

C3897

16

R3896

20%
25V
X5R-CERM
0603

R3888

330K

Platform (PCIe) Reset

10UF

6 7

DLY
RESET*

C3895

TBTBST_SHDN_DIV
PP1V05_TBTLC

TDFN

+ SENSE
- 0.7V

Max Vgs: 10V

TBT_EN_LC_PWR

IN

100K

U3800

2 201
34

R3807

VDD

330K

CRITICAL

<Ra>

Q3888

7 34 35 36

SOT563

C3800

=PP15V_TBT_REG

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

UVLO(falling) = 1.22 * (R1 + R2) / R2


UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)

Vout = 15.1V
Max Current = 1.0A
Freq = 300KHz

1%
1/16W
MF-LF
402 2

100PF
2

PLACE_NEAR=C3895.1:2 mm

133K

TBTBST_FBX

R38951

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

GND_TBTBST_SGND

SM

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

22PF

C3894
10%
6.3V
CERM-X5R
402

TBTBST_VSNS

NO STUFF

0.33UF

POWERDI-123

DFLS230L

XW3895

R3890
49.9K

31

FBX

4.7UF

73.2K
1%
1/20W
MF
201

TBTBST_SS

D3895

TBTBST_SNS2

TBTBST_VC_RC

C3892

10
35

16

RT

37

64 34

33

24

SOD-VESM-HF

SNS2

QFN

36

1%
1/20W
MF
201 2

5%
25V
NP0-C0G-CERM
0201

NC

TBTBST_RT

10K

47PF

SSM3K15FV

R38931

C3887

SNS1

23

VC

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

5%
1/20W
MF
MIN_NECK_WIDTH=0.2 mm
201
2
MIN_LINE_WIDTH=0.2 mm

30

TBTBST_VC

R3889 1

SW

CRITICAL

<R1>
1

CRITICAL

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

TBTBST_VSNS_RC

38

R3891

Q3805

TBTBST_BOOST
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE

C3891

15

14

10%
25V
X5R
402

20%
25V
X5R-CERM
0603

10UF

0.1UF

BOM options provided by this page:


TBTBST:Y - Stuffs 18V boost circuitry.

C3890

C3880

2
PIMB062D-SM

21

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

4
1

470K
5%
1/20W
MF
201

Voltage not specified here,


add property on another page.

R3880 1

Signal aliases required by this page:


- =TBT_CLKREQ_L
- =TBT_RESET_L

L3895

6.8UH-4.0A

PPVIN_SW_TBTBST

7 6

17

BGA

CRITICAL

SI8409DB

=PPVIN_SW_TBTBST
8-13V Input
Changes required
for 2S.

TBT 15V Boost Regulator

Q3880

-30V
+/-12V
-1.4V
46mOhm @ 4.5V Vgs
3.7A @ 70C

SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):

CRITICAL

13

Power aliases required by this page:


- =PPVIN_SW_TBTBST
(8-13V Boost Input)
- =PP18V_TBT_REG
(18V Boost Output)
- =PP3V3_TBT_P3V3TBTFET
(3.3V FET Input)
- =PP3V3_TBT_FET
(3.3V FET Output)
- =PP3V3_S0_TBTPWRCTL
- =PP1V05_TBT_P1V05TBTFET
(1.05V FET Input)
- =PP1V05_TBT_FET
(1.05V FET Output)

20

12

27

8
Page Notes

TBT "POC" Power-up Reset


Intel investigating whether RC is sufficient.
=PP3V3_S4_TBT

1.0UF
X5R-CERM

C2

1.0UF

GND

10%
6.3V

0201

X5R-CERM

U3810

ON

1 C3811

TBTPOCRST_CT

Part

TPS22924C

Type

Load Switch

CT

C3831

C3830

0.0047UF
2

10%
25V
CERM
0402

QFN

THRM
PAD

GND

0.1UF
10%
16V

X5R-CERM
0201

(IPU)

MR*

TBT_PWR_ON_POC_RST_L

TBTPOCRST_MR_L

=PP3V3_S0_PCH_GPIO
OUT

NO STUFF

R(on)
@ 2.5V

18.5 mOhm Typ


25.8 mOhm Max

C3825

1.05V TBT "LC" Switch

TBT_EN_LC_1V05

36 7

CSP

A2

B2

VIN

=PP1V05_TBTLC_FET
A1

VOUT

C2

10%
6.3V
X5R-CERM

ON
GND

TBT_EN_CIO_PWR

Part

TPS22924C

Type

Load Switch

Q3825

X5R-CERM
0201

34

D2

C3820 1

ON
GND

10%
6.3V
X5R-CERM

Max Current = 4A (85C)

U3820
Part

TPS22920

Type

Load Switch

R(on)
@ 1.05V

8 mOhm Typ
11.5 mOhm Max

IN

TBT Power Support


DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY:

TBT_EN_CIO_PWR_L

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-9277

SIZE

REVISION

2.8.0

C3816 must be 10%

SYNC_DATE=11/10/2011

PAGE TITLE

Apple Inc.

RC guarantees minimum 5ms to reach 0.5V

SYNC_MASTER=J13_MLB_NON_POR

0201

C3816 1
10%
6.3V

19

B1
C1

1.0UF

SOT563

20.3 mOhm Typ


28.6 mOhm Max

1.0UF

SSM6N37FEAPE

0201

R(on)
@ 1.0V

VOUT

CRITICAL

U3815

C1

1.0UF

VIN

=PP1V05_TBTCIO_FET
A1

C2

B1

CRITICAL
C3815 1

B2

5%
1/20W
MF
201 2

Max Current = 2A (85C)

CSP

A2

100K

TPS22924

=PP1V05_S0_P1V05TBTFET

IN

U3820

TPS22920

R38201

U3815

TBT_SW_RESET_L

1.05V TBT "CIO" Switch

=PP1V05_S0_P1V05TBTFET
=PP3V3_TBTLC_RTR

D1

36 7
36 35 34 7

5%
1/20W
MF

2 201

10%
16V
X7R-CERM
0201

TBT_EN_LC_ISOL

36.5K

100K

WF: C value may need tuning.

330PF
2

R38161
1%
1/20W
MF
201 2

SSM6N37FEAPE
SOT563

0201

R3830

Q3825
TPS3808G25
Vt = 2.33V +/- 2%
Delay = 27.3ms

7 16 17 18 19 25

34

TBT_EN_LC_3V3

5%
1/20W
MF
201

C3810 1
10%
6.3V

C1

CRITICAL

TPS3808

Max Current = 2A (85C)

B1

R3811

A1

VOUT

RESET*

VIN

U3830

B2

SENSE

CSP

A2

=PP3V3_TBTLC_FET

TPS22924

Pull-up: R3610

VDD

U3810

=PP3V3_S0_P3V3TBTFET

3.3V TBT "LC" Switch


7

CRITICAL

35 34 7

BRANCH
PAGE

38 OF 109

SHEET

36 OF 73

3V S3 WLAN FET
MOSFET

TPCP8102

CHANNEL

P-TYPE

RDS(ON)

20-30 MOHM @2.5V

LOADING

0.750 A (EDP)

CRITICAL

Q4050

CRITICAL

DMP2018LFK

R4052

DFN2563-6

F-RT-SM1

P3V3WLAN_SS

5%
1/20W
MF
2 201

R4050
1

100K 2

PM_WLAN_EN_L
IN

62

5%
1/20W
MF
201

10%
16V
X5R-CERM
0201

PLACEMENT_NOTE=Place close to Q4050.

WIFI_EVENT_L

10K

10%
16V 2
X5R
402

0.1UF

PLACEMENT_NOTE=Place close to Q4050.

C4050

J4001

SSD-K99

R4051

0.033UF

20%
10V
2 X5R
603

37

C4051 1

10UF

10%
6.3V 2
X5R
201

CRITICAL

C4020

0.1UF

C4021 1

=PP3V3_S3_WLAN 7

AIRPORT

1% MIN_LINE_WIDTH=20 mm
0.25W MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=20 mm
mm
MF-LF VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
805
VOLTAGE=3.3V
2 PP3V3_WLAN_R
42 37 6 PP3V3_WLAN_F1
3
4

1
2

0.020

6 41 42

OUT

3
4
5

69 6

PCIE_AP_R2D_N

1
10%

2
6.3V

C4030

0.1UF
201 X5R

IN

16 69

IN

16 69

ISNS_AIRPORT_P
ISNS_AIRPORT_N

OUT

46 72

OUT

46 72

PLACEMENT_NOTE=Place close to J4001.

PLACEMENT_NOTE=Place close to J4001.

10

69 6

C4031
1
2

PCIE_AP_R2D_P

11

0.1UF

10%

PCIE_AP_R2D_C_P

6.3V X5R 201

BTPWR:S4
PP3V3_S3RS4_BT_F

12

NOSTUFF

13

PCIE_CLK100M_AP_N

IN

6 16 69

PCIE_CLK100M_AP_P

IN

6 16 69

14

15K

15

SSM3K15FV

R4018 1

R4017

5%
1/20W
MF
201

C4010

0.1UF
2

VCC

16

19

OUT

6 16 69

OUT

6 16 69

NOSTUFF
1

20

PCIE_WAKE_L

21

OUT

6 17

514S0335

R4015

Y+

Y-

10%
6.3V
X5R
201

15K

1%
1/20W
MF
201

1%
1/20W
MF
201

TQFN

R4016

15K

U4010

M+

68

USB_BT_WAKE_P

M-

68

USB_BT_WAKE_N

D+

USB_BT_P

BI

24 68

D-

USB_BT_N

BI

24 68

PI3USB102ZLE

NOSTUFF

CRITICAL

SEL

10

OE*

OUT

42

R4014

BTPWR:S4
1

GND

NOSTUFF
1

R4012
15K

1%
1/20W
MF
201

R4013
15K

1%
1/20W
MF
201

1%
1/20W
MF
201

PCIE_AP_D2R_P
PCIE_AP_D2R_N

18

15K

17

SOD-VESM-HF

NOSTUFF

1%
1/20W
MF
201

=BT_WAKE_L

Q4010

6 37

BTPWR:S3

PCIE_AP_R2D_C_N

BTPWR:S4

R4011
41 26 17
62 49

PM_SLP_S4_L

IN

BTMUX_SEL

5%
1/20W
MF
201

BLUETOOTH
68 6
68 6

SEL

NOSTUFF

C4011

10%
16V
X7R-CERM
0402

L
H

0.01UF

USB_BT_CONN_N
USB_BT_CONN_P

BTPWR:S4

OUTPUT
USB_BT_WAKE
USB_BT

R4001

37 6

PP3V3_S3RS4_BT_F

MIN_LINE_WIDTH=0.5 mm

=PP3V3_S4_BT

5%
1/16W
MF-LF
402

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

BTPWR:S3

=PP3V3_S3_WLAN

R4002
1

C4032

0.1UF

=PP3V3_S3_BT

42 37 6

DLY = 60 MS +/- 20%

5%
1/16W
MF-LF
402

10%
2 6.3V
X5R
201

7 37

PP3V3_WLAN_F

C4053 1
0.1UF

10%
6.3V 2
X5R
201

CRITICAL
VDD

PLACE_NEAR=J4001.18:1.5mm

U4002

R40531 R40541
100K

5%
1/20W
MF
201 2

SLG4AP016V

232K

TDFN
2 SENSE
+
0.7V -

1%
1/20W
MF
201 2

P3V3WLAN_VMON

R40551

AP_CLKREQ_Q_L

4 RESET*

IN

25

AP_PWR_EN

IN

18 23 62

R4090
AP_CLKREQ_L_R
MR* 3

AP_CLKREQ_L

GND
SYNC_MASTER=J11_MLB

SYNC_DATE=10/11/2011

PAGE TITLE

1%
1/20W
MF
201 2

X21 WIRELESS CONNECTOR


DRAWING NUMBER

Apple Inc.

051-9277

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

2.8.0

16

(OD)

THRM
PAD

100K

OUT

5%
1/20W
MF
201

EN 6
OUT 8

7 IN
5

AP_RESET_CONN_L

DLY

AP_RESET_L

BRANCH
PAGE

40 OF 109

SHEET

37 OF 73

D
CRITICAL

R4599
0.002

PLACE_NEAR=J4501.1:3mm

CRITICAL

L4500

FERR-70-OHM-4A
6

PP3V3_S0_SSD_FLT

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.150mm
VOLTAGE=3.3V

C4504

100UF
2

20%
6.3V
CERM-X5R
1206-1

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.150mm
VOLTAGE=3.3V

2
0603

NOSTUFF

PP3V3_S0_SSD_R

C4503

100UF
2

C4501

0.1UF

20%
6.3V
CERM-X5R
1206-1

2
4

1%
1W
MF
0612

=PP3V3_S0_SSD

ISNS_SSD_P
ISNS_SSD_N

C4502
0.1UF

10%
10V
X5R-CERM
0201

1
3

OUT

46 72

OUT

46 72

10%
10V
X5R-CERM
0201

=PP3V3_S0_SATAMUX

514S0393

J4501
R4505

6 8 66

CBTL02043ABQ
PCIE_SSD_R2D_C_P<1>

10% 16V

IN

8 66

IN

8 66

0201

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_N<1>

0201

3
4

A0_P
A0_N

7
8

A1_P
A1_N

9
IN

6 16 66

IN

6 16 66

SATAMUX_EN_L

6 16

IN

6 25

OUT

6 41

IN

6 41
42

10K

5%
1/20W
MF
2 201

C4518

0.1UF

C4517

0.1UF

B1_P 17
B1_N 16

66 PCIE_SSD_D2R_MUX_OUT_N

C1_P 13
C1_N 12

2
10%

66 PCIE_SSD_R2D_MUX_IN_P

C4513

0.1UF

66 PCIE_SSD_R2D_MUX_IN_N

0.1UF

68 SATA_SSD_D2R_MUX_OUT_P

68 SATA_SSD_D2R_MUX_OUT_N

68 SATA_SSD_R2D_MUX_IN_P

C4516
C4515
C4511

=P3V3S0_EN

IN

61 62
68 SATA_SSD_R2D_MUX_IN_N

C4510

OUT

8 66

PCIE_SSD_R2D_C_P<0>

IN

8 66

PCIE_SSD_R2D_C_N<0>

IN

8 66

16V
0201
X5R-CERM

16V
0201
X5R-CERM

0.01UF
0.01UF

0.01UF

0.01UF

5%
1/20W
MF
201

27
28
29
30
31
32
33
34
35

8 66

PCIE_SSD_D2R_N<0>

2
10%

OUT

16V
0201
X5R-CERM

2
10%

C4512

PCIE_SSD_D2R_P<0>

16V
0201
X5R-CERM

SATA_HDD_D2R_P

10%

16V
0201
X5R-CERM

10%

16V
0201
X5R-CERM

10%

16V
0201
X5R-CERM

10%

16V
0201
X5R-CERM

SATA_HDD_D2R_N

R4520
1

6 SSD_P3V3S0_EN

10%
16V
X5R-CERM
0201

C0_P 15
C0_N 14

XSD

R4510

IN

CRITICAL

5
11
20

SSD_CLKREQ_L
SSD_RESET_L
SATA_PCIE_SEL
SMC_OOB1_RX_L
SMC_OOB1_TX_L

B0_P 19
B0_N 18

SEL

19
20
21
22
23
24
25
26

VQFN

THRM
PAD

C4519
0.01UF

10%

U4510

66 PCIE_SSD_D2R_MUX_OUT_P

21

PCIE_SSD_R2D_P<1>

6 8 66

OUT

10%
10V
X5R-CERM
0201

PLACE_NEAR=U4510.1:2 mm

5%
1/20W
MF
2 201
OUT

C4514
0.1UF

PLACE_NEAR=U4510.10:2 mm
PLACE_NEAR=U4510.6:2 mm

470K

VDD 1
VDD 10
VDD 6

1
2
3
4 GND_VOID=TRUE
PCIE_SSD_D2R_P<1>
5 GND_VOID=TRUE
PCIE_SSD_D2R_N<1>
6
7 GND_VOID=TRUE 68 6 SATA_SSD_D2R_P
8 GND_VOID=TRUE 68 6 SATA_SSD_D2R_N
9
C4521 0.1UF
66 6
10 GND_VOID=TRUE
X5R-CERM
11 GND_VOID=TRUE 666
C4520 0.1UF 1
2
12
X5R-CERM
10% 16V
13 GND_VOID=TRUE68 6 SATA_SSD_R2D_P
14 GND_VOID=TRUE68 6 SATA_SSD_R2D_N
15
16
PCIE_CLK100M_SSD_P
17
PCIE_CLK100M_SSD_N
18

10%
10V
X5R-CERM
0201

Per PCIe Spec, only TX side should have AC cap

F-RT-SM

VSS
VSS
VSS

SSD-J5

C4505
0.1UF

CRITICAL

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

OUT

16 68

OUT

16 68

IN

16 68

IN

16 68

353S3361

PCIE/SATA GUMSTICK2 CONNECTOR


A

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=10/17/2011

PAGE TITLE

SSD CONNECTOR
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

45 OF 109

SHEET

38 OF 73

Right USB Port A

USB Port Power Switch

CRITICAL
CRITICAL

U4600

L4605

TPS2561DR

FERR-120-OHM-3A

SON
2

IN_0
IN_1

23

OUT

USB_EXTA_OC_L

10

C4690

20%
6.3V
CERM-X5R
0402-2

10UF

C4691

10%
16V
X5R-CERM
0201

20%
2 6.3V
POLY-TANT
CASE-B2-SM1

0.1UF

USB_EN2

CRITICAL

EN1
EN2
GND

R46011

C4696

220UF-35MOHM

0
5%
1/20W
MF
201

PP5V_S3_RTUSB_A_ILIM

9
8
7

THRM
PAD

62 40 6

FAULT1* ILIM
FAULT2*

NC
=USB_PWR_EN

OUT1
OUT2

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=5V

NC

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

0603

C4605

USB_ILIM

0.01UF

10%
16V
X5R-CERM
0201

CRITICAL

CRITICAL

DLP0NS

USB3.0-J11-J13

L4600
90-OHM

J4600
F-RT-TH

SYM_VER-1

R4600 1
23.2K

11

=PP5V_S3_RTUSB

1%
1/16W
MF-LF
402

C4695

20%
6.3V
CERM-X5R
0402-2

68

USB2_EXTA_MUXED_N

10UF

68
68

USB2_EXTA_MUXED_P

68

USB2_EXTA_MUXED_F_N
USB2_EXTA_MUXED_F_P

68
68

USB3_EXTA_TX_F_P
USB3_EXTA_TX_F_N

Current limit per port (R4600): 2.18A min / 2.63A max

NC
IO
NC
IO

2 5 3 4
6 VBUS

68

1 GND
68

USB3_EXTA_RX_F_P
USB3_EXTA_RX_F_N

D4600

VBUS
SSTX+
SSTXGND
DD+
GND
SXRX+
SSRXGND

11
12
13
14
15
16
17
18

RCLAMP0582N

1
2
3
4
5
6
7
8
9
10

SLP1210N6
CRITICAL

GND_VOID=TRUE
CRITICAL

L4610
80OHM-25%-100MA
0504

L2

Mojo SMC Debug Mux


7

68 18

OUT

USB3_EXTA_RX_N

68 18

OUT

USB3_EXTA_RX_P

L1

=PP3V42_G3H_SMCUSBMUX

CRITICAL

MOJO:YES
1

MOJO:YES
1

0.1UF

68 42 41

IN

68 42 41

OUT

SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L

10%
10V
X5R-CERM
0201

2
5

M+

M-

U4650

Y+

Y-

68 18

BI

68 18

BI

USB_EXTA_P
USB_EXTA_N

D+
D-

CRITICAL
MOJO:YES

L4620
SEL

SMC_DEBUGPRT_EN_L

10

GND
3

TSSLP-2-1
1

GND_VOID=TRUE
CRITICAL

TQFN

OE*

CRITICAL

D4621

ESD0P2RF-02LS

PI3USB102ZLE
7

TSSLP-2-1

5%
1/20W
MF
2 201

VCC

ESD0P2RF-02LS

10K

C4650

D4620

R4650

SIGNAL_MODEL=MOJO_MUX

41

SEL=0 Choose SMC


SEL=1 Choose USB

C4620

68 18

IN

IN

USB3_EXTA_TX_N

USB3_EXTA_TX_P

R4651
0

L2

0.1UF

MOJO:NO

5%
1/20W
MF
201

0504

GND_VOID=TRUE

68 18

10% 6.3V
X5R 201

68

USB3_EXTA_TX_C_N

68

USB3_EXTA_TX_C_P

C4621
1

CRITICAL

D4610

ESD0P2RF-02LS

MOJO:NO

CRITICAL

D4611

ESD0P2RF-02LS

TSSLP-2-1

R4652
0

L1

GND_VOID=TRUE

0.1UF

10% 6.3V
X5R 201

80OHM-25%-100MA
IN

TSSLP-2-1
1

5%
1/20W
MF
201

SYNC_MASTER=J11_MLB

SYNC_DATE=09/30/2011

PAGE TITLE

External A USB3 Connector


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

46 OF 109

SHEET

39 OF 73

=PP3V3_S0_AUDIO

7 6

7 6

=PP3V42_G3H_ONEWIRE

CRITICAL

J4700

ON MLB SIDE AS LIO CANT FIT CAPS

DF40CG3.0-48DS-0.4V
F-ST-SM
49
50

C4721
GND_VOID=TRUE

(Right Speaker Enable)

42 41 6

IN

62 39 6

IN

18 6
7 6

OUT

1
3
5
7
9
11
13
15

SMC_BC_ACOK
=USB_PWR_EN
AUD_I2C_INT_L

=PP3V3R1V5_S0_AUDIO
44 6

BI

44 6

BI

=I2C_LIO_SDA
=I2C_LIO_SCL

2
4
6
8
10
12
14
16

68 6

23
16 6
69
41 6
42
49

BI
OUT
IN
IN
OUT

19
21
23
25
27
29
31

SYS_ONEWIRE
USB_EXTB_OC_L
HDA_RST_L
SMC_LID
AUD_GPIO_3

20
22
24
26
28
30
32

USB3_EXTB_TX_C_N

0.1UF

GND_VOID=TRUE

BI

44 6

BI

69 16 6

IN

69 16 6

IN

69 16 6

IN

69 16 6

IN

35
37
39
41
43
45
47

=I2C_MIKEY_SDA
=I2C_MIKEY_SCL
HDA_SYNC
HDA_SDIN0
HDA_BIT_CLK
HDA_SDOUT

36
38
40
42
44
46
48

SPKRAMP_INR_N
SPKRAMP_INR_P

OUT

6 51 72

IN

6 51 72

CRITICAL

D4720

AUD_IP_PERIPHERAL_DET
AUD_IPHS_SWITCH_EN

6 18

OUT

6 25

0.1UF

10%
16V
X5R-CERM 2
0201

C4710

PLACE_NEAR=J4700.17:1.5mm

USB3_EXTB_TX_P

CRITICAL

OUT

18 68

0.1UF

D4721
TSSLP-2-1

GND_VOID=TRUE

USB_CAMERA_N
USB_CAMERA_P

BI

6 18 68

BI

6 18 68

R4710
0

USB_EXTB_P
USB_EXTB_N

BI

6 24 68

BI

6 24 68

2
201

NOSTUFF

C4731

GND_VOID=TRUE
68 6

USB3_EXTB_RX_RC_N

GND_VOID=TRUE

X5R-CERM
10%
16V

GND_VOID=TRUE

USB3_EXTB_RX_N

IN

18 68

USB3_EXTB_RX_P

IN

18 68

0201

0.1UF
NOSTUFF

0.1UF
10%
16V
X5R-CERM
0201

X5R-CERM
10%
16V
0201

ESD0P2RF-02LS

TSSLP-2-1

OUT

USB3_EXTB_TX_C_P

C4732GND_VOID=TRUE

PLACE_NEAR=J4700.7:1.5mm

C4720

18 68

GND_VOID=TRUE
68 6

1/20W 5%
MF
44 6

OUT

C4722

GND_VOID=TRUE

ESD0P2RF-02LS
41 6

USB3_EXTB_TX_N

X5R-CERM
10%
0201
16V

51
1

52

CRITICAL

C4700

D4710

0.1UF

2
2

10%
16V
X5R-CERM
0201

ESD0P2RF-02LS

998-4617

CRITICAL

68 6

D4711

USB3_EXTB_RX_RC_P

10%

2 X5R-CERM
0201

0.1UF

ESD0P2RF-02LS

TSSLP-2-1

16V

TSSLP-2-1

GND_VOID=TRUE

PLACE_NEAR=J4700.9:1.5mm

R4720

1/20W 5%
MF

2
201

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

PAGE TITLE

Left I/O (LIO) Connector


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

47 OF 109

SHEET

40 OF 73

D
U4900
LM4FSXAH5BB
69 43 16 6

BI

69 43 16 6

BI

69 43 16 6

BI

69 43 16 6

BI

69 25

IN

69 43 16 6

IN

25

IN

43 16 6

BI

43 17 6

OUT

43 25 17 6
19

OUT

19

OUT

71 44

BI

71 44

BI

71 44

BI

71 44

BI

71 44

BI

71 44

BI

71 44

BI

71 44

BI

42

BI

42

BI

71 44

BI

71 44

BI

48

OUT

48

IN

42

OUT

42

IN

42

OUT

42

OUT

49

OUT

42

OUT

42

IN

BI

40 6

IN

42

IN

42

IN

42

BI

42

OUT

42

IN

42

IN

49 42 6

IN

42
62 42

IN
OUT

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_CLK33M_SMC
LPC_FRAME_L
SMC_LRESET_L
LPC_SERIRQ
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_RUNTIME_SCI_L
SMC_WAKE_SCI_L
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_4_ASF_SCL
SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMC_FAN_0_CTL
SMC_FAN_0_TACH
SMC_FAN_1_CTL
SMC_FAN_1_TACH
SMC_MPM5_LED_PWR
SMC_MPM5_LED_CHG
SMC_SYS_KBDLED
SMC_T25_EN_L
SYS_TDM_ONEWIRE
SYS_ONEWIRE
HISIDE_ISENSE_OC
SMC_ODD_DETECT

B13
A13
C12
D11
H12
D12
C13
H13
G11
F13
F12
B12

(OD)
(OD)

(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
NC FOR ENG PKG
NC FOR ENG PKG
(OD)
(OD)

NC FOR STACK BRD


NC FOR STACK BRD

42

IN
OUT

42

IN

42 40 6

IN

42

IN

62 26 17

IN

62 49 37 26 17

IN

62 17

IN

49 42 6

IN

43 42 6

IN

43 42 6

OUT

68 24

BI

68 24

BI

H11
L13
C11
A12
G3

PM6/FAN0PWM0
PM7/FAN0TACH0
PK6/FAN0PWM1
PK7/FAN0TACH1
PN2/FAN0PWM2
D10 PN3/FAN0TACH2
PN4/FAN0PWM3
PN5/FAN0TACH3
PN6/FAN0PWM4
PN7/FAN0TACH4
J4 PH2/FAN0PWM5
J2 PH3/FAN0TACH5

(OD)

CPU_PECI_R
SMC_PECI_L

AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23

E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8

SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7
SMC_ADC8
SMC_ADC9
SMC_ADC10
SMC_ADC11
SMC_ADC12
SMC_ADC13
SMC_ADC14
SMC_ADC15
SMC_ADC16
SMC_ADC17
SMC_ADC18
SMC_ADC19
SMC_ADC20
SMC_ADC21
SMC_ADC22
SMC_ADC23

C0C0+
C1PC5/C1+
T3CCP1/PJ5/C2T3CCP0/PJ4/C2+

K2
K1
L2
L1
C5
D5

CPU_PROCHOT_L
SMC_VCCIO_CPU_DIV2
SMC_S5_PWRGD_VIN

SSI0CLK/PA2
SSI0FSS/PA3
SSI0RX/PA4
SSI0TX/PA5

M2
M3
L4
N1

SMC_PM_G2_EN
PM_DSW_PWRGD
SMC_DELAYED_PWRGD
SMC_PROCHOT

U1RX/B0
U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7

F11
E11
F4
F3

SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
SMC_SYS_LED
SMC_GFX_THROTTLE_L

SSI1RX/PF0
SSI1TX/PF1
SSI1CLK/PF2
SSI1FSS/PF3
PF4
PF5

M9
N9
L10
K10
L9
K9

SPI_SMC_MISO
NC
SPI_SMC_MOSI
NC
SPI_SMC_CLK
NC
SPI_SMC_CS_L
NC
S5_PWRGD
PM_PCH_SYS_PWROK

I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
I2C2SCL
I2C2SDA
I2C3SCL
I2C3SDA
I2C4SCL
I2C4SDA
I2C5SCL
I2C5SDA

L11
N12
N11
M11

C4 PECI0RX
C6 PECI0TX

SMC_BIL_BUTTON_L
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
SMC_PME_S4_DARK_L
SMC_S4_WAKESRC_EN

M13
L12
M5
J12

NC FOR ENG PKG


49 42 40 6

E10
D13
M4
N2
N8
M8
L8
K8
N7
M7
N4
N3

BGA
LPC0AD0
(1 OF 2)
LPC0AD1
LPC0AD2 OMIT_TABLE
LPC0AD3
LPC0CLK
LPC0FRAME*
LPC0RESET*
LPC0SERIRQ
LPC0CLKRUN*
LPC0PD*
LPC0SCI*
PK5

SMC_LID
ENET_ASF_GPIO
SMS_INT_L
SMC_BC_ACOK
G3_POWERON_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_ONOFF_L

J13
L5
NC
D8
NC
K6
D4
E4
F5
N5
N6
K5
M6
L6

(OD)

PP0/IRQ116
PP1/IRQ117
PP2/IRQ118
PP3/IRQ119
PP4/IRQ120
PP5/IRQ121
PP6/IRQ122
PP7/IRQ123
PQ0/IRQ124
PQ1/IRQ125
PQ2/IRQ126
PQ3/IRQ127
PQ4/IRQ128
PQ5/IRQ129
PQ6/IRQ130
PQ7/IRQ131

PM_PWRBTN_L
PM_SYSRST_L
MEM_EVENT_L
SMC_ADAPTER_EN

T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3

C9
B9
A9
C8

SMC_OOB1_RX_L
SMC_OOB1_TX_L
IR_RX_OUT_RC
BDV_BKL_PWM

L3 U0RX
M1 U0TX

SMC_RX_L
SMC_TX_L
USB_SMC_N
USB_SMC_P

E13 USB0DM
E12 USB0DP

WT5CCP1/PM3 H10

SMC_BATLOW_L

42

IN

42

IN

42

IN

42

IN

42

IN

42

IN

42

NC FOR STACK BRD

IN

42

IN

42

IN

42

IN

42

IN

42

NC FOR STACK BRD

IN

42

NC FOR STACK BRD

IN

42

NC FOR STACK BRD

IN

42

NC FOR STACK BRD

IN

42

NC FOR STACK BRD

=PP3V3_S5_SMC

L4901

20%
2 6.3V
X5R
0201

IN
IN

42

IN

42

IN

10 42 57 66

0.1UF

10%
2 10V
X5R-CERM
0201

C4905
0.1UF

10%
2 10V
X5R-CERM
0201

R4902

C4906

1M

0.1UF

IN

C4908
0.1UF

10%
2 10V
X5R-CERM
0201

BI

C4909
0.1UF

10%
2 10V
X5R-CERM
0201

69 42

IN

42

42

OUT

62

OUT

17

OUT

25 36 42

OUT

42

IN

39 42 68

OUT

39 42 68

OUT

G10 RST*

WIFI_EVENT_L (OD)
SMC_WAKE_L
NC_SMC_HIB_L

B11
N13
M12

SMC_CLK32K
NC_SMC_XOSC1

M10

SMC_EXTAL
SMC_XTAL

G12
G13

N10

K12
D7
E6
E8
E9
F10
J7
J9
J10
42

42

IN

FOR STACK BRD

OUT

42 69

FOR STACK BRD

OUT

FOR STACK BRD

OUT

0.1UF

BGA
(2 OF 2)
SWCLK/TCK
SWDIO/TMS
PK4/RTCCLK
SWO/TDO
WAKE*
TDI
HIB*
OMIT_TABLE NC
XOSC0
XOSC1
VDDA
OSC0
OSC1
VREFA+
VREFAVBAT

SMC_RESET_L

GNDA

VDD

GND

J1
J6

PP1V2_S5_SMC_VDDC
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=1.2V

K13
D6

C4901

10%
2 10V
X5R-CERM
0201

LM4FSXAH5BB

25

42

U4900

5%
1/20W
MF
2 201

10%
2 10V
X5R-CERM
0201

PP3V3_S5_SMC_VDDA
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V

42

IN

VDDC

C10
A10
A11
B10
A2

SMC_TCK
SMC_TMS
SMC_TDO
SMC_TDI

6 42 43
6 42 43
6 42 43

6 42 43

NC

D3

PP3V3_S5_AVREF_SMC

D2
D1
C3
E3

42

XW4900
SM

46
45
42

GND_SMC_AVSS

PLACE_NEAR=U4900.A1:4MM

A1
C7
D9
E5
F9
H5
H9
J5
J8
J11

1 C4920

C4921

1UF

0.01UF

10%
10V
X5R
201

20%
6.3V
0201

2 X5R

PLACE_NEAR=U4900.D2:1MM
PLACE_NEAR=U4900.D1:1MM
PLACE_NEAR=U4900.D2:1MM
PLACE_NEAR=U4900.D1:1MM

K11

42 69
42 69

IN

62

IN

17 23 25

OUT

39

IN

42

B
1

23 25 52 62

OUT

42

OUT

17 23

C4910

C4911

C4912

1.0UF

1.0UF

1.0UF

20%
10V
X5R-CERM
0201-1

20%
10V
X5R-CERM
0201-1

20%
10V
X5R-CERM
0201-1

C4913
0.1UF

10%
2 10V
X5R-CERM
0201

C4914
0.1UF

10%
2 10V
X5R-CERM
0201

C4915
0.1UF

10%
2 10V
X5R-CERM
0201

C4916
0.1UF

10%
2 10V
X5R-CERM
0201

C4917
0.1UF

10%
2 10V
X5R-CERM
0201

NOSTUFF

17 25
42

IN

17 42 62

IN

6 38

OUT

C4904

42

42 69

NC FOR ENG PKG

C4907

10%
2 10V
X5R-CERM
0201

10 66

BI

10%
2 10V
X5R-CERM
0201

0.1UF

IN

OUT

0.1UF

FOR STACK BRD

(OD)

C4903

42 37 6

NC FOR STACK BRD

IN

53 43 42 6

42

BI

C4902
1UF

42

OUT

2
0402

IN

1.2V FOR ENG PKG

7 42

30-OHM-1.7A

NC FOR STACK BRD

ALL_SYS_PWRGD
SMC_THRMTRIP

J3
H4
H3
G4

42

IN

42

SMC_DEBUGPRT_EN_L
SMC_GFX_OVERTEMP

WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7

42

IN

IN

CPU_CATERR_L
CPU_THRMTRIP_3V3

WT2CCP0/PH0 K3
WT2CCP1/PH1 K4

42

IN

NC FOR STACK BRD

SPI_DESCRIPTOR_OVERRIDE_L

WT0CCP0/PG4 K7
WT0CCP1/PG5 L7

IN

6 38 42

NC FOR ENG PKG

IN

NC FOR ENG PKG

OUT

42

OUT

42 62

NOTE:
SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.

NOTE:
Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

SYNC_MASTER=J13_MLB_NON_POR
PAGE TITLE

SYNC_DATE=10/17/2011

SMC
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

49 OF 109

SHEET

41 OF 73

SMC Reset "Button", Supervisor & AVREF Supply


42 41 7
7

=PP3V3_S5_SMC
=PPVIN_S5_SMCVREF

C5020 1
0.47UF

V+

10%
6.3V
CERM-X5R 2
402
IN

49 42 41 6

IN

SMC_TPAD_RST_L
SMC_ONOFF_L

R5001

OUT

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

CRITICAL REFOUT
THRM

6 41 43 53

41

C5025 1

0.01UF

10%
10V
2 X5R
201

20%
10V
X5R-CERM 2
0402-1

SILK_PART=SMC_RST

C5026

10UF

10%
10V 2
X5R
201

GND_SMC_AVSS

PLACEMENT_NOTE=Place R5001 on BOTTOM side

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V

MR1* and MR2* must both be low to cause manual reset.


Used on mobiles to support SMC reset via keyboard.
NOTE: Internal pull-ups are to VIN, not V+.

OMIT

R50161
PLACE_SIDE=TOP

OUT

5%
1/10W
MF-LF
603 2

PLACE_SIDE=BOTTOM

5%
1/10W
MF-LF
2 603

SILK_PART=PWR_BTN

41

SMC_ADC5

41

SMC_ADC6

41

SMC_ADC7

41

SMC_ADC8

Y5010

3.2X2.5MM-SM
1

3
2

12PF

C5011

SMC_PBUS_VSENSE

45

SMC_HDD_ISENSE

46

SMC_BMON_ISENSE

46

SMC_ADC11

41

SMC_ADC12

41

SMC_ADC13

SMC_OTHER_HI_ISENSE

46

SMC_1V5S3_ISENSE

46

SMC_CPUVCCIO_ISENSE

45

SMC_GFX_VSENSE

45

SMC_CPU_SA_ISENSE

45

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

SMC_ADC14

41

SMC_ADC15

41

SMC_ADC16

41

SMC_ADC17

41

SMC_ADC18

41

SMC_ADC19

41

SMC_ADC20

SMC_3V3S0_ISENSE

MAKE_BASE=TRUE

SMC_WLAN_ISENSE

46

SMC_LCDBKLT_ISENSE

46

MAKE_BASE=TRUE
MAKE_BASE=TRUE

69 17

=PPVCCIO_S0_SMC

G 2
IN

Q5050

41

SSM3K15AMFVAPE
46

OUT

PM_THRMTRIP_L_R

41

SOT563

CRITICAL
S

IN

SMC_PECI_L

45

1NOSTUFF

R5053

IN

41 42

41

NC_SMC_ADC21

R5058

MAKE_BASE=TRUE

PM_THRMTRIP_R_L 1

NC_SMC_ADC22
SMC_ADC23

41 42

MAKE_BASE=TRUE

SMC_FAN_1_TACH

41

ENET_ASF_GPIO

41

SMC_MPM5_LED_PWR

41

SMC_MPM5_LED_CHG

41

SYS_TDM_ONEWIRE

3.3K 2

PM_THRMTRIP_L IN

69 41

IN

SPI_SMC_MOSI

10 19 66

PLACE_NEAR=R2170.2:5mm

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

MAKE_BASE=TRUE

NC_ENET_ASF_GPIO

SMC12
Eng Pkg Support
Eng Package requires 1.2V ON SMC_ADC23 pin.

MAKE_BASE=TRUE

NC_SMC_MPM5_LED_PWR

MAKE_BASE=TRUE
MAKE_BASE=TRUE

42 7

NC_SYS_TDM_ONEWIRE

MAKE_BASE=TRUE

NC_SMC_DP_HPD_L
SMC_BC_ACOK

41

SMBUS_SMC_4_ASF_SCL

41

SMBUS_SMC_4_ASF_SDA

R5099

6 40 41 42

MAKE_BASE=TRUE

41

NC_HISIDE_ISENSE_OC
NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

SMC_ADC23

42 41

42 41

5%
1/20W
MF
2 201

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

41 38 6
49 42 41 6

SMC_PACKAGE:ENG

MAKE_BASE=TRUE

BDV_BKL_PWM

NC_BDV_BKL_PWM

SMC_PME_S4_DARK_L

SDCONN_STATE_CHANGE_SMC

41
49 41 40 6

MAKE_BASE=TRUE

MAKE_BASE=TRUE

43 41 6
33
43 41 6

SMC_T25_EN_L

IN

34

68 41 39
42 7

NC_SMC_T25_EN_L

=PPVCCIO_S0_SMC

68 41 39

MAKE_BASE=TRUE

PM_CLK32K_SUSCLK_R 1

R5012
22

PLACE_NEAR=U1800.D3:5.1mm

43 41 6

R5097

5%

1/20W

43 41 6

100K

SMC_CLK32K

OUT

MF 201

SPI_SMC_CLK

43 41 6

1%
1/20W
MF
2 201

41 69

SMC_VCCIO_CPU_DIV2

43 41 6
41
42 41 40 6
41
41

R5096
100K

41

1%
1/20W
MF
2 201

42 41

43 6

SMC_ODD_DETECT
SMC_PME_S4_DARK_L

R5066 33K
R5067 100K

SMC_OOB1_TX_L
SMC_ONOFF_L
G3_POWERON_L
SMC_LID
SMC_TX_L
SMC_RX_L
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMC_S5_PWRGD_VIN
SMS_INT_L

R5068
R5070
R5072
R5071
R5073
R5074
R5075
R5076
R5077
R5078
R5079
R5080
R5081
R5087
R5092
R5093
R5014
R5017

MEM_EVENT_L
CPU_THRMTRIP_3V3

R5024
69 41

IN

SPI_SMC_CS_L

15

5%
1/20W
MF
201

5%
1/20W
MF
201

43 50 69

SPI_MLB_MOSI

PLACE_NEAR=U6100.5:1MM

OUT

43 50 69

62 41 17

42 41

SPI_MLB_CLK

PLACE_NEAR=U6100.6:1MM

SPI_MLB_CS_L

PLACE_NEAR=U6100.1:1MM

OUT

OUT

43 50 69

BATLOW# Isolation

43 50 69

=PP3V3_S5_SMCBATLOW

62 41

SMC_S4_WAKESRC_EN

MF

201

1/20W

MF

201

1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W

MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF

201
201
201
201
201
201
201
201
201
201
201
201
201
201
201
201

5%

1/20W
1/20W

MF
MF

201
201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

STUFF
100K NO
1
2
10K 1
2 5%
10K 1
2 5%
100K 1
2 5%
10K 1
2 5%
100K 1
2 5%
10K 1
2 5%
100K 1
2 5%
5%
10K 1
2
10K 1
2 5%
5%
10K 1
2
10K 1
2 5%
10K 1
2 5%
5%
100K 1
2
100K 1
2 5%
10K 1
2 5%
5%
10KNO1 STUFF
2
100K 1
2 5%

10K

10K

100K

100K

PP3V3_WLAN_F
Module has 3.3K PU
NO STUFF
R5089 10K 1
2
WIFI_EVENT_L

62 41

5%
1/20W
MF
2 201

IN

SMC_BATLOW_L

5%
1/16W
MF-LF
402

1/20W

MF

201

SYNC_DATE=11/10/2011

SMC Support

G 1

VESM

DRAWING NUMBER

PM_BATLOW_L

OUT

NOSTUFF

Apple Inc.

17

Internal 20K pull-up on


PM_BATLOW_L in PCH.

R5041
6 41 49

5%

PAGE TITLE

100K

1/20W

5%

SYNC_MASTER=J13_MLB_NON_POR

Q5040

R5082

R5085
R5086
R5091
R5090

SSM3K15AMFVAPE

5%
1/20W
MF
201 2

SMC_THRMTRIP
SMC_DELAYED_PWRGD

CRITICAL

100K

7 42

OUT

SMC_ADAPTER_EN

5%
1/20W
MF
2 201

41 36 25

=PP3V3_SUS_SMC 7

R5040

MAKE_BASE=TRUE

5%

37 6

SMC_PME_S4_WAKE_L

1K

=BT_WAKE_L

R5088

OUT

41 37 6

37

SPI_MLB_MISO

=PP3V3_S4_SMC

NO STUFF

SMC_ROMBOOT

PLACE_NEAR=U6100.2:1MM

=PP3V3_S0_SMC

PP1V2_S5_SMC_VDDC

41

MAKE_BASE=TRUE

HISIDE_ISENSE_OC

15

=PP3V3_S5_SMC
42 41 7
=PP3V3_S4_SMC

NC_SMC_MPM5_LED_CHG

41

R5023

66
10
19

BI

From/To CPU/PCH

NC_SMC_GFX_OVERTEMP

=CHGR_ACOK

CPU_PECI

MAKE_BASE=TRUE

SMC_DP_HPD_L

5%
1/20W
MF
201

5%
1/20W
MF
201

5%
1/20W
MF
201

MAKE_BASE=TRUE

43

CPU_PECI_R

OUT

To SMC

R5021

IN

330

R5034
1

DFN1006-3

SMC12 SPI Support

69 41

R5051
5%
1/20W
MF

Q5058
MMBT3904LP-7

MAKE_BASE=TRUE

41

15

2 201

CRITICAL

NC_SMC_ADC20

SMC_FAN_1_CTL

R5022

5%
1/20W
MF
201

CPU_THRMTRIP_3V3

OUT

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_L

1%
1/20W
MF
201

S 2

1.6K

SMC_THRMTRIP

NC_SMC_ADC19

41

SPI_SMC_MISO

SMC_PECI_L_R

5%
1/20W
MF
201

From SMC

G 5

Series resistors are no stuffed until the


topology of 2 SPI Masters are verified.

IN

R5052

Q5059

SSM6N15AFE

41

69 41

D 3

VESM

42 41

SMC_GFX_ISENSE

MAKE_BASE=TRUE

41

24.9 2
1

7 42

CRITICAL
SMC_PROCHOT

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP

IN

NC_SCM_ADC17

41

41

CRITICAL

45

=TBT_WAKE_L

5%
2 25V
NP0-C0G-CERM
0201

SMC12 PECI Support

SOT563

19

MAKE_BASE=TRUE

Q5059

SSM6N15AFE

MAKE_BASE=TRUE

41

CPU_PROCHOT_L

BI

SMC_HS_COMPUTING_ISENSE

SMC_ADC10

12PF

5%
2 25V
NP0-C0G-CERM
0201

46

MAKE_BASE=TRUE

SMC_ADC9

42 41

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

41

41

C5010

45

MAKE_BASE=TRUE

SMC_ADC23

12.000MHZ-30PPM-10PF

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

41

53 45

45

MAKE_BASE=TRUE

42 41

Note:
ADC10 and ADC11 are shared
with comparators on Stack Board.

SMC_XTAL_R
CRITICAL

1%
1/20W
MF
201

SMC_ADC4

41

2.49K2

SMC_EXTAL

41

66 57 41 10
45

SMC_VCCSA_VSENSE

MAKE_BASE=TRUE

SMC_ADC22

R5010

41

SMC_ADC3

41

SILK_PART=PWR_BTN

SMC USB Clock require these crystal


values:5,6,8,10,12,16,18,20,24,25 MHz

41

41

45

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_ADC21

SMC Crystal Circuit

SMC_XTAL

SMC_ADC2

SMC_CPU_VSENSE

MAKE_BASE=TRUE

41

6 41 42 49

R5015
0

41

41

SMC_ADC1

41 45 46

Debug Power "Buttons"


SMC_ONOFF_L
OMIT

SMC_ADC0

PAD

GND

SMC_RESET_L

RESET* 5

PP3V3_S5_AVREF_SMC

0.01UF

5%
1/10W
MF-LF
2 603

5%
1/20W
MF
2 201

(IPU)

4 DELAY

C5001

DFN
(IPU)
SN0903048

U5010

100K

VREF-3.3V-VDET-3.0V
6 MR1*
7 MR2*

SMC_MANUAL_RST_L
OMIT

R5000

VIN

49 6

Desktops: 5V
Mobiles: 3.42V

41

41

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

50 OF 109

SHEET

42 OF 73

LPC+SPI Connector
LPCPLUS
CRITICAL

J5100

DF40C-30DP-0.4V
7 6
7 6

69 25 6
69 41 16 6

LPC_CLK33M_LPCPLUS
LPC_AD<0>

BI
BI

69 41 16 6

IN

69 41 16 6

OUT

69 41 16 6

LPC_AD<2>
LPC_AD<1>
LPC_AD<3>
SPI_ALT_MOSI
LPCPLUS_GPIO
LPCPLUS_RESET_L
SMC_TDO
TP_SMC_TRST_L
TP_SMC_MD1
SMC_TX_L

IN

43 6

OUT

19 6

OUT

69 25 6

IN

42 41 6

OUT
6
6

42 41 6

M-ST-SM
31
32

=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS

IN

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

33

34

SPI_ALT_MISO
LPC_FRAME_L
SPIROM_USE_MLB

6 43

IN

PM_CLKRUN_L
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
SMC_TMS

BI

6 16 41 69

BI

6 19 50

6 17 41

OUT
IN

6 43

IN

6 43
6 16 41

BI

6 17 25 41

IN
OUT

6 41 42

OUT

6 41 42

OUT

6 41 42 53

OUT

6 42

OUT

6 41 42

OUT

6 41 42

998-4235

SPI Bus Series Termination


SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L
LPCPLUS

LPCPLUS

R5128

24.9

43

1%
1/20W
MF
2 201

IN

SPI_CS0_R_L

R5111

PLACE_NEAR=U1800.AD12:5mm
69 16

IN

SPI_CLK_R

PLACE_NEAR=U1800.W8:5mm
69 16

IN

SPI_MOSI_R

R5112
1

15

15

15

OUT

R5126

R5125

43

43

5%
1/20W
MF
2 201

SPI_CS0_L

R5121
69

SPI_CLK

43

5%
1/20W
MF
201

R5122
69

SPI_MOSI

R5123

SPI_MISO

PLACE_NEAR=J5100.14:5mm
PLACE_NEAR=J5100.12:5mm
PLACE_NEAR=J5100.9:5mm

R5120
69

5%
1/20W
MF
201

6 43

5%
1/20W
MF
2 201

5%
1/20W
MF
201

5%
1/20W
MF
201
69 16

5%
1/20W
MF
2 201

6 43

LPCPLUS

R5110

PLACE_NEAR=U1800.AB8:5mm
69 16

LPCPLUS

R5127

6 43
6 43

24.9 2
1%
1/20W
MF
201

43

5%
1/20W
MF
201

43

5%
1/20W
MF
201

SPI_MLB_CS_L

OUT

42 50 69

OUT

42 50 69

SPI_MLB_MOSI

OUT

42 50 69

SPI_MLB_MISO

IN

42 50 69

SPI_MLB_CLK

PLACE_NEAR=R5125.2:5mm

PLACE_NEAR=R5126.2:5mm

2
PLACE_NEAR=R5127.2:5mm

PLACE_NEAR=U6100.2:5mm

SYNC_MASTER=J11_MLB

SYNC_DATE=09/08/2011

PAGE TITLE

LPC+SPI Debug Connector


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

51 OF 109

SHEET

43 OF 73

PCH S0 SMBus "0" Connections

1K

5%
1/20W
MF
201 2

(MASTER)

R5201
1K

5%
1/20W
MF
2 201

69 16 SMBUS_PCH_CLK

SMC

LED BACKLIGHT
U9701

4.7K

5%
1/20W
MF
201 2

U4900

(WRITE: 0x58 READ: 0x59)


(MASTER)
=I2C_BKL_1_SCL

65

71 41 SMBUS_SMC_0_S0_SCL

=I2C_BKL_1_SDA

65

71 41 SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

7 =PP3V42_G3H_SMBUS_SMC_BSA

R52501

R5251

Internal DP

4.7K

MAKE_BASE=TRUE

R52801

SMC

J9000
(See Table)

5%
1/20W
MF
2 201

63

71 41 SMBUS_SMC_5_G3_SCL

=I2C_TCON_SDA

63

71 41 SMBUS_SMC_5_G3_SDA

Battery Charger

2.0K

5%
1/20W
MF
201 2

(MASTER)

=I2C_TCON_SCL

R5281

2.0K

U4900

MAKE_BASE=TRUE

69 16 SMBUS_PCH_DATA

SMC "5" SMBus G3H Connections

7 =PP3V3_S0_SMBUS_SMC_0_S0

R52001

U1800

SMC "0" SMBus S0 Connections

44 7 =PP3V3_S0_SMBUS_PCH

Cougar-Point

5%
1/20W
MF
2 201

ISL6258 - U7000
(Write: 0x12 Read: 0x13)
=SMBUS_CHGR_SCL

53

=SMBUS_CHGR_SDA

53

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

VRef DACs

Battery

U3300

J6955

Battery

(Write: 0x98 Read: 0x99)

TBT

(See Table)

Battery Manager - (Write: 0x16 Read: 0x17)

31 =I2C_VREFDACS_SCL

=SMBUS_BATT_SCL

6 52

=SMBUS_BATT_SDA

6 52

U3600
31 =I2C_VREFDACS_SDA

(Write: 0xXXX Read: 0xXXX)


=I2C_TBTRTR_SCL

34

=I2C_TBTRTR_SDA

34

Margin Control

SMC "3" SMBus S3

U3301

31 =I2C_PCA9557D_SCL

K21
Samsung LGD
Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88)
N
Y
Parade T-con
- (0x10-0x1F or 0x30-0x3F)
Y
N
DVR
- (Write: 0x4E Read: 0x4F)
Y
Y

Internal DP

31 =I2C_PCA9557D_SDA

K78
Samsung LGD
*
Y
*
N
Y
Y

7 =PP3V3_S3_SMBUS_SMC_MGMT

Trackpad

AUO
*
*
N

=I2C_MIKEY_SCL
=I2C_MIKEY_SDA

(Write: 0x90 Read: 0x91)

=I2C_TPAD_SCL

6 49

=I2C_TPAD_SDA

6 49

MAKE_BASE=TRUE

71 41 SMBUS_SMC_3_SDA

SMC "2" SMBus S3 Connections

6 40

J2600 & J2650


(MASTER)

5%
1/20W
MF

2 201

71 41 SMBUS_SMC_3_SCL

(Write: 0x72 Read: 0x73)

XDP Connectors

2.0K

5%
1/20W
MF
201 2

U4900

U6800

R5291

2.0K

(MASTER)

J5700

R5290

SMC

Mikey

Connections

(* = Multiple options)

(Write: 0x30 Read: 0x31)

MAKE_BASE=TRUE

NOTE: SMC RMT bus remains powered and may be active in S3 state

TBT & Inlet Temp

6 40
7 =PP3V3_S3_SMBUS_SMC_A_S3

23 =SMBUS_XDP_SCL

EMC1704: U5400
(Write: 0x98 Read: 0x99)

23 =SMBUS_XDP_SDA

R52701

SMC

1K

5%
1/20W
MF
201 2

U4900
(MASTER)

R5271

Left I/O Board

1K

J4700
(See Table)

5%
1/20W
MF
2 201

71 41 SMBUS_SMC_2_S3_SCL

=I2C_LIO_SCL

6 40

=I2C_LIO_SDA

6 40

=I2C_TBT_INLET_THMSNS_SCL

46

=I2C_TBT_INLET_THMSNS_SDA

46

MAKE_BASE=TRUE

71 41 SMBUS_SMC_2_S3_SDA
MAKE_BASE=TRUE

Left I/O Board


ALS
- (write: 0x72 Read: 0x73)
Finstack Temp - (Write: 0x92 Read: 0x93)

PCH S0 "SMLink 0" Connections


44 7 =PP3V3_S0_SMBUS_PCH

Cougar-Point
U1800
(MASTER)

R52101
8.2K

5%
1/20W
MF
201 2

R5211

8.2K

5%
1/20W
MF
2 201

69 16 SML_PCH_0_CLK
MAKE_BASE=TRUE

69 16 SML_PCH_0_DATA
MAKE_BASE=TRUE

SMC S0 "1" SMBus Connections


7 =PP3V3_S0_SMBUS_SMC_B_S0

PCH S0 "SMLink 1" Connections

R52601

SMC

4.7K

5%
1/20W
MF
201 2

U4900
(MASTER)

Cougar-Point

R5261

CPU Temp

4.7K

5%
1/20W
MF
2 201

EMC1414-A: U5570
(Write: 0x98 Read: 0x99)

71 41 SMBUS_SMC_1_S0_SCL

=I2C_CPUTHMSNS_SCL

47

=I2C_CPUTHMSNS_SDA

47

MAKE_BASE=TRUE

71 41 SMBUS_SMC_1_S0_SDA

U1800

MAKE_BASE=TRUE

(Write: 0x88 Read: 0x89)

SYNC_MASTER=J11_MLB

SYNC_DATE=10/04/2011

PAGE TITLE
69 16 SML_PCH_1_CLK

SMBus Connections

69 16 SML_PCH_1_DATA

DRAWING NUMBER

Apple Inc.

051-9277

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

access PCH

2.8.0

SMLink 1 is slave port to

SIZE

REVISION
BRANCH
PAGE

52 OF 109

SHEET

44 OF 73

PBUS Voltage Sense Enable & Filter

Q5300

SOT-963
N-CHANNEL

PBUSVSENS_EN_L

=PBUSVSENS_EN

IN

1%
1/20W
MF
201 2

1%
1/20W
MF
201 2

PLACE_NEAR=U4900.A3:5MM

SMC_PBUS_VSENSE
PLACE_NEAR=U4900.A3:5MM

1%
1/20W
MF
201 2

NOSTUFF1
R5315

42 53

NTUD3169CZ

1%
1/20W
MF
201

R5316

5%
1/20W
MF
201 2

72

SIGNAL_MODEL=EMPTY

CPUIMVP_ISUMG_R_P

72

RTHEVENIN = 4573 Ohms


SMC_DCIN_VSENSE

R5311 1
100K

Scale: 12.1A / V
Max VOut: 2.73V at 39.934A

OUT

42

OPA2333

PLACE_NEAR=U4900.H1:5MM

R5351

DFN

V+

1%
1/20W
MF
201 2

5.49K

V-

1%
1/20W
MF
201

R5354

715K 2

0.1%
1/20W
MF
2 0201

20%
6.3V
X5R
0201

=PP3V3_S0_SAISNS

CPU SA Current Sense / Filter

41 42 45 46

C5370

PLACE_NEAR=R7140.2:5 MM

72 54

=PPCPUVCORE_S0_VSENSE

CPUVSENSE_IN

1%
1/20W
MF
201

PLACE_NEAR=R7510.2:5 MM

41 42 45 46

PLACE_NEAR=U4900.E2:5MM

1.82K2

VCCSAS0_CS_N

IN

72

1%
1/20W
MF
201

V-

SMC_CPU_SA_ISENSE

OUT

42

PLACE_NEAR=U4900.C2:5MM

C5371
0.22UF
20%

0201

SIGNAL_MODEL=EMPTY

1.00M2
1

1.00M

0.1%
1/20W
MF
2 0201

0.22UF

GND_SMC_AVSS 41

R5375

R5374

20%
6.3V
2 X5R
0201

GND_SMC_AVSS

4.53K2

ISENSE_SA_IOUT

6.3V
2 X5R

EDP: 6A

C5320

R5371

SC70-5

V+

VCCSAISNS_R_N

Sense R is R7140
Sense R is 1mOhm

42

PLACE_NEAR=U4900.C2:5MM

OPA333DCKG4

0.1%
1/20W
MF
0201

PLACE_NEAR=U4900.E2:5MM
1

U5370

VCCSAISNS_R_P

R5373
72 54

GND_SMC_AVSS

SMC_CPU_VSENSEOUT

72

PLACE_NEAR=R7140.4:5MM

R5320
4.53K2
1

C5350

20%
6.3V
2 X5R
0201

CPU Vcore Voltage Sense / Filter

10%
6.3V
201

CRITICAL

0.1%
1/20W
MF
0201

0.22UF

PLACE_NEAR=U4900.F2:5MM

XW5320
SM

1.82K2

VCCSAS0_CS_P

IN

42

PLACE_NEAR=U4900.F2:5MM
1

0.1UF

2 X5R

R5372

SMC_VCCSA_VSENSE OUT

1%
1/20W
MF
201

PLACE_NEAR=U5370.5:3MM

PLACE_NEAR=R7140.3:5MM

R5340

VCCSAVSENSE_IN 14.53K2

41 42 45 46

0.22UF

VCCSA Voltage Sense / Filter


XW5340
SM

0.22UF

Scale: 8.24A / V
Max VOut: 2.18V at 27.2A

=PPVCCSA_S0_VSENSE

42

C5351

Gain:161.765x

0.1%
1/20W
MF
0201

715K

GND_SMC_AVSS

R5355
1

OUT

PLACE_NEAR=U4900.M13:5MM
PLACE_NEAR=U4900.H1:5MM
20%
2 6.3V
X5R
0201

SIGNAL_MODEL=EMPTY

SMC_GFX_ISENSE

C5314

GND_SMC_AVSS

4.53K2

CPUIMVP_ISUMG_IOUT

PLACE_NEAR=U4900.F1:5MM

R5314 1

PDCINVSENS_EN_L_DIV

CPUIMVP_ISUMG_R_N

0.1%
1/20W
MF
0201

Sense R is R7550
Sense R is 0.75mOhm
EDP: 18A
TDP: 15.3A

PLACE_NEAR=U4900.F1:5MM

PLACE_NEAR=U4900.F1:5MM

41 42 45 46

CRITICAL

THRM

PLACE_NEAR=R7550.4:5MM

P-CHANNEL

0.22UF

U5340
8

4.42K2

CPUIMVP_ISNS1G_N

IN

R5313 1
1%
1/20W
MF
201 2

C5341

Gain:110.181x

R5353
72 58

1%
1/20W
MF
201 2

0.1%
1/20W
MF
0201

0.1%
1/20W
MF
0201

=PPDCIN_S5_VSENSE

487K 2

27.4K

62

IN

4.42K2

CPUIMVP_ISNS1G_P

IN

Max VOut: 3.3V at 19.77V Input

PM_SUS_EN

72 58

Enables DC-In VSense


divider when SUS present.

GFX/IG VCore Load Side Current Sense / Filter

DCIN_S5_VSENSE

42

41 42 45 46

100K
S

20%
2 6.3V
X5R
0201

R5312 1

OUT

PLACE_NEAR=U4900.M11:5MM
PLACE_NEAR=U4900.E1:5MM

GND_SMC_AVSS

R5345

487K

R5352

SMC_CPU_ISENSE

1%
1/20W
MF
201

20%
2 6.3V
X5R
0201

R5344

DCINVSENS_EN_L

DCINVSENS_EN

CPUIMVP_ISUM_IOUT

PLACE_NEAR=R7550.3:5MM

N-CHANNEL

4.53K2

TDP :28.05A

SOT-963

5%
1/20W
MF
201

THRM

0.1%
1/20W
MF
2 0201

DC-In Voltage Sense Enable & Filter

Q5310

Enables DC-In VSense


divider when AC present.

OUT

EDP: 33A

42

V-

CPUIMVP_ISUM_R_N

72

PLACE_NEAR=U4900.E1:5MM

R5341

DFN

V+

0.1%
1/20W
MF
0201

0.22UF

1%
1/20W
MF
201 2

GND_SMC_AVSS
IN

C5304

5.49K

PBUSVSENS_EN_L_DIV

4.42K2

CPUIMVP_ISNS1_N

OPA2333

8
3

PLACE_NEAR=U4900.A3:5MM

R53041

100K

IN

Sense R is R7510
Sense R is 0.75mOhm

RTHEVENIN = 4573 Ohms

P-CHANNEL

=CHGR_ACOK

CRITICAL

R5343

72 58

10%
2 6.3V
X5R
201

U5340

CPUIMVP_ISUM_R_P

PLACE_NEAR=R7510.4:5MM

R53031

R53011

72

0.1%
1/20W
MF
0201

27.4K

=PPBUS_S0_VSENSE

Max VOut: 3.3V at 19.77V Input

4.42K2

IN CPUIMVP_ISNS1_P

PBUS_S0_VSENSE

72 58 57

C5340
0.1UF

R5342

100K

PLACE_NEAR=U5340.8:3MM
1

PLACE_NEAR=R7510.3:5MM

R53021

Enables PBUS VSense


divider when in S0.

=PP3V3_S0_IMVPISNS

CPU VCore Load Side Current Sense / Filter

NTUD3169CZ

62

42 45 46

Gain:???

0.1%
1/20W
MF
0201

Scale: ???A / V
Max VOut: ???V at ???A

41 42 45 46

GFX/IG Vcore Voltage Sense / Filter


XW5330
SM
7

=PPGFXVCORE_S0_VSENSE

R5330
GFXVSENSE_IN

4.53K2

1%
1/20W
MF
201

PLACE_NEAR=R7550.2:5 MM

PLACE_NEAR=U4900.C1:5MM

SMC_GFX_VSENSEOUT

42

3.3V S0 FET Current Sense / Filter

PLACE_NEAR=U4900.C1:5MM
1

C5330
0.22UF

20%
2 6.3V
X5R
0201

=PP3V3_S0_3V3S0ISNS

GND_SMC_AVSS

R5382
72 61

=PP3V3_S0_CPUVCCIOISNS

IN

1.82K2

ISNS_3V3S0_P

VCCIOISNS_ENG

V+

72 59

72 59

IN
IN

CPUVCCIOS0_CS_N
CPUVCCIOS0_CS_P

10%
2 6.3V
X5R
201

U5360

PLACE_NEAR=R7640.3:5MM

5 IN4

INA210
SC70

C5360
0.1UF

OUT 6

CRITICAL
IN+ (200V/V) REF

R5361

PLACE_NEAR=R7640.4:5MM

EDP: 8.5A

SMC_CPUVCCIO_ISENSE

OUT

Gain: 200x

TDP :7.225A

IN

ISNS_3V3S0_N

C5361 VCCIOISNS_ENG
0.22UF

Sense R is R7831
Sense R is 1mOhm
EDP: 5A

GND_SMC_AVSS

41 42 45 46

72

V+

OPA333DCKG4
SC70-5
4

PLACE_NEAR=U4900.B1:5MM

R5381

SMC_3V3S0_ISENSE

ISENSE_3V3S0_IOUT 14.53K2

OUT

1%
1/20W
MF
201

V2

ISNS_3V3S0_R_N

42

PLACE_NEAR=U4900.B1:5MM

C5381

SYNC_MASTER=J11_MLB

SYNC_DATE=12/02/2011

PAGE TITLE

0.22UF

Voltage & Load Side Current Sensing

20%
6.3V
0201

2 X5R

DRAWING NUMBER

Apple Inc.

GND_SMC_AVSS

R5384

41 42 45 46

0.1%
1/20W
MF
2 0201

051-9277

R5385
1.00M2

Gain:???

Scale: ???A / V
Max VOut: ???V at ???A

SIGNAL_MODEL=EMPTY

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

2.8.0

1.00M

0.1%
1/20W
MF
0201

Scale: 2.5A / V
Max VOut: 3.3V at 8.25A

1.82K2

0.1%
1/20W
MF
0201

42

PLACE_NEAR=U4900.A6:5MM
20%
2 6.3V
X5R
0201

GND

Sense R is R7640, 2mOhm

72 61

4.53K2
1%
1/20W
MF
201

R5383

PLACE_NEAR=U4900.A6:5MM
1

10%
6.3V
201

2 X5R

U5380

ISNS_3V3S0_R_P

PLACE_NEAR=R7831.4:5MM

VCCIOISNS_ENG

CPUVCCIO_IOUT

CRITICAL

0.1%
1/20W
MF
0201

VCCIOISNS_ENG

C5380
0.1UF

PLACE_NEAR=R7831.3:5MM

CPU 1.05V VCCIO Current Sense / Filter


7

PLACE_NEAR=U5380.5:3MM
1

41 42 45 46

BRANCH
PAGE

53 OF 109

SHEET

45 OF 73

COMPUTING High Side Current Sense / Filter

46 7 =PP3V3_S0_HS_COMPUTING_ISNS

DC-IN (AMON) Current Sense Filter

DDR3 1V5R1V35 Current Sense / Filter

PLACE_NEAR=U4900.B3:5MM

V+

10%

72 8

IN

ISNS_HS_COMPUTING_N

5 IN-

IN

ISNS_HS_COMPUTING_P

4 IN+

OUT 6

SC70

ISNS_HS_COMPUTING_IOUT 1

(100V/V)

4.53K

SMC_HS_COMPUTING_ISENSE

1%
1/20W
MF
201

GAIN: 100X

REF 1

CHGR_AMON

EDP Current: 15.5 A


Max Vdiff:
31 mV

OUT

PLACE_NEAR=U4900.B3:5MM
1

GND_SMC_AVSS

ISL6259 Gain: 20x

41 42 45 46

72 56

Scale: 2.5A / V

IN
IN

INA210

5 IN-

ISNS_1V5_S3_N

4 IN+

ISNS_1V5_S3_P

SC70

(200V/V)

Max VOut: 1.4V at 8.25A

Place close to SMC


(For R and C)

0.1UF
10%
6.3V
X5R
201

U5460

41 42 45 46

72 56

C5460

V+

Sense R is R7350, 1mOhm

DC-In AMON

GND_SMC_AVSS

=PP3V3_S3_1V5S3ISNS

42

20%
6.3V
X5R
0201

C5455
20%
6.3V
X5R
0201

OUT

0.22UF

Sense R is R7020, 20mOhm

PLACE_NEAR=U4900.B5:5mm

C5431

42

PLACEMENT_NOTEs:

Sense R is R5400, 2mOhm

SMC_DCIN_ISENSE

1%
1/20W
MF
201

0.22UF

SCALE:
5A/ V
MAX VOUT: 3.1V at 16.5A

GND

IN

R5455

201

INA214

53

PLACE_NEAR=U4900.B5:5mm

2 6.3V
X5R

4.53K

0.1UF

U5450
72 8

R5431

C5450

OUT

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=3.3V

C5410
0.1UF

1
VDD

U5410

10%
6.3V
X5R
201

R5411 1

EMC1414-1-AIZL
72 47

SIGNAL_MODEL=EMPTY

C5411

72 47

10%
10V
X7R-CERM
0201

ALERT*

4 DP2/DN3

5 DN2/DP3

INLET_THMSNS_D1_N

BI

THERM*/ADDR

CRITICAL

10K

47

5%
1/20W
MF
201

=PP3V3_S3_WLANISNS

5%
1/20W
MF
201

AIRPORTISNS_ENG

7 TBT_INLET_THM_L

SMDATA

SMCLK

10

AIRPORTISNS_ENG
C5470

0.1UF

V+

Sense R is R4052, 20mOhm


72 37

=I2C_TBT_INLET_THMSNS_SDA

BI

44

=I2C_TBT_INLET_THMSNS_SCL

BI

44

72 37

IN
IN

ISNS_AIRPORT_N

ISNS_AIRPORT_P

INA210

ININ+

SC70

(200V/V)

OUT
REF

ISNS_P5VWLAN_IOUT

10%
10V
X7R-CERM
0201

20%
6.3V
X5R
0201

72 ISNS_HS_OTHER_N

5 IN-

72 ISNS_HS_OTHER_P

4 IN+

HDDISNS_ENG

C5430

INA213

OUT 6

SC70

10%
6.3V
X5R
201

1W

1%

0.005

HS_OTHER_IOUT

CRITICAL

SCALE:
5A/ V
MAX VOUT: 3.1V at 16.5A

EDP Current: 15.5 A


Max Vdiff:
31 mV

SMC_OTHER_HI_ISENSE

1%
1/20W
MF
201

GAIN: 50X

REF 1

1
3

(50V/V)

GND
=PPVIN_S5_HS_OTHER_ISNS_R

IN

ISNS_SSD_P

INA211

ININ+

SC70

(500V/V)

OUT

42

OUT
REF

EDP Current: 2.36A


Max Vdiff:
7.0 mV

0.22UF
2

20%
6.3V
X5R
0201

IN

ISNS_LCDBKLT_N

IN

ISNS_LCDBKLT_P

ININ+

INA211
SC70

(500V/V)
2

42

0.1UF

PLACE_NEAR=U4900.G2:5mm

10%
6.3V

LCDBKLTISNS_ENG
R5495

2 X5R
201

OUT
REF

ISNS_LCDBKLT_IOUT

4.53K
1%
1/20W
MF
201

GAIN: 500X
SCALE:
0.2A / V
MAX VOUT: 3.3V AT 0.66A

SMC_LCDBKLT_ISENSE

2
1

OUT

10%
10V
X7R-CERM
0201

0.22UF

20%
6.3V
X5R
0201

PLACE_NEAR=U4900.G2:5mm

GND_SMC_AVSS

41 42 45 46

41 42 45 46

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=10/17/2011

PAGE TITLE

Charger BMON (Production) Solution

High Side Current Sensing

ISL6259 Gain: 36x

DRAWING NUMBER

Scale: 2.78A / V

Apple Inc.

Max VOut: 3.3V at 9.167A

051-9277

EDP Current: 310A

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

2.8.0

42

LCDBKLTISNS_ENG
C5495

Place close to SMC


(For R and C)

3300PF

GND_SMC_AVSS

41 42 45 46

LCDBKLTISNS_ENG
C5490

PLACEMENT_NOTEs:

EDP Current: 0.67 A


Max Vdiff:
6.7 mV

PLACE_NEAR=U4900.A4:5MM

1 C5422
2

PLACE_NEAR=U4900.B4:5mm

U5490

GND
OUT

20%
6.3V
X5R
0201

=PP3V3_S0_BKLTISNS

3
72 8

72 8

1%
1/20W
MF
201

0.22UF

LCD Backlight Driver Input Current Sense / Filter

R5422
From charger

42

Place close to SMC


(For R and C)

PLACE_NEAR=U4900.A4:5MM

IN

OUT

HDDISNS_ENG
C5485

41 42 45 46

CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter

53

PLACEMENT_NOTEs:

Sense R is R0910, 10mOhm

SMC_BMON_ISENSE

SMC_HDD_ISENSE

SCALE:
0.667A / V
MAX VOUT: 3.3V AT 2.2A

V+

4.53K
1%
1/20W
MF
201

GAIN: 500X

LCDBKLTISNS_ENG

300K

GND_SMC_AVSS

C5433

Place close to SMC


(For R and C)

HDDISNS_ENG
R5485

ISNS_P5VHDD_IOUT

PLACE_NEAR=U4900.A5:5mm

GND_SMC_AVSS

CHGR_BMON

PLACE_NEAR=U4900.B4:5mm

10%
6.3V
2 X5R
201

GND

PLACEMENT_NOTEs:

Sense R is R5430, 5mOhm

IN

ISNS_SSD_N

C5480
0.1UF

V+

R5433

MF

CRITICAL

72 38

PLACE_NEAR=U4900.A5:5mm

4.53K

41 42 45 46

=PP3V3_S0_HDDISNS

2
4

0612

72 38

0.1UF

U5430

=PPVIN_S5_HS_OTHER_ISNS

R5430

PLACE_NEAR=U4900.B2:5mm

Place close to SMC


(For R and C)

OTHER High Side Current Sense / Filter

=PP3V3_S0_HS_OTHER_ISNS

0.22UF

HDD Current Sense / Filter

Write Address: 0x98


Read Address: 0x99

V+

IN

AIRPORTISNS_ENG
C5475

GND_SMC_AVSS

U5480

SMC_WLAN_ISENSE

1%
1/20W
MF
201

PLACEMENT_NOTEs:

Sense R is R4599, 3mOhm

4.53K

Scale:
0.25A / V
MAX VOUT: 3V AT 0.825A

GND

HDDISNS_ENG

OUT

Gain: 200x

EDP Current: 0.750 A


Max Vdiff:
15 mV

=TBTTHMSNS_D2_N

BI

AIRPORTISNS_ENG
R5475

201

2200PF

47

PLACE_NEAR=U4900.B2:5mm

10%
6.3V

2 X5R

U5470

8 TBT_INLET_ALERT_L

SIGNAL_MODEL=EMPTY

C5412

41 42 45 46

10K

GND
6

PLACE_NEAR=U5410.4:5mm
PLACE_NEAR=U5410.5:5mm

42

20%
6.3V
X5R
0201

=TBTTHMSNS_D2_P

BI

OUT

0.22UF

R5412

3 DN1

2200PF

PLACE_NEAR=U5410.2:5mm
PLACE_NEAR=U5410.3:5mm

MSOP

2 DP1

INLET_THMSNS_D1_P

BI

C5465

AirPort Current Sense / Filter

PP3V3_S0_HS_COMPUTING_ISNS_R

5%
1/20W
MF
201

42

Place close to SMC


(For R and C)

47

OUT

PLACE_NEAR=U4900.B6:5mm

GND_SMC_AVSS

R5410
=PP3V3_S0_HS_COMPUTING_ISNS

SMC_1V5S3_ISENSE

1%
1/20W
MF
201

PLACEMENT_NOTEs:

TBT/Inlet Temp Sensor


46 7

4.53K

SCALE:
5A / V
MAX VOUT: 2.4V AT 16.5A

EDP Current: 12 A
Max Vdiff:
24 mV

R5465
1

GAIN: 200X

REF 1

GND

EDP Current: 3.5A

PLACE_NEAR=U4900.B6:5mm

ISNS_1V5S3_IOUT

BRANCH
PAGE

54 OF 109

SHEET

46 OF 73

CPU Proximity Sensor


TBT Die

R5510
7

=PP3V3_S0_CPUTHMSNS

47

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

5%
1/20W
MF
201

0.1UF

1
VDD

U5510

NO STUFF

C5510
10%
6.3V
X5R
201

R5511 1

EMC1413
72 9

SIGNAL_MODEL=EMPTY

C5511

Detect CPU Die Temperature

72 9

PLACE_NEAR=U5510.2:5mm
PLACE_NEAR=U5510.3:5mm

CRITICAL

5 DN2/DP3
GND
6

R5550

R5512

10K

10K

5%
1/20W
MF
201 2

5%
1/20W
MF
201
2

34

ALERT*

8 CPUTHMSNS_ALERT_L

SMDATA

SMCLK

10

BI

TP_TBT_THERM_DP

TBT_THERMD_P

MAKE_BASE=TRUE

=TBTTHMSNS_D2_P

46 47

5%
1/20W
MF
201

NO STUFF

R5551

PLACE_NEAR=U3600.B1:2mm

=I2C_CPUTHMSNS_SDA
=I2C_CPUTHMSNS_SCL

THRM_PAD

BI

44

BI

44

Use GND pin B1 on U3600 for N leg

72

TBT_THERMD_N

XW5520

=TBTTHMSNS_D2_N

46 47

5%
1/20W
MF
201

SM

11

To connect Die Sensor, Stuff R5550 & R5551, No stuff R5540 & R5541
To connect Proximity Sensor, Stuff R5540 & R5541, No Stuff R5550,R5551

Placement note:

CPUTHMSNS_D2_P

Place U5510 under CPU

SIGNAL_MODEL=EMPTY

72

Detect TBT Die Temperature

7 CPUTHMSNS_THM_L

THERM*/ADDR

4 DP2/DN3

CPU_THERMD_N

BI

72

Q5510

3 DN1

2200PF
10%
10V
X7R-CERM
0201

DFN

2 DP1

CPU_THERMD_P

BI

C5512

10%
10V
X7R-CERM
0201

2200PF

1
PLACE_NEAR=U5510.4:5mm
PLACE_NEAR=U5510.5:5mm

BC846BLP
DFN1006H4-3

2
72

Write Address: 0x98


Read Address: 0x99

CPUTHMSNS_D2_N

PART NUMBER

Detect DDR/5V/3.3V Proximity Temperature

Placement note:
Place Q5510 next to DDR/5V/3.3V supply on TOP side

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

C5361

VCCIOISNS_PROD

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

C5475

AIRPORTISNS_PROD

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

C5485

HDDISNS_PROD

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

C5495

LCDBKLTISNS_PROD

C
Replacing caps with 100K PD on ISENSE SMC inputs

TBT,MLB Bottom & Inlet Proximity Sensors


INLET_THMSNS_D1_P

46 72

Q5530

Placement note:
1

Place Q5530 between near rear vent on bottom side

BC846BLP
DFN1006H4-3

INLET_THMSNS_D1_N

46 72

B
R5540
72

TBTTHMSNS_D2_R_P

=TBTTHMSNS_D2_P

5%
1/20W
MF
201

Q5520

Placement note:

BC846BLP
DFN1006H4-3

Place Q5520 close to TBT on TOP side

R5541

2
72

TBTTHMSNS_D2_R_N

46 47

=TBTTHMSNS_D2_N

46 47

5%
1/20W
MF
201

=MLBBOT_THMSNS_D3_N

47

Q5540

Placement note:

Place Q5540 on MLB bottom side opposite U5400

BC846BLP
DFN1006H4-3

=MLBBOT_THMSNS_D3_P

47

=TBTTHMSNS_D2_P

72

47 46

TBT_MLBBOT_THMSNS_P

=TBTTHMSNS_D2_N

72

47 46

TBT_MLBBOT_THMSNS_N

=MLBBOT_THMSNS_D3_P

47

=MLBBOT_THMSNS_D3_N

47

MAKE_BASE=TRUE

SYNC_MASTER=J11_MLB

MAKE_BASE=TRUE

SYNC_DATE=08/03/2011

PAGE TITLE

Thermal Sensors
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

55 OF 109

SHEET

47 OF 73

FAN CONNECTOR

7 6

=PP5V_S0_FAN
=PP3V3_S0_FAN

R5660 1
47K
5%

R5665
41

1 47K2

SMC_FAN_0_TACH

1/20W
MF
201

CRITICAL

J5600

FF14A-4C-R11DL-B-3H

NC
2

F-RT-SM
5
1

FAN_RT_TACH

5%
1/20W
MF
201

3
4

NC

5V DC
TACH
MOTOR CONTROL
GND

R5661 1
Q5660
3

SMC_FAN_0_CTL

SOD-VESM-HF
2

41

518S0793

SSM3K15FV

1/20W
MF
201

100K
5%

FAN_RT_PWM

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

PAGE TITLE

Fan
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

56 OF 109

SHEET

48 OF 73

IPD Flex Connector


49 7

=PP3V3_S4_TPAD

CRITICAL

J5700

R5730
C5701

R5703
10K

5%
1/20W
MF
201 2
68
68

49 7

=PP3V3_S4_TPAD

0.1UF
10%
16V
X5R-CERM
0201

5% 1/20W
201

6
VOLTAGE=3.3V

MF

BI

68 24

BI

MIN_LINE_WIDTH=0.5 mm

0.1UF
10%
6.3V
X5R
201

USB_TPAD_M_P 5 M+
USB_TPAD_M_N 4 M-

68

=PP5V_S5_TPAD

SEL 10

5%
1/20W
MF
201 2

GND

SEL=0 Choose pull up/down


SEL=1 Choose USB

BI

49 44 6

BI

49 42 41 40 6

0.1UF
10%
16V
X5R-CERM
0201

49 42 6

C5732

=I2C_TPAD_SDA
=I2C_TPAD_SCL
MIN_LINE_WIDTH=0.5 mm

IN

SMC_ONOFF_L
SMC_LID

OUT

SMC_TPAD_RST_L

5%
25V
NP0-CERM
0201

11

C5733

PLACE_NEAR=J5700.8:1.5MM

13

IN

PM_SLP_S4_L

PLACE_NEAR=J5700.9:1.5mm

5% 1/20W
201

7 6

=PP3V42_G3H_TPAD

C5734

SMC_TPAD_RST_L

NOSTUFF
1

C5704

C5735

6 42 49

100PF
5%
25V
NP0-CERM
0201

C5736

100PF
5%
25V
NP0-CERM
0201

PLACE_NEAR=J5700.14:1.5MM

C5720 1

0.1UF
10%
16V
X5R-CERM
0201

6 40 41 42 49

100PF

PLACE_NEAR=J5700.11:1.5MM

518S0794

MF

6 41 42 49

SMC_LID

5%
25V
NP0-CERM
0201

PLACE_NEAR=J5700.10:1.5MM

USB_TPAD_MUX_SEL

6 44 49

PLACE_NEAR=J5700.12:1.5MM

=I2C_TPAD_SCL

100PF
5%
25V
NP0-CERM
0201

14

R5704
62 41 37 26 17

6 44 49

SMC_ONOFF_L

12

16

100PF

9
10

MIN_NECK_WIDTH=0.20mm
49 42 41 6
OUT

PLACE_NEAR=J5700.10:1.5MM

PP5V_TPAD_FILT

6
VOLTAGE=5V

0402-LF

C5710

49 44 6

=I2C_TPAD_SDA

USB_TPAD_P
USB_TPAD_N

FERR-120-OHM-1.5A

CRITICAL

8 OE*

10K

L5720

TQFN

2
3

68

R57021

SMC_PME_S4_WAKE_L

OUT

Y+ 1
Y- 2

U5700

7 D+
6 D-

USB_TPAD_R_P
USB_TPAD_R_N

42 41 6

PLACE_NEAR=J5700.1:1.5MM

PI3USB102ZLE
68 24

MIN_NECK_WIDTH=0.20mm

C5700 1

VCC

F-RT-SM
15

PP3V3_TPAD_CONN

FF14A-14C-R11DL-B-3H

0.1UF
10%
6.3V
X5R
201

PLACE_NEAR=J5700.13:1.5MM

Keyboard Backlight Driver & Detection


CRITICAL
7

=PP5V_S0_KBDLED

L5750

KBDLED_SW

CRITICAL

J5715

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE

FF14A-4C-R11DL-B-3H

1098AS-SM

VIN

MIC2292

1UF

U5750

10%

10V
X5R
402-1

BI

3 EN

SMC_SYS_KBDLED
6

NC

GND
1

R5755
5%
1/16W
MF-LF
402

J5815 pin 1 is grounded


on keyboard backlight flex

3
4
6

KBDLED_ANODE
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

NC

THRM

PAD

518S0793

C5755

4.7

OUT 1

5 NC

If LOW, keyboard backlight present


If HIGH, keyboard backlight not present

F-RT-SM
5
1

SW 7

CRITICAL

6 FB

KBDLED_FB

R5853 always stuffed, R5854 only


grounded when KB BL flex connected.

MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MM

MLF

41

To detect Keyboard backlight, SMC will


tristate and read SMC_SYS_KBDLED:

NC

C5750

Keyboard Backlight Connector

10UH-0.58A-0.35OHM
BYPASS=U5750.1:2:2 MM

0.22UF
10%
50V
X5R-CERM
0603-1

C5756
0.22UF
10%
50V
X5R-CERM
0603-1

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

PAGE TITLE

IPD / KBD Backlight


DRAWING NUMBER

Apple Inc.

051-9277
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0
BRANCH
PAGE

57 OF 109
SHEET

49 OF 73

SIZE

C
DUAL I/O MODE (MODE 0 & 3) SUPPORTED
High Speed CLK Frequency - 50MHz for fast read dual I/O
=PP3V3_SUS_ROM

R6101
3.3K

5%
1/20W
MF
2 201

69 43 42

IN

C6100

VDD

0.1UF

SPI_MLB_CLK

CRITICAL

U6100

10%
16V
X5R-CERM 2
0201

64MBIT
WSON

SCK

SI/SIO0

SPI_MLB_MOSI

IN

42 43 69

SPI_MLB_MISO

OUT

42 43 69

SST25VF064C
IN

43 19 6

IN

SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB

1
3
7

OMIT_TABLE
CE*
SO/SOI1
WP*
RST*/HOLD*
VSS THRM_PAD
4

NOTE: If HOLD* is asserted


ROM will ignore SPI cycles.

69 43 42

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

PAGE TITLE

SPI ROM
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

61 OF 109

SHEET

50 OF 73

SPEAKER AMPLIFIERS
APN:353S2888

80 HZ < FC < 132 HZ

GAIN

6DB

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V

R6214

=PP5V_S3_AUDIO_AMP

PP5V_S3_U6210

5%
1/20W
MF
201

C6207

NOSTUFF

0.1UF
10%
6.3V
X5R
201

CRITICAL

A1

SPEAKER LOWPASS

IN

SPKRAMP_INR_P
CRITICAL

C6211
0.1UF

72 40 6

40 6

IN

IN

SPKRAMP_INR_N

R6211
100K

72

MAX98300_R_P
MAX98300_R_N

A3
B3

IN+
IN-

OUT+
OUT-

B1

GAIN

C3

C6201
47UF

20%
2 6.3V
POLY-TANT
2012-LLP

SPKRAMP_ROUT_P

6 52 72

SPKRAMP_ROUT_N

6 52 72

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 mm

C1
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.30 mm

R_SPKRAMP_SHDN

C2

SHDN*

B2

NC

R_AMP_GAIN

R6210
1

72

10%
16V
X5R-CERM
0201

AUD_GPIO_3

10%
16V
X5R-CERM
0201

WLP

PGND

2
A2

72 40 6

5%
1/20W
MF
201

U6210
MAX98300

0.1UF

100K

PVDD
CRITICAL

C6210

CRITICAL

R6213 1

5%
1/20W
MF
201

R6212
100K

5%
1/20W
MF
2 201

5%
1/20W
MF
201

SYNC_MASTER=J11_MLB

SYNC_DATE=09/30/2011

PAGE TITLE

AUDI0: SPEAKER AMP


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

62 OF 109

SHEET

51 OF 73

MLB to LIO Power Cable Connector


CRITICAL

Right Speaker Connector

Debug LEDs

J6900
WTB-PWR-M82
M-RT-SM

7 6

(For development only)

=PP18V5_DCIN_CONN

CRITICAL

1
2

=PP5V_S3_LIO_CONN

J6903

=PP3V3_S3_DBGLEDS

78171-0002
3

S3_S0_LED

R69401

518S0508

C6906
0.1UF

C6907

1
1

1UF

10%
16V
2 X5R-CERM
0201

C6908
1UF C6905
10%

2 35V
X5R

10%
35V
X5R
603

603

S3_S0_LED
1

1K

NO STUFF
CRITICAL

NO STUFF
CRITICAL

M-RT-SM

6 7

0.1UF
10%
50V
X7R
603-1

1K

5%
1/20W
MF
201 2

R6941

5%
1/16W
MF-LF
402

72 51 6

IN

72 51 6

IN

SPKRAMP_ROUT_P
SPKRAMP_ROUT_N

1
2

DBGLED_S3
2

DBGLED_S0
S3_S0_LED

D6910

518S0519

S3_S0_LED

D6911

GREEN-3.6MCD
2.0X1.25MM-SM

GREEN-3.6MCD
2.0X1.25MM-SM

MPM5:NO

R6912

DBGLED_S0_D

40.2K

S3_S0_LED

1%
1/20W
MF
2 201

CRITICAL

Q6910

Q6940
3

SSM3K15FV

SOD-VESM-HF

SI5419DU
POWERPAK

5A

0.1UF
10%
25V
X5R
402

5%
1/20W
MF
201
62 41 25 23

MPM5:NO

IN

ALL_SYS_PWRGD

R6911

DCIN_ISOL_GATE_R 1

5%
1/20W
MF
201

DCIN_ISOL_GATE
7

100K

MPM5:YES
C6912 1

R6910

=PP18V5_DCIN_ISOL

CRITICAL
K

D6912

PART NUMBER

GDZT2R6.8

5.1V Zener
A

GDZ-0201

QTY

DESCRIPTION

PPBUS_G3H

R6905
1

10

5%
1/8W
MF-LF
805

5%
1/8W
MF-LF
805

R6912

MPM5:YES

117S0008

RES,MF,1/20W,100KOHM,1,0201,SMD

R6911

MPM5:YES

3.425V "G3Hot" Supply

D6905

2 PPBUS_G3H_R

BAT30CWFILM

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

PPDCIN_G3H_OR_PBUS_R

BOM OPTION

RES,MF,1/20W,90.9KOHM,1,0201,SMD

Supply needs to guarantee 3.31V delivered to SMC VRef generator

SOT-323
1
3

PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

P3V42G3H_BOOST
DIDT=TRUE
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V

7 6

4.7

CRITICAL

CRITICAL

R6906

REFERENCE DES

118S0560

1
1

VIN

C6994

BOOST

10%
10V
CERM
402

LT3470A

0.22UF

U6990

CRITICAL

L6995

33UH-20%-0.39A-0.435OHM

=PP3V42_G3H_REG

DFN

K16-Specific

NC

CRITICAL
1

CRITICAL

C6991

Battery Connector
PPVBAT_G3H_CONN

10%
25V
X5R
402

6 53

2
2

BIAS

FB
THRM
PAD

CRITICAL

GND

P3V42G3H_SW

10%
25V
X5R
402

60MA MAX OUTPUT


C6995
22PF

C6992

5.6UF

20%
25V
POLY-TANT
CASE-B2-SM

Vout = 3.425V

DP418C-SM

1 CRITICAL

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

C6990
1UF

1UF

NC

SW

SHDN*

5%
50V
NP0-C0G-CERM
0201

<Ra>
R6995 1

(Switcher limit)

348K
1%
1/20W
MF
201

CRITICAL
2

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

<Rb>
R6996 1
200K

CRITICAL

C6951

1UF

J6950

10%
16V
X5R
402

WTB-PWR-M82
M-RT-SM

C6999

20%
10V
X5R-CERM
0402-1

10UF

P3V42G3H_FB

1%
1/20W
MF
201

C6950
0.1UF
10%
25V
X5R
402

CRITICAL
1

C6998
10UF
20%
10V

2 X5R-CERM
0402-1

Vout = 1.25V * (1 + Ra / Rb)

1
2
3
4
5

=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SYS_DETECT_L

IN
BI

6 44
6 44

SYNC_MASTER=J13_MLB_NON_POR

518S0540

R6950 1
10K
5%
1/20W
MF
201

DC-In & Battery Connectors


DRAWING NUMBER

RCLAMP2402B

Apple Inc.

SC-75

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SYNC_DATE=11/10/2011

PAGE TITLE

CRITICAL
NO STUFF

D6950
2

BRANCH
PAGE

69 OF 109

SHEET

52 OF 73

Q7080

FROM ADAPTER

POWERPAK

POWERPAK

R7085

2
2

1%
1/20W
MF
201

=PPDCIN_S5_CHGR_ISOL

D7005

1%
1/20W
MF
201

53

PPCHGR_DCIN_D_R

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

30mA max load


4.7

C7020

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

C7001

100K

C7022

5%
1/20W
MF
201

Float CELL for 1S

CHGR_RST_L
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_CELL

2
44

IN

44

BI

62

IN

12
13
11
10
4
6

CHGR_ACIN

MIN_NECK_WIDTH=0.2 mm

R7015

71

255K

71

1%
1/20W
MF
2 201

17

CSOP
CSON

16

C7050
0.47UF

CHGR_VCOMP_R
2
1

C7099

10UF

10UF

20%
10V
X5R
603

20%
10V
X5R
603

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5.5V

Vout = 5.50V
200MA MAX OUTPUT
(Switcher limit)

MF
201

<Rb>
R7096

200K
MF
201

2
71

10

3 1 CRITICAL

CHGR_CSI_R_P

R7020

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

71

0.020

CHGR_CSI_R_N
4 2

10%
25V
X5R
402

0.5%
MF-LF
0612
1W

PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=18.5V

CRITICAL

C7030

C7021

20%
25V
POLY-TANT
CASE-D3L

0.1UF
2

CRITICAL
1

C7031

33UF-0.06OHM

10%
25V
X5R
402

PLACE_NEAR=Q7030.5:1.5mm
1

C7035

20%
25V
POLY-TANT
CASE-D3L

C7036

1UF

33UF-0.06OHM

C7037

1UF

10%
25V
X5R
603-1

BGATE
AMON
36V/V BMON
(OD) ACOK
20V/V

53

26
1
28 71
27 71

CHGR_DCIN

0.001UF

10%
25V
X5R
603-1

10%
50V
X7R-CERM
0402

23

CHGR_BOOT
CHGR_UGATE
CHGR_PHASE

21

CHGR_LGATE

25
24

Max Current = 8A

CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N

PLACE_NEAR=U7000.25:2mm

CHGR_BGATE
CHGR_AMON
CHGR_BMON
=CHGR_ACOK

15
14

Q7030

MIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

CRITICAL

RJK03P0DPA

GATE_NODE=TRUE

7
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

CRITICAL

L7030

F7040

4.7UH-17A

WPAK

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

TO SYSTEM

f = 400 kHz

CRITICAL

10%
10V
CERM
402

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm

C7025
0.22UF

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

VOLTAGE=8.4V

8AMP-24V

=PPBUS_G3H

PIMC104T4R7MN-SM
1206

GATE_NODE=TRUE

6
OUT

46

OUT

46

OUT

42 45

PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.4V

3 4 5

CRITICAL

CRITICAL

C7040 1
20%
11V
POLY
CASE-B

CRITICAL

C7041 1

62UF

20%
11V
POLY
CASE-B

PLACE_NEAR=L7030.2:1.5mm

C7043 1

62UF

20%
11V
POLY
CASE-B

C7045
1000PF

62UF

10%
16V
X7R-CERM
0201

1%
1/20W
MF
201 2

C7002
1UF

220

10%
10V
X5R
402

CRITICAL

XW7000
SM

R7050

Q7055

0.01

SI7615DN

(GND)

0.5%

PWRPK-1212-8

1W

TO/FROM BATTERY

MF

PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm

0612-3

CHGR_VNEG_R
(CHGR_CSO_P)

10%
16V
X5R-X7R-CERM
0201

(CHGR_CSO_N)

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

R7051

2.2

R7052

1
201

71

5%

(PPVBAT_G3H_CHGR_R)

PPVBAT_G3H_CHGR_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.4V

CHGR_CSO_R_P
1/20W

71

5%

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

MF

CHGR_CSO_R_N
1/20W

MF

PPVBAT_G3H_CONN

6 52

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=8.4V

C7016
470PF

CRITICAL
1

R70161

1%
1/20W

5%
50V
NP0-C0G-CERM
0201

470PF
10%
16V
X5R-X7R-CERM
0201

681K

22PF

C7015

10%
10V
X5R
0402

C7095

1%
1/20W
MF
2 201

18

C7098

R7095

23.7K

R7011

<Ra>
1

7
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

PP5V5_CHGR_VDDP
CRITICAL
1

MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.2 mm

201

MIN_LINE_WIDTH=0.2 mm

(AGND)

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

100

CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N

29

2
2520

VDDP

VHST
DCIN
SMB_RST_N
SGATE
SCL
U7000 AGATE
TQFN
SDA
CSIP
VFRQ
CSIN
CELL
BOOT
ACIN
UGATE
ICOMP
PHASE
VCOMP
LGATE
VNEG

ISL6259HRTZ

SMC_RESET_L

IN

VDD
2

CRITICAL
OMIT_TABLE

0.1UF

PGND

43 42 41 6

FB
THRM
PAD

P5V1_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE

P5V1_FB

22

5%
1/20W
MF
201

R7000

20

19

R7002

1%
1/20W
MF
201

10%
10V
X5R
402

NO STUFF

1%
1/20W
MF
2 201

5%
1/20W
MF
201

1UF

66.5K

10

R7022

PP5V1_CHGR_VDDP

R7013

10%
16V
X7R-CERM
0402

53

5%
1/16W
MF-LF
402

THRM_PAD

=PP3V42_G3H_CHGR

R7010

Vout = 1.25V * (1 + Ra / Rb)

5%
1/20W
MF
201

R7001

PP5V1_CHGR_VDD

PP5V1_CHGR_VDDP 53

R7021

(CHGR_DCIN)
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

DIVIDER SETS ACIN THRESHOLD AT 12.18V

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5.1V

2
402

1/20W

0.047UF

NC

SW
BIAS

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

5%
1/10W
MF-LF
603

ACIN pin threshold is 3.2V, +/- 50mV

Input impedance of ~40K meets


sparkitecture requirements

CRITICAL

(CHGR_AGATE)

R7005
20

5%
1/16W

1%

PP5V5_DCIN:NO

SHDN*

(CHGR_SGATE)

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

SOT-323

MF-LF

10UH-30%-0.85A-460MOHM

402

332K

L7095

R7086

5%
1/20W
MF
201

BAT30CWFILM

CERM

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

CRITICAL

CHGR_AGATE_DIV
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

CHGR_DCIN 53

DFN
8

GND

62K

CRITICAL

10%
10V

LT3470A

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

R7081

2
402

R7091

0.22UF

U7090

470K

C7094

BOOST

10%
25V
X5R
402

VIN

10%
25V
X5R-CERM
0603

0.1UF

5%
1/16W

PP5V5_VDDP

5A

C7085

4.7UF
2

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

C7084

MF-LF

DIDT=TRUE

402

10%
25V
X5R-CERM
0603

5A

CHGR_SGATE_DIV

NO STUFF

P5V1_BOOST

4.7UF

5%
1/20W
MF
201

5%
1/16W

R7090
1

CHGR_DCIN_D

PPDCIN_G3H_INRUSH

VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

100K

C7090

PPDCIN_G3H_OR_PBUS

MF-LF

Q7085
SI5419DU

R7080 1

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm

CRITICAL

SI5419DU

=PPDCIN_S5_CHGR

PPCHGR_DCIN_D_R

53

CRITICAL

Inrush Limiter

PP5V5_DCIN:YES

For Erp Lot6 spec

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm

Reverse-Current Protection

NO STUFF
R7092

5.5v "G3Hot" Supply

Need to stuff R7092 if either PP5v5_DCIN:Yes or PP5v5_VDDP are used

This node is powered


through body diodes:
* DCIN through Q7080.
* PBUS through Q7085,
Charger TOP FETs and
Q7055.

(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

C7042

C7011

0.1UF

0.01UF

10%
6.3V
X5R
201

10%
10V
X5R
201

C7000

C7005

1UF

0.22UF

10%
10V
X5R
402-1

10%
50V
X5R-CERM
0603-1

C7026

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE


DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

1000PF
10%
16V
X7R-CERM
0201

C7017

10UF

GND_CHGR_AGND

10%
25V
X5R
805

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

C7014

1UF
2

10%
25V
X5R
603-1

C7013

0.1UF
2

10%
25V
X5R
402

C7012
0.01UF

10%
25V
X7R
402

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=11/10/2011

PAGE TITLE

PBus Supply & Battery Charger


DRAWING NUMBER

Apple Inc.

051-9277

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

SIZE

REVISION

BRANCH
PAGE

70 OF 109

SHEET

53 OF 73

7
7

=PPVIN_S0_VCCSAS0
=PP5V_S0_VCCSA
PLACE_NEAR=Q7100.2:1.5mm

VCCSAS0_BOOT_RC
CRITICAL

R7101 1

C7101

20%
10V
X5R-CERM
0402-1

R7130

19

20

VCC

PVCC

ISL95870AH

IN

CPU_VCCSASENSE
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

IN

CPU_VCCSASENSE_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

1%
1/20W
MF
201

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

R7147
20K

1%
1/20W
MF
2 201

R7153
1.62K2

62

OUT

12 VO

VCCSAS0_OCSET

11 OCSET

PVCCSA_PGOOD

VCCSAS0_RTN
VCCSAS0_FSEL

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

R7148

10%
16V
X5R-X7R-CERM 2
0402

XW7101
SM

VCCSAS0_SET1_R

C7102
2.2UF

R7150
56K

20%
10V
X5R-CERM
0402

1%
1/20W
MF
2 201

1%
1/20W
MF
2 201

R7152
C7106 R7154
3.24K
3.24K
10PF

5%
2 50V
COG-CERM
0201-1

C7105
10PF

5%
50V
2 COG-CERM
0201-1

511K

C7121

10%
16V
X7R-CERM
0402

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

8 SET0
9 SET1

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

CPU_VCCSA_VID<0>

62UF
20%
11V
POLY
CASE-B

R7140

CRITICAL

0.001

L7100

PPVCCSA_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

FDV0630H-SM

1%
1W
MF-1
0612

=PPVCCSA_S0_REG

6A Max Output
1

f = 300 kHz

C7141
270UF

20%
2V
TANT
CASE-B2-SM

(ENDIAN SWAP)

PGND

R7141

72 45

VCCSAS0_CS_P

72 45

VCCSAS0_CS_N

1K
1%
1/20W
MF
201

IN

C7123

1.0UH-7.7A
8

VCCSAS0_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

GND

12

CRITICAL 1

CRITICAL

POWERPAK-6X3.7

5 VID1

CPU_VCCSA_VID<1>

CRITICAL

SIZ710DT

IN

5%
25V
NP0-C0G
402

1000PF

Q7100

VCCSAS0_DRVH

VCCSAS0_DRVL

VCCSAS0_SET0

12

C7122

FSEL

VCCSAS0_SET1

5%
1/20W
MF
201

0.1UF

10%
10V
CERM
402

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

R7149

10%
16V
X5R-CERM
0805

1%
1/20W
MF
201

C7120
10UF

RTN

R7103 1

PGOOD

6 VID0

1%
1/20W
MF
2 201

13

UGATE 17

LGATE 1

49.9K

PLACE_NEAR=C1763.2:3mm

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

C7103

0.022UF

14

BOOT 18

PHASE 16

SREF

VCCSAS0_VO

VCCSAS0_RTN_R 1

1%
1/20W
MF
201

CRITICAL

10 FB
7

VCCSAS0_SREF
1

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

15 EN

12

1.62K2
1

=PVCCSA_EN

C7130
0.22UF

R7151

62

UTQFN

10%
16V
X5R-CERM
0805

CRITICAL

VCCSAS0_VBST

U7100

0
5%
1/16W
MF-LF
402

PP5V_S0_VCCSAS0_VCC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

C7119
10UF

10UF

2.2
5%
1/16W
MF-LF
402

CRITICAL

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

C7140
1000PF
2

5%
25V
NP0-C0G
402

1%
1/20W
MF

(VCCSAS0_OCSET)

2 201

R7142
1K

MIN_LINE_WIDTH=0.2 mm

(VCCSAS0_VO)

1%
1/20W
MF
201

OCP = R7141 x 8.5uA / R7140


OCP = 8.5A

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

XW7100
SM

VCCSAS0_AGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=0V

PLACE_NEAR=U7100.3:1mm

INTEL TABLE:
VID1

VID0

Voltage

0.9V

0.8V

0.725V

0.675V

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=10/17/2011

PAGE TITLE

System Agent Supply


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

71 OF 109

SHEET

54 OF 73

=PPVIN_S5_P5VP3V3

PLACE_NEAR=Q7220.2:1.5mm

1000PF
2

C7200

55 P5VP3V3_VREG3

10%
16V
X5R
402

SIZ710DT

Vout = 5.0V

X5R
402

POWERPAK-6X3.7

L7220

1.5UH-20%-18A-15MOHM

C7254

62UF
20%
6.3V
ELEC
CASE-B2S

C7252

C7250 1

150UF
20%
6.3V
POLY-TANT
CASE-B2-SM

C7253

10V
X5R
603

150UF

20%
6.3V
POLY-TANT
CASE-B2-SM

SM

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

SM

DIDT=TRUE

55

P5VP3V3_VREG3

5%

10%
16V
X7R-CERM
0402

PLACE_NEAR=L7220.1:3mm

2
SM

1.33K

1/20W

P5VS3_CSN1

11

P5VS3_FUNC

201

P5VS3_VFB1

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

10
4

P5VS3_EN_R

1%
1/20W
MF
201

41.2K
1%
1/20W
MF
201

20K
1%
1/20W

201

MF
2

55

10%
16V
X7R-CERM
0201-1

VIN

402

10V
X5R

603

12

=P5V3V3_REG_EN

IN

62

VBST2

26

DRVH2

24

P3V3S5_DRVH
GATE_NODE=TRUE

SW2

25

P3V3S5_LL
SWITCH_NODE=TRUE

CSP2
CSN2

MODE
VFB1
COMP1

RF
VFB2
COMP2

EN1
PGOOD1

EN2
PGOOD2

P3V3S5_VBST

XW7200

27

C7264

18

402

CRITICAL
=PP3V3_S5_REG

POWERPAK-6X3.7

Vout = 3.3V

CRITICAL

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

L7260

DIDT=TRUE

P3V3S5_RF

XW7260

XW7261

10UF

20%

PLACE_NEAR=L7260.1:3mm
1

2
1

OUT

P5VS3_PGOOD

62

OUT

P3V3S5_PGOOD

C7272
1000PF

10%
16V
X7R-CERM
0201

PLACE_NEAR=L7260.2:3mm

20

R7246
1

353S2678

7.5K

R7239
1%

MF

1/20W

201

MF

1/20W
MF

1.54K

C7238

C7239
220PF

10%
10V
X7R
201

10%
25V
X7R-CERM
201

SM

R7216

PLACE_NEAR=L7260.2:3mm

6.65K

P3V3S5_VFB2_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

1%
1/20W
MF
2 201

201

4700PF

XW7262

P3V3S5_COMP2_R

201

1%
1/20W
MF
201

20K

1/20W

1/20W

PLACE_NEAR=U7201.28:1mm

NO STUFF

1%

5%

201

249K
1%

R7238

R7206

55

62

20%
6.3V
TANT
CASE-B2-SM

PLACE_NEAR=L7260.2:1.5mm

R7260
23.2K

P3V3S5_CSP2_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
2

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

1%
1/20W
MF
201

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

P5VP3V3_VREF2

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

10V
X5R
603

C7292

10%
16V
X7R-CERM
0402

P3V3S5_COMP2
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

P3V3S5_EN_R

1 C7290

SM

P3V3S5_VFB2

15

CRITICAL

SM

C7288

F=400KHZ

150UF-0.018OHM-1.8A

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

2
PCMC063T-SM

6.5A MAX OUTPUT

2.5UH-14A
1

0.1UF

P5VP3V3_VREF2

10K
1%
1/20W
MF
201

10%
16V
X7R-CERM
0201

Q7260

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

R7221

1000PF

SIZ710DT

X5R

P3V3S5_CSN2

16

21

10%
25V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

P3V3S5_CSP2

17

0.1UF

5%
1/16W
MF-LF
402

8
DIDT=TRUE

P3V3S5_DRVL
GATE_NODE=TRUE

SM
1

R7264

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

THRM_PAD

R7249

C7283

P3V3S5_VBST_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

20%

X5R-CERM

402

DRVL2

CSP1
CSN1

10%
16V
X5R
402

1 C7205
10UF

10V

MF

270PF

4700PF
10%
10V
X7R
201

201

20%

DRVL1

C7237

C7236 1

DRVH1

GND
1

2.2UF

10%
10V
CERM

EN

QFN

SW1

R7237

MF

C7203 1

0.22UF

U7201

VBST1

NO STUFF

1/20W

P5VS3_COMP1_R

P5VS3_CSP1_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

1%

4.22K

R7220

R7236
7.5K

R7256

V5SW
7

P5VS3_COMP1

1%
1/20W
MF
201

P5VS3_VFB1-R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

P5VS3_CSP1

R7247

XW7222

PLACE_NEAR=L7220.1.2:1.5mm

30

R7248
1

1
32

P5VS3_DRVL
GATE_NODE=TRUE

MF

10%
16V
X7R-CERM
0201

DIDT=TRUE

P5VS3_LL
SWITCH_NODE=TRUE

NO STUFF

0.1UF
1

P5VS3_DRVH
GATE_NODE=TRUE

C7218

C7271
1000PF

DIDT=TRUE

XW7221

20%

CRITICAL

XW7220

10UF

152S1424

31

DIDT=TRUE

C7201

CRITICAL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

SKIPSEL1
SKIPSEL2
OCSEL

28

CRITICAL

14

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

PLACE_NEAR=L7220.2:3mm

19

P5VS3_VBST

2
PCMC063T-SM

CRITICAL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

PLACE_NEAR=L7220.1:3mm

2 201

P5VP3V3_SKIPSEL

CRITICAL

7.2A MAX OUTPUT

5%
1/16W
MF-LF
402

10%
25V

5%
1/20W
MF

0.1UF

Q7220

55 7 =PP5V_S3_REG

2 201

R7245 1

C7224

R7201

5%
1/20W
MF

TPS51980

CRITICAL

23

SKIP_5V3V3:INAUDIBLE

R7200

20%
11V
POLY
CASE-B

C7281
1UF

62UF

P5VP3V3_VREF2

55

SKIP_5V3V3:AUDIBLE
1

F=400KHZ

20%
11V
POLY
CASE-B

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

1UF

C7282

62UF

10%
16V
X5R
402

PLACE_NEAR=Q7260.2:1.5mm

CRITICAL 1

C7284

1UF

10%
16V
X7R-CERM
0201

P5VS3_VBST_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

CRITICAL 1

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

55 7 =PP5V_S3_REG

13

20%
11V
POLY
CASE-B

C7241

VREF2

62UF
2

22

62UF

C7270

VREG3

C7240

33

C7242
20%
11V
POLY
CASE-B

7 =PP5V_S5_LDO

CRITICAL 1

29

CRITICAL 1

VREG5

R7261
10K

1%
1/20W
MF
201

GND_P5VP3V3_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

PLACE_NEAR=U7201.4:2mm

PLACE_NEAR=U7201.21:2mm

R7251

R7252

5%
1/20W
MF
2 201

62

IN

=P5VS3_EN

5%
1/20W
MF
2 201

62

IN

=P3V3S5_EN

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=10/17/2011

PAGE TITLE

5V / 3.3V Power Supply


DRAWING NUMBER

Apple Inc.

051-9277
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0
BRANCH
PAGE

72 OF 109
SHEET

55 OF 73

SIZE

=PPVIN_S3_DDRREG

1 CRITICAL

1 CRITICAL

C7330

62UF

20%
11V
POLY
CASE-B

20%
11V
POLY
CASE-B

2
7

=PPVIN_S0_DDRREG_LDO

=PP5V_S3_DDRREG

C7331

62UF
2

C7332

0.001UF

10%
25V
X5R
603-1

10%
50V
X7R-CERM
0402

1 CRITICAL

C7333

1UF

C7334
62UF
20%
11V
POLY
CASE-B

C7301
10UF
20%
10V
X5R
603

C7300

PLACE_NEAR=U7300.2:1mm

10UF

20%
10V
X5R
603

CRITICAL

Q7330

(DDRREG_DRVH)

PLACE_NEAR=U7300.12:1mm

IRFHM831PBF

MIN_NECK_WIDTH=0.2 mm

DDRREG_VBST

12

26 8

=DDRVTT_EN

IN

62

VTT Enable

=DDRREG_EN

IN

VDDQ/VTTREF Enable

17
16

DDRREG_1V8_VREF

V5IN
U7300

S3
S5

TPS51916

VREF

CRITICAL

MIN_LINE_WIDTH=0.2 mm

10%
16V
X7R-CERM
0402

31

R7315

0.1UF

DDRREG_FB

MIN_NECK_WIDTH=0.1 mm

DDRREG_MODE

1%

19

1/20W
DDRREG_TRIP

MF
PLACE_NEAR=U7300.6:1mm

REFIN

MIN_LINE_WIDTH=0.2 mm

20K
2

18

MODE
TRIP

201

DDRREG_DRVH

13

DDRREG_LL

DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
VTTREF

MF

0.01UF

1%
1/20W

MF

DDRREG_P1V35_L

201

PLACE_NEAR=U7300.8:5mm

10%
16V
CERM
402

11

DDRREG_DRVL

20

DDRREG_PGOOD

GATE_NODE=TRUE

Q7319

DIDT=TRUE

D 3

201

PLACE_NEAR=U7300.19:3mm

2
MPCG1040LR88-SM

OUT

72 46
(DDRREG_DRVL)

SM

1
1

DDRREG_VTTSNS

PLACE_NEAR=C7361.1:3mm

MIN_NECK_WIDTH=0.1 mm

5 31 7 =PPVTT_S3_DDR_BUF

CRITICAL

MIN_LINE_WIDTH=0.2 mm

VTT THRM
GND PAD

CRITICAL

C7360
20%
6.3V
X5R
603

C7361
10UF

10UF

21

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.8 MM

1
3

MF

0.5W

1206

1%

2
4

=PPDDR_S3_REG

2
2

20%
6.3V
X5R
603

Q7335

46
72

OUT

ISNS_1V5_S3_P
ISNS_1V5_S3_N

1 CRITICAL

C7340
330UF

PQFN3.3X3.3

MIN_NECK_WIDTH=0.2 mm

CRITICAL

C7341

1 C7362

20%
2.0V
POLY-TANT
CASE-B2-SM1

1 2 3

0.001UF
10%
50V
X7R-CERM
0402

1
1

330UF

10UF
20%
6.3V
X5R
603

C7346

20%
2.0V
POLY-TANT
CASE-B2-SM1

IRFHM830DPBF

MIN_LINE_WIDTH=0.5 mm

OUT

CRITICAL

CRITICAL

PLACE_NEAR=C3101.1:3mm

PLACE_NEAR=C3101.1:1mm

C7345
20%
10UF

2
2

6.3V
X5R
603

XW7301
SM

Vout = 1.5V
1

PLACE_NEAR=U7300.9:3mm

PLACE_NEAR=C7340.1:1mm
C7360, C7361 close
2

PLACE_NEAR=U7300.18:3mm

XW7300

SSM3K15AMFVAPE

C7350
0.22UF
10%
10V
CERM
402

SM

VESM

XW7360

=PPVTT_S0_DDR_LDO

PPDDR_S3_REG_R

MIN_NECK_WIDTH=0.1 MM

5
7

0.001

0.88UH-20%-19A-2.3MOHM

MIN_NECK_WIDTH=0.2 mm

DDRREG_VDDQSNS

R7350

L7330

1 2 3

10%
25V
X5R
402

1%
1/20W
MF
2 201

MF

CRITICAL

MIN_LINE_WIDTH=0.5 mm

84.5K

1/20W

CRITICAL

(DDRREG_LL)

R7318

R7317
1%

DIDT=TRUE

DIDT=TRUE

200K

PLACE_NEAR=U7300.8:1mm

1V5R1V35_SW
CRITICAL

C7316

10

100K

1/20W
201

PGND GND

R7316

LVDDR3_HW:NO
1

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

1%

DDRREG_VBST_RC

MIN_LINE_WIDTH=0.5 mm

GATE_NODE=TRUE

10mA max load

150K

1/16W

DIDT=TRUE

14

PLACE_NEAR=U7300.8:5mm

R7314

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.2 mm

PLACE_NEAR=U7300.8:5mm

1V5R1V35_SW

5%

MIN_NECK_WIDTH=0.17 mm

15

0.1UF

MF-LF

QFN

MIN_NECK_WIDTH=0.1 mm

C7315

VBST
DRVH
SW

C7325

R7325

402

PQFN3.3X3.3

MIN_LINE_WIDTH=0.5 mm

VLDOIN

14.1A max output


(Q7335 limit)

to memory

f = 400 kHz

(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm

PLACE_NEAR=U7300.21:1mm

S 2

GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=0V

17

IN

MEM_VDD_SEL_1V5_L

PART NUMBER
118S0460

QTY
1

DESCRIPTION

REFERENCE DES

RES,MF,60.4KOHM,1,1/20W,0201

R7316

CRITICAL

BOM OPTION
LVDDR3_HW:YES

If LVDDR3_HW:NO is turned ON, switch R2821 & R7971 back to the original value for 1.5V DDR unless 1V5R1V35_SW is turned ON

SYNC_MASTER=J11_MLB

SYNC_DATE=12/02/2011

PAGE TITLE

1.5V DDR3 Supply


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

73 OF 109

SHEET

56 OF 73

3
=PP5V_S0_CPUIMVP

R7401
P5V_S0_CPUIMVP_VDD
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

10

5%
1/16W
MF-LF
402

=PPVCCIO_S0_CPUIMVP
C7401

=PPVIN_S0_CPUIMVP

2.2UF

R7479 1

1%
1/20W
MF
201

2.2UF

20%
10V
X5R-CERM
402

20%
10V
X5R-CERM
402

PLACE_NEAR=U7400.24:2mm
PLACE_NEAR=U7400.15:2mm

15

PLACE_NEAR=U7400.16:2mm

24

VDDB

PLACE_NEAR=U7400.18:2mm

R7406

R7402

MAX15120

NC 31

66 12

IN

OUT

CPUIMVP_VR_ON

CPU_VIDSOUT
CPU_VIDSCLK
CPU_VIDALERT_L

16
18
17

5.76K

1%
1/20W
MF
2 201

NO STUFF

R7466

5.76K

R7464
200K

1%
1/20W
MF
2 201

1%
1/20W
MF
201

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

R7462

215K

1%
1/20W
MF
2 201

CRITICAL

R7467
100KOHM-1%-100MW
0603

PLACE_NEAR=Q7510.1:2mm

THERMA
THERMB

CPUIMVP_SLEW

32

SR

CPUIMVP_IMAXA
CPUIMVP_IMAXB

29
30

IMAXA
IMAXB

10K

1%
1/20W
MF
2 201

BSTB
DHB
LXB
DLB

11
13
12
14

R7463

137K

1%
1/20W
MF
2 201

CPUIMVP_ISUM
CPUIMVP_ISUM_N
CPUIMVP_FBA

C7444

R7461

137K

5%
25V
NP0-C0G-CERM
0201

OUT

58

OUT

58

OUT

58

1%
1/16W
MF-LF
402

5%

R7403
2

2.2 CPUIMVP_UGATE1

OUT

NO STUFF

C7408
OUT

58 72

C7404
2200PF

10%
10V
2 X7R-CERM
0201

57

CPUIMVP_ISUM_R

10%
10V
X5R-CERM
0402

C7409

R7410

470PF
2

5%
50V
NP0-C0G-CERM
0402

OUT

58

OUT

58

OUT

58

OUT

58

OUT

5%
1/20W
MF
201

58 72

57

OUT

58 72

OUT

58 72

C7407

0.0022UF

10%
50V
2 CERM
402
NO STUFF

XW7400

1%
1/20W
MF
2 201

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

CPUIMVP_ISUMG_P
CPUIMVP_ISUMG_N
CPUIMVP_FBB

45 58 72

IN

0.039UF

CPUIMVP_BOOT1G
CPUIMVP_UGATE1G
CPUIMVP_PHASE1G
CPUIMVP_LGATE1G

CPUIMVP_ISNS1_P

58

1/16WMF-LF402

NC
NC
NC
NC

CSPB1 8
CSNB 9
FBB 6
NO STUFF

R7465

38
28
26
27
25

1%
1/20W
MF
2 201

1
1

CSPA2
BSTA2
DHA2
LXA2
DLA2

215K

47PF

CRITICAL

0603

33
34

R7460

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

R7469

CPUIMVP_NTC
CPUIMVP_NTCG

100KOHM-1%-100MW

CSPAAVE 35
CSNA 37
FBA 4

VDIO
CLK
ALERT*

R7468

EN

CPUIMVP_BOOT1
CPUIMVP_UGATE1_R
CPUIMVP_PHASE1
CPUIMVP_LGATE1
CPUIMVP_ISUM_P

22
21
23
36

THRM
PAD

IN

62

CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD

CPUIMVP_TON

20

5%
1/20W
MF
201

90.9K2
1

41

IN

66 12

OUT

GNDSB

66 12

25

19
10

GNDSA

IN

CPU_PROCHOT_L

TQFN
TON
DRVPWMA
CRITICAL
BSTA1
CSPA3
DHA1
VR_HOT*
LXA1
DLA1
POKA
CSPA1
POKB

62

OUT

39
5

300

U7400

66 42 41 10

C7403

130

VCC 40

1%
1/20W
MF
201

2.2UF

VDDA

54.9

20%
10V
X5R-CERM
402

R7480

C7402

7 58

SM

C7418

NO STUFF

C7419

NO STUFF

NO STUFF

C7414

C7415

100PF

100PF

100PF

100PF

5%
25V
NP0-CERM
0201

5%
25V
NP0-CERM
0201

5%
25V
NP0-CERM
0201

5%
25V
NP0-CERM
0201

PLACE_NEAR=Q7550.1:2mm

GND_CPUIMVP_SGND

C7452

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

100PF

NO STUFF

C7440

1000PF

10%
16V
X7R-CERM
0201

R7440

CPU_AXG_SENSE_R

C7441
10%
16V
X7R-CERM
0201

CPU_AXG_SENSE_N

IN

12 66

5%
1/20W
MF
201

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

1000PF
2

10

R7412
57

CPUIMVP_FBA

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

1
1

NO STUFF

C7442
0.01UF

10%
10V
X5R-CERM
0201

NO STUFF

C7443

10

CPU_VCCSENSE_N

IN

C7412
1000PF

10%
16V
X7R-CERM
0201

R7413

CPUIMVP_FBA_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

12 66

C7422

5%
1/20W
MF
201

10

CPU_VCCSENSE_P

12 66

IN

5%
1/20W
MF
201

1000PF

R7422

0.01UF
2

6.34K
1%
1/20W
MF
201

R7441

CPU_VCCSENSE_R

5%
25V
NP0-CERM
0201

10%
10V
X5R-CERM
0201

57

CPUIMVP_FBB

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

8.25K

1%
1/20W
MF
201

10%
16V
X7R-CERM
0201

R7423

CPUIMVP_FBB_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

10

CPU_AXG_SENSE_P

IN

12 66

5%
1/20W
MF
201

C7462
100PF
1

5%
25V
NP0-CERM
0201
NO STUFF

SYNC_MASTER=J11_MLB

SYNC_DATE=10/14/2011

PAGE TITLE

CPU IMVP7 & AXG VCore Regulator


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

74 OF 109

SHEET

57 OF 73

CPU=IV Bridge ULV, AXG=GT2


D

D
57 7

=PPVIN_S0_CPUIMVP
CRITICAL

THESE TWO CAPS ARE FOR EMC

CRITICAL
CRITICAL

C7513
62UF

CPUIMVP_BOOT1_RC

C7514

10UF

62UF

20%
11V
POLY
CASE-B

20%
11V
POLY
CASE-B

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

1 C7516

C7515

10UF

20%
25V
X5R-CERM
0603

C7517
1UF

20%
25V
X5R-CERM
0603

C7518
0.001UF

10%
16V
X5R
402

0.001UF

10%
50V
X7R-CERM
0402

C7519

C7540

C7541

62UF

10%
50V
X7R-CERM
0402

62UF

20%
11V
POLY
CASE-B

20%
11V
POLY
CASE-B

C7510
62UF

C7520
62UF

20%
11V
POLY
CASE-B

20%
11V
POLY
CASE-B

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

PHASE 1

376S0984

DIDT=TRUE

CRITICAL

Q7510

R7511

0
5%
1/16W
MF-LF
402

57

IN

C7511
0.22UF

2
2

IN

10%
10V
CERM
402

2
5

CPUIMVP_BOOT1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

57

IRF6811STRPBF
SQ

DIDT=TRUE

CRITICAL

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

CPUIMVP_PHASE1

PPVCORE_S0_CPU_PH1

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

PIMB104T-SM

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

57

1%
1W
MF
0612

0.36UH-20%-30A-1.2MOHM

MIN_LINE_WIDTH=0.5 MM

IN

0.00075

L7510

CPUIMVP_UGATE1

57

R7510

CRITICAL

4
72 45

152S1323

SWITCH_NODE=TRUE

=PPVCORE_S0_CPU_REG

VOLTAGE=1.25V

CPUIMVP_ISNS1_N
CPUIMVP_ISNS1_P

OUT

45 57 72

CPUIMVP_LGATE1

IN

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

R7513

GATE_NODE=TRUE

46.4
1

376S0985

2 6

R7514
10

1%
1/20W
MF
201

CRITICAL

D
5

1%
1/20W
MF
201

CPUIMVP_ISUM_N

Q7520

IRF6894MTRPBF

G
3

57 72

C7571

DIRECTFET-MX

IN

NO STUFF

2200PF
10%
10V
X7R-CERM
0201

CPUIMVP_ISUM_P

IN

57 72

=PPVIN_S0_CPUAXG
CRITICAL

THESE TWO CAPS ARE FOR EMC

CRITICAL
CRITICAL

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

376S1005

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

3 TG
C7551
10%
10V
CERM
402

1/16W
MF-LF

IN

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

57

IN

CPUIMVP_BOOT1G

SON5X6

CPUIMVP_UGATE1G

4.7

57

IN

CPUIMVP_PHASE1G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

57

IN

DIDT=TRUE

20%
25V
X5R-CERM
0603

10%
16V
X5R
402

0.001UF
2

10%
50V
X7R-CERM
0402

C7559

CRITICAL

10%
50V
X7R-CERM
0402

C7560
62UF

0.001UF

C7561
62UF

20%
11V
POLY
CASE-B

20%
11V
POLY
CASE-B

R7550

0.00075

4 TGR

CPUIMVP_VSWG
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

SWITCH_NODE=TRUE
DIDT=TRUE

2
PIMB104T-SM

NOSTUFF
1

1%
1W
MF
0612

152S1323

R7552

CPUIMVP_ISNS1G_P

=PPVCORE_S0_AXG_REG

46.4
1%
1/20W
MF
201

C7552

R7554
10

1%
1/20W
MF
201
SYNC_MASTER=J13_MLB_NON_POR

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

CPU IMVP7 & AXG VCore Output

VOLTAGE=1.25V

CPUIMVP_ISUMG_N

10%
50V
CERM
402

IN

DRAWING NUMBER

57 72

Apple Inc.
NO STUFF

NOTICE OF PROPRIETARY PROPERTY:

10%
16V
X7R-CERM
0201

CPUIMVP_ISUMG_P

051-9277

IN

57 72

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

2.8.0

C7574
1000PF

SYNC_DATE=10/17/2011

PAGE TITLE

DIDT=TRUE

0.001UF

DIDT=TRUE

CPUIMVP_ISNS1G_N

72 45

R7553 1

5%
1/10W
MF-LF
603

NOSTUFF

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

72 45

CPUIMVP_AXG_SNUB
1

PPVCORE_S0_AXG_R
VOLTAGE=1.05V

2.2

5 BG

CPUIMVP_LGATE1G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

C7558

L7550

5%
1/16W
MF-LF
402

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

20%
25V
X5R-CERM
0603

1UF

0.36UH-20%-30A-1.2MOHM

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

VIN 1

PGND
2

20%
11V
POLY
CASE-B

10UF

C7557

CRITICAL

VSW 6
7
8

R7555

DIDT=TRUE

10UF

CRITICAL

402

0.22UF

5%

1 C7556

Q7550

10

62UF
2

CRITICAL

CRITICAL

1 C7555

CSD58872Q5D

DIDT=TRUE

R7551

20%
11V
POLY
CASE-B

C7554

CRITICAL

CPUIMVP_BOOT1G_RC

57

62UF

CPUIMVP_UGATE1G_R
MIN_NECK_WIDTH=0.2 MM

AXG PHASE

C7553

BRANCH
PAGE

75 OF 109

SHEET

58 OF 73

CPU VCCIO (1.05V S0) Regulator

7
7

=PPVIN_S0_CPUVCCIOS0
=PP5V_S0_CPUVCCIOS0
CPUVCCIOS0_BOOT_RC
CRITICAL

R7601

14

603

3.01K
1%
1/20W
MF
201

62

=CPUVCCIOS0_EN

IN

<Ra>

CPUVCCIOS0_FB

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_SREF

62

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

R7605 1

2.74K
1%
1/20W
MF
201

R7645

1%
1/20W
MF
201

C7602

1
1

10%
16V
X5R
603

<Rb>
1

47PF
5%
25V
NP0-C0G-CERM
0201

FB
SREF

C7605

VO

CPUVCCIOS0_OCSET

OCSET

LGATE

RTN

CPUVCCIOS0_FSEL

FSEL

R7603

15

C7619
62UF
20%
11V
POLY
CASE-B

Q7630

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm 5%
1/16W
GATE_NODE=TRUE
MF-LF
DIDT=TRUE

CPUVCCIOS0_LL

CRITICAL

CSD58872Q5D

2 CPUVCCIOS0_R

402

3 TG

SON5X6

VSW 6
7
8

4 TGR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

R7640

VIN 1

0.001

L7630

0.68UH-22A-2.7MOHM
PPCPUVCCIO_S0_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

2 PPCPUVCCIO_S0_REG_R
PIMB104T-SM

CRITICAL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

2
4

1%
1W
MF
0612

=PPCPUVCCIO_S0_REG
1
3
CRITICAL

C7649
PGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

C7623

5%
25V
NP0-C0G
402

2
2

20%
2V
TANT
CASE-B2-SM

1000PF

C7648

R7641

XW7600

72 45

CPUVCCIOS0_CS_P

72 45

CPUVCCIOS0_CS_N

20%
2V
TANT
CASE-B2-SM

3.01K

SM

f = 300 kHz
2

270UF

C7603

CPUVCCIOS0_AGND

21A Max Output

CRITICAL

PGND

5%
1/20W
MF
201

10%
16V
X7R-CERM
0402

270UF

PLACE_NEAR=L7630.2:1.5mm

CPUVCCIOS0_DRVL

Vout = 1.05V

5 BG

PGOOD

CPUVCCIOS0_RTN

10

CPUVCCIOS0_DRVH 1

0.047UF

47PF
5%
25V
NP0-C0G-CERM
0201

UGATE

11

PHASE

CPUVCCIOS0_VO

12

1 CRITICAL

CRITICAL

R7631
BOOT

5%
25V
NP0-C0G
402

1000PF

2.2UF

C7604

CRITICAL

GND

2.74K

UTQFN

EN

CPUVCCIOS0_PGOOD

OUT

C7622

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

ISL95870

20%
11V
POLY
CASE-B

PLACE_NEAR=Q7630.1:1.5mm

CPUVCCIOS0_VBST

U7600

62UF

20%
11V
POLY
CASE-B

R7644
1%
1/20W
MF
201

10%
16V
X5R
402

C7621

62UF

16

C7630
1UF

MF-LF

3.01K

R7604

R7630

PVCC

CRITICAL 1

C7620

5%
1/10W

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

CPU_VCCIOSENSE_N

CRITICAL 1
1

PP5V_S0_CPUVCCIOS0_VCC

CPU_VCCIOSENSE_P

VCC
66 12

20%
10V
X5R
603

13

66 12

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

10UF

2.2
5%
1/20W
MF
201

C7601

1%
1/20W
MF
201

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=0V

C7640
1000PF
2

PLACE_NEAR=U7600.1:1mm

5%
25V
NP0-C0G
402

(CPUVCCIOS0_OCSET)

OCP = R7641 x 8.5uA / R7640


OCP = 25.6A
Vout = 0.5V * (1 + Ra / Rb)

R7642
3.01K

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

(CPUVCCIOS0_VO)

1%
1/20W
MF
201

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm

SYNC_MASTER=J13_MLB_NON_POR

SYNC_DATE=10/17/2011

PAGE TITLE

CPU VCCIO (1.05V) Power Supply


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

76 OF 109

SHEET

59 OF 73

1.05V SUS LDO

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
CRITICAL
XDP_PCH

U7740
TPS720105
SON

=PP3V3_SUS_P1V05SUSLDO

1.8V S0 Regulator

=PP3V3_S0_P1V8S0

10%
16V
X7R-CERM
0201

20%
6.3V
X5R-CERM-1
603

22UF
2

C7740
10%
6.3V
CERM
402

152S1302

L7720

62

IN

=P1V8S0_EN

OUT

P1V8S0_PGOOD

IN

OUT

EN

NC

PIMB042T-SM

QFN

EN

LX
LX

CRITICAL

PG

SYNCH

5
2

Max Current = 0.020A

NC

XDP_PCH
1

C7741
2.2UF

7
2

10%
6.3V
X5R
402

SWITCH_NODE=TRUE
DIDT=TRUE

15

6
13

=PP1V8_S0_REG 7
2

Vout = 1.794V

CRITICAL

CRITICAL
1

P1V8S0_FB

8
16

NC

P1V8S0_SW

14

C7723

R7720 1

NC
NC
NC

113K
1%
1/20W
MF
201

Max Current = 1.8A

C7721
22UF

47PF
5%
25V
NP0-C0G-CERM
0201

Freq = 1 MHz

20%
6.3V
X5R-CERM-1
603

17

PGND
12

SGND
11

10

THRM_PAD

VFB

GND

THRM
PAD

Vout = 1.05V

1.0UH-20%-4.5A-24MOHM

U7720
ISL8014A
62

1UF

VDD

1000PF

C7720

VIN

C7724

XDP_PCH

CRITICAL

=PP1V05_SUS_LDO

BIAS

<Ra>
CRITICAL

R7721 1

C7722

90.9K

22UF

1%
1/20W
MF
201 2

20%
6.3V
X5R-CERM-1
603

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

1.05V S0 LDO

1.5V S0 LDO

CRITICAL

CRITICAL

U7780

U7770

TPS720105
SON

TPS72015
SON
7

=PP1V5_S0_REG

4 BIAS

=PP3V3_S0_P1V5S0

IN

=PP1V8_S0_P1V5S0

6 IN

OUT 1

62

IN

=P1V5S0_EN

3 EN

NC 2

C7770

1UF
10%
6.3V
CERM
402

C7771

1UF

10%
6.3V
CERM
402

GND
5

THRM
PAD
7

Vout = 1.5V
Max Current = 0.02A

NC
1

=PP1V8_S0_P1V05S0LDO

IN

OUT

=1V05_S0_LDO_EN

EN

NC

C7782

2.2UF
2

=PP3V3_S0_P1V05S0LDO

62

C7772
10%
6.3V
X5R
402

=PP1V05_S0_LDO

C7780

1UF

1UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

BIAS

GND
5

THRM
PAD

Vout = 1.05V
Max Current = 0.35A

NC
1

C7781
2.2UF

7
2

10%
6.3V
X5R
402

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

PAGE TITLE

PLACE_NEAR=U7780.4:1mm
PLACE_NEAR=U7770.4:1mm

Misc Power Supplies

PLACE_NEAR=U7780.6:1mm
PLACE_NEAR=U7770.6:1mm

DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

77 OF 109

SHEET

60 OF 73

1
CRITICAL

R7831
0.001

NOSTUFF

R7803

3.3V S0 FET

0
2

CRITICAL

Q7830

5%
MF-LF
402

VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM

=PP3V3_S0_P3V3S0FET

SSM3K15AMFVAPE

R7832

1
2

=PP3V3_S4_FET

Q7812

5%

VESM

1/16W

D 3

0.033UF

220K

SOT563

402

3.3V S4 FET

10%
5%

X5R

MF-LF
402
402

C7800

R7800

1
62

P3V3S4_EN_L

P3V3S3_S4

MOSFET

SiA427

CHANNEL

P-TYPE 8V/5V

62 38

0.01UF

47K

S 2

=P3V3S4_EN

IN

10%
16V
X5R
402

IN

5 G

=P3V3S0_EN

P3V3S0_EN_L

S 4

RDS(ON)

26 mOhm @1.8V

LOADING

0.7? A (EDP)

C7830
1

R7821
PP3V3_SUS_FET_R

CRITICAL

R7811

62

IN

=P3V3S3_EN

P3V3S3_SS

MOSFET

SiA427

0.01UF

CHANNEL

P-TYPE 8V/5V

5%
1/20W
MF
201

RDS(ON)

10%
10V
X5R
201

CRITICAL

Q7822

D 3

5 G
62 61

IN

=P5V_3V3_SUS_EN

0.033UF

220K

10%
16V
X5R 2
402

5%
1/20W
MF
2 201

P5VSUS_EN_L

S 4

=PP5V_SUS_FET

C7841 1

R7842

1.608 A (EDP)

SOT563

R7840
3.3K
1

0.01UF
1

10%
16V
CERM
402

IN

P1V5CPU_EN

PP5V_S0_FET_R

DMP2018LFK

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V

2
3

TDFN

ON

CRITICAL

D 5
G

10%
6.3V
X5R-CERM 2
603

PG

SHDN*

GND

THRM
PAD

4.7UF

P1V5S0FET_GATE

R7862
220K

5%
1/20W
MF
2201

Q7801
4

5%
P1V5S0FET_GATE_R
1/16W
MF-LF
402

FDMC2514SDC

POWER33

S
1 2

P5V0S0_EN_L

CRITICAL

C7861
10%
16V
X5R

R7860
1

R7850

PP1V5_S3RS0_FET_R
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM

10K

0.033UF

C7860

402

0.01UF

P5V0S0_SS

=PP5V_S0_FET

5%
1/16W
MF-LF
402

5.0V S0 FET

2
1

CRITICAL

R7801
0

=PP5V_S3_P5VS0FET

APN 376S0928

VCC

U7801

NO STUFF

C7802

100? mA (EDP)

R7841

Q7860

1
2

SLG5AP020
26

LOADING

CRITICAL

P-TYPE 12V/8V
29 mOhm @4.5V

0.1UF

SiA427

CHANNEL
RDS(ON)

CRITICAL

5.0V S0 FET

=PP1V5_S3_P1V5S3RS0_FET

DFN2563-6
20%
10V
CERM
402

MOSFET

C7840

5%
1/20W
MF
201

=PP5V_S5_P1V5DDRFET
C7801

5V SUS FET

P5VSUS_SS

1.5V S3/S0 FET


7

100? mA (EDP)

Q7840

=PP5V_S5_P5VSUSFET

SSM6N37FEAPE

26 mOhm @1.8V

LOADING

SC70-6L
7

31 mOhm @1.8V

LOADING

P-TYPE 8V/5V

SIA413DJ

C7810
1

SiA427

CHANNEL
RDS(ON)

10%
10V
X5R
201

5V_SUS FET

3.3V S3 FET

5%
1/20W
MF
201

MOSFET

=P5V_3V3_SUS_EN

47K

5%
1/10W
MF-LF
603

IN

R7810

P3V3S3_EN_L

S 1

62 61

SOT563

10%
16V
X5R
402

0.01UF

P3V3SUS_SS

4 7

SSM6N37FEAPE

2 G

C7811
0.033UF

5%
1/20W
MF
2201

=PP3V3_S3_FET

=PP3V3_SUS_FET 7

3.3V SUS FET

C7820

R7820

P3V3SUS_EN_L 1 12K 2

S 1

5%
1/16W
MF-LF
402

D 6

2 G

Q7812

R7812
100K

=PP3V3_S3_P3V3S3FET

10%
16V 2
X5R
402

PP3V3_S3_FET_R
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

SC70-6L
7

SOT563

C7821 1

0.033UF

5%
1/20W
MF
2 201

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

D 6

SSM6N37FEAPE
CRITICAL

3.2 A (EDP)
CRITICAL

R7822
100K

Q7810

26 mOhm @1.8V

=PP3V3_S5_P3V3SUSFET

Q7822

P-TYPE 8V/5V

CRITICAL

Q7820
SC70-6L

SiA427

CHANNEL
LOADING

SIA427DJ

SIA427DJ

45 72

10%
10V
X5R
201

402

3.3V S3 FET

ISNS_3V3S0_P

MOSFET
RDS(ON)

0.01UF

P3V3S0_SS

3.3V_SUS FET

16V
CERM

402

5%
1/20W
MF
201

10%

MF-LF

91K

5%
1/16W

45 72

3.3V S0 FET

R7830

16V

1/16W

=PP3V3_S0_FET

ISNS_3V3S0_N

0.033UF

5%
1/20W
MF
2 201

SSM6N37FEAPE

MF-LF

C7809

R7802

C7831

10K

D 3

PP3V3_S4_FET_R

Q7809

R7804

=PP3V3_S4_P3V3S4FET

1
3

SC70-6L
7

SC70-6L
7

2
4

CRITICAL

Q7800
SIA427DJ

3.3V S4 FET

PP3V3_S0_FET_R

SIA427DJ

1/16W

376S0945

1%
1W
MF-1
0612

MOSFET

TPCP8102

CHANNEL

P-TYPE

RDS(ON)

18 MOHM @4.5V

LOADING

1.678 A (EDP)

5%

=PP1V5_S3RS0_FET 7

1/20W

10%

MF

16V

201

CERM
402

5%
1/4W
MF-LF
1206

Q7802

D 3

SSM6N37FEAPE
SOT563

P1V5S3RS0_RAMP_DONE
OUT

8
62

IN

=P5VS0_EN

5 G

S 4

1.5V S3/S0 FET


MOSFET

PQFN2X2

CHANNEL

N-TYPE

RDS(ON)

9.4 mOhm @4.5V

LOADING

5 A (EDP)

SYNC_MASTER=K21_MLB
PAGE TITLE

SYNC_DATE=07/28/2011

Power FETs
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

78 OF 109

SHEET

61 OF 73

S5 Rail Enables & PGOOD

0.1UF
10%

VDD

6.3V 2
X5R
201

IN

62 7

U7941

5%
1/20W
MF
201

IN_A

OUT_A*

IN_B

(OD,IPU)

(IPD)

=PP3V3_S5_PWRCTL 6
Threshold: ??
DLY > 10 ms
S5PGOOD_DLY 7
1

343S0497

SLG4AP012
TDFN

SMC_PM_G2_EN
MAKE_BASE=TRUE

(OD,IPU)

OUT_A

P3V3S5_EN
MAKE_BASE=TRUE

C7942

10%
2 16V
X5R
402

NO STUFF

=P5V3V3_REG_EN
OUT

55

62 7

SMC_ADAPTER_EN

SMC_PM_G2_ENABLE

SMC_S4_WAKESRC_EN

PM_SUS_EN

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

Run (S0)

Sleep (S3)

Deep Sleep (S4AC)

Deep Sleep (S4)

Deep Sleep (S5AC)

Deep Sleep (S5)

Battery Off (G3HotAC)

toggle 3Hz

Battery Off (G3Hot)

DLY

OUT

MAKE_BASE=TRUE

(OD,IPU)

THRM
PAD

GND

220PF

10%
2 25V
X7R-CERM
201

MAKE_BASE=TRUE

20%
10V

6
41 17
2

IN

PLACE_NEAR=U7300.16:6mm

R7911

5%
1/20W
MF
201

=P5VS3_EN

MAKE_BASE=TRUE

55

OUT

NO STUFF

1 C7913
0.068UF

R7912

5.1K

9.1K

5%
1/20W
MF
1 201

10%
10V
CERM
402

P3V3S3_EN

P5V3V3_S4_EN

MAKE_BASE=TRUE

=TBTAPWRSW_EN

MAKE_BASE=TRUE

OUT

64

=P3V3S4_EN

OUT

61

NC

C7910

0.47UF

NOSTUFF

SMC_S4_WAKESRC_EN

PLACE_NEAR=Q7812.2:6mm

PLACE_NEAR=U7300.16:6mm

1
NC

=P3V3S3_EN

OUT

61

=DDRREG_EN

OUT

56

=USB_PWR_EN

OUT

6 39 40

MAKE_BASE=TRUE

DDRREG_EN

SOT891
4

S5_PWRGD (old name RSMRST_PWRGD)-->SMC


SMC-->PM_DSW_PWRGD

IN

P5VS3_EN

74LVC1G32

PM_SLP_S5_L

402

42 41

5%
1/20W
MF
201

DP S4 Power Enable

U7970

PM_SLP_S5_L:100K pull down on PCH page

0.1uF

41

CERM

C7941

PM_SLP_S4_L

IN

PLACE_NEAR=Q7812.2:6mm

C7970

S5_PWRGD

R7913
49
26 17
41 37

=PP3V3_S5_PWRCTL
PLACE_NEAR=U7940.1:2.3mm

OUT_B

3.3V,5V S3 ENABLE

State

Sleep (S3AC)

=P3V3S5_ENOUT

0.033UF

4 NC
3 P5V3V3_REG_EN
MAKE_BASE=TRUE

2:1 +
1.3V DLY_1C

100 2

41

R7941

CRITICAL

C7940 1

Mobile System Power State Table

=PP3V42_G3H_PWRCTL Internal pull-ups 100K +/- 20%

62 7

C7912
0.47UF

10%
6.3V
CERM-X5R
402

10%
6.3V
CERM-X5R
402

R7915

MAKE_BASE=TRUE

0
1

2
5%
1/16W
MF-LF

R7974
ALL_SYS_PWRGD

62 52 41 25 23

CPUVCORE ENABLE

402

CPUIMVP_VR_ON

5%
1/20W
MF
201

57

OUT

S0 ENABLE

PLACE_NEAR=U7400.1:5mm

62 41 26 17

R7978

PM_SLP_S3_L

IN

100

PM_SLP_S3_R_L

5%
1/20W
MF
201

3.3V/5.0V Sus ENABLE

=PP3V3_S5_PWRCTL

62 7

7
62

PLACE_NEAR=U7940.5:2.3mm
1

62 7

=PP3V3_S0_VMON

150K

1%
1/20W
MF
201 2

R7951
15K

R7953
1K

7.15K

R7954
1

=PP1V5_S3RS0_VMON

1K

VMON_Q3_BASE

5%
1/20W
MF
201

PP1V5_S3RS0

Q1
Q2

7
2

NC

=PP1V05_S0_VMON 1

1K

5%
1/20W
MF
201

VMON_Q4_BASE

353S2809
S0PGD_BJT_GND_R

Worst-Case Thresholds:

R79571

Q2: 0.XXXV
Q3: 0.640V
3.3V w/Divider: 2.345V
Q4: 0.660V

62 7

=PP1V5_S3RS0_VMON
C7960 1
=PP1V05_S0_VMON 0.1UF
62 7

10K

1/20W
MF
2012

1%
1/20W
MF
201 2

P5V_DIV_VMON

S0PGOOD_ISL

S0PGOOD_ISL

R79721

1%
1/20W
MF
2012

IN

1%
1/20W
MF
201 2

R7971
12.4K

1%
1/20W
MF
2012

S0PGOOD_ISL

R79731
15K

IN

100

P3V3S5_PGOOD 1

P5VS3_PGOOD

5%
1/20W
MF
201

U7960

3
5
6

ISL88042IRTEZ
TDFN
(IPU)
V2MON CRITICAL MR*
V3MON
S0PGOOD_ISL
V4MON
RST*

GND

1%
1/20W
MF
2012

59

IN

54

IN

100

5%
1/20W
MF
201

100

5 SENSE

5%
1/20W
MF
201 2

=PP3V3_SUS_PWRCTL

C7930
0.1UF

54

C7987

C7981

PLACE_NEAR=U7770.3:6mm

0.47UF

10%
6.3V
CERM-X5R
402

C7988

C7986
0.47UF

0.47UF

10%
6.3V
CERM-X5R
402

10%
6.3V
CERM-X5R
402

10%
6.3V
CERM-X5R
402

7 62

10%
6.3V 2
X5R
201

100K

5%
1/20W
MF
201 2

U7930 RESET*

SOT23-6

MR* 3

PM_RSMRST_L

OUT

17

PM_RSMRST_L goes to U1800.C21

(90K IPU)

C7931

WLAN Enable Generation

1000PF

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))


NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

NO STUFF

R7966
1

100

PM_WLAN_EN_L
SUS_PGOOD_MR_L

Q7925

37 23 18

IN

AP_PWR_EN

SOT-363
2

NC

(AC_EN_L)

SOT-363

SYNC_MASTER=J13_MLB_NON_POR

NO STUFF

IN

5%
1/20W
MF
201 2

S0PGOOD_ISL
2

ALL_SYS_PWRGD

OUT

62 41 26 17

IN

DRAWING NUMBER

2N7002DW-X-G

SOT-363
5

Apple Inc.

PM_SLP_S3_L

051-9277

(PM_SLP_S3_L)

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION

2.8.0

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

23 25 41 52 62

5%
1/20W
MF
201

Power Control 1/ENABLE

Q7920

SYNC_DATE=11/10/2011

PAGE TITLE

R79291

SMC_ADAPTER_EN

NC

AC_EN_L

2N7002DW-X-G
6

42 41 17

Q7920

R7964
100

Unused fet

SOT-363

5%
1/20W
MF
201

2N7002DW-X-G

2N7002DW-X-G

Q7925

NC

37

OUT

R7962
330

59

R79331

THRM_PAD

10%
2 16V
X7R-CERM
0201

5%
1/20W
MF
201

ALL_SYS_PWRGD_R

353S2310

OUT

60

VFRQ Low: Fix Frequency


VFRQ High: Variable Frequency

=PP3V3_S5_PWRCTL

R7901
1

CPUVCCIOS0_PGOOD
PVCCSA_PGOOD

60

PLACE_NEAR=U7720.5:6mm

CHGR VFRQ Generation

5%
1/20W
MF
201

R7963
1 NC

OUT

=1V05_S0_LDO_ENOUT
=CPUVCCIOS0_EN OUT

S 2

No stuff C7931, 12ms


Min delay time
U7930 Sense input
threhold is 3.07V

VDD

6.04K

P1V5_DIV_VMON
R79611S0PGOOD_ISL
P1V05_DIV_VMON
1

15K

55

10%
6.3V
X5R 2
201

62 7

P1V8S0_PGOOD

S0PGOOD_ISL

R79601S0PGOOD_ISL
6.04K
R79701
1%

5%
1/20W
MF
201

2
7

S0PGOOD_ISL

55

=PP5V_S0_VMON

100

CPUIMVP_AXG_PGOOD 1

R7965

=PP3V3_S0_VMON

=P1V5S0_EN

GND

10K

NO STUFF

R7968

IN

60

=PVCCSA_EN

0.47UF

S4_PGOOD_CT 4 CT

R79671

P1V5S0_PGOOD from U7710

60

OUT

PLACE_NEAR=U7930.6:2.3mm

=PP3V3_SUS_PWRCTL

=PP3V3_S0_PWRCTL

(ISL Version in development)


IN

=P1V8S0_EN

VDD

S0 Rail PGOOD Circuitry


57

PLACE_NEAR=U7720.5:6mm

MAKE_BASE=TRUE

CRITICAL
62 7

64

CPUVCCIOS0_EN

3.3V SUS Detect

100

5%
1/20W
MF
201 2

OUT

MAKE_BASE=TRUE

TPS3808G33DBVRG4

Thresholds:
VDD:
2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V

SOD-VESM-HF

R7930
62 7

45

=TBT_S0_EN

MAKE_BASE=TRUE

5%
1/20W
MF
2 201

OUT

P1V5S0_EN

53

61

38 61

=PBUSVSENS_EN

D 3

1 G

NO STUFF
Could stuff R7930 to satisfy
PCH power down timing t235

61

OUT

PVCCSA_EN

5%
1/20W
MF
201

Q4

OUT

=P3V3S0_EN

P1V8S0_EN

R7917

CRITICAL

PLACE_NEAR=U7770.3:6mm

=P5VS0_EN

MAKE_BASE=TRUE

NO STUFF

5.1K

5%
1/20W
1 MF
201

PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm

ASMCC0179

Q3

62 7

=P5V_3V3_SUS_EN
OUT

MAKE_BASE=TRUE

R7955

PM_SUS_EN

5%
1/20W
MF
201

39K

5%
1/20W
MF
201

PLACE_NEAR=U7600.3:6mm

DFN2015H4-8

NC

45

PM_SLP_SUS_L

Q7950
5

1%
1/20W
MF
2 201

IN

GND

5%
1/20W
MF
201

R7952

Y 4
17

VMON_Q2_BASE

23 25 41 52 62

VMON_3V3_DIV 1

62 7

ALL_SYS_PWRGD

R7988

20K

R7986

5%
1/20W
MF
201

CHGR_VFRQOUT

Q7931

SSM3K15FV

3 B

S0PGD_C
6

1%
1/20W
MF
2 201

U7940

74AUP1G3208
SOT891
1 A

R7981

5%
1/20W
MF
201

PLACE_NEAR=U7100.15:6mm

10K

VCC

SMC_BATLOW_L:100K pull up on SMC page


SMC_BATLOW_L
42 41
IN

R79561
1

10%
6.3V 2
X5R
201

R7931

0.1UF

=PP3V3_S5_VMON

R7987

33K

=PP3V42_G3H_PWRCTL

C7943

S0 Rail PGOOD (BJT Version)

MAKE_BASE=TRUE

(PM_SLP_S3_R_L)

BRANCH
PAGE

79 OF 109

SHEET

62 OF 73

PART NUMBER
518S0829

QTY
1

DESCRIPTION

REFERENCE DES

CONNTWIN-AX,P=0.4,30P,W-BOSS,HF

J9000

CRITICAL

BOM OPTION

LCD Connector
Internal DP Connector: 518S0787
OMIT_TABLE
CRITICAL

J9000
CABLINE-CA
F-RT-SM

Pull-ups on panel side,


4.7 kOhm to 3.3V

R9061
44

BI

=I2C_TCON_SDA

65 6

31

PPVOUT_SW_LCDBKLT

I2C_TCON_SDA_R

5%
1/20W
MF
201

NC

IN

=I2C_TCON_SCL

I2C_TCON_SCL_R

U9000

OUT

DP_INT_HPD

FPF1009
8

IN

LCD_IG_PWR_EN

R9014 1

ON

VIN_1

VOUT_1

PP3V3_SW_LCD_UF

VIN_2

VOUT_2

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

FERR-120-OHM-1.5A

1K
5%
1/20W
MF
201

C9009
0.1UF

2
2

10%
6.3V
X5R
201

65 6

OUT

65 6

OUT

65 6

OUT

65 6

OUT

65 6

OUT

C9011
0.1UF
10%
6.3V
X5R
201

C9012

66 9

10UF
2

BI

DP_INT_AUX_CH_N

20%
6.3V
X5R
603

10%
16V
X5R-CERM
0201
66 9

BI

DP_INT_AUX_CH_P

0.1UF
IN

DP_INT_ML_P<0>

IN

DP_INT_ML_N<0>

R9070
100K

2
2

5%
1/20W
MF
201

C9025

8
9

11

DP_INT_HPD_CONN

12
13
14

DisplayPort I/F

17

PP3V3_SW_LCD

18

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
66 6
66 6

19
20

DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_C_P

21
22
23

DP_INT_ML_F_P<0>
DP_INT_ML_F_N<0>

24
25
26

(DP_INT_AUX_CH_C_P)

NC
NC

10%
16V
X5R-CERM
0201

PLACE_NEAR=J9000.25:1mm

R9017

1M

5%
1/20W
MF
201 2

C9021
0.1UF
1

LED Backlight I/F

10

16

66 6

0.1UF

10%
16V
X5R-CERM
0201
66 9

15

66 6

C9020
66 9

(DP_INT_AUX_CH_C_N)

10%
16V
X7R-CERM
0201

NC

1000PF

0.1UF
1

C9015
C9024

0402-LF

THRM
PAD
7

OUT

NC

LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1

5%
1/20W
MF
201

L9004

MFET-2X2-8IN

GND

65 6

R9060

CRITICAL
=PP3V3_S3_LCD

5%
1/20W
MF
201

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

3
4

R9062
44

R9018

27
28
29
30

1M

5%
1/20W
MF
2 201

33
34

PLACE_NEAR=J9000.24:1mm

35

36
10%
16V
X5R-CERM
0201

37
38
39
40
41

PLACE_NEAR=J9000.14:2mm
1

R9050

32
1

R9080

100K

100K

5%
1/20W
MF
201

5%
1/20W
MF
201

PLACE_NEAR=J9000.3:2mm

C9017

1000PF
5%
50V
C0G-CERM
603

SYNC_MASTER=K21_MLB

SYNC_DATE=07/28/2011

PAGE TITLE

Internal DisplayPort Connector


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

90 OF 109

SHEET

63 OF 73

3
64 7

V3P3 must be S4 to support


wake from Thunderbolt devices.

C9481

22UF
20%
6.3V
X5R-CERM-1
603

0.1UF
2

10%
16V
X5R-CERM
0201

C9410
0.1UF

10%
25V
X5R-CERM
0603

10%
25V
X5R
402

12
14

OUT
VHV

U9410

10%
16V
X5R-CERM
0201

CD3210A0RGP

QFN

16 RSVD

C9486

=TBTAPWRSW_EN

36 34

IN

TBT_A_HV_EN

11 HV_EN

ISET_S0 10

TBTAPWRSW_ISET_S0

=TBT_S0_EN

17 S0

ISET_S3 9

TBTAPWRSW_ISET_S3

IN

70 34

BI

70 34

BI

C9430

DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_C_P

0.1UF

C9431

21

TBTHV:P15V

R94101

R9411

22.6K

22.6K

1%
1/20W
MF
201 2

IN

70 34

IN

64 7

R9412

R9414

1%
1/20W
MF
201 2

1%
1/20W
MF
2 201

5%
1/20W
MF
201

TBT_A_BIAS

IN

BIASIN

DP_AUXIO_EN

AUXIO_EN

DP_TBTPA_AUXCH_N
DP_TBTPA_AUXCH_P

AUXAUX+

DP_TBTSNK0_DDC_DATA
DP_TBTSNK0_DDC_CLK

70
70

10%
X5R-CERM

16V
0201

BI

IN

34

2
20%
X5R

OUT

6.3V
0201

70
70

2
20%
X5R

34

6.3V
0201

IN

DDC_DAT
DDC_CLK

SOT891

16

CA_DETOUT

DP_TBTPA_ML_P<1>
DP_TBTPA_ML_N<1>

11

DP+
DP-

TBT_A_LSTX
TBT_A_LSRX_UNBUF

14

34

IN

TBT_A_DP_PWRDN

34

OUT

DP_TBTPA_HPD

10

13
6
12

R9426

LSTX
LSRX

TBT_A_LSRX

Y = B
1

C9460
0.1UF

Single-fault protection
requires two Rs per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.

20%
10V
CERM
402

24

AUXIOAUXIO+

23

C9425
0.1UF

10%
16V
X5R-CERM
0201

5%
1/20W
MF
201

DP_A_AUXCH_DDC_N
DP_A_AUXCH_DDC_P

22

64 70
64 70

CA_DET

18

TBT_A_CONFIG1_RC

DPMLO+
DPMLO-

19

DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

20

64

64 70
64 70

TBT: LSX_A_R2P/P2R (P/N)

DP_PD
HPDOUT

TBT_A_HPD

17

HPD
GND THMPAD

1M

VCC
OUT

BIASOUT

TBT: RX_1 Bias Sink

TBT_A_CONFIG1_BUF

74AUP1T97

34

64

VOLTAGE=3.3V
1

CBTL05023
1

U9460

22.6K

C9433 1

TBT_A_CIO_SEL

16V
0201

CRITICAL

TBTHV:P15V

22.6K

0.22UF

IN

PP3V3_SW_TBTAPWR

1%
1/20W
MF
2 201

TBTAPWRSW_ISET_S0_R

R94131

DP_TBTPA_ML_C_P<1>
DP_TBTPA_ML_C_N<1>

36.5K

1%
1/20W
MF
2 201

TBTAPWRSW_ISET_S3_R

TBTHV:P15V

70 34

0.22UF

TBTHV:P15V
12V: See
below

100K

10%
X5R-CERM

0.1UF

TBTAPWRSW_ISET_V3P3

THRM
PAD

1
2
3
4
13

GND

C9432 1

ISET_V3P3 8

IN

62

25

RSVD 15

5 EN

62

5%
1/20W
MF
201

HVQFN

10%
25V
X5R
402

10K

SIGNAL_MODEL=TBT_MUX
34

0.1UF

20%
6.3V
CERM-X5R
0402

R9429 1

R9427

7 64

C9411

10UF

U9420

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

0.1UF

10%
16V
X5R-CERM
0201

VDD
CRITICAL

PPHV_SW_TBTAPWR

C9485

CRITICAL

0.1UF

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

V3P3OUT 18
V3P3

6
7

18.9V Max

4.7UF

Max
1200mA
930mA (assumes 15V, 12W minimum)
930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
PP3V3_SW_TBTAPWR

19
20

=PPHV_SW_TBTAPWRSW

C9415

Min
1030mA
830mA
830mA

10%
16V
X5R-CERM
0201

25

C9480

100UF

20%
6.3V
POLY-TANT
CASE-B2-SM

Nominal
IV3P3 1100mA
IHVS0
890mA
IHVS3
890mA

CRITICAL

C9487

C9421

0.1UF

CRITICAL

C9420

=PP3V3_S4_TBTAPWRSW

64

R9428
100K

5%
1/20W
MF
201

GND
2

PP3V3_SW_TBTAPWR

15

7
3.3V/HV Power MUX

21

C
ILIM = 40000 / RISET

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

RES,MF,1/20W,17.8K,1,0201

R9410,R9413

TBTHV:P12V

118S0145

RES,MF,1/20W,17.8K,1,0201

R9411,R9414

TBTHV:P12V

Min
1090mA

0.01UF

PP3V3RHV_SW_TBTAPWR

C9400

Max
1170mA (12W minimum)

R9401
12

5%
1/20W
MF
2 201

TBTACONN_20_RC

OUT

TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

C9474

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

(Both Cs)
1

2
20%
4V 201
CERM-X5R-1

0.47UF

C9475

70
70

TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>

20%
4V 201
CERM-X5R-1

0.47UF

C9401
R9494 1

GND_VOID=TRUE
1

1K
5%
1/20W
MF
201

IN

70 34

IN

C9478 1

DP_TBTPA_ML_C_P<3>
DP_TBTPA_ML_C_N<3>

C9479 1

20%
X5R

6.3V
0201

70
70

2
20%
X5R

0.22UF

64

6.3V
0201

70 34
70 34

OUT
OUT

TBT_A_D2R_P<1>
TBT_A_D2R_N<1>

(Both Cs)

C9477

0.47UF

2
5%
MF

R9479

470K

2.2K

5%
1/20W
MF
201

5%
1/20W
MF
201

GND_VOID=TRUE

0.01UF

2
1/20W
201

TBTACONN_7_C

70

0.22UF

1
3
5
7
9
11
8
15
17
19

GND_VOID=TRUE
1

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

10%
25V
X5R-CERM
0201
2

TBT_A_R2D_C_P<0>
TBT_A_R2D_C_N<0>

IN

34 70

IN

34 70

R9471
470K

5%
1/20W
MF
201

5%
1/20W
MF
201

(0-18.9V)
DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

64 70

64 70

TBT: LSX_R2P/P2R (P/N)

(Both Ds)

D9498

TBT_A_D2R_C_P<1>
TBT_A_D2R_C_N<1>

D9499

20%
4V 201
CERM-X5R-1

TSLP-2-7
A

70
70

BAR90-02LRH

C9472 1

TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N

70

TBT: TX_1

TSLP-2-7

TBT_A_R2D_P<1>
TBT_A_R2D_N<1>

C9473 1
0.22UF
GND_VOID=TRUE

L9498

DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N

514-0818

GND_VOID=TRUE

20%
X5R

6.3V
0201

20%
X5R

6.3V
0201

TBT_A_R2D_C_P<1>
TBT_A_R2D_C_N<1>

IN

34 70

IN

34 70

GND_VOID=TRUE
1

R9472
470K

650NH-5%-0.430MA-0.52OHM
2

0.22UF
70

BAR90-02LRH

(Both Cs)

SHIELD PINS

70 64

6.3V
0201

GND_VOID=TRUE
1

R9470
470K

CRITICAL

70 64

6.3V
0201

20%
X5R

GND_VOID=TRUE

CRITICAL

SIGNAL_MODEL=TBTPIN
GND_VOID=TRUE

GND_VOID=TRUE

70

1/20W
201

20%
X5R

C9406

F-RT-TH

HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
GND
GND
AUX_CHP
ML_LANE2P
AUX_CHN
ML_LANE2N
DP_PWR
RETURN

C9471 1

R9499

2.2K

20%
4V 201
CERM-X5R-1

0.47UF

TBT_A_BIAS

GND_VOID=TRUE

470K

DP_TBTPA_ML_P<3>
DP_TBTPA_ML_N<3>

5%
MF

10%
50V
X7R-CERM
0402

2
4
6
13
10
12
14
16
18
20

SIGNAL_MODEL=EMPTY

TBT: Unused

R9498 1

C9476

5%
1/20W
MF
201

R9478
2

0.22UF

DP Dir

TBT_A_R2D_P<0>
TBT_A_R2D_N<0>

TBT: TX_0

MDP-J11

1K

SIGNAL_MODEL=EMPTY

70 34

TBT Dir

R9495

0.22UF
70

J9400

C9470 1
70

CRITICAL

GND_VOID=TRUE

(Both Cs)

(0-18.9V)
TBT Dir

GND_VOID=TRUE

0.01UF

GND_VOID=TRUE

DP Dir

For J9400 TBT SMT pads


(3, 5, 17 & 19):

10%
25V
X5R-CERM
0201

28
27
26
25
24
23
22
21

OUT

70 34

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

0.01UF
10%
50V
X7R-CERM
0402

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

0603

GND_VOID=TRUE

70 34

C9405

FERR-120-OHM-3A

BOM OPTION

118S0145

Nominal
IHVS0/S3 1120mA

Thunderbolt Connector A

L9400

For 12V systems:

R9473
470K

5%
1/20W
MF
201

5%
1/20W
MF
201

0603

SIGNAL_MODEL=EMPTY

C9498

30PF

5%
50V
C0G-NP0
0402

CRITICAL

C9499

470k Rs for ESD protection


on AC-coupled signals.

L9499

30PF

650NH-5%-0.430MA-0.52OHM

5%
50V
C0G-NP0
0402

1
0603

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

A
34

64

TBT_A_HPD

64

TBT_A_CONFIG1_RC

OUT

SYNC_MASTER=J11_MLB

C9402
0.01UF

TBT_A_CONFIG2_RC

R9452

1M

5%
1/20W
MF
201

R9451
1M

5%
1/20W
MF
201

C9494

330PF

10%
16V
X7R-CERM
0201

C9495

10%
16V
X7R-CERM
0201

10%
25V
X5R-CERM 2
0201

100K

330PF
2

R9441

Thunderbolt Connector A
DRAWING NUMBER

Apple Inc.

051-9277

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

2.8.0

Sink HPD range:


High: 2.0 - 5.0V
Low: 0 - 0.8V

5%
1/20W
MF
201

SYNC_DATE=10/03/2011

PAGE TITLE

DP Source must pull


down HPD input with
greater than or equal
to 100K (DPv1.1a).

BRANCH
PAGE

94 OF 109

SHEET

64 OF 73

PPBUS S0 LCDBkLT FET


MOSFET

FDC638APZ

CHANNEL

P-TYPE

RDS(ON)

43 mOhm @4.5V

LOADING

0.65 A (EDP)

CRITICAL

Q9706
FDC638APZ_SBMS001
SSOT6-HF

PPBUS_S0_LCDBKLT_FUSED

BOTTOM

C9782

R9788

AND PPBUS_SW_BKL
ON THE SENSOR PAGE

10%
16V

1%
1/20W

X7R-CERM

MF

=PP5V_S0_BKL

PLACE_NEAR=L9701.2:3mm

CRITICAL

D9701

15UH-2.8A
8

=PPBUS_SW_BKL

R9789

C9712

10%
25V
X5R
805

10UF

1%
1/20W
MF
201

SOD-123

CRITICAL

147K

CRITICAL

L9701

LCDBKLT_EN_DIV

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

0402

201

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS


*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

0.1UF

301K

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

603-HF

=PPBUS_S0_LCDBKLT

PPBUS_SW_LCDBKLT_PWR

THERE IS A SENSE RESISTOR BETWEEN

8 65

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

F9700
3AMP-32V-467
1

PPBUS_SW_LCDBKLT_PWR

PIMB053T-SM

C9713
0.1UF

PLACE_NEAR=L9701.1:3mm

10%
25V
X5R
402

PPBUS_SW_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.150 MM
VOLTAGE=50V
SWITCH_NODE=TRUE
DIDT=TRUE

PLACE_NEAR=U9701.A5:3mm

PPVOUT_SW_LCDBKLT
CRITICAL

RB160M-60G

C9796

220PF

10UF

10%

2 50V
X7R-CERM

0402

PLACE_NEAR=L9701.1:3mm

CRITICAL

C9797

C9799

6 63

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V

10UF

10%
50V
X5R
1210-1

10%
50V
X5R
1210-1

PLACE_NEAR=D9701.2:5mm

LCDBKLT_EN_L

PLACE_NEAR=D9701.2:3mm
PLACE_NEAR=U9701.D1:5mm

Q9707

10%
25V
X5R
603-1

LCDBKLT_DISABLE

10%

XW9720
SM

201
PPVOUT_SW_LCDBKLT_FB
VOLTAGE=50V
MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM

C9711

10%
6.3V
X5R
201

PLACE_NEAR=C9797.1:5mm

0.1UF

SOT563

0.01UF

PLACE_NEAR=U9701.C4:4mm

SSM6N15FEAPE

BKLT_PLT_RST_L

C4

IN

10V
2 X5R

=PP3V3_S0_BKL_VDDIO

LCD_BKLT_EN

Q9707

25

C9714

C1

IN

D1

1UF

SOT563

PLACE_NEAR=U9701.D1:3mm

C9710

SSM6N15FEAPE

VIN

VDDIO VLDO

U9701
25-BUMP-MICRO

5%
1/20W
MF
201

5%
1/20W
MF
201

PPBUS_SW_LCDBKLT_PWR

65 8

R9731
200K

1%
1/20W
MF
201

R9704
8

IN

LCD_BKLT_PWM

33

5%
1/20W
MF
201

R9715

BKL_PWM
BKL_EN

A4

PWM

A3

EN

D4

C3

PLACE_SIDE=BOTTOM

SCLK
SDA

FAULT

100K
1%
1/20W
MF
201

Fpwm=9.62kHz
see spec for others

C9704
33PF
5%

D3

TP_BKL_FAULT

BKL_SCL
BKL_SDA

BKLT:PROD

B2

R9717
PLACE_NEAR=U9701.E5:10mm

A5

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

OUT1

E5

OUT2
OUT3

D5
C5

BKL_ISEN1
BKL_ISEN2
BKL_ISEN3

OUT4
OUT5

E3

BKL_ISEN4

OUT6

E1

GND_SW
GND_SW

Addr: 0x58(Wr)/0x59(Rd)

B1

E2

R9755
10K

5%
1/20W
MF
201

R9716
90.9K
1%
1/20W
MF
201

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

OUT

6 63

OUT

6 63

OUT

6 63

OUT

6 63

OUT

6 63

OUT

6 63

R9718
1

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

BKL_ISEN5
BKL_ISEN6

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

5%
1/16W
MF-LF
402

BOTTOM

BKLT:PROD

R9719
PLACE_NEAR=U9701.C5:10mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

5%
1/16W
MF-LF
402

BOTTOM

BKLT:PROD

R9714

R9720

18.2K

LED_RETURN_1

BKLT:PROD
PLACE_NEAR=U9701.D5:10mm

I_LED=20.3mA

25V
NPO-C0G
0201

5%
1/16W
MF-LF
402

BOTTOM

GND_L

FSET

FB

A1

=I2C_BKL_1_SDA

B4

ISET

E4

BI

R9757
44

BKL_FSET

B3

GND_S

IN

BKL_ISET

5%
1/20W
MF
201

C2

B5

44

BKL_FLTR

VSYNC
CRITICAL SW_0
SW_1
FILTER
LP8550

R9753
=I2C_BKL_1_SCL

10K

D2

A2

R9741

BKL_VSYNC_R

PLACE_NEAR=U9701.E3:10mm

1%
1/20W
MF
201

XW9710
SM

GND_BKL_SGND

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins) MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BOTTOM

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

5%
1/16W
MF-LF
402

BKLT:PROD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

R9721
PLACE_NEAR=U9701.E2:10mm

I_LED=369/Riset
(EEPROM should set EN_I_RES=1)

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

5%
1/16W
MF-LF
402

BOTTOM

BKLT:PROD

R9722
PLACE_NEAR=U9701.E1:10mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BOTTOM

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

5%
1/16W
MF-LF
402

SYNC_MASTER=K21_MLB

103S0198

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

R9717,R9718,R9719

BKLT:ENG

10.2 ohm resistors for current

103S0198

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

R9720,R9721,R9722

BKLT:ENG

measurement on LED strings.

SYNC_DATE=07/28/2011

PAGE TITLE

LCD Backlight Driver


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

97 OF 109

SHEET

65 OF 73

CPU Signal Constraints

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

CPU_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

ELECTRICAL_CONSTRAINT_SET

TABLE_PHYSICAL_RULE_ITEM

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

0.100 MM

0.100 MM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

CPU_AGTL

TOP,BOTTOM

=2x_DIELECTRIC

=STANDARD

DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>
FDI_DATA_P<7:0>
FDI_DATA_N<7:0>
FDI_FSYNC<1..0>
FDI_LSYNC<1..0>
FDI_INT

CPU_45S
CPU_45S
CPU_45S

CPU_COMP
CPU_AGTL
CPU_AGTL

CPU_PECI
PM_SYNC
PM_MEM_PWRGD

CPU_45S
CPU_45S
CPU_45S

CPU_ITP
CPU_ITP
CPU_ITP

XDP_DBRESET_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
DMI_CLK100M
DMI_CLK100M
DPLL_REF_CLK120M
DPLL_REF_CLK120M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L
XDP_BPM_L_R_CFG
(XDP_BPM_L_R_CFG)
(XDP_BPM_L_R_CFG)
(FSB_CPURST_L)

CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S

CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_ITP
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP

EDP_COMP
CPU_PEG_COMP
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
CPU_CFG<11..0>
CPU_CATERR_L
CPU_VCCIO_SEL
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
DPLL_REF_CLKP
DPLL_REF_CLKN
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
XDP_BPM_L<3..0>
XDP_BPM_L<7..4>
XDP_OBSDATA_B<3..0>
CPU_CFG<15..12>
XDP_CPURST_L

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCIOSENSE
CPU_VCCIOSENSE
CPU_AXG_SENSE
CPU_AXG_SENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE

SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N

?
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

CPU_8MIL_2ANY

CPU_8MIL_2ANY

8 MIL

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_ITP

CPU_ITP_2ANY

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

=4x_DIELECTRIC

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_COMP

CPU_COMP

TABLE_SPACING_RULE_ITEM

CPU_COMP_2SELF

CPU_COMP_2SELF

TOP,BOTTOM

=6x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_COMP

Note: CPU_8MIL and CPU_ITP can be converted


back to TABLE_SPACING_RULE
once rdar://10308147 is resolved

CPU_PECI
PM_SYNC
PM_MEM_PWRGD

TABLE_SPACING_RULE_ITEM

CPU_ITP_2ANY

TABLE_SPACING_RULE_ITEM

CPU_COMP_2OTHER

CPU_COMP_2OTHER

TOP,BOTTOM

=10x_DIELECTRIC

CPU_SM_RCOMP
CPU_SM_RCOMP
CPU_SM_RCOMP

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

CPU_COMP_2SELF

=4x_DIELECTRIC

CPU_CATERR_L
TABLE_SPACING_RULE_ITEM

CPU_COMP_2OTHER

=6x_DIELECTRIC

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

SPACING_RULE_SET

LAYER

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_VCCSENSE

CPU_VCCSENSE

TABLE_SPACING_RULE_ITEM

CPU_VCCSENSE_2SELF

CPU_VCCSENSE_2SELF

TOP,BOTTOM

=6x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_VCCSENSE

TABLE_SPACING_RULE_ITEM

CPU_VCCSENSE_2OTHER

CPU_VCCSENSE_2OTHER

TOP,BOTTOM

=10x_DIELECTRIC

?
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

CPU_VCCSENSE_2SELF

TABLE_SPACING_RULE_ITEM

CPU_VCCSENSE_2OTHER

=6x_DIELECTRIC

PCI-Express Interface Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

PCIE_80D

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

CLK_PCIE_80D

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

PCIE Clock Spacing


TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_ITEM

CLK_PCIE

CLK_PCIE

CLK_PCIE_2SELF

TABLE_SPACING_RULE_ITEM

CLK_PCIE_2SELF

TOP,BOTTOM

=6x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

CLK_PCIE

CLK_PCIE_2OTHER

CLK_PCIE_2OTHER

SPACING_RULE_SET

TOP,BOTTOM

=10x_DIELECTRIC

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

CLK_PCIE_2SELF

=4x_DIELECTRIC

?
TABLE_SPACING_RULE_ITEM

CLK_PCIE_2OTHER

=6x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_CPU_TX

PCIE_CPU_TX

PCIE_TX2TX

TABLE_SPACING_RULE_ITEM

PCIE_TX2TX

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_CPU_RX

PCIE_CPU_RX

PCIE_RX2RX

TABLE_SPACING_RULE_ITEM

PCIE_RX2RX

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_CPU_TX

*_CPU_TX

PCIE_TX2OTHERTX

*_CPU_RX

PCIE_RX2OTHERRX

PCIE_CPU_TX

*_CPU_RX

PCIE_TX2RX

PCIE_TX2OTHERTX

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

PCIE_RX2OTHERRX

TOP,BOTTOM

=5x_DIELECTRIC

PCIE_TX2RX

TOP,BOTTOM

=7x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

*_CPU_TX

PCIE_RX2TX

PCIE_CPU_TX

*_TX

PCIE_2OTHERHS

PCIE_RX2TX

TOP,BOTTOM

=7x_DIELECTRIC

PCIE_2OTHERHS

TOP,BOTTOM

=6x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

*_TX

PCIE_2OTHERHS

PCIE_CPU_TX

*_RX

PCIE_2OTHERHS

CPU_SVIDALERT_L
CPU_SVIDSCLK
CPU_SVIDSOUT

CPU_45S
CPU_45S
CPU_45S

CPU_COMP
CPU_COMP
CPU_COMP

CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT

PCIE_CPU_MUX_R2D
PCIE_CPU_MUX_R2D

PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D

PCIE_CPU_TX
PCIE_CPU_TX
PCIE_CPU_TX
PCIE_CPU_TX
PCIE_CPU_RX
PCIE_CPU_RX
PCIE_CPU_RX
PCIE_CPU_RX

PCIE_SSD_R2D_C_P<0>
PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_MUX_IN_P
PCIE_SSD_R2D_MUX_IN_N
PCIE_SSD_D2R_P<0>
PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_MUX_OUT_P
PCIE_SSD_D2R_MUX_OUT_N

PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D

PCIE_CPU_RX
PCIE_CPU_RX
PCIE_CPU_TX
PCIE_CPU_TX
PCIE_CPU_RX
PCIE_CPU_RX
PCIE_CPU_RX
PCIE_CPU_RX

PCIE_SSD_R2D_C_P<1>
PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_P<1>
PCIE_SSD_R2D_N<1>
PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_C_P<1>
PCIE_SSD_D2R_C_N<1>

CLK_PCIE_80D
CLK_PCIE_80D

CLK_PCIE
CLK_PCIE

PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N

DP_TX
DP_TX
DP_TX
DP_TX

DP_INT_ML_P<3..0>
DP_INT_ML_N<3..0>
DP_INT_ML_F_P<3..0>
DP_INT_ML_F_N<3..0>

TABLE_SPACING_RULE_ITEM

PCIE_2OTHER

TOP,BOTTOM

=5x_DIELECTRIC

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_CPU_RX

*_RX

PCIE_2OTHERHS

PCIE_CPU_TX

PCIE_2OTHER

PCIE_CPU_RX

PCIE_2OTHER

SPACING_RULE_SET

LAYER

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_TX2TX

=2.5x_DIELECTRIC

?
TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_RX2RX

=2.5x_DIELECTRIC

PCIE_TX2OTHERTX

=4x_DIELECTRIC

PCIE_RX2OTHERRX

=4x_DIELECTRIC

PCIE_TX2RX

=6x_DIELECTRIC

PCIE_RX2TX

=6x_DIELECTRIC

PCIE_CPU_SSD_R2D
PCIE_CPU_SSD_R2D

TABLE_SPACING_RULE_ITEM

PCH PCIE Spacing

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

PCIE_PCH_TX

PCIE_PCH_TX

PCIE_TX2TX

PCIE_PCH_RX

PCIE_PCH_RX

PCIE_RX2RX

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_CPU_SSD_D2R
PCIE_CPU_SSD_D2R

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_PCH_TX

*_PCH_TX

PCIE_TX2OTHERTX

PCIE_PCH_RX

*_PCH_RX

PCIE_RX2OTHERRX

PCIE_PCH_TX

*_PCH_RX

PCIE_TX2RX

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_CPU_MUX_D2R
PCIE_CPU_MUX_D2R

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_2OTHERHS

=4x_DIELECTRIC

PCIE_2OTHER

=3x_DIELECTRIC

?
PCIE_CLK100M_SSD
PCIE_CLK100M_SSD

PCIE_RX2TX

DP_INT_ML
DP_INT_ML

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_PCH_TX

*_TX

PCIE_2OTHERHS

PCIE_PCH_RX

*_TX

PCIE_2OTHERHS

DP_80D
DP_80D
DP_80D
DP_80D

TABLE_SPACING_ASSIGNMENT_ITEM

Note: DisplayPort tables are on Page 103

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_PCH_TX

*_RX

PCIE_2OTHERHS
TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_PCH_RX

*_RX

PCIE_2OTHERHS

PCIE_PCH_TX

PCIE_2OTHER

DP_INT_AUXCH
DP_INT_AUXCH

DP_80D
DP_80D
DP_80D
DP_80D

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_PCH_RX

DP_AUX
DP_AUX
DP_AUX
DP_AUX

DP_INT_AUX_CH_C_P
DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_P
DP_INT_AUX_CH_N

PCIE_2OTHER

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

9 17

9 17
9 17

10 19 42
10 17
10 17 26

10 23 25
10 23
10 23

9
9
10
10
10
9 23
10 41
12
10 41 42 57
10 19 23
10 19 42
10 16
10 16
8 10
8 10
10 16

10 16
16 23
16 23
23
23
10 23
10 23
10 23
10 23
10 23
10 23
10 23
23
9 23
23

12 57
12 57
12 59
12 59
12 57
12 57
12
12
9
9

9
9

12 57
12 57
12 57

8 38
8 38
38
38
8 38
8 38
38
38

8 38

PCIe SSD

8 38
6 38
6 38
6 8 38
6 8 38

6 16 38
6 16 38

SYNC_MASTER=J13_CONSTRAINTS

TABLE_SPACING_ASSIGNMENT_ITEM

*_PCH_TX

DMI/FDI

9 17

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_PCH_RX

9 17

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_CPU_RX

9 17

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_CPU_RX

9 17

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_CPU_RX

9 17

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

CPU PCIE Spacing

9 17

WEIGHT

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_8MIL

SPACING
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
CPU_AGTL
CPU_AGTL
CPU_AGTL

TABLE_SPACING_RULE_ITEM

CPU_AGTL

NET_TYPE
PHYSICAL
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
CPU_45S
CPU_45S
CPU_45S

DMI_S2N
DMI_S2N
DMI_N2S
DMI_N2S
FDI_DATA
FDI_DATA

TABLE_PHYSICAL_RULE_ITEM

CPU Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

CPU_27P4S

SYNC_DATE=01/11/2012

PAGE TITLE

9 63

CPU Constraints

9 63

DRAWING NUMBER

6 63

Apple Inc.

6 63

DP

051-9277

9 63
9 63

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

6 63
6 63

SIZE

REVISION
BRANCH
PAGE

100 OF 109

SHEET

66 OF 73

Memory Bus Constraints

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MEM_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

MEM_72D

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

ELECTRICAL_CONSTRAINT_SET

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

Spacing Rule Sets


TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=2x_DIELECTRIC

PalPilot Spacing

"Real" Spacing

=2x_DIELECTRIC

=2x_DIELECTRIC

=5.7x_DIELECTRIC

=3x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

MEM_DATA2SELF

TABLE_SPACING_RULE_ITEM

MEM_DQS2OWNDATA

=3x_DIELECTRIC

?
TABLE_SPACING_RULE_ITEM

MEM_CMD2CMD

=3x_DIELECTRIC

MEM_CMD2CTRL

=3x_DIELECTRIC

MEM_CTRL2CTRL

=3x_DIELECTRIC

=4x_DIELECTRIC

=3x_DIELECTRIC

=4x_DIELECTRIC

=3x_DIELECTRIC

=4x_DIELECTRIC

=3x_DIELECTRIC

=8.6x_DIELECTRIC

=6x_DIELECTRIC

=5.7x_DIELECTRIC

=4x_DIELECTRIC

=PWR_P2MM

=PWR_P2MM

=GND_P2MM

=GND_P2MM

=8.6x_DIELECTRIC

=6x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MEM_CLK2CLK

=6x_DIELECTRIC

MEM_2OTHERMEM

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MEM_2PWR

=PWR_P2MM

?
TABLE_SPACING_RULE_ITEM

MEM_2GND

=GND_P2MM

?
TABLE_SPACING_RULE_ITEM

MEM_2OTHER

=6x_DIELECTRIC

Memory to Power Spacing


TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_PWR

MEM_*

MEM_2PWR
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_PWR

DEFAULT

Memory to GND Spacing


TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

GND

MEM_*

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_0

MEM_A_DATA_0

MEM_DQS2OWNDATA

MEM_A_DATA_1

MEM_DQS2OWNDATA

MEM_A_DQS_0

MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_1

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_2

MEM_A_DATA_2

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_2

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_3

MEM_A_DATA_3

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_3

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_4

MEM_A_DATA_4

MEM_DQS2OWNDATA

MEM_A_DQS_5

MEM_A_DATA_5

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_4

MEM_2OTHER

MEM_A_DQS_5

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_6

MEM_A_DATA_6

MEM_DQS2OWNDATA

MEM_A_DQS_7

MEM_A_DATA_7

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_6

MEM_2OTHER

MEM_A_DQS_7

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_0

MEM_B_DATA_0

MEM_DQS2OWNDATA

MEM_B_DQS_1

MEM_B_DATA_1

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_0

MEM_2OTHER

MEM_B_DQS_1

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_2

MEM_B_DATA_2

MEM_DQS2OWNDATA

MEM_B_DQS_3

MEM_B_DATA_3

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_2

MEM_2OTHER

MEM_B_DQS_3

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_4

MEM_B_DATA_4

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_4

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_5

MEM_B_DATA_5

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_5

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_6

MEM_B_DATA_6

MEM_DQS2OWNDATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_6

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_7

MEM_B_DATA_7

MEM_DQS2OWNDATA

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS_1

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DQS_7

MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_*_DATA_*

=SAME

MEM_DATA2SELF

MEM_A_DATA_0

MEM_2OTHER

MEM_A_DATA_1

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DATA_2

MEM_2OTHER

MEM_A_DATA_3

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

NET_TYPE
PHYSICAL
SPACING

MEM_A_CLK
MEM_A_CLK
MEM_A_CTRL
MEM_A_CTRL
MEM_A_CTRL
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7

MEM_72D
MEM_72D
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D

MEM_CLK
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_A_DATA_0
MEM_A_DATA_1
MEM_A_DATA_2
MEM_A_DATA_3
MEM_A_DATA_4
MEM_A_DATA_5
MEM_A_DATA_6
MEM_A_DATA_7
MEM_A_DQS_0
MEM_A_DQS_0
MEM_A_DQS_1
MEM_A_DQS_1
MEM_A_DQS_2
MEM_A_DQS_2
MEM_A_DQS_3
MEM_A_DQS_3
MEM_A_DQS_4
MEM_A_DQS_4
MEM_A_DQS_5
MEM_A_DQS_5
MEM_A_DQS_6
MEM_A_DQS_6
MEM_A_DQS_7
MEM_A_DQS_7

MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

MEM_B_CLK
MEM_B_CLK
MEM_B_CTRL
MEM_B_CTRL
MEM_B_CTRL
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7

MEM_72D
MEM_72D
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_45S
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D
MEM_80D

MEM_CLK
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_B_DATA_0
MEM_B_DATA_1
MEM_B_DATA_2
MEM_B_DATA_3
MEM_B_DATA_4
MEM_B_DATA_5
MEM_B_DATA_6
MEM_B_DATA_7
MEM_B_DQS_0
MEM_B_DQS_0
MEM_B_DQS_1
MEM_B_DQS_1
MEM_B_DQS_2
MEM_B_DQS_2
MEM_B_DQS_3
MEM_B_DQS_3
MEM_B_DQS_4
MEM_B_DQS_4
MEM_B_DQS_5
MEM_B_DQS_5
MEM_B_DQS_6
MEM_B_DQS_6
MEM_B_DQS_7
MEM_B_DQS_7

MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

MEM_PWR
MEM_PWR
MEM_PWR
MEM_PWR

PP1V5_S3RS0
PP1V5_S3
PP0V75_S3_MEM_VREFCA_A
PP0V75_S3_MEM_VREFDQ_A

8 11 27 28 32
8 11 27 28 32
11 27 28 32
11 27 28 32
11 27 28 32
11 27 28 32
11 27 28 32

11 27 28 32
11 27 28 32
11 27 28 32
11 27
11 27
11 27
11 27
11 28
11 28
11 28
11 28
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 27
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28

MEM_2GND

Memory Bus Spacing Group Assignments


NET_SPACING_TYPE1

Memory Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

MEM_80D

SPACING_RULE_SET

8 11 29 30 32
8 11 29 30 32
11 29 30 32
11 29 30 32
11 29 30 32
11 29 30 32
11 29 30 32
11 29 30 32
11 29 30 32
11 29 30 32
11 29
11 29
11 29
11 29
11 30
11 30
11 30
11 30
11 29
11 29
11 29
11 29
11 29
11 29
11 29

11 29
11 30
11 30
11 30
11 30
11 30
11 30
11 30
11 30

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

MEM_CMD

MEM_CMD2CMD

MEM_CMD

MEM_CTRL

MEM_CMD2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

MEM_2OTHER

MEM_A_DATA_5

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

MEM_A_DATA_4

MEM_CTRL2CTRL

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DATA_6

MEM_2OTHER

MEM_A_DATA_7

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CLK

MEM_CLK

MEM_CLK2CLK

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_*

MEM_*

MEM_2OTHERMEM

6 7
6 7
27 28 31
27 28 31

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_DATA_0

MEM_2OTHER

MEM_B_DATA_1

MEM_2OTHER

MEM_B_DATA_2

MEM_2OTHER

MEM_B_DATA_3

MEM_2OTHER

MEM_B_DATA_4

MEM_2OTHER

MEM_B_DATA_5

MEM_2OTHER

MEM_B_DATA_6

MEM_2OTHER

MEM_B_DATA_7

MEM_2OTHER

MEM_CMD

MEM_2OTHER

MEM_CTRL

MEM_2OTHER

MEM_CLK

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SYNC_MASTER=J13_CONSTRAINTS

TABLE_SPACING_ASSIGNMENT_ITEM

SYNC_DATE=01/11/2012

PAGE TITLE

Memory Constraints

TABLE_SPACING_ASSIGNMENT_ITEM

DRAWING NUMBER

TABLE_SPACING_ASSIGNMENT_ITEM

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

101 OF 109

SHEET

67 OF 73

SATA Interface Constraints

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SATA_80D

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

ELECTRICAL_CONSTRAINT_SET

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_TX
SATA3_PCH_RX
SATA3_PCH_RX
SATA3_PCH_RX
SATA3_PCH_RX
SATA3_PCH_RX
SATA3_PCH_RX
SATA_ICOMP

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_SSD_R2D_MUX_IN_P
SATA_SSD_R2D_MUX_IN_N
SATA_SSD_R2D_P
SATA_SSD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_SSD_D2R_MUX_OUT_P
SATA_SSD_D2R_MUX_OUT_N
SATA_SSD_D2R_P
SATA_SSD_D2R_N
PCH_SATAICOMP

USB_TPAD_M
USB_TPAD_M
USB_SDCARD
USB_SDCARD
USB_SMC
USB_SMC

USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D

USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB

USB_HUB_UP_P
USB_HUB_UP_N
USB_BT_P
USB_BT_N
USB_BT_CONN_P
USB_BT_CONN_N
USB_BT_WAKE_P
USB_BT_WAKE_N
USB_TPAD_P
USB_TPAD_N
USB_TPAD_CONN_P
USB_TPAD_CONN_N
USB_TPAD_HUB_P
USB_TPAD_HUB_N
USB_TPAD_R_P
USB_TPAD_R_N
USB_TPAD_M_P
USB_TPAD_M_N
USB_SDCARD_P
USB_SDCARD_N
USB_SMC_P
USB_SMC_N

USB_CAMERA
USB_CAMERA

USB_80D
USB_80D

USB
USB

USB_CAMERA_P
USB_CAMERA_N

USB_EXTA
USB_EXTA

USB_80D
USB_80D
UART_45S
UART_45S
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D

USB
USB
UART
UART
USB
USB
USB
USB
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX

USB_EXTA_P
USB_EXTA_N
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N
USB2_EXTA_MUXED_F_P
USB2_EXTA_MUXED_F_N
USB3_EXTA_RX_P
USB3_EXTA_RX_N
USB3_EXTA_TX_P
USB3_EXTA_TX_N
USB3_EXTA_RX_F_P
USB3_EXTA_RX_F_N
USB3_EXTA_TX_F_P
USB3_EXTA_TX_F_N
USB3_EXTA_TX_C_P
USB3_EXTA_TX_C_N

USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D

USB
USB
USB
USB
USB
USB
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX

USB_EXTB_P
USB_EXTB_N
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
USB3_EXTB_RX_P
USB3_EXTB_RX_N
USB3_EXTB_RX_RC_P
USB3_EXTB_RX_RC_N
USB3_EXTB_RX_CONN_P
USB3_EXTB_RX_CONN_N
USB3_EXTB_TX_P
USB3_EXTB_TX_N
USB3_EXTB_TX_C_P
USB3_EXTB_TX_C_N

(USB_TPAD_HUB)
(USB_TPAD_HUB)

USB_80D
USB_80D

USB
USB

USB_EXTD_XHCI_P
USB_EXTD_XHCI_N

PCH_USB_RBIAS
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_

PCH_USB_RBIAS
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CPU_45S

CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE

PCH_USB_RBIAS
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK

WEIGHT
TABLE_SPACING_RULE_ITEM

SATA_ICOMP

=4x_DIELECTRIC

?
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SATA3_PCH_TX

SPACING_RULE_SET

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

SATA3_TX2TX

SATA3_TX2TX

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

SATA3_PCH_RX

SATA3_PCH_RX

TABLE_SPACING_RULE_ITEM

SATA3_RX2RX

SATA3_RX2RX

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

SATA3_PCH_TX

*_PCH_TX

SATA3_TX2OTHERTX

SATA3_PCH_RX

*_PCH_RX

SATA3_RX2OTHERRX

SATA3_TX2OTHERTX

TOP,BOTTOM

=5x_DIELECTRIC

SATA3_RX2OTHERRX

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

*_PCH_RX

SATA3_TX2RX

SATA3_PCH_RX

*_PCH_TX

SATA3_RX2TX

SATA3_TX2RX

TOP,BOTTOM

=7x_DIELECTRIC

SATA3_RX2TX

TOP,BOTTOM

=7x_DIELECTRIC

SATA3_2OTHERHS

SATA3_PCH_RX

*_TX

SATA3_2OTHERHS

SATA3_PCH_TX

*_RX

SATA3_2OTHERHS

SATA3_PCH_RX

*_RX

SATA3_2OTHERHS

USB_HUB1_UP
USB_HUB1_UP
USB_BT
USB_BT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

*_TX

TABLE_SPACING_RULE_ITEM

SATA3_2OTHERHS

TOP,BOTTOM

=6x_DIELECTRIC

SATA3_2OTHER

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

SATA3_2OTHER

LINE-TO-LINE SPACING

WEIGHT

=2.5x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

USB_TPAD
USB_TPAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SATA3_PCH_RX

LAYER

SATA3_TX2TX

TABLE_SPACING_ASSIGNMENT_ITEM

SATA3_PCH_TX

SATA3_2OTHER

SATA3_RX2RX

=2.5x_DIELECTRIC

SATA3_TX2OTHERTX

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

USB_TPAD_HUB
USB_TPAD_HUB

TABLE_SPACING_RULE_ITEM

SATA3_RX2OTHERRX

=4x_DIELECTRIC

SATA3_TX2RX

=6x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SATA3_RX2TX

=6x_DIELECTRIC

?
TABLE_SPACING_RULE_ITEM

SATA3_2OTHERHS

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

SATA3_2OTHER

=3x_DIELECTRIC

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

UART Interface Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

UART_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

UART

USB 2.0 Interface Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

USB3_EXTA_RX
USB3_EXTA_RX
USB3_EXTA_TX
USB3_EXTA_TX

TABLE_PHYSICAL_RULE_ITEM

PCH_USB_RBIAS

=STANDARD

8 MIL

8 MIL

=STANDARD

=STANDARD

=STANDARD

USB_80D

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

=2x_DIELECTRIC

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

USB

TABLE_SPACING_RULE_ITEM

USB

TOP,BOTTOM

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB 3.0 Interface Constraints


TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

USB3_PCH_TX

USB3_PCH_TX

USB3_TX2TX

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=5x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_PCH_RX

USB3_RX2RX

TOP,BOTTOM

TABLE_SPACING_RULE_ITEM

USB3_RX2RX

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_PCH_TX

*_PCH_TX

USB3_TX2OTHERTX

USB3_PCH_RX

*_PCH_RX

USB3_RX2OTHERRX

TABLE_SPACING_RULE_ITEM

USB3_TX2OTHERTX

TOP,BOTTOM

=5x_DIELECTRIC

USB3_RX2OTHERRX

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_PCH_TX

*_PCH_RX

USB3_TX2RX

USB3_PCH_RX

*_PCH_TX

USB3_RX2TX

USB3_TX2RX

TOP,BOTTOM

=7x_DIELECTRIC

USB3_RX2TX

TOP,BOTTOM

=7x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

*_TX

USB3_2OTHERHS

USB3_PCH_RX

*_TX

USB3_2OTHERHS

USB3_EXTB_RX
USB3_EXTB_RX

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_PCH_TX

USB_EXTB
USB_EXTB

TABLE_SPACING_RULE_ITEM

USB3_TX2TX

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_PCH_RX

TABLE_SPACING_RULE_ITEM

USB3_2OTHERHS

TOP,BOTTOM

=6x_DIELECTRIC

USB3_2OTHER

TOP,BOTTOM

=5x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

USB3_EXTB_TX
USB3_EXTB_TX

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_PCH_TX

*_RX

USB3_2OTHERHS

USB3_PCH_RX

*_RX

USB3_2OTHERHS

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_2OTHER

USB3_PCH_RX

USB3_2OTHER

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=2.5x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_PCH_TX

USB3_TX2TX

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

USB3_RX2RX

=2.5x_DIELECTRIC

USB3_TX2OTHERTX

=4x_DIELECTRIC

USB3_RX2OTHERRX

=4x_DIELECTRIC

USB3_TX2RX

=6x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

USB3_RX2TX

=6x_DIELECTRIC

?
TABLE_SPACING_RULE_ITEM

USB3_2OTHERHS

=4x_DIELECTRIC

?
TABLE_SPACING_RULE_ITEM

16 38
16 38
38
38
6 38
6 38
16 38

SATA SSD

16 38
38
38
6 38
6 38
16

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SATA3_PCH_TX

SATA_MUX_SSD_D2R
SATA_MUX_SSD_D2R
PCH_SATA_ICOMP

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

SATA3_PCH_TX

SATA_MUX_SSD_R2D
SATA_MUX_SSD_R2D
SATA_PCH_MUX_D2R
SATA_PCH_MUX_D2R

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SATA3_PCH_TX

NET_TYPE
PHYSICAL
SPACING
SATA_80D
SATA_80D
SATA_80D
SATA_80D
SATA_80D
SATA_80D
SATA_80D
SATA_80D
SATA_80D
SATA_80D
SATA_80D
SATA_80D

SATA_PCH_MUX_R2D
SATA_PCH_MUX_R2D

TABLE_SPACING_RULE_HEAD

LAYER

PCH Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

SPACING_RULE_SET

USB3_2OTHER

=3x_DIELECTRIC

SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

18 24
18 24
24 37
24 37
6 37
6 37
37
37
49

USB Hub nets

49
6
6
24
24
24 49
24 49
49
49
24 33
24 33

24 41
24 41

6 18 40
6 18 40

USB Camera nets

18 39
18 39
39 41 42
39 41 42
39
39
39
39
18 39
18 39

USB EXTA nets (Right USB port)

18 39
18 39
39
39
39
39
39
39

6 24 40

6 24 40
18 24
18 24
18 24
18 24
18 40
18 40
6 40

USB EXTB nets (Left USB port)

6 40

18 40
18 40
6 40
6 40

18 24
18 24

Unused USB nets

18
16
16
16
16
16
16
16

SYNC_MASTER=J13_CONSTRAINTS

SYNC_DATE=01/11/2012

PAGE TITLE

PCH Constraints 1
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

102 OF 109

SHEET

68 OF 73

LPC Bus Constraints

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

ELECTRICAL_CONSTRAINT_SET

TABLE_PHYSICAL_RULE_ITEM

LPC_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

CLK_LPC_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

LINE-TO-LINE SPACING

SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_0_CLK
SMBUS_PCH_0_DATA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA

SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S

SMB
SMB
SMB
SMB
SMB
SMB

SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA

HDA_BIT_CLK

HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S

HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA

HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
HDA_SDOUT_R

TABLE_SPACING_RULE_ITEM

LPC

=3x_DIELECTRIC

LPC_CLK33M

TABLE_SPACING_RULE_ITEM

CLK_LPC

=4x_DIELECTRIC

?
LPC_CLK33M

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SMBus Interface Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

SMB_45S_R_50S

TOP,BOTTOM

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

SMB_45S_R_50S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

=STANDARD

ELECTRICAL_CONSTRAINT_SET

LPC_AD<3..0>
LPC_FRAME_L
LPCPLUS_RESET_L
LPC_CLK33M_SMC
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS
LPC_CLK33M_LPCPLUS_R
PCH_CLK33M_PCIIN
PCH_CLK33M_PCIOUT

LPC_CLK33M

WEIGHT

NET_TYPE
PHYSICAL
SPACING
LPC
LPC
LPC
CLK_LPC
CLK_LPC
CLK_LPC
CLK_LPC
CLK_LPC
CLK_LPC

TABLE_SPACING_RULE_HEAD

LAYER

6 16 41 43
6 16 41 43

DP_TBT_ML
DP_TBT_ML

6 25 43
25 41
18 25
6 25 43

DP_TBT_AUXCH
DP_TBT_AUXCH

18 25
16 25

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

SMB

=2x_DIELECTRIC

?
HDA_SYNC

HD Audio Interface Constraints

HDA_RST_L

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

HDA_45S

=45_OHM_SE

SPACING_RULE_SET

LAYER

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

HDA_SDIN0
HDA_SDOUT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

HDA

=2x_DIELECTRIC

PM_SUS_CLK

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SPI_CLK

SIO Signal Constraints

SPI_MOSI

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

CLK_SLOW_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

SPI_MISO
SPI_CS0

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

CLK_SLOW

=4x_DIELECTRIC

SPI Interface Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SPI_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

PCIE_AP_R2D
PCIE_AP_R2D

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

SPI

XDP Constraints

PCIE_AP_D2R
PCIE_AP_D2R
PCIE_CLK100M_AP
PCIE_CLK100M_AP

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

PCH_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

PCIE_TBT_R2D
PCIE_TBT_R2D

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

PCH_ITP

=2:1_SPACING

?
PCIE_TBT_D2R
PCIE_TBT_D2R

DisplayPort

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

DP_80D

SPACING_RULE_SET

LAYER

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

=3x_DIELECTRIC

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

DP_2DP

TOP,BOTTOM

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

DP_2OTHERHS

=4x_DIELECTRIC

DP_2OTHER

=3x_DIELECTRIC

DP_2OTHERHS

TOP,BOTTOM

=6x_DIELECTRIC

DP_2OTHER

TOP,BOTTOM

=4x_DIELECTRIC

=3x_DIELECTRIC

XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D

PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RX
PCIE_PCH_RX
CLK_PCIE
CLK_PCIE

PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N

PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D

PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
CLK_PCIE
CLK_PCIE

PCIE_TBT_R2D_P<3..0>
PCIE_TBT_R2D_N<3..0>
PCIE_TBT_R2D_C_P<3..0>
PCIE_TBT_R2D_C_N<3..0>
PCIE_TBT_D2R_P<3..0>
PCIE_TBT_D2R_N<3..0>
PCIE_TBT_D2R_C_P<3..0>
PCIE_TBT_D2R_C_N<3..0>
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N

CLK_PCIE_80D
CLK_PCIE_80D

CLK_PCIE
CLK_PCIE

PEG_CLK100M_P
PEG_CLK100M_N

PCH_45S
PCH_45S
PCH_45S
PCH_45S

PCH_ITP
PCH_ITP
PCH_ITP
PCH_ITP

XDP_PCH_TDI
XDP_PCH_TDO
XDP_PCH_TMS
XDP_PCH_TCK

DP_TX
DP_TX
DP_TX
DP_TX
DP_AUX
DP_AUX
DP_AUX
DP_AUX

DP_TBTSNK0_ML_P<3..0>
DP_TBTSNK0_ML_N<3..0>
DP_TBTSNK0_ML_C_P<3..0>
DP_TBTSNK0_ML_C_N<3..0>
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N

DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D

DP_TX
DP_TX
DP_TX
DP_TX
DP_AUX
DP_AUX
DP_AUX
DP_AUX

DP_TBTSNK1_ML_P<3..0>
DP_TBTSNK1_ML_N<3..0>
DP_TBTSNK1_ML_C_P<3..0>
DP_TBTSNK1_ML_C_N<3..0>
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N

34
34
8 34
8 34
34
34
8 34

8 34

16 44

DP_TBT_ML
DP_TBT_ML

16 44
16 44
16 44
16 44

DP_TBT_AUXCH
DP_TBT_AUXCH

16 44

34
34
8 34
8 34
34
34
8 34
8 34

6 16 40
16
6 16 40

Clock Net Properties

16
16
6 16 40

ELECTRICAL_CONSTRAINT_SET

NET_TYPE
PHYSICAL
SPACING

6 16 40
6 16 40

SYSCLK_CLK32K_RTC

CLK_SLOW_45S

CLK_SLOW

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB

CLK_25M_45S
CLK_25M_45S

CLK_25M
CLK_25M

SYSCLK_CLK25M_SB
SYSCLK_CLK25M_SB_R

SYSCLK_CLK25M_TBT

CLK_25M_45S
CLK_25M_45S

CLK_25M
CLK_25M

SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBT_R

SYSCLK_CLK25M_XTAL

CLK_25M_45S
CLK_25M_45S
CLK_25M_45S

CLK_25M
CLK_25M
CLK_25M

SYSCLK_CLK25M_X1
SYSCLK_CLK25M_X2
SYSCLK_CLK25M_X2_R

16 25

16 25

17 42

16 25
16

41 42
16 43
43

25 34
34

16 43
43
16 43
16 43

25
25

25

43
41 42
41 42
41 42
41 42
42 43 50
42 43 50
42 43 50
42 43 50

6 37
6 37
16 37
16 37
6 16 37
6 16 37
6 16 37
6 16 37

34
34
8 34
8 34
8 34
8 34

34
34
16 34
16 34

8 16
8 16

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

DP_AUX

PM_CLK32K_SUSCLK_R
SMC_CLK32K
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L
SPI_SMC_CLK
SPI_SMC_MOSI
SPI_SMC_MISO
SPI_SMC_CS_L
SPI_MLB_CLK
SPI_MLB_MOSI
SPI_MLB_MISO
SPI_MLB_CS_L

DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D

TABLE_SPACING_RULE_HEAD

WEIGHT
TABLE_SPACING_RULE_ITEM

DP_2DP

PCIE_CLK100M_TBT
PCIE_CLK100M_TBT

CLK_SLOW
CLK_SLOW
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI

CLK_SLOW_45S
CLK_SLOW_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S

NET_TYPE
PHYSICAL
SPACING

18 25

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

Chipset Net Properties

LPC_45S
LPC_45S
LPC_45S
CLK_LPC_45S
CLK_LPC_45S
CLK_LPC_45S
CLK_LPC_45S
CLK_LPC_45S
CLK_LPC_45S

LPC_AD
LPC_FRAME_L

TABLE_PHYSICAL_RULE_ITEM

SPACING_RULE_SET

PCH Net Properties

TABLE_SPACING_RULE_ITEM

DP_AUX

TOP,BOTTOM

=4x_DIELECTRIC

16 23
16 23
16 23
16 23

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

DP_TX

DP_TX

DP_2DP

DP_TX

*_TX

DP_2OTHERHS

DP_TX

*_RX

DP_2OTHERHS

DP_TX

DP_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

System Clock Signal Constraints

SYNC_MASTER=J13_CONSTRAINTS

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

LAYER

CLK_SLOW_45S
CLK_25M_45S

SYNC_DATE=01/11/2012

PAGE TITLE

PCH Constraints 2

TABLE_PHYSICAL_RULE_HEAD

ALLOW ROUTE
ON LAYER?

PHYSICAL_RULE_SET

DRAWING NUMBER

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

TABLE_PHYSICAL_RULE_ITEM

051-9277

NOTICE OF PROPRIETARY PROPERTY:

TABLE_SPACING_RULE_HEAD

LAYER

LINE-TO-LINE SPACING

WEIGHT

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

TABLE_SPACING_RULE_ITEM

CLK_SLOW

=2x_DIELECTRIC

CLK_25M

=5x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

NOTE: 25MHz system clocks very sensitive to noise.

2.8.0

SPACING_RULE_SET

SIZE

REVISION
BRANCH
PAGE

103 OF 109

SHEET

69 OF 73

DisplayPort Signal Constraints

ELECTRICAL_CONSTRAINT_SET

Thunderbolt SPI Signal Constraints


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TBTDP_TX
TBTDP_TX
TBTDP_TX
TBTDP_TX

TBT_A_R2D_C_P<1..0>
TBT_A_R2D_C_N<1..0>
TBT_A_R2D_P<1..0>
TBT_A_R2D_N<1..0>

DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D

DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX

DP_TBTPA_ML_C_P<1>
DP_TBTPA_ML_C_N<1>
DP_TBTPA_ML_C_P<3>
DP_TBTPA_ML_C_N<3>
DP_TBTPA_ML_P<3..1:2>
DP_TBTPA_ML_N<3..1:2>
DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D

TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX

TBT_A_D2R_C_P<1..0>
TBT_A_D2R_C_N<1..0>
TBT_A_D2R_P<1>
TBT_A_D2R_N<1>
TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
TBTDP_80D
TBTDP_80D

DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
TBTDP_RX
TBTDP_RX

DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_N
DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N

TBT_B_R2D
TBT_B_R2D

TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D

TBTDP_TX
TBTDP_TX
TBTDP_TX
TBTDP_TX

TBT_B_R2D_C_P<1..0>
TBT_B_R2D_C_N<1..0>
TBT_B_R2D_P<1..0>
TBT_B_R2D_N<1..0>

DP_TBTPB_ML
DP_TBTPB_ML

DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D

DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX

DP_TBTPB_ML_C_P<3..1:2>
DP_TBTPB_ML_C_N<3..1:2>
DP_TBTPB_ML_P<3..1:2>
DP_TBTPB_ML_N<3..1:2>
DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>

TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D

TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX

TBT_B_D2R_C_P<1..0>
TBT_B_D2R_C_N<1..0>
TBT_B_D2R_P<1..0>
TBT_B_D2R_N<1..0>

DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
TBTDP_80D
TBTDP_80D

DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
TBTDP_RX
TBTDP_RX

DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_P
DP_TBTPB_AUXCH_N
DP_B_AUXCH_DDC_P
DP_B_AUXCH_DDC_N
TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N

TABLE_PHYSICAL_RULE_ITEM

TBT_SPI_45S

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD
DP_TBTPA_ML1
DP_TBTPA_ML1
DP_TBTPA_ML3
DP_TBTPA_ML3

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TBT_SPI

Thunderbolt/DP Connector Signal Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TBTDP_80D

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_TX

TBTDP_TX

TBTDP_TX2TX

TOP,BOTTOM

=6x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_RX

TBTDP_RX

TBTDP_RX2RX

TABLE_SPACING_RULE_ITEM

TBTDP_RX2RX

TOP,BOTTOM

=6x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_TX

TBTDP_RX

TBTDP_TX2RX

TABLE_SPACING_RULE_ITEM

TBTDP_TX2RX

TOP,BOTTOM

=10x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_RX

TBTDP_TX

TBTDP_TX2RX

TBTDP_TX

*_TX

TBTDP_2OTHERHS

TBT_A_D2R1
TBT_A_D2R1
TBT_A_D2R0
TBT_A_D2R0

TABLE_SPACING_RULE_ITEM

TBTDP_TX2TX

TBT_A_AUXCH
TBT_A_AUXCH

TABLE_SPACING_RULE_ITEM

TBTDP_2OTHERHS

TOP,BOTTOM

=10x_DIELECTRIC

TBTDP_2OTHER

TOP,BOTTOM

=6x_DIELECTRIC

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_RX

*_TX

TBTDP_2OTHERHS

TBTDP_TX

*_RX

TBTDP_2OTHERHS

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_RX

*_RX

TBTDP_2OTHERHS

TBTDP_TX

TBTDP_2OTHER

TABLE_SPACING_RULE_ITEM

TBTDP_TX2TX

=4x_DIELECTRIC

TBTDP_RX2RX

=4x_DIELECTRIC

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TBTDP_RX

TBTDP_2OTHER

TABLE_SPACING_RULE_ITEM

TBTDP_TX2RX

=6x_DIELECTRIC

NET_TYPE
PHYSICAL
SPACING
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D

TBT_A_R2D
TBT_A_R2D

TABLE_PHYSICAL_RULE_HEAD

ALLOW ROUTE
ON LAYER?

LAYER

Thunderbolt/DP Net Properties

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

PHYSICAL_RULE_SET

?
TABLE_SPACING_RULE_ITEM

TBTDP_2OTHERHS

=6x_DIELECTRIC

TBTDP_2OTHER

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

TBT_B_D2R
TBT_B_D2R
TBT_B_AUXCH
TBT_B_AUXCH

34 64
34 64
64
64

34 64
34 64
34 64

34 64
64
64
64
64

64
64
34 64
34 64
34 64
34 64

34 64
34 64
64
64
64
64
64
64

8 34
8 34

8 34

8 34

Only used on dual-port hosts.


8 34
8 34

8 34
8 34

Thunderbolt IC Net Properties


ELECTRICAL_CONSTRAINT_SET

B
TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L

NET_TYPE
PHYSICAL
SPACING
DP_80D
DP_80D
DP_80D
DP_80D

DP_TX
DP_TX
DP_AUX
DP_AUX

DP_TBTSRC_ML_C_P<3..0>
DP_TBTSRC_ML_C_N<3..0>
DP_TBTSRC_AUXCH_C_P
DP_TBTSRC_AUXCH_C_N

TBT_SPI_45S
TBT_SPI_45S
TBT_SPI_45S
TBT_SPI_45S

TBT_SPI
TBT_SPI
TBT_SPI
TBT_SPI

TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L

Only used on hosts supporting Thunderbolt video-in

34
34
34
34

SYNC_MASTER=J13_CONSTRAINTS

SYNC_DATE=01/11/2012

PAGE TITLE

Thunderbolt Constraints
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

105 OF 109

SHEET

70 OF 73

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

1:1_DIFFPAIR

=STANDARD

=STANDARD

=STANDARD

=STANDARD

0.1 MM

SMC SMBus Net Properties

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

0.1 MM

ELECTRICAL_CONSTRAINT_SET
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA

NET_TYPE
PHYSICAL
SPACING
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S

SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB

SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA

41 44
41 44
41 44
41 44
41 44
41 44
41 44

41 44
41 44
41 44

SMBus Charger Net Properties


ELECTRICAL_CONSTRAINT_SET
SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_DIFFPAIR
SENSE_DIFFPAIR

NET_TYPE
PHYSICAL
SPACING
1:1_DIFFPAIR
1:1_DIFFPAIR
1:1_DIFFPAIR
1:1_DIFFPAIR

CHGR_CSI_P
CHGR_CSI_N
CHGR_CSI_R_P
CHGR_CSI_R_N

1:1_DIFFPAIR
1:1_DIFFPAIR
1:1_DIFFPAIR
1:1_DIFFPAIR

CHGR_CSO_P
CHGR_CSO_N
CHGR_CSO_R_P
CHGR_CSO_R_N

53
53
53
53

53
53
53
53

SYNC_MASTER=J13_CONSTRAINTS

SYNC_DATE=01/11/2012

PAGE TITLE

SMC Constraints
DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

106 OF 109

SHEET

71 OF 73

J11/J13 Specific Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SENSE_1TO1_45S

=1:1_DIFFPAIR

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR

SENSE_1TO1_P2MM

=1:1_DIFFPAIR

0.200 MM

0.100 MM

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

THERM_1TO1_45S

=1:1_DIFFPAIR

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR

ELECTRICAL_CONSTRAINT_SET

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SPKR_DIFFPAIR

=1:1_DIFFPAIR

0.300 MM

0.100 MM

=1:1_DIFFPAIR

=1:1_DIFFPAIR

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

TABLE_SPACING_RULE_ITEM

=2:1_SPACING

THERM

=2:1_SPACING

=2:1_SPACING

CPU_COMP

GND

GND_P2MM

CPU_VCCSENSE

GND

GND_P2MM

?
NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

TABLE_SPACING_RULE_HEAD

LAYER

LINE-TO-LINE SPACING

=STANDARD

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

GND

WEIGHT

CLK_PCIE

TABLE_SPACING_ASSIGNMENT_ITEM

GND

PCIE*

GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

GND

SATA*

TABLE_SPACING_RULE_HEAD

LAYER

LINE-TO-LINE SPACING

WEIGHT

GND

USB*

GND_P2MM

GND

LVDS*

GND_P2MM

0.20 MM

1000

0.20 MM

TBT_THERMD_P
TBT_THERMD_N
TBT_MLBBOT_THMSNS_P
TBT_MLBBOT_THMSNS_N
TBTTHMSNS_D2_R_P
TBTTHMSNS_D2_R_N

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE

CPU_THERMD_P
CPU_THERMD_N

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE

CPUTHMSNS_D2_P
CPUTHMSNS_D2_N

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_P2MM SENSE
SENSE_1TO1_P2MM SENSE

CPUVCCIOS0_CS_N
CPUVCCIOS0_CS_P

SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE
SENSE
SENSE

CPUIMVP_ISNS1_P
CPUIMVP_ISNS1_N
CPUIMVP_ISUM_R_P
CPUIMVP_ISUM_R_N

SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE
SENSE
SENSE

CPUIMVP_ISNS1G_P
CPUIMVP_ISNS1G_N
CPUIMVP_ISUMG_R_P
CPUIMVP_ISUMG_R_N

SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE
SENSE
SENSE

VCCSAS0_CS_P
VCCSAS0_CS_N
VCCSAISNS_R_P
VCCSAISNS_R_N

SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE
SENSE
SENSE

ISNS_3V3S0_P
ISNS_3V3S0_N
ISNS_3V3S0_R_P
ISNS_3V3S0_R_N

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

PWR_P2MM

THERM
THERM
THERM
THERM
THERM
THERM

SENSE_DIFFPAIR
SENSE_DIFFPAIR

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

GND_P2MM

THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S

1000

46 47

47
47
47

47
47
47

9 47
9 47

47
47

45 59
45 59

GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

SENSE_DIFFPAIR
SENSE_DIFFPAIR

46 47

GND_P2MM

TABLE_SPACING_RULE_ITEM

GND

INLET_THMSNS_D1_P
INLET_THMSNS_D1_N

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET

THERM
THERM

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

THERM_1TO1_45S
THERM_1TO1_45S

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AUDIO

SENSE_DIFFPAIR
SENSE_DIFFPAIR

TABLE_SPACING_ASSIGNMENT_HEAD

WEIGHT

SENSE

=1:1_DIFFPAIR

NET_TYPE
PHYSICAL
SPACING

SB_POWER

CLK_PCIE

PWR_P2MM

SB_POWER

SATA*

PWR_P2MM

SB_POWER

SATA*

PWR_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

SENSE_DIFFPAIR
SENSE_DIFFPAIR

TABLE_SPACING_ASSIGNMENT_ITEM

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_P2MM SENSE
SENSE_1TO1_P2MM SENSE

CPUIMVP_ISUMG_P
CPUIMVP_ISUMG_N

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_P2MM SENSE
SENSE_1TO1_P2MM SENSE

CPUIMVP_ISUM_P
CPUIMVP_ISUM_N

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE

ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE

ISNS_HS_OTHER_N
ISNS_HS_OTHER_P

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE

ISNS_1V5_S3_N
ISNS_1V5_S3_P

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE

ISNS_AIRPORT_N
ISNS_AIRPORT_P

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE

ISNS_SSD_N
ISNS_SSD_P

SENSE_DIFFPAIR
SENSE_DIFFPAIR

SENSE_1TO1_45S
SENSE_1TO1_45S

SENSE
SENSE

ISNS_LCDBKLT_N
ISNS_LCDBKLT_P

AUD_DIFF
AUD_DIFF

1:1_DIFFPAIR
1:1_DIFFPAIR
1:1_DIFFPAIR
1:1_DIFFPAIR
SPKR_DIFFPAIR
SPKR_DIFFPAIR

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

SPKRAMP_INR_P
SPKRAMP_INR_N
MAX98300_R_P
MAX98300_R_N
SPKRAMP_ROUT_P
SPKRAMP_ROUT_N

SB_POWER
SB_POWER

PP3V3_S5
PP3V3_S0

GND

GND

SPKR_OUT
SPKR_OUT

45 57 58
45 58
45
45

45 58
45 58
45
45

45 54
45 54
45
45

45 61
45 61
45
45

57 58
57 58

57 58
57 58

8 46
8 46

46
46

46 56
46 56

37 46
37 46

38 46
38 46

8 46
8 46

6 40 51
6 40 51
51
51
6 51 52
6 51 52

6 7
6 7

SYNC_MASTER=J13_CONSTRAINTS

SYNC_DATE=01/11/2012

PAGE TITLE

Project Specific Constraints


DRAWING NUMBER

Apple Inc.

051-9277

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2.8.0

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION
BRANCH
PAGE

108 OF 109

SHEET

72 OF 73

J11/J13 Board-Specific Spacing & Physical Constraints


TABLE_BOARD_INFO

BOARD LAYERS

BOARD AREAS

BOARD UNITS
(MIL or MM)

ALLEGRO
VERSION

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA

MM

16.2
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

DEFAULT

TOP,BOTTOM

=50_OHM_SE

=50_OHM_SE

DEFAULT

ISL2,ISL11

=45_OHM_SE

=45_OHM_SE

DEFAULT

ISL3,ISL10

=45_OHM_SE

=45_OHM_SE

DEFAULT

ISL4,ISL9

=45_OHM_SE

=45_OHM_SE

DEFAULT

100 MM

100 MM

10 MM

0 MM

0 MM

STANDARD

=DEFAULT

=DEFAULT

=DEFAULT

=DEFAULT

=DEFAULT

=DEFAULT

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Single-ended Physical Constraints

Spacing Constraints
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

0.100 MM

TABLE_PHYSICAL_RULE_ITEM

27P4_OHM_SE

TOP,BOTTOM

0.310 MM

0.310 MM

TABLE_SPACING_RULE_ITEM

1:1_SPACING

TABLE_PHYSICAL_RULE_ITEM

27P4_OHM_SE

ISL2,ISL11

0.182 MM

0.182 MM

27P4_OHM_SE

ISL3,ISL10

0.182 MM

0.182 MM

27P4_OHM_SE

ISL4,ISL9

0.182 MM

0.182 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LINE-TO-LINE SPACING

WEIGHT

1x_DIELECTRIC

TOP,BOTTOM

LAYER

0.071 MM

1x_DIELECTRIC

ISL3,ISL10

0.053 MM

1x_DIELECTRIC

ISL4,ISL9

0.050 MM

1x_DIELECTRIC

0.090 MM

LINE-TO-LINE SPACING

WEIGHT

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

27P4_OHM_SE

100 MM

100 MM

=STANDARD

=STANDARD

=STANDARD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

35_OHM_SE

TOP,BOTTOM

0.195 MM

0.195 MM

35_OHM_SE

ISL2,ISL11

0.125 MM

0.125 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

TABLE_PHYSICAL_RULE_ITEM

35_OHM_SE

ISL3,ISL10

0.125 MM

0.125 MM

35_OHM_SE

ISL4,ISL9

0.125 MM

0.125 MM

DEFAULT

0.1 MM

STANDARD

=DEFAULT

TABLE_PHYSICAL_RULE_ITEM

100 MM

100 MM

=STANDARD

=STANDARD

=STANDARD

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

BGA

BGA_P1MM

MEM_CLK

BGA

BGA_P2MM

CLK_PCIE

BGA

BGA_P2MM

CLK_SLOW

BGA

BGA_P2MM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

35_OHM_SE

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

BGA_P1MM

=DEFAULT

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

BGA_P2MM

=DEFAULT

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

TOP,BOTTOM

0.170 MM

0.170 MM

40_OHM_SE

ISL2,ISL11

0.096 MM

0.096 MM

40_OHM_SE

ISL3,ISL10

0.096 MM

0.096 MM

40_OHM_SE

ISL4,ISL9

0.099 MM

0.099 MM

40_OHM_SE

100 MM

100 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

45_OHM_SE

TOP,BOTTOM

0.135 MM

0.135 MM

45_OHM_SE

ISL2,ISL11

0.075 MM

0.075 MM

45_OHM_SE

ISL3,ISL10

0.075 MM

0.075 MM

45_OHM_SE

ISL4,ISL9

0.080 MM

0.080 MM

45_OHM_SE

100 MM

100 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

50_OHM_SE

TOP,BOTTOM

0.110 MM

0.110 MM

50_OHM_SE

100 MM

100 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

55_OHM_SE

TOP,BOTTOM

0.090 MM

0.090 MM

55_OHM_SE

100 MM

100 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

=STANDARD

=STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

Differential Pair Physical Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

72_OHM_DIFF

TOP,BOTTOM

0.165 MM

0.165 MM

0.130 MM

0.130 MM

72_OHM_DIFF

ISL2,ISL11

0.109 MM

0.109 MM

0.150 MM

0.150 MM

72_OHM_DIFF

ISL3,ISL10

0.109 MM

0.109 MM

0.150 MM

0.150 MM

72_OHM_DIFF

ISL4,ISL9

0.114 MM

0.114 MM

0.150 MM

0.150 MM

72_OHM_DIFF

100 MM

100 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

80_OHM_DIFF

TOP,BOTTOM

0.132 MM

0.132 MM

0.130 MM

0.130 MM

80_OHM_DIFF

ISL2,ISL11

0.081 MM

0.081 MM

0.115 MM

0.115 MM

80_OHM_DIFF

ISL3,ISL10

0.081 MM

0.081 MM

0.115 MM

0.115 MM

80_OHM_DIFF

ISL4,ISL9

0.088 MM

0.088 MM

0.110 MM

0.110 MM

80_OHM_DIFF

100 MM

100 MM

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SYNC_MASTER=J13_CONSTRAINTS

SYNC_DATE=01/11/2012

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

PAGE TITLE

PCB Rule Definitions


DRAWING NUMBER

Apple Inc.

051-9277

NOTICE OF PROPRIETARY PROPERTY:

2.8.0

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION
BRANCH
PAGE

109 OF 109

SHEET

73 OF 73