module whisky(isTransfer, reset,clock, light,delay);

input isTransfer, reset, clock;

output reg [5:0] light; //6 led for 6 stages
reg [2:0] state;
output reg [9:0] delay; //use for counting delay time in each stage present on 7
-segment-leds
parameter [2:0] Fermenting = 3'b000, ReadyToTransfer = 3'b001, PrepareToTransfer
= 3'b010, newTank = 3'b011,Flush = 3'b100, Complete= 3'b101;
reg [9:0] count; //count for clock
parameter [9:0] delay80 = 8'b1010000, delay10 = 8'b00001010, delay50 = 8'b001100
10, delay150 = 9'b10010110;
always @(posedge reset, posedge clock)
if (reset == 1) //reset is trigged
begin //reset to Fermenting stage
delay = 0;
state = Fermenting;
count = 0;
light = 6'b000001;
end
else
case(state)
Fermenting: if (count < delay80) //wait for 80% of proce
ss is complete
begin
count <= count +
1;
state <= Ferment
ing;
delay <= delay +
1;
end
else
begin
state <= ReadyTo
Transfer;
count = 0;
light = 6'b00001
0;
end
ReadyToTransfer:
if(count < delay10) //wait to 90
%
begin
count <= count +
1;
state <= ReadyTo
Transfer;
light = 6'b00001
0;
delay <= delay +
1;
end
else
begin
state <= Prepare
ToTransfer;
count = 0;
light = 6'b00010

0;
end
PrepareToTransfer:
if (count <delay10) //complete 1
00%
begin
count <= count +
1;
state <= Prepare
ToTransfer;
light = 6'b00010
0;
delay <= delay +
1;
end
else
begin
state <= Complet
e;
count = 0;
light = 6'b00100
0;
end
Complete:
if (isTransfer) //allow to trans
fer
begin
state <= newTank
;
light = 6'b01000
0;
//delay = 0;
end
else //not transfer then flush
begin
state <= Flush;
light = 6'b10000
0;
//delay = 0;
end
newTank:
if (count < delay50) //time for
transfer to new tank
begin
count <= count +
1;
state <= newTank
;
light = 6'b01000
0;
delay <= delay +
1;
end
else
begin
count = 0;
state <= Ferment

ing;
light = 6'b00000
1;
delay = 0;
end
Flush:
if (count < delay150) //time for
flush
if (isTransfer)
begin
count =
0;
state <=
Fermenting;
light =
6'b000001;
//delay
= 0;
end
else
begin
delay <= delay +
1;
count <= count +
1;
state <= Flush;
light = 6'b10000
0;
end
else
begin
count = 0;
state <= Ferment
ing;
light = 6'b00000
1;
delay = 0;
end
default
begin
state = Fermenting;
end
endcase
endmodule
module whisky_run(isTransfer, reset,CLOCK_50, light,HEX0, HEX1,HEX2);
input wire isTransfer, reset, CLOCK_50;
output wire [5:0] light;
output wire [0:6] HEX0,HEX1,HEX2;
wire [9:0] delay;
wire clkout;
clkdiv clkdiv(CLOCK_50, reset, clkout);
whisky whisky(isTransfer, reset,clkout, light,delay);
leg7seg led7seg(delay, HEX0,HEX1,HEX2);
endmodule
module leg7seg ( count, HEX0, HEX1,HEX2);
input [9:0]
count;

output reg
[0:6] HEX0,HEX1,HEX2;
reg
[3:0] a2, a1, a0;
always @(*)
begin
a0 <= count %10;
a1 <= (count / 10) %10;
a2 <= count / 100;
end
always @(a0) begin //control HEX0
case (a0)
4'b0000:
HEX0 = 7'b0000001;
4'b0001:
HEX0 = 7'b1001111;
4'b0010:
HEX0 = 7'b0010010;
4'b0011:
HEX0 = 7'b0000110;
4'b0100:
HEX0 = 7'b1001100;
4'b0101:
4'b0110:
4'b0111:
4'b1000:
4'b1001:
default:

HEX0
HEX0
HEX0
HEX0
HEX0
HEX0

=
=
=
=
=
=

7'b0100100;
7'b0100000;
7'b0001111;
7'b0000000;
7'b0000100;
7'b1111111;

//
//
//
//
//

0
1
2
3
4

//
//
//
//
//

5
6
7
8
9

//
//
//
//
//

0
1
2
3
4

//
//
//
//
//

5
6
7
8
9

//
//
//
//
//

0
1
2
3
4

//
//
//
//
//

5
6
7
8
9

endcase
end
always @(a1) begin //control led HEX 1
case (a1)
4'b0000:
HEX1 = 7'b0000001;
4'b0001:
HEX1 = 7'b1001111;
4'b0010:
HEX1 = 7'b0010010;
4'b0011:
HEX1 = 7'b0000110;
4'b0100:
HEX1 = 7'b1001100;
4'b0101:
4'b0110:
4'b0111:
4'b1000:
4'b1001:
default:

HEX1
HEX1
HEX1
HEX1
HEX1
HEX1

=
=
=
=
=
=

7'b0100100;
7'b0100000;
7'b0001111;
7'b0000000;
7'b0000100;
7'b1111111;

endcase
end
always @(a2) begin //control HEX2
case (a2)
4'b0000:
HEX2 = 7'b0000001;
4'b0001:
HEX2 = 7'b1001111;
4'b0010:
HEX2 = 7'b0010010;
4'b0011:
HEX2 = 7'b0000110;
4'b0100:
HEX2 = 7'b1001100;
4'b0101:
4'b0110:
4'b0111:
4'b1000:
4'b1001:
default:
endcase

HEX2
HEX2
HEX2
HEX2
HEX2
HEX2

=
=
=
=
=
=

7'b0100100;
7'b0100000;
7'b0001111;
7'b0000000;
7'b0000100;
7'b1111111;

end
endmodule
module clkdiv ( clk , clr , clk_b );
input wire clk, clr;
output wire clk_b;
reg [31:0] div;
always @(posedge clk or posedge clr)
begin
if(clr == 1)
div <= 0;
else
div <= div + 1;
end
assign clk_b = div[21];
endmodule