ECE 453 Homework Assignment 5 Topic: Op Amp Design Active current Mirrors

Consider the following amplier:

Vdd

Vb1 Vb2 Vin+ M1 A

M4 M3 VinM2 Vb3

M11 M9

M12 M10

C M8

Vout CL

M7 M5

M6

This is a single stage amplier with dierential inputs, a single output and high gain. In other words, an op-amp. 1. Find the dierential gain and output swing of this op-amp 2. How many poles does the dierential response contain? Where are they? What is the bandwidth given by the output pole? Sketch magnitude and phase Bode plots. 3. Estimate common mode gain and frequency response. Sketch magnitude and phase plots. 4. Explain what the op-amp is doing and how it works. Answer the oowing in your description. Why are there two transistors stacked at node A (M3 and M4) rather than 1? Why is/isnt this a good idea. What does the connection at node C do? How would you size M5 and M6 and what do they do? What do M1 and M2 do? 5. Redraw the amplier with NFET inputs. Is the gain the same? Why or why not? 6. Design a bias network to set Vb1 , Vb2 , and Vb3 1