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Date:27-01-2014 Page No: Roll No:12H61A0511 _____________________________________________________________________________ AIM:To write the program to implement operation of 2x4 Decoder and observe wave forms SOFTWARE REQUIRED:Xilinx software THEORY:
DECODERS
ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,
CSE DEPT.
TITLE:
DECODERS
ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,
CSE DEPT.
TITLE:
DECODERS
ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,
CSE DEPT.
TITLE:
DECODERS
VHDL CODE FOR FA-BEHAVIORAL GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_Behavioral is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; SUM : out STD_LOGIC; Cout : out STD_LOGIC); end FA_Behavioral; architecture Behavioral of FA_Behavioral is begin process (A,B,Cin) begin if (A = '0' and B = '0' and Cin = '0') then SUM <= '0'; Cout <= '0'; elsif (A = '0' and B = '0' and Cin = '1') then SUM <= '1'; Cout <= '0'; elsif (A = '0' and B = '1' and Cin = '0') then SUM <= '1'; Cout <= '0'; elsif (A = '0' and B = '1' and Cin = '1') then SUM <= '0'; Cout <= '1'; elsif (A = '1' and B = '0' and Cin = '0') then SUM <= '1'; Cout <= '0'; elsif (A = '1' and B = '0' and Cin = '1') then SUM <= '0'; Cout <= '1'; elsif (A = '1' and B = '1' and Cin = '0') then SUM <= '0'; Cout <= '1'; else SUM <= '1'; Cout <= '1'; end if; end process; end Behavioral; OUTPUT WAVEFORM FOR FA-BEHAVIORAL GATE:
ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,
CSE DEPT.
TITLE:
DECODERS
ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,
CSE DEPT.
TITLE:
DECODERS
ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,
CSE DEPT.
TITLE:
DECODERS
ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,
CSE DEPT.
TITLE:
DECODERS
RESULTS:
Device utilization summary:
--------------------------Selected Device : 3s500efg320-4 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 1 2 5 5 out of out of out of 4656 9312 232 0% 0% 2%
Timing Summary:
--------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 6.236ns
ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,
CSE DEPT.