VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity trafic is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
G : inout STD_LOGIC_VECTOR (3 downto 0);
R : inout STD_LOGIC_VECTOR (3 downto 0);
Y : inout STD_LOGIC_VECTOR (3 downto 0));

end trafic;

architecture Behavioral of trafic is

TYPE STATE IS (S0,S1,S2,S3,S4,S5,S6,S7);
SIGNAL A : STATE;
signal count1:std_logic_vector(25 downto 0):="00000000000000000000000000";
signal count2:std_logic_vector(26 downto 0):="000000000000000000000000000";

begin
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
R <= "0000";
G <= "0000";
Y <= "0000";
ELSIF(CLK='1' AND CLK' EVENT) THEN
CASE A IS
WHEN S0 =>
R <= "0111";
G <= "1000";
Y <= "0000";
count2 <= count2+1;
if(count2(26)='1')then
count2<=(others=>'0');
A<=S1;
end if;

WHEN S1 =>
R <= "0111";
G <= "0000";
Y <= "1000";
count1 <= count1+1;

if(count1(25)='1')then
count1<=(others=>'0');
A<=S2;
end if;

WHEN S2 =>
R <= "1011";
G <= "0100";
Y <= "0000";
count2 <= count2+1;
if(count2(26)='1')then
count2<=(others=>'0');
A<=S3;
end if;

WHEN S3 =>
R <= "1011";
G <= "0000";
Y <= "0100";
count1 <= count1+1;
if(count1(25)='1')then
count1<=(others=>'0');
A<=S4;
end if;

WHEN S4 =>
R <= "1101";
G <= "0010";
Y <= "0000";
count2 <= count2+1;
if(count2(26)='1')then
count2<=(others=>'0');
A<=S5;
end if;

WHEN S5 =>
R <= "1101";
G <= "0000";
Y <= "0010";
count1 <= count1+1;
if(count1(25)='1')then
count1<=(others=>'0');
A<=S6;
end if;

WHEN S6 =>
R <= "1110";
G <= "0001";
Y <= "0000";

count2 <= count2+1;

if(count2(26)='1')then
count2<=(others=>'0');
A<=S7;
end if;

WHEN S7 =>
R <= "1110";
G <= "0000";
Y <= "0001";
count1 <= count1+1;
if(count1(25)='1')then
count1<=(others=>'0');
end if;

END CASE;
END IF;
END PROCESS;
end Behavioral;

TEST BENCH CODE:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY WD IS
END WD;

ARCHITECTURE behavior OF WD IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT trafic
PORT(
rst : IN std_logic;
clk : IN std_logic;
G : INOUT std_logic_vector(3 downto 0);
R : INOUT std_logic_vector(3 downto 0);
Y : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs

signal rst : std_logic := '0';

signal clk : std_logic := '0';

--BiDirs
signal G : std_logic_vector(3 downto 0);
signal R : std_logic_vector(3 downto 0);
signal Y : std_logic_vector(3 downto 0);

-- Clock period definitions

constant clk_period : time := 1us;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: trafic PORT MAP (
rst => rst,
clk => clk,
G => G,
R => R,
Y => Y
);

process(clk)
begin
clk<=(not clk) after 30 ns;

end process;

process
begin
rst <='1';
wait for 30 ns;
rst <='0';
wait;
end process;
END;

FPGA KIT:
net"rst"loc="p57";
net"clk"loc="p181";
net"G<0>"loc="p115";
net"R<0>"loc="p117";
net"Y<0>"loc="p106";
net"G<1>"loc="p123";
net"R<1>"loc="p120";
net"Y<1>"loc="p119";
net"G<2>"loc="p146";
net"R<2>"loc="p149";
net"Y<2>"loc="p131";
net"G<3>"loc="p152";
net"R<3>"loc="p13";
net"Y<3>"loc="p113";

RTL SYNTHESIS:

TEST-BENCH:

SYNTHESIS REPORT:
Release 10.1 - xst K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to D:/a/trafic/xst/projnav.tmp

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.14 secs

--> Parameter xsthdpdir set to D:/a/trafic/xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.14 secs

--> Reading design: trafic.prj

TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT

=========================================================================
*

Synthesis Options Summary

=========================================================================
---- Source Parameters
Input File Name
Input Format

: "trafic.prj"
: mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name

: "trafic"

Output Format
Target Device

: NGC
: xc3s400-4-pq208

---- Source Options

Top Module Name
Automatic FSM Extraction

: trafic
: YES

FSM Encoding Algorithm

: Auto

Safe Implementation
FSM Style

: No
: lut

RAM Extraction

: Yes

RAM Style

: Auto

ROM Extraction
Mux Style

: Yes
: Auto

Decoder Extraction

: YES

Priority Encoder Extraction

: YES

Shift Register Extraction

: YES

Logical Shifter Extraction

: YES

XOR Collapsing
ROM Style
Mux Extraction
Resource Sharing

: YES
: Auto
: YES
: YES

Asynchronous To Synchronous
Multiplier Style

: NO

: auto

Automatic Register Balancing

: No

---- Target Options

Add IO Buffers

: YES

Global Maximum Fanout

: 500

Add Generic Clock Buffer(BUFG)

Register Duplication
Slice Packing

: YES
: YES

:8

Optimize Instantiated Primitives : NO

Use Clock Enable

: Yes

Use Synchronous Set

: Yes

Use Synchronous Reset

: Yes

Pack IO Registers into IOBs

: auto

Equivalent register Removal

: YES

---- General Options

Optimization Goal

: Speed

Optimization Effort

:1

Library Search Order

: trafic.lso

Keep Hierarchy

: NO

Netlist Hierarchy

: as_optimized

RTL Output
Global Optimization
Read Cores

: Yes
: AllClockNets
: YES

Write Timing Constraints

: NO

Cross Clock Analysis

: NO

Hierarchy Separator

:/

Bus Delimiter

: <>

Case Specifier

: maintain

Slice Utilization Ratio

BRAM Utilization Ratio
Verilog 2001
Auto BRAM Packing

: 100
: 100
: YES
: NO

Slice Utilization Ratio Delta

:5

=========================================================================

=========================================================================
*

HDL Compilation

=========================================================================
Compiling vhdl file "D:/a/trafic/trafic.vhd" in Library work.
Entity <trafic> compiled.
Entity <trafic> (Architecture <behavioral>) compiled.

=========================================================================
*

Design Hierarchy Analysis

=========================================================================
Analyzing hierarchy for entity <trafic> in library <work> (architecture <behavioral>).

=========================================================================
*

HDL Analysis

=========================================================================
Analyzing Entity <trafic> in library <work> (Architecture <behavioral>).
Entity <trafic> analyzed. Unit <trafic> generated.

=========================================================================
*

HDL Synthesis

=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <trafic>.

Related source file is "D:/a/trafic/trafic.vhd".
Found finite state machine <FSM_0> for signal <A>.
----------------------------------------------------------------------| States
| Transitions
| Inputs
| Outputs
| Clock

|8
| 15
|2

|
|

| 12
| clk (rising_edge)

| Clock enable

|
|

| rst (negative)

| Power Up State
| Encoding

| s0

| automatic

| Implementation

| LUT

|
|
|
|

----------------------------------------------------------------------Found 4-bit register for signal <G>.

Found 4-bit register for signal <R>.
Found 4-bit register for signal <Y>.
Found 26-bit register for signal <count1>.
Found 26-bit adder for signal <count1$addsub0000>.

Found 27-bit register for signal <count2>.

Found 27-bit adder for signal <count2$addsub0000>.
Summary:
inferred 1 Finite State Machine(s).
inferred 65 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
Unit <trafic> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this
design can share the same physical resources for reduced device utilization. For improved clock
frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors

:2

26-bit adder

:1

27-bit adder

:1

# Registers

:5

26-bit register

:1

27-bit register

:1

4-bit register

:3

=========================================================================

=========================================================================
*

Advanced HDL Synthesis

=========================================================================

Analyzing FSM <FSM_0> for best encoding.

Optimizing FSM <A> on signal <A[1:3]> with sequential encoding.
------------------State | Encoding
------------------s0 | 000
s1 | 001
s2 | 010
s3 | 011
s4 | 100
s5 | 101
s6 | 110
s7 | 111
------------------Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx\10.1\ISE.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors

:2

26-bit adder

:1

27-bit adder

:1

# Registers

: 68

Flip-Flops

: 68

=========================================================================

=========================================================================
*

Low Level Synthesis

=========================================================================

Optimizing unit <trafic> ...

Mapping all equations...

Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block trafic, actual ratio is 1.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers
Flip-Flops

: 68
: 68

=========================================================================

=========================================================================
*

Partition Report

=========================================================================

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================
*

Final Report

=========================================================================
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format
Optimization Goal
Keep Hierarchy

Design Statistics

: trafic.ngr
: trafic

: NGC
: Speed
: NO

# IOs

: 14

Cell Usage :
# BELS

: 226

GND

:1

INV

LUT1

: 51

LUT2

:4

LUT3

: 12

LUT4

: 52

MUXCY

VCC

XORCY

:3

: 51
:1
: 51

# FlipFlops/Latches

: 68

FDC

: 12

FDE

: 56

# Clock Buffers
#

BUFGP

# IO Buffers
#

IBUF

OBUF

:1
:1
: 13
:1
: 12

=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s400pq208-4

Number of Slices:

67 out of 3584

1%

Number of Slice Flip Flops:

68 out of 7168

Number of 4 input LUTs:

122 out of 7168

1%

14 out of 141

9%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

0%

14

1 out of

8 12%

--------------------------Partition Resource Summary:

---------------------------

No Partitions were found in this design.

---------------------------

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal

| Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+
clk

| BUFGP

| 68 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

--------------------------------------------------------------------------+------------------------+-------+
Control Signal

| Buffer(FF name)

| Load |

-----------------------------------+------------------------+-------+
rst

| IBUF

| 12 |

-----------------------------------+------------------------+-------+

Timing Summary:
--------------Speed Grade: -4

Minimum period: 7.050ns (Maximum Frequency: 141.844MHz)

Minimum input arrival time before clock: 5.135ns
Maximum output required time after clock: 7.165ns
Maximum combinational path delay: No path found

Timing Detail:
-------------All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 7.050ns (frequency: 141.844MHz)
Total number of paths / destination ports: 929 / 68
------------------------------------------------------------------------Delay:
Source:

7.050ns (Levels of Logic = 28)

count2_1 (FF)

Destination:

count2_26 (FF)

Source Clock:

clk rising

Destination Clock: clk rising

Data Path: count2_1 to count2_26

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDE:C->Q

2 0.720 1.216 count2_1 (count2_1)

LUT1:I0->O
1 0.551 0.000 Madd_count2_addsub0000_cy<1>_rt
(Madd_count2_addsub0000_cy<1>_rt)
MUXCY:S->O
1 0.500 0.000 Madd_count2_addsub0000_cy<1>
(Madd_count2_addsub0000_cy<1>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<2>
(Madd_count2_addsub0000_cy<2>)

MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<3>
(Madd_count2_addsub0000_cy<3>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<4>
(Madd_count2_addsub0000_cy<4>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<5>
(Madd_count2_addsub0000_cy<5>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<6>
(Madd_count2_addsub0000_cy<6>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<7>
(Madd_count2_addsub0000_cy<7>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<8>
(Madd_count2_addsub0000_cy<8>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<9>
(Madd_count2_addsub0000_cy<9>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<10>
(Madd_count2_addsub0000_cy<10>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<11>
(Madd_count2_addsub0000_cy<11>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<12>
(Madd_count2_addsub0000_cy<12>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<13>
(Madd_count2_addsub0000_cy<13>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<14>
(Madd_count2_addsub0000_cy<14>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<15>
(Madd_count2_addsub0000_cy<15>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<16>
(Madd_count2_addsub0000_cy<16>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<17>
(Madd_count2_addsub0000_cy<17>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<18>
(Madd_count2_addsub0000_cy<18>)

MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<19>
(Madd_count2_addsub0000_cy<19>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<20>
(Madd_count2_addsub0000_cy<20>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<21>
(Madd_count2_addsub0000_cy<21>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<22>
(Madd_count2_addsub0000_cy<22>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<23>
(Madd_count2_addsub0000_cy<23>)
MUXCY:CI->O
1 0.064 0.000 Madd_count2_addsub0000_cy<24>
(Madd_count2_addsub0000_cy<24>)
MUXCY:CI->O
0 0.064 0.000 Madd_count2_addsub0000_cy<25>
(Madd_count2_addsub0000_cy<25>)
XORCY:CI->O

1 0.904 0.869 Madd_count2_addsub0000_xor<26> (count2_addsub0000<26>)

LUT3:I2->O

1 0.551 0.000 count2_mux0001<0>1 (count2_mux0001<0>)

FDE:D

0.203

count2_26

---------------------------------------Total

7.050ns (4.965ns logic, 2.085ns route)

(70.4% logic, 29.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 56 / 56
------------------------------------------------------------------------Offset:
Source:
Destination:

5.135ns (Levels of Logic = 2)

rst (PAD)
count1_0 (FF)

Destination Clock: clk rising

Data Path: rst to count1_0

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

13 0.821 1.170 rst_IBUF (rst_IBUF)

INV:I->O

56 0.551 1.991 A_ClkEn_inv1_INV_0 (A_ClkEn_inv)

FDE:CE

0.602

A_FFd3

---------------------------------------Total

5.135ns (1.974ns logic, 3.161ns route)

(38.4% logic, 61.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 12 / 12
------------------------------------------------------------------------Offset:
Source:

7.165ns (Levels of Logic = 1)

G_3 (FF)

Destination:

G<3> (PAD)

Source Clock:

clk rising

Data Path: G_3 to G<3>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDC:C->Q
OBUF:I->O

1 0.720 0.801 G_3 (G_3)

5.644

G_3_OBUF (G<3>)

---------------------------------------Total

7.165ns (6.364ns logic, 0.801ns route)

(88.8% logic, 11.2% route)

=========================================================================

Total REAL time to Xst completion: 3.00 secs

Total CPU time to Xst completion: 3.86 secs

-->

Total memory usage is 149236 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)