Acer Aspire 5551G 5552G (Compal LA-5911P) Laptop Schematics

A
ZZZ
PCB
Part Number = DAZ0FQ00100
ZZZ
1
64M512@
X76244BOL01
Part Number = X76244BOL01

ZZZ
64M1G@
Compal Confidential
X76244BOL03

ZZZ
128M1G@
X76244BOL05

ZZZ
128M2G@
2
PEW76 Schematics Document
X76244BOL06
AMD Danube
Champlain Processor with RS880M/SB820/Madison VGA
2010-06-07
LA5911P REV: 1.0
2008/10/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/03/12
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet
Tuesday, September 14, 2010

E
of
55
Compal Confidential
Model Name : NEW75/85/95
Danube
VRAM 1GB
64M16 x 8
AMD S1G4 Processor
DDR3
ATI M97
Madisan/Park
uFCBGA-962
Page 14,15,16,17,18,21,22
Memory BUS(DDR3)
uPGA-638 Package
Champlain page 4,5,6,7
page 19, 20
204pin DDRIII-SO-DIMM X2
Dual Channel
BANK 0, 1, 2, 3
page 8,9
1.5V DDRIII 800~1333MHz

1
Hyper Transport Link

16 x 16
PCI-Express x 16
Gen2
Thermal Sensor
ADM1032
ATI RS880M
Clock Generator
ICS9LPRS488
page 6
LVDS
page 23
uFCBGA-528
page 24
page 10,11,12,13
page 36,37
page 27
page 37
page 36
Bluetooth
Conn
Mini
card
(WL)X1
page 36
page 36
3G/GPS
WWAN
Card
Reader
CRT
page 26
USB
conn
X3
A link Express2
Gen1
HDMI Conn.
page 25
<Option>
USB port 0,1,2 USB port 5
ATI SB820M
Broadcom
BCM57780
WLAN
page 36
3.3V 48MHz
S-ATA
page 27,28,29,30,31
USB port 12
<Option>
USB port 8
USB port 9
USB port 6
2
USB
3.3V 24.576MHz/48Mhz
uFCBGA-605
LAN(GbE)
MINI Card 1
GPP1
CMOS
Camera
HD Audio
Gen2
page 34
HDA Codec
ALC272X
page 42
GPP0
RJ45
LPC BUS
page 35
SATA HDD
Conn. page 32
CDROM
Conn.
page 32
port 0
port 1
Audio AMP
page 43
LED
3
ENE KB926
Fan Control
page 40
page 38
page 44
Phone Jack x2
page 43
RTC CKT.
page 26
LID SW / MEDIA/B
page 39
Int.KBD
Touch Pad
Extend Card/B
page 39
1. USB X2
2. Cardreader
JM385
page 39
EC I/O Buffer
BIOS
page 38
page 39
Power On/Off CKT.

page 41
DC/DC Interface CKT.

4
page 45
Power Circuit
2008/10/06
Issued Date
Compal Secret Data
page 46,47,48,49,50,51
52,53,54
2009/10/06
Deciphered Date
Title
Size
B
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet

E
of
55
AMD
VGA
ATI
Madison/Park
VGA_CLKP/N
100MHz
MEM_MA_CLK1_P/N
MEM_MA_CLK7_P/N
A_SODIMM
C
1066MHz
MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N
B_SODIMM
CLK_SBSRC_BCLK/#
AMD
AMD
SB
SB820M
Internal CLK GEN
CPU_HT_CLKP/N
S1G4
CPU SOCKET
200MHz
1066MHz
AMD
100MHz
NB_DISP_CLKP/N
NB
RS880M
100MHz
NB_HT_CLKP/N
100MHz
32.768KHz
25MHz
GPP_CLK3P
100MHz
GPP_CLK1P/N
100MHz
WLAN
Mini PCI Socket
GbE LAN
Broadcom
B57780
2005/10/10
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Size Document Number
Custom
Date:
Rev
D
401827
Sheet

1
of
55
SIGNAL
STATE
Voltage Rails
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
Clock
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
Power Plane
Description
S1
S3
S5
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
VIN
Adapter power supply (19V)
N/A
N/A
N/A
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE_0
Core voltage for CPU (0.7-1.2V)
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
+CPU_CORE_1
Core voltage for CPU (0.7-1.2V)
ON
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+CPU_CORE_NB
Voltage for On-die Northbridge of CPU(0.8-1.1V)ON
OFF
OFF
+0.9V
0.9V switched power rail for DDR terminator
ON
ON
OFF
+1.1VS
1.1V switched power rail for NB VDDC & VGA
ON
OFF
OFF
+1.2V_HT
1.2V switched power rail
ON
OFF
OFF
Vcc
Ra/Rc/Re
+VGA_CORE
0.95-1.2V switched power rail
ON
OFF
OFF
Board ID
+1.5VS
1.5V power rail for PCIE Card
ON
OFF
OFF
+1.8V
1.8V power rail for CPU VDDIO and DDR
ON
ON
OFF
+1.8VS
ON
OFF
OFF
+2.5VS
2.5V for CPU_VDDA
ON
OFF
OFF
ON*
0
1
2
3
4
5
6
7
Full ON
+3VALW
3.3V always on power rail
ON
ON
+3V_LAN
3.3V power rail for LAN
ON
ON
ON
+3VS
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
Board ID / SKU ID Table for AD channel
REQ#/GNT#
EC SM Bus1 address
Board ID
0
1
2
3
4
5
6
7
Interrupts
Address
HEX
Smart Battery
0001 011X b
16H
Device
Address
HEX
ADI ADM1032 (CPU)
1001 100X b
98H
GMT G781-1 (GPU)
1001 101X b
9AH
SB-Temp Sensor
SB820
SM Bus 0 address
Address
HEX
Clock Generator
(SILEGO SLG8SP626)
1101 001Xb
D2
DDR DIMM1
1001 000Xb
90
DDR DIMM2
1001 010Xb
94
Device
98H
Address
EXT CLKGEN
BOM Config
Mini card
INT CLKGEN
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
BTO Option Table
Add USB patch

--For SSID define
--For TSI thermal math
3
PCB Revision
NEW75/85/95
PEW76/86/96
PEW56
PowerXpress SKU(Madison): 3G@/BT@/UMA@/ VGA@/SG@/EXT@/EXTPW@/VB@/MAD@

PowerXpress SKU(Park):
3G@/BT@/UMA@/ VGA@/SG@/EXT@/EXTPW@/VB@/PARK@
DIS ONLY:(Park)
3G@/BT@/DISO@/ VGA@/EXT@/EXTPW@/PARK@
UMA only SKU:
3G@/BT@/UMA@/ UMAO@/EXT@/VB@
PowerXpress SKU(Madison):3G@/BT@/UMA@/VGA@/SG@/INT@/VB@/MAD@
PowerXpress SKU(Park):
3G@/BT@/UMA@/VGA@/SG@/INT@/VB@/PARK@
DIS ONLY(PARK):
3G@/BT@/DISO@/VGA@/INT@/PARK@
UMA only SKU:
3G@/BT@/UMA@/UMAO@/INT@/VB@
2010/03/12
Deciphered Date
Title
Date:
Compal Secret Data

2008/10/06
Size
B
A
BOM Structure
Capilano w/ USB patch
Issued Date
BTO Item
No USB Patch
Board ID
0
1
2
3
4
5
6
7
SB820
SM Bus 1 address
Device
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
PCB Revision
Project ID Table
EC SM Bus2 address
Device
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
BOARD ID Table
External PCI Devices

IDSEL#
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Device
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet

E
of
55
AMD CPU S1G4

+CPU_CORE
BATTERY
12.6V
BATT+
PU5
CHARGER
ISL6261AHAZ-T
PU15
ISL6265IRZ-T
PU16
APL5508-25DC
AC ADAPTOR
19V 90W
+CPU_CORE
0.7~1.3V
VDD CORE 36A
+CPU_CORE_NB
0.8~1.2V
VDDNB 4A
2.5V
VDDA 250mA
1.5V
VDDIO 3A
1.05V
VDDR 1.5A
1.1V
VLDT 1.5A
+CPU_CORE_NB
+2.5VS
+1.05VS
+1.05VS
PU12
APL5915
VIN
+1.1VS
RAM DDRIII SODIMMX2

+1.5V
PU7
RT8209BGQW
B+
+1.5V
1.5V
VDD_MEM 4A
0.75V
VTT_MEM 0.5A
+0.75VS
PU10
APL5913
NorthBridge AMD RS880M
PU8
RT8209BGQW
PU6
RT8209BGQW
1.0~1.1V
VDDC 1.0V-1.1V 7.6A
1.1V_S0
VDDHTRX+HT 0.68A
VDDPCIE 1.1A
VDDHTTX 0.68A
PLLs 0.23A
1.8V_S0
VDDA18 0.64A
VDDG18 0.005A
VDDLT18 0.22A
PLLs 0.1A
3.3V_S0
VDDG33 0.06A
AVDD 0.125A
VDDLT33 0A
No Use
VDD18_MEM 1.8V 0.005A

VDD_MEM 1.8V 0.23A
+NB_CORE
+1.1VS
+1.1VALW
+1.1VALW
U36
SI4800BDY
+1.1VS
+1.5V
+1.5VS
PU19
TSP51117RGYR
U35
SI4800BDY
VGA ATI Madison / Park

PU17
APW7138NITRL
+GPU_CORE
+VDDCI
0.85~1.1V
+1VSG
PU10
APL5913
+1.8VS
PU14
APL5913
PU11
MP2121DQ
+1.8VSP2
1.0V
PCIE_VDDC 2 A
DP[F:A]_VDD10 230 mA
DPLL_VDDC 125 mA
SPV10 100 mA
1.5V
VDDR1 TBD A
1.8V
PCIE_PVDD 40 mA
PCIE_VDDR 400 mA
TSVDD 5 mA
VDDR4 TBD mA
VDD_CT 17 mA
DP[F:A]_PVDD 20 mA
DP[F:A]_VDD18 330 mA
AVDD 70 mA
VDD1DI 45 mA
A2VDDQ 1.5 mA
VDD2DI 50 mA
DPLL_PVDD 75 mA
MPV18 150 mA
SPV18 50 mA
3.3V
VDDR3 60 mA
A2VDD 130 mA
+1.8VSP1
PU4
SN0806081 RHBR
+5VALW
U37
SI1800BDY
+3VS
LCD panel
15.6"
Delay
+3VS_DELAY
U34
SI4800BDY +5VS
B+ 300mA
VRAM 1GB
64Mx16 (K4B1G1646E) * 8
+1.5VS
+3VALW
+INVPWR_B+
VDDC 29 A
VDDCI 4 A
+3.3 350mA
1.5V
2.4 A
SouthBridge AMD SB820M
1.1V_S0
+1.1VALW
FAN Control
APL5607
1.1V_S5
+5VS 500mA
3.3V_S0
+3VALW
U25/U40
TPS2061DRG4 +USB_VCCA
3.3V_S5
+USB_VCCB
Audio AMP
TPA6017A2
USB X3
+5V
Dual+1
2.5A
+5V 25mA
SATA
Audio Codec
ALC272
+5V 3A
+5V 45mA
+3.3V
+3.3VS 25mA
Realtek
RTS5159
EC
ENE KB926
LAN
Atheros AR8114
ICS9LPRS488B
+3.3VS 300mA
+3.3VALW 30mA
+3.3VS 3mA
+3.3VALW 201mA
+3.3V 400mA
Mini Card
No Use
RTC
Bettary
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
+1.1V
VDDCR_11_S 113mA
VDDAN_11_USB_S 200mA
VDDCR_11_USB_S 197mA
VDDPL_11_SYS_S
VDDIO_33_PCIGP 0.020A
VDDPL_33_PCIE 0.030A
VDDPL_33_SATA 0.020A
VDDPL_33_SYS
VDDIO_33_S
VDDPL_33_USB_S
VDDAN_33_USB_S 0.2A
VDDAN_33_S
VDDXL_33_S
VDDIO_AZ_S
VDDCR_11_GBE_S
VDDRF_GBE_S
VDDIO_33_GBE_S
VDDIO_GBE_S
VDDIO_18_FC
VDDBT_RTC_G
Compal Secret Data
Issued Date
2.5~3.6V
BAT
VDDCR_11 1.1V 0.5A

VDDAN_11_PCIE 1A
VDDAN_11_SATA 0.8A
VDDAN_11_CLK 0.4A
2009/3/8
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827

1
Sheet
of
55
VLDT CAP.
+1.1VS
250 mil
2
<12> H_CADIP[0..15]
<12> H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADON[0..15]
<12>
1
<12>
C1
10U_0805_10V4Z
C2
10U_0805_10V4Z
C3
0.22U_0603_16V4Z
C4
0.22U_0603_16V4Z
C5
180P_0402_50V8J
C6
180P_0402_50V8J
Near CPU Socket

+1.1VS
+1.1VS
JCPU1A
TBD
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
C7
HT LINK
D1
D2
D3
D4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
10U_0805_10V4Z
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
<12>
<12>
<12>
<12>
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
J3
J2
J5
K5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
Y1
W1
Y4
Y3
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
N1
P1
P3
P4
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
R2
R3
T5
R5
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
<12>
<12>
<12>
<12>
FOX_PZ6382A-284S-41F_Champlian
CONN@
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet

E
of
55
Processor DDR3 Memory Interface

JCPU1C
<11> DDRB_SDQ[63..0]
1
MEM:DATA
+1.5V
R1
1K_0402_1%
C8
1000P_0402_50V7K
C9
0.01U_0402_25V7K
MEM_VREF
1
R2
1K_0402_1%
+1.5V
+CPU_VDDR
+CPU_VDDR
JCPU1B
Place them
close to CPU
within 1"
R368
0_0402_5%
1
R4
1
1
R5
C588
10U_0805_10V4Z
@ 1
<10> MEM_MA_RST#
<10> DDRA_ODT0
<10> DDRA_ODT1
<10> DDRA_SCS0#
<10> DDRA_SCS1#
<10> DDRA_CKE0
<10> DDRA_CKE1
<10> DDRA_CLK0
<10> DDRA_CLK0#
<10> DDRA_CLK1
<10> DDRA_CLK1#
<10> DDRA_SMA[15..0]
<10> DDRA_SBS0#
<10> DDRA_SBS1#
<10> DDRA_SBS2#
<10> DDRA_SRAS#
<10> DDRA_SCAS#
<10> DDRA_SWE#
1.5A
D10
C10
B10
AD10
39.2_0402_1%
MEMZP AF10
2
MEMZN AE10
2
39.2_0402_1%
MEM_MA_RST#
H16
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1#
DDRA_CKE0
DDRA_CKE1
DDRA_CLK0
DDRA_CLK0#
VDDR: DDR3 under 1033MHz

set to 0.9V to save power
VDDR1 MEM:CMD/CTRL/CLK
VDDR5
VDDR2
VDDR6
VDDR3
VDDR7
VDDR4
VDDR8
VDDR9
MEMZP
MEMZN
VDDR_SENSE
W10
AC10
AB10
AA10
A10
MA_RESET_L
MEMVREF
W17
MEM_VREF
MB_RESET_L
B18
MEM_MB_RST#
MB0_ODT0
MB0_ODT1
MB1_ODT0
W26
W23
Y26
DDRB_ODT0
DDRB_ODT1
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
V26
W25
U22
DDRB_SCS0#
DDRB_SCS1#
MB_CKE0
MB_CKE1
J25
H26
DDRB_CKE0
DDRB_CKE1
DDRB_CLK0
DDRB_CLK0#
T19
V22
U21
V19
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
T20
U19
U20
V20
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
J22
J20
MA_CKE0
MA_CKE1
Y10
VTT_SENSE
N19
N20
E16
F16
Y16
AA16
P19
P20
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
P22
R22
A17
A18
AF18
AF17
R26
R25
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
R20
R23
J21
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
R24
U26
J26
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
R19
T22
T24
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
U25
U24
U23
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
DDRA_CLK1
DDRA_CLK1#
DDRB_CLK1
DDRB_CLK1#
PAD
T1
MEM_MB_RST# <11>
DDRB_ODT0 <11>
DDRB_ODT1 <11>
DDRB_SCS0# <11>
DDRB_SCS1# <11>
DDRB_CKE0 <11>
DDRB_CKE1 <11>
DDRB_CLK0 <11>
DDRB_CLK0# <11>
DDRB_CLK1 <11>
DDRB_CLK1# <11> <11> DDRB_SDM[7..0]
DDRB_SMA[15..0] <11>
DDRB_SBS0# <11>
DDRB_SBS1# <11>
DDRB_SBS2# <11>
DDRB_SRAS# <11>
DDRB_SCAS# <11>
DDRB_SWE# <11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
CONN@
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
E12
C15
E19
F24
AC24
Y19
AB16
Y13
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
DDRA_SDQ[63..0]
<10>
1
DDRA_SDM[7..0]
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
CONN@
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet

E
of
55
FBMA-L11-201209-221LMA30T_0805 1
1
+
C11
150U_B_6.3VM_R40M
change to SGA00002N80
VDDA=0.25A
3300P_0402_50V7K
4.7U_0805_10V4Z
1
C12
LDT_RES# / MEMHOT#
no support in S1g4
1
C13
+1.5V
C14
0.22U_0603_16V4Z
R6
10K_0402_5%
+2.5VS
Champlain: C1E
C1E: LDT_REQ# no connect
CLMC: LDT_REQ# connect to NB
+2.5VDDA
L1
R7
1K_0402_5%
1
JCPU1D
2 2
LDT_RST#
H_PWRGD
LDT_STOP#
R10
169_0402_1%
<22> CLK_CPU_BCLK#
C15
T2
2
3900P_0402_50V7K
+1.5V
+1.5V
+1.5VS
R12
R14
2
1
LDT_RST#
LDT_RST#
1
+1.5VS <13,26> LDT_STOP#
2
R21
300_0402_5%
<26> H_PWRGD
1
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC
THERMDA
HT_REF0
HT_REF1
CPU_SVC <52>
CPU_SVD <52>
PAD
W7
W8
THERMDC_CPU
THERMDA_CPU
T3
VDD0_FB_H
VDD0_FB_L
VDDIO_FB_H
VDDIO_FB_L
W9
Y9
CPU_VDD1_FB_H
Y6
CPU_VDD1_FB_L AB6
VDD1_FB_H
VDD1_FB_L
VDDNB_FB_H
VDDNB_FB_L
H6
G6
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
DBREQ_L
E10
CPU_DBREQ#
TDO
AE9
CPU_TDO
LDT_STOP#
G10
AA9
AC9
AD9
AF9
CPU_TEST23
AD7
CPU_TEST18
CPU_TEST19
H10
G9
CPU_TEST25H
CPU_TEST25L
C18
0.01U_0402_25V4Z
@
1
R24
TEST25_H
TEST25_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
2
0_0402_5%
C2
AA6
TEST9
TEST6
A3
A5
B3
B5
C1
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
+3VS
TEST28_H
TEST28_L
TEST18
TEST19
AB8
AF7
AE7
AE8
AC8
AF8
H_THERMTRIP# <27>
1
R9
2
0_0402_5%
1
R11
MAINPWON <44,45,49>
2
300_0402_5%
H_PROCHOT#
1
R13
2
0_0402_5%
H_PROCHOT_R# <26>
PROCHOT:
Input: For HTC Function
Output: Over Temperature Condition
CPU_VDDNB_FB_H <52>
CPU_VDDNB_FB_L <52>
+1.5V
TEST23
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
H_PWRGD
C19
0.01U_0402_25V4Z
@
E9
E8
DBRDY
TMS
TCK
TRST_L
TDI
2
0_0402_5%
CPU_THERMTRIP#_R
H_PROCHOT#
AF6
AC7
AA8
<52> CPU_VDD1_FB_H
<52> CPU_VDD1_FB_L
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
1
R8
MMBT3904_NL_SOT23-3
CPU_SVC
CPU_SVD
+1.5V
SIC
SID
ALERT_L
R6
P6
A6
A4
F6
E6
R18
300_0402_5%
SVC
SVD
<52> CPU_VDD0_FB_H
<52> CPU_VDD0_FB_L
+1.5VS
C17
0.01U_0402_25V4Z
@
AF4
AF5
AE6
VSS
RSVD11
CPU_VDD0_FB_H
CPU_VDD0_FB_L
PAD
2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1
1
1
CLKIN_H
CLKIN_L
B7
A7
F10
C6
CPU_SIC
CPU_SID
2
2 1K_0402_5%
1K_0402_5%
R15
R16
+1.1VS
R17
300_0402_5%
<26>
1
1
VDDA1
VDDA2
A9
A8
C16
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
2 3900P_0402_50V7K
CPU_THERMTRIP#_R
M11
W18
Q1
1
<22> CLK_CPU_BCLK
F8
F9
TEST17
TEST16
TEST15
TEST14
D7
E7
F7
C7
TEST7
TEST10
C3
K8
TEST8
C4
TEST29_H
TEST29_L
C9
C8
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
J7
H8
CPU_SVC
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
PAD
PAD
PAD
PAD
T5
T6
T7
T8
1
R19
1
R20
CPU_SVD
2
1K_0402_5%
2
1K_0402_5%
+1.5V
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
2
R25
CPU_TEST25H
1
R22
1
R23
CPU_TEST25L
1
R26
1
R27
1
80.6_0402_1%
H18
H19
AA7
D5
C5
2
510_0402_5%
2
510_0402_5%
+1.5V
2
510_0402_5%
2
510_0402_5%
CPU_TEST27
D+
THERMDC_CPU
D-
2
4
EC_SMB_CK2
SDATA
EC_SMB_DA2
ALERT#
CPU_TEST12
GND
CPU_TEST18
SCLK
THERM#
CPU_TEST19
ADM1032ARMZ_MSOP8
+1.5V
CPU_TEST20
C22
R41
2
0.1U_0402_16V4Z
R42
FDV301N, the Vgs is:

min = 0.65V
Typ = 0.85V
Max = 1.5V
30K_0402_1%
31.6K_0402_1%
2.09V for Gate
Q2
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
@
CPU_SID 3
EC_SMB_DA
BSH111 1N_SOT23-3
1
R44
1
R45
2
0_0402_5%
2
0_0402_5%
SB_SID
SB_SID <27>
EC_SMB_DA2
T0 SB
CPU_TEST22
CPU_TEST24
CPU_TEST23
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
JP2
1
3
5
7
9
11
13
15
17
19
21
23
TO EC
2
4
6
8
10
12
14
16
18
20
22
24
26
R43
@
2
0_0402_5%
+3VS
U2
HDT_RST#
CONN@ SAMTEC_ASP-68200-07
G
1
R29
1
R30
1
R31
1
R32
1
R33
1
R34
1
R35
1
R265
2
1
220_0402_5% R36
2
1
220_0402_5% R37
2
1
220_0402_5% R38
2
1
300_0402_5% R39
1
2
300_0402_5% R40
CPU_TEST21
CPU internal thermal sensor

1
For SCAN connect use
EC_SMB_DA2 <16,36>
Address 1001 100X b
+3VS
2
1K_0402_5%
EC_SMB_CK2 <16,36>
VDD
THERMDA_CPU
C21
100P_0402_50V8J
@
1
R28
U1 @
1
C20
Y
3
0.1U_0402_16V4Z
+1.5V
CONN@
LDT_RST#
SB_PWRGD <13,27,36>
NC7SZ08P5X_NL_SC70-5
Q3
@
CPU_SIC 3
1
D
BSH111 1N_SOT23-3
EC_SMB_CK
1
R46
1
R47
SB_SIC
2
0_0402_5%
EC_SMB_CK2
2
0_0402_5%
SB_SIC
<27>
T0 SB
TO EC
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet

E
of
55
JCPU1F
VDD(+CPU_CORE) decoupling.
JCPU1E
+CPU_CORE
+CPU_CORE
C23
330U_X_2VM_R6M
C24
330U_X_2VM_R6M
C25
330U_X_2VM_R6M
C26
330U_X_2VM_R6M
+
2
C27
330U_X_2VM_R6M
@
Near CPU Socket

+CPU_CORE
+CPU_CORE
+CPU_CORE_NB
C28
22U_0805_6.3V6M
C29
22U_0805_6.3V6M
C30
22U_0805_6.3V6M
C35
22U_0805_6.3V6M
C31
22U_0805_6.3V6M
+CPU_CORE
C32
22U_0805_6.3V6M
C33
22U_0805_6.3V6M
4A
C34
22U_0805_6.3V6M
+1.5V
+CPU_CORE
C36
0.22U_0603_16V4Z
C37
0.01U_0402_25V4Z
C38
180P_0402_50V8J
C39
0.22U_0603_16V4Z
C40
0.01U_0402_25V4Z
C41
180P_0402_50V8J
Under CPU Socket

2
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
K16
M16
P16
T16
V16
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
+CPU_CORE
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
36A
+1.5V
TBD
Athlon 64 S1
CONN@
VDDIO decoupling.
Processor Socket
+CPU_CORE_NB
decoupling.
+1.5V
+CPU_CORE_NB
1
C44
22U_0805_6.3V6M
C45
22U_0805_6.3V6M
C46
0.22U_0603_16V4Z
2
C47
0.22U_0603_16V4Z
2
C48
C50
180P_0402_50V8J 180P_0402_50V8J
2
2
C42
22U_0805_6.3V6M
C43
22U_0805_6.3V6M
C49
22U_0805_6.3V6M
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
Under CPU Socket
Athlon 64 S1 CONN@
Processor Socket
Between CPU Socket and DIMM

+1.5V
+CPU_VDDR
C51
0.22U_0603_16V4Z
C52
0.22U_0603_16V4Z
C53
0.22U_0603_16V4Z
C54
0.22U_0603_16V4Z
C354
0.22U_0603_16V4Z
VDDR decoupling.
C355
0.22U_0603_16V4Z
+
Near Power Supply

1
1
C56
150U_B_6.3VM_R40M
C55
22U_0805_6.3V6M
180PF Qt'y follow the distance between

+1.5V CPU socket and DIMM0. <2.5inch>
+1.5V
C64
0.01U_0402_25V4Z
C65
0.01U_0402_25V4Z
2
C66
0.1U_0402_16V7K
1
C67
0.1U_0402_16V7K
C68
180P_0402_50V8J
+CPU_VDDR
C69
1
180P_0402_50V8J C57
4.7U_0805_10V4Z
2
C58
4.7U_0805_10V4Z
+1.5V
C59
0.22U_0603_16V4Z
C60
0.22U_0603_16V4Z
C61
1000P_0402_50V7K
C62
1000P_0402_50V7K
C63
180P_0402_50V8J
C70
180P_0402_50V8J
Near CPU Socket Right side.

+CPU_VDDR
1
1
C71
4.7U_0805_10V4Z
1
C72
4.7U_0805_10V4Z
1
C73
4.7U_0805_10V4Z
C74
4.7U_0805_10V4Z
+ C75
330U_X_2VM_R6M
2
2
C76
4.7U_0805_10V4Z
C77
4.7U_0805_10V4Z
C78
0.22U_0603_16V4Z
C79
0.22U_0603_16V4Z
C80
1000P_0402_50V7K
C81
1000P_0402_50V7K
C82
180P_0402_50V8J
C83
180P_0402_50V8J
Near CPU Socket Left side.
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet

E
of
55
+VREF_DQ
+1.5V
+1.5V
JDIMM1
DDRA_SDQS2#
DDRA_SDQS2
<7> DDRA_SDQS2#
<7> DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ[0..63]
<7>
DDRA_SDM[0..7]
<7>
DDRA_SMA[0..15]
<7>
DDRA_SDQ12
DDRA_SDQ13
DDRA_SMA[0..15]
DDRA_SDM1
MEM_MA_RST#
MEM_MA_RST# <7>
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3
+VREF_CA
+VREF_DQ
DDRA_SDQ30
DDRA_SDQ31
DDRA_SMA3
DDRA_SMA1
<7> DDRA_CLK0
<7> DDRA_CLK0#
<7> DDRA_SBS0#
<7> DDRA_SWE#
<7> DDRA_SCAS#
<7> DDRA_SCS1#
DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
<7> DDRA_SDQS4#
<7> DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
<7> DDRA_SDQS6#
<7> DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R50
10K_0402_5%
1
2
+3VS
R51
+3VS
2
10K_0402_5%
C90
2.2U_0603_6.3V4Z
C91
G2
206
DDRA_CKE1
DDRA_CKE1 <7>
DDRA_SMA15
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
C84
@
C85
G1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
C10
R49
1K_0402_1%
C235
@
2
C351
1
C680
R315
1K_0402_1%
DDRA_SMA2
DDRA_SMA0
DDRA_CLK1
DDRA_CLK1#
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
DDRA_CLK1 <7>
DDRA_CLK1# <7>
DDRA_SBS1# <7>
DDRA_SRAS# <7>
DDRA_SCS0# <7>
DDRA_ODT0 <7>
DDRA_ODT1 <7>
+VREF_CA
DDRA_SDQ36
DDRA_SDQ37
C89
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
+1.5V
1000P_0402_50V7K
DDRA_SDQS5#
DDRA_SDQS5
0.1U_0402_16V4Z
2
DDRA_SDQ44
DDRA_SDQ45
C87
C643
1
0.1U_0402_16V4Z
DDRA_SDQS5# <7>
DDRA_SDQS5 <7>
0.1U_0402_16V4Z
2
C88
1
0.1U_0402_16V4Z
C644
1
0.1U_0402_16V4Z
2
C640
1
0.1U_0402_16V4Z
C645
1
0.1U_0402_16V4Z
2
C641
1
0.1U_0402_16V4Z
C646
1
0.1U_0402_16V4Z
2
C642
1
0.1U_0402_16V4Z
C647
1
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
+0.75VS
DDRA_SDM6
2
DDRA_SDQ54
DDRA_SDQ55
1
0.1U_0402_16V4Z
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
0.1U_0402_16V4Z
2
C665
C664
1
1
C961
2
4.7U_0603_6.3V6K
Place near DIMM1
DDRA_SDQS7# <7>
DDRA_SDQS7 <7>
DDRA_SDQ62
DDRA_SDQ63
PAD
T9
SB_SMDAT0 <11,22,27,34>
SB_SMCLK0 <11,22,27,34>
+0.75VS
4
FOX_AS0A626-U8SN-7F
CONN@
0.1U_0402_16V4Z
2
2008/10/06
Issued Date
Compal Secret Data
DIMM_A STD H:8mm
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
<Address: 00>
Date:
205
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
1000P_0402_50V7K
DDRA_SMA8
DDRA_SMA5
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
4.7U_0805_10V4Z
DDRA_SMA12
DDRA_SMA9
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
+VREF_CA
0.01U_0402_25V7K
<7> DDRA_SBS2#
DDRA_SBS2#
0.01U_0402_25V7K
DDRA_CKE0
<7> DDRA_CKE0
R310
1K_0402_1%
R48
1K_0402_1%
+VREF_DQ
+1.5V
+1.5V
DDRA_SDQS3# <7>
DDRA_SDQS3 <7>
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQS0# <7>
DDRA_SDQS0 <7>
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQS1#
DDRA_SDQS1
<7> DDRA_SDQS1#
<7> DDRA_SDQS1
DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ4
DDRA_SDQ5
1000P_0402_50V7K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
4.7U_0805_10V4Z
DDRA_SDQ2
DDRA_SDQ3
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
DDRA_SDM0
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDRA_SDQ0
DDRA_SDQ1
Rev
D
401827
Sheet

E
10
of
55
+VREF_DQ
+1.5V
+1.5V
JDIMM2
DDRB_SDQ8
DDRB_SDQ9
<7> DDRB_SDQS1#
<7> DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
<7> DDRB_SDQS2#
<7> DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
<7> DDRB_CKE0
2
<7> DDRB_SBS2#
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
<7> DDRB_SWE#
<7> DDRB_SCAS#
<7> DDRB_SCS1#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#
DDRB_SDQ32
DDRB_SDQ33
<7> DDRB_SDQS4#
<7> DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
<7> DDRB_SDQS6#
<7> DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R52
10K_0402_5%
1
2
+3VS
R53
205
10K_0402_5%
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
G2
206
G1
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQS0# <7>
DDRB_SDQS0 <7>
DDRB_SDQ[0..63]
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SDM[0..7]
<7>
<7>
1
DDRB_SDQ12
DDRB_SDQ13
DDRB_SMA[0..15]
DDRB_SDM1
MEM_MB_RST#
DDRB_SMA[0..15]
<7>
MEM_MB_RST# <7>
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQS3# <7>
DDRB_SDQS3 <7>
DDRB_SDQ30
DDRB_SDQ31
DDRB_CKE1
DDRB_CKE1 <7>
DDRB_SMA15
DDRB_SMA14
DDRB_SMA11
DDRB_SMA7
+VREF_DQ
DDRB_SMA6
DDRB_SMA4
+VREF_CA
DDRB_SMA2
DDRB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
+VREF_DQ
DDRB_CLK1 <7>
DDRB_CLK1# <7>
DDRB_SBS1# <7>
DDRB_SRAS# <7>
DDRB_SCS0# <7>
DDRB_ODT0 <7>
C92
C93
+VREF_CA
C682
C352
0.1U_0402_16V4Z
<7> DDRB_SBS0#
DDRB_SMA10
DDRB_SBS0#
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDRB_SDQ4
DDRB_SDQ5
0.1U_0402_16V4Z
<7> DDRB_CLK0
<7> DDRB_CLK0#
DDRB_CLK0
DDRB_CLK0#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C353
1000P_0402_50V7K
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
4.7U_0805_10V4Z
DDRB_SDQ2
DDRB_SDQ3
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1000P_0402_50V7K
DDRB_SDM0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
4.7U_0805_10V4Z
DDRB_SDQ0
DDRB_SDQ1
C683
DDRB_ODT1 <7>
+VREF_CA
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
C94
1000P_0402_50V7K
2
3
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQS5# <7>
DDRB_SDQS5 <7>
+1.5V
DDRB_SDQ46
DDRB_SDQ47
0.1U_0402_16V4Z
2
DDRB_SDQ52
DDRB_SDQ53
C677
0.1U_0402_16V4Z
2
C670
1
0.1U_0402_16V4Z
DDRB_SDM6
C666
C671
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C667
1
0.1U_0402_16V4Z
C672
1
0.1U_0402_16V4Z
2
C668
C673
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C669
C674
1
0.1U_0402_16V4Z
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
+0.75VS
+1.5V
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQS7# <7>
DDRB_SDQS7 <7>
DDRB_SDQ62
DDRB_SDQ63
PAD
0.1U_0402_16V4Z
2
C676
1
0.1U_0402_16V4Z
T10
C675
1
1
+
C925
2
4.7U_0603_6.3V6K
SB_SMDAT0 <10,22,27,34>
SB_SMCLK0 <10,22,27,34>
C86
330U_X_2VM_R6M
Place near DIMM2
+0.75VS
4
FOX_AS0A626-U4SN-7F
CONN@
DIMM_B STD H:4mm

<Address: 01>
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet

E
11
of
55
<15> PCIE_GTX_C_MRX_P[0..15]
<15> PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15] <15>
PCIE_MTX_C_GRX_N[0..15] <15>
U3B
1
2 GPP0P AE3
R54 1 0_0402_5%
2 GPP0N AD4
R55
0_0402_5%
AE2
AD3
AD1
AD2
PCIE_PTX_C_IRX_P0 1
PCIE_PTX_C_IRX_P3V5
@
2
PCIE_PTX_C_IRX_N0 1R56 @ 0_0402_5%
PCIE_PTX_C_IRX_N3
W6
2
R57
0_0402_5%
U5
U6
R56,R57 close to R54,R55
U8
U7
<32> PCIE_PTX_C_IRX_P0
<32> PCIE_PTX_C_IRX_N0
<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
AC8
AB8
PART 2 OF 6
PCIE I/F GPP
PCIE I/F SB
C96
C98
2VGA@
2VGA@
C100 1
2VGA@
C102 1
2VGA@
C104 1
2VGA@
C106 1
2VGA@
C108 1
2VGA@
C110 1
2VGA@
C112 1
2VGA@
C114 1
2VGA@
C116 1
2VGA@
C118 1
2VGA@
C120 1
2VGA@
C122 1
2VGA@
C124 1
2VGA@
C126 1
2VGA@
C127 1
C128
1
C129 1
C130
1
PCIE_ITX_PRX_P3 C131 1@
PCIE_ITX_PRX_N3 C132 @1
2
2
2
2
C95 1
0.1U_0402_16V7K
C97 1
0.1U_0402_16V7K
C99 1
0.1U_0402_16V7K
C101 1
0.1U_0402_16V7K
C103 1
0.1U_0402_16V7K
C105 1
0.1U_0402_16V7K
C107 1
0.1U_0402_16V7K
C109 1
0.1U_0402_16V7K
C111 1
0.1U_0402_16V7K
C113 1
0.1U_0402_16V7K
C115 1
0.1U_0402_16V7K
C117 1
0.1U_0402_16V7K
C119 1
0.1U_0402_16V7K
C121 1
0.1U_0402_16V7K
C123 1
0.1U_0402_16V7K
C125 1
0.1U_0402_16V7K
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
2VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
<32>
<32>GLAN
<34>
<34>WLAN
Reserve for LAN debug
C131,C132 close to C127,C128
<6> H_CADOP[0..15]
<6> H_CADON[0..15]
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R59
R58
C133
C134
C135
C136
C137
C138
C139
C140
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1.27K_0402_1%
2K_0402_1%
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>
H_CADIP[0..15]
H_CADIN[0..15]
+1.1VS
RS880 A11(SA000032710)
<6>
<6>
<6>
<6>
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<6>
<6>
<6>
<6>
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1
R60
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
T22
T23
AB23
AA22
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
M22
M23
R21
R20
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
2
HT_RXCALP
HT_RXCALN
301_0402_1%~D
C23
A24
<6>
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
H24
H25
L21
L20
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
M24
M25
P19
R18
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
B24
B25
HT_TXCALP
HT_TXCALN
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
PART 1 OF 6
<6>
<6>
<6>
<6>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
<6>
<6>
<6>
<6>
R61
301_0402_1%~D
Compal Secret Data

2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Date:
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
Custom
A
0718 Place within 1"

layout 1:2
RS880 A11(SA000032710)
2008/10/06
<6>
RS780M_FCBGA528
0718 Place within 1"

layout 1:2
H_CADIP[0..15]
H_CADIN[0..15]
U3A
RS780M_FCBGA528
Issued Date
H_CADOP[0..15]
H_CADON[0..15]
HYPER TRANSPORT CPU I/F
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
PCIE I/F GFX
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
Rev
D
401827
Sheet

E
12
of
55
+1.8VS
20mA
1
+AVDDQ
FBMA-L11-160808-221LMT 0603
C148
2.2U_0603_6.3V4Z
L7
C149
1U_0402_6.3V4Z
2
1
C151
1U_0402_6.3V4Z
2
1
20mA
R66
1
1
R67
<14,26,36> A_RST#
<27> NB_PWRGD
+1.8VS
R68
<22> CLK_NBHT
<22> CLK_NBHT#
1
2
R70
4.7K_0402_5%
2 INT@ 1
R504 2 INT@4.7K_0402_5%
1
R506
4.7K_0402_5%
EXT@
2 4.7K_0402_5%
R78
2 4.7K_0402_5% GMCH_LCD_DATA
R79
2 4.7K_0402_5%
R80
2 4.7K_0402_5% GMCH_CRT_DATA
R173 2
1 4.7K_0402_5%
<22> CLK_SBLINK_BCLK
<22> CLK_SBLINK_BCLK#
GMCH_LCD_CLK
CLK_NBGFX
CLK_NBGFX#
<22> CLK_NBGFX
<22> CLK_NBGFX#
R77
0_0402_5%
NB_RESET#
NB_PWRGD_R
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
NB_REFCLK_P
NB_REFCLK_N
EXT@
+3VS
0_0402_5%
2
2
1
300_0402_5%
1EXT@
2
0_0402_5%
1INT@
2
R456 1INT@ 0_0402_5%
2
R439
0_0402_5%
1
2
+1.1VS
R69
4.7K_0402_5%
<26> NB_DISP_CLKP
<26> NB_DISP_CLKN
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
G18
G17
E18
F18
E19
F19
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
A11
B11
F8
E8
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
GMCH_LCD_CLK
GMCH_LCD_DATA
<23> GMCH_LCD_CLK
<23,38> GMCH_LCD_DATA
<38> AUX0N
GMCH_CRT_CLK
AUX0N
<48> POWER_SEL
H17
120mA
+VDDA18PCIEPLL
R536
E17
F17
F15
+NB_PLLVDD
+NB_HTPVDD
C155
1U_0402_6.3V4Z
+VDDA18HTPLL
<22> CLK_NB_14.318M
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
DAC_RSET
G14
2
715_0402_1%
65mA
+NB_PLLVDD
A12
+NB_HTPVDD 20mA
D14
B12
1
R65
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA
<14,25> GMCH_CRT_HSYNC
<14,25> GMCH_CRT_VSYNC
<25> GMCH_CRT_CLK
<25> GMCH_CRT_DATA
L9
1
GMCH_CRT_B
<25> GMCH_CRT_B
+VDDA18PCIEPLL
FBMA-L11-160808-221LMT 0603
C154
2.2U_0603_6.3V4Z
GMCH_CRT_G
<25> GMCH_CRT_G
+1.8VS
GMCH_CRT_R
<25> GMCH_CRT_R
1
2
R82
2K_0402_5%
POWER_SEL
@
1
R86
2
100_0402_5%
1
R85
@ C158
@C158
1
2
100P_0402_25V8K
2
150_0402_1%
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
VDDA18HTPLL
D8
A10
C10
C12
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
C25
C24
HT_REFCLKP
HT_REFCLKN
E11
F11
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
T2
T1
GFX_REFCLKP
GFX_REFCLKN
U1
U2
GPP_REFCLKP
GPP_REFCLKN
V4
V3
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
B9
A9
B8
A8
B7
A7
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
EMI
C8
A22
B22
A21
B21
B20
A20
A19
B19
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
B18
A18
A17
B17
D20
D21
D18
D19
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
A15
B15
A14
B14
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
C14
D15
C16
C18
C20
E20
C22
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
E9
F7
G12
DAC_RSET(PWM_GPIO1)
VDDA18PCIEPLL1
VDDA18PCIEPLL2
B10
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
PART 3 OF 6
D7
E7
G11
CLK_NB_14.318M
HIGH
POWER_SEL
L8
C152
1U_0402_6.3V4Z
15mA
STRP_DATA
RSVD
AUX_CAL(NC)
TMDS_HPD(NC)
HPD(NC)
1
R87
1
R88
1
R89
R71 1
2 0_0402_5%
R72 1 VB@
2 0_0402_5%
R76 1 VB@
2 0_0402_5%
GMCH_ENBKL
GMCH_INVT_PWM <23>
If support VB, pop VB@ and reserve R71
R74
R75
1
R81
2
0_0402_5%
D9
D10
SUS_STAT#(PWM_GPIO5)
D12
THERMALDIODE_P
THERMALDIODE_N
AE8
AD8
TESTMODE
D13
SUS_STAT# <27>
To SB
SUS_STAT_R# <14>Strap
pin
1
2
R84
1.8K_0402_5%
2
R106
1
4.7K_0402_5%
GMCH_CRT_R
2
140_0402_1%
GMCH_CRT_G
2
150_0402_1%
GMCH_CRT_B
2
150_0402_1%
Q41
UMA@
2N7002_SOT23
PD on chip side
VGA_ENBKL
Q63
2N7002_SOT23
4
Q62
VGA@
2
G
S
2N7002_SOT23
Compal Secret Data

2008/10/06
ENBKL <36>
D
2
G
<16> VGA_ENBKL
Issued Date
R149
4.7K_0402_5%
GMCH_ENBKL 2
G
Wire-OR
+3VS
+3VS
0_0402_5%
NB_ALLOW_LDTSTOP
2
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
+1.8VS
C157
4.7U_0805_10V4Z
GMCH_ENVDD <23>
VARY_ENBKL
RS880 A11(SA000032710)
1.1V
1
2
<26> ALLOW_LDTSTOP
C156
0.1U_0402_16V4Z
+VDDLT18
+1.8VS
L10
1
2
BLM18AG601SN1D_2P
+VDDLT18
0.95V
R90
1K_0402_5%
R91
1
FBMA-L11-160808-221LMT 0603
C153
2.2U_0603_6.3V4Z
2
+VDDLTP18
300mA
1
1
GMCH_TXCLK+ <23>
GMCH_TXCLK- <23>
R73
MIS.
<23>
<23>
<23>
<23>
<23>
<23>
+VDDLTP18
1
+1.8VS
LOW
5
GMCH_TXOUT0+
GMCH_TXOUT0GMCH_TXOUT1+
GMCH_TXOUT2-
RS780M_FCBGA528
RS880
U3C
F12
E12
F14
G15
H15
H14
4NB_PWRGD_R
FBMA-L11-160808-221LMT 0603
C150
2.2U_0603_6.3V4Z
Check if needed?
2
0_0402_5%
+VDDA18HTPLL
4mA
U4
C147
1U_0402_6.3V4Z
AMD suggest
L6
+1.8VS
<8,27,36> SB_PWRGD
NB_LDTSTOP#
U8
2
1
4.7K_0402_5%
2
1
4.7K_0402_5%
+AVDDDI
125mA
R64
CRT/TVOUT
FBMA-L11-160808-221LMT 0603
C145
0.1U_0402_16V4Z
FBMA-L11-160808-221LMT 0603
C146
2.2U_0603_6.3V4Z
L4
+NB_HTPVDD
L5
1
<8,26> LDT_STOP#
2.2U_0603_6.3V4Z
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V4Z
+1.8VS
+1.8VS
C143
1
FBMA-L11-160808-221LMT 0603
C144
1
PLL PWR
LVTM
C679
1
PM
L3
C142
1U_0402_6.3V4Z
NB_PWRGD
+3VS
CLOCKs
+AVDD1
FBMA-L11-160808-221LMT 0603
C141
2.2U_0603_6.3V4Z
C684
+1.8VS
R63
2.2K_0402_5%
1
+NB_PLLVDD
L2
1
+1.8VS
2
1
4.7K_0402_5%
+1.1VS
R417
@
300_0402_5%
+1.8VS
0.1U_0402_16V4Z
1
2
5
+1.8VS
Rev
D
401827
Sheet

E
13
of
55
0.1U_0402_16V4Z
+VDDHT
1
C174
C177
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
1
C178
2
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
L15
2
1
FBMA-L11-201209-221LMA30T_0805
1
C181
4.7U_0805_10V4Z
C176
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE

1
C179
2
1
C192
1
C185
1
C190
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
700mA
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
1
C186
2
0.1U_0402_16V4Z
10mA
F9
G9
AE11
AD11
+1.8VS
C197
1U_0402_6.3V4Z
5mA
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
AE10
AA11
Y11
AD10
AB10
AC10
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
H11
H12
VDD33_1(NC)
VDD33_2(NC)
+NB_CORE
10A
23mA
1
+
2
330U_D2E_2.5VM
C175
C189
+1.8VS
C196
C184
@
C261
680mA
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX
10U_0603_6.3V6M
2
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
1
1
C172
C173
C195
L14
2
+1.1VS
FBMA-L11-201209-221LMA30T_0805
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
10U_0805_10V4Z
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
2 4.7U_0805_10V4Z
1
1
C183
H18
G19
F20
E21
D22
B23
A23
C168
C171
0.1U_0402_16V4Z
700mA
C161
C163
C188
C170
2 10U_0805_10V4Z
2 10U_0805_10V4Z
0.1U_0402_16V4Z
C169
+VDDHTRX
1
1
1
C180
C164
C160
C162
0.1U_0402_16V4Z
+VDDA11PCIE
C194
0.1U_0402_16V4Z
2.5A
0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
C193
1U_0402_6.3V4Z
PART 5/6
0.1U_0402_16V4Z
L13
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
C187
U3E
J17
K16
L16
M16
P16
R16
T16
+1.1VS
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
U3F
C182
2
4.7U_0805_10V4Z
C167
L28
1
2
FBMA-L11-201209-221LMA30T_0805
L12
1
2
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
C159
C191
C166
0.1U_0402_16V4Z
C165
600mA
0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805
1U_0402_6.3V4Z
POWER
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
60mA
RS880 A11(SA000032710)
C198
0.1U_0402_16V4Z
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
RS780M_FCBGA528
+3VS
1
RS780M_FCBGA528
PART 6/6
GROUND
L11
1.3A
+1.1VS
RS880 A11(SA000032710)
1
C199
0.1U_0402_16V4Z
U3D
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Debug Mode
2
R92
2
R93
1
3K_0402_5%
1
3K_0402_5%
Enables the Test Debug Bus using GPIO. (VSYNC)

1 : Disable
0 : Enable
+3VS
DFT_GPIO1: LOAD_EEPROM_STRAPS
Load EEPROM Strap

D1 @
CH751H-40PT_SOD323-2
2
1
<13> SUS_STAT_R#
2
R264 @
Selects Loading of STRAPS from EPROM

1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
A_RST# <13,26,36>
1
3K_0402_5%
Enable Side Port Memory
Enable Side Port Memory

4
2
R94
2
R95
1
3K_0402_5%
1
3K_0402_5%
RS880: HSYNC#
0:
Enable
1 : Disable
+3VS
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
AD16
AE17
AD17
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
W12
Y12
AD18
AB13
AB18
V14
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
V15
W14
MEM_CKP(NC)
MEM_CKN(NC)
AE12
AD12
Register Readback of strap:

NB_CLKCFG:CLK_TOP_SPARE_D[1]
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W18
AD20
AE21
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
W17
AE19
IOPLLVDD18(NC)
IOPLLVDD(NC)
AE23
AE24
IOPLLVSS(NC)
AD23
MEM_VREF(NC)
AE18
MEM_COMPP(NC)
MEM_COMPN(NC)
+1.8VS
+1.1VS
Compal Secret Data

2008/10/06
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Date:
26mA
RS880 A11(SA000032710)
Custom
A
15mA
RS780M_FCBGA528
Issued Date
SBD_MEM/DVO_I/F
Side port and Strap setting

PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
Rev
D
401827
Sheet

E
14
of
55
<12> PCIE_GTX_C_MRX_P[0..15]
<12> PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15] <12>
PCIE_MTX_C_GRX_N[0..15] <12>
add for VB support.

U5G
LVDS CONTROL
GFX PCIE LANE REVERSAL
R96
10K_0402_5%
1
2
VARY_BL
DIGON
AK27
AJ27
VGA_PNL_PWM <23>
VGA_ENVDD <23>
R97
1
2
10K_0402_5%
U5A
PCIE_MTX_C_GRX_P15 AA38
PCIE_MTX_C_GRX_N15 Y37
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_GTX_MRX_P14C202 1
PCIE_GTX_MRX_N14C203
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
W33
W32
W38
V37
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
U33
U32
V35
U36
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
U30
U29
Y35
W36
U38
T37
T35
R36
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_TX4P
PCIE_TX4N
PCI EXPRESS INTERFACE
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
2
1
VGA@
Y33
Y32
T33
T32
T30
T29
PCIE_TX6P
PCIE_TX6N
P33
P32
PCIE_GTX_MRX_P9 C212 1
PCIE_GTX_MRX_N9 C213
PCIE_TX7P
PCIE_TX7N
P30
P29
PCIE_TX8P
PCIE_TX8N
N33
N32
PCIE_TX9P
PCIE_TX9N
N30
N29
PCIE_TX10P
PCIE_TX10N
L33
L32
PCIE_TX11P
PCIE_TX11N
L30
L29
PCIE_TX12P
PCIE_TX12N
K33
K32
PCIE_TX5P
PCIE_TX5N
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
R38
P37
PCIE_RX6P
PCIE_RX6N
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
P35
N36
PCIE_RX7P
PCIE_RX7N
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
N38
M37
PCIE_RX8P
PCIE_RX8N
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
M35
L36
PCIE_RX9P
PCIE_RX9N
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
L38
K37
PCIE_RX10P
PCIE_RX10N
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
K35
J36
PCIE_RX11P
PCIE_RX11N
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
J38
H37
PCIE_RX12P
PCIE_RX12N
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
H35
G36
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
J33
J32
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
G38
F37
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
K30
K29
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
F35
E37
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
H33
H32
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
2
1
2
VGA@
VGA@
0.1U_0402_16V7K PCIE_GTX_C_MRX_P15
0.1U_0402_16V7K PCIE_GTX_C_MRX_N15
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
AK35
AL36
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
AJ38
AK37
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AH35
AJ36
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
AG38
AH37
TXOUT_U3P
TXOUT_U3N
AF35
AG36
LVTMDP
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AP34
AR34
VGA_TXCLK+
VGA_TXCLK-
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AW37
AU35
VGA_TXOUT0+
VGA_TXOUT0-
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AR37
AU39
VGA_TXOUT1+
VGA_TXOUT1-
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AP35
AR35
VGA_TXOUT2+
VGA_TXOUT2-
TXOUT_L3P
TXOUT_L3N
AN36
AP37
VGA_TXCLK+ <23>
VGA_TXCLK- <23>
VGA_TXOUT0+ <23>
VGA_TXOUT0- <23>
VGA_TXOUT1+ <23>
VGA_TXOUT1- <23>
C
VGA_TXOUT2+ <23>
VGA_TXOUT2- <23>
216-0729002 A12 M96_BGA962
MAD@
U5 PARK@
PARK XT-M2 A11
PARK A11 (SA00003MC10)
+3VSG
CLOCK
For M96, AH16 is NC

For Mahatten need PD
R99
1
VGA@ 10K_0402_5%
CALIBRATION
AJ21
AK21
AH16
AA30
NC#1
NC#2
NC_PWRGOOD
PCIE_CALRP
Y30
R98
PCIE_CALRN
Y29
R100 1 VGA@ 2
1 VGA@ 2
1.27K_0402_1%
2K_0402_1%
D45 RB751V_SOD323
1
2
VGA@
<26,32,34> PLT_RST#
R491
10K_0402_5%
VGA@
VGA_RST#
+1.0VSG
<26>
PE_GPIO0
PERSTB
1
VGA_RST#
PCIE_REFCLKP
PCIE_REFCLKN
<22> CLK_PEG_VGA
<22> CLK_PEG_VGA#
AB35
AA36
216-0729002 A12 M96_BGA962

MAD@
D44 RB751V_SOD323
SG@
R492
2.2K_0402_5%
@
Pop for PX verify
MAD A12 (SA00003M300)
+3VSG
A
Issued Date
Compal Secret Data
2009/7/14
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Rev
D
401827
Date:
Sheet

1
15
of
55
U5B
Setting
Transmitter Power Saving Enable

0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
GPIO0
TX_DEEMPH_EN
D
BIOS_ROM_EN
GPIO22
AUD[1]
AUD(0)
GPIO13,12,11 (config 2,1,0) :

memory apertures
a) If BIOS_ROM_EN = 1, then Config[2:0] defines CONFIG[3:0]
the ROM type.
128 MB 000
b) If BIOS_ROM_EN = 0, then Config[2:0] defines 256 MB 001 *
64 MB 010
the primary memory aperture size.
GPIO13
GPIO12
GPIO11
CONFIG[2]
CONFIG[1]
CONFIG[0]
PCI Express Transmitter De-emphasis Enable

0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)
GPIO1
Enable external BIOS ROM device

0: Diable, 1: Enable
BIF_GEN2_EN
GPIO2
RESERVED
H2SYNC
GPIO8
GPIO21
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
NC on Park
VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
001
00: No audio function;

10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on
5.0 GT/s capability will be controlled by software
HSYNC
VSYNC
DPA
11
Internal use only. THIS PAD HAS AN INTERNAL

PULL-DOWN AND MUST BE 0 V AT RESET. The
pad may be left unconnected
NC on Park
+3VSG
VGA@ R104 1
VGA@ R107 1
@ R109 1
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
@ R110 1
2 10K_0402_5%
VGA_AC_DET
@ R111 1
2 10K_0402_5%
SOUT_GPIO8
@ R113 1
2 10K_0402_5%
VGA@ R115
@ R116
@ R117
@ R118
@ R119
1
1
1
1
1
1 VGA@
1 VGA@
<vendor1>
Samsung
<pcs> 64MX16
VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
Hynix(128MbX16)
<4 pcs>
<4 pcs>
<4 pcs>
O
O
<51>
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
GPU_VID0
GPU_VID0
T11
THM_ALERT#
<51>
Location
VGA_ENBKL
SOUT_GPIO8
SIN_GPIO9
2
1
R120
VGA@
10K_0402_5%
GPU_VID1
GPU_VID1
ROMSE_GPIO22
Hynix
AMD
<8 pcs>
<8 pcs>
<8 pcs>
T14
TCK
TMS
T17
GENERICC
AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF
GENERICG
AK24
HPD1
DAC1
2
VGA@
GPU_THERM_D+
GPU_THERM_D-
2
1
2
1
2
2
1
2
1
2
1
2
For VGA boot unstable issue

A
VGA@
XTALOUT
27MCLK
VGA@
1
2
VGA@
27MHZ_16PF_X5H027000FG1H
C262
VGA@
18P_0402_50V8J
2
VGA@
2
VGA@
C260
0.1U_0402_16V4Z
Y1
AF29
AG29
20mA
+TSVDD
C259
1U_0402_6.3V4Z
R148
+1.8VSG L23
BLM18AG121SN1D_0603
2
1
VGA@
1
C258
10U_0603_6.3V6M
1M_0603_5%
27MCLK
AV33
XTALOUT AU34
AK32
AJ32
AJ33
TX2P_DPC0P
TX2M_DPC0N
AT17
AR16
TXCDP_DPD3P
TXCDM_DPD3N
AU20
AT19
TX3P_DPD2P
TX3M_DPD2N
AT21
AR20
TX4P_DPD1P
TX4M_DPD1N
AU22
AV21
TX5P_DPD0P
TX5M_DPD0N
AT23
AR22
R
RB
AD39
AD37
VGA_CRT_R <25>
G
GB
AE36
AD35
VGA_CRT_G <25>
B
BB
AF37
AE38
VGA_CRT_B <25>
HSYNC
VSYNC
AC36
AC38
D-
ALERT#
GND
R597
0_0402_5%
THERM#
PLL/CLOCK
DPLL_PVDD
DPLL_PVSS
VGA_SMB_CK2
1
2
R101
4.7K_0402_5%
VGA@
+3VSG
EC_SMB_CK2
EC_SMB_CK2 <8,36>
Q5B VGA@
DMN66D0LDW-7_SOT363-6
EC_SMB_DA2
6
VGA@
1
Q5A
EC_SMB_DA2 <8,36>
NC on Park
1 VGA@
RSET
AB34
AD34
AE34
+AVDD
VDD1DI
VSS1DI
AC33
AC34
+VDD1DI
R2
R2B
AC30
AC31
G2
G2B
AD30
AD31
B2
B2B
AF30
AF31
C
Y
COMP
AC32
AD32
AF32
H2SYNC
V2SYNC
AD29
AC29
H2SYNC
V2SYNC
VDD2DI
VSS2DI
AG31
AG32
+VDD2DI
A2VDD
AG33
+A2VDD
AD33
+A2VDDQ
AF33
R2SET
AA29
DDC1CLK
DDC1DATA
AM26
AN26
AM27
AL27
DDC2CLK
DDC2DATA
AUX2P
AUX2N
AN20
AM20
DDCCLK_AUX3P
DDCDATA_AUX3N
AL30
AM30
DDCCLK_AUX4P
DDCDATA_AUX4N
AL29
AM29
DDCCLK_AUX5P
DDCDATA_AUX5N
AN21
AM21
XTALIN
XTALOUT
THERMAL
A2VSSQ
AM19
AL19
DPLL_VDDC
DPLUS
DMINUS
VGA_CRT_HSYNC
VGA_CRT_VSYNC
R122
TS_FDO
TSVDD
TSVSS
DDC6CLK
DDC6DATA
AJ30
AJ31
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N
AK30
AK29
216-0729002 A12 M96_BGA962

MAD@
<25>
<25>
499_0402_1%
70mA
45mA
2
VGA@
50mA
2
VGA@
2
VGA@
2
VGA@
130mA
20mA
2
VGA@
VGA_HDMI_SCLK
VGA_HDMI_SDATA
2
VGA@
2
VGA@
2
VGA@
R140
715_0402_1%
1
2
VGA@
2
VGA@
2
VGA@
2
VGA@
L16
BLM18AG121SN1D_0603
1
+1.8VSG
VGA@
ACIN_BUF
ACIN
ACIN
<36,37,42,43>
1
2
R127
0_0402_5%
VGA@
B
+3VSG
Y
@
Check If needed?
U7
L19
BLM18AG121SN1D_0603
1
+3VSG
VGA@
V2SYNC
H2SYNC
Strap
@ R132 1
@ R134 1
2 10K_0402_5%
2 10K_0402_5%
VGA_CRT_VSYNC
VGA_CRT_HSYNC
VGA@ R136 1
VGA@ R137 1
2 10K_0402_5%
2 10K_0402_5%
VGA_HDMI_SCLK
VGA_HDMI_SDATA
VGA_CRT_CLK
VGA_CRT_DATA
VGA@ R138
VGA@ R139
VGA@ R141
VGA@ R142
2
2
2
2
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
1
1
1
1
VGA@ R143 1
VGA@ R144 1
VGA@ R145 1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2 150_0402_1%
2 150_0402_1%
2 150_0402_1%
BLM18AG121SN1D_0603
1
+1.8VSG
L22 VGA@
VGA@
NC on Park
VGA_CRT_CLK
VGA_CRT_DATA
VGA_CRT_CLK <25>
VGA_CRT_DATA <25>
FLASH ROM
CRT
Compal Secret Data

2009/7/14
A 1-Mbit serial EEPROM is

required on GDDR5 designs
DDR3 can be removed
NC on Park
Deciphered Date
2010/03/12
Title
Size
C
Date:
L18
BLM18AG121SN1D_0603
2
1
+1.8VSG
VGA@
HDMI
VGA@
1
+3VALW
L17
BLM18AG121SN1D_0603
1
+1.8VSG
VGA@
2
VGA@
VGA_HDMI_SCLK <24>
VGA_HDMI_SDATA <24>
VGA@
Issued Date
THM_ALERT#
VGA@
R103
4.7K_0402_5%
VGA@
VGA_SMB_DA2
AVDD
AVSSQ
AUX1P
AUX1N
C263
VGA@
18P_0402_50V8J
VGA_SMB_DA2
+3VSG
C257
10U_0603_6.3V6M
2
VGA@
AU16
AV15
R102
4.7K_0402_5%
VGA@
C248
10U_0603_6.3V6M
TX1P_DPC1P
TX1M_DPC1N
A2VDDQ
150mA
AN31
AT15
AR14
+3VSG
C255
0.1U_0402_16V4Z
<17>
+DPLL_VDDC
AM32
AN32
TX0P_DPC2P
TX0M_DPC2N
VREFG
DDC/AUX
120mA
AU14
AV13
SDATA
ADM1032ARMZ-2REEL_MSOP8
C254
1U_0402_6.3V4Z
TESTEN
2
VGA@
C256
1U_0402_6.3V4Z
TESTEN
2
VGA@
2
VGA@
C251
1U_0402_6.3V4Z
TCK
C250
0.1U_0402_16V4Z
+1.0VSG
L21
BLM18AG121SN1D_0603
2
1
VGA@
1
TXCCP_DPC3P
TXCCM_DPC3N
SCLK
D+
Address 1001 101X b
DAC2
+DPLL_PVDD
C253
0.1U_0402_16V4Z
TMS
C252
10U_0603_6.3V6M
TRSTB
1VGAOPT@ 2
R420
10K_0402_5%
2
VGA@
+VGA_VREF AH13
2 VGA@
0.1U_0402_16V4Z
1
C245
AT33
AU32
VGA_SMB_CK2
VDD
C244
10U_0603_6.3V6M
2 249_0402_1%
AR32
AT31
TX5P_DPB0P
TX5M_DPB0N
C247
0.1U_0402_16V4Z
2 499_0402_1%
1 VGA@
TX4P_DPB1P
TX4M_DPB1N
C243
0.1U_0402_16V4Z
1 VGA@
R135
+1.8VSG L20
BLM18AG121SN1D_0603
2
1
VGA@
1
1VGAOPT@ 2
R147
10K_0402_5%
1VGAOPT@ 2
R421
10K_0402_5%
R133
PD-Reset
27M_NSSC
+3VSG
+1.8VSG
Internal PD
C249
10U_0603_6.3V6M
VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
AV31
AU30
U6 VGA@
1
Not share via for other GND
R131
10K_0402_5%
R126
10K_0402_5%
R130
10K_0402_5%
R129
10K_0402_5%
R128
10K_0402_5%
<22>
R125
10K_0402_5%
+3VSG
R124
10K_0402_5%
R123
10K_0402_5%
@
VGA_HDMI_DET
TX3P_DPB2P
TX3M_DPB2N
SCL
SDA
<24,27> VGA_HDMI_DET
AR30
AT29
C246
1U_0402_6.3V4Z
Park NC pins
+1.8VSG
TXCBP_DPB3P
TXCBM_DPB3N
GPU_THERM_D+
2200P_0402_50V7K
VGA@ 1
2
C233
GPU_THERM_D-
C242
1U_0402_6.3V4Z
<8 pcs>
VGA_HDMI_TXD2+ <24>
VGA_HDMI_TXD2- <24>
C241
10U_0603_6.3V6M
Samsung
Hynix(128MbX16)
TRSTB
<size> 64MX16
AT27
AR26
C239
0.1U_0402_16V4Z
<vandor>
T12
TX2P_DPA0P
TX2M_DPA0N
1
C232
VGA@
C240
1U_0402_6.3V4Z
VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0
VRAM
VGA_AC_DET
<13> VGA_ENBKL
TX1P_DPA1P
TX1M_DPA1N
VGA_HDMI_TXD1+ <24>
VGA_HDMI_TXD1- <24>
C238
22U_0805_6.3V6M
AK26
AJ26
VGA_HDMI_TXD0+ <24>
VGA_HDMI_TXD0- <24>
AU26
AV25
C237
0.1U_0402_16V4Z
AMD
I2C
GENERAL PURPOSE I/O
<size>
DPC
AT25
AR24
C236
1U_0402_6.3V4Z
Hynix
<vendor2>
<4 pcs>
2 4.7K_0402_5%
2 4.7K_0402_5%
VGA_LCD_CLK
VGA_LCD_DAT
<23> VGA_LCD_CLK
<23> VGA_LCD_DAT
VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0
VRAM
Madsion
(Pro)
R105
R108
SIN_GPIO9
DPB
DPD
ACIN_BUF
1
2
D2
@
Location
Park
(XT)
+3VSG
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
ROMSE_GPIO22
GENERICC
10K_0402_5%
10K_0402_5%
10K_0402_5%
3K_0402_5%
10K_0402_5%
2
2
2
2
2
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
TX0P_DPA2P
TX0M_DPA2N
TX_PWRS_ENB
MUTI GFX
+3VSG
VGA Disable determines

0: VGA Controller capacity enabled
1: The device will not be recognized as the systems VGA controller
VGA_HDMI_TXC+ <24>
VGA_HDMI_TXC- <24>
GPIO9
AU24
AV23
VGA_DIS
External VGA Thermal Sensor

TXCAP_DPA3P
TXCAM_DPA3N
VIP Device Strap Enable indicates to the software driver

0: Driver would ignore the value sampled on VHAD_0 during reset
1: VHAD_0 to determine whether or not a VIP slave device
V2SYNC
0.1U_0402_16V4Z
VIP_DEVICE_EN
Pin Straps description <all internal PD>
Strap Name
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
1
Sheet
16
of
55
Park only support single channel

memory (channel B only)
U5D
U5C
CLKA0
CLKA0B
H27
G27
CLKA0
CLKA0#
CLKA1
CLKA1B
J14
H14
CLKA1
CLKA1#
RASA0B
RASA1B
K23
K19
RASA0#
RASA1#
CASA0B
CASA1B
K20
K17
CASA0#
CASA1#
CSA0B_0
CSA0B_1
K24
K27
CSA0#_0
CSA1B_0
CSA1B_1
M13
K16
CSA1#_0
MVREFDA
MVREFSA
CKEA0
CKEA1
K21
J20
CKEA0
CKEA1
NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2
WEA0B
WEA1B
MEM_CALRP1
NC_MEM_CALRP0
NC_MEM_CALRP2
VGA@
RSVD#1
RSVD#2
RSVD#3
RSVD#5
RSVD#6
H23
J19
RSVD#9
RSVD#11
T8
W8
216-0729002 A12 M96_BGA962

MAD@
If use M96 upper resistor will

change to 100ohm for
MVREFDA/B and MVREFSA/B
Mahatten upper resistor use 40.2ohm
WEA0#
WEA1#
K26
L15
AF28
AG28
AL31
GCORE_SEN
+1.5VSG
ODTA0
ODTA1
<20>
<20>
CLKA0
CLKA0#
<20>
<20>
CLKA1
CLKA1#
<20>
<20>
RASA0#
RASA1#
<20>
<20>
CASA0#
CASA1#
<20>
<20>
CSA0#_0
<20>
CSA1#_0
<20>
CKEA0
CKEA1
<20>
<20>
WEA0#
WEA1#
<20>
<20>
R151
VGA@
40.2_0402_1%
MVREFDB
R153
VGA@
100_0402_1%
C265
VGA@
+1.5VSG
MVREFDB Y12
MVREFSB AA12
R156
VGA@
40.2_0402_1%
GCORE_SEN <51>
<16>
MAA13
MAB13
<20>
R165
VGA@
100_0402_1%
<21>
M96 no support
In M97, Medison and Park, AF28 is

FB_VDDC, AG28 is FB_VDDCI, AH29 is
FB_GND. GCORE_SEN and FB_GND
should route as differential pair Same
as VDDCI_SEN and FB_GND
C267
VGA@
If use M96 upper resistor will

change to 100ohm for
MVREFDA/B and MVREFSA/B
Mahatten upper resistor use
40.2ohm
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1
DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
DQMB_7
H3
H1
T3
T5
AE4
AF5
AK6
AK5
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB_0/RDQSB_0
QSB_1/RDQSB_1
QSB_2/RDQSB_2
QSB_3/RDQSB_3
QSB_4/RDQSB_4
QSB_5/RDQSB_5
QSB_6/RDQSB_6
QSB_7/RDQSB_7
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
ODTB0
ODTB1
T7
W7
ODTB0
ODTB1
CLKB0
CLKB0B
L9
L8
CLKB0
CLKB0#
CLKB1
CLKB1B
AD8
AD7
CLKB1
CLKB1#
RASB0B
RASB1B
T10
Y10
RASB0#
RASB1#
CASB0B
CASB1B
W10
AA10
CASB0#
CASB1#
CSB0B_0
CSB0B_1
P10
L10
CSB0#_0
CSB1B_0
CSB1B_1
AD10
AC10
CSB1#_0
CKEB0
CKEB1
U10
AA11
CKEB0
CKEB1
WEB0B
WEB1B
N10
AB11
WEB0#
WEB1#
QSB_0B/WDQSB_0
QSB_1B/WDQSB_1
QSB_2B/WDQSB_2
QSB_3B/WDQSB_3
QSB_4B/WDQSB_4
QSB_5B/WDQSB_5
QSB_6B/WDQSB_6
QSB_7B/WDQSB_7
MVREFDB
MVREFSB
TESTEN
MVREFSB
1
TESTEN
2
10K_0402_5%
TEST_MCLK
TEST_YCLK
1
R161
AD28
TESTEN
AK10
AL10
CLKTESTA
CLKTESTB
DRAM_RST
B_BA[0..2]
DQMB#[0..7] <21>
QSB[0..7]
QSB[0..7]
<21>
QSB#[0..7]
QSB#[0..7] <21>
ODTB0
ODTB1
<21>
<21>
CLKB0
CLKB0#
<21>
<21>
CLKB1
CLKB1#
<21>
<21>
RASB0#
RASB1#
<21>
<21>
CASB0#
CASB1#
<21>
<21>
CSB0#_0
<21>
CSB1#_0
<21>
CKEB0
CKEB1
<21>
<21>
WEB0#
WEB1#
<21>
<21>
R163
@ 4.7K_0402_5%
1
2
R166 VGA@
51.1_0402_1%
1
2
AH11
1 C270
VGA@
216-0729002 A12 M96_BGA962
MAD@
B_BA[0..2] <21>
DQMB#[0..7]
+1.5VSG
VRAM_RST# <20,21>
R168
VGA@
68P_0402_50V8J 10K_0402_5%
Modify for ATI suggestion

R169
VGA@
51.1_0402_1%
R170
VGA@
51.1_0402_1%
M96
M96 use 4.7K to

PD directly.
R166
R163
C270
2009/7/14
10k Ohm
SD028100280
680 Ohm
SD028680080
2010/03/12
Deciphered Date
68 pF
SE071680J80
Title
Custom
SCHEMATIC, MB A5911
Rev
D
401827
Date:
DNI
Compal Secret Data
Broadway
4.7k Ohm
SD028470180
0 Ohm
SD028000080
4.7k Ohm
SD028470180
1000 pF
SE074102K80
R168
Issued Date
MAB[0..12] <21>
D
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13/BA2
MAB_14/BA0
MAB_15/BA1
ODTA0
ODTA1
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
2
1
J21
G19
QSA#[0..7] <20>
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
C269 VGA@
0.1U_0402_16V4Z
ODTA0
ODTA1
QSA#[0..7]
<20>
C268 VGA@
0.1U_0402_16V4Z
C266
0.1U_0402_16V4Z
R167
VGA@
100_0402_1%
A34
E30
E26
C20
C16
C12
J11
F8
QSA[0..7]
0.1U_0402_16V4Z
R160
R162
R164
MVREFSA
QSA_0B/WDQSA_0
QSA_1B/WDQSA_1
QSA_2B/WDQSA_2
QSA_3B/WDQSA_3
QSA_4B/WDQSA_4
QSA_5B/WDQSA_5
QSA_6B/WDQSA_6
QSA_7B/WDQSA_7
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
QSA[0..7]
L18
L20
L27
1 VGA@ 2
1 VGA@ 2 240_0402_1% N12
1 VGA@ 2 240_0402_1% AG12
240_0402_1%
M12
1 VGA@ 2
1 VGA@ 2 240_0402_1% M27
1 VGA@ 2 240_0402_1% AH12
240_0402_1%
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
R155
R158
R159
R157
VGA@
40.2_0402_1%
C34
D29
D25
E20
E16
E12
J10
D7
DQMA#[0..7] <20>
+1.5VSG
QSA_0/RDQSA_0
QSA_1/RDQSA_1
QSA_2/RDQSA_2
QSA_3/RDQSA_3
QSA_4/RDQSA_4
QSA_5/RDQSA_5
QSA_6/RDQSA_6
QSA_7/RDQSA_7
DQMA#[0..7]
A_BA[0..2] <20>
+1.5VSG
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
MVREFDA
MVREFSA
A32
C32
D23
E22
C14
A14
E10
D9
A_BA[0..2]
MDB[0..63]
VGA@
DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7
MAB[0..12]
<21>
C264
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1
0.1U_0402_16V4Z
R154
VGA@
100_0402_1%
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
2
1
MVREFDA
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1
0.1U_0402_16V4Z
R152
VGA@
40.2_0402_1%
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
+1.5VSG
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
MDB[0..63]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MDA[0..63]
MEMORY INTERFACE A
<20>
MAA[0..12] <20>
MEMORY INTERFACE B
MAA[0..12]
MDA[0..63]
Sheet

1
17
of
55
U5E
+1.5VSG
L24
VGA@
C304 VGA@
10U_0805_6.3V6M
C303 VGA@
1U_0402_6.3V4Z
+VGA_CORE
C335 VGA@
1U_0402_6.3V4Z
C325 VGA@
1U_0402_6.3V4Z
C334 VGA@
1U_0402_6.3V4Z
C333 VGA@
1U_0402_6.3V4Z
C324 VGA@
1U_0402_6.3V4Z
C323 VGA@
1U_0402_6.3V4Z
C332 VGA@
1U_0402_6.3V4Z
C322 VGA@
1U_0402_6.3V4Z
C331 VGA@
1U_0402_6.3V4Z
C321 VGA@
1U_0402_6.3V4Z
VGA@
2
1
R569
0_0603_5%
C339 VGA@
10U_0805_6.3V6M
C346 VGA@
10U_0805_6.3V6M
+ C347
+ C693
C340
VGA@
VGA@
@
330U_D2_2V_Y 330U_D2_2V_Y
330U_D2_2V_Y
2
2
2
Reserve for PWR test
+VGA_CORE
BIF_VDDCI (T27,N27) need

isolate VGA_CORE
*Confirm with AMD
M97 and Mahattan VDDC and

VDDCI ball assignments are
different from M96, If M96 is
populated on this
design,VDDC and VDDCI
shoudl be shorted.
2
1
FBMA-L11-201209-221LMA30T_0805
L96
VGA@
2
1
FBMA-L11-201209-221LMA30T_0805
L97
VGA@
C376 VGA@
1U_0402_6.3V4Z
C375 VGA@
1U_0402_6.3V4Z
C374 VGA@
1U_0402_6.3V4Z
+VDDCI
1
C373 VGA@
1U_0402_6.3V4Z
5A
C372 VGA@
1U_0402_6.3V4Z
C371 VGA@
1U_0402_6.3V4Z
C370 VGA@
1U_0402_6.3V4Z
2009/7/14
C289 VGA@
10U_0805_6.3V6M
+VGA_CORE
Confirm ATI, for

Mahattan, it could be
connected to VGA_CORE
Compal Secret Data
Issued Date
C288 VGA@
1U_0402_6.3V4Z
2
216-0729002 A12 M96_BGA962
MAD@
C384 VGA@
10U_0805_6.3V6M
M15
N13
R12
T12
C383 VGA@
10U_0805_6.3V6M
ISOLATED VDDCI#1
CORE I/O VDDCI#2
VDDCI#3
VDDCI#4
C382 VGA@
10U_0805_6.3V6M
C381 VGA@
0.1U_0402_16V4Z
C380 VGA@
1U_0402_6.3V4Z
BBP#1
BBP#2
C345 VGA@
10U_0805_6.3V6M
AA13
Y13
C369 VGA@
1U_0402_6.3V4Z
32mA
1
C330 VGA@
1U_0402_6.3V4Z
SPVSS
C320 VGA@
1U_0402_6.3V4Z
SPV10
AN10
C302 VGA@
1U_0402_6.3V4Z
NC_SPV18
AN9
BACK BIAS
SPV18 For
Mahattan only
NC_MPV18#1
NC_MPV18#2
C368 VGA@
1U_0402_6.3V4Z
AM10
136mA
PCIE_PVDD
34.6A
C367 VGA@
1U_0402_6.3V4Z
50mA
C365 VGA@
0.1U_0402_16V4Z
C364 VGA@
1U_0402_6.3V4Z
C379 VGA@
0.1U_0402_16V4Z
C378 VGA@
1U_0402_6.3V4Z
C377 VGA@
10U_0603_6.3V6M
For M96 SPV10=+GPU_CORE

For M97,Nahattan SPV10=+1.0VS
+SPV10
C366 VGA@
10U_0603_6.3V6M
+1.8VSG
BLM18AG121SN1D_0603
2
1
L35
VGA@
1
1
2
1
L34
VGA@
BLM18AG121SN1D_0603 1
150mA
H7
H8
C287 VGA@
1U_0402_6.3V4Z
+MPV_18
PLL
AB37
C344 VGA@
10U_0805_6.3V6M
68mA
+PCIE_PVDD
+SPV_18
+1.0VSG
VDDRHB
VSSRHB
For M96 only,

Manhattan are NC pin
C329 VGA@
1U_0402_6.3V4Z
V12
U12
C319 VGA@
1U_0402_6.3V4Z
AA15
AA17
AA20
AA22
AA24
AA27
AB13
AB16
AB18
AB21
AB23
AB26
AB28
AC12
AC15
AC17
AC20
AC22
AC24
AC27
AD13
AD16
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
M16
M18
M23
M26
N15
N17
N20
N22
N24
N27
R13
R16
R18
R21
R23
R26
T15
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V15
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AH27
AH28
C272 VGA@
1U_0402_6.3V4Z
VDDRHA
VSSRHA
MEM CLK
C358 VGA@
0.1U_0402_16V4Z
C357 VGA@
1U_0402_6.3V4Z
C363 VGA@
0.1U_0402_16V4Z
C362 VGA@
1U_0402_6.3V4Z
C361 VGA@
0.1U_0402_16V4Z
C360 VGA@
1U_0402_6.3V4Z
C359 VGA@
10U_0603_6.3V6M
MPV18 For
Mahattan only
C356 VGA@
10U_0603_6.3V6M
2
BLM18AG121SN1D_0603
2
1
L32
VGA@
1
1
+1.8VSG
C286 VGA@
1U_0402_6.3V4Z
M20
M21
+1.8VSG
C301 VGA@
1U_0402_6.3V4Z
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#4
C285 VGA@
1U_0402_6.3V4Z
2
1
L31 VGA@
BLM18AG121SN1D_0603
1
AD12
AF11
AF12
AG11
C343 VGA@
10U_0805_6.3V6M
170mA
C328 VGA@
1U_0402_6.3V4Z
VDDR5#1
VDDR5#2
VDDR5#3
VDDR5#4
C318 VGA@
1U_0402_6.3V4Z
AF13
AF15
AG13
AG15
+1.0VSG
C300 VGA@
1U_0402_6.3V4Z
170mA
+VDDR4_5
C284 VGA@
1U_0402_6.3V4Z
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
C342 VGA@
10U_0805_6.3V6M
AF23
AF24
AG23
AG24
C327 VGA@
1U_0402_6.3V4Z
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
I/O
60mA
+VDDR3
LEVEL
TRANSLATION
2A
C341 VGA@
10U_0805_6.3V6M
AF26
AF27
AG26
AG27
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
VDDC#59
VDDC#60
VDDC#61
VDDC#62
VDDC#63
VDDC#64
VDDC#65
VDDC#66
VDDC#67
VDDC#68
VDDC#69
VDDC#70
VDDC#71
VDDC#72
VDDC#73
VDDC#74
C317 VGA@
1U_0402_6.3V4Z
136mA
CORE
C299 VGA@
1U_0402_6.3V4Z
+VDD_CT
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
BLM18AG601SN1D_2P
2
1
+1.8VSG
+PCIE_VDDR
C283 VGA@
0.1U_0402_16V4Z
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
400mA
C326 VGA@
1U_0402_6.3V4Z
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
C316 VGA@
1U_0402_6.3V4Z
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
C298 VGA@
1U_0402_6.3V4Z
PCIE
C282 VGA@
0.1U_0402_16V4Z
C350 VGA@
0.1U_0402_16V4Z
C349 VGA@
1U_0402_6.3V4Z
C348 VGA@
10U_0603_6.3V6M
BLM18AG601SN1D_2P 1
MEM I/O
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34
POWER
+1.8VSG
VGA@
1
C338 VGA@
0.1U_0402_16V4Z
L27
2
C315 VGA@
0.1U_0402_16V4Z
C312 VGA@
1U_0402_6.3V4Z
C337 VGA@
1U_0402_6.3V4Z
C336 VGA@
10U_0603_6.3V6M
2
1
L26
VGA@
BLM18AG121SN1D_0603
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
C297VGA@
1U_0402_6.3V4Z
+3VSG
2900mA
TBD AC7
C281 VGA@
1U_0402_6.3V4Z
C314 VGA@
1U_0402_6.3V4Z
C311 VGA@
1U_0402_6.3V4Z
C296VGA@
1U_0402_6.3V4Z
C313 VGA@
10U_0603_6.3V6M
2
1
L25
VGA@
BLM18AG121SN1D_0603
C280 VGA@
1U_0402_6.3V4Z
C310 VGA@
1U_0402_6.3V4Z
C295VGA@
1U_0402_6.3V4Z
C273 VGA@
1U_0402_6.3V4Z
C309 VGA@
10U_0805_6.3V6M
C279 VGA@
1U_0402_6.3V4Z
C294VGA@
1U_0402_6.3V4Z
C278 VGA@
1U_0402_6.3V4Z
C293VGA@
1U_0402_6.3V4Z
C277 VGA@
1U_0402_6.3V4Z
C308 VGA@
10U_0805_6.3V6M
+1.8VSG
C292VGA@
1U_0402_6.3V4Z
C307 VGA@
10U_0805_6.3V6M
C306 VGA@
10U_0603_6.3V6M
C305 MAD@
10U_0603_6.3V6M
C291VGA@
1U_0402_6.3V4Z
C290VGA@
1U_0402_6.3V4Z
C276 VGA@
1U_0402_6.3V4Z
C271 VGA@
1U_0402_6.3V4Z
+
C274
VGA@
330U_D2_2V_Y
2
C275 VGA@
1U_0402_6.3V4Z
2010/03/12
Deciphered Date
Title
Custom
SCHEMATIC, MB A5911
Rev
D
401827
Date:
Sheet

1
18
of
55
U5F
+1.8VSG
+DPD_VDD18
AP14
AP15
AP31
AP32
DPC_VSSR#1
DPC_VSSR#2
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5
DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
AN27
AP27
AP28
AW24
AW26
NC_DPB_VDD18#1
NC_DPB_VDD18#2
AP25
AP26
DPB_VDD10#1
DPB_VDD10#2
AN33
AP33
130mA
NC_DPD_VDD18#1
NC_DPD_VDD18#2
DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5
AN29
AP29
AP30
AW30
AW32
AW18
DPCD_CALR
DPAB_CALR
AW28
DP PLL POWER
DPA_PVDD
DPA_PVSS
AU28
AV27
2
0_0402_5%
DPE_VDD10#1
DPE_VDD10#2
DPB_PVDD
DPB_PVSS
AV29
AR28
AN34
AP39
AR39
AU37
AW35
DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5
DPC_PVDD
DPC_PVSS
AU18
AV17
AF34
AG34
DPD_PVDD
DPD_PVSS
1
2
+DPD_PVDD
20mA
DPF_VDD18#1
DPF_VDD18#2
DPE_PVDD
DPE_PVSS
AM37
AN38
20mA
DPF_VDD10#1
DPF_VDD10#2
AL38
AM35
1
+DPF_PVDD
2
DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5
1
1 AM39
DPEF_CALR
2
2009/7/14
L46
VGA@
BLM18AG121SN1D_0603
2
1
+1.8VSG
L48
VGA@
BLM18AG121SN1D_0603
2
1
+1.8VSG
L49
VGA@
BLM18AG121SN1D_0603
2
1
+1.8VSG
L51
VGA@
BLM18AG121SN1D_0603
2
1
+1.8VSG
L53
VGA@
BLM18AG121SN1D_0603
2
1
+1.8VSG
C438
VGA@
10U_0603_6.3V6M
Issued Date
2010/03/12
Deciphered Date
For M96 are NC pins

A
Title
Custom
216-0729002 A12 M96_BGA962
+1.8VSG
Compal Secret Data
C437
VGA@
1U_0402_6.3V4Z
C436
VGA@
0.1U_0402_16V4Z
A39
AW1
AW39
L44
VGA@
BLM18AG121SN1D_0603
2
1
C432
VGA@
10U_0603_6.3V6M
R179
2
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
C431
VGA@
1U_0402_6.3V4Z
+DPE_PVDD
C435 VGA@
1U_0402_6.3V4Z
+1.0VSG
C426
VGA@
10U_0603_6.3V6M
AF39
AH39
AK39
AL34
AM34
AV19
AR18
216-0729002 A12 M96_BGA962

MAD@
1
C425
VGA@
1U_0402_6.3V4Z
AK33
AK34
150_0402_1%
C434 VGA@
0.1U_0402_16V4Z
C433 VGA@
10U_0603_6.3V6M
+DPC_PVDD
C430
VGA@
0.1U_0402_16V4Z
L52
VGA@
BLM18AG121SN1D_0603
2
1
+1.0VSG
C429 VGA@
1U_0402_6.3V4Z
+DPB_PVDD
20mA
NC_DPF_PVDD
NC_DPF_PVSS
C428 VGA@
0.1U_0402_16V4Z
C427 VGA@
10U_0603_6.3V6M
C424
VGA@
0.1U_0402_16V4Z
L50
VGA@
BLM18AG121SN1D_0603
2
1
1
+1.8VSG
C423
VGA@
10U_0603_6.3V6M
@
1
R177
+DPF_VDD10
+DPA_PVDD
20mA
AL33
AM33
120mA
R176
150_0402_1%
2
SCHEMATIC, MB A5911
Rev
D
401827
MAD@
Date:
For M96 are NC pins
L43
VGA@
BLM18AG121SN1D_0603
2
1
20mA
+DPF_VDD18
+1.8VSG
20mA
DP E/F POWER
DPE_VDD18#1
DPE_VDD18#2
200mA
R178
0_0402_5%
C422
VGA@
1U_0402_6.3V4Z
2
+DPB_VDD10
C421
VGA@
0.1U_0402_16V4Z
C420 VGA@
1U_0402_6.3V4Z
Ball AW34 and AW35

are GND ball in M96,
but have another ball
name in Broadway,
that is XO_IN and
X0_IN2.
C419 VGA@
0.1U_0402_16V4Z
C418 VGA@
10U_0603_6.3V6M
C417
VGA@
10U_0603_6.3V6M
DPD_VSSR#1
DPD_VSSR#2
DPD_VSSR#3
DPD_VSSR#4
DPD_VSSR#5
120mA
+DPE_VDD10
+DPB_VDD18
200mA
DPD_VDD10#1
DPD_VDD10#2
AN19
AP18
AP19
AW20
AW22
AH34
AJ34
C416
VGA@
1U_0402_6.3V4Z
L47
VGA@
BLM18AG121SN1D_0603
2
1
C415
VGA@
0.1U_0402_16V4Z
+DPE_VDD18
+DPA_VDD10
C414
VGA@
10U_0603_6.3V6M
R175
150_0402_1%
2
1
L41
VGA@
BLM18AG121SN1D_0603
2
1
C413
VGA@
1U_0402_6.3V4Z
DPA_VDD10#1
DPA_VDD10#2
200mA
+DPD_VDD10
L38
VGA@
BLM18AG121SN1D_0603
1
+1.0VSG
C408
VGA@
10U_0603_6.3V6M
DPC_VDD10#1
DPC_VDD10#2
130mA
AP22
AP23
200mA
200mA
+1.8VSG
For M96 are NC pins
C402
VGA@
10U_0603_6.3V6M
AN17
AP16
AP17
AW14
AW16
+DPA_VDD18
C407
VGA@
1U_0402_6.3V4Z
For PX, leave NC when

SBIOS control PWR on/off
+1.0VSG
C397
VGA@
10U_0603_6.3V6M
AP13
AT13
130mA
AN24
AP24
C412
VGA@
0.1U_0402_16V4Z
C411
VGA@
1U_0402_6.3V4Z
C410
VGA@
0.1U_0402_16V4Z
C409
VGA@
10U_0603_6.3V6M
1
VGA@
R174
0_0402_5%
NC_DPA_VDD18#1
NC_DPA_VDD18#2
200mA
L45
VGA@
BLM18AG121SN1D_0603
2
1
FB_GND
NC_DPC_VDD18#1
NC_DPC_VDD18#2
C401
VGA@
1U_0402_6.3V4Z
AP20
AP21
DP A/B POWER
C406
VGA@
0.1U_0402_16V4Z
C405 VGA@
1U_0402_6.3V4Z
C404 VGA@
0.1U_0402_16V4Z
@
1
2
R402
0_0402_5%
C396
VGA@
1U_0402_6.3V4Z
L42
VGA@
BLM18AG121SN1D_0603
2
1
130mA
DP C/D POWER
C400
VGA@
0.1U_0402_16V4Z
U5H
C399 VGA@
1U_0402_6.3V4Z
C395
VGA@
0.1U_0402_16V4Z
C393
VGA@
1U_0402_6.3V4Z
C398 VGA@
0.1U_0402_16V4Z
C390 VGA@
1U_0402_6.3V4Z
+DPC_VDD10
C392
VGA@
0.1U_0402_16V4Z
L40
VGA@
BLM18AG121SN1D_0603
2
1
1
For M96 are NC pins
+1.8VSG
+1.0VSG
L39
VGA@
BLM18AG121SN1D_0603
2
1
1
+1.8VSG
+DPC_VDD18
1
C389 VGA@
0.1U_0402_16V4Z
+1.0VSG
L37
VGA@
BLM18AG121SN1D_0603
2
1
C388 VGA@
10U_0603_6.3V6M
C387 VGA@
1U_0402_6.3V4Z
C386 VGA@
0.1U_0402_16V4Z
For M96 are NC pins
C403 VGA@
10U_0603_6.3V6M
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AH29
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
AW34
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
C394 VGA@
10U_0603_6.3V6M
GND
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#152
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#162
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#176
GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
GND#99
GND#100
C391
VGA@
10U_0603_6.3V6M
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35
C385 VGA@
10U_0603_6.3V6M
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
L36
VGA@
BLM18AG121SN1D_0603
2
1
Sheet

1
19
of
55
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
M2
N8
M3
BA0
BA1
BA2
J7
K7
K9
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSA2
QSA0
F3
C7
DQSL
DQSU
DQMA#2
DQMA#0
E7
D3
DML
DMU
QSA#2
QSA#0
G3
B7
DQSL
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
CLKA0
CLKA0#
ODTA0_1
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CSA0#_0
RASA0#
CASA0#
WEA0#
M2
N8
M3
BA0
BA1
BA2
CLKA0
CLKA0#
CKEA0
J7
K7
K9
CK
CK
CKE/CKE0
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTA0_1
CSA0#_0
RASA0#
CASA0#
WEA0#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSA3
QSA1
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA#3
DQMA#1
E7
D3
DML
DMU
QSA#3
QSA#1
G3
B7
DQSL
DQSU
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
Pull high for Madison and Park...
J7
K7
K9
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSA4
QSA5
F3
C7
DQSL
DQSU
DQMA#4
DQMA#5
E7
D3
DML
DMU
QSA#4
QSA#5
G3
B7
DQSL
DQSU
ODTA1_1
<17>
<17>
<17>
<17>
CSA1#_0
RASA1#
CASA1#
WEA1#
MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
A_BA0
A_BA1
A_BA2
M2
N8
M3
BA0
BA1
BA2
CLKA1
CLKA1#
CKEA1
J7
K7
K9
CK
CK
CKE/CKE0
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTA1_1
CSA1#_0
RASA1#
CASA1#
WEA1#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSA6
QSA7
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA#6
DQMA#7
E7
D3
DML
DMU
QSA#6
QSA#7
G3
B7
DQSL
DQSU
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.5VSG
VRAM_RST# T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
+1.5VSG
E3
F7
F2
F8
H3
H8
G2
H7
MDA48
MDA51
MDA55
MDA54
MDA50
MDA52
MDA49
MDA53
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
R182 VGA@
243_0402_1%
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
R183 VGA@
243_0402_1%
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG
+1.5VSG
+1.5VSG
96-BALL
SDRAM DDR3
X76@
+1.5VSG
VGA@ 2
VGA@ 2
R201
VGA@
4.99K_0402_1%
1
VGA@ 2
2
VREFCA_A4
1
R202
VGA@
4.99K_0402_1%
VGA@ 2
C445
VREFDA_Q4
1
R203
VGA@
4.99K_0402_1%
C446
VGA@ 2
C466
VGA@
1U_0402_6.3V6K
C465
VGA@
1U_0402_6.3V6K
C462
VGA@
1U_0402_6.3V6K
C461
VGA@
1U_0402_6.3V6K
C460
VGA@
1U_0402_6.3V6K
C459
VGA@
1U_0402_6.3V6K
C458
VGA@
1U_0402_6.3V6K
VREFDA_Q3
1
C444
C443
R193
VGA@
4.99K_0402_1%
+1.5VSG
C457
VGA@
1U_0402_6.3V6K
C456 VGA@
1U_0402_6.3V6K
C455 VGA@
1U_0402_6.3V6K
C454 VGA@
1U_0402_6.3V6K
VREFCA_A3
1
R200
VGA@
4.99K_0402_1%
+1.5VSG
C453 VGA@
1U_0402_6.3V6K
R191
VGA@
4.99K_0402_1%
C442
+1.5VSG
2
VREFDA_Q2
1
R199
VGA@
4.99K_0402_1%
2
VREFCA_A2
1
C441
VGA@
R189
VGA@
4.99K_0402_1%
1
2
R188
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
R187
VGA@
4.99K_0402_1%
C464
VGA@
1U_0402_6.3V6K
VGA@ 2
R198
VGA@
4.99K_0402_1%
+1.5VSG
VRAM_RST# T2
Compal Secret Data
Issued Date
C475 VGA@
10U_0603_6.3V6M
VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
C474 VGA@
10U_0603_6.3V6M
C473 VGA@
10U_0603_6.3V6M
C472 VGA@
10U_0603_6.3V6M
2009/7/14
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Rev
D
401827
Date:
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
0.1U_0402_16V4Z
VREFDA_Q1
1
C440
C452 VGA@
1U_0402_6.3V6K
C471 VGA@
10U_0603_6.3V6M
CLKA1
CLKA1#
CKEA1
D7
C3
C8
C2
A7
A2
B8
A3
M8
H1
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
C463
VGA@
1U_0402_6.3V6K
R197
VGA@
4.99K_0402_1%
C451 VGA@
1U_0402_6.3V6K
C470 VGA@
10U_0603_6.3V6M
R207 VGA@
56_0402_1%
2
<17>
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VREFCA_A4
VREFDA_Q4
0.1U_0402_16V4Z
C450 VGA@
1U_0402_6.3V6K
BA0
BA1
BA2
MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33
+1.5VSG
C469 VGA@
10U_0603_6.3V6M
CLKA1#
B1
B9
D1
D8
E2
E8
F9
G1
G9
M2
N8
M3
E3
F7
F2
F8
H3
H8
G2
H7
+1.5VSG
C468 VGA@
10U_0603_6.3V6M
<17>
C476 VGA@
0.01U_0402_25V7K
R206 VGA@
56_0402_1%
2
C449 VGA@
1U_0402_6.3V6K
C448 VGA@
1U_0402_6.3V6K
CLKA0#
R205 VGA@
56_0402_1%
2
<17>
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A_BA0
A_BA1
A_BA2
+1.5VSG
C447 VGA@
1U_0402_6.3V6K
C467 VGA@
0.01U_0402_25V7K
CLKA0
R204 VGA@
56_0402_1%
2
<17>
CLKA1
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
0.1U_0402_16V4Z
C439
VGA@
+1.5VSG
<17>
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
0.1U_0402_16V4Z
VREFCA_A1
1
R196
4.99K_0402_1%
VGA@
ODTA1_1
A1
A8
C1
C9
D2
E9
F1
H2
H9
0.1U_0402_16V4Z
VGA@
1
1
2
0_0402_5% R195
56_0402_1%
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
+1.5VSG
R186
VGA@
4.99K_0402_1%
R185
VGA@
4.99K_0402_1%
VGA@
B2
D9
G7
K2
K8
N1
N9
R1
R9
1
R184
4.99K_0402_1%
VGA@
VGA@
VGA@
ODTA0 2
1
1
2
R192
0_0402_5% R190 56_0402_1%
ODTA1 2
R194
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
96-BALL
SDRAM DDR3
X76@
+1.5VSG
0.1U_0402_16V4Z
ODTA1
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
+1.5VSG
0.1U_0402_16V4Z
<17>
J1
L1
J9
L9
MDA15
MDA11
MDA14
MDA10
MDA13
MDA9
MDA12
MDA8
VREFCA
VREFDQ
+1.5VSG
ODTA0_1
ODTA0
ZQ/ZQ0
R181 VGA@
243_0402_1%
96-BALL
SDRAM DDR3
X76@
+1.5VSG
+1.5VSG
<17>
RESET
L8
D7
C3
C8
C2
A7
A2
B8
A3
M8
H1
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
+1.5VSG
R180 VGA@
243_0402_1%
VRAM_RST# T2
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VREFCA_A3
VREFDA_Q3
+1.5VSG
MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28
VRAM_RST#
<17,21> VRAM_RST#
A_BA0
A_BA1
A_BA2
E3
F7
F2
F8
H3
H8
G2
H7
QSA#[7..0]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
+1.5VSG
<17> DQMA#[7..0]
QSA[7..0]
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
<17>
<17>
<17>
<17>
VREFCA
VREFDQ
<17> MAA[13..0]
<17>
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
MDA[0..63]
<17> MDA[0..63]
<17>
MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6
M8
H1
CKEA0
D7
C3
C8
C2
A7
A2
B8
A3
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
<17>
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VREFCA_A2
VREFDA_Q2
A_BA0
A_BA1
A_BA2
MDA22
MDA19
MDA21
MDA18
MDA23
MDA16
MDA20
MDA17
<17>
<17>
<17>
E3
F7
F2
F8
H3
H8
G2
H7
U12
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VREFCA
VREFDQ
U11
VREFCA_A1 M8
VREFDA_Q1 H1
U10
U9
Sheet

1
20
of
55
U13
VREFCB_A1 M8
VREFDB_Q1 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
<17>
<17>
<17>
B_BA0
B_BA1
B_BA2
<17>
CKEB0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
M2
N8
M3
BA0
BA1
BA2
J7
K7
K9
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSB3
QSB1
F3
C7
DQSL
DQSU
DQMB#3
DQMB#1
E7
D3
DML
DMU
QSB#3
QSB#1
G3
B7
DQSL
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
CLKB0
CLKB0#
<17> MAB[13..0]
ODTB0_1
<17>
<17>
<17>
<17>
<17> DQMB#[7..0]
CSB0#_0
RASB0#
CASB0#
WEB0#
MDB26
MDB28
MDB27
MDB31
MDB25
MDB30
MDB24
MDB29
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB15
MDB10
MDB12
MDB11
MDB13
MDB9
MDB14
MDB8
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VREFCB_A2 M8
VREFDB_Q2 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
+1.5VSG
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
B_BA0
B_BA1
B_BA2
M2
N8
M3
BA0
BA1
BA2
CLKB0
CLKB0#
CKEB0
J7
K7
K9
CK
CK
CKE/CKE0
ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSB2
QSB0
F3
C7
DQSL
DQSU
DQMB#2
DQMB#0
E7
D3
DML
DMU
QSB#2
QSB#0
G3
B7
DQSL
DQSU
+1.5VSG
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VREFCB_A3 M8
VREFDB_Q3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
<17>
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
B_BA0
B_BA1
B_BA2
M2
N8
M3
BA0
BA1
BA2
CLKB1
CLKB1#
J7
K7
K9
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSB4
QSB5
F3
C7
DQSL
DQSU
DQMB#4
DQMB#5
E7
D3
DML
DMU
QSB#4
QSB#5
G3
B7
DQSL
DQSU
VRAM_RST#
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
CKEB1
ODTB1_1
<17>
<17>
<17>
<17>
CSB1#_0
RASB1#
CASB1#
WEB1#
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB44
MDB43
MDB47
MDB41
MDB45
MDB40
MDB46
MDB42
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
+1.5VSG
+1.5VSG
U16
MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60
M2
N8
M3
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
CLKB1
CLKB1#
CKEB1
J7
K7
K9
CK
CK
CKE/CKE0
ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
QSB6
QSB7
F3
C7
DQSL
DQSU
DQMB#6
DQMB#7
E7
D3
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
QSB#6
QSB#7
G3
B7
DQSL
DQSU
VRAM_RST#
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.5VSG
96-BALL
SDRAM DDR3
X76@
+1.5VSG
96-BALL
SDRAM DDR3
X76@
+1.5VSG
96-BALL
SDRAM DDR3
X76@
C481
VGA@ 2
VREFDB_Q3
1
R229
VGA@
4.99K_0402_1%
C482
VGA@ 2
R230
VGA@
4.99K_0402_1%
2
VREFCB_A4
1
C483
VGA@ 2
R231
VGA@
4.99K_0402_1%
VREFDB_Q4
1
C484
VGA@ 2
C505 VGA@
1U_0402_6.3V6K
C504 VGA@
1U_0402_6.3V6K
C503 VGA@
1U_0402_6.3V6K
C502 VGA@
1U_0402_6.3V6K
C501 VGA@
1U_0402_6.3V6K
C500 VGA@
1U_0402_6.3V6K
C499 VGA@
1U_0402_6.3V6K
C498 VGA@
1U_0402_6.3V6K
+1.5VSG
C497 VGA@
1U_0402_6.3V6K
C496 VGA@
1U_0402_6.3V6K
C495 VGA@
1U_0402_6.3V6K
C494 VGA@
1U_0402_6.3V6K
C493 VGA@
1U_0402_6.3V6K
C492 VGA@
1U_0402_6.3V6K
C491 VGA@
1U_0402_6.3V6K
C490 VGA@
1U_0402_6.3V6K
C489 VGA@
1U_0402_6.3V6K
1
2
2
R228
VGA@
4.99K_0402_1%
VGA@ 2
VREFCB_A3
1
C480
1
2
1
2
1
2
1
2
VREFDB_Q2
1
+1.5VSG
+1.5VSG
C514 VGA@
10U_0603_6.3V6M
Compal Secret Data
Issued Date
C513 VGA@
10U_0603_6.3V6M
C512 VGA@
10U_0603_6.3V6M
C510 VGA@
10U_0603_6.3V6M
C509 VGA@
10U_0603_6.3V6M
C508 VGA@
10U_0603_6.3V6M
C507 VGA@
10U_0603_6.3V6M
C511 VGA@
10U_0603_6.3V6M
1
1
C506 VGA@
0.01U_0402_25V7K
CLKB1#
R235 VGA@
56_0402_1%
1
2
VGA@ 2
R227
VGA@
4.99K_0402_1%
+1.5VSG
C488 VGA@
1U_0402_6.3V6K
CLKB1
C479
+1.5VSG
R234 VGA@
56_0402_1%
1
2
VGA@ 2
VREFCB_A2
1
R226
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
+1.5VSG
C487 VGA@
1U_0402_6.3V6K
R233 VGA@
56_0402_1%
2
C486 VGA@
1U_0402_6.3V6K
R232 VGA@
56_0402_1%
2
C485 VGA@
0.01U_0402_25V7K
CLKB0#
VGA@ 2
VREFDB_Q1
1
C478
R219
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
R224
VGA@
4.99K_0402_1%
R225
VGA@
4.99K_0402_1%
+1.5VSG
R218
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
CLKB0
VREFCB_A1
1
C477
+1.5VSG
R217
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
R223 VGA@
56_0402_1%
2
+1.5VSG
R216
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
ODTB1
VGA@
ODTB1 R222
0_0402_5%
R215
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
R212
VGA@
4.99K_0402_1%
0.1U_0402_16V4Z
R221 VGA@
56_0402_1%
2
0.1U_0402_16V4Z
+1.5VSG
R214
VGA@
4.99K_0402_1%
VGA@
ODTB0 R220
R211
VGA@
243_0402_1%
2
R210
VGA@
243_0402_1%
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
+1.5VSG
ODTB0
ODTB1_1
<17>
E3
F7
F2
F8
H3
H8
G2
H7
J1
L1
J9
L9
R213
VGA@
4.99K_0402_1%
0_0402_5%
B_BA0
B_BA1
B_BA2
+1.5VSG
<17>
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
ZQ/ZQ0
+1.5VSG
<17>
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
+1.5VSG
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VREFCA
VREFDQ
RESET
L8
R209
VGA@
243_0402_1%
96-BALL
SDRAM DDR3
X76@
+1.5VSG
ODTB0_1
<17>
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
+1.5VSG
1
2
Pull high for Madison and Park...
VRAM_RST# T2
VRAM_RST#
R208
VGA@
243_0402_1%
<17>
VREFCB_A4 M8
VREFDB_Q4 H1
QSB#[7..0]
<17,20> VRAM_RST#
<17>
U15
QSB[7..0]
<17>
E3
F7
F2
F8
H3
H8
G2
H7
MDB[0..63]
<17> MDB[0..63]
<17>
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
U14
2009/7/14
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Rev
D
401827
Date:
Sheet

1
21
of
55
+VDDCLK_IO
+1.1VS
UMAO@ L54
1
2
0.1U_0402_16V4Z
1
1
FBMA-L11-201209-221LMA30T_0805 C515
C516
EXT@
2
2
22U_0805_6.3V6M
0.1U_0402_16V4Z
1
1
C517
C518
EXT@
EXT@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C519
C520
EXT@
EXT@
2
0.1U_0402_16V4Z
EXT@
+3VS_CLK
L55
0.1U_0402_16V4Z +3VS
1
2
1
1
FBMA-L11-201209-221LMA30T_0805
C521
C522
2
EXT@
C523
0.1U_0402_16V4Z
1
C524
22U_0805_6.3V6M EXT@
2 EXT@
2
0.1U_0402_16V4Z
EXT@
0.1U_0402_16V4Z
1
C526
C525
EXT@
2
0.1U_0402_16V4Z
EXT@
0.1U_0402_16V4Z
1
C528
C527
EXT@
2
0.1U_0402_16V4Z
EXT@
C529
0.1U_0402_16V4Z
1
C530
EXT@
2
0.1U_0402_16V4Z
EXT@
C531
EXT@
C532
D
1U_0402_6.3V4Z
2 EXT@
2
0.1U_0402_16V4Z
1U CLOSE PIN 69
+3VS
EXT@ L56
1
+3VS_CLKVDDA
+3VS_CLK
FBMA-L11-201209-221LMA30T_0805
1
U17
C534
0.1U_0402_16V4Z
EXT@
ICS 9LPRS488
49
48
VDDA
GNDA
62
66
VDDREF
GNDREF
SB_SRC_SLOW#
41
12
18
28
37
53
VDDSRC_IO
VDDSRC_IO
VDDATIG_IO
VDDSB_SRC_IO
VDDCPU_IO
CPUKG0T_LPRS
CPUKG0C_LPRS
56
55
HTT0T_LPRS / 66 M
HTT0C_LPRS / 66 M
60
59
SMBCLK
SMBDAT
1
2
R236
8.2K_0402_5%
EXT@
SB_SMCLK0 <10,11,27,34>
SB_SMDAT0 <10,11,27,34>
2
C533
22U_0805_6.3V6M
EXT@
Mini Card1
<27,32> LAN_CLKREQ#
<27,34> MINI1_CLKREQ#
1
R243
2
90.9_0402_1%
<13> CLK_NB_14.318M
CLKREQ0 #
51
CLKREQ1#
50
CLKREQ2#
43
CLKREQ3#
42
CLKREQ4#
63
REF2/SEL_27
SEL_SATA
64
REF1/SEL_SATA
CLK_14.318M
2
158_0402_1%
1
R244
24
27M_SEL
EXT@
CLK_CPU_BCLK <8>
CLK_CPU_BCLK# <8>
CPU
CLK_NBHT <13>
CLK_NBHT# <13>
NB HT
1
R237
8.2K_0402_5%
2
SB_SRC0T_LPRS
SB_SRC0C_LPRS
40
39
SB_SRC1T_LPRS
SB_SRC1C_LPRS
35
34
ATIG0T_LPRS
ATIG0C_LPRS
33
32
1 INT@ 2
R432 1 INT@ 0_0402_5%
2
R431
0_0402_5%
NB_HT_CLKP <26>
NB_HT_CLKN <26>
+3VS_CLK
ATIG1T_LPRS
ATIG1C_LPRS
31
30
ATIG2T_LPRS
ATIG2C_LPRS
26
25
SRC0T_LPRS
SRC0C_LPRS
23
22
SRC1T_LPRS
SRC1C_LPRS
21
20
65
REF0/SEL_HTT66
SRC2T_LPRS
SRC2C_LPRS
16
15
71
48MHz_0
14
13
70
SRC3T_LPRS
SRC3C_LPRS
48MHz_1
SRC4T_LPRS
SRC4C_LPRS
10
9
SRC5T_LPRS
SRC5C_LPRS
8
7
CLK_NBGFX <13>
CLK_NBGFX# <13>
ATIG1
1 EXT@ 2
ATIG1# R534 1 EXT@ 0_0402_5%
2
R535
0_0402_5%
1 INT@ 2
R438 1 INT@ 0_0402_5%
2
R437
0_0402_5%
1 INT@ 2
R436 1 INT@ 0_0402_5%
2
R433
0_0402_5%
R241
8.2K_0402_5%
EXT@
VGA
SEL_SATA
VGA_CLKP <26>
VGA_CLKN <26>
GPP_CLK1P <26>
GPP_CLK1N <26>
CLK_PCIE_LAN <32>
CLK_PCIE_LAN# <32>
CLK_PCIE_MINI1 <34>
CLK_PCIE_MINI1# <34>
1 INT@ 2
R435 1 INT@ 0_0402_5%
2
R434
0_0402_5%
R240
8.2K_0402_5%
@
NB GFX
CLK_PEG_VGA <15>
CLK_PEG_VGA# <15>
R239 8.2K_0402_5%
1
2
R238 8.2K_0402_5%
1
2
LAN
VDDDOT
VDDSRC
VDDATIG
VDDSB_SRC
VDDSATA
VDDCPU
VDDHTT
VDD48
1 EXT@ 2
R539 1 EXT@ 0_0402_5%
2
R538
0_0402_5%
3
17
29
38
44
54
L57
61
69
1
2
BLM18AG601SN1D_2P
EXT@
+3VS_CLK
CPUCK
CPUCK#
CPU_HT_CLKP <26>
CPU_HT_CLKN <26>
+3VS_CLK
C
SRC_SLOW
1 INT@ 2
R429 1 INT@ 0_0402_5%
2
R430
0_0402_5%
+VDDCLK_IO
SRC_SLOW
27M_SEL
EXT@
2
1
C535
0.1U_0402_16V4Z
R242
8.2K_0402_5%
EXT@
GLAN
+3VS_CLK
MiniCard_1
CLK_XTAL_OUT
GPP_CLK3P <26>
GPP_CLK3N <26>
CLK_XTAL_IN
EXT@
CLK_48M
1
33_0402_5%
2
R246
<27> CLK_48M_USB
CLK_XTAL_IN
67
X1
CLK_XTAL_OUT
68
X2
6
11
19
27
36
47
52
58
72
73
GNDDOT
GNDSRC
GNDSRC
GNDATIG
GNDSB_SRC
GNDSATA
GNDCPU
GNDHTT
GND48
GNDPAD
CLK_SBLINK_BCLK <13>
CLK_SBLINK_BCLK# <13>
Y2
2
NB A LINK
EXT@
1
14.318MHZ_16PF_7A14300083
2
2
C536
C537
27P_0402_50V8J
1
EXT@
+1.1VS_CLK
EXTPW@
R599
470_0603_5%
Q54
VGA option solution
1 INT@
R520
1 INT@
R519
CLK_SBLINK_BCLK
2
0_0402_5%
CLK_SBLINK_BCLK#
2
0_0402_5%
1 INT@
R497
1 INT@
R518
CLK_SBSRC_BCLK#
2
0_0402_5%
CLK_SBSRC_BCLK
2
0_0402_5%
1.1V 158R/90.0R
differential spread SRC_7 output
single-ended 66MHz HTT output
0*
differential 100MHz HTT output
1*
NON SPREAD 100M SATA SRC6 output
SPREAD 100M SATA SRC6 output
SEL_HTT66
A
SEL_SATA
* default
SUSP
<42,49>
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
VGA_ON# <42>
Custom
Date:
CLK_NB_14.318M
RS780
VGA_DBCLK <36>
S EXTPW@
2
1 R263
2
0_0402_5%
2N7002_SOT23
G
1 @ R150 2
10K_0402_5% 2
Q52 S
EXTPW@
R255 2
1
@ 0_0402_5%
C847
EXTPW@
0.1U_0402_16V4Z
2N7002_SOT23
1
<36,38,42,50> VGA_ON
27M_NSSC <16>
EXT@
27M_SEL
2nd (ICS) : SA000023H10 S IC ICS9LPRS488CKLFT MLF 72P CLK GEN
2
D
1 INT@ 2
R245 0_0402_5%
27P_0402_50V8J
Routing the trace at least 10mil
SB RCLK
1 1
R600 EXTPW@
2
1
2
G
100K_0402_5%
<36,42,46> SUSP#
1VGAOPT@ 2
R248 0_0402_5%
2 EXT@ 1
+3VS_CLK
R249
8.2K_0402_5%
1st (SILEGO) : SA00001Z310 S IC SLG8SP626VTR QFN 72P CLK GEN
100K_0402_5%
EXTPW@
1 EXT@ 2
R540 0_0402_5%
SLG8SP626VTR_QFN72_10x10
EXT@
R601
57
CLK_SRC7C
CLK_SB#
PD#
5
4
CLK_SBSRC_BCLK <26>
CLK_SBSRC_BCLK# <26>
1 * NON SPREAD 27M and SPREAD 27M output
L98
1
2
FBMA-L11-201209-221LMA30T_0805
EXTPW@
to CLK_GEN
+VDDCLK_IO
SRC7T_LPRS/27MHz_SS
SRC7C_LPRS/27MHz_NS
46
45
CLK_SB
Q50 EXTPW@
Close
SI2301CDS-T1-GE3_SOT23-3
+1.1VALW
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
Change Y2 to
TXC-SJ100009R00
<20ppm / 20pF>
Rev
D
401827
Sheet

1
22
of
55
LCD POWER CIRCUIT
JLVDS1
+LCDVDD
1
W=60mils
1
R250
300_0603_5%
41
42
43
44
45
46
+3VS
+3VALW
R251
100K_0402_5%
C538
G1
G2
G3
G4
G5
G6
4.7U_0805_10V4Z
1
1K_0402_5%
1
C539
1
GMCH_ENVDD
Q23
UMA@
2N7002_SOT23
2
G
1 R507
2
100K_0402_5%
+LCDVDD
W=60mils
0.047U_0402_16V7K
2
1
4.7U_0805_10V4Z
2
VGA_ENVDD
1 R508
2
100K_0402_5%
C541
0.1U_0402_16V4Z
D
Q29
VGA@
2
G
3
<15> VGA_ENVDD
<NCQD0 use>
C540
S
2N7002_SOT23
+3VS
+LCDVDD
B+
1
+INVPWR_B+
L59 2
1
FBMA-L11-201209-221LMA30T_0805
<36>
BKOFF#
BKOFF#
C545
680P_0402_50V7K 68P_0402_50V8J
2
2
2
2
2
2 10K_0402_5%
10U_0805_10V4Z
DAC_BRIG <36>
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXCLKTXCLK+
R525 2
1 0_0402_5%
LOCAL_DIM <36>
R524 2
1 0_0402_5%
COLOR_ENG_EN <36>
USB20_CMOS_N5
USB20_CMOS_P5
+3VS
R256 2
R257 2
1 0_0402_5%
1 0_0402_5%
USB20_N5 <27>
USB20_P5 <27>
IPEX_20143-040E-20F
CONN@
0.1U_0402_16V4Z
D14 @
+3VS
+3VS
CH3
Vp
CH2
Vn
CH1
USB20_CMOS_N5
220P_0402_50V7K
220P_0402_50V7K
+3VS C687 SG@

0.1U_0402_16V4Z
1
2
220P_0402_50V7K
U42
4
BUS_SEL
D
2
G
SG@
CH4
CM1293-04SO_SOT23-6
Q61
SG@
3
NC
<38> PE_GPIO2
USB20_CMOS_P54
R253
SG@
4.7K_0402_5%
2
DISPOFF#
1
C542
1
C543
1
C548
R171 1
DISPOFF#
+LCDVDD
S
2N7002_SOT23
BUS_SEL#
BUS_SEL# <25>
+3VS
SEL1
B1
DIS
<BUS>
B2
UMA
SEL2
B1
DIS
<DDC>
B2
UMA
R926
0_0603_5%
SG@
U68
For DIS only
DISO@RP2
DISO@
RP2
TXOUT2TXOUT2+
DISO@RP4
DISO@
RP4
TXOUT1+
TXOUT1DISO@RP6
DISO@
RP6
TXOUT0+
TXOUT0DISO@RP8
DISO@
RP8
3
4
2
1
3
4
2
1
3
4
2
1
3
4
VGA_TXCLKVGA_TXCLK+
0_0404_4P2R_5%
VGA_TXOUT2VGA_TXOUT2+
0_0404_4P2R_5%
VGA_TXOUT1+
VGA_TXOUT10_0404_4P2R_5%
VGA_TXOUT0+
VGA_TXOUT00_0404_4P2R_5%
VGA_TXCLK- <15>
VGA_TXCLK+ <15>
VGA_TXOUT2- <15>
VGA_TXOUT2+ <15>
0_0402_5% 2 DISO@ 1 R270

0_0402_5% 2
1 R272
DISO@
VGA_LCD_CLK
VGA_LCD_DAT
GMCH_INVT_PWM
VGA_TXOUT1+ <15>
VGA_TXOUT1- <15>
RP1 1
TXCLKTXCLK+
UMAO@
TXOUT2TXOUT2+
UMAO@ RP3
A
TXOUT1+
TXOUT1UMAO@ RP5
TXOUT0+
TXOUT0UMAO@ RP7
I2CC_SCL
I2CC_SDA
4
3
1
2
4
3
1
2
4
3
1
2
4
3
0_0402_5% 2 UMAO@1 R269

0_0402_5% 2
1 R271
UMAO@
GMCH_LCD_CLK
GMCH_LCD_DATA
2
0_0402_5%
@
1
R262
2
0_0402_5%
R533
VGA_LCD_CLK <16>
VGA_LCD_DAT <16>
R319
10K_0402_5%
+5VS C681 SG@

0.1U_0402_16V4Z
1
2
1
2
0_0402_5%
U33
<15> VGA_PNL_PWM
<13> GMCH_INVT_PWM
GMCH_TXCLKGMCH_TXCLK+
0_0404_4P2R_5%
0_0404_4P2R_5%
GMCH_TXOUT1+
GMCH_TXOUT10_0404_4P2R_5%
GMCH_TXOUT0+
GMCH_TXOUT00_0404_4P2R_5%
1 @
R261
PX & VB support
VGA_TXOUT0+ <15>
VGA_TXOUT0- <15>
UMA ONLY
INVT_PWM
DISO@2
1
R260
0_0402_5%
VGA_PNL_PWM
EC_INVT_PWM
I2CC_SCL
I2CC_SDA
EC_INVT_PWM
<36> EC_INVT_PWM
2
1
GMCH_TXCLK- <13>
GMCH_TXCLK+ <13>
@
1
R532
2
0_0402_5%
BUS_SEL#
BUS_SEL
2
5
1
7
1A
2A
1OE#
2OE#
VCC
1B
2B
GND
8
3
6
4
SN74CBTD3306CPWR_TSSOP8
SG@
GMCH_TXOUT2- <13>
GMCH_TXOUT2+ <13>
1OE#
GMCH_TXOUT1+ <13>
GMCH_TXOUT1- <13>
2OE#
GMCH_TXOUT0+ <13>
GMCH_TXOUT0- <13>
GMCH_LCD_CLK <13>
GMCH_LCD_DATA <13,38>
B1
B1
INVT_PWM_L1
R316
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
GMCH_TXCLKGMCH_TXCLK+
GMCH_TXOUT1+
GMCH_TXOUT0GMCH_LCD_DATA
GMCH_LCD_CLK
46
45
41
40
35
34
30
29
25
26
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
INVT_PWM
2
0_0402_5%
54
SEL2
52
5
51
NC
NC
NC
57
Thermal_GND
BUS_SEL#
Pop for PX verify

<If pop, Remove R260>
DIS
UMA
2010/03/12
Deciphered Date
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
2
3
7
8
11
12
14
15
19
20
C1152 C1153 C1154

TXCLKTXCLK+
TXOUT2TXOUT2+
TXOUT1+
TXOUT1TXOUT0+
TXOUT0I2CC_SDA
I2CC_SCL
SEL
17
BUS_SEL#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
6
9
13
16
21
24
28
33
39
44
49
53
55
SG@ SG@ SG@

2
2
2
Title
Date:
4
10
18
27
38
50
56
Compal Secret Data

2008/10/06
Size
B
5
+3VS_SWITCH
1
1
1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PI3LVD400ZFEX_TQFN56_11X5
SG@
Issued Date
48
47
43
42
37
36
32
31
22
23
VGA ONLY
TXCLKTXCLK+
VGA_TXCLKVGA_TXCLK+
VGA_TXOUT1+
VGA_TXOUT0VGA_LCD_DAT
VGA_LCD_CLK
0.1U_0402_16V4Z
INVT_PWM
2 0_0402_5%
C547
1
0_0603_5%
+3VS
TXOUT0TXOUT0+
DAC_BRIG
R172 1
C546
INVT_PWM
DISPOFF#
I2CC_SCL
I2CC_SDA
@
2
+LCDVDD R522
4.7U_0603_6.3V6K
+INVPWR_B+
+LCDVDD_L
R121
@
4.7K_0402_5%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
C544
C
D9
@
1
2
L58 2
1
FBMA-L11-201209-221LMA30T_0805
W=40mils
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0.1U_0402_16V4Z
<13> GMCH_ENVDD
S
2N7002_SOT23
AO3413_SOT23-3
Q13
2
R252
2
G
Q11
2
D
LCD/LED PANEL Conn.
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet

1
23
of
55
+3VSG
+3VSG
+HDMI_5V_OUT
JHDMI1
HDMI_HPD
3
2
2K_0402_5%
1
2
HDMI_SDATA
HDMI_SCLK
HDMI_R_CK-
VGA@
HDMI_R_CK+
HDMI_R_D0-
HDMI_SCLK
HDMI_R_D0+
HDMI_R_D1-
Q16 VGA@
BSH111 1N_SOT23-3
HDMI_SDATA
HDMI_R_D1+
HDMI_R_D2-
<16> VGA_HDMI_SDATA
R277
<5V tolerant>
VGA@
<16> VGA_HDMI_SCLK
2K_0402_5%
1
2
2
R275
R276
10K_0402_5%
2
R274
D
10K_0402_5%
+HDMI_5V_OUT
Q17 VGA@
BSH111 1N_SOT23-3
HDMI_R_D2+
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
@
2
R278
1
0_0402_5%
SUYIN_100042MR019S153ZL
CONN@
@
2
R279
1
0_0402_5%
<NAV70 use>
Check 5V tolerant
Place closed to JHDMI1
+3VS
R280
0_0402_5%
VGA@
1.1A_6VDC_FUSE
C549
0.1U_0402_16V4Z
VGA@
VGA_HDMI_DET 2 VGA@ 1
R282
0_0402_5%
R284
VGA@
10K_0402_5%
HDMI_HPD
2
1 VGA@ 2
B
R281
150K_0402_5%
E VGA@
Q18
MMBT3904_NL_SOT23-3
R283
@
365K_0402_1%
1
RB491D_SC59-3
W=40mils
VGA@
2
D3 VGA@
F1
1+HDMI_5V_OUT_1 1
+5VS
1 1
+HDMI_5V_OUT
HDMI_C_CLK-
R285 1 VGA@ 2
1
<16> VGA_HDMI_TXD2<16> VGA_HDMI_TXD2+
1 0.1U_0402_16V7K HDMI_C_TX2-R286 1
1 0.1U_0402_16V7K HDMI_C_TX2+R287 1
2VGA@ 499_0402_1%
2VGA@ 499_0402_1%
HDMI_C_CLK+
C552 VGA@2
C553 VGA@2
1 0.1U_0402_16V7K HDMI_C_TX1-R289 1
1 0.1U_0402_16V7K HDMI_C_TX1+R290 1
2VGA@ 499_0402_1%
2VGA@ 499_0402_1%
HDMI_C_TX0-
C554 VGA@2
C555 VGA@2
1 0.1U_0402_16V7K HDMI_C_TX0-R292 1
1 0.1U_0402_16V7K HDMI_C_TX0+R293 1
2VGA@ 499_0402_1%
2VGA@ 499_0402_1%
<16> VGA_HDMI_TXC<16> VGA_HDMI_TXC+
C556 VGA@2
C557 VGA@2
1 0.1U_0402_16V7K HDMI_C_CLK-R294 1
1 0.1U_0402_16V7K HDMI_C_CLK+R295 1
2VGA@ 499_0402_1%
2VGA@ 499_0402_1%
HDMI_C_TX0+
2N7002_SOT23
Q19
VGA@
HDMI_C_TX1-
Place closed to JHDMI1
HDMI_C_TX1+
HDMI_C_TX2-
HDMI_R_CK+
R291 1 VGA@ 2
0_0402_5%
HDMI_R_D0-
R296 1
VGA@
2
3
2
R297 1 VGA@ 2
R299
R300
1
2
3
2
3
0_0402_5%
HDMI_R_D0+
0_0402_5%
HDMI_R_D1-
2
3
0_0402_5%
HDMI_R_D1+
1 VGA@ 2
0_0402_5%
HDMI_R_D2-
VGA@
L63
WCM2012F2SF-900T04_0805
@
4 4
HDMI_C_TX2+
3
0_0402_5%
1 1
L62
WCM2012F2SF-900T04_0805
@
4 4
R298
VGA@
100K_0402_5%
HDMI_R_CK-
VGA@
1 1
L61
WCM2012F2SF-900T04_0805
@
4 4
2
G
3
+HDMI_5V_OUT
R288 1
0_0402_5%
2
L60
WCM2012F2SF-900T04_0805
@
4 4
C550 VGA@2
C551 VGA@2
R301 1
VGA@
2
3
0_0402_5%
HDMI_R_D2+
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet

1
24
of
55
CRT Connector
W=40mils
+R_CRT_VCC
+5VS
D7
2
RB491D_SC59-3
D5
PJDLC05C_SOT23-3
@
W=40mils
2
1.1A_6VDC_FUSE
1
C558
0.1U_0402_16V4Z
D4
PJDLC05C_SOT23-3
@
+CRT_VCC
F2
CRT_R_1
CRT_G
2
R408
1
0_0402_5%
CRT_G_1
L65 1
2 FCM2012CF-800T06_2P
CRT_G_2
CRT_B
2
R409
1
0_0402_5%
CRT_B_1
L66 1
2 FCM2012CF-800T06_2P
CRT_B_2
R305
L64 1
R307
R308
C559
C560
2
10P_0402_50V8J
150_0402_1%
140_0402_1%
2 FCM2012CF-800T06_2P
CRT_R_2
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
1
0_0402_5%
2
R407
CRT_R
150_0402_1%
C561
C562
2
10P_0402_50V8J
C563
2
10P_0402_50V8J
C564
2
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
C565
<NAL00 use>
16
17
G
G
C-H_13-12201513CP
CONN@
100P_0402_50V8J
+CRT_VCC
L68 1
2
FCM2012CF-800T06_2P
U18
CRT_HSYNC_1
C566
10P_0402_50V8J
CRT_HSYNC
L67 1
2
FCM2012CF-800T06_2P
CRT_DET# <27>
CRT_HSYNC_2
DSUB_12
CRT_VSYNC_2
1
R311
100K_0402_5%
C567
10P_0402_50V8J
74AHCT1G125GW_SOT353-5
C568 2
68P_0402_50V8J 1
+CRT_VCC
2
DSUB_15
C570
68P_0402_50V8J
+CRT_VCC
P
A
OE#
U19
Y
CRT_VSYNC_1
CRT_VSYNC
2 0.1U_0402_16V4Z
5
C571 1
1 10K_0402_5%
R312 2
5
2 0.1U_0402_16V4Z
OE#
C569 1
74AHCT1G125GW_SOT353-5
+3VS
R268 2 UMAO@ 1 0_0402_5%
CRT_B
GMCH_CRT_HSYNC
R273 2 UMAO@ 1 0_0402_5%
CRT_HSYNC
GMCH_CRT_VSYNC
R267 2 UMAO@ 1 0_0402_5%
CRT_VSYNC
GMCH_CRT_DATA
R410 2 UMAO@ 1 0_0402_5%
CRT_DATA
GMCH_CRT_CLK
<13> GMCH_CRT_CLK
R406 2 UMAO@ 1 0_0402_5%
For VGA Only

<16> VGA_CRT_R
<16> VGA_CRT_G
<16> VGA_CRT_B
<16> VGA_CRT_HSYNC
<16> VGA_CRT_VSYNC
4
<16> VGA_CRT_DATA
<16> VGA_CRT_CLK
R306 2 DISO@ 1 0_0402_5%
CRT_R
VGA_CRT_G
R302 2 DISO@ 1 0_0402_5%
CRT_G
VGA_CRT_B
R304 2 DISO@ 1 0_0402_5%
CRT_B
VGA_CRT_HSYNC
R303 2 DISO@ 1 0_0402_5%
CRT_HSYNC
VGA_CRT_VSYNC
R309 2 DISO@ 1 0_0402_5%
CRT_VSYNC
VGA_CRT_DATA
R411 2 DISO@ 1 0_0402_5%
CRT_DATA
VGA_CRT_CLK
R412 2 DISO@ 1 0_0402_5%
CRT_CLK
27
25
22
20
18
12
14
0B1
1B1
2B1
3B1
4B1
5B1
6B1
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA
26
24
21
19
17
13
15
0B2
1B2
2B2
3B2
4B2
5B2
6B2
SEL1
BUS_SEL# <23>
A5
A6
9
10
CRT_CLK
CRT_DATA
SEL2
30
BUS_SEL#
R317
4.7K_0402_5%
R318
4.7K_0402_5%
DSUB_12
CRT_CLK
VGA_CRT_R
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_CLK
VGA_CRT_DATA
GND
GND
GND
GND
GPAD
3
11
28
31
33
DSUB_15
B1
DIS
<BUS>
B2
UMA
SEL2
B1
DIS
<DDC>
B2
UMA
CRT_CLK
@
2
R321
1
0_0402_5%
@
2
R323
1
0_0402_5%
2010/03/12
Deciphered Date
Title
Size
B
Date:
Compal Secret Data

2008/10/06
Issued Date
Check 5V tolerant for DISO state
Q65
BSH111 1N_SOT23-3
PI3V712-AZLEX_TQFN32_6X3~D
SG@
SEL1
CRT_DATA
Q53
BSH111 1N_SOT23-3
CRT_G
GMCH_CRT_B
2
G
<13> GMCH_CRT_DATA
2 UMAO@ 1 0_0402_5%
+3VS
CRT_R
R83
+CRT_VCC
2
G
R266 2 UMAO@ 1 0_0402_5%
GMCH_CRT_G
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
<13> GMCH_CRT_B
GMCH_CRT_R
1
2
5
6
7
<13> GMCH_CRT_G
2
2
0.1U_0402_16V4Z
A0
A1
A2
A3
A4
<13> GMCH_CRT_R
2
2
0.1U_0402_16V4Z
VDD
VDD
VDD
VDD
VDD
For UMA Only
Close to Conn side
U69
4
16
23
29
32
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
C1155
C1156
C1157
C1158
SG@
SG@
SG@
SG@
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet

E
25
of
55
1
1
AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27
A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N
AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
590_0402_1% AD29
2K_0402_1% AD28
+3VS
AA28
AA29
Y29
Y28
Y26
Y27
W28
W29
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
AA22
Y21
AA25
AA24
W23
V24
W24
W25
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
+1.5VS
PCIE_CALRP
PCIE_CALRN
1
D
level shift to ISL6265

M23
P23
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
<13> NB_DISP_CLKP
<13> NB_DISP_CLKN
U29
U28
NB_DISP_CLKP
NB_DISP_CLKN
<22> NB_HT_CLKP
<22> NB_HT_CLKN
T26
T27
NB_HT_CLKP
NB_HT_CLKN
<22> CPU_HT_CLKP
<22> CPU_HT_CLKN
V21
T21
CPU_HT_CLKP
CPU_HT_CLKN
V23
T23
SLT_GFX_CLKP
SLT_GFX_CLKN
L29
L28
GPP_CLK0P
GPP_CLK0N
<22> CLK_SBSRC_BCLK
<22> CLK_SBSRC_BCLK#
When this pin is high, the SVI interface is

active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXEN input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high
<22> VGA_CLKP
<22> VGA_CLKN
<22> GPP_CLK1P
<22> GPP_CLK1N
LAN
MINI1
<22> GPP_CLK3P
<22> GPP_CLK3N
25M_CLK_X1
GPP_CLK1P
GPP_CLK1N
M29
M28
GPP_CLK2P
GPP_CLK2N
T25
V25
GPP_CLK3P
GPP_CLK3N
L24
L23
GPP_CLK4P
GPP_CLK4N
P25
M25
GPP_CLK5P
GPP_CLK5N
P29
P28
GPP_CLK6P
GPP_CLK6N
N26
N27
GPP_CLK7P
GPP_CLK7N
T29
T28
GPP_CLK8P
GPP_CLK8N
L25
14M_25M_48M_OSC
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
2
0_0402_5%
INT_VGA_EN# <38>
+3VALW
C581
1
2
AMD suggest add GPIO control gate

1
R427
1
R425
<27> SB_GPIO_A_RST#
2
@ 0_0402_5%
2
0_0402_5%
A_RST#
0.1U_0402_16V4Z
2
1
U21
Y
PLT_RST#
PLT_RST# <15,32,34>
R328
8.2K_0402_5%
@
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
<30>
<28,30> PCI_AD24
<30>
<30>
<30>
<30>
<30>
: VDDR Voltage SW
SG@
1
R322
2
0_0402_5%
PX_EN#
2
0_0402_5%
PE_GPIO1 <38,42>
<38>
Power Xpress Support
SG@
1
R259
PE_GPIO0 VGA RESET,
H: Enable
PE_GPIO1 VGA PWR Enable,
H: Enable
PE_GPIO2 MODE Switch,
H: VGA , L: NB
SG@
1
R258
2
0_0402_5%
LPCCLK0
PE_GPIO0 <15>
LPC_CLK0_EC
2
22_0402_5%
1
R330
LPC_CLK0_EC <30,36>
LPC_CLK1 <30>
LPC_AD0 <36>
LPC_AD1 <36>
LPC_AD2 <36>
LPC_AD3 <36>
LPC_FRAME# <36>
SERIRQ <36>
ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
+RTCBATT
SB_32KHI
32K_X2
C2
SB_32KHO
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
D2
B2
B1
32K_X1
@ R332 20M_0402_5%
@R332
1
2
L27
25M_X1
25M_X2
RTC
25M_CLK_X2
L26
ALLOW_LDTSTOP <13>
H_PROCHOT_R# <8>
H_PWRGD <8>
LDT_STOP# <8,13>
LDT_RST# <8>
C1
AMD suggest add Crystal for Internal CLK GEN

25M_CLK_X1
G21
H21
K19
G22
J24
PAD
+RTCVCC
D8
SB820 A12(SA00003IW10)
0.1U_0402_16V4Z
C584 1
4
2
C586
Y3
1
OSC
NC
OSC
NC
Close to SB
32.768KHZ_12.5PF_Q13MC14610002
SB_32KHO
2008/10/06
Issued Date
W=20mils
R334
C583
@
0_0603_5%
for Clear CMOS
1
2
+CHGRTC
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
BAS40-04_SOT23-3
Compal Secret Data
18P_0402_50V8J
1 C585
2
510_0402_5%
0.1U_0402_16V4Z
1
R333
SB_32KHI
R335
20M_0603_5%
R331
1K_0402_5%
T21
SB820M_FCBGA605
C582
18P_0402_50V8J
25M_CLK_X2
1
2
C688
27P_0402_50V8J
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
SG@
1
R320
R426
1M_0603_5%
25MHZ_20PF_7A25000012
AJ6
AG6
AG4
AJ4
Y6
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
1
2
C689
27P_0402_50V8J
N29
N28
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
CLOCK GENERATOR
ISL6265 PWROK input, TTL level: 0.8V~2.0V
V2
<30>
<30>
<30>
<30>
H_PWRGD_L <52>
FDV301N_NL_SOT23-3
PCIRST#
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
1U_0402_6.3V4Z
3
Q21
W2
W1
W3
W4
Y1
CPU
H_PWRGD
R329
4.7K_0402_5%
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
2
2
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
Part 1 of 5
R326
R327
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
SB800
PCIE_RST#
A_RST#
+1.1VS_PCIE
2
2
2
2
2
2
2
2
P1
L1
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
1
1
1
1
1
1
1
1
PAD
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
C579
C573
C574
C575
C576
C580
C577
C578
T4
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
U20A
33_0402_5%
1
PCI INTERFACE
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
LPC
R325
2
PCI CLKS
<13,14,36> A_RST#
2 150P_0402_50V8J
A_RST#
PCI EXPRESS INTERFACES
C572 1
Rev
D
401827
Sheet

E
26
of
55
2
<32,34> SB_PCIE_WAKE#
<8> H_THERMTRIP#
<13> NB_PWRGD
EC_RSMRST#
<36> EC_RSMRST#
<26> SB_GPIO_A_RST#
+3VS
SKU_ID
R340 1 VGA@ 2 2.2K_0402_5%

R341 1
2 100K_0402_5%
R416 1 SG@
R370
2
R516 1 INT@
R515 1
R593
R612
SB_SMCLK0
SB_SMDAT0
SB_SMCLK1
PX Function: 1-> PX Enable
SB_SMDAT1
Cinfigure to output or
0-> PX Disable *
VB_EN
Internal PU/PD
R517 1 INT@ 2 0_0402_5%
<22,32> LAN_CLKREQ#
VB Function: 1-> VB Enable
0-> VB Disable *
8L_6L_UMA
UMA 8L/6L SEL: 1-> 6L UMA

0-> 8L UMA
100K_0402_5%
2 2.2K_0402_5%
VB_EN
<39> SB_SPKR
<10,11,22,34> SB_SMCLK0
<10,11,22,34> SB_SMDAT0
100K_0402_5%
2 2.2K_0402_5%
1
PX_FN
100K_0402_5%
2 2.2K_0402_5%
1
R521 1
2 2.2K_0402_5%
1
R418 1 VB@
R588
Pop for PX verify
SKU ID: 1-> VGA *

0-> UMA
8L_6L_UMA
2 0_0402_5%
SB_GPIO_A_RST#
SKU_ID
MUXLESS_SEL
PX_FN
MUXLESS_SEL
<36> EC_LID_OUT#
MUXLESS SEL: 1->PX with Muxless

0->PX with Mux
VGA_HDMI_DET#
100K_0402_5%
<39> HDA_BITCLK_AUDIO
R345 1
2 33_0402_5%
R346 1
2 33_0402_5%
<35>
<35>
<35>
<30> HDA_SDOUT
<39> HDA_SDOUT_AUDIO
<39> HDA_SDIN0
<39> HDA_SYNC_AUDIO
<39> HDA_RST_AUDIO#
EC_LID_OUT#
USB_OC#2
USB_OC#1
USB_OC#0
USB_OC#2
USB_OC#1
USB_OC#0
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
R347 1
2 33_0402_5%
HDA_SYNC
R348 1
2 33_0402_5%
HDA_RST#
GBE_COL
GBE_CRS
GBE_MDIO
+3VS
1
R339
@
1
R349
@
1
R350
@
1
R351
GBE_RXERR
EC_RSMRST#
2
2.2K_0402_5%
HDA_BITCLK
2
10K_0402_5%
HDA_SDIN0
2
10K_0402_5%
HDA_SDIN1
2
10K_0402_5%
R342 1
2 2.2K_0402_5% SB_SMCLK0
R343 1
2 2.2K_0402_5% SB_SMDAT0
R344 1
2 4.7K_0402_5%
SUS_STAT#
GBE_PHY_INTR
+3VALW
+3VALW
1
R355
@
1
R357
1
R359
1
R360
1
R361
1
R362
1
R363
SB_PCIE_WAKE#
2
10K_0402_5%
EC_LID_OUT#
2
100K_0402_5%
SB_SIC
2
2.2K_0402_5%
SB_SID
2
2.2K_0402_5%
H_THERMTRIP#
2
10K_0402_5%
SB_SMCLK1
2
2.2K_0402_5%
SB_SMDAT1
2
2.2K_0402_5%
1
R352
1
R358
1
R353
1
R354
1
R356
2
2
GBE_MDIO
10K_0402_5%
GBE_PHY_INTR
10K_0402_5%
GBE_COL
10K_0402_5%
G1
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20
USB_FSD1P/GPIO186
USB_FSD1N
J10
H11
USB_FSD0P/GPIO185
USB_FSD0N
H9
J8
2 100P_0402_25V8K
CLK_REQ4#/SATA_IS0#/GPIO64
SMARTVOLT1/SATA_IS2#/GPIO50
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#
M3
N1
L2
M2
M1
M4
N2
P2
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
E23
E24
F21
G29
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160
D27
F28
F29
E27
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
SB820M_FCBGA605
CLK_48M_USB <22>
USB_RCOMP 1
11.8K_0402_1%
2
R338
OHCI4
USB20_P14
USB20_N14
USB_HSD13P
USB_HSD13N
B12
A12
USB_HSD12P
USB_HSD12N
F11
E11
USB_HSD11P
USB_HSD11N
E14
E12
USB_HSD10P
USB_HSD10N
J12
J14
USB_HSD9P
USB_HSD9N
A13
B13
USB20_P9
USB20_N9
USB_HSD8P
USB_HSD8N
D13
C13
USB20_P8
USB20_N8
USB_HSD7P
USB_HSD7N
G12
G14
USB20_P7
USB20_N7
USB_HSD6P
USB_HSD6N
G16
G18
USB20_P6
USB20_N6
USB_HSD5P
USB_HSD5N
D16
C16
USB20_P5
USB20_N5
USB_HSD4P
USB_HSD4N
B14
A14
USB_HSD3P
USB_HSD3N
E18
E16
USB_HSD2P
USB_HSD2N
J16
J18
USB20_P2
USB20_N2
USB_HSD1P
USB_HSD1N
B17
A17
USB20_P1
USB20_N1
USB_HSD0P
USB_HSD0N
A16
B16
USB20_P0
USB20_N0
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
D25
F23
B26
E26
F25
E22
F22
E21
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
G24
G25
E28
E29
D29
D28
C29
C28
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
RSMRST#
H3
D1
E4
D4
E8
F7
E7
F8
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
G19
USB 1.1 USB MISC
SB800
A10
USB_RCOMP
USB 2.0
<36> EC_GA20
<36> EC_KBRST#
<36> EC_SCI#
<36> EC_SMI#
ACPI / WAKE UP EVENTS
HPD for PX
0 -> DGPU
1 -> IGPU
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#
USBCLK/14M_25M_48M_OSC
EMBEDDED CTRL
<36>
<36>
<36>
<8,13,36>
<13>
Q64
SG@
2N7002_SOT23
PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
Part 4 of 5
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD
GPIO
CRT_DET
USB OC
J2
K1
D3
F1
H1
F2
H5
SUS_STAT#
G6
B3
T24
PAD
C4
T22
PAD
F6
T23
PAD
AD21
AE21
K2
J29
H2
J1
H6
F3
H_THERMTRIP#
J6
NB_PWRGD
AC19
EC_SWI#
EMBEDDED CTRL
2N7002_SOT23
<36>
HD AUDIO
1
S
2
G
@
C587 1
2
100_0402_5%
U20D
GBE LAN
Q22
1
3
1
R337
VGA_HDMI_DET#
D
R413
100K_0402_5%
SG@
CRT_DET
D
2
G
<25> CRT_DET#
R336
100K_0402_5%
+3VALW
+3VALW
USB20_P14 <35>
USB20_N14 <35>
BT
EHCI13 / OHCI3
USB20_P9 <35>
USB20_N9 <35>
WWAN
USB20_P8 <34>
USB20_N8 <34>
Mini1-WLAN
USB20_P7 <35>
USB20_N7 <35>
For China WWAN
USB20_P6 <35>
USB20_N6 <35>
CardReader
USB20_P5 <23>
USB20_N5 <23>
Camera
USB20_P2 <35>
USB20_N2 <35>
Ext USB3
USB20_P1 <35>
USB20_N1 <35>
Ext USB2
USB20_P0 <35>
USB20_N0 <35>
Ext USB1
EHCI2 / OHCI2
EHCI1 / OHCI1
<Wake Up support>
Check SW:
Cinfigure to output or Internal PU/PD
SB_SIC
SB_SID
<8>
<8>
GPIO199
GPIO200
<30>
<30>
Check SW:
STRAP PIN
SB820 A12(SA00003IW10)
GBE_CRS
10K_0402_5%
GBE_RXERR
10K_0402_5%
AMD recommend PD 10K
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Port7 and Port9 is disable for

2009 AMD platform
Rev
D
401827
Sheet

E
27
of
55
U20B
<31> SATA_DTX_C_SRX_N0
<31> SATA_DTX_C_SRX_P0
AJ8
AH8
SATA_RX0N
SATA_RX0P
AH10
AJ10
SATA_TX1P
SATA_TX1N
AG10
AF10
SATA_RX1N
SATA_RX1P
AG12
AF12
SATA_TX2P
SATA_TX2N
AJ12
AH12
SATA_RX2N
SATA_RX2P
AH14
AJ14
SATA_TX3P
SATA_TX3N
AG14
AF14
SATA_RX3N
SATA_RX3P
AG17
AF17
SATA_TX4P
SATA_TX4N
AJ17
AH17
SATA_RX4N
SATA_RX4P
AJ18
AH18
SATA_TX5P
SATA_TX5N
AH19
AJ19
SATA_RX5N
SATA_RX5P
<31> SATA_STX_DRX_P1
<31> SATA_STX_DRX_N1
+1.1VS_SATA
R364
2
2
R365
1K_0402_1%
SATA_CALRP
1
SATA_CALRN
1
931_0402_1%
<37> SATA_LED#
+3VS
R367 1
Part 2 of 5
FLASH
SATA_TX0P
SATA_TX0N
SERIAL ATA
ODD
AH9
AJ9
AB14
AA14
SATA_CALRP
SATA_CALRN
AD11
SATA_ACT#/GPIO67
2 10K_0402_5%
T13 PAD
T15 PAD
AD16
AC16
J5
E2
K4
K9
G2
HW MONITOR
HDD
SB800
SATA_X1
SATA_X2
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
AH28
AG28
AF26
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
AF28
AG29
AG26
AF27
AE29
AF29
AH27
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
W5
W6
Y9
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
W7
V9
W8
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
B6
A6
A5
B5
C7
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
A3
B4
A4
C5
A7
B7
B8
A8
NC1
NC2
SPI ROM
@R366
@
R366
1
2
0_0402_5%
EC_THERM# <36>
Check SW:
MEM_1V5
G27
Y2
SB820M_FCBGA605
3
SB820 A12(SA00003IW10)
MEM_1V5 is for gating the

glitch on PCI_AD24
+3VS
C685
2
1
5
0.1U_0402_16V4Z
Y
A
1 @
R423
PCI_AD24
1 : VDDR=1.05V
0 : VDDR=0.9V
U22
2
2
0_0402_5%
<26,30> PCI_AD24
1
R422
MEM_1V5
1
R424
2
33_0402_5%
VDDR_SW <48>
2
2
0_0402_5%
C686
150P_0402_50V8J
For VDDR Voltage Switch, AMD suggest

4
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet

E
28
of
55
U20E
+1.1VS_VDDC
1
R369
U20C
71mA
1
R371
AF22
AE25
AF24
AC22
2
0_0402_5%
VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4
POWER
43mA
AE28
+VDDPL_3V_PCIE
+1.1VS_PCIE
L70
2
1
FBMA-L11-201209-221LMA30T_0805
+1.1VS
C604
C605
C606
C607
1
1
1
1
2
2
2
2
600mA
22U_0805_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDPL_3V_SATA
+1.1VS
1
1
1
1
1
2
2
2
2
2
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AD14
VDDPL_33_SATA
AJ20
AF18
AH20
AG19
AE18
AD18
AE16
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
+1.1V_USB
L74
2
1
FBMA-L11-160808-221LMT 0603
+1.1VALW
C625 2
C626 2
VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
200mA
C11
D11
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
V1
M10
CORE S0
C590
2
2
2
2
1
1
1
1
C596
C594
C597
C598
L69
2
1
FBMA-L11-201209-221LMA30T_0805
1
R372
1
R373
2
0_0402_5%
2
0_0402_5%
L7
L9
1
R374
2
0_0402_5%
VDDIO_GBE_S_1
VDDIO_GBE_S_2
M6
P8
1
R375
2
0_0402_5%
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
VDDCR_11_S_1
VDDCR_11_S_2
VDDIO_AZ_S
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
A21
D21
B21
K10
L10
J9
T6
T8
F26
G26
M8
A11
B11
VDDPL_33_SYS
M21
VDDPL_11_SYS_S
L22
VDDPL_33_USB_S
F19
VDDAN_33_HWM_S
VDDXL_33_S
1 2.2U_0603_6.3V4Z
1 0.1U_0402_16V4Z
+1.1VS_CKVDD
400mA
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
CORE S5
2
2
2
2
2
A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19
PLL
1
1
1
1
1
658mA
USB I/O
+AVDD_USB
L72
2
1
FBMA-L11-201209-221LMA30T_0805
C617
C618
C619
C620
C621
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.1VS
1
2
2
2
2
+1.1VS
C595
External Clock, connect to +1.1VS

directly, no need thick trace
1
1
1
1
C600
C601
C602
C603
check can be removed?
D6
L20
32mA
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
1
2
2
Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16
A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
+3VALW
check 220ohm bead
+3VALW
K28
K29
J28
K26
J21
J20
K21
J22
2
0_0805_5%
10U_0805_10V4Z
93mA
+1.1VS_SATA
L71
2
1
FBMA-L11-201209-221LMA30T_0805
567mA
C610
C611
C612
C613
C614
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
VDDRF_GBE_S
VDDPL_33_PCIE
U26
V22
V26
V27
V28
V29
W22
W26
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
N13
R15
N17
U13
U17
V12
V18
W12
W18
VDDIO_33_GBE_S
3.3V_S5 I/O
2
2
2
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12
PCI/GPIO I/O
1
1
1
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CLKGEN I/O
GBE LAN
SERIAL ATA
C591
C592
C593
C599
FLASH I/O
+3VS
Part 3 of 5
SB800
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19
PCI EXPRESS
131mA
C608
C609
C615 2
C616 2
113mA
1 1U_0402_6.3V4Z
1 1U_0402_6.3V4Z
TBD
+VDDIO_AZ
+1.1VALW
+VDDCR_USB
197mA
2
1
L73 FBMA-L11-160808-221LMT 0603
C622
1
2 10U_0805_10V4Z
47mA
62mA
17mA
+VDDPL_3V
C623
C624
+VDDPL_11V
2
2
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
+VDDPL_3V_USB
5mA
197mA
+3V_HWM
+3VALW
+VDDLX_3V
Y4
EFUSE
D8
VSSAN_HWM
M19
VSSXL
P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13
2
1
L75 FBMA-L11-160808-221LMT 0603
C627 1
2 2.2U_0603_6.3V4Z
SB820M_FCBGA605
+VDDPL_3V
+1.1VALW
+VDDPL_3V_USB
L76
2
1
FBMA-L11-160808-221LMT 0603
L80
0.1U_0402_16V4Z
2
1
FBMA-L11-160808-221LMT 0603
1
C634
2.2U_0603_6.3V4Z
+VDDPL_3V_SATA
+3VS
M20
VSSPL_SYS
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27
Part 5 of 5
SB820M_FCBGA605
+3VALW
+3V_HWM
+3VALW
L77
2
1
FBMA-L11-160808-221LMT 0603
1
C628
+3VS
L79
2
1
FBMA-L11-160808-221LMT 0603
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
SB820 A12(SA00003IW10)
+VDDPL_11V
+3VS
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28
+1.1VALW
SB820 A12(SA00003IW10)
+VDDPL_3V_PCIE
SB800
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
GROUND
510mA
C635
2.2U_0603_6.3V4Z
+VDDIO_AZ
C630
C629
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
L78
2
1
FBMA-L11-160808-221LMT 0603
C632
C631
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
C633
2.2U_0603_6.3V4Z
+3VALW
L81
4
2
1
FBMA-L11-160808-221LMT 0603
C636
0.1U_0402_16V4Z
1
R376
0_0402_5%
1
C637
2.2U_0603_6.3V4Z
C638
2.2U_0603_6.3V4Z
For 3V AZ device
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet

E
29
of
55
REQUIRED STRAPS
PCI_CLK3
PCI_CLK4
LPC_CLK0
LCP_CLK1
USE
DEBUG
STRAP
CPU/HT CLK
SEL
EC
ENABLE
CLOCKGEN
ENABLE
Performance
MODE
PULL
LOW
FORCE PCIE
GEN1
DEFAULT
IGNORE
DEBUG
STRAP
+3VS
+3VS
R380
10K_0402_5%
2
1
+3VS
R379
10K_0402_5%
2
1
+3VS
R378
10K_0402_5%
2
1
DEFAULT
EC
DISABLE
L,H = LPC ROM (Default L,NC)
CLOCKGEN
DISABLE
L,L = FWH ROM
Disable
DEFAULT
H,L = SPI ROM
CPU/HT CLK
SEL
DEFAULT
H,H = Reserved
Enable
DEFAULT
R377
10K_0402_5%
2
1
+VDDIO_AZ
WATCHDOG
TIMER
DISABLE
GPIO199
DEFAULT
+3VALW
INT@
DEFAULT
+3VALW
+3VALW
INT@
+3VALW
R385
2.2K_0402_5%
2
1
GPIO200
R384
10K_0402_5%
2
1
PCI_CLK2
LOW POWER ALLOW PCIE WATCHDOG

MODE
GEN2
TIMER
ENABLE
R383
10K_0402_5%
2
1
PCI_CLK1
Check Internal PU/PD
R382
10K_0402_5%
2
1
AZ_SDOUT
PULL
HIGH
R381
10K_0402_5%
2
1
<27> HDA_SDOUT
<26>
PCI_CLK1
<26> PCI_CLK2
<26> PCI_CLK3
<26> PCI_CLK4
<26,36> LPC_CLK0_EC
<26> LPC_CLK1
<27> GPIO200
<27> GPIO199
USE PCI
PLL
DISABLE ILA
AUTORUN
USE FC PLL
USE DEFAULT
PCIE STRAPS
DISABLE PCI
MEM BOOT
DEFAULT
PULL
LOW
BYPASS
PCI PLL
Check AD29,AD28 strap function
PCI_AD23
DEFAULT
DEFAULT
DEFAULT
DEFAULT
ENABLE ILA
AUTORUN
BYPASS
FC PLL
USE EEPROM
PCIE STRAPS
ENABLE PCI
MEM BOOT
<26>
<26>
<26>
<26>
<26>
<26,28>
<26>
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
check default
R401
2.2K_0402_5%
2
1
PCI_AD24
R400
2.2K_0402_5%
2
1
PCI_AD25
R399
2.2K_0402_5%
2
1
PCI_AD26
R398
2.2K_0402_5%
2
1
PULL
HIGH
PCI_AD27
+3VS
R397
2.2K_0402_5%
2
1
R396
10K_0402_5%
2
1
R395
10K_0402_5%
2
1
DEBUG STRAPS
R394
2.2K_0402_5%
2
1
EXT@
+3VS
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
R393
2.2K_0402_5%
2
1
R392
10K_0402_5%
2
1
EXT@
R391
10K_0402_5%
2
1
R390
10K_0402_5%
2
1
R389
10K_0402_5%
2
1
R388
10K_0402_5%
2
1
R387
10K_0402_5%
2
1
R386
10K_0402_5%
2
1
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet

E
30
of
55
SATA HDD Conn.
JHDD1
C656 1
C658 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
C657 1
C659 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
+3VS
1
+5VS
R405 1
+3VS
C639
0.1U_0402_16V4Z
+5VS_HDD
2 0_0805_5%
10U_0805_10V4Z
1
C660
C661
0.1U_0402_16V4Z
1
C662
C663
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
GND
24
23
SANTA_192301-1
CONN@
1U_0402_6.3V4Z
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
1000P_0402_50V7K
<NAV70 use>
SATA ODD Conn.

JODD1
C648 1
C649 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
C650 1
C651 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1
R403 1
R404 1
+5VS
2 0_0805_5%
10U_0805_10V4Z
C652
2 1K_0402_1%
+5VS_ODD
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
DP
+5V
+5V
MD
GND
GND
GND
GND
NC
NC
17
16
15
14
0.1U_0402_16V4Z
C653
C654
1U_0402_6.3V4Z
C655
OCTEK_SLS-13SB1G_RV
CONN@
2
1000P_0402_50V7K
Issued Date
Compal Secret Data
2008/10/06
2010/03/12
Deciphered Date
Title
Size
B
SCHEMATIC, MB A5911
Document Number
Date:
Rev
D
401827
G
Sheet
31
H
of
55
+3V_LAN
+3VALW
R800
60mil
0_1206_5%
1
U70
+3V_LAN
C901
C902
4.7U_0603_6.3V6K
2
2
0.1U_0402_16V4Z
+LAN_BIASVDDH
42
VDDC
BIASVDDH
25
6
15
41
VDDC
VDDC
VDDC
XTALVDDH
14
AVDDH
30
AVDDH
36
TRD3_N
37
LAN_MIDI3-
TRD3_P
38
LAN_MIDI3+
TRD2_N
35
LAN_MIDI2-
TRD2_P
34
LAN_MIDI2+
TRD1_N
31
LAN_MIDI1-
TRD1_P
32
LAN_MIDI1+
TRD0_N
29
LAN_MIDI0-
TRD0_P
28
LAN_MIDI0+
LINKLED#
48
SPD100LED#
47
2
0.1U_0402_16V4Z
+LAN_AVDDL
+LAN_GPHYPLLVDDL
24
AVDDL
AVDDL
AVDDL
LAN_MIDI3- <33>
LAN_MIDI3+ <33>
LAN_MIDI2- <33>
SPROM_CLK
(EECLK)
SPROM_DOUT
(EEDATA)
On chip
AT24C02
+3V_LAN
LAN_MIDI2+ <33>
C906 1
GPHY_PLLVDDL
18
PCIE_PLLVDDL
21
PCIE_PLLVDDL
LAN_MIDI1- <33>
LAN_MIDI0- <33>
LAN_MIDI0+ <33>
2 0.1U_0402_16V7K PCIE_PTX_IRX_P0 17
2 0.1U_0402_16V7K PCIE_PTX_IRX_N0 16
22
23
LAN_PME#
4
LAN_RESET# 2
20
@
2 0_0402_5%
19
2 0_0402_5%
2 4.7K_0402_5%
C9071
C9081
PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
<36> EC_PME#
+3V_LAN
R806 1
R807 1
R808 1
R809 1
<15,26,34> PLT_RST#
PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
WAKE#
REST#
PCIE_REFCLK_P
PCIE_REFCLK_N
SPD1000LED#
46
TRAFFICLED#
45
2
R805
0_0402_5%
U71 @
8
7
6
5
R812
1K_0402_1%
@
LAN_ACTIVITY# <33>
20mil
+LAN_XTALVDDH 1
C909
+3VS
R810 1
2 1K_0402_5%
40
R813 1
2 10K_0402_5%
SPROM_DOUT
EECLK
44
SPROM_CLK
VMAIN_PRSINT
SR_LX
LAN_XTALO_R
LAN_XTALI
13
XTALO
12
XTALI
SR_VFB
11
+1.2V_LAN_OUT
1
2
4.7UH_PG031B-4R7MS_1.1A_20%
+1.2V_LAN
C913
0.1U_0402_16V4Z
26
RDAC
SR_VDDP
1.24K_0402_1%
0.1U_0402_16V4Z
2
NC
0.1U_0402_16V4Z
+1.2V_LAN
4.7U_0603_6.3V6K
20mil
L105
+LAN_GPHYPLLVDDL
1
2
BLM18AG601SN1D_2P
1
1
C919
C920
0.1U_0402_16V4Z
49
BCM57780A0KMLG_QFN48_7X7
L104
1
2
BLM18AG601SN1D_2P
1
C916
C918
2
2
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
CLKREQ#
0.1U_0402_16V4Z
+LAN_PCIEPLLVDD
1
C915
PAD
<22,27> LAN_CLKREQ#
C917
20mil
+3V_LAN
1
L102
1
2
BLM18AG601SN1D_2P
C914
10U_0805_10V4Z
10
SR_VDD
0.1U_0402_16V4Z
+LAN_AVDDH
1
1
C911
C912
R814
LAN_RDAC
20mil
LOW_PWR
+3V_LAN
L101
1
2
BLM18AG601SN1D_2P
+LAN_BIASVDDH 1
C910
L103
L100
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
20mil
43
1
2
3
4
AT24C02_SO8
R811
1K_0402_1%
<22> CLK_PCIE_LAN
<22> CLK_PCIE_LAN#
EEDATA
A0
A1
NC
GND
LAN_LINK# <33>
2 0_0402_5%
MODE
VCC
WP
SCL
SDA
<12>
<12>
<12>
<12>
2
R801
0_0402_5%
R803
1K_0402_1%
SPROM_CLK
SPROM_DOUT
2 0.1U_0402_16V4Z
@
R802
1K_0402_1%
@
LAN_MIDI1+ <33>
+LAN_PCIEPLLVDD
27
33
39
+LAN_AVDDH
2
2
0.1U_0402_16V4Z
+LAN_XTALVDDH
C903
4.7U_0603_6.3V6K
2
0.1U_0402_16V4Z
1
1
C904
C905
C900
+1.2V_LAN
20mil
+LAN_AVDDL
1
C921
LAN_XTALI
0.1U_0402_16V4Z
+1.2V_LAN
4.7U_0603_6.3V6K
L106
1
2
BLM18AG601SN1D_2P
C922
+1.2V_LAN
4.7U_0603_6.3V6K
LAN_XTALO_R
R815
200_0402_1%
Y5
1
2 LAN_XTALO
25MHZ_20PF_7A250000121
C923
33P_0402_50V8J
Issued Date
Compal Secret Data
C924
33P_0402_50V8J
2
2008/04/16
Deciphered Date
2010/03/12
Title
Custom
Date:
SCHEMATIC, MB A5911
Rev
D
401827

D
Sheet
32
of
55
LAN Connector
BH GS5009-D
<SP050006B00>
JRJ45
T25
<32> LAN_ACTIVITY#
LAN_MIDI0+
LAN_MIDI0-
1
2
3
TCT1
TD1+
TD1-
MCT1
MX1+
MX1-
24
23
22
RJ45_MIDI0+
RJ45_MIDI0-
<32> LAN_MIDI1+
<32> LAN_MIDI1-
LAN_MIDI1+
LAN_MIDI1-
4
5
6
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
21
20
19
RJ45_MIDI1+
RJ45_MIDI1-
<32> LAN_MIDI2+
<32> LAN_MIDI2-
LAN_MIDI2+
LAN_MIDI2-
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
RJ45_MIDI2+
RJ45_MIDI2-
<32> LAN_MIDI3+
<32> LAN_MIDI3-
LAN_MIDI3+
LAN_MIDI3-
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
RJ45_MIDI3+
RJ45_MIDI3-
350UH_IH-037-2
0.1U_0402_16V4Z
2
2
R819
75_0402_1%
C931
R820
75_0402_1%
0.1U_0402_16V4Z
2
2
R824
+3V_LAN
1
C942
R821
75_0402_1%
0.1U_0402_16V4Z
PR4-
RJ45_MIDI3+
PR4+
RJ45_MIDI1-
PR2-
RJ45_MIDI2-
PR3-
RJ45_MIDI2+
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
PR1-
RJ45_MIDI0+
PR1+
10
1
1K_0402_5%
SHLD2
SHLD1
13
14
C
Green LED-
Green LED+
SANTA_130451-K
CONN@
2
220P_0402_50V7K
RJ45_GND
RJ45_GND
Place close to TCT pin
Yellow LED+
RJ45_MIDI3-
R822
75_0402_1%
0.1U_0402_16V4Z
C930
Yellow LED-
11
C929
C928
1
1K_0402_5%
2
220P_0402_50V7K
<32> LAN_LINK#
2
R823
1
C938
+3V_LAN
<32> LAN_MIDI0+
<32> LAN_MIDI0-
12
LANGND
1
C940
1000P_1206_2KV7K
40mil
1
C941
0.1U_0402_16V4Z
LAN_ACTIVITY#
LAN_LINK#
40mil
C939
4.7U_0603_6.3V6K
D40
PJDLC05C_SOT23-3
@
LAN_ACTIVITY#
1
C943
2
220P_0402_50V7K
LAN_LINK#
1
C944
2
220P_0402_50V7K
B
Compal Secret Data
2008/10/06
Issued Date
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet
1
33
of
55
Mini-Express Card for WLAN

+3VS
+1.5VS
C705
4.7U_0805_10V4Z
C706
0.1U_0402_16V4Z
C707
0.1U_0402_16V4Z
C708
4.7U_0805_10V4Z
C709
0.1U_0402_16V4Z
C710
0.1U_0402_16V4Z
JMINI1
SB_PCIE_WAKE#
R440 1
2 0_0402_5%
<22> CLK_PCIE_MINI1#
<22> CLK_PCIE_MINI1
<12> PCIE_ITX_C_PRX_N1
<12> PCIE_ITX_C_PRX_P1
+3VS
R445 1
0_0402_5%
2
E51TXD_P80DATA_R
E51RXD_P80CLK
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS
+1.5VS
Mini Card Power Rating

Power
WL_OFF#
PLT_RST#
+3V_WLAN
1
R441 1
R442
@
MINI1_SMBCLK
@
1
MINI1_SMBDAT R443
@
1
R444
2
2 0_0603_5%
0_0603_5%
2
0_0603_5%
2
0_0603_5%
WL_OFF# <36>
PLT_RST# <15,26,32>
+3VS
+3VALW
Auxiliary Power (mA)

Normal
Peak
Normal
+3VS
1000
750
+3V
330
250
250 (wake enable)
+1.5VS
500
375
5 (Not wake enable)
USB20_N8 <27>
USB20_P8 <27>
WIMAX_LED#
WLAN_LED#_L
(9~16mA)
+3VS
1
ACES_88910-5204
CONN@
R530 2
<NAV70 use>
WIMAX_LED#
D47
2
Height : 4mm
WLAN_LED#_L
1 0_0402_5%
@
R537
100K_0402_5%
2
53
54
55
56
Primary Power (mA)
SB_SMDAT0 <10,11,22,27>
SB_SMCLK0 <10,11,22,27>
G1
G2
G3
G3
<36> E51TXD_P80DATA
<36> E51RXD_P80CLK
1
3
5
7
9
11
13
15
MINI1_LED# <36>
CHP202UPT_SOT323-3
R531 2
1 0_0402_5%
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
Size
B
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet

E
34
of
55
+USB_VCCA
+3VALW
C713
R447 1
2 10K_0402_5%
<42>
C714
0.1U_0402_16V4Z
R448
<27>
+3VALW
+USB_VCCB
C715
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
80mil
2
@ 0_0402_5%
USB20_N0
USB20_N0
USB20_P0
USB20_P0
JUSB1
1
2
3
4
5
6
7
8
USB20_N0_R
USB20_P0_R
WCM2012F2SF-900T04_0805
R449
0_0402_5%
1
2
R450
100K_0402_5%
USB_OC#2 <27>
R451
2
@ 0_0402_5%
1
2
R452
10K_0402_5%
RT9715BGS_SO8
1
2
3
4
GND
GND
GND
GND
<NAL00 use>
SUYIN_020133MB004S580ZL-C
CONN@
U25
1
2
3
4
<27>
+5VALW
2
470P_0402_50V7K
L83
SYSON#
220U_6.3V_M
USB_OC#0 <27>
RT9715BGS_SO8
4.7U_0805_10V4Z
2
1
C712
R446
100K_0402_5%
80mil
C711
W=80mils
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
U24
1
2
3
4
SVPE, 4.4m, 17mohm
+USB_VCCA
+USB_VCCA
+5VALW
USB_OC#1 <27>
1
4.7U_0805_10V4Z
2
C716
D10
0.1U_0402_16V4Z
CH3
Vp
CH2
Vn
CH1
USB20_P0_R
SYSON#
+USB_VCCA
USB20_N0_R
2
CH4
CM1293-04SO_SOT23-6
To USB/B Connector
To CardReader/B Connector
+USB_VCCB
(Port 1,2)
JUSB2
USB20_N1
USB20_P1
GND
GND
8
7
6
5
4
3
2
1
USB20_N1 <27>
USB20_P1 <27>
USB20_N2
USB20_P2
USB20_N2 <27>
USB20_P2 <27>
10
9
8
7
6
5
4
3
2
1
C717
4.7U_0805_10V4Z
1
2
Bluetooth Conn.
5IN1_LED# <37>
USB20_N6
USB20_P6
USB20_N6 <27>
USB20_P6 <27>
+3VALW
+3VS
ACES_85201-08051
CONN@
1
C718
BT@ 2
1
R453
10K_0402_5%
BT_ON#
+BT_VCC
WWAN_OFF#
+3VS_WWAN
USB20_N9 <27>
USB20_P9 <27>
10
1
+
USB20_N7 <27>
USB20_P7 <27>
2
C723
150U_B_6.3VM_R40M
3G@
BT@
GND 8
7
6
5
4
3
2
GND 1
BT@
R454
300_0603_5%
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
8
7
6
5
4
3
2
1
USB20_P14 <27>
USB20_N14 <27>
BT@
Q25
2N7002_SOT23
2
G
ACES_87213-0800G
CONN@
Close to WWAN CONN
ACES_87036-1001-CP
CONN@
C722
JBT1
Peak: 2.75A
Normal: 1.1A
3G@ 2
1
R455
0_1206_5%
WWAN_OFF# <36>
WWAN_LED# <36>
BT@
+3VS
1
2
3
4
5
6
7
8
9
10
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
+BT_VCC
R457
100K_0402_5%
JP4
+3VS_WWAN
C721
(Port 9)
AO3413_SOT23-3
W=40mils
BT@
0.1U_0402_16V4Z
+3VS_WWAN
1U_0402_6.3V4Z
3
C720
To 3G Module Connect
BT@
C719
<36>
BT@
Q24
BT@
0.1U_0402_16V4Z
<NEW70 use>
<NAL00 use>
ACES_85201-1205N
CONN@
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+3VS
JCR1
1
2
3
4
5
6
7
8
9
10
11
12
<NAL00 use>
<NAV70 use>
4
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
Size
B
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet

E
35
of
55
For EC Tools
+3VALW
L84
C730
<37>
1
33_0402_5%
LPC_CLK0_EC
A_RST#
<26,30> LPC_CLK0_EC
<13,14,26> A_RST#
<27>
2
1
R462
47K_0402_5%
2
1
C733
0.1U_0402_16V4Z
+3VALW
EC_SCI#
12
13
37
EC_SCI#
20
1
2
38
@ R428
10K_0402_5%
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
+5VS
TP_CLK
2
4.7K_0402_5%
TP_DATA
2
4.7K_0402_5%
1
R465
1
R466
1
R541
1
R467
1
R468
1
R542
+3VALW
+3VS
+3VALW
2
2.2K_0402_5%
EC_SMB_CK2
2
2.2K_0402_5%
EC_SMB_DA2
2
2.2K_0402_5%
2
2.2K_0402_5%
@
@
+3VALW
1
R471
1
R472
1
R473
1
R474
2
R475
1
R476
2
R488
2
R526
2
R527
EC_SMB_CK1
2
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%
LID_SW#
1
100K_0402_5%
EC_PME#
2
10K_0402_5%
ENBKL
1
100K_0402_5%
LOCAL_DIM
1
100K_0402_5%
COLOR_ENG_EN
1
100K_0402_5%
For Low PWR panel use
<44>
<44>
<8,16>
<8,16>
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<27> PM_SLP_S3#
<27> PM_SLP_S5#
<27>
EC_SMI#
<38>
ON/OFF
<37> PWR_SUSP_LED
<37> WLAN_LED#
77
78
79
80
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
OSC
OSC
NC
3
NC
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
X1
67
9
22
33
96
111
125
AVCC
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
DAC_BRIG
EN_DFAN1
IREF
CALIBRATE#
EC_MUTE#
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
3S/4S#
65W/90W#
VLDT_EN
LID_SW#
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
WWAN_OFF#
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SWI#
EC_PWROK
BKOFF#
WL_OFF#
KB926_ID
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
VGATE
ENBKL
EAPD
EC_THERM#
SUSP#
PBTN_OUT#
EC_PME#
V18R
124
SPI Flash ROM
GPIO
GPI
XCLK1
XCLK0
1
100K_0402_5%
2
100K_0402_5%
EC Version control
KB926_ID
High : D3
Low : E0
<46,49>
KB926QFD3_LQFP128_14X14
BATT_TEMP <44>
Analog Project ID definition
DAC_BRIG <23>
EN_DFAN1 <41>
IREF
<46>
CALIBRATE# <46>
R463
Ra
PEW@
EC_MUTE# <40>
WWAN_LED#
3G_LED#
TP_CLK
TP_DATA
WWAN_LED# <35>
3G_LED# <37>
TP_CLK <37>
TP_DATA <37>
56@
18K_0402_5%
R464
768696@
For PEW76/86/96 PID
R464
AD_PID0
8.2K_0402_5%
3S/4S# <46>
65W/90W# <46>
VLDT_EN <42,48>
LID_SW# <37>
C734
For NEW76/86/96 PID
0.1U_0402_16V4Z
NEW@
R464 100K_0402_5%
Analog Board ID definition
EC_SI_SPI_SO <37>
EC_SO_SPI_SI <37>
EC_SPICLK_L
EC_SPICS#/FSEL#
WWAN_OFF#
Delay EC_PWROK 50ms

for VGA criterial
AD_BID0
18K_0402_5%
R470
Rb
C735
0.1U_0402_16V4Z
EC_SPICLK <37>
EC_SPICLK_L 1
R419
2
0_0402_5%
@
C783 33P_0402_50V8K
Reserve for EMI, close to EC
BKOFF# <23>
WL_OFF# <34>
Delay SUSP# 10ms
VGATE
<52>
ENBKL
<13>
EAPD
<39>
EC_THERM# <28>
SUSP#
<22,42,46>
PBTN_OUT# <27>
EC_PME# <32>
EC_PWROK 1
R254
2
0_0402_5%
SB_PWRGD <8,13,27>
C736
BATT_TEMP
4.7U_0805_10V4Z
ACIN
KB926 Rev:D3(SA00001J580)
KB926 Rev:E0(SA00001J5A0)
Deciphered Date
C737
2
C738
2
C741
2
100P_0402_50V8J
1
100P_0402_50V8J
1
100P_0402_50V8J
1
Compal Secret Data

2008/10/06
100K_0402_5%
8.2K_0402_5%
EC_RSMRST# <27>
EC_LID_OUT# <27>
EC_ON
<38>
EC_SWI# <27>
VGA_ON <22,38,42,50>
CAP@ R470
Ra
<35>
FSTCHG <46>
BATT_BLUE_LED# <37>
INT_VGAPWR_ON <38>
BATT_AMB_LED# <37>
PWR_LED <37>
SYSON
<42,47>
VR_ON
<52>
ACIN
<16,37,42,43>
BATT_BLUE_LED#
INT_VGAPWR_ON
BATT_AMB_LED#
PWR_LED
SYSON
VR_ON
ACIN
For Capilano VGA identify
R469
<37>
BATT_OVP
2010/03/12
Title
Size
B
3
For PEW56 PID
100K_0402_5%
Rb
Date:
ECAGND
2
1
C731 0.01U_0402_16V7K
20mil
Issued Date
+3VALW
ECAGND 2
L85
1
BLM18AG601SN1D_2P
+3VALW
2
R529
1
R528 @
R459
3S/4S#
R460
BATT_OVP <46>
ADP_I
<46>
SPI Device Interface
SM Bus
1
100K_0402_5%
1
100K_0402_5%
2
4.7K_0402_5%
+3VALW
83
84
85
86
87
88
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
15P_0402_50V8J
32.768KHZ_12.5PF_Q13MC14610002
ACOFF
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
PS2 Interface
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
C740
ACOFF
BATT_TEMP
BATT_OVP
ADP_I
AD_BID0
AD_PID0
11
24
35
94
113
2
1
15P_0402_50V8J
1
122
123
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_CRY2
C739
A
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
VR_ON
VGA_DBCLK <22>
BEEP#
<39>
BEEP#
63
64
65
66
75
76
GND
GND
GND
GND
GND
EC_CRY1
EC_CRY2
EC_CRY1
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
21
23
26
27
PWM Output
DA Output
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
MINI1_LED#
LOCAL_DIM
COLOR_ENG_EN
EC_INVT_PWM
FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PWR_SUSP_LED
WLAN_LED#
<34> MINI1_LED#
<23> LOCAL_DIM
<23> COLOR_ENG_EN
<23> EC_INVT_PWM
<41> FAN_SPEED1
<35>
BT_ON#
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
AD
R458
VGA_DBCLK
EC must program to 500KHZ output
Start and stop follow SUP high/Low
2
R461
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
65W/90W#
1
2
3
4
5
7
8
10
ACES_85205-0400
@
AGND
<27> EC_GA20
<27> EC_KBRST#
<26>
SERIRQ
<26> LPC_FRAME#
<26>
LPC_AD3
<26>
LPC_AD2
<26>
LPC_AD1
<26>
LPC_AD0
69
C732
@ 22P_0402_50V8J
2
1
EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
0.1U_0402_16V4Z
E51RXD_P80CLK <34>
E51TXD_P80DATA <34>
+3VALW
VCC
VCC
VCC
VCC
VCC
VCC
U26
KSI[0..7]
Place on MiniCard door
E51RXD_P80CLK
E51TXD_P80DATA
KSI[0..7]
2
2
0.1U_0402_16V4Z
C729
1000P_0402_50V7K
2
2
0.1U_0402_16V4Z
KSO[0..17] <37>
C728
1000P_0402_50V7K
1
1
1
2
3
4
1
2
3
4
KSO[0..17]
C727
JP7
C726
+3VALW
1
2+EC_VCCA
BLM18AG601SN1D_2P
1
0.1U_0402_16V4Z
1
2
ECAGND
0.1U_0402_16V4Z
1 C725
1
C724
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet
1
36
of
55
+5VS
+5VS
JTP1
2 0.1U_0402_16V4Z
+SPI_VCC
1
3
7
4
CS#
WP#
HOLD#
GND
8
6
5
2
VCC
SCLK
SI
SO
EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R
R481 1
R483 1
R484 1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
SW1
SMT1-05-A_4P
3
1
D11
D13
2
PJDLC05C_SOT23-3
1
5
6
+SPI_VCC
EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R
TP_DATA
PJDLC05C_SOT23-3
8
6
5
2
RIGHT_BTN#
SW2
SMT1-05-A_4P
3
1
5
6
U28 @
VDD
SCK
SI
SO
TP_CLK
LEFT_BTN#
CE#
WP#
HOLD#
VSS
0.1U_0402_16V4Z
RIGHT_BTN#
LEFT_BTN#
1
3
7
4
TP_CLK <36>
TP_DATA <36>
LEFT_BTN#
RIGHT_BTN#
ACES_85201-0605N
CONN@
EC_SPICLK <36>
EC_SO_SPI_SI <36>
EC_SI_SPI_SO <36>
MX25L1605DM2I-12G SOP 8P
SA00002TO00
EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#
C745
1
2
3
4
5
6
EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI_WP#
2 4.7K_0402_5% SPI_HOLD#
R480 1
R482 1
+3VALW
7
8
U27
<36> EC_SPICS#/FSEL#
1
2
3
4
5
6
GND
GND
C742 1
2
0_0603_5%
1
R479
+3VALW
MX25L1005AMC-12G_SOP8
@
R485
1
0_0402_5%
@
C746
33P_0402_50V8K
Right side
Left side
JLED2
1
2
3
4
5
6
7
8
9
10
GND
GND
JKB1
28
27
KSI[0..7]
KSO[0..17]
<36>
KSO[0..17] <36>
100P_0402_50V8J
C751 1
100P_0402_50V8J
KSO6
C752 1
100P_0402_50V8J
KSO13
C753 1
100P_0402_50V8J
KSO5
C754 1
100P_0402_50V8J
KSO12
C755 1
100P_0402_50V8J
KSO4
C756 1
100P_0402_50V8J
KSI0
C757 1
100P_0402_50V8J
KSO3
C758 1
100P_0402_50V8J
KSO11
C759 1
100P_0402_50V8J
KSI4
C760 1
100P_0402_50V8J
KSO10
C761 1
100P_0402_50V8J
KSO2
C762 1
100P_0402_50V8J
KSI1
C763 1
100P_0402_50V8J
KSO1
C764 1
100P_0402_50V8J
R487
100K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
C771 1
100P_0402_50V8J
KSO8
KSO0
C766 1
100P_0402_50V8J
KSI5
C768 1
100P_0402_50V8J
KSI6
C770 1
100P_0402_50V8J
C772 1
100P_0402_50V8J
KSI7
2
1
5
+3VS
5IN1_LED# <35>
SATA_LED# <28>
1 7585@ 2
2
R477
2.2K_0402_5%
NEW95 LED Option
2 95@ 1
R477
680_0402_5%
PWR_LED#
2 95@ 1
R478
680_0402_5%
Change to SC591NB5A30 for BC bin

LED2
HT-191UD5_AMBER
+3VALW
1 7585@ 2
2
R478
3.9K_0402_5%
+3VALW
1 7585@ 2
2
R499
2.2K_0402_5%
2 95@ 1
R499
680_0402_5%
PWR_SUSP_LED#
2 95@ 1
R498
680_0402_5%
PWR_SUSP_LED#
LED3
HT-191NB5_BLUE
Q26B
5
2
C769 1
LED1
HT-191NB5_BLUE
Q26A
<36> PWR_LED
<36> PWR_SUSP_LED
C767 1
3
100P_0402_50V8J
KSI3
MEDIA_LED#
2N7002_SOT23
1
3
100P_0402_50V8J
KSO9
100K_0402_5%
U29
B 2
2
2
100P_0402_50V8J
C747 1
C750 1
Q71
PWR_LED#
KSO16
C748 1
C765 1
R486
2
G
<16,36,42,43> ACIN
KSO7
KSI2
+3VS
PWR_LED#
ON/OFFBTN#
ACES_85201-1005N
CONN@
+3VS
KSO17
KSO14
ON/OFFBTN# <38>
+3VS
100P_0402_50V8J
C749 1
3G_LED# <36>
WLAN_LED# <36>
+3VS
+3VALW
LID_SW#
ACIN_LED#
3G_LED#
WLAN_LED#
MEDIA_LED#
ACIN_LED#
KSO15
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
GND
GND
ACES_85201-1005N
CONN@
ACES_88747-2601
CONN@
KSI[0..7]
PWR_LED#
ON/OFFBTN#
+3VALW
LID_SW# <36>
R490
100K_0402_5%
BATT_BLUE_LED#
BATT_BLUE_LED# <36>
Change to SC591NB5A30 for BC bin

LED4
HT-191UD5_AMBER
+3VALW
1 7585@ 2
2
R498
3.9K_0402_5%
BATT_AMB_LED#
2008/10/06
Deciphered Date
BATT_AMB_LED# <36>
Compal Secret Data
Issued Date
(Right)
KSO0
G2
KSO1
G1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LID_SW#
ACIN_LED#
3G_LED#
WLAN_LED#
MEDIA_LED#
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
(Left)
JLED1
1
2
3
4
5
6
7
8
9
10
11
12
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet
37
of
55
ON/OFF switch
PX MODE SELECT CONTROL
Power Button
<AMD Suggestion>
+3VS
EN1
<13>
D
Q70
@
S 2N7002_SOT23
2
G
AUX0N
EN1
<26>
1000P_0402_50V7K
1
PX_EN#
EC_ON
S 2N7002_SOT23
<13,23> GMCH_LCD_DATA
Q75A @
3
Q75B
@
Q27
2
G
Q73B
@
Pop for PX verify
EN1#
2
Q73A
@
C773
PE_GPIO2 <23>
<43>
<36>
51ON#
ON/OFF
3
DAN202UT106_SC70-3
EC_ON
ON/OFFBTN# <37>
<36>
R324
1.8K_0402_5%
Q74A
@
Q74B @
SG@ 2
6
1
4
3
1
R513
0_0402_5%
D12
1
EN1#
6
5
SG@
RB751V_SOD323
2
D46
1
<26> INT_VGA_EN#
R502
Bottom Side
ON/OFFBTN#
100K_0402_5%
@
R500
100K_0402_5%
@
SW3
SMT1-05-A_4P
1
3
100K_0402_5%
@
INT_VGA_EN# keeps HIGH if PX is enable
R495
1
2
@ 10K_0603_5%
+3VS
+3VS
R494
2
@ 10K_0603_5%
R493
1
+3VALW
TOP Side
AUX0N
R496
@
1
R514
PE_GPIO2
2
0_0402_5%
Verify only
10K_0402_5%
PX_EN#
AUX0N
EDP_DISABLED
I2C_DATA
EDP_ENABLED
INT_VGA_EN#
DISPLAY OUTPUT
IGP only mode
IGP( LVDS,EDP,VGA,DP)
VGA only mode
VGA( LVDS,EDP,CRT,DP)
PX (MUXED)
0/1
0/1
PX (MUXLESS)
VGA/IGP(CRT, LVDS, EDP); MXM(DP)
VGA Power ON Circuit

+3VALW
For PX sequence and internal clock mode, VGA

PWR need ramp up after SB_CLK oscillate
I
G
U30B
SN74LVC14APWLE_TSSOP14
14
U30A
14
+3VALW
IGP( LVDS,EDP,CRT,DP)
SB_PWROK
3
+3VALW
Delay EC_PWROK 50ms

for VGA criterial
38ms
+3VALW
U30D
VGAPWR_ON
VGA_PWR_ON_L
GPIO1_DELAY
For PX sequence, >1mS delay is required between

PE_GPIO1 and VGA_PWR_ON
2
+3VS
+3VALW
R509
0_0402_5%
DISO@
+3VALW
14
U30F
PE_GPIO1
For VGA Power on control
>1ms
14
10
13
O
7
O
G
2
C778
U30E
2
11
D Q66
SG@
2
G
2N7002_SOT23
S
0.1U_0402_16V4Z
1
12
1
R505
SG@ 2
0_0402_5%
Pop for PX verify
VGA_PWR_ON <42,50,51>
2
VGA_PWR_ON
C777
0.1U_0402_16V4Z
@
<42> PE_GPIO1#
2 0.1U_0402_16V4Z
R415
31.6K_0402_1%
@
C776
R414 SG@
10K_0402_1%
1
2
50ms
0.1U_0402_16V4Z
<22,36,42,50> VGA_ON
1
2
R501
0_0402_5%
2
EXT@
C775
14
U30C
14
INT@
1
2
R512
0_0402_5%
<36> INT_VGAPWR_ON
<26,42> PE_GPIO1
SB_CLK
D Q76
INT@
2
G
2N7002_SOT23
S
3
GPIO1_DELAY
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
Size
B
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet

E
38
of
55
+3VS
1
R784
+VDDA
2
0_0805_5%
+5VAMP
FBMA-L11-201209-221LMA30T_0805
MONO_IN
1
R786
2
2
HD Audio Codec
C
2
2.4K_0402_1%
Q72
2
B
0.1U_0402_16V4Z
C952 1
1U_0402_6.3V4Z
BEEP#
0.1U_0402_16V4Z
C936
1
1U_0402_6.3V4Z
22U_0805_6.3V6M
<36>
R787
FBMA-L11-201209-221LMA30T_0805
L88 1
2
C947
RB751V_SOD323
1
U81
60mil
2
C899
R789
10K_0402_5%
C678
D38
L87
+5VS
R783
20K_0402_1%
40mil
IN
GND
SHDN
OUT
BYP
+VDDA
4.75V
1
2
C949
0.01U_0402_25V7K
@ G9191-475T1U_SOT23-5
(output = 300 mA)
560_0402_5%
2SC2411KT146_SOT23-3
SB_SPKR
R788
560_0402_5%
<27>
C946 1
1U_0402_6.3V4Z
D37
RB751V_SOD323
L82
BLM18AG601SN1D_2P
1
2
1
+AVDD_HDA
2
R523
C794 1
1INT_MIC_2
1K_0402_1%
C797 1
+3VS
MIC2_VREFO
C926
10U_0805_10V4Z
R585
2.2K_0402_5%
0.1U_0402_16V4Z
2
C945
MIC2_C_L
2
4.7U_0805_10V4Z
MIC2_C_R
2
4.7U_0805_10V4Z
35
AMP_LEFT
LINE2_R
LOUT_R
36
AMP_RIGHT
MIC2_L
LOUT2_L
39
MIC2_R
LOUT2_R
41
45
LINE2_L
15
16
17
AMP_LEFT <40>
JP1
INT_MIC
15mil
23
LINE1_L
SPDIFO2
24
LINE1_R
DMIC_CLK1/2
46
18
LINE1_VREFO
NC
43
20
LINE2_VREFO
DMIC_CLK3/4
19
MIC2_VREFO
<27> HDA_SDOUT_AUDIO
R794 2
R795 2
<40> MIC_PLUG#
<40> HP_PLUG#
<36>
1 20K_0402_1%
1 5.11K_0402_1%
1
R796
EAPD
SENSE_A
SENSE_B
2
0_0402_5%
PCBEEP_IN
MONO_OUT
37
CBP
29
CPVEE
31
MIC1_VREFO
28
RESET#
SYNC
SDATA_OUT
2
3
13
34
GPIO0/DMIC_DATA1/2
GPIO1/DMIC_DATA3/4
SENSE A
SENSE B
47
EAPD
48
4
7
SPDIFO1
HPOUT_R
32
CBN
30
VREF
27
JDREF
40
HPOUT_L
33
AVSS1
AVSS2
26
42
DVSS1
DVSS2
1
R793
2
33_0402_5%
10mil
1
MIC1_VREFO
HP_RIGHT
CODEC_VREF
HP_RIGHT
C954
2.2U_0402_6.3V6M
SENSE A
4
SENSE B
Codec Signals
LOUT2
20K
PORT-B (PIN 21, 22)
MIC1
10K
PORT-C (PIN 23, 24)
LINE1
5.1K
PORT-D (PIN 35, 36)
LOUT1
39.2K
PORT-E (PIN 14, 15)
LINE2
20K
PORT-F (PIN 16, 17)
1
HP_LEFT
AGND
MIC2
PORT-I (PIN 32, 33)
HP
5.1K
1
R798
2
0_0805_5%
1
R799
2
0_0805_5%
1
R804
2
0_0805_5%
1
R816
2
0_0805_5%
1
R818
2
0_0805_5%
1
R817
2
0_0805_5%
GND
10K
GNDA
GND
2008/10/06
2010/03/12
Deciphered Date
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Date:
Title
Size
B
A
GNDA
Compal Secret Data
Issued Date
HP_LEFT <40>
10mil
Function
PORT-A (PIN 39, 41)
HP_RIGHT <40>
HP_LEFT
ALC272X
39.2K
PJDLC05C_SOT23-3
2.2U_0402_6.3V6M
C951 1
ALC272-VA2-GR_LQFP48_7X7
Impedance
G1
G2
HDA_SDIN0 <27>
Change to ALC272X
DGND
Sense Pin
3
4
MIC1_R
C937
10
<27> HDA_SYNC_AUDIO
1
2
<27>
MIC1_L
0.1U_0402_16V4Z
11
<27> HDA_RST_AUDIO#
SDATA_IN
For EMI
HDA_BITCLK_AUDIO
C927
C932 1
2 C948
22P_0402_50V8J
2
1
0_0402_5%
10U_0805_10V4Z
MIC1_R
BITCLK
1
R792
MIC1_R
MIC1_C_L
21
4.7U_0805_10V4Z
MIC1_C_R
22
2
4.7U_0805_10V4Z
MONO_IN
12
2
44
6
1
2
ACES_88266-02001
CONN@
20K_0402_1%
MIC1_L
<40>
C934 1
D27
R797
<40>
MIC1_L
C808
220P_0402_50V7K
AMP_RIGHT <40>
MIC2_VREFO
LOUT1_L
14
Close to Conn
INT_MIC
DVDD
U82
DVDD_IO
2
0.1U_0402_16V4Z
38
C953
INT_MIC
25
C950
10U_0805_10V4Z
AVDD1
1
2
BLM18AG601SN1D_2P
+VDDA
40mil
AVDD2
0.1U_0402_16V4Z
1
1
C935
C933
L86
+3VS_DVDD
0.1U_0402_16V4Z
10mil

G
Sheet
39
H
of
55
GAIN0 GAIN1 AV(inv)

0
6dB
0
1
10dB
0
1
0
15.6dB
1
1
21.6dB
Ri
90k
70k
45k
25k
+5VAMP
0.1U_0402_16V4Z
1
C959
10U_0805_10V4Z
Int. Speaker Conn.
1
C960
JSPK2
C955 1
C971
1
2
<39> AMP_LEFT
1
R828
2 0.47U_0603_10V7K
AMP_C_LEFT
2
0_0603_5%
18
SPKR+
ROUT-
14
SPKR-
LOUT+
@ R825
100K_0402_5%
LOUT-
Left
JSPK1
SPKR+
SPKR-
R831 1
R832 1
2 0_0603_5%
2 0_0603_5%
20mil
SPK_R+
SPK_R-
SPKL+
1
2
1
2
D41
3
4
G1
G2
SPKL-
Right
ACES_88266-02001
CONN@
PJDLC05C_SOT23-3
SCA00001100
1
G1
G2
ACES_88266-02001
CONN@
LIN-
3
4
R826
100K_0402_5%
LIN+
0.47U_0603_10V7K
1
2
ROUT+
GAIN1
1
1
2
0.47U_0603_10V7K
GAIN1
RIN-
AMP_C_RIGHT 17
2
0_0603_5%
GAIN0
GAIN0
1
R830
RIN+
@
PJDLC05C_SOT23-3
SCA00001100
<39> AMP_RIGHT
SPK_L+
SPK_L-
D39
@ R829
100K_0402_5%
C957
1
2
2 0.47U_0603_10V7K
1
16
15
6
R827
100K_0402_5%
VDD
PVDD1
PVDD2
C958 1
2 0_0603_5%
2 0_0603_5%
20mil
+5VAMP
U83
R834 1
R833 1
SPKL+
SPKL-
10 dB
19
NC
12
BYPASS
10
SHUTDOWN
Keep 10 mil width

2
GND5
GND1
GND2
GND3
GND4
<36> EC_MUTE#
EC_MUTE#
C956
0.47U_0603_10V7K
21
20
13
11
1
TPA6017A2_TSSOP20
C779
330P_0402_50V7K
<39> HP_LEFT
R686 1
2 56.2_0603_1%
HPOUT_L_1
<39> HP_RIGHT
R685 1
2 56.2_0603_1%
HPOUT_R_1
1
L94
1
L93
C774
Headphone Out
330P_0402_50V7K
1
JHP1
1
2
HPOUT_L_2
2
FBMA-L11-160808-700LMT_2P
HPOUT_R_2
2
FBMA-L11-160808-700LMT_2P
3
4
HP_PLUG#
<39> HP_PLUG#
6
SINGA_2SJ-0960-C01
CONN@
MIC_PLUG#
<NAL00 use>
HP_PLUG#
MIC1_VREFO MIC1_VREFO
MIC1_R
R695 1
1
C780
220P_0402_50V7K
JMIC1
4.7K_0402_5%
L89 1
2
FBMA-L11-160808-700LMT_2P
L90 1
2
FBMA-L11-160808-700LMT_2P
MIC1_L_R
1
2
MIC1_R_R
<39>
MIC1_L_1
2
1K_0603_1%
MIC1_R_1
2
1K_0603_1%
R694 1
MIC JACK
R693
2
R692
4.7K_0402_5%
MIC1_L
PJDLC05C_SOT23-3
SCA00001100
D42
RB751V_SOD323
1 1
1 1
D43
RB751V_SOD323
<39>
C781
220P_0402_50V7K
<39> MIC_PLUG#
MIC_PLUG#
@
D29
PJDLC05C_SOT23-3
SCA00001100
SINGA_2SJ-A960-C01
CONN@
D24
<NAV70 use>
2008/10/06
Issued Date
Compal Secret Data
2010/03/12
Deciphered Date
Title
Size
B
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet

E
40
of
55
FAN1 Conn
+5VS
+5VS
1
10U_0805_10V4Z
2
C821
1
2
0_0402_5% 1
C822
EN
VIN
VOUT
VSET
8
7
6
5
+3VS
C824
1000P_0402_50V7K
1
2
0.01U_0402_25V4Z
@ D26 BAS16_SOT23-3
1
2
C823
10U_0805_10V4Z
1
2
APL5607KI-TRG_SO8
@
2
GND
GND
GND
GND
R568
10K_0402_5%
CONN@
ACES_85205-03001
LDO FAN
2008/10/06
H13
H_3P0N
FD4
FD3
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FIDUCIAL_C40M80
Deciphered Date
H23
H_4P2
H17
H_3P0X3P5N
H10
H_3P0
H22
H_4P2
H9
H_3P0
H21
H_4P2
H20
H_4P2
Compal Secret Data
H8
H_3P0
H7
H_3P0
FD2
1
H18
H_3P4
H6
H_3P0
FD1
Issued Date
H24
H_3P0
H5
H_3P0
H15
H_4P0
H19
H_3P0
H12
H_3P0
H14
H_4P0
H4
H_3P0
H11
H_3P0
H2
H_3P0
H1
H_3P0
C825
1000P_0402_50V7K
1
2
3
JFAN1
<36> FAN_SPEED1
+VCC_FAN1
40mil
2
1
R567
U35
1
2
3
4
+VCC_FAN1
<36> EN_DFAN1
D25
1SS355_SOD323-2
@
R566
0_0603_5%
@
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet
41
of
55
S
2
2
1
3
2
1
1
3
R580
10K_0402_5%
2
2
R572
VGA@
470_0603_5%
R589
100K_0402_5%
PE_GPIO1#
<38> PE_GPIO1#
2VGA_PWR_ON#
G
Q32
2N7002_SOT23
VGA@
C832
C833
VGA@
VGA@
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z
<26,38> PE_GPIO1
Q67
2N7002_SOT23
R609
100K_0402_5%
C835
VGA@
0.1U_0603_25V7K
2
G
+5VALW
Q49
VGA@
2N7002_SOT23
R602
100K_0402_5%
ACIN 2
G
Q35
2N7002_SOT23
2
1
2
G
C848
VGA@
0.1U_0603_25V7K
R313
470_0603_5%
2
10U_0805_10V4Z
D
VGA@
2
G
Q34
S
1 2N7002_SOT23
2
G
VGA@
VGA_PWR_ON# 2 VGA@ 1
R503 47K_0402_5%
10U_0805_6.3V6M
2
<22,36,46> SUSP#
+5VALW
1
2
3
+1.5VS
C690
1
1
1
C831
8
7
6
5
1.5VSG_GATE
1 VGA@ 2
R575
100K_0402_5%
100K_0402_5%
Q42
2N7002_SOT23
3
10U_0805_10V4Z
R314
0.1U_0603_25V7K
+VSB
1
C830
VGA@
C843
Q59
2
G
R586
10K_0402_5%
+1.5VSG
SUSP
SUSP
U37
VGA@
AO4430L_SO8
2 SUSP
G
Q36
2N7002_SOT23
+1.5VS
+1.5V
<22,49>
VGA_ON#
VGA_ON#
2
Q38G
2N7002_SOT23
R576
100K_0402_5%
<22>
+1.5V
SUSP
0.1U_0603_25V7K
C836
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z
+5VALW
+1.5V to +1.5VSG
R579
470_0603_5%
Q30
2N7002_SOT23
R573
100K_0402_5%
2
G
SYSON
+5VALW
<36,47>
R584
10K_0402_5%
2
1
3VS_GATE
1
200K_0402_5%
2
R582
+VSB
C842
SYSON#
SYSON#
R587
100K_0402_5%
510K_0402_5%
10U_0805_10V4Z
2
2
10U_0805_10V4Z
Q40
2N7002_SOT23
2
G
C844
Q48
2N7002_SOT23
VGA@ R596
2
1
2VLDT_EN#
G
Q37
2N7002_SOT23
<22,36,38,50> VGA_ON
1 1
C841
U39
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5
4
ACIN 2
G
<16,36,37,43> ACIN
+3VS
+3VALW
C840
<35>
D
1
R595
S
1 2
+3VALW TO +3VS
VLDT_EN# 2
Q39G
2N7002_SOT23
<36,48> VLDT_EN
300K_0402_5%
0.1U_0603_25V7K
1.1VS_GATE
2
47K_0402_5%
1
R581
+VSB
VLDT_EN#
470_0603_5%
C834
1
2
10U_0805_10V4Z
R578
1
SUSP
2
Q33G
2N7002_SOT23
2 SUSP
G
Q31
2N7002_SOT23
5VS_GATE
2
100K_0402_5%
1
R574
+VSB
C839
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z
C838
R577
C837
1K_0402_5%
R571
470_0603_5%
R570
100K_0402_5%
R583
100K_0402_5%
1
2
3
C829
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z
10U_0805_10V4Z
2
2
10U_0805_10V4Z
+1.1VS
8
7
6
5
2
C827
C828
+1.1VALW
+5VALW
U38
AO4430L_SO8
C826
+5VALW
+1.1VALW TO +1.1VS
+5VS
U36
8
1
7
2
6
3
5
+5VALW
+5VALW TO +5VS
VGA_PWR_ON#
S
SSM3K7002FU_SC70-3
+1.8VS to +1.8VSG
<38,50,51> VGA_PWR_ON
1
C691
0.22U_0603_16V4Z2
+CPU_VDDR
2
2
1
VGA_PWR_ON 1
10K_0402_5%
2
R607 1
C846
VGA@
2
0.1U_0603_25V7K
2
G
C234
R112
470_0603_5%
VGA@
10U_0805_6.3V6M
2
D
VGA@
Q8
VGA@
2 VGA_PWR_ON#
G
Q7
2N7002_SOT23
S
SSM3K7002FU_SC70-3
4
1
D
2 VLDT_EN#
G
Q56
2N7002_SOT23
2 VLDT_EN#
G
Q69
2N7002_SOT23
Compal Secret Data

2008/10/06
Issued Date
2010/03/12
Deciphered Date
Title
Size
B
Date:
2
1
2
R611 33K_0402_5%
VGA@
Q60
@
2N7002_SOT23
VGA@
R114
VGA@
100K_0402_5%
C849 1
VGA@
0.1U_0603_25V7K
2
3VSG_GATE
+3VSG
510K_0402_5%
D
C852
VGA@
0.1U_0603_25V7K
1
S
2
G
Q43 VGA@
2N7002_SOT23
R610
470_0603_5%
D
2 SUSP
G
2N7002_SOT23
Q45
R604
470_0603_5%
1
D
2 SUSP
G
Q44
2N7002_SOT23
D
2 SYSON#
G
Q57
2N7002_SOT23
R591
470_0603_5%
1
1
R590
470_0603_5%
R605
470_0603_5%
Q58
+3VS
+0.75VS
@ R606
1
VGA_PWR_ON# 2 VGA@ 1
2
R489 100K_0402_5%
G
Q47
S
1
2N7002_SOT23
VGA@
C692
VGA@
2
0.1U_0603_25V7K
+NB_CORE
ACIN 2
G
1.8VSG_GATE
2 VGA@ 1
R510 100K_0402_5%
2 VGA_ON#
G
Q46
2N7002_SOT23
1
3
2
1
1
1
+2.5VS
+3VSG
3VSG_GATE
+1.5V
D
2 VGA_PWR_ON#
G
Q55
2N7002_SOT23
VGA@
R594
VGA@
470_0603_5%
1
1
C855
VGA@
C853
10U_0805_10V4Z
2
2 VGA@
1U_0402_6.3V4Z
VGA_PWR_ON#
D
2 VGA_PWR_ON#
G
Q51
2N7002_SOT23
VGA@
VGA@ VGA@
2
2
10U_0805_10V4Z 10U_0805_10V4Z
R592
470_0603_5%
+VSB
D
C854
Q68
2N7002_SOT23
R603
470_0603_5%
VGA@
R598
470_0603_5%
VGA@
C856
+1.8VSG
U45
VGA@
8
1
7
2
6
3
5
4
+1.8VS
+VGA_CORE
+1.0VSG
2
G
R608
100K_0402_5%
+1.8VS
VGA_ON#
2
G
Q10
2N7002_SOT23
Q9
2
G
R511
2
1
47K_0402_5%
VGA_ON
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet

E
42
of
55
PR1
1M_0402_1%
1
2
VIN
VIN
VIN
PC1
PR7
1000P_0402_50V7K
20K_0402_1%
PC2
0.1U_0603_25V7K
PR8
10K_0402_5%
PC6
1000P_0402_50V7K
LM393DR_SO8
1
PC5
100P_0402_50V8J
PD1
RLZ4.3B_LL34
PC4
100P_0402_50V8J
1
PC3
1000P_0402_50V7K
PJP1
P
PACIN
<BOM Structure>
<16,36,37,42> ACIN
PR4
22K_0402_5%
1
2
PU1A
PR5
10K_0402_1%
1
2
DC_IN_S1
1
2
3
4
5
6
PR3
84.5K_0402_1%
PL1
SMB3025500YA_2P
1
2
1
2
3
4
GND
GND
PR2
10K_0402_5%
SP02000GC00
ACES_50305-00441-001
VS
PR9
10K_0402_5%
1
2
RTCVREF
<46,49> PACIN
Vin Dectector
Min.
H-->L 16.976V
L-->H 17.430V
Typ
17.525V
17.901V
Max.
17.728V
18.384V
PJ32
1
+1.0VSG
+RTCBATT
+RTCBATT
PJ29
ML1220T13RE
45@
@ PC130
@PC130
0.1U_0402_16V7K
+3VALW
<38> 51ON#
+5VALW
+1.1VALWP
@ PC8
@PC8
0.1U_0402_16V7K
+1.1VALW
PJ11
1
+VSB
JUMP_43X39
+0.75VSP
@ PC10
@PC10
0.1U_0402_16V7K
+0.75VS
3
(3A,120mils ,Via NO.=6)
(120mA,40mils ,Via NO.= 2)
JUMP_43X118
+1.5VP
1
+NB_CORE
JUMP_43X118
@PC12
@
PC12
0.1U_0402_16V7K
+1.5V
PJ19
2
PC14
0.1U_0603_25V7K
JUMP_43X118
@ PC15
@PC15
0.1U_0402_16V7K
+NB_COREP
JUMP_43X118
TP0610K-T1-E3_SOT23-3
(9.5A,400mils ,Via NO.=20)

PJ9
PU2
+2.5VS
@ PC69
@PC69
0.1U_0402_16V7K
PC18
1U_0805_25V4Z
+VGA_CORE
JUMP_43X118
PJ13
2 2
1 1
+CPU_VDDRP
PC70
0.1U_0402_25V6
PJ21
JUMP_43X39
1
2 2
+CPU_VDDR
+VGA_COREP
(1.5A,60mils ,Via NO.= 3)

1
GND
G920AT24U_SOT89-3
PC17
1
10U_0805_10V4Z
PJ20
2
2
IN
N2
OUT
3.3V
JUMP_43X39
PR15
200_0603_5%
PR17
560_0603_5%
1
2
@PC16
@
PC16
0.1U_0402_16V7K
RTCVREF
+CHGRTC
(5.2A,220mils ,Via NO.=11)
+2.5VSP
PR16
560_0603_5%
1
2
JUMP_43X118
PJ8
VS
1
2
PJ26
1
PJ6
PC13
0.22U_0603_25V7K
PR14
22K_0402_1%
1
2
+1.8VS
2
1
3
1
PR13
100K_0402_1%
PQ1
N1
PC11
0.1U_0402_25V6
JUMP_43X118
PJ5
PR11
68_1206_5%
2
PR12
200_0603_5%
1
2
JUMP_43X118
(5A,200mils ,Via NO.= 10)
+VSBP
1
PR10
68_1206_5%
CHGRTCP
+1.8VS
@ PC71
@PC71
0.1U_0402_16V7K
PJ3
2
@ PC9
@PC9
0.1U_0402_16V7K
PD2
RLS4148_LL34-2
PD3
RLS4148_LL34-2
+1.8VSP1
2
(3.9A,160mils ,Via NO.= 8)
+5VALWP

PJ22
JUMP_43X118
VIN
BATT+
JUMP_43X118
PJ1
2
+3VALWP
@ PC7
@PC7
0.1U_0402_16V7K
+1.8VSP2
2
JUMP_43X118
@PC148
@
PC148
0.1U_0402_16V7K
+1.0VSGP
PBJ1
JUMP_43X118
(25A,1000mils ,Via NO.=50)
Issued Date
Compal Secret Data
2007/09/20
Deciphered Date
2010/03/12
Title
Custom
Date:
SCHEMATIC, MB A5911
Rev
D
401827

D
Sheet
43
of
55
PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
VL
1
<40,41>
BATT+
OT1 TMSNS2
OT2 RHYST2
PR30
9.53K_0402_1%
PH1
G718TM1U_SOT23-8
100K_0402_1%_NCP15WF104F03RC
PR261
1K_0402_5%
@PR169
@
PR169
PR24
6.49K_0402_1%
2
1
PR28
21K_0402_1%
47K_0402_1%
+3VALWP
MAINPWON <8,45,49>
PR33
1K_0402_1%
BATT_TEMP <36>
PH2 @
100K_0402_1%_NCP15WF104F03RC
1
2
EC_SMB_CK1 <36>
PC19
0.01U_0402_25V7K
GND RHYST1
VCC TMSNS1
4
PC20
1000P_0402_50V7K
2
1
PL2
SMB3025500YA_2P
1
2
BATT_S1
EC_SMB_DA1 <36>
PR32
100_0402_1%
PR21 @
100K_0402_1%
CONN@
PU3
PJP2
SUYIN_200275GR008G13GZR
PR27
10K_0402_1%
<40,41>
VMB
PC21
0.1U_0603_25V7K
PR29
100_0402_1%
EC_SMCA
TH
PI
VL
EC_SMDA
10
9
8
7
6
5
4
3
2
1
GND
GND
8
7
6
5
4
3
2
1
+VSBP
1
PC25
0.1U_0603_25V7K
VL
1
PR34
100K_0402_1%
PC24
0.22U_0603_25V7K
PQ3 TP0610K-T1-E3_SOT23-3
B+
PR36
22K_0402_1%
PR39
0_0402_5%
2
PQ4
2N7002W-T/R7_SOT323-3
2
G
<45,47> SPOK
PC27
0.1U_0402_16V7K
PR38
100K_0402_1%
Issued Date
Compal Secret Data
2007/09/20
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827

D
Sheet
44
of
55
TPS51427_B+
TPS51427_B+
5
6
7
8
PC29
4.7U_0603_6.3V6M
2
1
3
2
1
22
VOUT1
10
FB1
11
VSW
VOUT2
VL
32
REFIN2
2VREF_TPS51427
1
PC47
FB5
LDOREFIN
@PR59
@
PR59
2
29
PR45
1
20
PGOOD1
13
TRIP1
12
TRIP2
31
2
1
GND
0_0402_5%
1
VL
0_0402_5%
2
SPOK
<44,47>
PR60
330K_0402_1%
2
1
ILIM2
SN0806081RHBR_QFN32_5X5
PR57
294K_0402_1%
B
PR53
0_0402_5%
2VREF_TPS514272
1
2
PC38
0.047U_0402_16V7-K
21
EN2
TONSE
EN1
27
VREF3
14
@ PR55
@PR55
47K_0402_5%
1
2
PR54
0_0402_5%
2
EN_LDO
PC143
1U_0603_10V6K
1
2
2
2
28
@ PR56
@PR56
0_0402_5%
PR52
806K_0603_1%
<8,44,49> MAINPWON
PGOOD2
2
PR51
0_0402_5%
2
VL
NC
2
PC44
0.22U_0603_25V7K
2VREF_TPS514271
PD16
1SS355_SOD323-2
PR58
200K_0402_5%
1
2
PR46
100K_0402_1%
2
VS
VREF2
SKIPSEL
PD17
GLZ5.1B_LL34-2
1
2
0.22U_0603_10V7K
8
+3.3VALWP Ipeak=5.9A ; Imax=4.1A;Iocp=6.6A

Choke DCRmax=23m ohm,
Rds(on)=18m ohm(max) ; Rds(on)=15m
ohm(typical)
Vlimit=(5E-06 * 294K)/10=147mV
Ilimit=147mV/18m ~ 147mV/15m
=8.17A ~ 9.8A
Delta I=1.94A (Freq=300KHz)
Iocp=Ilimit+Delta I/2
=9.14A ~ 10.77A
PGND
30
+ PC35
220U_6.3V_M
FB3
@ PR44
@PR44
10K_0402_1%
DL5
DRVL2
PR49
66.5K_0402_1%
18
23
4.7_1206_5%
DRVL1
LL2
DL3
25
PQ8
AO4712_SO8
680P_0402_50V7K
LX5
PC42
0.1U_0603_25V7K
LX3
PR43
LL1
16
DH5
PR47 2.2_0603_5%
BST5A 2
1
17
PC34
2
15
VBST1
5
6
7
8
7
LDO
3
V5FILT
VIN
DRVH1
VBST2
3
2
1
PC41
1U_0603_10V6K
1
2
2
DRVH2
24
PC43
0.1U_0603_25V7K
1
2
3
1
PC37
680P_0402_50V7K
26
DH3
PR40
2
1 BST3A
2.2_0603_5%
19
PC36
1U_0603_10V6K
1
2
TP
PR42
0_0402_5%
PC39
220U_6.3V_M
PQ7
AO4712_SO8
+5VALWP
33
V5DRV
PL4
4.7UH_SIL1045R-4R7PF_6.3A_30%
2
1
PR41
4.7_1206_5%
PU4
PL3
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
+3VALWP
PC40
0.1U_0603_25V7K
PQ6
AO4466_SO8
4
PR48
0_0402_5%
2
8
7
6
5
PQ5
AO4466_SO8
4
VL
1
2
3
PC31
10U_1206_25V6M
PC120
2200P_0402_25V7K
PC122
2200P_0402_25V7K
JUMP_43X118
PC30
2200P_0402_50V7K
2
1
8
7
6
5
PC45
2200P_0402_50V7K
2
1
PC28
10U_1206_25V6M
PR50
0_0805_5%
1
2
PJ12
2
B+
+5VALWP Ipeak=7A ; Imax=5A;Iocp=8.4A

Choke DCRmax=23m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
Delta I=1.96A (Freq=400KHz)
Iocp=Ilimit+Delta I/2
=9.729A ~ 11.562A
@ PC46
@PC46
0.047U_0402_16V7K
PQ37
TP0610K-T1-E3_SOT23-3
2007/09/20
Issued Date
Compal Secret Data
Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5911
Custom
Date:
Rev
D
401827
Sheet
1
45
of
55
B+
Iada=0~4.74A(90W/19V=4.736A)
CP = 85%*Iada ; CP = 4.03A
CSOP
21
ICOMP
CSIN
20
CSIP
19
PHASE
CHLIM
UGATE
17
BOOT
16
DH_CHG
PR82
0_0603_5%
BST_CHG 1
ACLIM
VDDP
15
12.1K_0402_1%
20K_0402_1%
PR87
11
VADJ
LGATE
14
12
GND
PGND
13
1
3
DL_CHG
3
26251VDD
<40,41>
PQ57
4
PD12
RB751V-40TE17_SOD323-2
6251VDDP
PC61
2200P_0402_25V7K
2
1
PC48
0.1U_0603_25V7K
2
1
PC59
0.1U_0603_25V7K
BST_CHGA 2
1
10
PL5
10UH_PCMB104T-100MS_6A_20%
CHG
1
2
AO4466_SO8
VREF
6251aclim
PQ54
2
G
3
2
1
PR84
<36> 65W/90W#
PC51
10U_1206_25V6M
2
1
PC50
10U_1206_25V6M
2
1
18
PQ55
5
6
7
8
ICM
6251VREF
VCOMP
CSOP
PR86
4.7_0603_5%
BATT+
PR78 0.02_1206_1%
4
PC63
10U_1206_25V6M
2
1
CELLS
2 PACIN
2N7002W-T/R7_SOT323-3
G
S
CSON
PC53
0.047U_0603_16V7K
1
2
PR73
20_0402_5%
2
1
PR74
PC129
20_0402_5%
0.1U_0603_25V7K
1
2
PR76
2_0402_5%
LX_CHG
PQ23D
PC68
10U_1206_25V6M
2
1
22
PR80
4.7_1206_5%
CSON
PD11
1SS355TE-17_SOD323-2
1
2
PC128
680P_0402_50V7K
EN
AO4466_SO8
PR72
20_0402_5%
1
2
23
ACSET ACPRN
0.1U_0402_16V7K
6251VREF 1
PQ20
PDTC115EU_SOT323
24
PR67
200K_0402_1%
1
2 VIN
5
6
7
8
DCIN
PR83
100K_0402_1%
SUSP# <22,36,42>
wrong Value
PC127
0.1U_0603_25V7K
2
1
VDD
PR77
100_0402_1%
1
2
PC58
1
2
PR81
80.6K_0402_1%
2
1
SUSP#
VIN
PD8
1SS355TE-17_SOD323-2
ACOFF
1
2
FSTCHG <36>
3
2
1
2 10K_0402_1%
1
2
PC57
@ 100P_0402_50V8J
ADP_I
PR63
47K_0402_1%
1
2
1 1
1
1
PR71
2
DCIN
6251_EN
<36>
IREF
PU5
PC55
0.01U_0402_25V7K
PR79
22K_0402_5%
PACIN 1
2
ACOFF
1 PR75
PR85
2.55K_0402_1%
ACOFF
FSTCHG
BAS40CW_SOT323-3
6800P_0402_25V7K
2
ACON
PQ53
PDTC115EU_SOT323
<36,49>
D 2N7002W-T/R7_SOT323-3
1
<36>
PC54
1
2
1
100K_0402_1%
PACIN
1
2
PC67
0.1U_0402_16V7K
<43,49>
PR68
10K_0402_5%
2
1
3S/4S#
2
1
PC60
0.01U_0402_25V7K
2
1
ACON
6251VDD
8
7
6
5
PR65
10K_0402_1%
PD9
2
PQ56
2
G
PQ18
PDTC115EU_SOT323
PR66
2
PQ24
PDTC115EU_SOT323
<36>
3
<49>
PR70 47K_0402_5%
2
DCIN
100K_0402_1%
1
PR69
150K_0402_1%
PDTC115EU_SOT323
1
3
PQ22
2
G
2N7002W-T/R7_SOT323-3
1
2
3
CSIN
JUMP_43X118
P3
FSTCHG
PQ17 TP0610K-T1-E3_SOT23-3
3
PD10
1SS355TE-17_SOD323-2
1
6251VDD
CSIP
47K
PQ21
PR61
3 0.02_2512_1%
PR94
200K_0402_1%
PC56
5600P_0402_25V7K
1
2
4
1
2
PC62
0.1U_0603_25V7K
2
1
PQ19
PDTA144EU_SOT323-3
47K
2
PQ16
AO4407_SO8
PJ23
8
7
6
5
1
PR62
47K_0402_1%
CHG_B+
B+
P3
1
2
3
PQ15
AO4407_SO8
1
2
3
PC49
2.2U_0603_6.3V6K
2
1
P2
8
7
6
5
PR64
100K_0402_1%
2
1
PQ14
AO4407_SO8
VIN
PC52
0.1U_0603_25V7K
2
1
PC64
4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
2N7002W-T/R7_SOT323-3
VMB
1
VS
BATT-OVP=0.1112*VMB
8
+
6
PR93
105K_0402_1%
2
ADP_I = 19.9*3.42*0.95*0.02=1.29V
4
BATT Type
Charging Voltage
(0x15)
12600mV
CV mode
12.60V
Issued Date
Compal Secret Data
Normal 3S LI-ON Cells
PU18B
LM358DT_SO8
7 0
PR92
10K_0402_1%
1
2
<36> BATT_OVP
PR91
499K_0402_1%
2
Per cell=4.5V
CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.464V (90W), Iinput=4.03A
PR84=12.1K;PR87=20K
where Vaclm=0.391(65W), Iinput=2.91A
PR84=12.1K;PR85=2.55K
IREF=0.7224*Icharge
PR89
340K_0402_1%
LI-3S :13.5V----BATT-OVP=1.5012V
PC66
0.01U_0402_25V7K
PR90
31.6K_0402_1%
<36> CALIBRATE#
<40,41>
CP= 85%*Iada; CP=2.91A
PC65
0.01U_0402_25V7K
CP= 85%*Iada; CP=4.03A
Iada=0~3.42A(65W)
Iada=0~4.74A(90W)
PR88
15.4K_0402_1%
1
2
2007/09/20
Deciphered Date
2010/03/12
Title
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
SCHEMATIC, MB A5911
Rev
D

D
Sheet
46
of
55
PJ14
PQ25
PR96
255K_0402_1%
1
2
14
11
VDDP
10
LX_1.1VALW
PQ26
2
PR102
7.32K_0402_1%
LGATE
DL_1.1VALW
4
1
PGND
RT8209BGQW_WQFN14_3P5X3P5
2
PGOOD
GND
PR100
4.7_1206_5%
+5VALW
+1.1VALWP
FB
12
CS
1
+ PC76
330U_6.3V_M
PHASE
VDD
0.1U_0603_25V7K
VOUT
DH_1.1VALW
13
5
6
7
8
UGATE
PC80
4.7U_0805_10V6K
3
2
1
TON
BOOT
NC
1
EN/DEM
PC79
@ 47P_0402_50V8J
1
2
<Vo=1.1V> VFB=0.75V
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz
2
PC78
680P_0603_50V7K
AO4456_SO8
PR103
4.7K_0402_1%
1
2
Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.

Ipeak=7.42A, Imax=5.2A, Iocp=8.9A
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A
Vtripmax=Iocp*Rdson=8.9*5.6*1.3=0.065V
Rcs=Vtrip/9uA=0.065V/9uA=7.2K
choose Rcs=7.32K
Iocpmax=((7.32K*11uA)/0.0045)+1.03A=19A
Iocpmin=((7.32K*9uA)/(0.0056*1.3))+1.03A=10A
Iocp=10A~19A
PR104
8.45K_0402_1%
PJ15
PR105 0_0402_5%
1
2
PR106
226K_0402_1%
1
2
PC82
10U_1206_25V6M
5
6
7
8
PC81
2200P_0402_50V7K
1.5V_B+
PQ27
SYSON
PL6
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2
PC75
BST_1.1VALW-11
2
PR101
100_0603_1%
1
2
15
PU6
PC74
@0.1U_0402_16V7K
PC77
4.7U_0603_6.3V6K
<36,42>
B+
DCR= 7.5 mohm
PR99
30K_0402_5%
@
+5VALW
AO4466_SO8
<44,45> SPOK
JUMP_43X118
PR98
0_0603_5%
BST_1.1VALW
1
2
3
2
1
PR97
0_0402_5%
1
2
PC72
10U_1206_25V6M
5
6
7
8
PC139
2200P_0402_50V7K
1.1VALW_B+
B+
JUMP_43X118
AO4466_SO8
3
11
VDDP
10
2
PR112
13K_0402_1%
FB
DL_1.5V
LGATE
+5VALW
Cout ESR=17 mohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm

Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=3.9A
=>1/2Delta I=1.95A
choose Rcs=13K
Iocpmax=((13K*11uA)/0.0045)+1.95A=32A
Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A
Iocp=18A~32A
PC88 @
680P_0603_50V7K
PC90
4.7U_0805_10V6K
AO4456_SO8
PR113
10K_0402_1%
1
2
PR114
10K_0402_1%
2
<Vo=1.5V> VFB=0.75V
Vo=0.75*(1+10K/10K)=1.5V
Fsw=280KHz
1
+ PC86
330U_6.3V_M
2
4
1
PGND
8
PGOOD
GND
6
PC89
@ 47P_0402_50V8J
1
2
PC87
4.7U_0603_6.3V6K
PQ28
1
+1.5VP
14
12
CS
PHASE
PR110 @
4.7_1206_5%
VDD
LX_1.5V
VOUT
DH_1.5V
5
6
7
8
13
UGATE
PL7
1UH_MMD-10DZ-1R0M-X1A_18A_20%
1
2
3
2
1
+5VALW
TON
PC84
0.1U_0603_25V7K
BST_1.5V-1
1
2
BOOT
NC
PU7
PR111
100_0603_1%
1
2
15
@PC85
@PC85
0.1U_0402_16V7K
@ PR109
@PR109
30K_0402_5%
EN/DEM
3
2
1
PR108
0_0603_5%
BST_1.5V 1
2
Issued Date
Compal Secret Data
2007/09/20
Deciphered Date
2010/03/12
Title
Custom
Date:
SCHEMATIC, MB A5911
Rev
D
401827

D
Sheet
47
of
55
FB1_NB_COREP
POWER_SEL
+5VALW
0.95V
PR158
11.8K_0402_1%
PR117
0_0603_5%
BST_NB_CORE
1
2
B+
1
+
2
14
12
CS
11
VDDP
10
2
PR121
7.5K_0402_1%
DL_NB_CORE
+ PC95
330U_6.3V_M
2
PC97 @
680P_0603_50V7K
2
2
Cout ESR=15m ohm Rdson(max)=18m Rdson(typ)=15m

Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A
choose Rcs=7.5K
Iocpmax=((7.5K*11uA)/0.0045)+1.03A=19.36A
Iocpmin=((7.5K*9uA)/(0.018*1.3))+1.03A=10.3A
Iocp=10.3A~19.36A
2
4
1
LGATE
PR119 @
4.7_1206_5%
NC
PGND
PGOOD
PC98
@ 47P_0402_50V8J
1
2
PC96
4.7U_0603_6.3V6K
GND
FB
PQ30
+5VALW
+NB_COREP
PHASE
LX_NB_CORE
VDD
DH_NB_CORE 0.1U_0603_25V7K
5
6
7
8
VOUT
4
5
15
13
UGATE
PC99
4.7U_0805_10V6K
3
2
1
FB1_NB_COREP
TON
PL8
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2
PC93
BST_NB_CORE-1
1
2
BOOT
<Vo=1.1V> VFB=0.75V
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz
AO4466_SO8
PU8
PC94
0.1U_0402_16V7K
PR120
100_0603_1%
1
2
+5VALW
DCR= 7.5 mohm
@ PR118
@PR118
30K_0402_5%
@ JUMP_43X79
3
2
1
PR116
100K_0402_5%
1
2
<36,42> VLDT_EN
PC218
100U_25V_M
PR115
255K_0402_1%
1
2
5
6
7
8
PQ29
PC125
0.1U_0402_25V6
NB_CORE_B+
PC91
10U_1206_25V6M
PQ44
SSM3K7002F_SC59-3
PC140
2200P_0402_50V7K
EN/DEM
10K_0402_5%
PR159
1
2
2
G
PC126
0.01U_0402_25V7K
D
SSM3K7002F_SC59-3
<13> POWER_SEL
PQ43
2
G
2
PR157
0_0402_5%
PJ16
PR131
10K_0402_1%
1.1V
LOW
HIGH
AO4456_SO8
PR122
2.37K_0402_1%
1
2
PR123
8.87K_0402_1%
+1.5V
PU16
APL5508-25DC-TRL_SOT89-3
1
+5VALW
1
2
1
1
1
SSM3K7002F_SC59-3
PQ58
1
2
VDDR_SW
HIGH
LOW
1.05V
0.9V
2
G
VDDR_SW
@ PR153
@PR153
150_1206_5%
+CPU_VDDRP
PR156
249K_0402_1%
PR161
165K_0402_1%
PC118
2
GND
PR154
31.6K_0402_1%
1
@PR152
@
PR152
10K_0402_1%
PR160
10K_0402_1%
Issued Date
Compal Secret Data
2007/09/20
Deciphered Date
2010/03/12
Title
<28>
2
9
+2.5VSP
PC119
22U_0805_6.3V6M
VIN
APL5915KAI-TRL_SO8
FB
+5VALW
1
2
2
1
VOUT
PC116
4.7U_0805_6.3V6K
PR188 @
47K_0402_5%
EN
PC114
1U_0402_6.3V6K
PC121
0.1U_0402_16V7K
10K_0402_1%
1
2
VIN
VOUT
0.01U_0402_25V7K
PR155
VLDT_EN
OUT
POK
VCNTL
PU12
7
IN
GND
PC115
1U_0402_6.3V6K
+3VS
PJ24
@ JUMP_43X79
PC113
4.7U_0805_6.3V6K
Custom
Date:
SCHEMATIC, MB A5911
Rev
D
401827

D
Sheet
48
of
55
PR124
1K_1206_5%
1
2
NC
VOUT
NC
TP
PC101
1U_0603_6.3V6M
VREF
PR127
1K_1206_5%
1
2
PR129
+3VALW
NC
VCNTL
GND
2
2
2
PR130
1K_0402_1%
PC100
4.7U_0805_6.3V6K
VIN
1
PR132
100K_0402_5%
+0.75VSP
ACOFF
PQ34
DTC115EUA_SC70-3
2
<36,46>
DTC115EUA_SC70-3
PC103
10U_0805_6.3V6M
1 2
PQ33
1
2
PC102
0.1U_0402_16V7K
2
1
PR134
1K_0402_1%
1
2
PC104
0.22U_0402_10V4Z
PQ32
2
G
PR133
300K_0402_5%
1
2
2N7002W-T/R7_SOT323-3
APL5336KAI-TRL SOP
<22,42> SUSP
B+
1
PR126
1K_1206_5%
1
2
LL4148_LL34-2
PU9
1
100K_0402_5%
PR128
1
PJ17
JUMP_43X79
PQ31
TP0610K-T1-E3_SOT23-3
PR125
1K_1206_5%
1
2
PD13
VIN
100K_0402_5%
+1.5V
Ipeak=1A, Imax=0.7A
VL
B+
PR135
2.2M_0402_5%
1
PR136
499K_0402_1%
VS
RTCVREF
1
2
PR139
PR140
34K_0402_1%
2
1
PC107
0.01U_0402_25V7K
1
PR138
191K_0402_1%
PRG++ 2
1
2
PC105
0.1U_0603_25V7K
499K_0402_1%
PQ35
2
G
PR141
47K_0402_5%
1
PACIN <43,46>
LM393DR_SO8
1
2
BAS40CW_SOT323-3
32.4
PC106
1000P_0402_50V7K
<46> ACON
PU1B
PD14
2
<8,44,45> MAINPWON
PR137
100K_0402_1%
PQ36
DTC115EUA_SC70-3
+5VALW
1
2
66.5K_0402_1%
@ PR142
@PR142
Precharge detector
Min.
typ.
Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V
SSM3K7002FU_SC70-3
ACIN
BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V
Compal Secret Data
2007/09/20
Issued Date
Deciphered Date
2010/03/12
Title
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
SCHEMATIC, MB A5911
Rev
D
401827
Sheet
1
49
of
55
PR144
200K_0402_1%
1
2
TP
11
MP2121DQ-LF-Z_QFN10_3X3
PR143
4.7_1206_5%
POK
+1.8VSP1
PC124
22U_0805_6.3V6M
BS
IN
PL9
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2
IN
SW
SW
10
GND
2
PR148
0_0402_5%
EN/SYNC
GND
JUMP_43X79
FB
PD15
2
PC154
10U_0805_10V4Z
PC123
10U_0805_10V4Z
1
2
PC157
0.1U_0402_25V6
2
1
B340A_SMA2
PJ28
+5VALW
PU11
PC153
0.1U_0402_16V7K
1
+1.8VSP1
VGA_ON <22,36,38,42>
PC156
0.22U_0402_10V4Z
316K_0402_1%
PR145
PR147
402K_0402_1%
2
1
PC117
22U_0805_6.3V6M
PC155
680P_0603_50V7K
+5VALW
PC109 @
1U_0402_6.3V6K
@PJ18
@
PJ18
JUMP_43X79
PC147
1U_0402_6.3V6K
VGA@
PU10
PR150 @
12K_0402_1%
APL5913-KAC-TRL_SO8
1
1
VGA@ PC146
1U_0402_6.3V6K
@PR172
@
PR172
22K_0402_5%
2
2008/08/10
Issued Date
Ien=10uA, Vth=0.3V, notice

the res. and pull high
voltage from HW
Deciphered Date
2010/03/12
Title
Custom
Date:
Compal Secret Data
PC144
22U_0805_6.3V6M
VGA@
VGA@ PR175
6.04K_0402_1%
VGA@ PR173
2
10K_0402_5%
@
PR146
47K_0402_5%
@ PC150
@PC150
0.1U_0402_10V7K
@ PR151
200K_0402_1%
1
2
1
VGA_ON
VGA_PWR_ON
PC145
0.022U_0402_25V7K
VGA@
<38,42,51> VGA_PWR_ON
+1.0VSGP
2
FB
PR174
1.54K_0402_1%
VGA@
VGA@
GND
PC142
4.7U_0603_6.3V6K
VGA@
FB=0.8V
EN
POK
3
4
8
7
VOUT
VOUT
VCNTL
VIN
VIN
PC111 @
22U_0805_6.3V6M
6
5
9
1
PC108 @
0.01U_0402_25V7K
APL5913-KAC-TRL_SO8
@
PJ31
JUMP_43X79
VGA@
+1.8VSP2
@ PR149
@PR149
15K_0402_1%
FB
3
4
EN
POK
@PC112
@
PC112
4.7U_0603_6.3V6K
VOUT
VOUT
8
7
VCNTL
VIN
VIN
GND
6
5
9
PU14
+1.5V
+3VALW
+3VALW
SCHEMATIC, MB A5911
Rev
D
401827
Sheet
1
50
of
55
VGA_CORE
F=1/(75*e-12*33)=400K
Ipeak=33A Imax=23.1A Iocp=39.6A
Rsenmax=(5.6*1.3*39)/20=14.2 Kohm choose
Rsen=14.3Kohm
Iocpmin=(14.3*20)/(5.6*1.3)=39.3A
PL13
B+
B+_core
LX_VCORE
BST_VCORE
1
VGA@
1 PR183 2
PR184 0_0603_5%
2
0_0603_5%
+5VS VGA@
15
PGND
12
ISEN
11
5
VGA@
PQ39
4
14.3K_0402_1%
VGA@
5
6
7
8
VGA@
PQ40
4
PR191
4.7_1206_5%
VGA@
PC171 VGA@
PR298
0_0402_5%
VGA@
PR297
1
680P_0603_50V7K
3
2
1
3
2
1
VFB=0.6V
1 PC169
+
GCORE_SEN
GCORE_SEN
<17>
10_0402_5%
VGA@
10
VO
FSET
PR190
ISEN_VCORE
1
2
+VGA_COREP
Rds(TYP)=2.3mohm;
Rds(max)=3.2mohm
MAD@ PR197
68.1K_0402_1%
4.99K_0402_1%
+3VS
PAK@
PR197
43.2K_0402_1%
PC998
0.01U_0402_25V7K
@
VGA@
VGA@
PR193
1
VGA@
PR196
2
VGA@
PR211
33K_0402_1%
1
2
1
2
1 1
3
PR200 @
10K_0402_1%
PC175
4700P_0402_25V7K
VGA@
+3VS
PAK@ PR201
25.5K_0402_1%
PR199
10K_0402_5%
1
2
VGA@
2
G
MAD@ PR201
31.6K_0402_1%
2N7002W-T/R7_SOT323-3
10K_0402_5%
VGA@
PQ41 D
8.87K_0402_1%
PAK@
MAD@ PR198
9.53K_0402_1% PR198
VGA@
2
1
PR195
VGA@
22K_0402_1%
PC174
VGA@
2200P_0402_25V7K
PC172
0.1U_0402_10V7K
ESR=15 mohm
VGA@
PC170
22P_0402_50V8J
VGA@
FB
NC
EN
2
20K_0402_1%
AO4456_SO8
5
6
7
8
APW7138NITRL_SSOP16
PL14
0.56U_PCMC104T-R56MN_25A_20%
1
2
VGA@
330U_6.3V_M
13
LG
VGA@
1
PR177
VCC
DCR=2.2m OHM
2.2U_0603_6.3V6K
VGA@
DL_VCORE
AO4456_SO8
@ PR187
10K_0402_5%
<38,42,50> VGA_PWR_ON
4.7_0603_5% VGA@
1
2 PC167
14
PC168
2.2U_0603_6.3V6K
VGA@
7138_VCORE
4
PVCC
7138_VCORE
PR1862
TPCA8030-H_SOP-ADV8-5
PQ45 @
UG
BOOT
PQ38 VGA@
3
2
1
16
VGA@
PR185
0_0603_5%
2
VIN
2
VGA@
0.1U_0603_25V7K
1 2
+3VS
PHASE
GND
PGOOD
NC
PU998
PC166
VGA@
DH_VCORE-1
1
DH_VCORE
3
2
1
1
2
VGA@
PC165
10U_1206_25V6M
PC164
10U_1206_25V6M
HCB4532KF-800T90_1812
VGA@
+3VS
2
@ PR212
GPU_VID0
GPU_VID1
Core Voltage Level
Core Voltage Level
0.93 V
0.9 V
1.0 V
0.95 V
1.05V
1.0V
1.12 V
1.05 V
<16>
1
3
GPU_VID1
PR205 VGA@
10K_0402_1%
@PR204
@PR204
10K_0402_1%
GPU_VID1
10K_0402_5%
VGA@
PC177
4700P_0402_25V7K
PQ60D
2N7002W-T/R7_SOT323-3
VGA@
GPU_VID0
VGA@ PR202
1
2
2
G
Madison
Park XT
PQ42 D
2N7002W-T/R7_SOT323-3
VGA@
S
10K_0402_5%
VGA@ PR203
10K_0402_1%
2
1
2
G
PR210 VGA@
10K_0402_5%
+3VS
@ PR213
PQ61
2N7002W-T/R7_SOT323-3
2
G
VGA@ PR206
10K_0402_1%
1
2
GPU_VID0 <16>
10K_0402_5%
D
PR207 VGA@
10K_0402_1%
VGA@
Compal Secret Data
2007/12/18
Issued Date
Deciphered Date
2010/03/12
Title
Size
C
Date:

SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet
51
H
of
55
CPU_B+
PR214
44.2K_0402_1%
10_0402_5%
1
5
UGATE1
PR243
2.2_0603_1%
BOOT1 1
2 1
COMP0
VW1
PC211
180P_0402_50V8J
PR255
1K_0402_5%
2
1
PR256
2
PC216
2
1
PR254
PC213
255_0402_1% 4700P_0402_25V7K
FB_1
2
1 2
1
PC212
1000P_0402_50V7K
PR257
6.81K_0402_1%
2
1
COMP1
PC214
180P_0402_50V8J
PR258
1K_0402_5%
2
1
PR259
2
PC217
2
1
PC197
0.01U_0402_25V7K
2
1
PC196
10U_1206_25V6M
2
1
PC198
2200P_0402_50V7K
2
1
2
+CPU_CORE
1
1 2
2
PR247
16.2K_0402_1%
PR248
4.7_1206_5%
PC208
680P_0603_50V7K
1 PR249 2
4.02K_0402_1%
PC209
2
1
0.1U_0402_16V7K
PC215
1000P_0402_50V7K
PR260
6.81K_0402_1%
2
1
54.9K_0402_1% 1200P_0402_50V7K
54.9K_0402_1% 1200P_0402_50V7K
3
2
1
3
2
1
PR251
10_0402_5%
1
DIFF_1
@
PQ52
TPCA8028-H_SOP-ADVANCE8-5
PQ49
LGATE1
3
2
1
PC207
0.22U_0603_10V7K
+CPU_CORE_0
Design Current: 25A
Max current: 35A
OCP_min:42A
PL18
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
VSEN1
+CPU_CORE
PR253
PC210
255_0402_1% 4700P_0402_25V7K
FB_0
2
1 2
1
PC195
10U_1206_25V6M
2
1
5
@ PR252 1K_0402_1%
2
1
<8> CPU_VDD1_FB_H
PQ51
PHASE1
RTN1
PR246 10K_0402_1%
2
1
3
2
1
5
CPU_B+
49
24
ISN1
VW1
FB1
ISP1
23
ISP1
22
14
0_0402_5%
PR240
2
ISP0
BOOT1
PC201
2
1
UGATE1
25
26
BOOT1
ISP1
UGATE1
VW0
1 PR235 2
4.02K_0402_1%
0.1U_0402_16V7K
PC206
2200P_0402_50V7K
2
1
COMP0
12
LGATE0
TP
11
ISN1
PHASE1
COMP1
FB0
PC202
1U_0603_16V6K
PC204
10U_1206_25V6M
2
1
PHASE1
PC200
680P_0603_50V7K
27
1 2
28
PC203
10U_1206_25V6M
2
1
29
PGND1
10
LGATE1
LGATE1
+CPU_CORE
PR232
16.2K_0402_1%
PR233
4.7_1206_5%
ISL6265IRZ-T_QFN48_6X6~D
VDIFF0
OCSET
3
2
1
3
2
1
30
RBIAS
+5VS
@
PQ47
LGATE0
PVCC
ENABLE
PC199
0.22U_0603_10V7K
LGATE0
31
5
1
37
PHASE_NB
UGATE_NB
40
39
LGATE_NB
38
41
PGND_NB
OCSET_NB
32
PL17
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
PC205
0.01U_0402_25V7K
2
1
2
42
RTN_NB
PGND0
RTN0
VW0
44
SVC
+1.5VS
DIFF_0
43
<8> CPU_VDD0_FB_L
PR245
2
FSET_NB
33
PR241
2
1
10_0402_5%
<8> CPU_VDD1_FB_L
VSEN_NB
46
PHASE0
VSEN0
+CPU_CORE
45
SVD
13
<8> CPU_VDD0_FB_H
FB_NB
ISP0
ISN0
COMP_NB
47
VCC
48
VIN
PR239
1
95.3K_0402_1%
ISP0
PQ48
PHASE0
21
VR_ON
PR238
2
1
21.5K_0402_1%
UGATE0
20
1
0_0402_5%
BOOT0
34
VDIFF1
2
PR236
35
19
CPU_SVC
BOOT0
VSEN1
<8>
PR229
2.2_0603_1%
BOOT0 1
2 1
UGATE0
RTN1
1
0_0402_5%
PWROK
PQ46
PHASE0
PGOOD
RTN0
2
PR234
UGATE0
BOOT_NB
VSEN0
CPU_SVD
<8>
36
OFS/VFIXEN
15
PR242 0_0402_5%
16
2
1
0_0402_5%
17
2 PR244 1
0_0402_5%
18
2 PR250 1
<8>
<36>
CPU_VDDNB_FB_L
PR237 0_0402_5%
1
2
1
2
PR231 0_0402_5% @
<26> H_PWRGD_L
BOOT_NB
ISN0
VGATE
CPU_B+
PR226
10_0402_5%
2
<36>
1
2
1 2
LGATE_NB
PR224
0_0402_5%
PU15
+VDDNB
Design Current: 2.8A
Max current: 4A
OCP_min:5A
UGATE_NB
PR228
@ 105K_0402_1%
PR227
105K_0402_1%
PC193
680P_0603_50V7K
PC192
220U_D2_4VM
PHASE_NB
2
PR225
@ 10K_0402_1%
<8>
PHASE_NB
PR223
@ 105K_0402_1%
CPU_VDDNB_FB_H
PR221
13.7K_0402_1%
2
1
PR220
0_0402_5%
PC194
0.1U_0603_16V7K
PR222
0_0402_5%
+CPU_CORE_NB
PR219
2_0603_5%
+3VS
+
2
+CPU_CORE_NB
PR217
4.7_1206_5%
PC191
0.22U_0603_10V7K
+5VS
1
2
3
4
PL16
3.3UH_SIQB74B-3R3PF_5.9A_20%
1
2
PR230
0_0603_5%
BOOT_NB 1
2 1
PR218
10_0402_5%
1
2
+3VS
D2
D2
G1
S1
PHASE_NB
PR216
22K_0402_1%
2
1
2
1
G2
S2/D1
S2/D1
S2/D1
AO4932_SO8
PC189
1000P_0402_50V7K
2
1
PC190
0.1U_0603_16V7K
CPU_B+
8
7
6
5
B+
1
ISN0
PR215
2_0603_5%
1
2
+5VS
UGATE_NB
PC184
1200P_0402_50V7K
PL15
HCB4532KF-800T90_1812
1
2
ISN1
PC186
0.01U_0402_25V7K
2
1
PC185
10U_1206_25V6M
2
1
PQ50
PC187
2200P_0402_50V7K
2
1
LGATE_NB
PC183
33P_0402_50V8K
2
1
PC220
1000P_0402_50V7K
2
1
PC219
1000P_0402_50V7K
2
1
PC188
100U_25V_M
PR263 @
1K_0402_5%
PR262 @
1K_0402_5%
4
2008/04/16
Issued Date
Compal Secret Data
Deciphered Date
2010/03/12
Title
Size
C
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet
52
H
of
55
Version change list (P.I.R. List)

Item
Fixed Issue
ADD 2 switch mos and remove 2 pull

high resistance to modify VGA_CORE
switch level
change thermister , tune PH1

protection and recovery set
point
Add GPU voltagr sence net
change DC-IN connector part number
change reistance PR81 value
ADD switch circuit for 1.05V
Reason for change
Rev.
PG#
Before modify to fault, we recognize that

VGAPWRSEL pin is open drain state. But after
check with AMD AE regoer to clear the foul that
VGAPWRSEL pin has driviing ability.so i take
away 2 pull high resistance and add 2 switch
mos to modify the switch level.
0.1
52
change thermister from 150K to 100K
0.1
44
0.1
51
0.1
43
0.1
46
0.1
48
46
Cause GPU have GCORE_SEN and FB_GND pin

so power add receive net.
to meet pin definition
Cause meet battery Ki value setting

from 1.106 to 0.7224. change PR81
from 154K(0402_1%) to 80.6K(0402_1%)
Modify List
ADD PQ60 and PQ61

PR213(10K.0402)
Cause follow AMD electrcial sheet,

VDDIO/ VDDR voltage setting procedure.
AMD processor will switch between 1.05V
and 0.9V by VDDIO and VDDR
cause for component de-rating . Prevent the
component break down when inrush current happen.
0.1
Modify VGA_CORE mapping table.
cause ATI change power play voltage, so change the

table value.
0.1
51
Change 1.0VSGP enable RC value
Prevent LDO can't turn off when it should turn off
0.1
50
10
Change lowside MOS of VGA_CORE
0.1
51
11
Change 3/5Valw boost resistance

value
0.1
45
0.1
52
0.1
51
0.2
37,39,40
12
ADD two capacity
13
ADD three resistance
14
Change chock
For EMI request
Cause madison and park need different voltage switch

level so add different resistance value for the
problem.
Cause A phase put wrong chock
Date
Phase
2009/08/21
EVT_NEW75
2009/08/27
EVT_NEW75
ADD GCORE_SEN and FB_GND net, also add

PR296(0_0402_1%), PR297(10_0402_5%) and
PR298(0_0402_5%)
2009/09/04
EVT_NEW75
change part number is SP020908120
2009/09/10
EVT_NEW75
2009/09/22
EVT_NEW75
ADD PR161 (165K_0402_1%),

PQ58,PR152(10K_0402_5%),PR160(10K_0402_5%),
PC131(0.1U_25V6) , change PR161 value from 100K
to 249K, and ADD enable net name -VDDR_SW
change resistance size
For EMI request
remove PR212(10K,0402) and
change resistance PR81 value from 154K to 80.6K
Cause light load efficiency result is fail,

and we get result after discuss FAE. The
reason is lowside mos Rdson too less and IC
will detect not very sensitive
Page 1 of 2
for PWR
thermister part number SL200000V00 and PR28

change to 21K, PR30 change to 9.53K
2009/09/22
EVT_NEW75
change PR61 from (0.02_1206_1%) to (0.02_2512_1%)
2009/10/06
EVT_NEW75
change PR198 from 9.76_0402_1% to 9.53_0402_1%,

PR197 from 37.4_0402_1% to 64.9_0402_1% and
PR201 from 17.8_0402_1% to 31.6_0402_1%
2009/10/06
EVT_NEW75
Change PR173 from 100K_0402_5% to 10K_0402_5%,

PC146 from 0.1u_0402 to 1u_0402
2009/10/15
EVT_NEW75
Change PQ39 and PQ40 from TPCA8028(SB00000GL00)

to AO4456(SB000009F80)
2009/11/19
EVT_NEW75
Change PR40 and PR47 from 0_0603_5% to

2.2_0603_5%(SD013220B80)
2009/11/19
EVT_NEW75
Add pc219 and pc220 are both S CER CAP

1000P 50V K X7R 0402
2009/11/23
EVT_NEW75
2009/11/23
EVT_NEW75
2009/11/23
EVT_NEW75
Add PR197( 68.1K_0402_1%) , PR198 (

9.53K_0402_1%) and PR201 ( 31.6K_0402_1%)
Change PL9 from SH00000FK00
to SH000009Q00
2007/09/20
Issued Date
Compal Secret Data
Deciphered Date
2008/09/20
Title
Custom
Date:
SCHEMATIC, MB A5911
Rev
D
401827
Sheet
1
53
of
55
DVT Stage
1. remove Y4 related
2. add a bead on +VDDA11PCIE ---ok (add L28)
3. use 6mohm MOS on +1.1VS ---ok (U38,U37)
4. +1.1VALW vlotage level --check PW rail
5. check EC sequence (syson/vga_on) --ok
6. VRAM ID --ok
7. VRAM_RST circuit -- check slew rate
8. 3G module circuit update --ok
9. EC 500K circuit --ok
10. MEMZN circuit (0ohm/10uF) --ok
11. check GBE PU/PD --ok
12. check capacitor size
13. TXC crystal value --ok (change X1,Y2), Y5
14. internal clock circuit --ok
15. ADD VGAPWR_ON --ok, INT_VGAPWR_ON
16. define PX_FN/CLK_MODE strap pin --ok
17. define CLK_REQ for internal CLKREQ --ok
18. change 4.7u_0805 type --ok
19. BOM change for SG --ok
20. add VGAPWR_ON for SG&int clock use --ok
21. add PJ25 --ok
22. LED1/3 680ohm, LED2/4 3.9Kohm --ok
23. add MUXLESS strap --ok (R521,R612)
24. add LPW planel feature --ok (LOCAL_DIM /
COLOY_ENG_EN)
25. EC version control--ok (R529,R528)
26. WiMAX LED combine circuit --ok (R530,R531,D47)
27. change INT_VGAPWR_ON to EC_pin91 --ok
28. add VB function --ok (R533,R532)
29. Add R534,R535,R536 for layout --ok
30. change Y5 to 33p cap
31. pop ESD diode --ok
32. set T25 to BH for main --ok
33. Define Board file ID for SW req. --ok
PVT Stage
1. un-pop D39,D41
2. pop D27
3. un-pop Q73,Q74,Q75,Q70,R500,R502
4. Change R470 to 8.2K
5. Change R600,R510,R489 to 100K
6. Change C847 to 0.1u
7. Change C739,C740 to 15p
8. Change LED resistance R477,R499 change to 2.2K
9. Change R611 to 33K
10. Change HDMI_HPD PU from +3VSG to +3VS
11. Change C957,C971 to 0.47u_0603
12. Remove VGA option solution
unpop R147,R420,R421,R248 pop R161
13. Pop R595,R596,Q49,Q48 change R595 to 300k
14. Change LED1,LED3 to SC591NB5A30
15. Change Q5,Q26 to SB00000DH00
16. Change C468~C475 to MAD@
17. Change C305,C306 to 0603 size
18. Change LED control circuit, Pop R537,R457
19. Update AMP GAIN to 10dB
20. Change C11,C56,C723 to SGA00002N80
21. Change TPC24 to TPC12 for layout
p.40
p.39
p.38
p.36
p.22/p.42
p.22
p.36
p.37
p.42
p.24
p.40
p.16/p.22/p.17
p.42
p.37
p.16/p.37
p.20
p.18
p.34/p.35
p.40
p.8/p.9/p.35
MP Stage
1.
2.
3.
4.
5.
For PEW change list

1. Change Strap/PID/BID for SW
2. Change EC version to E0
3. Change thermal sensor to SB-TSI
4. Define 8L_6L_UMA strap on SB
5. Change EC version to D3 06/29
Add R541, R542 for TSI leakage current issue. (option) p.36
Change C21 from 3300pF to 100pF
Unpop C21
Unpop SW3
Change C305 to MAD@
6. Change VGA to R3 P/N
0419
7. Unpop ESD Diode D24 / D27 / D29
0512
Issued Date
Compal Secret Data
2008/10/06
Deciphered Date
2010/03/12
Title
Size
B
Date:
SCHEMATIC, MB A5911
Document Number
Rev
D
401827
Sheet
1
54
of
55

Item
Fixed Issue
Reason for change
Rev.
Change chock
Cause NB_CORE and 1.1VALW efficiency measurement

result fail. so change inductor from 1.8uH to 1.0
uH, and change the tye from ferrite to moding
0.2
16
Change resistance value
Cause change low side MOS from TPCA8028 to

AO4456. And there have different Rds(on). then
OCP will different, so i need to change ocp
setting resistance.
0.2
17
ADD sunbber
18
Change resistance value
15
19
Delete component PC73, PC83

and PC92
Cause VGA_CORE phase ringing too strong, so add

sunbber to reduce the ringing
change VGA_CORE switch frequency fromm 300K to

400K, for solve efficiency fail issue
Cause for design resinable
PG#
47,48
51
0.2
51
0.2
51
0.2
47,48
Modify List
Page 1 of 2
for PWR
Change PL6 and PL8 from SH000009680

SH000009U00
to
Change PR190 from SD000004100 (S RES 1/16W 8.2K

+-1% 0402) to SD00000QM80 (S RES 1/16W 14.3K
+-1% 0402)
ADD PR191(SD001470B80 ,S RES 1/4W 4.7 +-5% 1206
) and PC171(SE025681K80 S CER CAP 6,80P 50V K
X7R 0603 )
Change PR196 from 44.2K to 33K
Delete PC73,PC83 and PC92
Date
2009/12/01
Phase
EVT_NEW75
D
2009/12/01
EVT_NEW75
2009/12/01
EVT_NEW75
2009/12/01
EVT_NEW75
2009/12/01
EVT_NEW75
2007/09/20
Issued Date
Compal Secret Data
Deciphered Date
2008/09/20
Title
Custom
Date:
SCHEMATIC, MB A5911
Rev
D
401827
Sheet
1
55
of
55

Acer Aspire 5551G 5552G (Compal LA-5911P) Laptop Schematics

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Acer Aspire 5551G 5552G (Compal LA-5911P) Laptop Schematics

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A

Part Number = X76244BOL01

Part Number = X76244BOL03

Part Number = X76244BOL05

PEW76 Schematics Document

Part Number = X76244BOL06

Compal Electronics, Inc.

Compal Secret Data

Tuesday, September 14, 2010

AMD S1G4 Processor

1.5V DDRIII 800~1333MHz

Hyper Transport Link

USB port 0,1,2 USB port 5

Power On/Off CKT.

DC/DC Interface CKT.

Compal Electronics, Inc.

Compal Secret Data

Tuesday, September 14, 2010

Compal Electronics, Inc.

Compal Secret Data

Tuesday, September 14, 2010

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU (0.7-1.2V)

Core voltage for CPU (0.7-1.2V)

Voltage for On-die Northbridge of CPU(0.8-1.1V)ON

0.9V switched power rail for DDR terminator

1.1V switched power rail for NB VDDC & VGA

1.2V switched power rail

0.95-1.2V switched power rail

1.5V power rail for PCIE Card

1.8V power rail for CPU VDDIO and DDR

1.8V switched power rail

2.5V for CPU_VDDA

3.3V always on power rail

3.3V power rail for LAN

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

Board ID / SKU ID Table for AD channel

ADI ADM1032 (CPU)

GMT G781-1 (GPU)

BTO Option Table

Add USB patch

PowerXpress SKU(Madison): 3G@/BT@/UMA@/ VGA@/SG@/EXT@/EXTPW@/VB@/MAD@

Compal Electronics, Inc.

Compal Secret Data

Capilano w/ USB patch

External PCI Devices

Tuesday, September 14, 2010

AMD CPU S1G4

VDD CORE 36A

RAM DDRIII SODIMMX2

NorthBridge AMD RS880M

VDDC 1.0V-1.1V 7.6A

VDD18_MEM 1.8V 0.005A

VGA ATI Madison / Park

SouthBridge AMD SB820M

Compal Electronics, Inc.

Compal Secret Data