H BCH KHOA TP.

HCM * KHOA IN - IN T * B MN IN T
im

THI HK1 (2013-2014)

Mn: K thut s Thi gian: 110 pht (SINH VIN KHNG C S DNG TI LIU)

Ch k gim th

H TN: . MSSV: NHM: .. SINH VIN LM BI NGAY TRN THI - THI C 6 TRANG Cu 1 (1,0 im) Phn tch v xc nh dy m ca b m nh hnh v.
Q0 Q1 Q2

0 D Pr Q D

0 Pr Q D

0 Pr Q

CK

CK

Cl 0

CK

Cl 0

CK

Cl

T hnh v, ta thy y l b m ln, khng y . Ta c, tn hiu reset: Z = Q2Q0, vy khi Q2Q1Q0= 1x1, b m s reset v trng thi u. Xt 2 trng hp: * T/H1: Q2Q1Q0= 101, trng thi u l Q2Q1Q0= 001 (do Z ch a vo chn Clear ca Q2). T trng thi 001, b m s m ln: 001 -> 010 -> 011 -> 100. Xung clock tip theo s reset b m v li 001. Ta c b m ln m=4, bt u t trng thi 001. 0,5 * T/H2: Q2Q1Q0= 111, trng thi u l Q2Q1Q0= 011. T trng thi 011, b m s m ln: 011 -> 100. Vi xung clock tip theo s reset b m v li 001. Ta cng li c b m ln m=4, bt u t trng thi 001 nh trng hp 1. Vy ta c dy m l: Q2Q1Q0= 001, 010, 011, 100, 001, Cu 2 (2,0 im) S dng JK-FF, thit k b m song song c gin xung nh hnh v (cc trng thi khng c trong vng m u chn trng thi k tip l trng thi u ca gin ). CK QA(msb) QB QC 1 0,5

Dy m QAQBQC = 100, 010, 000, 001, 101, 111, 100, QA QB QC 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Q+A Q+B Q+C 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 1 1 1 0 0 1 0 0 JAKA 0 X 1 X 0 X 1 X X 1 X 0 X 0 X 0 JBKB JCKC 0 X 1 X 0 X X 0 X 1 0 X X 1 X 1 1 X 0 X 1 X X 0 X 1 0 X X 1 X 1

Rt gn ba K, ta c: JA = QC JB = QA JC = QA QB KA = QB QC KB = 1 KC = QB 0,75

0,75

QA

QB

QC

JA

QA

JB

QB

JC

QC

KA

QA 1

KB

QB

KC

QC

CK

0,5

Cu 3 (1,0 im) Mt h tun t kiu MEALY c mt ng vo X v mt ng ra Z. Ng ra Z l 1 khi ng vo X nhn c chui bit lin tip l 010 hoc 0110. Bit rng chui c xt lin tc. Hy thnh lp bng chuyn trng thi. Rt gn bng trng thi (nu c) Vd: X = 0,1,1,1,0,1,0,1,1,0,1,0,0,0,1,1,0,1,1,1,0,1,0,1,.. Z = 0,0,0,0,0,0,1,0,0,1,0,1,0,0,0,0,1,0,0,0,0,0,1,0,.. (1,0 ) Trng thi A B C D E ngha Trng thi reset (cha nhn bit) 1 bit 0 1 bit 1 2 bit 0,1 3 bit 0,1,1 HT A B C D E KT X=0 X=1 B C B B B B D C E C Z X=0 X=1 0 0 0 0 1 1 0 0 0 0

1,0 Ta c, A v C tng ng HT KT Z X=0 X=1 X=0 X=1 A B A 0 0 B D E B B B D E A 0 1 1 0 0 0

Cu 4 (2,0 im) H tun t c 1 ng vo X v 2 ng ra U, V. Khi c xung clock cnh ln th h chuyn trng thi theo bng sau: TT hin ti Q1Q0 10 01 00 11 np ROM) X Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 U V Q+1 Q+0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1 1 1 0 1 T1 T0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 0 A B C D TT k tip X=0 A C B C X=1 B A D B Ng ra (UV) X=0 01 00 01 10 X=1 01 11 10 11

a. Thit k h trn bng T-FF v ROM (v s kt ni ROM vi Flipflop v bng

1,0 ROM 23 x 4 (bit) D3 D2 A1 D1 U V T1 Q1

A2

Bng np ROM X Q1 Q0 U V T1 T0 A2 A1 A0 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 1 1 1

A0

D0

T0

Q0

CK

b. Bit rng ban u h tun t trng thi C v X = 1 khi h c cnh ln clock nh hnh v. Xc nh ng vo X cn thit c U = V= 0 vi s xung clock t nht. V xung ca ng vo X v ng ra U v V trong trng hp ny. (Ch tn hiu X khng thay i ti cnh ln ca clock) Clock X Trng thi U V 3 C D B 1,0

Cu 5 (1,0 im) H tun t c thit k bng PLA v D-FF nh hnh v. Hy v gin trng thi ca h. Bng np PLA X QA Z DA D ck QB DB D ck CK Q Q X Q A QB 1 0 - - 1 - 0 1 - 1 0 Z DA DB 0 0 1 1 1 1 0 0 0 0 1 0

T bng PLA, ta c: Z = QA QB + QA QB DA = X QA + QB = Q+A DB = QA QB = Q+B

Bng chuyn trng thi X Q A QB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Z Q+AQ+B 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 0

0,5 00 0 X=0

1 10 1

0, 1

0,5 0, 1 01 1 11 0

0, 1

Cu 6 (1,0 im) Cho code VHDL m t hm logic F. Hy xc nh biu thc ca F v vit li code bng lnh WITH-SELECT-WHEN (ch vit t phn architecture)
library ieee; use ieee.std_logic_1164.all; entity CAU6 is port ( A, B, C, D : IN std_logic; F : OUT std_logic); end CAU6; architecture THI of CAU6 is begin process (A, B, C, D) begin if A = 0 then F <= B and C; else F <= not C or D; end if; end process; end THI;

Biu thc ca hm F: F = A.BC + A (C + D) 0,5

Vit li bng lnh WITH SELECT - WHEN

architecture THI of CAU6 is begin WITH A SELECT WHEN 0, WHEN OTHERS; not C or D end THI; F <= B and C

0,5

Cu 7 (1,0 im) Cho Flip-flop nh hnh v. Hy vit code VHDL m t Flip-flop ny. *Ch : Ng vo Cl (clear) l ng vo ng b M CK N Cl Q Q
Bng hot ng

Cl M N 0 X X 1 0 0 1 0 1 1 1 0 1 1 1

Q+ 0 0 Q Q 1

entity MN_FF is port ( CK, Cl, M, N : IN Q, nQ end MN_FF; architecture THI of MN_FF is begin process (CK) begin if rising_edge (CK) then if Cl = 0 then Q <= 0 ; : std_logic; BUFFER std_logic);

1,0

elsif M = 0 and N = 0 then Q <= 0; elsif M = 0 and N = 1 then Q <= not Q; elsif M = 1 and N = 1 then Q <= 1; end if; end if; nQ <= not Q; end process; end THI;

Cu 8: cu t chn (sinh vin chn lm 8a hoc 8b) (1,0 im) 8a. Thnh lp lu SM (rt gn nu c) ca h tun t c m t cu 4

10 = Q1Q0

Lu SM rt gn

0,5 0 V X 1 V 0

A V

10 = Q1Q0 0,5 1

01

B 0 C X 1 U,V 0 C 0 V U D V U D 1 U,V X 0 U 1 V X 0 U X 1 0 X 1 X

01

1 U,V

8b. Vit code VHDL m t h t hp ny vi yu cu X B1 B0 X

d0 d1 s MUX2to1 y

d0 d1 s MUX2to1 y

A1
x c FA s y z

A0
x c FA s y z

- ng vo: X, C0 v 2 vector A, B. - ng ra: D l vector. - s dng component MUX2to1 v FA (khng cn vit code cho 2 component ny) C0

D2

D1

D0

library ieee; use ieee.std_logic_1164.all; entity CAU8 is port ( X, C0: IN std_logic; A, B : IN std_logic_vector (1 downto 0); D : OUT std_logic_vector (2 downto 0)); end CAU8; architecture THI of CAU8 is signal E, F, G, H, I : std_logic; component MUX2to1 port ( d0, d1, s : IN std_logic; end component; component FA port ( x, y, z : IN std_logic; end component; begin E <= not B(1); u1: u2: u3: u4: end THI; F <= not B(0); MUX2to1 port map (B(1), E, X, G); MUX2to1 port map (B(0), F, X, H); FA port map (A(1), G, I, D(1), D(2)); FA port map (A(0), H, C0, D(0), I); s, c : OUT std_logic); y: OUT std_logic);

1,0

GV ra

Ngy 30 thng 12 nm 2013 BM in T

NGUYN TRNG LUT 7