MODEL EXAMINATION

Branch: ME VLSI Design Date Time: 6.5.14 10.45 to 12.15

Semester: I Max. Marks: 50
Sub: CP7023Reconfigurable Computing

PART A (5*2=10)
1. Why does general purpose computing give slow speed of
processing compared to FPGA computing?
2. Draw a LAB for Altera Startix.
3. Write down the problems present in FPGA placement.
4. What are the steps involved in structural mapping?
5. Define the application characteristics for FPGA.
6. How is synchronous dataflow differed from dynamic
streaming dataflow?
7. How is synchronous dataflow differed from dynamic
streaming dataflow?
8. Differentiate block and pipeline reconfigurable.
9. Briefly explain the objective Software Programmable
Reconfiguration.
10. Reconfiguration in FPGA needs whether higher level
abstraction or lower level of abstraction. Justify your answer.

PART B (40)
Answer all questions
11. Explain about various types of CPLDs .(16)
(or)
12. Distinguish the operations involved in temporal and spatial
computing.(16)

13. Explain the Reconfigurable Processing Fabric
Architectures.(16)
(or)
14. (i).Explain about various configuration architectures.(8)
(ii). How reconfiguration process is managed.(8)

15. (i).What is parametric hardware generation? Explain it. (8)
(ii).How automatic compilation is carried out for
reconfiguration.(8)
(or)
16. (i). What are the functions followed by operating system for
reconfigurable computing .(8)
(ii).How scheduling is carried out by operating system for
reconfigurable computing.(8)

17. Explain in detail about for configuration bit stream
generation.(16)
(or)
18. (i).Write down the word length optimization models for
fixed point computation. (8)
(ii).Write short notes about partition based placement and
analytic placement.(8)

19. Explain the CORDIC architecture(processor) and its
algorithm for FPGA computing (16)
(or)
20. (i).Draw the architecture for and explain the NIOS II
processor .(8)
(ii).Explain the implementation and mapping of DAA into
FPGA platform.(8)


Faculty in charge HOD/ECE