TRNG AI HOC S PHAM KY THUAT TP.

HCM
KHOA IEN T
BO MON VIEN THONG














Bien soan: Nguyen nh Phu

TP.HCM 2007



TRNG AI HOC S PHAM KY THUAT TP.HCM
KHOA IEN T
BO MON VIEN THONG














Bien soan: Nguyen nh Phu

TP.HCM 2007


LI NOI AU

~ +- :++ - ~ :++ +~y ~+ +-+ -+ :+ ++-. :+-: : -+ :+ ~+ .+ .+ +++
:+ ~ :+-: : -. +-+ + ++-
. - .~ :+-: : - ~ :++ ~ ~ + ~+ -+ +~y ~+ ++ + ~: :+ +
~, ++ ~: ++-. :+ ~+ + .- -: + .~ :++ ++- - . , - :+~y y-. ~. -.
+-+ .~ ~+, +- : -+ :+ ++ ~+, : +~y :~+ - ~ .- ~ ~ ++ + ~
++ .+ + .- : +~ + y + ++ + -. +
.+ .+ -~+ +~y + :-+ -~+ - +++ ++~ +. .. + + + :+ +,
:+ +++ ' :+-. .- ~ :+-: : - ~ :++ +, +++ :++ :~y ++ ++ .
.+ - ~ :++ + +- :++ -, +++ :++ :~y ~+ ~ :++ + ~ ~+ -+ : +,
+++ - :++ :~y ~+ ~ :++ + ~ ~+ -+ :.~+ :+
.+ :+ .+ -~+ ++~ :~+ : ~ -+ :++ :~+ .- y :+.~: .~ / +
-++ .-+ +~++ -+ -+ :+
+ .~ :++ :-+ -~+ :+~ +~ ++-. :~ -. +-+ .~+ + -~ -: +-+ + -+ +
~y ++ - :~ ~+ + +~+ :+-+ ++ + +~y .- :~ ~ :+- ~ +
+._+9y~+ + +~+ :+~++ ~ +



MUC LUC
LOI NOI AU
CHUONG z. GIOI THIEU CAC CAU TRUC LAP TRNH UOC
|. C|0| 1H|EU PLD -
' / 3 / / / / -
/ 3 / / / 3/
3/ / //3/
- 3 / / //3/ 7
\/ 7
/ 3
7 / '
||. CPLD CUA HANC AL1EkA 2
' \// 7 '
\/ '
\ 3 / '
- \ 3 3 3 '
\// '
|||. CPLD CUA HANC X|L|NX '`
' / 3/\\/ 3 //) '`
'3
|V. L0C|C LAP 1kNH FPCA
' / 3 , /
/ \ 3 -
3/ 3 3 3 /\
- / / 3/
V. FPCA CUA AL1EkA 7
' \/3 3 / 3 // ) 7
\ 3 3 /\ `
/ /3
V|. FPCA CUA X|L|NX '
' / 3 , / 3/ 3 ) '

/ 3/ 3 ./ / /\
V||. PHAN MEM LAP 1kNH 7
' / 3
\ 3 /3 -
3 --
- ) -
/ \\ / -
\ 3 3/ -7
7 / , / / 3 -7
V|||. CAU H0| 0N 1AP VA 8A| 1AP -`

CHUONG z. NGON NGU LAP TRNH VHDL '
|. 5U kA 0| NC0N NCU VHDL
||. CAC 1HUA1 NCU CUA VHDL
|||. M0 1A PHAN CUNC 1k0NC VHDL
' )
/ -
/ /
- / 3 / 7
/ `
/ / / 3
7 \ /
|V. C|0| 1H|EU VE M0 HNH HANH V|
' / / ./ /
\ 3 /
. `
- 3 3
/ / 7'
\ / 7
V. XU L 1UAN 1U 7
' / 7
3/ / . 3/ 7`
/ / / `'
- / `'
/ / `
/ `
7 / / `7
` / N/ ``
V|. CAC K|EU 0| 1U0NC 1k0NC VHDL 3'
' / / 3'
/ / 3
/ / /3 3
V||. CAC K|EU DU L|EU 1k0NC VHDL 3
' / // 3-
./ '
/ '
V|||. CAC 10AN 1U C0 8AN 1k0NC VHDL '
' / / 3 '
/ / / '7
/ / '`
- / / / '`
/ / / / '3
/ / , '
7 / / '7
|X. CHU0NC 1kNH C0N VA C0| '7
' 3 '7
3 '
X. CAU H0| 0N 1AP VA 8A| 1AP '

CHUONG . THIET KE MACH TO HOP BANG VHDL '3
|. C|0| 1H|EU '3
||. 1H|E1 KE MACH C|A| MA MACH MA H0A '3
' \/ 3/ \/ '3
\/ \/ / ''
\/ 3/ \/ 7 / / / 3 '
|||. 1H|E1 KE MACH A H0P MACH C|A| A H0P '-
' \/ / '-
\/ 3/ / '
|V. CAU H0| 0N 1AP VA 8A| 1AP 37

CHUONG q. CAC THANH GHI BO EM TRON VHDL ''3
|. C|0| 1H|EU '-'
||. 1H|E1 KE CAC L0A| FL|P FL0P '-'
' } '-'
/ '--
|||. 1H|E1 KE 1HANH CH| D[CH N '-
' / 3 , - '-
/ 3 , ` '-`
\/ \ } ` '-3
- \/ \ .3 ` ''
\/ ` /3 / / / '
|V. 1H|E1 KE MACH EM '
' \/ \ , / - \ '
\/ \ '
\/ \ ./ 3/ \/ , 7 / '7
- \/ \ 3 , 7 / '3
\/ \ 333 , 7 / ''
V. CAU H0| 0N 1AP VA 8A| 1AP '
1o| ||eu thom khoc. 66




Chucng
C|0| 1H|EU CAC CAU 1kUC LAP 1kNH
U0C


C|0| 1H|EU PLD
/ 3 / / / /
/ 3 / / / 3/
3/ / //3/
3 / / //3/
\/
/
/
CPLD CUA HANC AL1EkA
\// 7
\/
\ 3 /
\ 3 3 3
\//
CPLD CUA HANC X|L|NX
/ 3/\\/ 3 //)

L0C|C LAP 1kNH FPCA
/ 3 , /
/ \ 3
3/ 3 3 3 /\
/ / 3/
FPCA CUA AL1EkA
\/3 3 / 3 // )
\ 3 3 /\
K|eu hcot dcng b|nh thucng
K|eu hcot dcng LU1 mc rcng
/ /3
FPCA CUA X|L|NX
/ 3 , / 3/ 3 )

/ 3/ 3 ./ / /\
Cou truc truyen thcng
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
2 y :+.~: .~ /
Cou truc A5M8L
PHAN MEM LAP 1kNH
/
\ 3 /3
3
)
/ \\ /
\ 3 3/
/ , / / 3 ,
CAU H0| 0N 1AP VA 8A| 1AP
/ /
H|nh -. Cou truc cuo PAL.
H|nh -2. PAL sou kh| |op tr|nh de toc hom.
H|nh -3. Cou truc cuo CAL.
H|nh -4. K| h|eu dcn g|on chc PAL/CAL.
H|nh -5. H|nh chc v| du -.
H|nh -6. 5c dc khc| cuo PAL/CAL.
H|nh -7. 5c dc moch coc Mocrcce||.
H|nh -8. 5c dc khc| vo h|nh dong vc cuo PAL6V8.
H|nh -. 5c dc khc| vo h|nh dong vc cuo CAL22V0.
H|nh -0. 5c dc khc| cuo CPLD tcng quot.
H|nh -. Cou truc CPLD MAX 7000
H|nh -2. 5c dc khc| mcrcce|| dcn g|on cuo MAX 7000.
H|nh -3. V| du coch mc rcng.
H|nh -4. M|nh hco chc v|ec ch|o se.
H|nh -5. M|nh hco chc bc mc rcng scng scng.
H|nh -6. M|nh hco chc bc mc rcng scng scng tu mocrcce|| khoc.
H|nh -7. 5c dc khc| cuo MAX ||.
H|nh -8. Phon b|et 2 k|eu xoy dung hom.
H|nh -. Phon b|et 2 k|eu ket nc|.
H|nh -20. 5c sonh PAL vc| PLA.
H|nh -2. 5c dc cou truc cuo Ccc|runner ||.
H|nh -22. Cou truc cuo mct khc| chuc nong F8.
H|nh -23. M|nh hco chc v| du -2.
H|nh -24. Cou truc cc bon cuo FPCA.
H|nh -25. Coc khc| CL8 cuo FPCA.
H|nh -26. 5c dc khc| cc bon cuo mcdu|e |cg|c trcng FPCA.
H|nh -27. Kho| n|em cc bon cuo LU1 ducc |op tr|nh de toc 50P ngc ro .
H|nh -28. M|nh hco chc v| du -3.
H|nh -2. Kho| n|em ve FPCA boy hc|.
H|nh -30. Kho| n|em chuc nong |c| phon cung trcng FPCA.
H|nh -3. 5c dc khc| cuo cou truc LA8 cuo 5trot|x || vo ALM
H|nh -32. 5c dc khc| ALM cuo 5trot|x ||.
H|nh -33. Coc cou h|nh cc the cc cuo LU1 trcng ALM c k|eu b|nh thucng.
H|nh -34. Mc rcng ALM de toc ro hom 50P 7 b|en trcng k|eu LU1 mc rcng.
H|nh -35. M|nh hco chc v| du -4.
H|nh -36. 5c dc khc| cuo FPCA 5trot|c ||.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 3
H|nh -37. M|nh hco coc cop |cg|c d|nh cou h|nh tu te boc |cg|c chc den CL8.
H|nh -38. V| du coch dung chuc| nc| t|ep de mc rcng b|eu thuc 50P.
H|nh -3. M|nh hco chc v| du -5.
H|nh -40. 1|ch hcp nh|eu chuc nong |P ket quo |om g|om CL8 vo/hcoc pho| tong k|ch thucc
ch|p.
H|nh -4. M|nh hco cou truc A5M8L cuo FPCA p|otfcrm.
H|nh -42. 5c dc dcng th|et ke tcng quot de |op tr|nh chc 5PLD, CPLD hcoc FPCA.
H|nh -43. Coc th|et b| cc bon de |op tr|nh chc 5PLD, CPLD hcoc FPCA.
H|nh -44. M|nh hco chc 2 k|eu |op tr|nh.
H|nh -45. M|nh hco chc k|eu |op tr|nh tung dcon.
H|nh -46. Luu thonh khc| |cg|c 3.
H|nh -47. Mon h|nh scon thoc dong scng tcng quot .
H|nh -48. 1h|et |op coc dong scng ngc voc.
H|nh -4. Dong scng ngc voc vo ro kh| choy mc phcng.
H|nh -50. M|nh hco chc chuc nong tcng hcp.
H|nh -5. 5c dc moch vo donh soch ||et ke.
H|nh -52. M|nh hco chc mc phcng thc| g|on.
H|nh -53. Dcwn|cod th|et ke voc th|et b| |op tr|nh.

+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
4 y :+.~: .~ /

|. C|0| 1H|EU PLD:
Hai thanh phan chnh cua thiet b logic lap trnh n gian SPLD (Simple Programmable
Logic Device) la PAL va GAL. PAL tng trng cho logic mang lap trnh (Programmable
Array Logic) va GAL tng trng cho logic mang tong quat (Generic Array Logic). Thng
th PAL ch lap trnh 1 lan con GAL th cho phep lap trnh lai, tuy nhien co nhieu loai SPLD lap
trnh lai van con c goi la PAL.
Thuat ng GAL la ten do hang Lattice Semeconductor at va sau o th c cap phep cho
cac nha san xuat khac.
Cau truc c ban cua PAL va GAL la mang AND cho phep lap trnh va mang OR co nh to
chc theo phng phap tong cua cac tch SOP (Sum-Of-Product). Vi CPLD (Complex
Programmable Logic Device) c tch hp t nhieu SPLD e co chc nang manh hn cho cac
thiet ke phc tap.
Trong phan nay chung ta se khao sat hoat ong cua SPLD, phng phap tong cua cac tch
c dung trong PAL va GAL, giai thch c s o logic cua PAL/GAL, mo ta macrocell c
ban cua PAL/GAL, khao sat PAL16V8 va GAL22V10, mo ta CPLD c ban.
' / 3 / / / /
PAL cha mang cong AND lap trnh va c noi vi mang cong OR co nh. Thng th
PAL dung cong nghe x ly cau ch nen ch cho phep lap trnh 1 lan OTP (One-time-
Programmable).
Cau truc PAL cho phep thc hien tat ca cac ham tong cua cac tch vi cac bien a c
xac nh. Cau truc cua mot PAL n gian c trnh bay nh hnh 1-1 cho 2 bien ngo vao va 1
bien ngo ra:

H|nh -. Cou truc cuo PAL.
Mot mang lap trnh la mot ma tran cac day dan gom cac hang va cac cot va chung co the
lap trnh e noi vi nhau tai iem giao nhau. Moi iem noi lap trnh co cau tao la cau ch oi
vi loai PAL va c goi la mot te bao cell. Moi hang co the noi vi mot ngo vao cua cong
AND va moi cot la mot bien ngo vao hoac bien phu nh. Bang cach lap trnh gi nguyen cau
ch hay pha hong cau ch th co the tao ra bat ky ham to hp nao t cac bien ngo vao e a
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 5
en cong AND tao ra cac thanh phan tch mong muon. Cac cong AND c ket noi vi cong
OR e tao nen cac ham ngo ra tong cua cac tch.
V du 1: Mot PAL c lap trnh nh hnh 1-2 e tao ra thanh phan AB , B A va B A .
Trong hnh 1-2 ta co the nhn thay mot so cau ch b pha hong va mot so cau ch con nguyen e
ket noi cac bien ngo vao vi cac ngo vao cua cac cong AND tao ra ham tch theo yeu cau va
sau cung la ham tong cua cac tch:
B A B A AB X + + =

H|nh -2. PAL sou kh| |op tr|nh de toc hom.
/ 3 / / / 3/
GAL ve c ban chnh la PAL co the lap trnh c, GAL co to chc AND/OR giong nh
PAL nhng s khac nhau c ban la GAL dung cong nghe x ly cho phep lap trnh lai giong nh
EEPROM thay cho cau ch c trnh bay nh hnh 1-3.

H|nh -3. Cou truc cuo CAL.
3/ / //3/
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
6 y :+.~: .~ /
Cac thiet b lap trnh PAL va GAL co cac cong logic AND va OR va them mot so phan t
khac cung vi cac bien ngo vao va cac bien phu nh. Hau het cac PAL va GAL eu co s o k
hieu n gian nh hnh 1-4:

H|nh -4. K| h|eu dcn g|on chc PAL/CAL.
Cac bien ngo vao cua PAL hoac GAL thng co mach em e ngan chan qua tai khi co
qua nhieu cong AND noi ti ngo vao o. Trong s o, khoi em la khoi tam giac va em tn
hieu ngo vao va ao tn hieu e tao ra bien phu nh cua tn hieu o.
PAL va GAL eu co mot lng rat ln cac ng lap trnh ket noi ben trong va moi cong
AND co nhieu ngo vao. Thng th trong s o mach cua PAL va GAL thay cong AND nhieu
ngo vao bang cong AND ch co mot ng ngo vao cho gon nhng tren o co ghi so lng ngo
vao thc cho cong AND o. Trong hnh 1-4 th moi cong AND eu co 2 ngo vao.
iem noi lap trnh nam trong ma tran c xac nh bang dau nam tren cac ng giao
nhau va cau ch se c gi nguyen, con cac iem khong co anh dau th cau ch se b pha
hong. Hnh 1-4 cua v du tren c lap trnh e tao ra ham B A B A AB X + + = .

V du 1-2: Hay ve s o mach cho mot PAL a lap trnh e tao ra ham co 3 bien ngo vao
nh sau: AC B A C B A C B A X + + + =
Giai: S o mach cua PAL nh hnh 1-5:
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 7

H|nh -5. H|nh chc v| du -.
- 3 / / //3/
S o khoi cua PAL hoac GAL c trnh bay hnh 1-6. Nen nh rang s khac nhau c
ban la GAL co mang cho phep lap trnh lai con PAL th ch lap trnh mot lan. Cac ngo ra cua
mang cong AND lap trnh c a en cac cong OR co nh a c ket noi e tao cac ham
logic ngo ra. Cong OR ket hp vi ham logic ngo ra thng c goi la macrocell.

H|nh -6. 5c dc khc| cuo PAL/CAL.
\/
Mot macrocell gom mot cong OR va cac ham logic ngo ra ket hp. Mc o phc tap cua
macrocell tuy thuoc vao thiet b cu the PAL hoac GAL. Mot macrocell co the c nh cau
hnh cho mot ham to hp, ham thanh ghi hoac cho ca hai.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
8 y :+.~: .~ /
Ham thanh ghi co lien quan en flip flop chnh v the trong macrocell cung co flip flop e
tao ra cac ham tuan t.
Hnh 1-7 trnh bay 3 loai macrocell c ban vi cac ham to hp.

(o[

(b[

(c[
H|nh -7. 5c dc moch coc Mocrcce||.
Hnh 1-7a trnh bay mot macrocell n gian vi mot cong OR va mot cong ao ba trang
thai. Ngo ra cua cong ao ba trang thai co the hoat ong tao ra mc HIGH, mc LOW va trang
thai tong tr cao xem nh h mach.
Hnh 1-7b trnh bay mot macrocell co the hoat ong nh ngo vao hoac ngo ra. Khi ngo vao
c dung nh ngo ra th cong ao phai trang thai tong tr cao e h mach va tn hieu t ben
ngoai a en bo em va ket noi vi mang cong AND ben trong.
Hnh 1-7c trnh bay mot macrocell co the lap trnh e co ngo ra tch cc mc HIGH hoac
mc tch cc mc LOW va cung co the s dung nh ngo vao. Mot ngo vao cua cong XOR (ex-
or) co the c lap trnh mc HIGH hoac mc LOW. Khi lap trnh ngo vao cong XOR mc
HIGH th tn hieu ngo ra cua cong OR se b ao v : 1 1 0 = va 0 1 1 = . Tng t khi lap trnh
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 9
ngo vao cong XOR mc LOW th tn hieu ngo ra cong OR khong b ao v: 0 0 0 = va
1 0 1 = .
/
Thng th hnh dang vo cua SPLD co cau hnh chan nam trong khoang t 20 en 28 chan.
Co 2 thanh phan giup chung ta xac nh PAL hoac GAL mot cach thch hp cho cac thiet ke
logic a cho la so lng ngo vao va ngo ra cung vi so lng cong logic. Mot vai thong so khac
can phai xem xet la tan so hoat ong cc ai, thi gian tre va nguon ien ap cung cap.
Cac nha san xuat Lattice, Actel, Atmel va Cypress la cac cong ty san xuat SPLD.
Cac loai PAL va GAL thng s dung la PAL16V8 va GAL22V10. Cac ma so cho biet so
lng ngo vao, so lng ngo ra va loai ngo ra logic. V du: PAL16V8 se cho biet thiet b nay co
16 ngo vao, 8 ngo ra va ngo ra la bien (V: variable). Ch H hoac ch L co ngha la ngo ra tch
cc mc HIGH hoac mc LOW tng ng. S o khoi cua PAL16V8 va hnh dang vo c trnh
bay hnh 1-8.

H|nh -8. 5c dc khc| vo h|nh dong vc cuo PAL6V8.
Moi macrocell co 8 ngo vao lay t mang cong AND nen co the co ti 8 thanh phan tch
cho moi ngo ra. Co 10 ngo vao k hieu la I, 2 ngo ra k hieu la O va 6 chan co the c dung
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
10 y :+.~: .~ /
nh la ngo vao hoac ngo ra va k hieu la I/O. Moi ngo ra tch cc mc LOW. PAL16V8 co mat
o tch hp khoang 300 cong.
S o khoi cua GAL 22V10 va hnh dang vo nh hnh 1-9. GAL nay co 12 ngo vao va 10
chan co the s dung nh ngo vao hoac ngo ra. Cac macrocell co cac ngo vao ket noi vi mang
cong AND co the thay oi so lng ket noi t 8 en 16. GAL 22V10 co mat o tch hp khoang
500 cong.

H|nh -. 5c dc khc| vo h|nh dong vc cuo CAL22V0.
7 /
Mot CPLD cha nhieu mang SPLD vi ket noi ben trong cho phep lap trnh nh hnh 1-10.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 11
Chung ta xem moi mang SPLD trong CPLD la mot khoi mang logic LAB (Logic Array
Block). Mot ten khac oi khi cung c dung la khoi chc nang, khoi logic hoac khoi tong
quat.
Cac ket noi lap trnh ben trong thng c goi la PIA (Programmable Interconnect
Array) nhng mot so nha che tao nh Xilinx dung thuat ng AIM (Advance Interconnect
Matrix) hoac cac thuat ng tng t.
Cac LAB va cac ket noi ben trong c lap trnh bang phan mem. Mot CPLD co the c
lap trnh cho cac chc nang phc tap da vao cau truc tong cua cac tch cho moi LAB oc lap
hay chnh xac hn la moi SPLD. Cac ngo vao co the ket noi ti bat ky khoi LAB nao va cac
ngo ra cung co the ket noi ti bat ky LAB nao thong qua PIA.

H|nh -0. 5c dc khc| cuo CPLD tcng quot.
Hau het cac nha che tao ra mot chuoi CPLD c sap xep theo mat o tch hp, cong
nghe x ly, cong suat tieu thu, nguon cung cap va toc o. Cac nha che tao thng cung cap mat
o CPLD theo cac thanh phan macrocell hoac LAB. Mat o tch hp co the sap xep t 10
macrocell en 2000 macrocell trong mot vo co the len en vai tram chan.
PLD cang phc tap th mat o tch hp cang cao. Mot vai CPLD co the lap trnh lai va
dung cong nghe x ly EEPROM hoac SRAM cho cac iem ket noi lap trnh. Cong suat tieu tan
co the nam trong khoang t vai mili watt en vai tram mili watt. Nguon cung cap DC thng th
nam trong khoang t 2,5V en 5V tuy thuoc vao cac ch nh cua thiet b. Co nhieu nha san
xuat CPLD nh Altera, Xilinx, Lattice va Cypress.
Trong phan tiep theo chung ta se khao sat cac CPLD cua hai nha san xuat la Altera va
Xilinx bi v hai cong ty nay ang chiem lnh th trng. Cac nha che tao khac th cung san xuat
thiet b va phan mem tng t.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
12 y :+.~: .~ /
||. CPLD CUA HANC AL1EkA
Altera san xuat ra nhieu ho CPLD nh MAX II, MAX 3000 va MAX 7000. Trong phan
nay ch trnh bay chu yeu ho MAX 7000.
Sau khi hoan tat phan nay th ban co the: mo ta c ho CPLD MAX, thao luan ve cau
truc cua CPLD MAX 7000 va CPLS MAX II, giai thch cach tao cac thanh phan tch c tao ra
trong CPLD.
' \// 7
Cau truc cua CPLD la cach thc ma cac thanh phan ben trong c to chc va c sap
xep. Cau truc cua ho CPLD MAX 7000 th giong nh s o khoi cua CLPD tong quat c trnh
bay hnh 1-11.

H|nh -. Cou truc CPLD MAX 7000.
CPLD MAX 7000 co cau truc lp PAL/GAL e tao ra cac ham SOP. Mat o nam trong
khoang t 2 LAB en 16 LAB tuy thuoc vao CPLD cu the. Nen nh la mot LAB tng ng
vi mot SPLD dung cong nghe x ly EEPROM. Kieu lap trnh trong he thong ISP (In-System
Programmable) dung giao tiep chuan JTAG.
Hnh 1-11 trnh bay s o khoi tong quat CPLD ho MAX 7000 cua Altera. Bon khoi LAB
c trnh bay nhng so lng co the len en 16 khoi LAB. Moi khoi LAB co 16 macrocell,
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 13
nhieu khoi LAB c ket noi vi nhau thong qua PIA, PIA la cau truc bus lap trnh toan cuc
(cho tat ca cac LAB) bao gom cac ngo vao co cung chc nang, I/O va cac macrocell.
\/
S o khoi macrocell n gian cua ho MAX 7000 c trnh bay trong hnh 1-12.
Macrocell cha mot mang cong AND lap trnh gom 5 cong AND, mot cong OR, mot ma tran la
chon thanh phan tch e ket noi cac ngo ra cua cong AND vi cong OR, va logic ket hp e co
the lap trnh cho ngo vao, ngo ra logic tong hp hoac ngo ra thanh ghi dch.

H|nh -2. 5c dc khc| mocrcce|| dcn g|on cuo MAX 7000.
Mac du van dung cung mot khai niem nhng macrocell nay khac vi macrocell a trnh
bay phan SPLD bi v no co mang cong AND lap trnh va ma tran la chon thanh phan tch.
Trong hnh 1-12 co 5 cong AND tao ra cac thanh phan tch t PIA vao ma tran la chon thanh
phan tch. Thanh phan tch t cong AND nam di cung co the c hoi tiep tr lai ma tran lap
trnh xem nh phan m rong chia se e s dung bi cac macrocell khac.
Cac ngo vao m rong song song cho phep mn cac thanh phan tch khong dung t cac
macrocell khac e m rong bieu thc SOP. Ma tran la chon thanh phan tch la mot ma tran cua
cac ket noi lap trnh c dung e ket noi cac ngo ra a la chon t mang cong AND va t ngo
vao m rong en cong OR.
\ 3 /
Bu cua thanh phan tch c dung e tang so lng thanh phan tch trong bieu thc SOP
th co the dung c cho moi macrocell trong LAB. Hnh 1-13 minh hoa cach thc thanh phan
m chia se t macrocell khac co the c dung e thiet lap them cac thanh phan tch.
Trong trng hp nay mot trong 5 cong AND trong 1 mang macrocell b gii han, ch co 4
ngo vao va do o co the tao ra 1 thanh phan tch co 4 bien khac nhau c minh hoa trong hnh
(a). Hnh (b) trnh bay phan m rong cho 2 thanh phan tch.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
14 y :+.~: .~ /

o. Ccng AND 4 ngc voc toc ro b. Ccng AND ducc mc rcng de
thonh phon t|ch 4 b|en. toc ro 2 thonh phon t|ch.
H|nh -3. V| du coch mc rcng.
Moi macrocell cua MAX 7000 co the tao ra 5 thanh phan tch t mang cong AND. Neu 1
macrocell can nhieu hn 5 thanh phan tch cho ham ngo ra SOP th no phai dung them thanh
phan m rong t macrocell khac. Gia s thiet ke can bieu thc SOP cha 6 thanh phan tch.
Hnh 1-14 trnh bay cach thanh phan tch t macrocell khac co the c dung e tang bieu thc
SOP ngo ra.

H|nh -4. M|nh hco chc v|ec ch|o se.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 15
Macrocell th 2 tao ra thanh phan m rong chia se ) ( F E + c noi en cong AND th 5
trong macrocell th 1 e tao ra bieu thc SOP vi 6 thanh phan tch. Cac dau ket noi c tao
ra trong phan cng t chng trnh thiet ke va phan mem bien dch roi nap vao chip.
- \ 3 3 3
Mot phng phap khac e tang so lng cac thanh phan tch cho mot macrocell bang cach
dung bo m rong song song trong no cac thanh phan tch m rong c OR vi cac thanh
phan c tao ra macrocell thay v dung ket hp trong ma tran AND nh bo m rong chia se.
Mot macrocell a cho co the mn cac thanh phan tch khong dung t cac macrocell lan can (co
the len en 5 thanh phan t cac macrocell khac oi vi MAX 7000). Khai niem nay c minh
hoa nh hnh 1-15 trong o mach ien n gian c tao ra t 2 thanh phan tch mn them 3
thanh phan tch m rong.

H|nh -5. M|nh hco chc bc mc rcng scng scng.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
16 y :+.~: .~ /

H|nh -6. M|nh hco chc bc mc rcng scng scng tu mocrcce|| khoc.
Hnh 1-16 trnh bay cach mot macrocell co the mn cac thanh phan m rong song song t
macrocell khac e tang bieu thc ngo ra SOP. Macrocell th 2 dung 3 thanh phan tch t
macrocell th 1 e tao ra bieu thc SOP gom 8 thanh phan.
\//
Cau truc cua CPLD MAX II khac vi hoc MAX 7000 va c Altera goi la CPLD Post-
macrocell. Nh a trnh bay trong s o khoi hnh 1-17, thiet b nay cha cac khoi LAB cung
vi nhieu thanh phan logic LE (Logic Elements). Mot LE la mot n v thiet ke logic c ban va
tng t nh macrocell. Ket noi ben trong co the lap trnh c sap xep theo hang va cot chay
gia cac LAB va cac phan t ngo vao/ngo ra (IOE: Input/Output Elements) c nh hng
xung quanh. Cau truc cua ho CPLD nay giong nh FPGA co the xem MAX II la FPGA co mat
o thap.
S khac nhau gia CPLD MAX II va cac CPLD thiet ke t SPLD la cach xay dng mot
ham logic. CPLD MAX II s dung cac bang tra LUT (Look-Up Tables) thay cho ma tran
AND/OR. Mot LUT ve c ban la loai bo nh co the lap trnh e tao ra cac ham SOP. Hai
phng phap nay c minh hoa nh hnh 1-18.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 17


H|nh -7. 5c dc khc| cuo MAX ||.

Lco| dung LU1. Lco| dung |cg|c mong AND/0k
H|nh -8. Phon b|et 2 k|eu xoy dung hom.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
18 y :+.~: .~ /
Nh a e cap CPLD MAX II co cach sap xep hang/cot cua cac ket noi ben trong thay
cho cach ket noi ben trong theo loai kenh co trong hau het cac CPLD. Co 2 phng phap c
minh hoa trong hnh 1-19.


Ket nc| ben trcng dung hong/cct Ket nc| thec k|eu kenh
H|nh -. Phon b|et 2 k|eu ket nc|.
Hau het cac CPLD dung cong nghe x ly khong bay hi cho cac iem noi lap trnh. Tuy
nhien MAX II dung cong nghe x ly nh SRAM nen chung co the bay hi tat ca cac logic a
lap trnh se mat het khi mat ien. Bo nh c gan vao ben trong chip e lu tr d lieu chng
trnh dung cong nghe bo nh khong bay hi va se nh cau hnh lai cho CPLD khi co ien.
|||. CPLD CUA HANC X|L|NX:
Cung giong nh Altera, Xilinx san xuat ra cac ho CPLD c sap xep theo mat o tch
hp, cong nghe x ly, ien ap nguon cung cap va toc o. Xilinx che tao ra nhieu ho CPLD nh
Cool Runner II, Cool Runner XPLA3 va XC9500. Ho XC9500 th co cau truc giong nh ho
CPLD MAX 7000 cua Altera s dung cau truc loai PAL/GAL. Trong phan nay chung ta ch
phan tch Cool Runner II.
Sau khi ket thuc phan nay ban co the: mo ta PLA va so sanh vi PAL, thao luan ve cau
truc CPLD Cool Runner II va mo ta cac khoi chc nang.
' / 3/\\/ 3 //)
Nh a trnh bay, cau truc cua CPLD la cach ma cac thanh phan ben trong c to chc
va sap xep. Cau truc cua ho Cool Runner II cua Xilinx th da vao cau truc mang logic lap trnh
PLA (Programmable Logic Array) tot hn cau truc PAL (Programmable Array Logic). Hnh 1-
20 so sanh cau truc PAL vi cau truc PLA n gian.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 19

H|nh -20. 5c sonh PAL vc| PLA.
Nh a trnh bay, PAL co mang cong AND lap trnh va theo sau la mang cong OR co nh
e tao ra cac bieu thc SOP nh hnh 1-20a. PLA co mang cong AND lap trnh va theo sau la
mang cong OR lap trnh nh hnh 1-20b.

CPLD Cool Runner II dung loai cau truc PLA. Cool Runner II co nhieu khoi chc nang FB
(Function Block) tng t nh LAB trong CPLD MAX 7000 cua Altera. Moi khoi chc nang FB
cha 16 macrocell. Cac khoi chc nang c ket noi ben trong bi mot ma tran ket noi ben
trong cai tien AIM tng t nh PIA trong MAX 7000. S o cau truc c ban cho Cool Runner II
c trnh bay hnh 1-21.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
20 y :+.~: .~ /

H|nh -2. 5c dc cou truc cuo Ccc| runner ||.
S o khoi CPLD cua Xilinx va cua Altera gan nh la giong nhau tuy nhien ben trong th
khac nhau.
CPLD ho Cool Runner II cha t 32 macrocell en 512 macrocell. Do co 16 macrocell cho
moi khoi chc nang, so lng khoi chc nang nam trong khoang t 2 en 32. S o khoi cua
mot khoi chc nang FB c trnh bay nh hnh 1-22.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 21

H|nh -22. Cou truc cuo mct khc| chuc nong F8.
Mang cong AND co 56 cong AND va mang cong OR lap trnh co 16 cong OR. Vi cau
truc PLA th bat ky thanh phan tch nao cung co the noi ti cong OR e tao nen bieu thc SOP
cho ngo ra. Vi kha nang cc ai moi khoi chc nang co the tao ra 16 ngo ra va moi ngo ra co
bieu thc SOP cha 56 thanh phan tch.
V du 1-2: Hay lap trnh ket noi ben trong khoi FB cua hnh 1-22 e tao ra ham chc nang
SOP t macrocell th 1 la: D C AB D C B A ABCD + + va ham cho macrocell th 2 la:
D ABC CD B A BCD A D BC A + + +
Giai: ket qua nh hnh 1-23:
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
22 y :+.~: .~ /

H|nh -23. M|nh hco chc v| du -2.

|V. L0C|C LAP 1kNH FPCA
Nh a trnh bay tren, cau truc phan loai CPLD bao gom cac khoi logic loai PAL/GAL
hoac PLA vi cac ket noi ben trong co the lap trnh. Ve c ban FPGA (Field Programmable
Gate Array) co cau truc khac khong dung mang loai PAL/PLA co mat o tch hp cao hn
nhieu so vi CPLD. Cac phan t dung e tao ra cac ham logic trong FPGA thng th nho hn
nhieu so vi cac thanh phan trong CPLD. Tng t trong FPGA th cac ket noi ben trong c
to chc theo hang va cot.
Sau khi ket thuc phan nay ban co the: mo ta cau truc c ban cua FPGA, so sanh FPGA vi
CPLD, thao luan ve LUT, thao luan ve FPGA dung cau truc SRAM va nh ngha loi cua
FPGA.
Co 3 thanh phan c ban trong FPGA la khoi logic co the nh cau hnh logic CLB
(Configurable Logic Block), cac ket noi ben trong va cac khoi ngo vao/ra c minh hoa nh
hnh 1-24.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 23

H|nh -24. Cou truc cc bon cuo FPCA.
Cac khoi co the nh cau hnh logic CLB trong FPGA th khong phc tap bang cac khoi
LAB hoac FB trong CPLD nhng thng th co nhieu thanh phan hn. Khi CLB kha n gian th
cau truc FPGA c goi la fine grained. Cac khoi IO nam xung quanh cua cau truc tao ra s
truy xuat ngo vao, ngo ra hoac ca hai chieu co the la chon mot cach oc lap en the gii ben
ngoai.
Ma tran phan loai cua cac ket noi ben trong co the lap trnh tao ra cac ket noi ben trong
cua CLB va ket noi en cac ngo vao va cac ngo ra. Cac FPGA ln co the co 10000 CLB va co
them bo nh va cac nguon tai nguyen khac.
Hau het cac nha che tao cac thiet b logic lap trnh thng sap xep thanh chuoi FPGA
phan loai theo mat o, cong suat tieu tan, ien ap nguon cung cap, toc o va mot vai mc o
khac nhau ve cau truc. FPGA la thiet b co the lap trnh lai va s dung cong nghe x ly SRAM
hoac ban cau ch e lap trnh cho cac iem noi. Mat o co the nam trong khoang t vai tram
module logic en sap x khoang 180000 module logic trong 1 vo vi so lng chan len en
1000. Nguon cung cap DC thng nam trong khoang 1,2V en 2,5V tuy thuoc vao loai chip.
' / 3 , /
Thng th khoi logic cua FPGA cha mot vai module logic kha nho tng t nh
macrocell trong CPLD. Hnh 1-25 trnh bay cac khoi CLB c ban nam trong cac ket noi ben
trong co the lap trnh hang/cot toan cuc c dung e ket noi cac khoi logic. Moi CLB c
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
24 y :+.~: .~ /
thiet lap t nhieu module logic nho hn va cac ket noi ben trong co the lap trnh cuc bo c
dung e ket noi cac module logic vi CLB.

H|nh -25. Coc khc| CL8 cuo FPCA.
/ \ 3
Mot module logic trong mot khoi logic cua FPGA co the c nh cau hnh cho ham logic
to hp, ham logic thanh ghi hoac cho ca 2. Flip flop la thanh phan logic ket hp va c dung
cho cac ham logic thanh ghi. S o khoi cua module logic tieu bieu dung cau truc LUT c
trnh bay nh hnh 1-26.

H|nh -26. 5c dc khc| cc bon cuo mcdu|e |cg|c trcng FPCA.
Thng th to chc cua mot LUT bao gom mot so cac o nh bang vi
n
2 , trong o n la so
lng cac bien ngo vao. V du: 3 ngo vao co the la chon en 8 o nh, do o LUT vi bien ngo
vao co the tao ra bieu thc SOP len en 8 thanh phan tch. Mot mo hnh mau cua 1 va 0 co the
c lap trnh vao trong cac o nh cua LUT c minh hoa nh hnh 1-27 e tao ra ham SOP
theo ch nh. Cac o nh cha so 1 co ngha la thanh phan tch c ket hp trong bieu thc
SOP cua ngo ra va o nh cha so 0 co ngha la thanh phan tch ket hp khong xuat hien trong
bieu thc SOP cua ngo ra.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 25
Ket qua bieu thc SOP ngo ra la
0 1 2 0 1 2 0 1 2 0 1 2
A A A A A A A A A A A A + + +

H|nh -27. Kho| n|em cc bon cuo LU1 ducc |op tr|nh de toc 50P ngc ro.
V du 1-3: Hay thiet lap LUT co 3 bien c ban c lap trnh e tao ra bieu thc SOP theo
sau:
0 1 2 0 1 2 0 1 2 0 1 2 0 1 2
A A A A A A A A A A A A A A A + + + +
Giai: ket qua nh hnh 1-28:

H|nh -28. M|nh hco chc v| du -3.
3/ 3 3 3 /\
Cac FPGA cung co the la khong bay hi neu dung cong nghe ban cau ch hoac co the bay
hn neu dung cong nghe SRAM. Khai niem bay hi co ngha la tat ca cac d lieu a lap trnh
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
26 y :+.~: .~ /
vao trong cac khoi CLB se b mat het khi mat ien. Do o, cac FPGA dung cong nghe SRAM
cha ca bo nh khong bay hi tch hp ben trong chip e lu tr chng trnh va d lieu va nh
cau hnh lai cho thiet b moi khi co ien tr lai hoac chung dung bo nh ben ngoai vi viec
chuyen d lieu c ieu khien vi x ly chu. Khai niem bo nh tch hp trong chip c minh
hoa nh hnh 1-29a va khai niem nh cau hnh lai dung vi x ly c trnh bay nh hnh 1-29b.

o. FPCA boy hc| d|nh |o| cou h|nh dung bc nhc khcng boy hc| ben trcng.


b. FPCA boy hc| d|nh |o| cou h|nh dung bc nhc khcng boy hc| vo v| xu |y.
H|nh -2. Kho| n|em ve FPCA boy hc|.
- / / 3/
Cac FPGA ve c ban giong nh cac phien trang ma ngi dung co the lap trnh cho cac
thiet ke logic. Cac FPGA tien li khi ma no cha cac mach logic loi phan cng (hard core).
Mot mach logic loi phan cng la mot phan logic trong FPGA c at vao ben trong bi nha
che tao e cung cap cac chc nang at biet va khong the lap trnh lai. V du neu khach hang
can mot vi x ly nho nh la mot phan cua thiet ke he thong th no co the c lap trnh vao
trong FPGA cho khach hang hoac no co the c cung cap nh la mot loi phan cng bi nha
che tao. Neu chc nang c tch hp vao ben trong co vai cau truc co the lap trnh c th no
c xem nh la chc nang loi mem (soft core).
u iem cua phng phap dung loi phan cng la cung mot thiet ke co the thc hien ay
u dung kha nang cua FPGA t hn neu so vi cach ngi dung s dung cach lap trnh, ket qua
la khong gian tren chip nho hn va thi gian thiet ke ngan hn.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 27
Khuyet iem cua phng phap dung loi phan cng la cac thong so ky thuat la co nh
trong qua trnh che tao va khach hang phai co kha nang dung c chc nang o. No khong the
thay oi ve sau.
Cac loi phan cng thng co tac dung cho cac chc nang ma chung c s dung pho bien
trong cac he thong so nh vi x ly, giao tiep ngo vao/ngo ra va x ly tn hieu so (Digital Signal
Processor). Co nhieu chc nang loi phan cng co the lap trnh trong FPGA. Hnh 1-30 minh hoa
cho khai niem loi phan cng c bao quanh bi CLB c lap trnh bi ngi s dung.

H|nh -30. Kho| n|em chuc nong |c| phon cung trcng FPCA.
Viec thiet ke cac loi phan cng thng c xay dng bi nha che tao FPGA va chung
thuoc s hu cua nha che tao. Cac thiet ke rieng bi nha che tao c at ten la Intellectual
Property (IP) s hu tr tue. Mot cong ty thng liet cac loai s hu tr tue ma chung co hieu
lc tren cac website. Nhieu s hu tr tue la s ket hp cua loi phan cng va loi phan mem. Vi
x ly la mot v du minh hoa co vai tnh nang mem deo trong la chon va ieu chnh mot vai
thong so bi ngi dung.
Cac FPGA cha cac vi x ly tch hp mot trong hai hoac ca hai loi phan cng va loi phan
mem va nhieu chc nang khac th c at ten la Platform FPGA bi v chung co the c
dung e ieu khien mot he thong ay u ma khong can them mot thiet b ho tr nao.
V. FPCA CUA AL1EkA
Altera san xuat ra nhieu ho FPGA bao gom Stratix II, Stratix , Cyclone va ACEX. Trong
phan nay chung ta ch khao sat ho Stratix II e minh hoa cho cac khai niem.
Sau khi ket thuc phan nay chung ta co the:
Thao luan ve cau truc c ban cua FPGA ho Stratix II, giai thch cach thanh phan c tao
ra trong FPGA, thao luan ve cac chc nang c tch hp.
' \/3 3 / 3 // )
S o khoi cua FPGA tong quat a c trnh bay nh hnh 1-24; cau truc cua Stratix II
va cac ho Altera khac th giong nhau. Chung eu co cau truc loai LUT cho cac module logic
c goi la module logic thch nghi ALM (Adaptive Logic Module) c trnh bay trong thiet
b tong quat LAB. Mat o c phan loai t 2000 LAB cho en 22000 LAB tuy thuoc vao cac
ho cu the va moi LAB co 8 ALM. Kch thc vo thay oi t 314 chan en 1173 chan. Thiet b
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
28 y :+.~: .~ /
yeu cau s dung nguon DC cung cap t 1,2V; 1,5V va 2,5V. Ho FPGA Stratix II s dung cong
nghe cua SRAM.
Hnh 1-31 trnh bay s o khoi cua cau truc LAB cua Stratix II. Moi LAB cha 8 ALM,
cac LAB c lien ket vi nhau thong qua cac ket noi hang va cot ben trong. Cac iem ket noi
cuc bo ben trong lien ket cac ALM vi moi LAB.

H|nh -3. 5c dc khc| cuo cou truc LA8 cuo 5trot|x || vo ALM
\ 3 3 /\
ALM la n v thiet ke c ban trong FPGA Stratix II. Moi ALM cha mot phan to hp
logic dung cau truc LUT va mach logic ket hp co the c lap trnh cho 2 ngo ra logic to hp
hoac hai ngo ra thanh ghi dch. Ben canh o, ALM co mach cong logic, cac flip flop va cac
mach logic khac cho phep thc hien chc nang tnh toan so hoc, chc nang em va thanh ghi
dch. S o khoi ALM cua Stratix II c trnh bay nh hnh 1-32.
Hcot dcng cuo ALM:
Mot ALM co the c lap trnh cho ra nhieu kieu hoat ong nh sau:
Kieu hoat ong bnh thng.
Kieu hoat ong LUT m rong.
Kieu tnh toan so hoc.
Kieu tnh toan so hoc dung chung.
Ngoai 4 kieu hoat ong th ALM co the c dung nh la 1 chuoi thanh ghi e xay dng
bo em va thanh ghi dch. Trong phan nay chung ta se khao sat kieu hoat ong bnh thng va
kieu hoat ong LUT m rong.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 29

H|nh -32. 5c dc khc| ALM cuo 5trot|x ||.
o. K|eu hcot dcng b|nh thucng
c s dung au tien e tao cac ham logic to hp. Mot ALM co the thc hien mot hoac
hai ham ngo ra to hp vi hai LUT cua no. V du ve 4 cau hnh LUT c minh hoa hnh 1-33.

H|nh -33. Coc cou h|nh cc the cc cuo LU1 trcng ALM c k|eu b|nh thucng.
Hai ham SOP moi ham co 4 bien hoac t hn co the c thc hien trong mot ALM
ma khong can dung cac ngo vao chia se. V du ban co the co 2 ham 4 bien, mot ham co 4
bien va mot ham 3 bien hoac hai ham 3 bien. Bang cach chia se cac ngo vao, ban co the co
bat ky to hp nao cua 8 ngo vao len en toi a 6 ngo vao cho moi LUT. Trong kieu hoat ong
bnh thng th ban b gii han la cac ham SOP ch co toi a la 6 bien.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
30 y :+.~: .~ /
b. K|eu hcot dcng LU1 mc rcng
Cho phep m rong ham len en 7 bien c minh hoa hnh 1-34. Mach ien AND OR
vi ngo vao ao la mot v du n gian cua mach don kenh. Mach don kenh la mot phan cua
mach logic dung rieng trong ALM.

H|nh -34. Mc rcng ALM de toc ro hom 50P 7 b|en trcng k|eu LU1 mc rcng.

V du 1-4: Mot ALM trong FPGA Stratix II c nh cau hnh hoat ong kieu LUT m
rong c trnh bay hnh 1-35. Hay xac nh bieu thc ngo ra SOP.

H|nh -35. M|nh hco chc v| du -4.
Giai: bieu thc ngo ra tren th AND vi bien ngo vao
0
A va bieu thc ngo ra ben di th
AND vi
0
A . Bieu thc sau cung nh sau:
0 2 3 4 5 6 0 2 3 4 5 6 0 2 3 4 5 6 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A + + + + +
/ /3
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 31
S o khoi tong quat cua FPGA Stratix II c trnh bay hnh 1-36. FPGA cha cac
thanh phan bo nh va chc nang x ly tn hieu so DSP. Chc nang cua DSP nh cac mach loc
so thng c s dung nhieu trong cac he thong. Khi quan sat s o khoi, cac khoi tch hp
ben trong c sap xep khap ni trong ma tran ket noi ben trong cua FPGA va cac phan t
ngo vao/ngo ra c at xung quanh chu vi FPGA.

H|nh -36. 5c dc khc| cuo FPCA 5trot|x ||.
V|. FPCA CUA X|L|NX
Xilinx co 2 ho FPGA chnh la Spartan va Virtex va co nhieu loai khac nhau trong moi ho.
V du Spartan 3 va Spartan IIE, Virtex-4, Virtex II va Virtex II Pro X. Xilinx nh ro Virtex-4,
Virtex II va Virtex II Pro X la cac FPGA loai platform (nen) bi v chung tch hp nhieu chc
nang nh bo nh, vi x ly, bo thu phat va cac phan cng khac va cac loi phan mem IP. Cac ho
FPGA thng th khac ve mat o tch hp va cac thong so ky thuat. Hau het cac thiet b cua
Xilinx co cau truc FPGA truyen thong, tuy nhien Virtex II Pro X co cai goi la cau truc khoi
module ch nh ng dung ASMBL (Application Specific Modular Block c phat am la
assemble) co tren 1 t transistor trong 1 chip n.
' / 3 , / 3/ 3 )
Vung logic nh cau hnh cua hau het cac FPGA ho Xilinx c chia thanh nhieu khoi
logic co the nh cau hnh CLB vi moi CLB cha nhieu n v logic c ban c la cac te bao
logic (logic cell - LC). Moi te bao logic LC s dung mach logic LUT truyen thong co 4 ngo vao
va them mach logic cong va mot flip flop. Mot LUT co 4 ngo vao co the tao ra t mot thanh
phan tch cho en ham SOP cha 16 thanh phan tch. Hai te bao logic LC giong nhau c goi
la slice (lat mong). Hnh 1-37 minh hoa cac cap logic nh cau hnh t te bao logic cho en
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
32 y :+.~: .~ /
CLB. Mat o tch hp nam trong khoang t 2000 en 74000 te bao logic LC trong mot thiet b
Virtex n.

H|nh -37. M|nh hco coc cop |cg|c d|nh cou h|nh tu te boc |cg|c chc den CL8.

Slice n gian (hai te bao logic LC) vi logic chuoi lien tiep c trnh bay hnh 1-38.
Co mach a hp (MUX) danh rieng nam trong mach logic ket hp cua moi LC c dung
trong chuoi lien tiep va mot cong OR danh rieng nam trong slice.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 33
Hnh 1-38a trnh bay v du cach ma mot slice trong CLB co the c nh cau hnh nh la
mot cong AND e tao ra thanh phan tch 8 bien. Hai slice co the c nh cau hnh e tao ra
mot ham SOP vi 2 thanh phan tch 8 bien c trnh bay hnh 1-38b. Toan bo CLB cua 4
slice co the c nh cau hnh thanh mot chuoi lien tiep e tao ra mot ham SOP vi 4 thanh
phan tch co 8 bien c trnh bay nh hnh 1-38c. Bieu thc SOP dai hn na co the c thc
hien dung them cac CLB m rong.

(o[

(b[
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
34 y :+.~: .~ /

(c[
H|nh -38. V| du coch dung chuc| nc| t|ep de mc rcng b|eu thuc 50P.

V du 1-5: Hay trnh bay cach cong AND co 16 ngo vao co the tao ra bieu thc trong CLB.
Giai: Hai slice c nh cau hnh c trnh bay hnh 1-39 la ket qua cua cong AND co
16 ngo vao.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 35

H|nh -3. M|nh hco chc v| du -5.
/ 3/ 3 ./ / /\
o. Cou truc truyen thcng
Nh a biet, cau truc FPGA truyen thong xuat hien nh la mot mang cua cac khoi logic
(CLB hoac LAB) c bao boc xung quanh bi cac te bao ngo vao/ngo ra co the nh cau hnh.
So LCB trong FPGA tuy thuoc vao so lng cac phan t IO co the at xung quanh. Khi loi IP
nh DSP va bo nh tch hp ben trong khi c yeu cau th mot lng logic nh cau hnh phai
mat i va tai mot vai v tr c thay the bang IO neu co yeu cau. Khi nhieu loi IP c them
vao th kch thc vat ly cua FPGA phai tang len e am bao so lng logic cau hnh can thiet
va tang them so lng IO. Khai niem nay c minh hoa bang hnh 1-40.

(o[ FPCA vc| |cg|c d|nh h|nh doy du. (b[ FPCA cung k|ch thucc vc| bc nhc
vo |c| |P (D5P[ nen cc |t CL8 hcn.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
36 y :+.~: .~ /

(c[ FPCA cc nh|eu bc nhc, them |c| D5P vo |c| v| xu |y se yeu cou k|ch thucc |cn hcn.
H|nh -40. 1|ch hcp nh|eu chuc nong |P ket quo |om g|om CL8 vo/hcoc pho| tong k|ch
thucc ch|p.
Logic cau hnh trong FPGA cang phc tap th cang dung nhieu IO. Moi lien he rang buoc
gia logic va IO se dan en tang kch thc chip va tang gia thanh. Ngoai ra mot van e khac
vi FPGA platform la khi them cac chc nang loi IP tch hp ben trong neu co yeu cau th phai
thiet ke lai thanh phan chnh hoac thiet ke lai mot phan trong cach bo tr chip (layout) co the
c yeu cau se lam tang them gia thanh.
o. Cou truc A5M8L
Xilinx a xay dng mot phng phap mem deo cho FPGA platform chip Virtex II Pro X
e khac phuc mot vai han che xuat hien trong cau truc truyen thong. Cau truc ASMBL la cau
truc s dung cot thay v dung cau truc hang/cot. Cac IO c at rai rac khap ni tot hn la at
xung quanh, dan en so lng IO cua no tang ma khong can lam tang kch thc chip. Moi cot
ve c ban la mot dai logic co the c thay the bang dai logic khac ma khong can thiet ke lai
cach bo tr chip. Cac v du ve cac loai cua cac dai logic la cac khoi logic nh cau hnh CLB,
khoi IO, bo nh va cac loi phan cng va phan mem nh DSP va vi x ly.
So lng khac nhau cua moi loai dai logic co the c tron lai e tng thch vi cac yeu
cau ng dung rieng biet. V du, trong cau hnh n gian nhat th co the pha tron cac dai CLB va
cac dai khoi IO c minh hoa nh hnh 1-41a. Nhieu hoac t hn cua ca 2 cung co the c s
dung tuy thuoc vao cac yeu cau.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 37
Neu can nhieu bo nh th mot hoac nhieu dai CLB co the c thay the nh hnh 1-41b.
Neu vung rieng biet trong ng dung la x ly tn hieu so th co the them vao cac loi IP DSP tron
vi bo nh nh hnh 1-41c. Hnh 1-41d trnh bay cac loi vi x ly c them vao.

(o[ (b[

(c[ (d[
H|nh -4. M|nh hco cou truc A5M8L cuo FPCA p|otfcrm.

V||. PHAN MEM LAP 1kNH
e s dung thiet b logic lap trnh th phai co phan cng va phan mem ket hp vi nhau.
Tat ca cac nha che tao SPLD, CPLD va FPGA cung cap phan mem ho tr cho moi thiet b phan
cng. Cac goi phan mem nam trong danh sach phan mem c dung e thiet ke di s giup
cua may tnh CAD. Trong phan nay phan mem lap trnh c gii thieu mot cach tong quat.
Sau khi ket thuc phan nay ban co the: giai thch quy trnh lap trnh cho cac thanh phan cua
thiet ke, mo ta giai oan thiet ke, mo ta giai oan mo phong chc nang, mo ta giai oan tong
hp, mo ta giai oan thi hanh, mo ta mo phong theo thi gian, mo ta cach tai chng trnh.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
38 y :+.~: .~ /
Quy trnh lap trnh thiet ke c xem nh la dong thiet ke (design flow). Gian o dong
thiet ke c ban dung e thc hien thiet ke logic cho thiet b lap trnh c trnh bay nh hnh 1-
42. Hau het cac goi phan mem rieng le se ket hp cac cong oan cua quy trnh lai vi nhau va
qua trnh x ly hoan toan t ong. Thiet b e c lap trnh thng c xem la thiet b ch
(target device)

H|nh -42. 5c dc dcng th|et ke tcng quot de |op tr|nh chc 5PLD, CPLD hcoc FPCA.
Phai co 4 thiet b e co the lap trnh cho thiet b la: may tnh, phan mem lap trnh, thiet b
logic lap trnh (SPLD, CPLD hoac FPGA) va thiet b ket noi may tnh vi thiet b lap trnh (cap
hoac mach nap). Tat ca cac thanh phan nay c minh hoa nh hnh 1-43.

+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 39

H|nh -43. Coc th|et b| cc bon de |op tr|nh chc 5PLD, CPLD hcoc FPCA.
' /
Gia s rang chung ta co mot thiet ke mach ien logic muon ieu khien bang thiet b lap
trnh th chung ta co the thiet ke tren may tnh bang mot trong hai cach c ban: thiet ke dung s
o nguyen ly (schematic entry) va cach dung ngon ng (text entry).
e dung cach thiet ke bang ngon ng th phai lam quen vi ngon ng HDL nh VHDL,
Verilog, ABEL hoac AHDL. Hau het cac nha che tao thiet b lap trnh cung cap cac goi phan
mem ho tr ngon ng VHDL va Verilog bi v chung la ngon ng HDL chuan. Nhieu nha che
tao con cung cap them ngon ng ABEL, AHDL.
Kieu thiet ke dung s o mach cho phep chung ta at cac k hieu cua cac cong logic va
cac chc nang logic khac t th vien len man hnh va ket noi chung theo yeu cau cua thiet ke.
Vi kieu thiet ke nay th can biet cac ngon ng HDL. Hnh 1-44 minh hoa cho ca 2 kieu thiet ke
cho mot mach ien logic AND-OR n gian.

+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
40 y :+.~: .~ /

H|nh -44. M|nh hco chc 2 k|eu |op tr|nh.
Xoy dung sc dc |cg|c:
Khi xay dng mach ien logic ay u tren man hnh th no c goi la s o phang flat.
Cac mach ien logic phc tap hn th kho ma tng thch vi man hnh. Chung ta co the thiet ke
mach ien logic thanh nhieu oan (segment), lu tr moi oan nh la mot k hieu khoi va sau
o ket noi cac k hieu khoi lai vi nhau e tao thanh mot mach ien hoan chnh c goi la
thiet ke co th t.
V du thiet ke mach ien co bieu thc SOP nh sau:
( ) ( )
0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
A A A A A A A A A A A A A A A A A A A A Z + + + + =
Chung ta dung phng phap thiet ke co th t va xay dng mach logic cho 2 thanh phan
tong trong phng trnh, lam n gian moi mach ien logic bang mot k hieu duy nhat, sau khi
thiet ke xong ca 2 mach ien th at chung len man hnh va ket noi cac ngo ra vi cong OR e
tao thanh mach hoan chnh tat ca c minh hoa bang hnh 1-45.

o. 1h|et ke thonh phon thu gcm tcng cuo 2 t|ch.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 41

b. Lom dcn g|on khc| moch d|en bong k| h|eu |cg|c .

c. 1h|et ke thonh phon thu 2 gcm tcng cuo 3 t|ch.

d. Lom dcn g|on khc| moch d|en bong k| h|eu |cg|c 2.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
42 y :+.~: .~ /

e. Ket nc| 2 khc| |cg|c vo |cg|c 2 bong ccng 0k.
H|nh -45. M|nh hco chc k|eu |op tr|nh tung dcon.
Toan bo mach ien tren co the at len man hnh nhng phng phap thiet ke theo trnh t
rat tien li khi mach ien logic ln va phai chia ra thanh nhieu phan.
hnh 1-46e, mach ien logic co the lam n gian bang 1 k hieu khac va c s dung
e thiet ke mach ien ln hn hoac co the lu va dung lai cho cac thiet ke khac c minh hoa
nh hnh 1-46.

+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 43

H|nh -46. Luu thonh khc| |cg|c 3.
\ 3 /3
Muc ch cua chc nang mo phong trong dong thiet ke la e am bao chac chan thiet ke
hoat ong ung theo yeu cau trc khi tong hp thanh thiet ke phan cng. Ve c ban sau khi
mach ien logic c bien dch th sau o co the mo phong bang cach cung cap cac dang song
au vao va kiem tra dang song ngo ra cho cac to hp ngo vao co the co dung trnh soan thao
dang song.
Trnh soan thao dang song cho phep la chon cac nut (cac ngo vao va cac ngo ra) muon
kiem tra. Ten cac ngo vao va ngo ra a chon xuat hien tren man hnh soan thao dang song bang
k hieu hoac ten khac e xac nh cho moi mot ngo vao hoac mot ngo ra c trnh bay hnh
1-47. Khi bat au th tat ca cac ngo vao mac nhien mc 0 va cac ng cheo song song tng
trng cho tn hieu cha xac nh. Co the la chon cac khoang thi gian e hien th.

H|nh -47. Mon h|nh scon thoc dong scng tcng quot .
Bc tiep theo chung ta xay dng dang song cho moi ngo vao bang cach nhap vao 1 hoac
0 cho moi khoang thi gian. Hnh 1-48 trnh bay cac dang song ngo vao.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
44 y :+.~: .~ /

H|nh -48. 1h|et |op coc dong scng ngc voc.
Sau khi thiet lap cac dang song ngo vao th m ca so ieu khien mo phong e thiet lap
thi gian bat au va thi gian ket thuc cho viec mo phong va ch nh cac khoang thi gian hien
th. Khi bat au mo phong th dang song cua tn hieu Z se c hien th tren man hnh dang
song nh hnh 1-49.
Ket qua dang song ngo ra Z cua v du nay se cho chung ta biet thiet ke hoat ong ung
hay khong ung. Trong trng hp nay dang song ngo ra la ung vi dang song ngo vao a
chon. Khi dang song ngo ra khong ung th phai quay lai kiem tra thiet ke ban au cho en khi
mach hoat ong ung.

H|nh -4. Dong scng ngc voc vo ro kh| choy mc phcng.
3
Moi khi mach logic c xay dng va c mo phong chc nang e kiem tra ung sai cua
mach logic thiet ke th phan mem bien dch a t ong thc hien mot vai cong oan e chuan b
cho viec nap thiet ke vao cho thiet b lap trnh.
Trong cong oan tong hp cua dong thiet ke th thiet ke c toi u theo cac thanh phan
e lam giam so lng cong, thay the cac phan t logic bang cac phan t logic khac ma chung co
the thc hien cung mot chc nang nhng hieu qua hn va loai tr cac thanh phan logic tha.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 45
Ngo ra cuoi cung t cong oan tong hp la liet ke ket noi (netlist) chung dien ta trang
thai toi u cua mach ien logic.
- )
Liet ke li ve c ban la mot danh sach liet li ma chung mo ta cac thanh phan va cach
ket noi vi nhau. Tong quat, liet ke li cha cac tham chieu mo ta cac thanh phan va cac phan
t c s dung.
Moi lan mot thanh phan nh cong logic c s dung trong liet ke li th no c goi la
instance. Moi instance co xac nh liet ke cac ket noi. Cac iem ket noi c goi la cac cang
(port) hoac cac chan (pin).
Thng th moi instance se co mot ten duy nhat, v du nh neu co 2 instance cua cac cong
AND th mot la and1 va cong con lai la and2. Ngoai ten ra con co ten khac, cac li la cac
ng day noi vi nhau trong mach ien. Bang liet ke cac li thng mo ta tat ca cac
instance va cac thuoc tnh cua chung, sau o mo ta tng li va at biet la cac port noi vi moi
instance.
Mach ien logic AND-OR a thiet ke tren c trnh bay hnh 1-50a co the c toi
u thanh mach ien hnh 1-50b. Trong phan minh hoa nay, trnh bien dch thay the cac cong OR
va bang mot cong OR co 5 ngo vao, bo hai cong ao tha trong mach.

(o[. Moch d|en th|et ke (b[. Moch tc| uu sou kh| tcng hcp
H|nh -50. M|nh hco chc chuc nong tcng hcp.
Phan mem tong hp tao ra danh sach liet ke li. e minh hoa cho khai niem tao ra danh
sach li th hnh 1-51a se trnh bay cach gan ten cho li, gan ten cho instance va gan ten cho
IO. Danh sach liet ke li c trnh bay hnh 1-51b khong can thiet phai giong bat ky danh
sach liet ke nao ve cu phap va khuon kho. Danh sach liet ke nham xac nh cac loai thong tin
can e mo ta mach ien. Mot khuon kho c dung cho bang liet ke cac li la EDIF
(Electronic Design Interchange Format).

+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
46 y :+.~: .~ /

(o[ (b[
H|nh -5. 5c dc moch vo donh soch ||et ke.
/ \\ /
Sau khi thiet ke a c tong hp th trnh bien dch thi hanh thiet ke ve c ban cong
viec nay chnh la sap xep thiet ke e no co the tng thch vi thiet b lap trnh a chon bang
cach da vao cau truc va cau hnh chan.
Qua trnh x ly nay goi la lam cho tng thch (fitting). e ket thuc cong oan thi hanh
cua dong thiet ke th phan mem phai biet thiet b ro rang va co ay u cac thong tin chi tiet ve
chan. D lieu ay u cho tat ca cac thiet b thng c lu trong th vien cua bo nh va ngi
thiet ke ch can chon ung thiet b lap trnh.
\ 3 3/
Phan nay nam trong dong thiet ke c thc hien sau khi phan mem thi hanh bien dch va
trc khi nap chng trnh vao thiet b. Mo phong theo thi gian e kiem tra mach ien hoat
ong tai tan so thiet ke va khong co thi gian tre hoac cac van e ve thi gian khac lam anh
hng en hoat ong cua mach.
Phan mem thiet ke dung cac thong tin cua thiet b lap trnh nh thi gian tr hoan cua cac
cong e thc hien mo phong theo thi gian cua thiet ke.
Khi mo phong chc nang a c thc hien th mach ien se hoat ong ung theo quan
iem logic. Khi mo phong chc nang th cac thong so ch nh ve thiet b ch la khong can thiet
nhng khi mo phong ve thi gian th phai la chon thiet b ch. Phan mem soan thao dang song
co the c dung e xem ket qua mo phong cung nh mo phong chc nang c minh hoa nh
hnh 1-52.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 47
Neu khong co van e g vi ket qua mo phong nh c trnh bay hnh 1-52a th thiet ke
co the nap vao thiet b lap trnh. Tuy nhien, gia s rang cac khoang mo phong thi gian phat
hien khong eu hay khong giong nhau phu thuoc vao thi gian tre nh c trnh bay hnh 1-
52b.


H|nh -52. M|nh hco chc mc phcng thc| g|on.
Viec thc thi khong giong nhau ch xay ra trong mot khoang thi gian rat ngan trong dang
song. Trong trng hp nay can phai phan tch thiet ke mot cach can than e tm ra nguyen
nhan va sau o hieu chnh lai thiet ke va lap lai cac bc thiet ke.
7 / , / / 3 ,
Sau khi kiem tra mo phong chc nang va mo phong theo thi gian va thiet ke a hoat
ong ung th co the tien hanh download. Chuoi bit nh phan c tao ra tng trng cho thiet
ke va c gi en thiet b ch e t ong nh cau hnh cho thiet b. Sau khi thc hien xong th
thiet ke co the c kiem tra bang mach ien thc te. Hnh 1-53 trnh bay khai niem cho qua
trnh download.
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
48 y :+.~: .~ /

H|nh -53. Dcwn|cod th|et ke voc th|et b| |op tr|nh.
V|||. CAU H0| 0N 1AP VA 8A| 1AP
Cau 1-1. PAL tng trng cho cai g ?
Cau 1-2. GAL tng trng cho cai g ?
Cau 1-3. S khac nhau gia PAL va GAL la g ?
Cau 1-4. Mot macrocell c ban cha cac thanh phan nao?
Cau 1-5. CPLD la g?
Cau 1-6. LAB tng trng cho cai g ?
Cau 1-7. Mo ta LAB trong CPLD MAX 7000 ?
Cau 1-8. Muc ch ca bo m rong chia se la g ?
Cau 1-9. Muc ch ca bo m rong song song la g ?
Cau 1-10. CPLD MAX II khac vi MAX 7000 iem nao ?
Cau 1-11. S khac nhau c ban cua CPLD hang Altera va hang Xilinx la g?
Cau 1-12. Hay mo ta PLA ?
Cau 1-13. PLA khac vi PAL la g ?
Cau 1-14. FB tng trng cho cai g ?
Cau 1-15. FPGA khac vi CPLD nh the nao ?
Cau 1-16. CLB tng trng cho cai g ?
Cau 1-17. Mo ta LUT va cho biet chc nang cua no ?
Cau 1-18. S khac nhau gia ket noi ben trong toan cuc va cuc bo trong FPGA la g ?
Cau 1-19. Loi FPGA la g ?
Cau 1-20. nh ngha thuat ng IP co lien en nha san xuat FPGA ?
+++ ' 3 :+-. ~ ~. :. ~ :++ + .y-+ ++ +.
y :+.~: .~ / 49
Cau 1-21. n v thiet ke logic c ban trong FPGA Stratix II la g?
Cau 1-22. Co bao nhieu ALM trong LAB?
Cau 1-23. Cai g tao ra cac ham logic to hp trong ALM?
Cau 1-24. Co bao nhieu ham SOP co the c tao ra t mot ALM ?
Cau 1-25. Hay cho biet ten cua 2 loai chc nang tch hp trong Stratix II ?
Cau 1-26. CLB trong FPGA cua Xilinx cha cai g ?
Cau 1-27. LC cha cai g ?
Cau 1-28. Hay mo ta slice trong FPGA cua Xilinx ?
Cau 1-29. Chuoi noi tiep SOP la g ?
Cau 1-30. ASMBL tng trng cho cai g ?
Cau 1-31. Hay liet ke cac cong oan cua dong thiet ke cho mot thiet b lap trnh ?
Cau 1-32. Hay liet ke cac phan t c ban e lap trnh cho CPLD va FPGA?
Cau 1-33. Hay cho biet chc nang cua bang liet ke ca li ?
Cau 1-34. Co bao nhieu ham SOP co the c tao ra t mot ALM ?
Cau 1-35. Hay cho biet ten cua 2 loai chc nang tch hp trong Stratix II ?


end