ch8 9 5m

yingqichen@sjtu.edu.
cn
VHDL
Simulation & Synthesis

ROMRAMFIFO

DT JK

8b

condsig.vhd
Library IEEE ;
use IEEE.std_logic_1164.all ;

ENTITY condsig IS
PORT
( input0, input1, sel : IN BIT;
output : OUT BIT);
END condsig;

ARCHITECTURE maxpld OF condsig IS
BEGIN
output <= input0 WHEN sel = '0' ELSE input1;
END maxpld;
input1
input2
sel
output
Reg12.vhd
Library IEEE ;
ENTITY reg12 IS
PORT( d : IN BIT_VECTOR(11 DOWNTO 0);
clk : IN BIT;
q : OUT BIT_VECTOR(11 DOWNTO 0));
END reg12;

ARCHITECTURE a OF reg12 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1';
q <= d;
END PROCESS;
END a;

D Q

CLK

Comparator8.vhd
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT688 is
port(Q, P : in std_logic_vector(7 downto 0);
GBAR : in std_logic; PEQ : out std_logic);
end HCT688;

architecture VER1 of HCT688 is
begin
PEQ <= '0' when ((To_X01(P) = To_X01(Q)) and (GBAR = '0'))
else '1';
end VER1;
Comp
P
Q
PEQ
GBAR
Comparator8.vhd (1)
Comp
P
0~7

Q
0~7
PEQ
GBAR
Comp
P
8~15

Q
8~15
PEQ
Latchinf.vhd
Library IEEE ;

ENTITY latchinf IS
PORT
( enable, data : IN BIT;
q : OUT BIT);
END latchinf;

ARCHITECTURE maxpld OF latchinf IS
BEGIN
latch : PROCESS (enable, data)
BEGIN
IF (enable = '1') THEN
q <= data;
END IF;
END PROCESS latch;
END maxpld;
data q

enable
conversion_altera.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY adder IS
PORT (op1, op2 : IN UNSIGNED(7 downto 0);
result : OUT INTEGER);
END adder;

ARCHITECTURE maxpld OF adder IS
BEGIN
result <= CONV_INTEGER(op1 + op2);
END maxpld;
Op1
Op2
result
condsigm.vhd
Library IEEE ;

ENTITY condsigm IS
PORT
( high, mid, low : IN BIT;
q : OUT INTEGER);
END condsigm;

ARCHITECTURE maxpld OF condsigm IS
BEGIN
q <= 3 WHEN high = '1' ELSE -- when high
2 WHEN mid = '1' ELSE -- when mid but not high
1 WHEN low = '1' ELSE -- when low but not mid or high
0; -- when not low, mid, or high
END maxpld;
high
mid
q
low
3
2
1
0
Selesigen.vhd
Library IEEE ;

PACKAGE meals_pkg IS
TYPE MEAL IS (BREAKFAST, LUNCH, DINNER, MIDNIGHT_SNACK);
END meals_pkg;

USE work.meals_pkg.all;

ENTITY selsigen IS
PORT
( previous_meal : IN MEAL;
next_meal : OUT MEAL);
END selsigen;

ARCHITECTURE maxpld OF selsigen IS
BEGIN
WITH previous_meal SELECT
next_meal <= BREAKFAST WHEN DINNER | MIDNIGHT_SNACK,
LUNCH WHEN BREAKFAST,
DINNER WHEN LUNCH;
END maxpld;

Dev164.vhd
library IEEE;

ENTITY dev164 IS
PORT(a, b, nclr, clock : IN BIT;
q : BUFFER BIT_VECTOR(0 TO 7));
END dev164;
ARCHITECTURE version1 OF dev164 IS
BEGIN
PROCESS(a,b,nclr,clock)
BEGIN
IF nclr = '0' THEN
q <= "00000000";
ELSE
IF clock'EVENT AND clock = '1 THEN
FOR i IN q'RANGE LOOP
IF i = 0 THEN q(i) <= (a AND b);
ELSE
q(i) <= q(i-1);
END IF;
END LOOP;
END IF;
END IF;
END PROCESS;
END version1;
a
b
clk
nclr
q(0) q(1) q(2) q(3) q(4) q(5) q(6) q(7)
Compinst.vhd
LIBRARY altera;
USE altera.maxplus2.ALL;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY compinst IS
PORT
( data, clock, clearn, presetn : IN STD_LOGIC;
q_out : OUT STD_LOGIC;
a, b, c, gn : IN STD_LOGIC;
d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
y, wn : OUT STD_LOGIC );
END compinst;

ARCHITECTURE a OF compinst IS

BEGIN
dff1 : dff PORT MAP (d =>data, q => q_out, clk => clock, clrn => clearn, prn => presetn);
mux : a_74151b PORT MAP (c, b, a, d, gn, y, wn);
END a;
prn
d q
clk
clrn
presetn
clearn
clock
data
q_out
dff
a_74151b
c
b
a
gp
d
y
wp
TTL374.vhd
LIBRARY ieee;

ENTITY ttl374 IS
PORT(clock, oebar : IN std_logic;
data : IN std_logic_vector(7 DOWNTO 0);
qout : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY ttl374;

ARCHITECTURE using_1164 OF ttl374 IS
--internal flip-flop outputs
SIGNAL qint : std_logic_vector(7 DOWNTO 0);
BEGIN
qint <= data WHEN rising_edge(clock); --d-type flip flops
qout <= qint WHEN oebar = '0' ELSE "ZZZZZZZZ"; --three-state buffers
END ARCHITECTURE using_1164;
qint
data

clock
oebar
qout
HCT245.vhd
library IEEE;

entity HCT245 is
port(A, B : inout std_logic_vector(7 downto 0);
DIR, GBAR : in std_logic);
end HCT245;

begin
A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');
B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');
end VER1;

A(0)
A(1)

A(6)
A(7)

GBAR

DIR
B(0)
B(1)

B(6)
B(7)
Mux.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mux is port (
a, b, c, d: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
x: out std_logic_vector(3 downto 0));
end mux;
architecture archmux of mux
is
begin
mux4_1: process (a, b, c, d, s)
begin
if s = "00" then
x <= a;
elsif s = "01" then
x <= b;
elsif s = "10" then
x <= c;
else
x <= d;
end if;
end process mux4_1;
end archmux;

a
b
c
d
s
x
HCT175.vhd
library IEEE;
entity HCT175 is
port(D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
CLRBAR, CLK : in std_logic);
end HCT175;

begin
Q <= (others => '0') when (CLRBAR = '0')
else D when rising_edge(CLK)
else unaffected; -- VHDL 93
end VER1;
CLRBAR
D Q

CLK
Cntrnbit.vhd
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;

ENTITY cntrnbit IS
GENERIC(n : Positive := 8);
PORT(
clock, reset, enable : IN Std_logic;
count : OUT Std_logic_vector((n-1) DOWNTO 0)
);
END cntrnbit;
ARCHITECTURE v1 OF cntrnbit IS
SIGNAL count_int : Std_logic_vector((n-1)
DOWNTO 0);
BEGIN

PROCESS
BEGIN
WAIT UNTIL rising_edge(clock);
IF reset = '1' THEN
count_int <= (OTHERS => '0');
ELSIF enable = '1' THEN
count_int <= count_int + 1;
ELSE
NULL;
END IF;
END PROCESS;
count <= count_int;
END v1;

count
clock reset enable
Seg7dec.vhd
LIBRARY ieee;

ENTITY seg7dec IS
PORT(
bcdin : IN std_logic_vector(3 DOWNTO 0);
segout : OUT std_logic_vector(6 DOWNTO 0));
END seg7dec;
ARCHITECTURE ver3 OF seg7dec IS
BEGIN
WITH bcdin SELECT
segout <= "1000000" WHEN X"0",
"1100111" WHEN X"1",
"1101101" WHEN X"2",
"0000011" WHEN X"3",
"0100101" WHEN X"4",
"0001001" WHEN X"5",
"0001000" WHEN X"6",
"1100011" WHEN X"7",
"0000000" WHEN X"8",
"0000001" WHEN X"9",
"-------" WHEN OTHERS;
END ver3;
a
d
b
c
f
e
g
a b c d e f g
1
0
Hamenc.vhd
LIBRARY ieee;
ENTITY hamenc IS
PORT(datain : IN BIT_VECTOR(0 TO 3);
--d0 d1 d2 d3
hamout : OUT BIT_VECTOR(0 TO 7));
--d0 d1 d2 d3 p0 p1 p2 p4
END hamenc;
ARCHITECTURE ver2 OF hamenc IS
SIGNAL p0, p1, p2, p4 : BIT; --check bits
BEGIN
--generate check bits
p0 <= (datain(0) XOR datain(1)) XOR datain(2);
--connect up outputs
hamout(4 TO 7) <= (p0, p1, p2, p4);
hamout(0 TO 3) <= datain(0 TO 3);
END ver2;
d0 d1 d2 d3 p0 p1 p2 p3
d0 d1 d2 d3
Hamdec.vhd
LIBRARY ieee;
ENTITY hamdec IS
PORT(hamin : IN BIT_VECTOR(0 TO 7); --d0 d1 d2 d3 p0 p1 p2 p4
dataout : OUT BIT_VECTOR(0 TO 3); --d0 d1 d2 d3
sec, ded, ne : OUT BIT); --diagnostic outputs
END hamdec;

ARCHITECTURE ver1 OF hamdec IS
BEGIN
PROCESS(hamin)
VARIABLE syndrome : BIT_VECTOR(3 DOWNTO 0);
BEGIN
--generate syndrome bits
syndrome(0) := (((((((hamin(0) XOR hamin(1)) XOR hamin(2)) XOR hamin(3))
XOR hamin(4)) XOR hamin(5)) XOR hamin(6)) XOR hamin(7));
syndrome(1) := (((hamin(0) XOR hamin(1)) XOR hamin(3)) XOR hamin(5));
IF (syndrome = "0000") THEN --no errors
ne <= '1';
ded <= '0';
sec <= '0';
dataout(0 TO 3) <= hamin(0 TO 3);
ELSIF (syndrome(0) = '1') THEN --single bit error
ne <= '0';
ded <= '0';
sec <= '1';
CASE syndrome(3 DOWNTO 1) IS
WHEN "000"|"001"|"010"|"100" =>
dataout(0 TO 3) <= hamin(0 TO 3); -- parity errors
WHEN "011" => dataout(0) <= NOT hamin(0);
dataout(0) <= hamin(0);
dataout(3) <= hamin(3);
END CASE;
--double error
ELSIF (syndrome(0) = '0') AND
(syndrome(3 DOWNTO 1) /= "000") THEN
ne <= '0';
ded <= '1';
sec <= '0';
dataout(0 TO 3) <= "0000";
END IF;
END PROCESS;
END ver1;
d0 d1 d2 d3 p0 p1 p2 p3
d0 d1 d2 d3
Pldcntr8.vhd
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;

ENTITY pldcntr8 IS
PORT (clk, load : IN Std_logic;
datain : IN Std_logic_vector(7 DOWNTO 0);
q : OUT Std_logic_vector(7 DOWNTO 0);
tc : OUT Std_logic);
END pldcntr8;
ARCHITECTURE using_std_logic OF pldcntr8 IS
SIGNAL count : Std_logic_vector(7 DOWNTO 0);
BEGIN
PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
IF load = '1' THEN
count <= datain;
ELSE
count <= count - 1;
END IF;
END PROCESS;

tc <= '1' WHEN count = "00000000" ELSE '0';
q <= count;

END using_std_logic;
q tc
datain clk load
(-1)
cntr3.vhd
library ieee;

ENTITY cntr3 IS
PORT(
clock : IN BIT;
count : OUT NATURAL);
END cntr3;
ARCHITECTURE using_wait OF cntr3 IS
BEGIN
PROCESS
BEGIN
--WAIT UNTIL (clock'EVENT AND clock = '1');
WAIT UNTIL clock = '1';
count <= 0;
count <= 1;
count <= 2;
END PROCESS;
END using_wait;
0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1, 2, 0, 1,
HCT139.vhd
library IEEE;
entity HCT139 is
port(A2, B2, G2BAR, A1, B1, G1BAR : in std_logic;
Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic);
end HCT139;
begin
Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';
end VER1
Y1
Y2
Y10
Y11
Y12
Y13
Y20
Y21
Y22
Y23
B1 A1 B2 A2
Addn.vhd
library IEEE;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no. of bits less one
PORT(addend, augend : IN BIT_VECTOR(0 TO n);
carry_in : IN BIT; carry_out : OUT BIT;
sum : OUT BIT_VECTOR(0 TO n));
END addn;
ARCHITECTURE generated OF addn IS
SIGNAL carries : BIT_VECTOR(0 TO n);
BEGIN
addgen : FOR i IN addend'RANGE
GENERATE
lsadder : IF i = 0 GENERATE
sum(i) <= addend(i) XOR augend(i) XOR carry_in;
carries(i) <= (addend(i) AND augend(i)) OR
(addend(i) AND carry_in) OR
(carry_in AND augend(i));
END GENERATE;
otheradder : IF i /= 0 GENERATE
sum(i) <= addend(i) XOR augend(i) XOR carries(i-1);
carries(i) <= (addend(i) AND augend(i)) OR
(addend(i) AND carries(i-1)) OR
(carries(i-1) AND augend(i));
END GENERATE;
END GENERATE;
carry_out <= carries(n);
END generated;
FA

FA
FA
carry_in
addend(0)
augend(0)
carries(0) .
addend(1) .
augend(1) .
carries(n-1) .
addend(n) .
augend(n) .
sum(0)
sum(1)
sum(n-1)
carry_out
Priority.vhd
LIBRARY ieee;
entity priority is
port(I : in bit_vector(7 downto 0);
--inputs to be prioritised
A : out bit_vector(2 downto 0);
--encoded output
GS : out bit); --group signal output
end priority;
architecture v1 of priority is
begin
process(I)
begin
GS <= '1';
--set default outputs
A <= "000";
if I(7) = '1' then
A <= "111";
elsif I(6) = '1' then
A <= "110";
A <= "101";
A <= "100";
A <= "011";
A <= "010";
A <= "001";
A <= "000";
else
GS <= '0';
end if;
end process;
end v1;
A

I
GS

Ram16x8.vhd
LIBRARY ieee;
ENTITY ram16x8 IS
PORT(address : IN STD_LOGIC_VECTOR
(3 DOWNTO 0);
csbar, oebar, webar : IN STD_LOGIC;
data : INOUT STD_LOGIC_VECTOR
(7 DOWNTO 0));
END ram16x8;

ARCHITECTURE version1 OF ram16x8 IS
BEGIN
PROCESS(address, csbar, oebar, webar, data)
TYPE ram_array IS ARRAY (0 TO 15)
OF BIT_VECTOR(7 DOWNTO 0);
VARIABLE index : INTEGER := 0;
VARIABLE ram_store : ram_array;
BEGIN
IF csbar = '0' THEN
--calculate address as an integer
index := 0;
FOR i IN address'RANGE LOOP
IF address(i) = '1' THEN
index := index + 2**i;
END IF;
END LOOP;
IF rising_edge(webar) THEN
--write to ram on rising edge of write pulse
ram_store(index) := To_bitvector(data);
ELSIF oebar = '0' THEN
data <= To_StdlogicVector(ram_store(index));
ELSE
data <= "ZZZZZZZZ";
END IF;
ELSE
data <= "ZZZZZZZZ";
END IF;
END PROCESS;
END version1;

address
data
csbar
oebar
webar
Address index locate the data using index
updata / return data in array
Ram.vhd
Library IEEE ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;

entity ram is
generic (data_width : natural := 8 ;
address_width : natural := 8);
port ( data_in : in UNSIGNED(data_width - 1 downto 0) ;
address : in UNSIGNED(address_width - 1 downto 0) ;
we : in std_logic ;
data_out : out UNSIGNED(data_width - 1 downto 0) );
end ram ;
architecture rtl of ram is
type mem_type is array (2**address_width downto 0) of
UNSIGNED(data_width - 1 downto 0) ;
signal mem : mem_type ;
begin
I0 : process (we,address,mem,data_in)
begin
if (we = '1') then
mem(conv_integer(address)) <= data_in ;
end if ;
data_out <= mem(conv_integer(address)) ;
end process ;
end RTL ;

data_width
2
*
*
a
d
d
r
e
s
s
_
w
i
d
t
h

Tff.vhd
bigcntr.vhd
library ieee;

entity tff is
port(clk, t, clear : in std_logic; q : buffer std_logic);
end tff;

architecture v1 of tff is
begin
process(clear, clk)
begin
if clear = '1' then
q <= '0';
elsif rising_edge(clk) then
if t = '1' then
q <= not q;
else
null;
end if;
end if;
end process;
end v1;
library ieee;
entity bigcntr is
generic(size : positive := 32);
port(clk, clear : in std_logic;
q : buffer std_logic_vector((size-1) downto 0));
end bigcntr;
architecture v1 of bigcntr is
component tff is
port(clk, t, clear : in std_logic; q : buffer std_logic);
end component;
signal tin : std_logic_vector((size-1) downto 0);
Begin
genttf : for i in (size-1) downto 0 generate
ttype : tff port map (clk, tin(i), clear, q(i));
end generate;

genand : for i in 0 to (size-1) generate
t0 : if i = 0 generate
tin(i) <= '1';
end generate;
t1_size : if i > 0 generate
tin(i) <= q(i-1) and tin(i-1);
end generate;
end generate;
end v1;
TFF
t
clk
clear
q
TFF TFF TFF TFF

Prnsgen.vhd
library ieee;

ENTITY prbsgen IS
GENERIC(length : Positive := 8;
tap1 : Positive := 8;
tap2 : Positive := 4);
PORT(clk, reset : IN Bit;
prbs : OUT Bit);
END prbsgen;
ARCHITECTURE v2 OF prbsgen IS
--create a shift register
SIGNAL prreg : Bit_Vector(length DOWNTO 0);
BEGIN
--conditional signal assignment shifts
--register and feeds in xor value
prreg <= (0 => '1', OTHERS => '0') WHEN reset = '1' ELSE
(prreg((length - 1) DOWNTO 0) & (prreg(tap1) XOR prreg(tap2)))
WHEN clk'EVENT AND clk = '1 ELSE
prreg;
prbs <= prreg(length);
END v2;

D Q

CLK
D Q

CLK
D Q

CLK
XOR
Cntr4bit.vhd
library ieee;
ENTITY cntr4bit IS
PORT(reset,clock : IN BIT; count : OUT BIT_VECTOR(0 TO 3));
END cntr4bit;
ARCHITECTURE dataflow OF cntr4bit IS
--interface function to generate output bit_vector from
--internal count value.
FUNCTION nat_to_bv(input : NATURAL; highbit : POSITIVE)
RETURN BIT_VECTOR IS
VARIABLE temp : NATURAL := 0;
VARIABLE output : BIT_VECTOR(0 TO highbit);
BEGIN
temp := input;
--check that input fits into (highbit+1) bits
ASSERT (temp <= (2**(highbit + 1) - 1))
REPORT "input no. is out of range" SEVERITY ERROR;
--generate bit values
FOR i IN highbit DOWNTO 0 LOOP
IF temp >= (2**i)
THEN output(i) := '1';
temp := temp - (2**i);
ELSE output(i) := '0';
END IF;
END LOOP;
RETURN output;
END nat_to_bv;
--signal to hold current count value
SIGNAL intcount : NATURAL :=0;

BEGIN
--conditional natural signal assignment models counter
intcount <= 0 WHEN (reset = '1') ELSE
((intcount + 1) MOD 16) WHEN (clock'EVENT AND clock = '1')
ELSE intcount;
--interface function converts natural count to bit_vector count
count <= nat_to_bv(intcount,3);
END;
Addrec.vhd
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be '0' to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
library ieee;
entity addrdec is
port( asbar : in std_logic;
address : in std_logic_vector(19 downto 0);
csbar : out std_logic_vector(3 downto 0));
end entity addrdec;
architecture v1 of addrdec is
begin
csbar(0) <= '0' when
((asbar = '0') and
((address >= X"00000") and (address <= X"01FFF")))
else '1';
((asbar = '0') and
((address >= X"40000") and (address <= X"43FFF")))
else '1';
((asbar = '0') and
((address >= X"08000") and (address <= X"0AFFF")))
else '1';
((asbar = '0') and
((address >= X"E0000") and (address <= X"E01FF")))
else '1';
end architecture v1;
68008 CPU

Addrec.vhd (1)
00000

01FFF

08000

0AFFF

40000

43FFF

E0000

E01FF
cs(0)
cs(2)
cs(1)
cs(3)
Mai.vhd
ENTITY maj IS
PORT(a,b,c : IN BIT; m : OUT BIT);
END maj;
Majority Voter
--Structural style architecture
ARCHITECTURE structure OF maj IS

--declare components used in architecture
COMPONENT and2 PORT(in1, in2 : IN BIT;
out1 : OUT BIT);
END COMPONENT;
COMPONENT or3 PORT(in1, in2, in3 : IN BIT;
out1 : OUT BIT);
END COMPONENT;
--declare local signals
SIGNAL w1, w2, w3 : BIT;

BEGIN
--component instantiation statements.
--ports of component are mapped to signals
--within architecture by position.
gate1 : and2 PORT MAP (a, b, w1);
gate2 : and2 PORT MAP (b, c, w2);
gate3 : and2 PORT MAP (a, c, w3);
gate4 : or3 PORT MAP (w1, w2, w3, m);
END structure;
a
b

c
w1

w3

w2
m
Mai.vhd (1)
--Dataflow style architecture
ARCHITECTURE concurrent OF maj IS
BEGIN
--selected signal assignment statement (concurrent)
WITH a&b&c SELECT
m <= '1' WHEN "110"|"101"|"011"|"111",'0' WHEN
OTHERS;
END concurrent;
--Behavioural style architecture using a look-up table
ARCHITECTURE using_table OF maj IS
BEGIN
PROCESS(a,b,c)
CONSTANT lookuptable : BIT_VECTOR(0 TO 7) := "00010111";
VARIABLE index : NATURAL;
BEGIN
index := 0; --index must be cleared each time process executes
IF a = '1' THEN index := index + 1; END IF;
IF b = '1' THEN index := index + 2; END IF;
IF c = '1' THEN index := index + 4; END IF;
m <= lookuptable(index);
END PROCESS;
END using_table;
List all
possible input
and outputs
True table
index
(cba)
2
0 000 0
1 001 0
2 010 0
3 011 1
4 100 0
5 101 1
6 110 1
7 111 1
Cpudemo.vhd
-- Structural description of a Microprocessor System
LIBRARY ieee;
ENTITY cpudemo IS
END cpudemo;
ARCHITECTURE version1 OF cpudemo IS
COMPONENT rom256x8
PORT(address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
csbar, oebar : IN STD_LOGIC;
data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT ram16x8
csbar, oebar, webar : IN STD_LOGIC;
data : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT cpu
GENERIC(cycle_time : TIME := 200 ns); --must be divisible by 8
PORT(reset : IN std_logic;
memrd, memwr : OUT std_logic;
address : OUT std_logic_vector(11 DOWNTO 0);
data : INOUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
SIGNAL reset, memrd, memwr, romenable, ramenable : std_logic;
SIGNAL address : std_logic_vector(11 DOWNTO 0);
SIGNAL data : std_logic_vector(7 DOWNTO 0);
--selecting the rom architecture (program) for simulation
FOR rom : rom256x8 USE ENTITY work.rom256x8(version2);
BEGIN
processor : cpu PORT MAP(reset, memrd, memwr, address, data);
rom : rom256x8 PORT MAP(address(7 DOWNTO 0), romenable, memrd, data);
ram : ram16x8 PORT MAP(address(3 DOWNTO 0), ramenable, memrd, memwr, data);
--memory address decoding ,rom is at bottom of address space
--ram is situated at address $100
romenable <='0' WHEN (address(11 DOWNTO 8) ="0000") ELSE '1';
ramenable <='0' WHEN (address(11 DOWNTO 4) ="00010000") ELSE '1';
END version1;
CPU
RAM
ROM
Chip
select
Reginf.vhd
Library IEEE ;
ENTITY reginf IS
PORT
( d, clk, clr, pre, load, data : IN BIT;
q1, q2, q3, q4, q5, q6, q7 : OUT BIT );
END reginf;
ARCHITECTURE maxpld OF reginf IS
BEGIN
-- Register with active-high Clock
PROCESS
BEGIN
q1 <= d;
END PROCESS;
-- Register with active-low Clock
PROCESS
BEGIN
q2 <= d;
END PROCESS;
-- Register with active-high Clock
-- & asynchronous Clear
PROCESS (clk, clr)
BEGIN
IF clr = '1' THEN
q3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
q3 <= d;
END IF;
END PROCESS;
-- Register with active-low Clock & asynchronous Clear
PROCESS (clk, clr)
BEGIN
IF clr = '0' THEN
q4 <= '0';
q4 <= d;
END IF;
END PROCESS;
-- Register with active-high Clock & asynchronous Preset
PROCESS (clk, pre)
BEGIN
IF pre = '1' THEN
q5 <= '1';
q5 <= d;
END IF;
END PROCESS;
-- Register with active-high Clock & asynchronous load
PROCESS (clk, load, data)
BEGIN
IF load = '1' THEN
q6 <= data;
q6 <= d;
END IF;
END PROCESS;
-- Register with active-high Clock & asynchronous Clear & Preset
PROCESS (clk, clr, pre)
BEGIN
IF clr = '1' THEN
q7 <= '0';
ELSIF pre = '1' THEN
q7 <= '1';
q7 <= d;
END IF;
END PROCESS;
END maxpld;
All kinds
of
registers
Unicntr.vhd
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;

ENTITY unicntr IS
GENERIC(n : Positive := 8); --size of counter/shifter
PORT(
clock, serinl, serinr : IN Std_logic;
--serial inputs
mode : IN Std_logic_vector(2 DOWNTO 0);
--mode control
datain : IN Std_logic_vector((n-1) DOWNTO 0);
--parallel inputs
dataout : OUT Std_logic_vector((n-1) DOWNTO 0);
--parallel outputs
termcnt : OUT Std_logic); --terminal count output
END unicntr;
ARCHITECTURE v1 OF unicntr IS
SIGNAL int_reg : Std_logic_vector((n-1) DOWNTO 0);

BEGIN
main_proc : PROCESS
BEGIN
WAIT UNTIL rising_edge(clock);
CASE mode IS
--reset
WHEN "000" => int_reg <= (OTHERS => '0');
--parallel load
WHEN "001" => int_reg <= datain;
--count up
WHEN "010" => int_reg <= int_reg + 1;
--count down
WHEN "011" => int_reg <= int_reg - 1;
--shift left
WHEN "100" => int_reg <= int_reg((n-2) DOWNTO 0) & serinl;
--shift right
WHEN "101" => int_reg <= serinr & int_reg((n-1) DOWNTO 1);
--do nothing
WHEN OTHERS => NULL;
END CASE;
END PROCESS;

det_zero : PROCESS(int_reg) --detects when count is 0
BEGIN
termcnt <= '1';
FOR i IN int_reg'Range LOOP
IF int_reg(i) = '1' THEN
termcnt <= '0';
EXIT;
END IF;
END LOOP;
END PROCESS;

--connect internal register to dataout port
dataout <= int_reg;
END v1;
000 Clear to 0
001 Load data
010 +1 count
011 -1 count
100 Shift left
101 Shift right
110, 111 No operation
FIFOMXN.vhd
library IEEE;
entity FIFOMXN is
generic(m, n : Positive := 8); --m is fifo depth, n is fifo width
port(RESET, WRREQ, RDREQ, CLOCK : in Std_logic;
DATAIN : in Std_logic_vector((n-1) downto 0);
DATAOUT : out Std_logic_vector((n-1) downto 0);
FULL, EMPTY : inout Std_logic);
end FIFOMXN;
architecture V2 of FIFOMXN is
type Fifo_array is array(0 to (m-1)) of Bit_vector((n-1) downto 0);
signal Fifo_memory : Fifo_array;
signal Wraddr, Rdaddr, Offset : Natural range 0 to (m-1);
signal Rdpulse, Wrpulse, Q1, Q2, Q3, Q4 : Std_logic;
signal Databuffer : Bit_vector((n-1) downto 0);
begin
--pulse synchronisers for WRREQ and RDREQ
--modified for Synplify to a process
sync_ffs : process
begin
wait until rising_edge(CLOCK);
Q1 <= WRREQ;
Q2 <= Q1;
Q3 <= RDREQ;
Q4 <= Q3;
end process;

--concurrent logic to generate pulses
Wrpulse <= Q2 and not(Q1);
Rdpulse <= Q4 and not(Q3);
Fifo_read : process
begin
if RESET = '1' then
Rdaddr <= 0;
Databuffer <= (others => '0');
elsif (Rdpulse = '1' and EMPTY = '0') then
Databuffer <= Fifo_memory(Rdaddr);
Rdaddr <= (Rdaddr + 1) mod m;
end if;
end process;

Fifo_write : process
begin
if RESET = '1' then
Wraddr <= 0;
elsif (Wrpulse = '1' and FULL = '0') then
Fifo_memory(Wraddr) <= To_Bitvector(DATAIN);
Wraddr <= (Wraddr + 1) mod m;
end if;
end process;

Offset <= (Wraddr - Rdaddr) when (Wraddr > Rdaddr)
else (m - (Rdaddr - Wraddr)) when (Rdaddr > Wraddr)
else 0;

EMPTY <= '1' when (Offset = 0) else '0';
FULL <= '1' when (Offset = (m-1)) else '0';

DATAOUT <= To_Stdlogicvector(Databuffer)
when RDREQ = '0'
else (others => 'Z');
end V2;
FIFOMXN.vhd (1)
Write Point
Read Point
D Q

CLK
D Q

CLK
Wrpulse
Rdpulse
Pointer will loop back
Rdaddr <= (Rdaddr + 1) mod m;
Wraddr <= (Wraddr + 1) mod m;
priority_encoder.vhd
Library IEEE ;

entity priority_encoder is
generic (data_width : natural := 25 ;
address_width : natural := 5 ) ;
port (
data : in UNSIGNED(data_width - 1 downto 0) ;
address : out UNSIGNED(address_width - 1 downto 0) ;
none : out STD_LOGIC
);
end priority_encoder ;

architecture rtl of priority_encoder is
attribute SYNTHESIS_RETURN : STRING ;

FUNCTION to_stdlogic (arg1:BOOLEAN)
RETURN STD_LOGIC IS

END ;

FUNCTION to_UNSIGNED(ARG: INTEGER; SIZE: INTEGER)
RETURN UNSIGNED IS

END;
constant zero :
UNSIGNED(data_width downto 1) := (others => '0') ;
begin
PRIO : process(data)
variable temp_address :
UNSIGNED(address_width - 1 downto 0) ;
begin
temp_address := (others => '0') ;
for i in data_width - 1 downto 0 loop
if (data(i) = '1') then
temp_address := to_unsigned(i,address_width) ;
exit ;
end if ;
end loop ;
address <=temp_address ;
none <=to_stdlogic(data =zero) ;
end process ;
end RTL ;

Find 1st
'1' from
up to
down
Mag4comp.vhd
LIBRARY ieee;

ENTITY mag4comp IS
GENERIC(eqdel,gtdel,ltdel : TIME := 10 ns);
-- output delay parameters
PORT(a,b : IN BIT_VECTOR(3 DOWNTO 0);
-- input words, DOWNTO ordering needed
- -for comparison operators
aeqbin,agtbin,altbin : IN BIT; --expansion inputs
aeqbout,agtbout,altbout : OUT BIT); --outputs
END mag4comp;

ARCHITECTURE dataflow OF mag4comp IS
BEGIN
aeqbout <= '1' AFTER eqdel WHEN ((a = b) AND (aeqbin = '1'))
ELSE '0' AFTER eqdel;
agtbout <= '1' AFTER gtdel WHEN ((a > b) OR ((a = b) AND (agtbin = '1')))
ELSE '0' AFTER gtdel;
altbout <= '1' AFTER ltdel WHEN ((a < b) OR ((a = b) AND (altbin = '1')))
ELSE '0' AFTER ltdel;
END dataflow;
ARCHITECTURE behaviour OF mag4comp ISBEGIN
PROCESS(a,b,aeqbin,agtbin,altbin)
BEGIN
IF (a > b) THEN
agtbout <= '1' AFTER gtdel;
aeqbout <= '0' AFTER eqdel;
altbout <= '0' AFTER ltdel;
ELSIF (a < b) THEN
ELSE --a=b,expansion inputs have priority ordering
IF (aeqbin = '1') THEN
ELSIF (agtbin = '1') THEN
ELSIF (altbin = '1') THEN
gtbout <= '0' AFTER gtdel;
ELSE
END IF;
END IF;
END PROCESS;
END behaviour;
Mag4comp.vhd (1)
a=b
a>b
a<b
a
b
aeqbin
agtbin
altbin
aeqbout
agtbout
altbout
1 0 0 0 0 0 1 1 1 1
1 0 0 1 0 0 1 1 1 1
smart_waveform.vhd
Library IEEE ;

package waveform_pkg is
constant rom_width : integer := 6 ;
subtype rom_word is std_logic_vector ( 1 to rom_width) ;
subtype rom_range is integer range 0 to 12 ;
type rom_table is array ( 0 to 12) of rom_word ;
constant rom_data : rom_table := rom_table'(
"111010" ,
"101000" ,
"011000" ,
"001000" ,
"011010" ,
"010011" ,
"101110" ,
"110100" ,
"001010" ,
"001000" ,
"010110" ,
"010101" ,
"001111" ) ;
subtype data_word is integer range 0 to 100 ;
subtype data_range is integer range 0 to 12 ;
type data_table is array (0 to 12) of data_word ;
constant data : data_table := data_table'(1,40,9,2,2,4,1,15,5,1,1,3,1) ;
end waveform_pkg ;
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_arith.ALL ;
USE work.waveform_pkg.all ;
entity smart_waveform is
port ( clock : in std_logic ;
reset : in boolean ;
waves : out rom_word ) ;
end ;
architecture rtl of smart_waveform is
signal step,next_step : rom_range ;
signal delay : data_word ;
begin
next_step <= rom_range'high
when step = rom_range'high else step + 1 ;
time_step : process
begin
wait until clock'event and clock = '1'
and clock'last_value = '0';
if (reset) then
step <= 0 ;
elsif (delay = 1) then
step <= next_step ; -- update wave form index
else
null ; -- waiting for delay ends
end if ;
end process ;
delay_step : proces
begin
wait until clock'event and clock = '1' ;
if (reset) then
delay <= data(0) ;
elsif (delay = 1) then
delay <= data(next_step) ; -- get next delay value
else
delay <= delay - 1 ;
end if ;
end process ;
waves <= rom_data(step) ; -- Find waveform from table
end ; -- by index step
smart_waveform.vhd (1)
step
Waveform 1
Waveform 2
Waveform 3
Waveform N
rom_data
waves
Delay_step
process
Delay value 1
Delay value 2
Delay value N

data_table
Jkff.vhd
library ieee;
ENTITY jkff IS
PORT(clock, j, k : IN BIT; q, qbar : BUFFER BIT);
END jkff;
ARCHITECTURE using_process OF jkff IS
BEGIN
--sequential process to model JK flip-flop
PROCESS
--declare a local variable to hold ff state
VARIABLE state : BIT := '0';
BEGIN
--synchronise process to rising edge of clock
WAIT UNTIL (clock'EVENT AND clock = '1');
IF (j = '1' AND k = '1') THEN --toggle
state := NOT state;
ELSIF (j = '0' AND k = '1') THEN --reset
state := '0';
ELSIF (j = '1' AND k = '0') THEN --set
state := '1';
ELSE --no change
state := state;
END IF;
--assign values to output signals
q <= state AFTER 5 ns;
qbar <= NOT state AFTER 5 ns;
END PROCESS;
END using_process;
J K Q
n+1

0 0 Q
n
0 1 0
1 0 1
1 1 Q
n
Rom256x8.vhd
-- Behavioural model of a 256-word, 8-bit Read Only Memory
LIBRARY ieee;
USE work.cpu8pac.ALL;
ENTITY rom256x8 IS
END rom256x8;

--version 1 loads acca and accb from locations 254 and 256
--and exclusive or's the values and jumps back to repeat
ARCHITECTURE version1 OF rom256x8 IS
TYPE rom_array IS ARRAY (0 TO 255) OF BIT_VECTOR(7 DOWNTO 0);
CONSTANT rom_values : rom_array :=
(0 => clra & X"0",
1 => lda & X"0", --lda $FE
2 => X"fe",
3 => ldb & X"0", --ldb $FF
4 => X"ff",
5 => lxor & X"0", --lxor
6 => jmp & X"0", --jmp $001
7 => X"01",
254 => X"aa",
255 => X"55",
OTHERS => X"00");
BEGIN
PROCESS(address, csbar, oebar)
BEGIN
IF (csbar = '1' OR oebar = '1')
THEN data <= "ZZZZZZZZ";
ELSE
index := 0;
END IF;
END LOOP;
--assign to output data lines
data <= To_StdlogicVector(rom_values(index));

END IF;
END PROCESS;
END version1;
Std_logic_vector integer
Address Index

rom256x8
Rom256x8.vhd(1)
--version2 increments a location in the ram
-- download from: www.fpga.com.cn & www.pld.com.cn
ARCHITECTURE version2 OF rom256x8 IS
TYPE rom_array IS ARRAY (0 TO 255) OF BIT_VECTOR(7 DOWNTO 0);
CONSTANT rom_values : rom_array :=
(0 => clra & X"0",
1 => sta & X"1", --sta $100
2 => X"00",
3 => lda & X"1", --lda $100
4 => X"00",
5 => inc & X"0", --inc a
6 => jmp & X"0", --jmp $001
7 => X"01",
OTHERS => X"00");
BEGIN
PROCESS(address, csbar, oebar)
BEGIN
IF (csbar = '1' OR oebar = '1')
THEN data <= "ZZZZZZZZ";
ELSE

index := 0;
END IF;
END LOOP;

--assign to output data lines
data <= To_StdlogicVector(rom_values(index));

END IF;
END PROCESS;
END version2;
-- Behavioural model of a 256-word, 8-bit Read Only Memory
LIBRARY ieee;
USE work.cpu8pac.ALL;
ENTITY rom256x8 IS
END rom256x8;

Testbench.vhd
entity testbench is
end;
library IEEE;
use IEEE.std_logic_1164.all;
architecture adder8 of testbench is
component adderN
generic(N : integer);
port (a : in std_logic_vector(N downto 1);
b : in std_logic_vector(N downto 1);
cin : in std_logic;
sum : out std_logic_vector(N downto 1);
cout : out std_logic);
end component;
constant N : integer := 8;
signal a : std_logic_vector(N downto 1);
signal b : std_logic_vector(N downto 1);
signal cin : std_logic;
signal sum : std_logic_vector(N downto 1);
signal cout : std_logic;\
type test_record_t is record
a : std_logic_vector(N downto 1);
b : std_logic_vector(N downto 1);
cin : std_logic;
sum : std_logic_vector(N downto 1);
cout : std_logic;
end record;
type test_array_t is array(positive range <>) of
test_record_t;
constant test_patterns : test_array_t := (
(a => "00000000", b => "00000001", cin => '0', sum => "00000001", cout => '0'),
(a => "00000001", b => "00000001", cin => '0', sum => "00000010", cout => '0'),
(a => "00000001", b => "00000001", cin => '1', sum => "00000011", cout => '0'),
(a => "00001010", b => "00000011", cin => '0', sum => "00001101", cout => '0'),
(a => "00000011", b => "00001010", cin => '0', sum => "00001101", cout => '0'),
(a => "00000101", b => "00000001", cin => '1', sum => "00001000", cout => '0'),
(a => "00000011", b => "11111100", cin => '0', sum => "11111111", cout => '0'),
(a => "00000011", b => "11111100", cin => '1', sum => "00000000", cout => '1'),
(a => "01010101", b => "01010101", cin => '0', sum => "10101010", cout => '0'),
(a => "00000000", b => "00000000", cin => '0', sum => "00000000", cout => '0') );
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U', 'X' => 'X', '0' => '0',
'1' => '1', 'Z' => 'Z', 'W' => 'W',
'L' => 'L', 'H' => 'H', '-' => '- );
function to_string(inp : std_logic_vector) return string is
alias vec : std_logic_vector(1 to inp'length) is inp;
variable result : string(vec'range);
begin
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
Begin
-- instantiate the component
uut: adderN generic map(N)
port map(a => a, b => b, cin => cin,
sum => sum, cout => cout);
test: process
variable vector : test_record_t;
variable found_error : boolean := false;
begin
for i in test_patterns'range loop
vector := test_patterns(i);
a <= vector.a;
b <= vector.b;
cin <= vector.cin;
wait for 100 ns;
if (sum /= vector.sum) then
assert false
report "Sum is " & to_string(sum) & ". Expected "
& to_string(vector.sum);
found_error := true;
end if;
if (cout /= vector.cout) then
assert false
report "Cout is " & to_char(cout) & ". & "Expected value is "
& to_char(vector.cout);
found_error := true;
end if;
end loop;
assert not found_error
report "There were ERRORS in the test.
severity note;
assert found_error
report "Test completed with no errors.
severity note;
wait;
end process;
end;
configuration test_adder_behavioral of testbench is
for adder8
for all: adderN
use entity work.adderN(behavioral);
end for;
end for;
end test_adder_behavioral;

configuration test_adder_structural of testbench is
for adder8
for all: adderN
use entity work.adderN(structural);
for structural
for gen
for all : adder
use entity work.adder(structural);
end for;
end for;
end for;
end for;
end for;
end test_adder_structural;
Library IEEE ;

ENTITY counters IS
PORT
(
d : IN INTEGER RANGE 0 TO 255;
clk : IN BIT;
clear : IN BIT;
ld : IN BIT;
enable : IN BIT;
up_down : IN BIT;
qa : OUT INTEGER RANGE 0 TO 255;
qb : OUT INTEGER RANGE 0 TO 255;
qc : OUT INTEGER RANGE 0 TO 255;
qd : OUT INTEGER RANGE 0 TO 255;
qe : OUT INTEGER RANGE 0 TO 255;
qf : OUT INTEGER RANGE 0 TO 255;
qg : OUT INTEGER RANGE 0 TO 255;
qh : OUT INTEGER RANGE 0 TO 255;
qi : OUT INTEGER RANGE 0 TO 255;
qj : OUT INTEGER RANGE 0 TO 255;
qk : OUT INTEGER RANGE 0 TO 255;
ql : OUT INTEGER RANGE 0 TO 255;
qm : OUT INTEGER RANGE 0 TO 255;
qn : OUT INTEGER RANGE 0 TO 255
);
END counters;

ARCHITECTURE a OF counters IS
BEGIN

END a;

A
l
l

K
i
n
d
s

o
f

C
o
u
n
t
e
r
s

-- An enable counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF enable = '1' THEN
cnt := cnt + 1;
END IF;
END IF;

qa <= cnt;

END PROCESS;
-- A synchronous load counter
PROCESS (clk)
BEGIN
IF ld = '0' THEN
cnt := d;
ELSE
cnt := cnt + 1;
END IF;
END IF;

qb <= cnt;
END PROCESS;
-- A synchronous clear counter
PROCESS (clk)
BEGIN
IF clear = '0' THEN
cnt := 0;
ELSE
cnt := cnt + 1;
END IF;
END IF;

qc <= cnt;

END PROCESS;
-- An up/down counter
PROCESS (clk)
VARIABLE direction : INTEGER;
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := -1;
END IF;

cnt := cnt + direction;
END IF;

qd <= cnt;

END PROCESS;
-- A synchronous load enable counter
PROCESS (clk)
BEGIN
IF ld = '0' THEN
cnt := d;
ELSE
cnt := cnt + 1;
END IF;
END IF;
END IF;

qe <= cnt;

END PROCESS;
-- An enable up/down counter
PROCESS (clk)
BEGIN
direction := 1;
ELSE
direction := -1;
END IF;

END IF;
END IF;

qf <= cnt;

END PROCESS;
-- A synchronous clear enable counter
PROCESS (clk)
BEGIN
IF clear = '0' THEN
cnt := 0;
ELSE
cnt := cnt + 1;
END IF;
END IF;
END IF;

qg <= cnt;

END PROCESS;
-- A synchronous load clear counter
PROCESS (clk)
BEGIN
IF clear = '0' THEN
cnt := 0;
ELSE
IF ld = '0' THEN
cnt := d;
ELSE
cnt := cnt + 1;
END IF;
END IF;
END IF;

qh <= cnt;

END PROCESS;
-- A synchronous load up/down counter
PROCESS (clk)
BEGIN
direction := 1;
ELSE
direction := -1;
END IF;

IF ld = '0' THEN
cnt := d;
ELSE
END IF;
END IF;

qi <= cnt;

END PROCESS;
-- A synchronous load enable up/down
counter
PROCESS (clk)
BEGIN
direction := 1;
ELSE
direction := -1;
END IF;

IF ld = '0' THEN
cnt := d;
ELSE
END IF;
END IF;
END IF;

qj <= cnt;

END PROCESS;
-- A synchronous clear load enable counter
PROCESS (clk)
BEGIN
IF clear = '0' THEN
cnt := 0;
ELSE
IF ld = '0' THEN
cnt := d;
ELSE
cnt := cnt + 1;
END IF;
END IF;
END IF;
END IF;

qk <= cnt;

END PROCESS;
-- A synchronous clear up/down counter
PROCESS (clk)
BEGIN
direction := 1;
ELSE
direction := -1;
END IF;

IF clear = '0' THEN
cnt := 0;
ELSE
END IF;
END IF;

ql <= cnt;

END PROCESS;
-- A synchronous clear enable up/down counter
PROCESS (clk)
BEGIN
direction := 1;
ELSE
direction := -1;
END IF;

IF clear = '0' THEN
cnt := 0;
ELSE
END IF;
END IF;
END IF;

qm <= cnt;

END PROCESS;
-- A modulus 200 up counter
PROCESS (clk)
CONSTANT modulus : INTEGER := 200;
BEGIN
IF cnt = modulus THEN
cnt := 0;
ELSE
cnt := cnt + 1;
END IF;
END IF;

qn <= cnt;

END PROCESS;
Counters.vhd

ch8 9 5m

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