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Message Reference for

Encounter

RTL Compiler
Product Version 12.2
May 2013
20032012 Cadence Design Systems, Inc. All rights reserved.
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Message Reference for Encounter RTL Compiler
May 2013 3 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
1
Info Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Info Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
List of Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3
Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
List of Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Contents
Message Reference for Encounter RTL Compiler
May 2013 4 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
Message Reference for Encounter RTL Compiler
May 2013 5 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
1
Info Messages
Message Reference for Encounter RTL Compiler
Info Messages
May 2013 6 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
List of Info Messages
Message-ID Title Help
ATTR-101 Setting attribute.
ATTR-102 Resetting attribute.
CDFG-5 Error encountered during high level
optimization.
The optimization can be turned off by setting
the hdl-architecture's (module's) attribute to
false before elaboration.
CDFG-6 Error encountered during high level
optimization.
The optimization can be turned off by setting
the tcl variable to 0 before elaboration.
CDFG-22 Unresolved instance '%s'.
CDFG-23 Wrote CDFG.
CDFG-250 Processing multi-dimensional arrays.
CDFG-286 Reference to global signal in subprogram.
CDFG-295 Applying architecture pragma. Error during elaboration.
CDFG-300 Checking HDL design.
CDFG-301 No HDL designs to process. The 'read_hdl' command creates an HDL
design for every Verilog module and every
VHDL architecture. HDL designs are
automatically deleted when you use the
'elaborate' or the 'read_netlist' command. Use
'find / -hdl_arch *' to list all available HDL
designs.
CDFG-302 HDL design is up to date.
CDFG-303 Processing HDL design.
CDFG-305 Deleting HDL design.
CDFG-308 Processing HDL design from subprogram.
CDFG-309 Processing HDL design from operator.
CDFG-325 Problem in processing of input RTL. Error in processing of HDL during elaboration.
Possibly due to combinational loops, or
unsynthesizable constructs.
CDFG-327 Processing ChipWare component.
CDFG-328 Processing module from operator.
CDFG-340 Building parameterized design.
CDFG-345 Ignored range specification for parameter. In Verilog-1995 a range given in a parameter
declaration is ignored. To make use of the
parameter range, read the design with
'read_hdl -v2001' or 'read_hdl -sv'.
CDFG-359 Building ChipWare component.
Message Reference for Encounter RTL Compiler
Info Messages
May 2013 7 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
CDFG-361 Signal is not referenced within the process or
block, but is in the sensitivity list.
Asynchronous logic, such as a latch or
combinational logic, is inferred for this process
or block. Signals that are not referenced can be
removed from the sensitivity list. If the intent is
to infer a flip-flop, ensure that the process or
block is sensitive to the signal edge by adding
'posedge' or 'negedge' for Verilog designs or
'event' for VHDL designs.
CDFG-362 Assuming that the full range of indexed or sliced
sensitivity signal is in the sensitivity list.
CDFG-363 Ignored invalid sensitivity signal in the sensitivity
list.
CDFG-365 Clock signal is not used as a clock in this
process or block.
CDFG-372 Bitwidth mismatch in assignment.
CDFG-373 Sign mismatch in assignment.
CDFG-425 Instantiated design.
CDFG-426 Searching for library cell.
CDFG-427 Linking module.
CDFG-458 Inferred leading 0/1 detector from a 'for loop'
statement.
For example, a 'for loop' statement of the form:
reg [width-1:0] array;
for (i = 0; i < width; i = i + 1)
if (array[i])
count = i;
is recognized as a leading-1 detector. Other
coding styles, including loops with disable
statements, can be recognized. See 'HDL
Modeling in Encounter RTL Compiler' for more
information.
CDFG-459 Detected an RTL macro for the 'for loop'
statement. Replacing it with an equivalent
internal representation.
RTL macro replacement can result in improved
QOR.
CDFG-470 Constant conditional expression.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Info Messages
May 2013 8 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
CDFG-478 Converting if statement to equivalent case
statement.
An if statement is internally converted to an
equivalent case statement if:
1. Each condition compares the same
expression against a constant value
2. Conditions may be OR'd together
3. There are at least two branches in the if
statement containing the above types of
conditions
This transformation converts an if statement,
which is by default considered to have priority
logic, to a case statement, which has simpler
parallel logic.
CDFG-479 Constant relational expression. A relational expression can evaluate to a
constant when a variable is compared to a
value which is outside the bounds of the
variable.
CDFG-500 Unused module input port. The value of the input port is not used within the
design.
CDFG-501 Unused module inout port. The value of the inout port is not used within the
design.
CDFG-505 Assignment to supply0/supply1.
CDFG-509 Preserving unused register. A flip-flop or latch that was inferred for an
unused signal or variable is being preserved.
Better area results are possible if the
'hdl_preserve_unused_registers' attribute is set
to 'false'.
CDFG-511 An 'X' or 'Z' value propagated to a conditional
statement can cause a simulation mismatch
between the original and the synthesized
designs.
Verify that 'X' and 'Z' assignments in the HDL
are as intended. If the HDL source line given for
this assignment is not accurate, search
backwards in the file for an explicit 'X' or 'Z'
assignment that may have been propagated to
the given location.
CDFG-512 HDL design already elaborated.
CDFG-555 Linking parameterized module by name.
CDFG-560 Implementation selected for component
instance.
CDFG-565 Linking to ChipWare library component instead
of user module.
CDFG-738 Common subexpression eliminated.
CDFG-739 Common subexpression kept.
CDFG-740 Constant propagating graph.
CDFG-741 Tree height reduction on graph.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Info Messages
May 2013 9 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
CDFG-742 Common subexpression elimination.
CDFG-743 Balancing Boolean functions.
CDFG-744 Constant indexed array optimizing.
CDFG-747 Balancing arithmetic functions.
CDFG-749 Arithmetic nodes found outside datapath
partitions after initial partitioning. This may be
due to incomplete graph cleanup. Creating
partitions for these nodes.
CDFG-750 Created sum-of-products hierarchy.
CDFG-752 Enabling partial SOP-logic extraction.
CDFG-753 Transformed priority-encoded case to casex.
CDFG-754 Transformed if-else-if to priority-encoded case.
CDFG-755 Combined sum-of-products logic.
CDFG-757 Performing xz propagation on HDL design. Use 'set_attribute hdl_xz_propagation false /' to
disable xz propagation (which has no effect on
QOR).
CDFG-758 Detected an RTL macro. Replacing it with an
equivalent internal representation.
RTL macro replacement can result in improved
QOR.
CDFG-759 Detected an RTL macro for the conditional logic.
Replacing it with an equivalent internal
representation.
RTL macro replacement can result in improved
QOR.
CDFG-768 Simplified the variable part select operation.
CDFG-771 Replaced logic with a constant value.
CDFG-772 Removed unused code identified during
constant propagation.
CDFG-800 Statistics for case statements.
CDFG-815 Redundant conditional branches removed. There were some redundant branches as part
of a conditional if-else-if or case statement
which are removed.
CDFG-820 DesignWare instantiations are mapped to
feature compatible ChipWare components,
ChipWare components should be independently
verified to meet design requirements.
Support for third-party components like
DesignWare is provided for compatibility
purposes. All supported third-party
components are mapped to ChipWare
components proprietary to Cadence. While the
features and functions are compatible they
cannot be guaranteed to be exactly
implementation equivalent. It is your
responsibility to verify if the specific Cadence
implementation matches your requirements.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Info Messages
May 2013 10 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
CDFG2G-110 Finished processing module. The processing of the referenced module is
complete.
CDFG2G-210 Sum-of-products logic.
CDFG2G-616 Latch inferred. Use 'set_attribute hdl_error_on_latch true' to
issue an error when a latch is inferred. Use
'set_attribute hdl_latch_keep_feedback true' to
infer combinational logic rather than a latch
when a variable is explicitly assigned to itself.
CDFG2G-624 Detected a RTL Macro Function represented as
constant conditional logic.
CG-103 Created discrete clock-gating module. Two discrete clock-gating modules are created:
one for the positive-edge triggered registers
and one for the negative-edge triggered
registers. The names of the clock-gating
modules are based on the name of the design.
CG-210 Failed to insert observability logic. Use 'set_attr lp_clock_gating_add_obs_port
true /designs/<design>' to select clock-gating
logic with observability logic. Insert clock-gating
logic starting either from RTL or a netlist. Rerun
the 'clock_gating insert_obs' command to insert
observability logic.
CG-211 Skipped insertion of observability logic.
CG-214 No value was specified for the '-max_cg' option. The '-max_cg' option of the 'clock_gating
insert_obs' command specifies the maximum
number of clock-gating cells that can be
observed per observability flip-flop. You can
specify a number between 1 and 32.
CG-400 Removed a clock-gating instance.
CG-430 Retained a clock-gating instance.
CG-700 Could not insert dummy clock-gating logic. Set the lp_clock_gating_exclude attribute to
false on the flop to insert dummy clock-gating
logic.
CHECK_CWD-104 The permutable_group for the hdl_operator
defined is set.
CHECK_CWD-121 Same pin of the component used in
pin_association formula is associated with many
pins of the operator.
CHECK_CWD-126 The hdl_operator output pin is associated with
any output pin of the component.
CHECK_CWD-131 Bit_width attribute for the input pin is not set to
empty.
CHLNK-201 Performing change_link. The instance would be linked to a new libcell or
subdesign.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Info Messages
May 2013 11 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
CHLNK-203 The instance of a non-uniquified module is
being changed.
The same change will be copied to all the
modules when the module is uniquified.
CHNM-102 Changed names successfully.
CPF-392 Overwrote one of the operating voltages in
library set.
The specified library set had no library whose
operating voltage corresponded to the voltage
specified with the '-voltage' option of the
'create_nominal_condition' command. The
'read_cpf' command chose the operating
voltage closest to the voltage specified in the
CPF file and replaced it with that voltage.
CPF_ISO-109 No driver pin found in pin list given with
'-enable_driver'. Selecting one of drivers of
specified pins.
CPF_ISO-112 Isolation rule applied.
CPF_ISO-113 Port cloning turned off. Set variable
::lp_dont_clone_ports_for_insertion to 1 to turn
this behavior ON.
CPF_ISO-117 Multiple isolation rules specified on a pin in cpf
file.
CPF_ISO-201 Completed isolation cell insertion.
CPF_ISO-202 Completed level shifter insertion.
CPF_ISO-203 Isolation cell inserted.
CPF_ISO-204 Enabled level shifter inserted.
CPF_ISO-205 Level shifter inserted.
CPF_ISO-214 Global inversion not done.
CPF_ISO-215 Local inversion not done.
CPF_ISO-217 Global inversion done.
CPF_ISO-218 Local inversion done.
CPF_ISO-220 Skipping isolation / level shifter insertion.
CPF_ISO-221 Skipping isolation / level shifter insertion.
CPF_ISO-225 Optimization of isolation cell instances done.
CPF_ISO-226 Optimization of level shifter instances done.
CPF_ISO-227 Found an enabled level shifter as an appropriate
isolation cell for insertion.
CPF_ISO-228 Global inversion not done on isolation control
signal.
CPF_ISO-229 Local inversion not done on isolation control
signal.
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Info Messages
May 2013 12 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
CPF_ISO-230 Global inversion done on isolation control signal.
CPF_ISO-231 Local inversion done on isolation control signal.
CPF_ISO-232 Multi driven pin is found. This pin will be skipped from low power cell
insertion.
CPF_ISO-301 Completed assigning secondary domain to low
power instances.
CPF_ISO-302 Secondary domain is assigned to the low power
instance.
CPF_ISO-802 Rule removed from splitted port.
CPF_ISO-803 Buffer cannot be inserted for constant. LS/ISO insertion requires buffers to be inserted
at constants.
CPF_ISO-804 Hierarchical instance not a valid hierarchical
buffer instance.
CPF_ISO-805 No buffers found in library domain. LS/ISO might not be inserted at constants in
this library domain.
CPF_ISO-806 Multiple level shifter rules applied on pin.
CPF_ISO-807 Multiple isolation rules applied on pin.
CPF_ISO-808 Duplicate isolation rules specified in cpf-file. Rule with higher sequence value will win.
CPF_ISO-809 Multiple isolation rules specified for same
crossing in cpf-file.
This rule will win, since it is either more towards
load or it is a more specific rule.
CPF_ISO-812 Port cloning performed.
CPF_ISO-820 Isolation cell import completed.
CPF_ISO-821 Level shifter import completed.
CPF_ISO-822 Instance imported as isolation cell.
CPF_ISO-823 Instance imported as level shifter cell.
CPF_ISO-901 ICG swapped with ICG-Retention.
CPF_ISO-904 ICG swapped with ICG-Isolation.
CPF_ISO-910 Uniquifying the multiple instantiated subdesign
to prepare for pin/port cloning.
CPF_ISO-912 Uniquifying the multiple instantiated subdesign
to prepare for LS/ISO insertion.
For inserting LS/ISO in hierarchy given with
'-within_hierarchy', uniquifying the subdesign.
CPF_ISO-914 Timing exception is present on LS/ISO cell data
pin driver path.
LS/ISO cells may not be merged due to this
reason.
CPF_LS-809 Level shifter rule applied.
CPF_LS-810 Port cloning turned off. Set variable
::lp_dont_clone_ports_for_insertion to 1 to turn
this behavior ON.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Info Messages
May 2013 13 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
CPF_LS-814 Multiple level shifter rules specified on a pin in
cpf file.
CPF_LS-816 Duplicate level shifter rules specified in cpf-file. Rule with higher sequence value will win.
CPF_LS-817 Multiple level shifter rules specified for same
crossing in cpf-file.
This rule will win, since it is either more towards
load or it is a more specific rule.
CTP-2 A clock source lies in the fan-out of another
source.
CTP-9 A clock source is associated by more than one
clock.
CTP-14 A reconvergent path exists, and all fan-out flops
are common to all branches.
Clock skew estimates will be correct.
CTSTCH-2 Found unsupported keyword while parsing
CTSTCH file.
The unsupported keyword will be ignored.
CWD-11 Library already exists.
CWD-19 An implementation was inferred.
CWD-21 Skipping an invalid binding for a subprogram
call.
CWD-26 The output pin is unused.
CWD-29 The netlist for implementation was already built. The netlist for the implementation was
previously built from its synthesis model for the
specified set of parameter values.
CWD-36 Sorted the set of valid implementations for
synthetic operator.
CWD-37 Actual speed grade differs from the expected
speed grade.
CWD-46 Multiple components found with the same name.
DATABASE-100 Writing the database to a default file name. For a different name, specify a file name with
-to_file option.
DATABASE-101 Reading the netlist of the given name. Use this name to refer to the design.
DATABASE-102 Deleting the existing design of this name. If an existing design is not to be overwritten,
rename it prior to reading a database.
DATABASE-105 The database was successfully written. The database is now saved to the file.
DATABASE-111 While writing the database, attribute
'write_db_unresolved' to a subdesign was
encountered.
Only parts of the design and no data besides
the netlist will be written.
DATABASE-112 Ignoring file/row/column information. File/row/column is included in the database.
Since root attribute
'hdl_track_filename_row_col' is set to 'false' it
will not be restored.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Info Messages
May 2013 14 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
DATABASE-113 While writing the database, certain data cannot
be saved.
Avoid creating objects that cannot be saved
and restored.
DATABASE-120 Current directory restored.
DEX-401 Removing existing exploration power domain. The existing exploration power domain was
removed as another exploration power domain
with same name was requested to be created.
DEX-402 Removing existing exploration run. The existing exploration run was removed as
another exploration run with same name was
requested to be created.
DEX-403 No reports to show. Add reports before querying for report.
DFM-201 No systematic probability defined. There is no defined systematic probability in the
coefficient file.
DFT_GL-102 Skip the 'pll' clock related checks. In order to run 'pll' clock related checks specify
the 'pll' instances.
DFT-100 Added DFT object.
DFT-101 Moved/renamed DFT object.
DFT-102 Removed DFT object.
DFT-103 Changed attribute value. DFT changed some user-definable attribute.
DFT-118 Would remove DFT object.
DFT-130 Created DFT port. A port for DFT purposes was created.
DFT-140 Identified pad hookup pin. A primary input/output port was specified as the
driver/load of a DFT object; the tool determined
the port to be connected to a pad and reported
the hookup pin on the pad's core side.
DFT-151 Added scan chain.
DFT-163 Marking instance as dft_abstract_dont_scan as
an abstract segment is being defined on it.
This is done to prevent flops (if present) within
the instance from being scan synthesized.
DFT-164 Unmarking instance as dft_abstract_dont_scan
as all abstract segments defined on it have been
deleted.
This is done to allow flops (if present) within the
instance to be scan synthesized.
DFT-182 No internal registers with fixed value outputs
were found.
Ensure that the STIL file used by the
'identify_test_mode_registers' command has
been updated with the required test-mode
initialization sequence.
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Message Reference for Encounter RTL Compiler
Info Messages
May 2013 15 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
DFT-185 Did not find any shift-register segment in the
design.
Shift registers are searched along the
functional path. A shift register is considered a
valid scan segment if the set, reset, and preset
pins of all its flops are held at their inactive
value and the enable pin is held to its active
value. Ensure that test mode signals are
specified for the synchronous pins of the flops
in the shift register. Additionally, ensure that the
'-min_length' and '-max_length' options have
proper values, and that the design is not
already scan-connected.
DFT-186 Identified a shift-register scan segment.
DFT-187 Would identify a shift-register scan segment.
DFT-220 Cannot unmap instance.
DFT-275 Propagating DFT constants. Will propagate the DFT constants and try to
determine the hookup pin again.
DFT-276 Test clock defined during DFT constant
propagation.
A test clock is auto-defined when the signal
controls the enable port of a latch that is fed by
a constant. To prevent auto-identification,
define this port as a test signal before running
this command OR set the design level attribute
'dft_identify_top_level_test_clocks' to false. The
later will prevent any test_clock identification
and so may not be the best choice.
DFT-303 Auto detection of Async control signal.
DFT-306 Rerun check_dft_rules. An operation has occurred that may cause
previous Test Design Rule Check (TDRC) data
to be invalidated. Examples of such operations
are netlist changes, modification of test clocks
or signals, etc. Rerun check_dft_rules.
DFT-501 Terminal lockup not needed. The terminal lockup element is not needed
because the last element in the chain already is
a lockup element, probably because the tail
segment in the chain is a skew-safe segment.
DFT-502 Terminal lockup not needed for the current scan
style.
Terminal lockup elements serve no purpose for
the current scan style.
DFT-550 Scan mapping summary. A short summary of what happened during
scan mapping.
DFT-564 Updated the scan chain.
DFT-569 Associating wrapper segment to port.
DFT-650 Identified test clock for dedicated wrapper cell. A test clock has been identified from the fanin/
fanout analysis of the port.
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May 2013 16 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
DFT-653 Excluding port from wrapper cell insertion. Excluding this port from wrapper cell insertion,
since user has specified to exclude it or it is a
combinational feedthrough path and user has
specified option
'-exclude_comb_feedthrough_paths'.
DFT-715 Lockup element insertion is unnecessary for
analyzed chain.
Insertion of lockup elements is unnecessary
when (1)The the analyzed scan chain has no
test clock domain transitions (2)It already has
lockup elements inserted where the test clock
domain transitions occur or (3)The scan style is
not 'muxed_scan'.
DFT_GL-103 Skip the 'pll' reset pin related checks. In order to run the 'pll' reset pin related checks
specify the 'pll' reset pin.
DFT_GUIDELINE-407 Test clock signal propagates to primary output
port.
The endpoint of test signal is a primary output
port, which may be effected during functional
examination and not get the expected value .
DFT_GUIDELINE-408 Async clear and preset pins are driven by same
source point.
As async clear and preset pins are driven by
same source point, the output of flop became
irregular if both the pins are active at same
time.
DFT_GUIDELINE-409 The data pin of flop is driven by constant. Failure detection rate decreases as data pin of
flop is tied to a constant ,so ensure that a
constant should not propagate to data pin of
flop..
DFT_GUIDELINE-410 Blackbox connected to the data pin. Detection of failure cannot be performed, as the
data pin is driven by blackbox and failure
detection rate decreases.
ECCD-414 Completed CCD execution. CCD ran successfully without any errors.
ELAB-1 Elaborating Design.
ELAB-2 Elaborating Subdesign.
ELAB-3 Done Elaborating Design.
ELAB-4 Error in Elaborating Design.
ELABUTL-128 Undriven module output port.
ELABUTL-129 Unconnected instance input port detected.
ELABUTL-130 Undriven signal detected.
ELABUTL-131 Undriven module input port.
ELABUTL-132 Unused instance port.
ENC-8 Encounter executable found. The specified Encounter executable will be
used for the Encounter batch jobs.
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May 2013 17 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
ENC-13 The design has been changed by Encounter. The design was changed during QoS
prediction. This may include netlist structural
changes.
ENC-17 The following license was used for the
Encounter session.
The specified license was used for the
Encounter session. Use the enc_license_flag
attribute to specify a particular license.
ENC-18 The following executable version was used for
the Encounter session.
The specified Encounter version was used for
the Encounter batch job.
ENC-21 An Encounter license will be checked out. A license will be checked out for the Encounter
batch job. The license will be checked in when
the job is finished.
ENC_MSV-301 Design has no library or power domains. No power domains will be created for
Encounter.
GB-1 Doing context sensitive CSA optimization.
GB-2 Generating Booth encoder for Product-Of-Sum
form.
GB-3 Doing super operator transformations.
GB-4 Doing conservative CSA transformations.
GB-6 A datapath component has been ungrouped.
GLO-12 Replacing a flip-flop with a logic constant 0. This optimization was enabled by the root
attribute 'optimize_constant_0_flops'.
GLO-13 Replacing a flip-flop with a logic constant 1. This optimization was enabled by the root
attribute 'optimize_constant_1_flops'.
GLO-14 Replacing a latch with a logic constant 0. This optimization was enabled by the root
attribute 'optimize_constant_latches'.
GLO-15 Replacing a latch with a logic constant 1. This optimization was enabled by the root
attribute 'optimize_constant_latches'.
GLO-16 Deleting a transparent latch. This optimization replaces a latch with a
feedthrough.
GLO-17 Replacing a blocking latch with a logic constant
0.
The value used to replace the latch can be set
by the root attribute 'optimize_seq_x_to'.
GLO-18 Replacing a blocking latch with a logic constant
1.
The value used to replace the latch can be set
by the root attribute 'optimize_seq_x_to'.
GLO-19 Replacing a blocking latch with a dont care. The value used to replace the latch can be set
by the root attribute 'optimize_seq_x_to'.
GLO-20 Replacing a blocking flip-flop with a dont care. The value used to replace the flop can be set by
the root attribute 'optimize_seq_x_to'.
GLO-21 Replacing a blocking flip-flop with a logic
constant 0.
The value used to replace the flop can be set by
the root attribute 'optimize_seq_x_to'.
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GLO-22 Replacing a blocking flip-flop with a logic
constant 1.
The value used to replace the flop can be set by
the root attribute 'optimize_seq_x_to'.
GLO-23 Replacing a dont care flip-flop with a dont care. The value used to replace the flop can be set by
the root attribute 'optimize_seq_x_to'.
GLO-24 Replacing a dont care flip-flop with a logic
constant 0.
The value used to replace the flop can be set by
the root attribute 'optimize_seq_x_to'.
GLO-25 Replacing a dont care flip-flop with a logic
constant 1.
The value used to replace the flop can be set by
the root attribute 'optimize_seq_x_to'.
GLO-30 Replaced instances of avoided library cells. To disable this replacement, set the 'preserve'
attribute on the affected instance(s) or the
instances' library cell, or remove the 'avoid'
attribute on the instances' library cell.
GLO-31 Replaced instance of avoided library cell. To prevent this replacement, set the 'preserve'
attribute to 'true' on the affected instance(s) or
its library cell, or set the 'avoid' attribute to
'false' on the library cell of the instance.
GLO-32 Deleting instances not driving any primary
outputs.
Optimizations such as constant propagation or
redundancy removal could change the
connections so an instance does not drive any
primary outputs anymore. To see the list of
deleted instances, set the 'information_level'
attribute to 2 or above.
GLO-33 Found floating hierarchical output. To see the list of floating hierarchical instances,
set the 'information_level' attribute to 2 or
above.
GLO-40 Combinational hierarchical blocks with identical
inputs have been merged.
This optimization usually reduces design area.
To prevent merging of combinational
hierarchical blocks, set the
'merge_combinational_hier_instances' root
attribute to 'false' or the
'merge_combinational_hier_instance' instance
attribute to 'false'.
GLO-41 Sequential hierarchical blocks with identical
inputs have been merged.
This can be turned off with 'set
cse_sequential_hier_instances 0'.
GLO-42 Equivalent sequential instances have been
merged.
To prevent merging of sequential instances, set
the 'optimize_merge_flops' and
'optimize_merge_latches' root attributes to
'false' or the 'optimize_merge_seq' instance
attribute to 'false'.
GLO-43 Invert equivalent sequential instances have
been merged.
To prevent merging of sequential instances, set
the 'optimize_merge_flops' and
'optimize_merge_latches' root attributes to
'false' or the 'optimize_merge_seq' instance
attribute to 'false'.
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2003-2013 Cadence Design Systems, Inc. All rights reserved.
GLO-45 Replacing the synchronous part of an always
feeding back flip-flop with a logic constant.
The value used to replace the flop can be set by
the root attribute 'optimize_seq_x_to'. The
assigned constant might also conflict with the
simulation and/or verification setup.
GLO-51 Hierarchical instance automatically ungrouped. Hierarchical instances can be automatically
ungrouped to allow for better area or timing
optimization. You can control auto ungrouping
using the root-level attribute 'auto_ungroup'.
You can skip individual instances or modules
using the attribute 'ungroup_ok'.
GSC-1 No pins specified.
GSC-2 No pins with general stitching code attributes
found.
Found no pin with gsc_pin_function attributes.
HF-113 DEF file is not created for ILM. A floorplan is not read. So DEF file is not
written for ILM. Load the floorplan using
'read_def'.
HF-114 File is not found for ILM. Check the path and filename again and check if
the file exists.
HPT-78 Freeing module.
HPT-79 Undumping module.
INCRSYN-1 Preparing incremental synthesis.
INCRSYN-12 Finished creating incremental synthesis cache
data.
ISO-102 Isolation rule defined.
ISO-103 Empty rule created. No valid pin(s)/port(s) for isolation rule
definition available.
ISO-116 Could not define isolation rule.
ISO-117 No driver pin found in pin list given with
'-enable_driver'. Selecting one of drivers of
specified pins.
ISO-200 Completed isolation cell insertion.
ISO-208 Isolation cell not inserted. Isolation cells are inserted between two power
domains, if one of them is OFF in at least one
power mode.
ISO-214 Isolation cell inserted.
ISO-216 No cell found that is an isolation cell and level
shifter.
The tool will try to synthesize the required
isolation logic using available cells. Depending
on whether it finds suitable cells, the tool may or
may not insert isolation logic.
ISO-301 Could not use the library cell as isolation cell. Data pin of the cell is inverted.
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ISO-403 Removed isolation logic.
ISO-501 Isolation cell inserted at dft port.
ISO-602 Found isolation cells inserted by other tools.
ISO-603 Isolation cell import completed.
ISO-604 Could not import as isolation cell.
ISO-605 Uniquifying the multiple instantiated subdesign
to prepare for isolation cell import.
ISO-606 Hierarchical instance imported as isolation cell.
ISO-607 Subdesign imported as isolation cell module.
ISO-611 Skipping the current hierarchy from importing. Try using 'ui_respects_preserve' to false.
ISO-612 Uniquifying the multiple instantiated subdesign
to prepare for isolation cell import.
LBR-1 Multiple objects with same name in library. The new object will overwrite the original one.
LBR-3 Appending library. Appending libraries will overwrite some of the
characteristics of the library.
LBR-27 Replacing timing arc(s).
LBR-30 Promoting a setup arc to recovery. Setup arcs to asynchronous input pins are not
supported.
LBR-31 Promoting a hold arc to removal. Hold arcs to asynchronous input pins are not
supported.
LBR-40 An unsupported construct was detected in this
library.
Check to see if this construct is really needed
for synthesis. Many liberty constructs are not
actually required.
LBR-41 An output library pin lacks a function attribute. If the remainder of this library cell's semantic
checks are successful, it will be considered as
a timing-model (because one of its outputs
does not have a valid function.
LBR-42 Could not parse a library pin's function
statement.
Check the pin's function statement in the library
source.
LBR-46 Unsupported bus_type declaration. Attribute values should be integer.
LBR-47 Unsupported bus_type declaration. Non-bool
value for bus_type attribute 'downto'.
Attribute value should be either 'true' or 'false'.
LBR-48 Unsupported bus_type declaration. 'bus_type' attribute 'bus_width' is less than 1.
LBR-49 Unsupported bus_type declaration.
LBR-54 Library has missing unit. Current library has missing unit.
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2003-2013 Cadence Design Systems, Inc. All rights reserved.
LBR-70 Automatically disabling a borrow arc in a
flip-flop.
The library cell was described as a flip-flop yet
this timing arc appears to be intended for
time-borrowing. Time borrowing is not
supported in flip-flops.
LBR-71 Automatically disabling an unsupported borrow
arc.
The library cell appears to be a latch, yet an arc
was found between the D and Q pins that was
not described as combinational. Only
combinational arcs may be used for
time-borrowing.
LBR-72 Detected an unsupported timing arc type. Refer to 'Supported Liberty timing_type Values'
in 'Setting Constraints and Performing Timing
Analysis Using Encounter RTL Compiler' for
more information.
LBR-74 Disabling a setup/recovery arc. Setup/recovery arcs to output pins are not
supported.
LBR-77 Automatically disabling a scan-only
combinational arc.
The library cell is sequential and it has a
combinational arc involving at least one pin that
is only used in scan mode. You can enable
such arcs by setting root-level attribute
"ignore_scan_combinational_arcs" to false, but
that will deem the cell unusable.
LBR-83 Found 'statetable' group in cell. Currently, state tables are only supported for
scan cells for the clocked LSSD scan style and
for clock-gating cells whose Liberty attribute
'clock_gating_integrated_cell' is set to 'generic'.
LBR-109 Set default library domain.
LBR-114 Overwrite previously defined pin function with
user function.
LBR-118 Inverting the sense of a setup arc to be
consistent with the launching clock edge.
In a flip-flop, the setup and clock -> q arcs must
refer to the same clock edge. In a latch, they
must refer to opposite clock edges. The
technology library has an inconsistency in this
respect.
LBR-119 Use model will change in future release. Operating condition is set before libraries were
loaded. Future releases will require you to
specify an object instead of a string.
Consequently, you will only be able to set this
attribute after you load libraries.
LBR-120 Removing libraries.
LBR-122 Automatically disabling an inconsistent clock
edge arc.
The library description of this flip-flop or latch
specified multiple clock edge arcs that are
sensitive to different clock edges. A flip-flop or
latch may only be sensitive to one clock edge.
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LBR-123 Automatically disabling an unsupported timing
arc.
The timing arc connects two pins that are
already connected by a clock edge arc. Clock
edge arcs cannot be mixed with non-clock-edge
arcs in a flip-flop or latch.
LBR-149 Replaced unresolved instances with mapped
instances.
The subdesigns with the same name as the
library cells that were missing in the old library
domain were removed.
LBR-155 Mismatch in unateness between 'timing_sense'
attribute and the function.
The 'timing_sense' attribute will be respected.
LBR-160 Library-cells are not swappable. Check the number of input, output, and internal
pins of the two library cells as well as the
functions of the output pins.
LBR-161 Setting the maximum print count of this
message to 10 if information_level is less than 9.
LBR-162 Both 'pos_unate' and 'neg_unate' timing_sense
arcs have been processed.
Setting the 'timing_sense' to non_unate.
LBR-170 Ignoring specified timing sense. Timing sense should never be set with
'rising_edge' or 'falling_edge' timing type.
LBR-202 Invalid level shifter / isolation cell.
LBR-204 Undefined 'mode_definition' group.
LBR-209 Removed the existing level shifter group.
LBR-218 Level shifter cell is set to be avoided. To use the level shifter cell, the avoid attribute
must be set to false.
LBR-409 Found conflicting clock polarity information. The tool derives the clock polarity from the
sequential timing arcs specified through the
Liberty 'timing_type' attribute. For the
positive-edge triggered cells a positive value is
expected for the 'clocked_on' or 'enable'
attribute while an inverted value is expected for
the negative-edge triggered sequential cells.
LBR-412 Created nominal operating condition. The nominal operating condition represents
either the nominal PVT values if specified in the
library source, or the default PVT values (1.0,
1.0, 1.0).
LBR-415 Found unusable library cells. For more information, refer to 'Cells Identified
as Unusable' in the RC User Guide. The
number of unusable cells that is listed depends
on the setting of the 'information_level' root
attribute. If set to a value less than 6, the list is
limited to 10 unusable cells. If set to a value
equal to or higher than 6, all unusable cells are
listed.
LEX-3 Illegal size specification.
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May 2013 23 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
LIC-1 Limited access feature. Final production licensing of this limited access
feature has not been determined and is subject
to change. Usage and support of this limited
access feature are subject to prior agreement
with Cadence. In addition, Cadence assumes
you understand the feature limitations and
expected results. Contact your Cadence
representative if you have any questions.
LIC-2 Beta feature. Final production licensing of this beta feature
has not been determined and is subject to
change. Usage and support of this beta feature
are subject to prior agreement with Cadence. In
addition, Cadence assumes you understand
the feature limitations and expected results.
Contact your Cadence representative if you
have any questions.
LIC-10 License checkout request.
LIC-11 Preventing license checkout.
LS-100 Removed level shifter.
LS-106 Ignored instance for level shifter removal. The instance is neither a hierarchical level
shifter instance nor its parent.
LS-110 Removed invalid level shifter hierarchy.
LS-201 Skipped level shifter insertion. Define level shifter cells between these
domains. To define level shifters, use
'define_level_shifter_group' in non-CPF flow or
'define_level_shifter_cell' in CPF flow.
LS-207 Completed level shifter insertion.
LS-209 Ignore level shifter insertion from a library
domain to another library domain with lower or
same operating voltage.
LS-210 Uniquifying the multiple instantiated subdesign
to prepare for level shifter insertion.
LS-220 Could not insert level shifter.
LS-221 Pin/Port has multiple domain load. Extra ports might be created for level shifter
insertion.
LS-222 Insert level shifter using CPF specifications.
LS-223 No CPF commands for level shifter insertion can
be found.
LS-233 One or more pin/port loads' power domain does
not match with the power domain given with
-to_power_domain option.
For more information on -from_power_domain
option, consult 'level_shifter insert' in user
guide.
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LS-234 One or more pin/port drivers' power domain
does not match with the power domain given
with -from_power_domain option.
For more information on -from_power_domain
option, consult 'level_shifter insert' in user
guide.
LS-300 Merging level shifters.
LS-301 Newly merged level shifters.
LS-302 Merging level shifters from.
LS-303 Level shifters before merging.
LS-304 Level shifters after merging.
LS-501 Removing level shifter instance.
LS-502 Inserting level shifter instance.
LS-602 Found level shifters inserted by other tools.
LS-603 Level shifter import completed.
LS-604 Could not import level shifter.
LS-605 Uniquifying the multiple instantiated subdesign
to prepare for level shifter import.
LS-606 Hierarchical instance imported as level shifter.
LS-607 Subdesign imported as level shifter module.
MAP-4 Non-standard use of global mapping. The results from the non-standard flow are not
necessarily better or worse, but could just be
different from the standard flow.
MAP-6 Unable to unmap a sequential cell with
exceptions/attributes on the input pins.
MAP-7 Removing exceptions from a sequential cell
while unmap.
MAP-9 Could not find pin or port.
MAP-10 You can reproduce this netlist by setting attribute
'stop_at_iopt_state' to the appropriate iopt state
as follow:
MAP-15 Sequential phase inversion. This optimization was enabled by
'lbr_seq_in_out_phase_opto' root attribute.
MAP-24 Rerun of check_dft_rules may be needed. Multibit mapping has changed the previous Test
Design Rule Check (TDRC) data as it ran
check_dft_rules with default options.
MAP-25 Discrepancy between the mapper-timer and
ian-timer has been detected.
This is a development only check and can be
disabled by setting
fatal_on_constraint_checking to '0'.
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MAP-26 Cannot split the multibit cell. A multibit cell mapped to regular multibit library
cell and having proper 1-bit replacement
available in library can only be split.
MAP-29 Sequential phase inversion. This optimization was enabled by
'lbr_async_clr_pre_seq_interchangable' root
attribute.
MAP-30 Attribute map_enhanced_parallelization is
enabled.
MAP-127 Enabling some advanced optimizations in
incremental optimization.
Enabling this attribute can potentially improve
Qor and increase runtime.
MAP-128 Enabling some advanced optimizations in global
mapping.
Enabling this attribute can potentially improve
Qor and increase runtime.
MAP-130 Enabling TNS optimization for Parallel
Incremental Optimization.
Parallel Incremental Optimization is executed in
TNS mode to ensure consistency of QOR. Any
comparison to single thread Incremental
Optimization should be done in TNS mode only.
MAP-133 The create_timing_budgets command was
successful.
Timing Budget Created.
MBIST-1 No memory cells to BIST. No target memory cells or instances provided in
the configuration file.
MBIST-2 Module location is used multiple times. Module location for the target BIST engine is
used multiple times and has multiple instances.
All instances will be modified to insert the BIST
engine. Verify that the indicated number of
instances of a module agree with the expected
value.
MBIST-3 Module location has a single instance. Module location for the target BIST engine has
a single instance. Instance will be modified to
insert the BIST engine.
MBIST-4 No JTAG attention pin found. No BIST engine inserted, thus no JTAG
attention pin associated with the memory BIST
engine found. Verify no BIST engines are to be
inserted.
MBIST-5 No TDO pin found. No memory BIST engine inserted, thus no TDO
pin associated with the memory BIST engine's
scan chain found. Ensure no BIST engines are
to be inserted.
MBIST-6 No TDI pin found. No memory BIST engine inserted, thus no TDI
pin associated with the memory BIST engine's
scan chain found. Ensure no BIST engines are
to be inserted.
MBIST-7 System clock source net is found in module. Clock source net is used as a clock input to the
associated target group's BIST engine(s).
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MBIST-9 The synthesis phase of the processing
completed.
Check the log file to verify no rules or
assumptions are violated.
MBIST-10 Completed writing output netlist file. Check for any preceding Warning messages to
ensure the file's format and contents are as
intended.
MBIST-11 No functional net is connected to pin. Ensure no functional net is assumed to be
connected.
MBIST-12 Input pin on memory instance is left
unconnected.
Ensure the pin is required to be left
unconnected.
MBIST-13 Input bus on memory instance is left
unconnected.
Ensure the bus is required to be left
unconnected.
MBIST-14 Writing output netlist of test macro to file.
MBIST-15 Deleting unconnected ports on program
generated module.
MBIST-16 Synthesis/Timing completed successfully for
module.
MBIST-17 Synthesis ran successfully for module.
MBIST-18 Directory was not found, creating directory.
MBIST-19 Checking the existence of file.
MBIST-20 Embedded test macro targeted to run at
specified frequency.
MBIST-21 Memory Target and BIST Engine Summary.
MBIST-22 Memory Cell and Initial MBIST Status.
MBIST-23 Started MBIST insertion.
MBIST-24 MBIST inserted successfully.
MBIST-25 Started checking MBIST rules.
MBIST-26 Finished checking MBIST rules.
MBIST-27 Generation of the configuration file template
completed.
Check for any preceding Warning messages to
ensure the file's format and contents are as
intended.
MBIST-28 Bitmap MBISTREAD TDR segment summary
table.
MBIST-29 All the traversals will be done in a specific
'dft_configuration_mode'.
Verify that the attributes of this mode are
correct.
MBIST-30 Interface files location used for checking MBIST
rules is specified below.
Make sure that the interface files directory
being used is correct.
MBIST-31 Memory cell pin usage status.
MBIST-32 MBIST area overhead summary table.
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MBIST-33 MBIST area comparison table.
MBIST-34 No clock gating macros found in the design. Make sure that the clock gating logic exist in the
design and re-run.
MBIST-35 Clock gating macros are replaced with clock
gating integrated cell.
MBIST-36 MBIST scheduling summary table.
MBIST-37 MBIST scheduling summary table, power and
test-time.
MBIST-38 Interface files location used for optimizing
MBIST schedule is specified below.
Make sure that the interface files directory
being used is correct.
MBIST-39 MBIST grouping summary table.
MBIST-40 MBIST grouping summary table, area and
wire-length.
MBIST-53 Redundant interface files specified. No response required.
MBIST-54 Created temporary directory. No response required.
MBIST-55 The format of the input netlist file is assumed. Ensure the assumed HDL format is as
expected.
MBIST-57 Black-box instance found. This instance will be ignored from the analysis.
MBIST-58 File with the same name already used.
Generated file will have different name.
No response required.
MBIST-59 Gathering required information for the memory. No response required.
MBIST-61 Write enable pin will be treated as write enable
mask for BIST purpose.
In case write enable mask pin is not present on
a memory then the write enable pin is treated
as write enable mask for BIST purpose. No
action is required.
MBIST-93 Pin of a memory cell is tied to logic. Ensure the pin is tied to a required value.
MBIST-96 This is an informational message. For faster resolution of the issue, provide this
information.
MESG-7 Message severity has been changed from
default value.
MM_FE-50 No output directory has been specified. Creating the output directory using the design
name appended with '_RC_FE_MM_PATH'.
MM_FE-51 FE path has been created.
MM_FE-53 File has been generated.
MM_FE-66 Not a Multi-Mode design. Default corner and mode will be created.
MSV_FE-50 FE path has been created.
MSV_FE-51 Identify the library domain for design top.
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MSV_FE-52 No FE file name specified.
MSV_FE-54 All the files are created successfully.
MSV_FE-55 This library domain is for level shifter.
MSV_FE-56 No hierarchical instances found for library
domain.
MSV_FE-57 No output directory has been specified. Creating the output directory using the design
name appended with '_RC_FE_MSV_PATH'.
MSV_FE-59 Start to generating file.
MSV_FE-60 File has been generated.
MTDCL-12 An inverter and a 2-input gate found in library
set.
MTDCL-14 Processing the instances on clock-path.
MTDCL-15 Preserved instance is skipped for replacement/
remapping.
MTDCL-18 Ignoring clock for dedicated cell library mapping. The clock should have a valid library set
defined in clock_library_cells attribute and a
source pin/port to track clock-path.
MTDCL-19 Preview mode is enabled. No changes will be
done to the design.
Keep information_level above 0 to get info
about all the changes.
MTDCL-20 Library cell of instances on clock-path will be
changed.
MTDCL-29 Successfully finished remapping the instances
on clock-path.
MTDCL-30 Preview of remapping based clock-path
optimization feature is not supported.
PA-6 Removed switching activities from nets driven by
clock source.
Removed switching activities (user-asserted or
computed) from all nets driven by this clock
source, because the switching activities of a
clock net are derived from the new (or latest)
clock definition.
PA-7 Resetting power analysis results. All computed switching activities are removed.
PA-8 Set the toggle rate for the clock net to '0/ns'. The toggle rate is the number of toggles within
a clock period. When the clock period is very
large, the toggle rate is rounded to '0/ns'. To
achieve better accuracy for power analysis,
define the clock with a meaningful value for the
period.
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PA-10 Ignored clock redefinition for power analysis. A clock redefinition is ignored for power
analysis when its associated clock net has
user-asserted switching activity information. To
apply the redefined clock for power analysis,
remove the user-asserted switching activity
information from the clock net, redefine the
clock and then perform power analysis.
PA-18 Skipped building RTL power model for
nonexistent instance.
Skipped modeling the hierarchical instance as it
is dangle and has been removed during netlist
clean-up.
PA-21 Ignoring this scope as it is outside the hierarchy
which can be monitored.
If '-module' option is used in 'read_vcd', you can
monitor scopes only which lie under the
specified hierarchy.
PA-30 A power loop has been found. The power loop has been disabled for power
analysis. This has no QoR impact.
PHYS-52 Physical information has been annotated. The physical information for the design has
been prepared and annotated.
PHYS-53 Existing placement will be used. The current instance placement will be used for
QoS prediction.
PHYS-63 Replay file created. The replay file contains a list of subcommands
run by Encounter interface commands.
PHYS-90 Generating design database. The database contains all the files required to
restore the design in the specified application.
PHYS-127 Macro with non-zero origin.
PHYS-129 Via with no resistance will have a value of '0.0'
assigned.
PHYS-145 Inconsistent pin direction prevents conversion to
pgpin.
Although the pin is considered a power or
ground pin in LEF, to be converted to pgpin, the
direction of the pin must be consistent in both
lib and LEF libraries.
PHYS-146 Pin complexity prevents conversion to pgpin. Although the pin is considered a power or
ground pin in LEF, it cannot be converted to
pgpin because it either has timing arcs, is a bus
or bundle member, is a retention pin, or has a
function defined for an output pin in the lib.
PHYS-153 Creating toplevel port.
PHYS-154 Creating physical pin.
PHYS-160 Creating derived placement blockages for
pre-routes.
PHYS-173 Reading hierarchical DEF for subdesign.
PHYS-174 Creating fence for hierarchical DEF.
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May 2013 30 Product Version 12.2
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PHYS-180 Placement blockage created for hierarchical
DEF.
PHYS-181 Full preserve set on instance. This message has a default max print count of
'10', which can be changed by setting the
'max_print' attribute.
PHYS-182 Cover component present.
PHYS-184 Incremental mode found existing component.
PHYS-185 Incremental mode found existing pin.
PHYS-186 Full preserve set on net. This message has a default max print count of
'10', which can be changed by setting the
'max_print' attribute.
PHYS-188 Preserve with sizing allowed set on instance.
PHYS-215 Power switch cell present.
PHYS-216 Skipping GCELLGRID statement.
PHYS-218 Connecting power switch cell nets.
PHYS-223 Placed component changed to fixed. Placed components with libcell not class CORE
are changed to fixed.
PHYS-230 Creating physical power domain.
PHYS-358 Unconnected port found. A port with no net connected has been found.
The net name is assumed to be the same as
the port name.
PHYS-362 SPECIALNETS section skipped during
write_def.
SPECIALNETS section is skipped during
write_def if input DEF is read using the
-no_specialnets option or the attribute
phys_ignore_special_nets is set to true.
PHYS-364 NETS section skipped during write_def. NETS section is skipped during write_def if
input DEF is read using the -no_nets option or
the attribute phys_ignore_nets is set to true.
PHYS-383 Loading library and cap-tables according to the
worst_corner specified by the user.
Loading library and cap-tables according to the
worst_corner specified by the user as opposed
to loading library and cap-tables from config
file.
PHYS-398 Restoration Complete. Finished Restoration.
PHYS-399 Found cap-table file. Found cap-table file in view definition.
PHYS-400 View definition file does not exist in encounter
db.
View definition does not exist in the encounter
database.
PHYS-401 Mode file not present. Mode file is not present in encounter db, mode
information will not be passed on to FE.
PHYS-402 Loaded config file. Successfully loaded config file into RC.
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May 2013 31 Product Version 12.2
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PHYS-403 Checking for avoided libcells in netlist. Checking for avoided libcells in netlist.
PHYS-404 No avoided libcells present in netlist. There are no libcells in the netlist which have
avoid=true.
PHYS-405 Avoided libcells present in netlist. There are libcells in the netlist which have
avoid=true.
PHYS-406 Skipping virtual clock. Skipping virtual clock for preserving
clock-source pin.
PHYS-407 Done preserving clock network/pins. Finished preserving all the clock-pins, except
virtual clocks.
PHYS-408 Done preserving sdc-gates. Finished preserving all the gates that appear in
the sdc.
PHYS-410 Using user specified DEF file. The DEF file specified by the user will take
precedence over the one present in the
database.
PHYS-414 No timing_derate information found in view
definition file for specified worst-corner.
Derate information could not be found the
worst-corner in the view definition file.
PHYS-419 Using constraint files specified in view definition
file.
The constraint files corresponding to the
specified analysis view will be used.
PHYS-420 The original location attributes have been
populated.
The original location attributes have been
populated.
PHYS-421 Location statistics. Printing instance location related statistics.
PHYS-422 Highlight statistics. Printing movement highlight statistics.
PHYS-423 No design loaded, cannot compute row height. Since there was no design loaded, row height
could not be computed.
PHYS-424 Multiple designs loaded, cannot compute row
height.
Since there is more than one design loaded,
row height could not be computed.
PHYS-425 Could not compute row height. Row height could not be computed from the
row attribute.
PHYS-431 Using delay-corner corresponding to specified
analysis mode.
The delay-corner corresponding to specified
analysis mode will be used.
PHYS-432 Timing derate sdc file found. The timing derate sdc file was found in the
saved database.
PHYS-434 Timing derate sdc file not found. The timing derate sdc file was not found in the
saved database.
PHYS-435 Operating condition was not set. The operating condition was not set because of
the above reasons.
PHYS-437 Found operating conditions in view definition file. Found the above operating conditions
corresponding to the specified corner.
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May 2013 32 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
PHYS-438 Could not find operating conditions in the view
definition file.
Could not find the operating conditions
corresponding to the specified corner for the
above reasons.
PHYS-439 Set the operating conditions from the view
definition file.
Operating conditions set according the view
definition file.
PHYS-440 The design being restored is a CPF design. The design being restored is a CPF design.
PHYS-444 Found QRC tech file. Found QRC tech file in view definition.
PHYS-604 It is recommended to provide average RC file
from encounter.
The Average RC file is not provided using
option "-average_rc_file". Already available per
unit capacitance and resistance information is
being used.
PLC-1 Placement Information.
PMBIST-16 Synthesis/Timing completed successfully for
module.
PMBIST-17 Synthesis ran successfully for module.
PMBIST-18 Directory was not found, creating directory. Creating the specified directory for storing the
generated output.
PMBIST-20 Embedded test macro targeted to run at
specified frequency.
PMBIST-21 Memory Target and programmable MBIST
Engine Summary.
PMBIST-23 Started programmable MBIST insertion.
PMBIST-24 Programmable MBIST inserted successfully.
PMBIST-27 Generation of the configuration file template
completed.
Check for any preceding warning messages to
ensure the file's format and contents are as
intended.
PMBIST-28 Generation of the view file template completed. Check for any preceding warning/error
messages to ensure the file's format and
contents are as intended.
PMBIST-29 All the traversals will be done in a specific
'dft_configuration_mode'.
Verify that the attributes of this mode are
correct.
PMBIST-30 No test signals present. All the traversals will be
done in the functional mode.
Verify that the mode is correct.
PMBIST-31 Memory cell pin usage status.
PMBIST-32 PMBIST area overhead summary table.
PMBIST-33 PMBIST area comparison table.
PMBIST-41 Summary table for 'read_memory_view'.
PMBIST-42 Summary table for 'algorithm constraints'.
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May 2013 33 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
PMBIST-43 Freeing existing interface files in memory.
PMBIST-53 Redundant interface files specified. No response required.
PMBIST-54 Created temporary directory. No response required.
PMBIST-55 The format of the input netlist file is assumed. Ensure the assumed HDL format is as
expected.
PMBIST-57 Black-box instance found. This instance will be ignored from the analysis.
PMBIST-58 File with the same name already used.
Generated file will have different name.
No response required.
PMBIST-59 Gathering required information for the memory. No response required.
PMBIST-61 Write enable pin will be treated as write enable
mask for BIST purpose.
In case write enable mask pin is not present on
a memory then the write enable pin is treated
as write enable mask for BIST purpose. No
action is required.
PMBIST-93 Pin of a memory cell is tied to logic. Ensure the pin is tied to a required value.
PMBIST-96 This is an informational message. For faster resolution of the issue, provide this
information.
POPT-10 Cannot find requested type of clock-gating
integrated cell.
POPT-11 Found user created clock-gating module.
POPT-12 Could not find any user created clock-gating
module.
Looking for Integrated clock-gating cell in
library.
POPT-13 User defined clock-gating module is not
complete.
Make sure the module has all ports defined
according to the manual.
POPT-17 The user specified clock-gating integrated cell
will override the 'lp_clock_gating_control_point'
and 'lp_clock_gating_style' settings.
POPT-22 Ignore the setting for automatically generating
test control port for clock-gating because the
user specified test signal exists.
POPT-25 CG instance drives dft_dont_scan flops.
POPT-27 Ignore the flip-flop for clock gating because its
synchronous pin is always enabled.

POPT-28 Ignore the flip-flop for clock gating because it
has multiple synchronous inputs.

POPT-29 Driver of the scan enable pin does not match the
scan signal defined by
lp_clock_gating_test_signal attribute. Treat the
scan pin as a regular synchronous enable signal
for clock gating insertion purpose.

POPT-30 MUX is deleted after clock gating logic inserted.
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May 2013 34 Product Version 12.2
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POPT-34 Could not include pin in clock-gating enable
logic.
Make sure the instance or module in which the
pin resides is not preserved.
POPT-35 Could not insert clock-gating for flip-flop. Make sure the logic which enables the
feedback loop is not preserved.
POPT-50 Could not declone clock-gating instances. Reset the 'lp_clock_gating_max_flops' attribute
to a bigger number and re-run the command.
POPT-51 Could not declone clock-gating instances. The design should have 2 or more clock-gating
instances for decloning.
POPT-52 Clock-gating instance will not be considered for
declone.
Make sure the 'preserve' attribute is set to
'false' on the clock-gating instance.
POPT-53 Clock-gating instance cannot be considered for
decloning.
Make sure the logic gates inside the
clock-gating module either have the correct
library cell attribute to be identified as
clock-gating logic, or implement a correct
clock-gating function.
POPT-61 Splitted the enable function of a clock-gating
instance.
The complex enable function of a clock-gating
instance is decomposed into multiple smaller
enable function and the original clock-gating
instance is converted into a set of multi-stage
clock-gating instances.
POPT-62 Merged the enable functions of two clock-gating
instances.
The enable function of a root level clock-gating
instance is merged with the enable function of a
leaf level clock gating instance. The original
multi-stage clock gating is converted into a
regular clock gating.
POPT-63 Clock-gating instance cannot be considered for
splitting.
Make sure the clock gating instance, the nets
connected to the clock pin and enable pin of the
clock gating logic and the driving logic for the
enable pin are not preserved.
POPT-64 Clock-gating instance cannot be considered for
splitting.
POPT-65 Clock-gating instance cannot be considered for
splitting.
A clock-gating instance is splittable only if its
enable logic is driven by a single output
combinational gate.
POPT-66 Clock-gating instance is not splittable. The enable logic of the clock gating instance
cannot be decomposed.
POPT-67 Clock-gating instance cannot be considered for
joining.
Make sure the clock gating instance and the
nets connected to the clock pin and enable pin
of the clock gating logic are not preserved.
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POPT-68 Clock-gating instance cannot be considered for
joining.
A clock-gating instance with synchronous set
logic cannot be considered for joining because
there is no way to create the new enable logic
without change the logic inside the clock gating
hierarchy. A clock-gating whose enable pin is
multiply driven is also ignored for joining.
POPT-69 Clock-gating instances cannot be considered for
joining.
Only those clock-gating instances, which have
the same test pin drivers and
lp_clock_gating_test_signal settings, can be
considered for joining.
POPT-71 The clock gating instance is violating the
'lp_clock_gating_min_flops' constraint.
Either the 'lp_clock_gating_min_flops'
constraint value was changed or the driven
flops were optimized. If the clock gating
instance is not preserved it might be removed.
POPT-83 Inserted a shared clock-gating instance. Shared clock-gating logic is inserted for enable
function shared by clock-gating logic in the
design.
POPT-92 A potential clock gating enable was not
considered due to the presence of timing
exceptions.
Clock gating timing exception awareness can
be disabled with the
'lp_clock_gating_exceptions_aware' attribute.
POPT-96 One or more cost groups were automatically
created for clock gate enable paths.
This feature can be disabled by setting the
attribute lp_clock_gating_auto_cost_grouping
false.
POPT-201 Signal width is too small. Signals of bitwidth lesser than 8 are not
considered for Operand Isolation.
POPT-204 Nothing to do in Operand Isolation.
POPT-205 Candidates found for Operand Isolation.
POPT-207 Committing Operand Isolation instance.
POPT-208 Decommitting (deleting) operand isolation
instance.

POPT-500 Make sure 'max_leakage_power' is set to
enable leakage power optimization.
Set 'max_leakage_power' before optimization.
POPT-510 Could not connect a power gating pin of a state
retention instance.
Specify an appropriate driver in state retention
rule in CPF file to make connections.
POPT-511 No usable cells in the libraries loaded has the
'power_gating_cell' attribute setting.
Load a library which has 'power_gating_cell'
attribute as 'true' on cells which are intended to
be used as state retention cells.
POPT-513 Could not find an always on buffer in the library
to feed the driver for this instance.
Load a proper library which contains always on
buffer cells or set the 'is_always_on' attribute on
buffer cells for them to get selected.
POPT-514 Cannot find a matching state retention cell for
the flip-flop.
Provide a complete state retention library with a
matching flip-flop for each regular flip-flop.
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May 2013 36 Product Version 12.2
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POPT-515 Preserve the instance of the power gating pin
driver.
POPT-525 Cannot detect a single state retention cell which
can be used for mapping.
Provide a proper state retention library with
cells usable as state retention cells.
POPT-536 Library pin phase mismatch detected while
swapping to an state retention cell.
Ensure that library cells with similar pin phases
are used for swapping state retention flops.
POPT-539 Could not find an always on inverter in the
library to feed the driver for this instance.
Load a proper library which contains always on
inverter cells or set the 'is_always_on' attribute
on inverter cells for them to get selected.
POPT-541 No state retention cell with a matching functional
class as that of the flip-flop being replaced was
found.
Both the normal and state retention cells should
have a common functional class for the state
retention cell to be considered as a candidate
for replacing the normal flip-flop.
POPT-542 The state retention library cell is not suitable to
replace the current library cell attached to the
flip-flop.
The state retention library cell must have been
provided either with the 'lp_map_to_srpg_cells'
attribute or the 'state_retention define_map'
command. Provide a proper state retention
library cell for effective replacement of the cell
attached to the flip-flop.
POPT-543 The state retention library cell does not have an
input pin corresponding to the normal library cell
it is trying to replace.
The state retention cell which has an equal
number of input pins as that of the normal
flip-flop will be used for replacement. Provide a
state retention cell with equal number of input
pins as that of the normal flip-flop.
POPT-544 The state retention library cell does not have an
output pin corresponding to the normal library
cell it is trying to replace.
The state retention cell which has an equal
number of output pins as that of the normal
flip-flop will be used for replacement. Provide a
state retention cell with equal number of output
pins as that of the normal flip-flop.
POPT-557 The '-vcd_module' option has not been specified
with the 'read_vcd' command.
The first scope encountered in the VCD file has
been selected for processing. This may result in
lesser coverage if the selected scope does not
match up to the design hierarchy to be
annotated. To get better coverage, provide the
VCD scope name with the '-vcd_module'
option.
POPT-558 The object could not be found under the
specified hierarchy.
This happens if the hierarchy specified with the
'-vcd_module' option lies more than one level
below the top level hierarchy or the hierarchy
specified with the '-module' option. Adjust the
specifications for the '-vcd_module' and the
'-module' options to avoid this scenario.
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May 2013 37 Product Version 12.2
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POPT-559 Multiple objects were found under the specified
hierarchy.
This happens if the hierarchy specified with the
'-vcd_module' option is not unique under the
top level hierarchy or the hierarchy specified
with the '-module' option. Adjust the
specifications for the '-vcd_module' and the
'-module' options to avoid this scenario.
POPT-560 The name of the generated SST2 database will
have the VCD filename as its prefix as the
'-write_sst2' option has not been specified.
You have specified either the '-activity_profile'
or the '-dynamic' option. To automatically load
the SST2 database in the waveform viewer, you
need to provide the '-simvision' option. To have
your own named SST2 database, you need to
use the '-write_sst2' option.
POPT-600 Could not dedicate subdesign of instance. Make sure the subdesign is not preserved.
PTAM-1 Performing setup for insert_dft ptam. Creating temporary work area, and
synthesizing modules that will be used
internally during insertion.
PTAM-2 Collecting isolation rule information.
PTAM-3 No isolation rules found.
PTAM-4 Collecting information about the lp_srpg_pg
enable signals.
The lp_srpg_pg_driver attributes on the
sequential instances in the design are used to
gather information about the lp_srpg_pg enable
signals.
PTAM-5 No sequential elements found in the design.
PTAM-6 Collecting information about all of the power
domains.
PTAM-7 No power domains found.
PTAM-8 Shutoff signal not found for power domain.
PTAM-9 Power Mode / Power Domain Summary.
PTAM-10 Verifying the pin connections. Ensuring that pins specified on the command
line are accessible for connections.
PTAM-11 Pin not specified. A pin was not specified on the command line,
using default pin name.
PTAM-12 Marking required pins with general stitching
code attributes.
PTAM-13 Identifying logical controls. Logical controls required to control each
power_control signal are identified.
PTAM-14 Multiple enable signals found for power domain. Logic consisting of OR gates will be created for
these enable signals.
PTAM-15 Inserting the test power control blocks. Inserting test power control blocks for the power
switch enable signals.
PTAM-16 Mux inserted for power domain.
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May 2013 38 Product Version 12.2
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PTAM-17 Block ptam_shift_logic_pse_block inserted for
power domain.
PTAM-18 Applying general stitching code attributes for
ptam_shift_logic_pse blocks.
PTAM-19 Inserting the test power control blocks. Inserting test power control blocks for the
isolation control enable signals.
PTAM-20 Multiple enable signals found for isolation rule. Logic consisting of AND gates will be created
for these enable signals.
PTAM-21 Block ptam_logic_pse_block inserted for
isolation rule.
PTAM-22 Inserting the test power control blocks. Inserting test power control blocks for the
lp_srpg_pg driver signals.
PTAM-23 Multiple enable signals found for lp_srpg_pg
driver.
Logic consisting of AND gates will be created
for these enable signals.
PTAM-24 Block ptam_shift_logic_pc_block inserted for
lp_srpg_pg driver.
PTAM-25 Creating test mode files. Using write_atpg -cadence to generate the
base assign file. Additional power test access
method flags are appended to this file.
PTAM-26 Creating assign file for power mode.
PTAM-27 Command insert_dft ptam started.
PTAM-28 Creating sequence file for power mode.
PTAM-29 Power Domain / Shutoff Signal Summary.
PTAM-30 Isolation Rule Summary.
PTAM-31 Block lp_srpg_pg Summary.
PTAM-32 No I/O cell present for port. Connections will made directory to the port.
PTAM-33 I/O cell found for port. Connections will be made to the pad pin.
PTAM-34 Port found for pin. The specified pin was traced to the port. This
port will be used in the generated sequence file.
PTAM-35 JTAG module found.
PTAM-36 Single enable signal found for power domain.
PTAM-37 Location for power mode shutoff signal found. The location for the power mode shutoff signal
for the power domain has been determined.
PTAM-38 Location for isolation control enable signal
determined.
PTAM-39 Single power domain found for isolation rule.
PTAM-40 Location for lp_srpg_pg driver signal
determined.
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May 2013 39 Product Version 12.2
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PTAM-41 Single power domain found for lp_srpg_pg
driver.
PTAM-42 Directory created.
PTAM-43 Reading Verilog file.
PTAM-44 Elaborating entity.
PTAM-45 Synthesizing design.
PTAM-46 Executing general stitching code. The general stitching code will use the following
general stitching code attributes to make the
connections for the various power control logic:
gsc_pin_function, gsc_pin_type,
gsc_pin_polarity.
PTAM-47 Tracing JTAG pin on JTAG module. Traced pin on the JTAG module back to a port.
PTAM-48 Control block summary. Position 0 is closest to final output.
PTAM-49 Insertion of power test access method logic
complete.
PTAM-50 Preview of power test access method logic
complete. No modifications have been made to
the netlist.
PTAM-51 Insertion of power test access method logic did
not complete successfully.
PTAM-52 Updated the length of the instruction.
PTAM-53 No power modes found.
RETIME-112 Retiming timing-critical design for area. Use min_delay option to retime for improved
delay.
RETIME-113 Retimed asynchronous reset behavior could not
be preserved without negatively impacting
timing.
Inserting gates for explicit reset and redoing
retiming. Disable with
retime_fallback_to_explicit_reset root-level
attribute.
RETIME-114 Retiming cannot be done on preserved designs/
subdesigns.
Change the preserve setting if the design/
subdesign should be retimed.
RETIME-501 Categorized flops into classes. Only flops in the same class can merge during
a retiming move.
RETIME-601 Unable to perform incremental retiming due to
following reason.
Refer to RC documentation for further details.
RETIME-701 Retiming modules are combinational connected. This might limit parallel processing.
RETIME-702 Retiming modules are combinational connected
through as cycle.
This might limit parallel processing.
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May 2013 40 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
RMSENA-10 Inserted synchronous enable has flops in its
transitive fanout.
Valid inserted synchronous enable signal
should be an output pin of a hierarchical
instance, should not be driven by constant,
should not be unconnected and should have at
least one flop in its transitive fanout.
RMSENA-11 Removed inserted synchronous enable. Inserted synchronous enable is removed
because it was found to be timing critical.
RMSENA-12 Removed inserted synchronous enable. Inserted synchronous enable is removed
because the command
'remove_inserted_sync_enable_logic' was
issued with '-all' option.
RMSENA-13 Could not find any inserted synchronous enable
in the design.
Load a design with inserted synchronous
enable.
RMSENA-14 Could not find a valid inserted synchronous
enable in the design.
Valid inserted synchronous enable signal
should be an output pin of a hierarchical
instance, should not be driven by constant,
should not be unconnected and should have at
least one flop in its transitive fanout.
RMSENA-15 Found valid inserted synchronous enables. Valid inserted synchronous enable signal
should be an output pin of a hierarchical
instance, should not be driven by constant,
should not be unconnected and should have at
least one flop in its transitive fanout.
RMSENA-16 Could not find any timing critical inserted
synchronous enable in the design.
Timing is either met for all inserted
synchronous enables or no timing constraints
are set for the design.
RMSENA-17 Found critical inserted synchronous enables. Critical synchronous enables have negative
slack.
RPT-7 Time taken to report power.
RPT-11 Detected inconsistency between voltage of
library and voltage from nominal_condition in
CPF.
The voltage specified in the library of power
domain does not match with the voltage
specified in CPF file. Using the voltage
specified in library.
RPT-22 Nothing to report. There is no more help available in this
message. If the help in this message was
insufficient, contact customer support with this
message ID.
RPT-34 HDL cross referencing is not enabled. Set the 'hdl_track_filename_row_col' root
attribute to 'true' before 'elaborate' to enable
HDL cross referencing. HDL cross referencing
is supported until 'synthesize -to_generic'.
RPT-42 No power mode specified. The design has power modes and 'report
power' is used without '-power_mode' option.
Without the option '-power_mode', power is
reported for the current state the design is in.
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May 2013 41 Product Version 12.2
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RTLOPT-10 Performing RTL speculation.
RTLOPT-15 Performing RTL shannon expansion.
RTLOPT-16 Performing pre-map downsize.
RTLOPT-17 Performing conservative CSA.
RTLOPT-20 Done carrysave optimization.
RTLOPT-21 Found netlist enhancement opportunities for
better CSA.
RTLOPT-22 Found carry save over truncation-extension.
RTLOPT-29 Tried to perform RTL resource sharing; but
finally rejected.
RTLOPT-30 Performing RTL resource sharing.
RTLOPT-40 Applied datapath macro transformation.
RTLOPT-42 Exploring sop box alternatives.
SDC-300 Entering sdc_shell. All sdc commands will work without the dc::
prefix inside sdc_shell. Type 'exit' to leave the
shell.
SDC-301 Leaving sdc_shell. Type sdc_shell to use it again.
ST-110 Connection established with super-threading
server.
RC is entering super-threading mode and has
established a connection with a CPU server
process. This is enabled by the root attributes
'super_thread_servers' or 'auto_super_thread'.
ST-112 A super-threading server has been shut down
normally.
A super-threaded optimization is complete and
a CPU server was successfully shut down.
ST-120 Attempting to launch a super-threading server. RC is entering super-threading mode and is
launching a CPU server process. This is
enabled by the root attribute
'super_thread_servers' or 'auto_super_thread'.
ST-121 Automatically enabling super-threading. RC is entering super-threading mode because
it is running on a multi-processor machine. Two
super-thread servers will be running on
'localhost' and no super-thread licenses will be
checked out. This is enabled by the root
attribute 'auto_super_thread'.
ST-150 Hit in the super-threading cache. An equivalent super-threading job was
previously computed and its result stored in the
cache. This is enabled by the root attribute
'super_thread_cache'.
ST-151 Miss in the super-threading cache. A job's data has not been found in the
super-threading cache and will be
subsequently stored. This is enabled by the
root attribute 'super_thread_cache'.
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May 2013 42 Product Version 12.2
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ST-153 Locked file in the super-threading cache. A job locked a file in the super-threading cache
while creating an entry and another job tried
creating the same entry. The second job will
proceed without caching.
STAT-2 No QOR data available to write statistics
database.
Enable 'statistics_log_data' attribute before
synthesis or run 'statistics log' command to
create the QOR metrics at required stages
before writing out the database.
STAT-3 Writing statistics database to file.
STAT-4 Reset the statistics information preset in the
database.
STAT-6 Specified metric name already exists.
STAT-7 Removed user defined metric.
STAT-12 No run and stage id data available to report.
STRUCT-100 GBB. This variable is not driving anything and will be
simplified.
STRUCT-101 Net driven by constant '0' and constant '1'. This will compromise the integrity of the
logic-constant source. Disconnecting constant
source 1.
STRUCT-102 Undriven variable.
STRUCT-103 Variable has no fanout. This variable is not driving anything and will be
simplified.
STRUCT-104 Implicit net declaration. Creating new wire with a default bit width equal
to '1'.
TIM-44 Could not find any critical driver pin. This is usually due to the slack limit being lower
than the worst negative slack.
TIM-92 Changing wireload model of a design/
subdesign.
The change of wireload model will likely change
the design's timing slightly.
TIM-102 Removing a clock object. If this clock is being removed unexpectedly, you
should investigate the cause for its removal.
Usually clocks get removed by the 'rm'
command.
TIM-167 An external clock is being defined. An external clock does not directly drive any
points within the design, but is only used as a
reference for external delays.
TIM-301 The following instances, preserved as
'size_delete_ok', are referred to by the exception
or clock being deleted. Leaving the
'inherited_preserve' attribute untouched for
these instances.
The attribute can be manually reset using
'set_attribute preserve'.
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May 2013 43 Product Version 12.2
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TIM-304 Replacing an existing timing exception with
another.
Existing exception had a name conflict with the
newly created exception. The exception created
at a later time is maintained.
TIM-307 Removing a timing exception.
TIM-501 Resetting the break_timing_paths attribute of a
pin removes exceptions set on the pin.
TIM-502 Removing the break_timing_paths attribute on a
pin removes external delays on the pin.
TSY-107 Processing existing instance of the
JTAG_MACRO.
If the JTAG_MACRO subdesign has no logic
content, the RC-DFT engine will build a default
JTAG_MACRO with support for all of the
user-defined JTAG instructions. If the
JTAG_MACRO contains logic, the RC-DFT
engine will check to make sure that it has all of
the required pins that would exist for an
RC-generated JTAG Macro built with the
mandatory JTAG instructions.
TSY-110 Adding a pin to the 'JTAG_MACRO' instance. Since the 'JTAG_MACRO' subdesign has more
pins than the instance, the RC-DFT engine will
add the additional pins to the instance. The
instance cannot have more pins than the
subdesign, otherwise the tool will terminate.
TSY-111 Excluded port from boundary scan insertion. Ports associated with pad cells that have more
than one pin with its 'is_pad' attribute set to
'true' are excluded from boundary scan
insertion.
TSY-812 IOSpecList data erased. IOSpecList of the specified type was
successfully erased from the memory.
TSY-813 IOSpecList file read. IOSpecList of the specified type was
successfully read into memory.
TSY-814 IOSpecList file written. IOSpecList of the specified type was
successfully written to the specified file.
TUI-54 Object already has requested name. No changes were performed. No further action
is required.
TUI-58 Removed object.
TUI-59 Potentially inefficient use of the 'find' command. The number of objects searched exceeded the
threshold set by the 'find_object_threshold' root
attribute. The 'find' command does not stop
when this threshold is reached. This is an
informational message indicating a potentially
inefficient use of 'find'. To disable this message
use 'suppress_messages TUI-59' or set the
attribute value to zero or a higher value.
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May 2013 44 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
TUI-212 'map_size_ok' only applies to sequential leaf
instances.
Use other preserve flavors to preserve
non-sequential instances.
TUI-246 Deleting the contents of subdesign. The subdesign is gone and cannot be brought
back.
TUI-247 Unresolved attribute set to false for loop breaker
instances. Loop breakers will be reinserted if a
combinational cycle is found.
Loop breaker will be re-inserted if a
combinational cycle is found.
TUI-269 Instance already bound to the specified libcell. Specify a different library cell.
TUI-280 An additional product license has been checked
out.
The command 'license checkin' can be used to
check the license back in when it is no longer
needed.
TUI-284 A product license has been checked in. The 'license' command controls license
check-out and check-in.
TUI-287 Beta feature checking was successful. The 'beta_feature_enabled' function checked
the validity of the specified Beta feature.
TUI-296 The given (sub)design is already uniquified. Try running the 'edit_netlist uniquify' command
on the parent hierarchy of this (sub)design, if
there exists any.
TUI-297 The given instance(s) already have a dedicated
subdesign.
Try running the 'edit_netlist
dedicate_subdesign' command on the parent
hierarchy of the instance(s), if there exists any.
TUI-306 An additional product license has been checked
out.
TUI-307 A product license has been checked in.
TUI-308 License promotion has been used to check out a
more advanced license.
This can be prevented by checking out the
desired license using the 'license checkout'
command ahead of time.
TUI-309 License checkout failed. If the DFT Architect Basic license is not
available, the tool will additionally attempt to
check out the LBIST option and then Architect
Advanced licences to enable the feature.
TUI-507 Executing scripts embedded in the input HDL
file.
Scripts embedded in the input HDL file between
'script_begin' and 'script_end' pragmas are
automatically executed at the end of 'elaborate'.
Use 'set_attribute hdl_auto_exec_sdc_scripts
false' to disable automatic execution of
embedded scripts. Use 'get_attribute
embedded_script <design/subdesign>' to
retrieve the embedded scripts.
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May 2013 45 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
TUI-508 Found scripts embedded in the input HDL file. Scripts are embedded in the input HDL file
between 'script_begin' and 'script_end'
pragmas. Use 'exec_embedded_script' to
execute the scripts. Use 'get_attribute
embedded_script <design/subdesign>' to
retrieve the embedded scripts.
TUI-710 Changing library domain on non-uniquified
subdesign. The library domain will be set on all
instantiations of this subdesign.
Use 'edit_netlist dedicate' to uniquify
subdesigns first and then set the attribute on
the uniquified subdesign if you do not want to
copy the library domain to all instantiations.
TUI-726 Found instances of power domain with different
library domains.
All the instances within a power domain are
expected to be bound to the same library
domain, but multiple library domains were
found. It is possible that the library domains
were assigned directly on the instances'
subdesigns instead of being set using the
library_domain attribute of the power domain.
The 'library_domain' attribute on the power
domain will have no value in such cases.
TUI-737 Timing analysis will be done only for default
mode.
An RTL_Compiler_Low_Power_Option license
is required to do timing analysis for non-default
modes.
TUI-739 Timing analysis will be done for this mode. Worst paths will be shown in this mode.
TUI-740 Report instances with pin(s) where timing paths
are broken per modes.
Only instance(s) will be shown.
TUI-753 Cannot define an isolation rule for the pin/port. Isolation rule cannot be applied on a pin/port, if
this is same as the enable driver of the rule. As
a result, the isolation rule is created with the pin
specified to drive the enable signal, but the pin
is not added to the list of pins to be isolated.
TUI-787 Type: Cell selected for insertion is from level
shifter rule.
TUI-788 Type: Cell selected for insertion is from isolation
rule.
TUI-791 Type: Completed isolation cell insertion.
TUI-792 Type: Completed level shifter insertion.
TUI-796 Type: Level shifting is not necessary based on
threshold value specified with rule.
TUI-853 Type: Looking for Enabled level shifter cell.
TUI-856 Type: Command 'commit_power_intent' cannot
proceed as there is no power intent loaded.
TUI-857 Type: Inserted LP cell.
Message-ID Title Help
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May 2013 46 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
TUI-858 Type: Command 'commit_power_intent' cannot
proceed as there are no power domains
present.
TUI-860 Type: Low power cell insertion is not tried out.
TUI-863 Type: Skipping cell insertion on pin.
UTUI-119 Net is user-preserved/internal-preserved.
Assign cannot be removed.
To allow assign removal remove the preserve
attribute or use -ignore_preserve_setting of
set_remove_assign_options command.
UTUI-122 Removing instance. This loop breaker instance has been removed.
UTUI-125 Option '-skip_unconstrained_paths' is a hidden
obsolete option.
The option '-skip_unconstrained_paths' is ON
be default and will be removed from next
release of RC.
UTUI-130 Design/Subdesign is preserved. Assign cannot
be removed.
To allow assign removal remove the preserve
attribute or use -ignore_preserve_setting of
set_remove_assign_options command.
UTUI-132 Adding floating buffer.
UTUI-201 Scan inputs are ignored for tie-cell insertion. Use the '-all' option to avoid skipping of scan
pins.
UTUI-202 Unused hierarchical pins are ignored for tie-cell
insertion.
Do not use the '-skip_unused_hier_pins' to
allow inserting tiecells for these pins for
stand-alone command. These are skipped by
default when tie-cell insertion is done as part of
Incremental Optimization.
UTUI-203 Preserved nets are ignored for tie-cell insertion. Set 'ui_respects_preserve' attribute to 'false' or
'ignore_preserve_in_tiecell_insertion' attribute
to true to insert tiehilo cells for 'preserved' nets.
UTUI-207 Connecting constant net to TIELO/TIEHI cells.
UTUI-210 Done connecting 1'b0 and 1'b1 to TIELO/TIEHI
cells.
UTUI-217 Using tiecell of opposite phase with inverter. This is enabled by use of attribute
'iopt_allow_tiecell_with_inversion' or
'-allow_inversion' option.
VCD-16 Directory path has been created.
VCD-18 '-time_window' option not specified. No timing window was specified for either
activity profiling or dynamic analysis. Automatic
time window selection was done based on
power analysis effort level.
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May 2013 47 Product Version 12.2
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VCD-19 'start_time' option was specified but '-end_time'
and '-time_window' options were not specified.
If no 'time_window' option is specified, the
timing window is automatically selected based
on power analysis effort level if the start and
end times are also specified. Provide an end
time with the '-end_time' option for the time
window to be selected automatically based on
power analysis effort level.
VCD-20 '-start_time', 'end_time' and '-time_window'
options were not specified.
If no 'time_window' option is specified, the
timing window is automatically selected based
on power analysis effort level if the start and
end times are also specified. Provide the start
and end times with the '-start_time' and
'-end_time' options respectively for the time
window to be selected automatically based on
power analysis effort level.
VCD-21 '-time_window' option not specified. No timing window was specified for either
activity profiling or dynamic analysis. The timing
window selection was not done based on power
analysis effort levels as the total analysis period
is small at less than '100' picoseconds.
VHDL-205 VHDL file(s) analyzed successfully.
VHDL-212 Replacing architecture. An architecture is replaced when an
architecture of the same name for the same
entity is read again.
VHDL-224 Deleting out-of-date entity from module pool. Assume that an entity 'E' has been successfully
analyzed previously. If entity E is analyzed
again and contains errors, it (and all its
architectures) are deleted from the module pool
and will need to be re-analyzed.
VHDL-622 Using resolution function. The specified signal or its subtype has a
resolution function which has been annotated
with a 'wired_or' or 'wired_and' resolution
behavior.
VHDL-659 Binding to entity.
VHDL-661 Binding to architecture. The architecture that is selected for
implementing an entity is determined by the
following priority:
1) Root attribute
'hdl_vhdl_preferred_architecture'
2) Configuration specification or component
configuration for current instance of entity
3) Configuration declaration for entity
4) Most recently analyzed architecture for
entity.
VHDLPT-506 Design unit not stored.
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May 2013 48 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
VHDLPT-507 Error limit reached, terminating analysis.
VHDLPT-508 Error summary.
VHDLPT-509 Analyzing file.
VHDLPT-510 The analyzer has suffered an internal error:
terminating.
VHDLPT-514 Design unit stored.
VHDLPT-515 Too many source errors to continue with this
unit.
VHDLPT-525 Continuation.
VLOGPT-657 The reference to the module will be removed
from the design database.
An error occurred during parsing or elaboration
of this module.
VTIM-104 ETS timing report generated successfully. Open the timing report to check for timing
correlation.
VTIM-108 ETS log file generated successfully. Open the log file to check for timing correlation.
WDO-112 The dofile generated by RC v12.20-b004_1 is
compatible with LEC 7.1.
WDO-211 Design has instantiated ChipWare components. If CDN_SYNTH_ROOT is different while
invoking LEC, then uncomment appropriately in
the dofile.
WDO-212 Forcing flat compare.
WDO-222 No logfile has been specified. Default log file would be generated.
WDO-308 Scan out pin is not a output port. Only output ports which are scan out of a scan
chain can be ignored.
WDO-501 The dofile generated is compatible with LEC
version 'lec.07.20-d315' or later.
WDO-600 'Conformal LEC12.1-p100' or later builds is
recommended for verification.
The use of 'Conformal LEC12.1-p100' or later
builds is recommended to get better verification
results.
WMT-1 Command write_mbist_testbench started.
WMT-2 Creation of MBIST testbench(es) complete.
WMT-3 Creation of MBIST testbench(es) did not
complete successfully.
WMT-4 Directory not specified, creating default
directory: ./wmt.
WMT-5 Created the script to execute build_model,
create_embedded_test and write_vectors.
WMT-6 Executing the script to run build_model,
create_embedded_test and write_vectors.
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May 2013 49 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
WMT-10 The write_vectors command completed
successfully. The 1149 testmode is used for
JTAG patterns (production, bypass, diagnostic,
redundancy and bitmap), and the mda testmode
is used for MDA patterns (poweron, burnin).
WMT-11 Directory for generated testbenches not
specified, creating default directory:
mbist_testbench.
WMT-12 If executing simulation using ncsim, add the
following lines to your script to point to the
patterns created by write_mbist_testbench.
WMT-13 If there are ROMs in the design, ensure the
rompath and romcontentsfile keywords are
passed to create_embedded_test via the
'-create_embedded_test_options' keyword.
WMT-14 Created ncsim script for MBIST direct access
patterns.
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May 2013 50 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 51 Product Version 12.2
2
Warning Messages
Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 52 Product Version 12.2
List of Warning Messages
Message-ID Title Help
1801-99 There was a potential problem
while applying power intent of
1801 file.
The power intent of design may not be correct.
1801-100 The specified scenario is currently
not supported.
The power intent of design may not be correct.
1801-199 Detected a potential problem in
1801 power intent file.
The linter has detected a potential problem with 1801
power intent file. The power intent may be incorrect.
CDFG-24 License check failed. Unable to
write CDFG.
CDFG-145 Illegal node in datapath operator
merging.
CDFG-146 Illegal node in required precision
width analysis of graph.
CDFG-147 Illegal node in information content
analysis of graph.
CDFG-148 Illegal node in influence
propagation analysis of graph.
CDFG-149 Illegal influence section type in
influence propagation analysis of
graph.
CDFG-150 Cleanup based on influence
analysis of graph has failed.
CDFG-185 Element width mismatch in
unpacked union.
This may cause verification mismatches between the
original and synthesized designs.
CDFG-217 Signal or variable has multiple
drivers and no loads. This may
cause verification mismatches
between the original and
synthesized designs.
Verify that the drivers of this signal are correct.
CDFG-223 Detected empty range. An empty range occurs in VHDL when the range is of
the form 'L to R', where L > R, or 'L downto R', where L
< R. A port may not have an empty range, and a signal
or variable with an empty range may be assigned to or
indexed.
CDFG-236 Detected non-positive value for
replication prefix.
The prefix expression of a replication generally must
evaluate to a positive constant. The value of a
replication with a non-positive prefix depends on the
setting of the attribute 'hdl_zero_replicate_is_null'. If
true, the replication is treated as a zero-width
expression. If false, the replication evaluates to 1'b0.
Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 53 Product Version 12.2
CDFG-237 Port redeclared with different type
or size.
The type associated with the two declarations of a port
should be identical.
CDFG-239 Incompatible bitwidths in
assignment.
The width of lhs and rhs should be identical.
CDFG-243 Argument size to integer type
conversion is too large.
The expression will be truncated to the bitwidth of the
integral return type.
CDFG-248 Ignored conflicting multiplier
pragmas.
Multipliers merged into a cluster must have the same
type.
CDFG-265 Treated wild equality operator as
ordinary equality.
The SystemVerilog wild equality operators (==? and
!=?) can be synthesized correctly only if the second
argument is a constant. When the second argument
is not a constant, then these operators are
synthesized to ordinary equality (== and !=)
operators. This may produce a mismatch between
synthesis and simulation results.
CDFG-277 Ignored 'hdl_ff_keep_feedback'
and
'hdl_ff_keep_explicit_feedback'
attributes.
When the 'lp_insert_clock_gating' attribute is set to
'true', all flip-flop feedback logic is removed during
'elaborate'.
CDFG-278 Comparison to 'X' always
evaluates to false. This may cause
simulation mismatches between
the original and synthesized
designs.
CDFG-279 Comparison of discrete arrays of
unequal sizes may produce
unexpected results.
CDFG-281 Ignored asynchronous set/reset
pragma.
A signal is connected to the asynchronous set/reset pin
on a latch only if constant 0 or 1 is asynchronously
assigned to the signal associated with the latch.
CDFG-282 Ignored synchronous set/reset
pragma.
A signal is connected to the synchronous set/reset pin
on a flip-flip only if constant 0 or 1 is synchronously
assigned to the signal associated with the flip-flop.
CDFG-284 Invalid use of enum. Enums can only be used for signals and parameters.
CDFG-285 Conflicting enum definitions.
CDFG-287 Index out of bounds. Ensure that the desired index is specified correctly in
the HDL.
CDFG-288 Incompatible array index
constraint.
CDFG-289 Incompatible range constraint.
CDFG-290 Bitwidth mismatch.
CDFG-291 Could not determine case type.
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May 2013 54 Product Version 12.2
CDFG-292 Ignored architecture.
CDFG-293 Detected null array.
CDFG-296 Function may not be assigned a
value in all cases.
For synthesis, a function reg which is not assigned is
set to 0, while in simulation, it retains the value from the
previous call. This may result in a simulation mismatch.
CDFG-297 Invalid value for sub_arch pragma. The sub_arch pragma accepts only the values 'booth',
'non_booth' and 'radix8'.
CDFG-304 No top-level HDL designs to
process.
There are no top-level designs in the /hdl_libraries
directory. This may be caused by:
- all designs are instantiated by another design.
- a top-level Verilog module or VHDL entity has the
template pragma or attribute.
- a top-level VHDL entity has an unconstrained array
port.
CDFG-310 Deleting existing HDL design.
CDFG-311 Ignored attempt to delete primitive
operator.
CDFG-312 Ignored attempt to delete
subprogram.
CDFG-313 Ignored attempt to delete blackbox
or cell.
CDFG-314 Ignored attempt to redefine
primitive operator.
CDFG-315 Ignored attempt to delete design
specified as 'don't modify'.
CDFG-316 Ignored attempt to redefine cell.
CDFG-317 Did not inline instance with empty
input ports.
CDFG-331 Detected a logic abstract. A logic abstract is an unresolved reference with defined
port names and directions. It is inferred from an empty
Verilog or VHDL design, or when the 'black_box'
pragma or 'blackbox' hdl_arch attribute is specified. Use
'set_attribute hdl_infer_unresolved_from_logic_abstract
false /' to treat an empty module as a defined module.
CDFG-332 Detected a logic abstract. A logic abstract is an unresolved reference with defined
port names and directions. It is inferred from a
SystemVerilog extern module declaration or a VHDL
component declaration. Use 'set_attribute
hdl_infer_unresolved_from_logic_abstract false /' to
treat this as a defined module.
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Warning Messages
May 2013 55 Product Version 12.2
CDFG-360 Referenced signal not in sensitivity
list. This may cause simulation
mismatches between the original
and synthesized designs.
CDFG-366 Edge-triggered signal is not in the
sensitivity list of the process.
Therefore, the process will not
execute an implicit wait statement.
This may cause simulation
mismatches between the original
and synthesized designs.
This message indicates that a process contains a signal
that clocks or gates other signals in the process.
However, this signal does not appear in either a wait
statement or the process sensitivity list. In simulation,
this process may cause an infinite loop to occur at time
zero. Synthesis builds the logic described by the
process as if the signal did appear in the process
sensitivity list. The difference in interpretation between
synthesis and simulation may result in a simulation
mismatch.
CDFG-367 Asynchronous assignment within
an edge-triggered block will be
treated as a synchronous
assignment.
CDFG-368 Generated logic differs from the
expected logic.
The logic generated for an always_comb, always_latch
or always_ff process may not match the specified
behavior.
CDFG-370 Type conversion truncates
constant value.
CDFG-371 Real value rounded to nearest
integral value.
CDFG-380 Assignment to input port.
CDFG-381 Signal referenced before it is
assigned. This may cause
simulation mismatches between
the original and synthesized
designs.
CDFG-409 Arguments to primitive instance
must have same size.
CDFG-417 Too few arguments to instance.
CDFG-418 Too many arguments to primitive
gate.
CDFG-419 Only a net expression may be
connected to an output or inout
port.
In standard Verilog, only a net, or a bit-select,
part-select, or concatenation of nets may be connected
to the output or inout port of a module instance.
Connecting a reg will result in a simulation error. This
restriction does not exist in SystemVerilog.
CDFG-422 Unable to group subprogram. The subprogram contains a reference to a global signal
and therefore cannot be grouped into a separate
hierarchy.
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May 2013 56 Product Version 12.2
CDFG-423 Blackbox instantiated from both
VHDL and Verilog. Exact matches
will be used for resolving the
blackbox.
When a blackbox module 'FOO' is instantiated in both
VHDL and Verilog modules, only exact matches will be
used when resolving the blackbox instantiations. If a
module 'foo' is then read in, it will not be used to resolve
instances of 'FOO'.
CDFG-428 Creating blackbox. Blackboxes are represented as unresolved references
in the design. Use 'set_attribute hdl_error_on_blackbox
true /' to cause an error when a blackbox is found.
CDFG-436 Empty port expression.
CDFG-440 Module has both named and
positional ports.
The two types of port definitions should not be mixed;
the ports of a particular module definition should all be
defined by order or all by name.
CDFG-441 Renamed port. A module port is renamed when it conflicts with another
port name. This can happen when a port name is
duplicated in the port list, or when a port of a complex
data type is split into sub-ports, and the name of
sub-port conflicts with an existing port.
CDFG-448 Unspecified port size for array of
blackbox instances.
The 'elaborate' command assumes that if a port size for
an array of blackbox instances is not specified, the port
has the same size as the corresponding port
connection. If this is incorrect, specify the correct size
for the blackbox port.
CDFG-449 There are ports of different
directions in port concat
expression.
CDFG-456 Index expression overflow. A value that is greater than what the index expression
can hold is assigned to the index expression. For
example, a register of 2 bits can hold the range of
values 0 to 3. The following example will cause an
overflow error when index is greater than 3:
reg [1:0] index;
for (index = 0; index < 7; index = index + 1)
...
CDFG-464 Connected signal is wider than
input port.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG-465 Connected signal is wider than
output port.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG-466 Connected signal is wider than
input/output port.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG-467 Input port is wider than connected
signal.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG-468 Output port is wider than
connected signal.
This may cause simulation mismatches between the
original and synthesized designs.
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May 2013 57 Product Version 12.2
CDFG-469 Input/output port is wider than
connected signal.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG-471 Case item expression is not used. This case item expression never matches the case
condition expression.
CDFG-472 Unreachable statements for case
item.
CDFG-473 Case items contain 'don't care' or
'high impedance' values.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG-474 Casez items contain 'don't care'
values.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG-475 Case statement is not parallel but
has the 'parallel' case pragma set.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG-476 Case statement is not full but has
the 'full' case pragma set.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG-477 Case statement with 'one hot', 'one
cold' or 'enum' pragma is not full.
CDFG-480 Ignored redundant case item. When multiple case item expressions match the case
condition, only the statements associated with the first
matching item are considered.
CDFG-481 Ignored duplicate case branch. Ignored the sequential statements associated with this
case branch because all of its case items match the
case condition in previous branches.
CDFG-482 An 'X' or 'Z' value appears in a
comparison expression.
An 'X' or 'Z' value in a comparison statement can cause
a simulation mismatch between the original and the
synthesized designs.
CDFG-483 An interface-type port has no
modport specified.
If no modport is specified in the declaration of an
interface-type port or in the connection of such a port,
then all variables and wires from the interface are
accessible with direction inout. This can result in
multiple drivers to these variables and wires. It is
therefore recommended that all interface-type ports be
used with modports.
CDFG-484 A negative value is used where an
unsigned value is expected.
The value will be interpreted as an unsigned number.
CDFG-485 Loop condition is always false. Loop body will not be synthesized.
CDFG-487 Non-static conditional expression
in 'for' statement.
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Warning Messages
May 2013 58 Product Version 12.2
CDFG-507 Reversing assignment for undriven
signal.
An undriven signal is on the right-hand side of an
'assign' statement, and the signal on the left-hand side
has other drivers. By default, RC assumes 'assign'
statements are bidirectional and reverses the
assignment to drive the undriven signal with the
multiply-driven signal. This may cause a simulation
mismatch between the original and the synthesized
designs. Use 'set_attribute hdl_bidirectional_assign
false /' to prevent bidirectional assignments.
CDFG-508 Removing unused register. A flip-flop or latch that was inferred for an unused signal
or variable was removed. Use 'set_attribute
hdl_preserve_unused_registers true /' to preserve the
flip-flop or latch.
CDFG-552 Instantiation of empty module. Perhaps a simulation module was instantiated by
mistake.
CDFG-556 Library cell has same name as
module.
CDFG-558 Could not find valid
map_to_operator implementation
for call to subprogram.
A legal implementation could not be found for the given
subprogram call from the available set of ChipWare
implementations. The 'map_to_operator' pragma is
being ignored for this call, and it will be treated as a
regular subprogram call by the elaborator.
CDFG-559 Could not find valid
implementation for component
instance.
A legal implementation could not be found for a specific
instance of a ChipWare component from the set of
implementations defined for the component. The
instance will be treated as a blackbox.
CDFG-562 Input port connected to output
instance port.
CDFG-563 Connecting actual to multiple
formal ports.
A port of a complex type (record, struct, interface, or
multidimensional array) is broken up into sub-ports
during synthesis. When instantiating a synthesized
netlist with such ports in a bottom-up flow, elaborate
attempts to match the sub-ports to the elements of the
complex type port in the instantiating module.
CDFG-564 Connecting actual to multiple ports
of cell.
A connection has been made between a vector net in
the rtl and a bit-blasted collection of pins of a library
cell.
CDFG-566 No actual corresponding to
wildcard port; will be left
unconnected.
In a module instance using '.*' notation, it is not
necessary to have a matching signal in the instantiating
module for every unconnected port of the instantiated
module. When there is no matching signal, the
corresponding port is left unconnected.
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Warning Messages
May 2013 59 Product Version 12.2
CDFG-600 Illegal value for attribute
'hdl_parameter_naming_style'.
The 'hdl_parameter_naming_style' attribute value must
include zero or one instances of '%s' to represent the
parameter name and exactly one instance of '%d' to
represent the parameter value. For example,
'set_attribute hdl_parameter_naming_style "_%s_%d"'.
CDFG-602 Illegal value for attribute
'hdl_array_naming_style'.
The 'hdl_array_naming_style' attribute value must
include one instance of '%s' to represent the variable
name and one instance of '%d' (in order) to represent
the bit number. For example, 'set_attribute
hdl_array_naming_style "%s[%d]"'.
CDFG-603 Illegal value for attribute
'hdl_record_naming_style'.
The 'hdl_record_naming_style' attribute value must
include one instance of '%s' to represent the variable
name and one instance of '%s' to represent the field
name. For example, 'set_attribute
hdl_record_naming_style "%s[%s]"'.
CDFG-604 Illegal value for attribute
'hdl_generate_index_style'.
The 'hdl_generate_index_style' attribute value must
include zero or one instances of '%s' to represent the
generate label and exactly one instance of '%d' to
represent the generate index value. For example,
'set_attribute hdl_generate_index_style "%s[%d]"'.
CDFG-605 Illegal value for attribute
'hdl_instance_array_style'.
The 'hdl_instance_array_style' attribute value must
include zero or one instances of '%s' to represent the
instance label and exactly one instance of '%d' to
represent the array index value. For example,
'set_attribute hdl_instance_array_style "%s[%d]"'.
CDFG-606 Illegal value for attribute
'hdl_bus_wire_naming_style'.
The 'hdl_bus_wire_naming_style' attribute value must
include one instance of '%s' to represent the wire name
and one instance of '%d' to represent the bit number.
For example, 'set_attribute hdl_bus_wire_naming_style
"%s[%d]"'.
CDFG-745 Common subexpression not
eliminated.
CDFG-746 Ignored 'map_to_mux' pragma due
to FSM extraction.
The 'map_to_mux' pragma is used with a 'case'
statement that is part of an extracted finite state
machine.
CDFG-748 No datapath license available.
Operator merging will not be done.
CDFG-751 Ignored 'map_to_mux' pragma due
to constant data inputs.
The 'map_to_mux' pragma is used for a signal that is
only assigned constant values. The logic is
implemented with AND and OR gates rather than a
multiplexer so that efficient logic optimization
techniques can be applied.
CDFG-756 Bit-select index out of bounds for
CDFG node.
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Warning Messages
May 2013 60 Product Version 12.2
CDFG-760 Invalid carrysave signal. Operator
cannot produce carrysave output.
CDFG-761 Invalid carrysave signal. Operator
cannot accept carrysave input.
CDFG-762 Invalid carrysave signal. Signal is
unsigned and operator is signed.
CDFG-763 Invalid carrysave signal due to
truncation followed by extension.
CDFG-764 Invalid carrysave signal. Operator
size is less than the threshold (four
bits), and the downstream
operator is a multiplier.
CDFG-765 Invalid carrysave signal. Multiplier
cannot have two carrysave inputs.
Multiplier implementations are inefficient when both
inputs are carrysave.
CDFG-766 Invalid carrysave signal. Operator
represents a trivial carrysave sum.
CDFG-801 Case statements marked with a '*'
may cause simulation mismatches
between the original and
synthesized designs.
A 'full' or 'parallel' case pragma is used with a case
statement in which not all cases are covered or some
case items overlap.
CDFG-811 Port connection width mismatch.
CDFG-812 Ignored architecture because it is
not applicable to any operator in
the instance.
CDFG-814 Linking to Physical only cell in
absence of timing library. Paths
involving these cells will not be
timed.
Read in .lib file for timing information.
CDFG-818 Using default parameter value for
module elaboration.
CDFG2G-207 Unsupported datapath operation.
CDFG2G-216 Illegal value for attribute
'hdl_reg_naming_style'.
The 'hdl_reg_naming_style' attribute value must include
one instance of '%s' to represent the name of the
variable for which the flip-flop or latch was inferred and
one instance of '%s' to represent the bit number as
specified by the 'hdl_array_naming_style' attribute if the
variable is a vector. For example, 'set_attribute
hdl_reg_naming_style "%s_reg%s"'.
CDFG2G-217 Preserving 'keep_signal_name'
signal.
Better results may be possible if the
'keep_signal_name' pragma is removed.
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Warning Messages
May 2013 61 Product Version 12.2
CDFG2G-607 Ignored 'map_to_mux' pragma due
to excessive mux size.
The 'map_to_mux' pragma specifies that a multiplexer
with 2^n data inputs be used to implement the 'case'
statement logic, where 'n' is the width of the 'case'
condition. When 'n' exceeds the
'hdl_max_map_to_mux_control_width' attribute value,
the logic is implemented with AND and OR gates rather
than a multiplexer. Increase the
'hdl_max_map_to_mux_control_width' attribute value to
implement a multiplexer.
CDFG2G-608 Accessed non-constant signal
during asynchronous set or reset
operation.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG2G-610 Accessed non-constant signal
during synchronous set or reset
operation.
Better results may be possible if the logic is
implemented using the flip-flop data pin rather than the
set and reset pins. To use the data pin, remove the
'sync_set_reset' attribute or pragma that affects this
assignment.
CDFG2G-611 Could not create carrysave
operation.
The $carrysave function input expression cannot be
implemented with carrysave arithmetic operations and
is instead in binary format. The $carrysave function
output is a zero extension of the input expression.
CDFG2G-612 Ignored 'map_to_mux' pragma due
to lack of library mux cells.
To map to a mux, either load a library with a mux cell
that is not specified 'dont_use', or set the 'avoid'
attribute of a library mux cell to 'false' prior to
'elaborate'.
CDFG2G-613 Ignored 'map_to_mux' pragma due
to non-mux behavior.
The logic is implemented with AND and OR gates
rather than a multiplexer. The 'map_to_mux' pragma is
ignored when, for example, some case items are not
covered, overlap, or are not constant, or the assigned
signal fans out to flip-flop or latch set or reset pins.
CDFG2G-614 Pragma 'map_to_mux' is not
recommended for some bits of
signal.
Better results may be possible if the 'map_to_mux'
pragma is not specified for this statement.
CDFG2G-615 Generated logic differs from the
expected logic.
The logic generated for an always_comb, always_latch
or always_ff process may not match the behavior
specified in the input HDL.
CDFG2G-618 Deleted transparent (always
enabled) latch.
Use 'set_attribute hdl_delete_transparent_latch false' to
preserve transparent latches during 'elaborate'.
CDFG2G-619 Preserved transparent (always
enabled) latch.
This latch will be deleted during 'synthesize'. Use
'set_attribute hdl_delete_transparent_latch true' to
delete transparent latches during 'elaborate'.
CDFG2G-620 Module already exists. The referenced module will not be generated again.
CDFG2G-621 SystemVerilog variable has
multiple concurrent or sequential
drivers.
SystemVerilog variables can be written by one or more
sequential statements or one concurrent assignment or
one port.
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Warning Messages
May 2013 62 Product Version 12.2
CDFG2G-622 Signal or variable has multiple
drivers.
This may cause simulation mismatches between the
original and synthesized designs.
CDFG2G-623 Signal or variable has multiple
drivers, including a constant driver.
Some tools may not accept this HDL.
CDFG2G-625 Connected a power or ground
positional port.
RC assumes that power and ground port connections
are listed last for positional instantiations, and are
connected in the order that the power and ground pins
are specified in the cell library.
CG_CLONE-104 Flops list is not valid for clock
gating cloning.
CG_CLONE-105 Flops and clock gating instance
are not in the same hierarchy.
Clock gate cloning is not supported for hierarchical
clock gates.
CG-102 The requested clock-gating cell
type does not exist.
You can only request observability logic if you also
requested test-control logic. If
'lp_clock_gating_add_obs_port' is set to 'true', you must
set 'lp_clock_gating_control_point' to either 'precontrol'
or 'postcontrol'.
CG-202 Cannot insert observability logic. Observation logic is inserted based on clock
information. The clock information is required because
only clock-gating logic driven by the same clock can
share an observability flip-flop. The clock information
can be derived from clock constraints or from the
physical connectivity. To insert the observation logic
based on clock constraints, define the clocks using the
'define_clock' command, then rerun the 'clock_gating
insert_obs' command. To insert the observation logic
based on physical connectivity, invoke the 'clock_gating
insert_obs' command with the
'-ignore_clock_constraint' option.
CG-203 Failed to insert observability logic. No RC inserted clock-gating instances found in the
instances not excluded by the exclude option.
CG-204 Failed to insert observability logic. You must set 'lp_clock_gating_add_obs_port' to 'true',
before inserting clock gating in the design, to select
clock-gating logic that contains observability logic. Then
rerun the 'clock_gating insert_obs' command.
CG-206 Failed to insert observability logic. The '-max_cg' option of the 'clock_gating insert_obs'
command specifies the maximum number of
clock-gating cells that can be observed per
observability flip-flop. Specify a number between 1 and
32.
CG-208 Failed to insert observability logic. Define the test signal using the 'define_dft test_mode'
or the 'define_dft shift_enable' command. Set the
'lp_clock_gating_test_signal' attribute. Then rerun the
'clock_gating insert_obs' command.
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Warning Messages
May 2013 63 Product Version 12.2
CG-212 Failed to insert observability logic
for clock-gating logic.
Observability logic cannot be inserted in an instance if
part of its hierarchy is marked preserved. To ensure the
insertion of observability logic, set the 'preserve'
attribute to 'false' on the subdesign or instance that was
reported preserved, then rerun the 'clock_gating
insert_obs' command.
CG-302 No shared clock-gating logic
inserted.
CG-303 The clock-gating instance will not
be considered for share operation.
CG-401 Could not find any design. Unable
to remove clock-gating.
CG-404 Could not remove clock-gating
logic.
To remove all clock-gating logic in the hierarchy, use
'clock_gating remove -hier'. If this fails, either the design
did not contain any clock-gating logic, or you removed
the clock-gating logic previously.
CG-405 Could not remove clock gating
instance.
The specified clock gating instance gates a flop which is
either marked preserved or is connected to a net
marked preserve. To remove the clock gating instance
you would first need to remove the preserve status of
the flop or the net.
CG-407 Failed to remove observability
logic.
Found no observability logic under current hierarchy.
CG-408 Removed observation flip-flop
from scan chain.
When removing an observation flip-flop from a scan
chain, that scan chain becomes disconnected. To
reconnect the scan chains, use the
'connect_scan_chains' command.
CG-409 Combinational logic at the gated
clock of clock-gating instance too
complex for 'clock_gating remove'
to handle.
'clock_gating remove' can only work on trivial
combinational logic, consisting of inverters and buffers
in the fanout of the gated clock, when the clock-gating
instance and the flops that it is driving are in the same
hierarchy. For more complex logic, 'clock_gating
remove' would not be attempted.
CG-410 Cannot remove a multi-stage
clock-gating instance.
Currently, only leaf-level clock-gating instances can be
removed.
CG-411 Cannot remove clock-gating
instance which is preserved.
To remove preserved clock-gating instances, first
unpreserve them.
CG-412 Cannot remove clock-gating
driving flops with opposite edges.
A positive-edge controlled clock-gating instance cannot
be removed if it is driving negative-edge triggered flops,
and a negative-edge controlled clock-gating instance
cannot be removed if it is driving positive-edge triggered
flops.
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Warning Messages
May 2013 64 Product Version 12.2
CG-413 Cannot remove clock-gating
instance, which is not driving flops.
'clock_gating remove' does not remove clock-gating
instances, which either do not drive any flops or drive
instances other than flops, such as - black-boxes,
latches, etc.
CG-414 Cannot remove clock-gating
instance, which is driving generic
flops.
CG-415 Cannot remove clock-gating
instance, which has a
synchronous set/reset pin.
Currently, only clock-gating instances, which do not
have a synchronous set/reset pin, can be removed.
CG-416 Could not remove clock-gating
instance.
To remove the clock-gating instance you first need to
change the preserve status of the net.
CG-417 Cannot remove clock-gating
instance.
The clock-gating instance gates flops with synchronous
reset. Currently only clock-gating instances, which are
not gating any flops with synchronous reset, can be
removed.
CG-418 Cannot remove a negative-edge
controlled clock-gating instance,
which has a constant 0 connected
to its enable pin.
CG-419 Cannot remove clock-gating
instance, which is driving scan
flops that are being used as
regular flops.
'clock_gating remove' can only remove clock-gating
instances driving scan flops, which are not used as
regular functional flops.
CG-420 Cannot remove clock-gating
instance, which is driving flops in a
scan chain.
'clock_gating remove' can only remove clock-gating
instances driving scan flops, which are not connected in
a scan chain.
CG-421 Cannot remove clock-gating
instance, which is driving scan
flops that do not have a unique
data pin.
CG-422 Cannot remove clock-gating
instance, which is driving flops that
do not have a unique data pin.
To remove such clock-gating logic, invoke the
'clock_gating remove' command in high effort mode
using the '-effort high' option.
CG-423 Cannot remove clock-gating
instance, which is driving flops that
do not have a unique data pin.
CG-424 Cannot remove clock gating
instance.
The command 'clock_gating remove -flops' is ignored
for the specified flop because there is no logic to be
removed.
CG-425 Complex logic other than inverters
and buffers found between the flop
and the CG; The CG for this flop
will not be removed.
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Warning Messages
May 2013 65 Product Version 12.2
CG-427 Could not remove clock gating
instance.
The specified clock gating instance drives a clock
gating cell which is either marked preserved or is
connected to a net marked preserve. To remove the
clock gating instance you would first need to remove the
preserve status of the clock gating cell or the net.
CG-601 Failed to uniquify the design. Parent module of a Clock-Gating instance is preserved.
It cannot be uniquified.
CG-602 Failed to uniquify the design. An Instance is preserved. Its parent module cannot be
uniquified.
CG-603 Failed to uniquify the design.
CHECK_CWD-101 No Input pin for the hdl_operator
defined.
CHECK_CWD-102 No Output pin for the hdl_operator
defined.
CHECK_CWD-103 No hdl_operator has binding
whose avoid attribute is false.
CHECK_CWD-105 The file specified by the location
attribute of hdl_comp is not set
correctly.
CHECK_CWD-106 The file specified by the
sim_model attribute of hdl_comp is
not set correctly.
CHECK_CWD-110 The default_location attribute for
the hdl_pack is set to empty.
CHECK_CWD-127 The hdl_operator output pin is
associated with any output pin of
the component.
CHECK_CWD-130 Bit_width attribute for the output
pin has set to empty.
CHECK_CWD-149 The column name specified with
-max_width option does not match
a valid list register check column
name. Ignoring the user specified
width for the column.
The option -max_width is used to control the width of
the various columns in list register output. The valid
columns names are Checkpoint_name Check_name
Effort Description.
CHECK_CWD-157 There is no vdir present under the
present working directory.
The present working directory specified is not a valid
vdir or there is no vdir present under present working
directory.
CHECK_CWD-159 There is no argument specified
with report_check command.
For the correct usage of report_check see the help
message below and specify the correct argument.
CHKLIB-701 No libraries are loaded.
CHKLIB-702 Libcell cannot be reported.
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Warning Messages
May 2013 66 Product Version 12.2
CHKLIB-703 Libcell cannot be reported.
CHKLIB-704 Libcell cannot be reported.
CHKLIB-705 Libcell cannot be reported.
CHKLIB-706 Libcell cannot be reported.
CHKLIB-707 Libcell cannot be reported.
CHKLIB-708 Libcell cannot be reported.
CHLNK-104 Pin not found in the new instance. Some exceptions might get lost.
CHLNK-105 Instance not found in the new
instance.
Some exceptions might get lost.
CHLNK-301 An instance does not have a
dedicated subdesign.
Change link will uniquify the subdesign.
CHLNK-302 Pin left unconnected.
CHNM-100 Failed to change names. Could not change names.
CHNM-101 Failed to change names. Could not change names.
CHNM-103 Cannot rename an object to the
desired name.
CHNM-104 -append_log option is used along
with -log_changes.
CHNM-105 -name_collision cannot be used
without prefix or suffix.
CHNM-106 Object specified is not a
hierarchical instance.
CHNM-110 Failed to change names.
CPF_ISO-101 Cannot define isolation rule. Power domains are not created.
CPF_ISO-106 Multiple enable drivers are
specified.
CPF_ISO-110 No isolation rules defined. To insert isolation cells, use 'create_isolation_rule' in
CPF.
CPF_ISO-111 Cannot define isolation rule as rule
with given name already exists.
CPF_ISO-114 Cannot clone port for applying
isolation rule.
Isolation rule will not be applied at this pin.
CPF_ISO-115 Isolation rule not defined. Pins listed in the rule are also excluded.
CPF_ISO-116 Cannot define isolation rule as
instance given with
'-within_hierarchy' is unresolved
instance.
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Warning Messages
May 2013 67 Product Version 12.2
CPF_ISO-118 Cannot insert isolation on macro
pin.
Isolation rule has no within_hierarchy specified with it.
CPF_ISO-206 Skipping enabled level shifter
insertion.
No appropriate enabled level shifter is available.
CPF_ISO-207 Skipping level shifter insertion. No appropriate level shifter is available.
CPF_ISO-208 Skipping isolation cell insertion. No appropriate isolation cell is available.
CPF_ISO-209 Cannot proceed with isolation and
level shifter insertion.
Power domains are not created.
CPF_ISO-210 Cannot insert isolation or level
shifter cell.
Isolation and level shifter cells cannot be inserted on
pins inside level shifter hierarchy.
CPF_ISO-211 Cannot insert isolation or level
shifter cell.
Isolation and level shifter cells cannot be inserted on
pins inside isolation hierarchy.
CPF_ISO-212 Cannot insert isolation or level
shifter cell.
Isolation and level shifter cells cannot be inserted on
pins inside clock gating hierarchy.
CPF_ISO-213 Cannot insert isolation or level
shifter cell.
Isolation and level shifter cells cannot be inserted on
pins inside operand isolation hierarchy.
CPF_ISO-216 Cannot insert isolation or level
shifter cell.
Power domain of pin and the parent where isolation and
level shifter cells are being put should match.
CPF_ISO-219 Cannot insert isolation or level
shifter cell.
Power domain of '-within_hier' must be same as
equivalent to 'from' or 'to' domain, depending upon the
location. To skip this test, set
'lp_skip_pd_equivalence_check' to 1.
CPF_ISO-222 Reversing the level shifter and
isolation ordering.
Level shifter and isolation cell order changes with
isolation cell first followed by level shifter if the variable
'cpf_reverse_level_shifter_isolation_order' is set to 1.
User needs to check the proper secondary domain
setting with the corresponding isolation rule in the CPF.
CPF_ISO-223 Back to back level shifter detected. Back to back level shifter is not supported in RC.
CPF_ISO-303 Secondary domain is reassigned
to the low power instance.
The low power instance is covered in multiple
'identify_secondary_domain' cpf command.
CPF_ISO-304 '-from' / '-to' options are ignored.
CPF_ISO-305 Not a low power cell instance.
CPF_ISO-306 Base domain not assigned to
power domain.
CPF_ISO-307 Multiple base domains are
assigned to power domain.
Explicitly assign the secondary domain to the low power
instance.
CPF_ISO-308 Instance specified is not a valid
state retention instance.
CPF_ISO-309 Instance specified is not a valid
isolation cell instance.
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Warning Messages
May 2013 68 Product Version 12.2
CPF_ISO-310 Enable pin of the isolation cell
instance is undriven.
CPF_ISO-311 Instance specified is not a valid
always on cell instance.
CPF_ISO-312 Instance specified is not a valid
power switch cell instance.
CPF_ISO-313 Instance specified is not a valid
level shifter cell instance.
CPF_ISO-314 Data pin of the low power cell
instance is undriven.
CPF_ISO-315 Output pin of the low power cell
instance is not driving any load.
CPF_ISO-316 Could not assign default
secondary domain for the low
power instance.
CPF_ISO-317 Low power instance is driven by
level shifter.
CPF_ISO-318 Back to back level shifter detected. Either the base domain of the primary power domain of
the level shifter instance will be considered as
secondary domain of the level shifter instance, or the
primary power domain itself.
CPF_ISO-801 Prefix conflicts with existing rule. The prefixes of level shifter rules and isolation rules
should be unique independently.
CPF_ISO-902 Failed to swap ICG with
ICG-Retention cell.
CPF_ISO-903 Retention pin of the ICG-Retention
instance not connected.
Provide 'default_save_edge' for the power domain.
CPF_ISO-905 Failed to swap ICG with
ICG-Isolation cell.
CPF_ISO-906 Isolation pin of the ICG-Isolation
instance not connected.
Provide 'default_isolation_condition' for the power
domain.
CPF_ISO-907 'default_save_edge' is not defined
for power domain. No swapping
will be done for the clock gating
instance.
CPF_ISO-908 'default_isolation_condition' is not
defined for power domain. No
swapping will be done for the clock
gating instance.
CPF_ISO-911 Cannot perform port cloning
required for respecting
'-within_hierarchy' option.
For inserting LS/ISO in hierarchy given with
'-within_hierarchy', the required cloning of pins is not
possible.
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Warning Messages
May 2013 69 Product Version 12.2
CPF_ISO-913 Voltage specified with nominal
condition and library domain are
not matching.
For level shifter insertion, voltage specified in the CPF
file will take higher priority.
CPF_LS-801 Cannot insert level shifters. Power domains are not created.
CPF_LS-803 No level shifter rules defined. To insert level shifters, use 'create_level_shifter_rule' in
CPF.
CPF_LS-804 Cannot define level shifter rule. Either 'to' or 'from' acceptable for location in level shifter
rule.
CPF_LS-805 Cannot define level shifter rule as
an unacceptable option is given
with '-threshold'.
In a level shifter rule, '-from_power_domain',
'-to_power_domain', '-cpf_pins', '-exclude_pins' are not
accepted in combination with '-threshold' option.
CPF_LS-806 Cannot define level shifter rule as
'direction' is specified without
'threshold.
For level shifter rule definition, '-direction' can be given
only when '-threshold' is provided.
CPF_LS-807 Cannot define level shifter rule. One of 'up', 'down' or 'both' are acceptable for direction
in a level shifter rule.
CPF_LS-808 Cannot define level shifter rule as
rule with given name already
exists.
CPF_LS-811 Cannot clone port for applying
level shifter rule.
Level shifter rule will not be applied at this pin.
CPF_LS-812 Level shifter rule not defined. Pins listed in the rule are also excluded.
CPF_LS-813 Cannot define level shifter rule as
instance given with
'-within_hierarchy' is unresolved
instance.
CPF_LS-815 Cannot insert level shifter on
macro pin.
Level shifter rule has no within_hierarchy specified with
it.
CPF_LS-913 Voltage specified with nominal
condition and library domain are
not matching.
For level shifter insertion, voltage specified in the CPF
file will take higher priority.
CPF_SYNTH-102 No usable always on buffer is
available.
CPF_SYNTH-103 No usable buffer is available.
CPF-99 Attempting to read CPF in a CPF
enabled design.
Reading CPF for a design multiple times is not
supported and can corrupt power intent.
CPF-150 Specified top design and top
design in CPF do not match.
The design specified with '-design' option does not
match with the design name of first 'set_design'
command of CPF file.
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Warning Messages
May 2013 70 Product Version 12.2
CPF-151 Subdesign and current scope do
not match.
The value specified with the 'set_design' CPF command
does not correspond to the subdesign (module) name
of the hierarchical instance specified with the preceding
'set_instance' CPF command.
CPF-199 Detected a warning from CPF
linter.
CPF linter has detected a potential problem with CPF
file. The power intent may be incorrect.
CPF-203 A CPF command has been
ignored.
The specified CPF command has been ignored and will
have no effect.
CPF-204 Could not find a design object. Ensure that the object name is correct.
CPF-205 Overwriting a previous CPF
definition.
In CPF, the last command specification prevails. To
avoid this behavior, remove the duplicate command.
CPF-206 Detected an invalid expression. An invalid expression was specified. Refer to CPF
reference manual on valid expression syntax.
CPF-207 The specified expression cannot
be synthesized.
CPF-292 Removing previously loaded
libraries.
It is recommended to use the same libraries for
elaboration as listed in the CPF file by loading them
using the 'read_cpf -library' command.
CPF-303 A pin in macro definition is
missing.
Ensure that pin name in macro definition is correct.
CPF-341 Could not find a pin for a cell. The specified cell will not be processed.
CPF-342 Could not find the specified library
cells.
Make sure that the specified cell names are correct or
that the library containing the cells was specified in the
CPF file.
CPF-391 Specified voltage not in inferred
voltage range of library set.
Make sure that the voltage specified in the
'create_nominal_condition' CPF command and the
library set specified in the 'update_nominal_condition'
CPF command are correct.
CPF-401 Removed previously read timing
constraints.
You can associate timing constraints with each power
mode using the CPF 'update_power_mode' command.
CPF-402 Activity file format not supported. Supported file formats are TCF, VCD and SAIF. The
format of activity file is derived from its extension.
CPF-560 An instance is ignored in power
domain specification.
Only hierarchical or timing-model instances are
supported.
CPF-561 A pin is ignored in power domain
specification.
Only primary ports and pins of a timing-model instance
or an unresolved instance are supported.
CPF-565 Unused message.
CPF-566 Unused message.
CPF-567 Unused message.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 71 Product Version 12.2
CPF-568 Design not CPF enabled. 'commit_cpf' works for designs for which CPF file has
been read.
CTP-1 A clock is driving a non-clock input
on a sequential instance.
The pin will be treated as a non-timed capacitive load.
CTP-3 A branch of fan-out of a clock does
not drive any clock inputs.
The pin will be treated as a non-timed capacitive load.
CTP-4 The clock cannot be traced
backward through an instance.
The driver will be treated as a clock source.
CTP-5 The clock drives an unsupported
sequential instance.
Its clock pin will be treated as a non-timed capacitive
load.
CTP-6 No usable clock buffers were
specified with the
lp_clock_tree_buffers attribute.
A subset of the buffers in the available library will be
used.
CTP-7 An unusable clock buffer was
specified.
The cell will be ignored.
CTP-10 A combinational loop was detected
in the clock network.
The timing through the break point will be ignored.
CTP-11 A flop libcell is lacking an internal
power arc on its clock pin.
The power will be assumed to be zero. If this is
incorrect, the result may be undesirable.
CTP-12 No usable clock gating cells were
found in the library.
Discrete components will be used to estimate clock
gate power and timing.
CTP-15 A reconvergent path exists, but
some fan-out flops are not
common to all branches.
Clock skew estimates may be incorrect across this
point.
CTP-16 Discrete clock gate modules with
multiple levels of logic are
incompletely supported.
Power and timing estimates may be affected.
CTP-18 Ignoring disabled hierarchical
clock gating.
Removing false values from
lp_clock_gating_hierarchical root, design, or subdesign
attributes will quiet this warning.
CTP-20 A clock period in the clock tree
specification file is different a
previously defined period value.
The original period will be kept.
CTSTCH-1 Found unknown keyword while
parsing CTSTCH file.
The unknown keyword will be ignored.
CTSTCH-6 Unrecognized libcell. A libcell referenced in the clock specification file was not
recognized.
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Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 72 Product Version 12.2
CWD-5 Case mismatch between the
actual and the specified package
names.
Some commands, such as the 'hdl_create *'
commands, tolerate case mismatches between the
specified name and the actual name of HDL objects.
But other commands, such as, 'ls', 'cd', 'find',
'set_attribute', 'get_attribute' etc., will not work if the
specified name differs in case from the actual object
name.
CWD-6 The synthesis model for the
implementation overridden by
design module of the same name.
While building a ChipWare implementation for a given
set of parameters, if the tool finds a previously built
design module with the same name as the
implementation, then the tool binds that module as the
synthesis model for the implementation. No further
attempt is made to build the model specified via the
'location' attribute of the implementation. If this is not
the expected behavior, then the design module should
be renamed so that its name does not match the name
of the implementation's synthesis model.
CWD-7 The preferred component attribute
will not be honored.
The 'preferred_comp' attribute setting of the specified
'label' pragma will be ignored. The tool will try to build
an alternate implementation for the operator or function
call.
CWD-8 The preferred implementation
attribute will not be honored.
The 'preferred_impl' attribute setting of the specified
'label' pragma will be ignored. The tool will try to build
an alternate implementation for the operator or function
call.
CWD-15 Failed to find a valid synthetic
operator binding.
A call to an HDL subprogram that is mapped to a
synthetic operator via the 'map_to_operator' pragma
could not be replaced by a ChipWare component during
elaboration. This happens when either no binding exists
for the synthetic operator or when none of the specified
binding for the synthetic operator is valid for the given
call.
CWD-23 Found an input or inout pin with no
drivers.
CWD-24 No implementations exist for
component.
A valid implementation cannot be selected for the given
ChipWare component since no implementation has
been specified for it. Use 'hdl_create implementation'
command to specify an implementation in the
component vdir.
CWD-31 Implementation with the given
name does not exist.
CWD-32 The preferred implementation
attribute will not be honored.
The 'preferred_impl' attribute setting of the specific
instance will be ignored. The tool will try to build an
alternate implementation for the instance.
CWD-38 The synthetic operator already
exists.
The attempt to re-define the definition of an existing
operator was ignored.
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Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 73 Product Version 12.2
CWD-39 The pin already exists. The attempt to re-define the definition of an existing pin
was ignored.
CWD-40 The component already exists. The attempt to re-define the definition of an existing
component was ignored.
CWD-41 The parameter already exists. The attempt to re-define the definition of an existing
parameter was ignored.
CWD-42 The binding already exists. The attempt to re-define the definition of an existing
binding was ignored.
CWD-43 The implementation already exists. The attempt to re-define the definition of an existing
implementation was ignored.
CWD-48 The ChipWare component is being
obsoleted.
Support for the given ChipWare component will be
discontinued in a future release.
CWD-49 The ChipWare implementation is
being obsoleted.
Support for the given ChipWare implementation will be
discontinued in a future release.
DATABASE-103 The database contains a field that
the reader does not support.
DATABASE-107 While reading the database, an
attribute was not found.
DATABASE-108 While reading the database, an
attribute could not be set.
DATABASE-109 The database was written with a
different version.
In production, read and write databases with the very
same version of the product.
DATABASE-118 While reading the database, an
item was expected but not found.
DFM-200 No instance probability defined. There is no defined instance probability in the
coefficient file.
DFM-203 Missing library cell. A cell defined in the coefficient file could not be found in
the libraries directory.
DFT_GUIDELINE-401 Test clock signal propagates to
tristate pin.
Enable pin of tristate instance is driven by test clock, to
control the enable pin create a mask of the clock signal
using the test mode signal.
DFT_GUIDELINE-402 Clock signal propagates to EN pin
or D pin.
Correct the circuit and ensure that the test clock should
not propagate to data or enable pin of flop.
DFT_GUIDELINE-403 Test object is driven by different
phase of same clock source.
Ensure that the same phase of clock is propagating to
the flops or macro's (test object) else it will effect during
examination.
DFT_GUIDELINE-404 Clock gating integrated instance is
not in clock path.
Replace the CGIC by any other combinational circuit
cell or treat the CGIC cell as blackbox as the CGIC
(clock gating integrated cell) is not in clock path.
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Warning Messages
May 2013 74 Product Version 12.2
DFT_GUIDELINE-405 Clocks of a multi port macro are
driven by multi test clock.
Correct the circuit and ensure that the same test clock
is propagating to multi clock port of macro otherwise
there would be timing margin design problem.
DFT_GUIDELINE-406 Reference clock of 'pll' is not
driven by primary reference clock.
Real rate test using 'pll' cannot be performed, as its
reference clock is not driven by primary reference clock.
Correct the circuit to make it controllable.
DFT_GUIDELINE-411 Reset pin of 'pll' is not driven by
the primary reset pin.
The real rate test using 'pll' clock cannot be performed,
as its reset pin is not driven by primary reset pin.
Correct the circuit.
DFT_GUIDELINE-412 Same test clock is
re-convergence.
It is a converged clock which generated from a master
test clock source. The master test clock may be
propagated to the inputs of a combinational logic, as a
result of that the converged clock generated.
DFT_GUIDELINE-413 The primary clock is not passes
through 'pll'.
The primary reference clock should propagate to any
sequential element through 'pll'.
DFT-104 Ignored test signal definition. A test signal definition can be safely ignored if another
signal with same name, port and active value already
exists.
DFT-108 Removed scan segment.
DFT-109 Removed scan segment/chain
element.
An element was removed from a scan segment or scan
chain during optimization. To prevent that an element is
removed during optimization, set the 'preserve' attribute
to 'true' on this element.
DFT-110 No source available. A DFT clock has no source (driving pin), and hence, it
will not be used. The source pin may have been
renamed, or removed during a previous synthesis
operation.
DFT-111 Modified the clock path. A testpoint inserted in the clock path can adversely
affect the timing of the design.
DFT-113 Cannot fix TDRC violation. Some types of Test Design Rule Check (TDRC)
violations cannot be fixed. Undriven clock pins and
undriven asynchronous set or reset pins are considered
design errors. They cannot be fixed automatically.
Currently, clock violations reported for the clocked
LSSD scan style cannot be fixed.
DFT-115 Uniquifying design. A DFT operation requires the design to be uniquified.
DFT-117 Detected an already used scan
data input.
The specified scan data input (SDI) is already used as
input for another scan chain. Although acceptable, this
practice is not common and might indicate a
specification mistake.
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May 2013 75 Product Version 12.2
DFT-122 Removed empty scan segment. A floating, fixed, or preserved segment is empty if it has
no (zero) elements. An abstract segment is empty if
either of its two elements (SDI or SDO) is deleted. A
shift-register segment is empty if it has less than two
flops.
DFT-126 Invalid string. The string given is not a valid choice. Check the
command/attribute help for set of valid values.
DFT-127 Ignored option. A given option can be safely ignored.
DFT-129 Changed default shift enable
signal.
The default shift enable (SE) signal has changed. The
default SE is used to connect scan chains for which no
chain-specific shift-enable signal has been defined (see
the define_dft scan chain command).
DFT-136 Redefined a tool-defined test
mode signal.
If a test-mode signal was defined by the tool during DFT
rule checking, you can redefine this signal as a shift
enable signal.
DFT-137 Irrelevant test signal for current
scan style.
Nevertheless creating the test signal.
DFT-153 Option -lockup_element does not
apply to the current scan style.
The current scan style does not use terminal lockup
elements. The information is stored with the defined
scan_chain object, but is ignored during scan
connection if the scan style remains the same. If at the
time of scan connection the scan style allows terminal
lockup elements, the option will be honored.
DFT-158 Driver for a test pin is an internal
node.
DFT-160 Generating incomplete ATPG file
due to definition of internal
test-signal.
Test related signals are expected to be controllable from
the top module ports to write out a valid ATPG file Test
related objects are test_clocks, test_signals, scan-data
input and output signals. You need to update the ATPG
file with initialization sequence to access the internal
test pins.
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Warning Messages
May 2013 76 Product Version 12.2
DFT-161 Since no core-side hookup pin was
identified on the core side of the
pad, the test mode signal may not
be used for any connection.
For bidirectional pad cells, the core side pin of the pad
instance is used to make the connection to the
core-level logic. When the core-side pin of the pad
instance cannot be determined - such as in case of
complex pad cells - the signal cannot be used to
connect to DFT logic. To resolve this issue, manually
inspect the PAD instance to determine if it has both
input-enable (IE) and output-enable (OE) control pins. If
the IE pin is floating, you must edit the netlist and tie off
the pin to the appropriate logic value as to enable the
pad to to-core path by reviewing the to-core pin function
in the libcell description. If the OE pin is not controlled in
test_mode, you can respecify the test_mode constraint
with the '-configure_pad' option. Otherwise, identify test
mode using the '-hookup_pin' option to the appropriate
core side of pad pin, or use a different pin as test mode
pin.
DFT-162 A test point without -cfo option is
assumed to be an
observation-only test point.
Without a CFO pin, a test-point cannot control a net and
hence must be an observation test point. Make sure
that a correct test point is being specified.
DFT-166 Cannot define waveform for the
specified test clock.
Determine if the internal test clock can be traced back
to a primary input pin. If so, the test clock waveform for
the internal clock is derived from the root clock that
drives the internal test clock. If the internal clock cannot
be traced back to a primary input, and is controllable in
test mode, specify the '-controllable' option with the
'define_dft test_clock' command. In the latter case, you
can define the test clock waveform.
DFT-168 Failed to analyze specified scan
chain.
If the scan data path contains combinational logic that is
controllable in test mode, you must specify the proper
test control signals using either the 'define_dft
shift_enable or 'define_dft test mode' command before
defining the scan chain with the -analyze option.
Alternately analysis may have failed because a scan
flop is part of another scan chain or scan segment. In
that case remove the offending scan chain or segment
and reanalyze.
DFT-170 Found incompatible test clocks in
scan chain (or segment).
When two scan elements are clocked by different test
clocks that were not declared compatible, and these
elements are connected in the same scan segment or
scan chain without a lockup element, the segment or
chain might not shift correctly during testing.
DFT-176 Removed first element from a
mapped shift register segment.
You can prevent such removal by specifying the
element to be preserved (e.g. via "set_attr preserve true
<object>").In order to connect the shift register segment
to a chain, you need to remap the design.
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Warning Messages
May 2013 77 Product Version 12.2
DFT-177 Found an invalid shift-register
element.
Non-scan flip-flops marked with either a 'dft_dont_scan'
attribute or a 'preserve' attribute will fail the DFT rule
checks. To include the shift-register segment during
scan chain connection, all its elements must pass the
DFT rule checks. Either use 'set_attribute
dft_dont_scan false <flop>' or 'set_attribute preserve
false <flop>', then rerun the 'check_dft_rules' command
to ensure a valid shift-register segment.
DFT-179 Invalid shift-register segment
configuration.
By definition, all of the elements of a shift-register
segment should be triggered by the same test clock and
same active edge. Different test clocks can only be
accepted if you define these clocks as equivalent before
scan chain connection. Different clock edges can never
be accepted in a shift-register segment.
DFT-180 Found shift-register element that
might be invalid.
If the first flop of a shift register is mapped to scan, it
must be mapped for DFT for the segment to be
considered during scan chain connection. A flop is
mapped for DFT if its shift-enable pin is either tied off,
floating, or connected to a shift-enable signal defined
with a 'define_dft shift_enable' constraint. If the scan
flop is not mapped for DFT and the shift-enable pin is
functionally connected, either define the signal that the
shift-enable pin is connected to as a shift-enable signal
and run the 'check_dft_rules' command before you run
the 'connect_scan_chains' command, or run the
'replace_scan' command before you run the
'connect_scan_chains' command.
DFT-190 Internal test signals are not written
to the scan abstraction model.
Full chip ATPG will require that these internal test
signals be controlled to their test mode logic values
during scan mode. This is accomplished by adding the
required initialization sequences to the ATPG interface
file to control or access internal pins.
DFT-192 Pin used to fix DFT violation might
not be dedicated for test.
Use a pin that is dedicated for test to ensure that the
functional behavior of the design in non-test mode is not
affected.
DFT-193 Could not define segment.
DFT-196 Could not fix violation. Violations reported due to multiple drivers are not fixed
by the tool. Multiple drivers can be realized for a driving
pin originating from a black-box component. To alleviate
the violation, the black-box component should be
defined as a logic abstract model (empty module
description) when the top-level design is elaborated.
DFT-199 Cannot idealize the test signal. The tool cannot idealize a test signal when its driver is
neither a leaf instance nor a driver port.
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Warning Messages
May 2013 78 Product Version 12.2
DFT-204 Masking recommended with
OPMISR compression.
OPMISR compression without any masking requires an
X-state free design. It is recommended to run
Encounter Test's verify_test_structure command to
verify the design contains no X-sources. An Encounter
Test script to run verify_test_structures can be
generated using the check_atpg_rules command.
DFT-211 Scan chain(s) cannot be
compressed.
The scan chain(s) will be ignored for compression.
DFT-212 A subset of the scan chains have
been specified with OPMISR
compression.
If you plan to compress the remaining chains with a
separate invocation of compress_scan_chains, they
must be compressed using OPMISR compression, and
the generated pin assign files will need to be hand
edited.
DFT-224 Follow-up action needed. One or more option specified requires additional user
action after this command completes.
DFT-226 Failed to analyze specified scan
chain or scan segment.
Specify the proper test control signals using either the
'define_dft shift_enable or 'define_dft test mode'
command before defining the scan chains or scan
segments with the -analyze option. Alternately if scan
flops are already part of a scan chain or scan segment
remove the offending scan chain or segment and
reanalyze.
DFT-230 Removed violation object. An element belonging to the violation object was
removed during optimization. Rerun 'check_dft_rules'
with option 'advanced'.
DFT-235 JTAG instruction may fail
Boundary Scan Verification.
JTAG instructions used to control tool inserted ATPG
scan-modes require its test data register specified using
the '-register' option to be 'BYPASS', or the JTAG
instruction must be specified as a private instruction
using the '-private' option.
DFT-236 DFT configuration modes are
being removed due to test signal
definition. Scan chains may not be
traceable for this configuration
mode.
Redefine the configuration mode with the correct test
signal setup, run check_dft_rules for the configuration
mode and then reanalyze the scan chains associated
with the configuration mode.
DFT-238 Cannot insert inverter before chain
scan out as scan out is shared.
DFT-247 Removing OPCG segment. Removal of OPCG segments can result in loss of
information on inserted OPCG logic.
DFT-248 Removing chain with OPCG
segments.
Removal of chains consisting of OPCG segments can
lead to inconsistent chain reports.
DFT-254 Removing OPCG vdir object.
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Warning Messages
May 2013 79 Product Version 12.2
DFT-255 Overriding the counter length for
the domain macro parameter.
The user specified max trigger delay value for the
domain macro parameter is too small and is being reset
by using the smallest possible counter length.
DFT-257 No Mode initialization file specified
for OPCG mode.
To ensure proper verification, the OPCG logic should be
initialized for each mode of operation using a mode
initialization file.
DFT-258 Undriven pin used for DFT
purposes.
DFT-264 The OPCG domain will be running
at a frequency that is greater than
the specified maximum frequency.
Ensure that the correct minimum domain period is
specified to the 'define_dft opcg_domain' command and
that the correct oscillator source output period is
specified using the '-osc_source_parameters' option to
'define_dft opcg_mode'.
DFT-270 DFT attribute check. Best scan chain balance can be achieved with this
attribute set to true.
DFT-271 Multiple test clock domain found. This can be achieved with the command
'set_compatible_test_clocks -all'.
DFT-281 Missing scan chain or scan
segment.
During the DB restore process the actual scan chains
and actual scan segments are traced to validate their
functionality and are only restored when the trace is
successful. The specified chain or segment was
present in the original session, but is not present in the
restored session. Check for messages earlier in the log
to indicate the reason.
DFT-282 Requested channel length is less
than maximum length of
compressed segment.
The requested channel length is recommended to be
greater than or equal to the maximum length of the
compressed segments for best compression results.
DFT-283 Ignoring asserted domain on test
clock or test signal source pin.
The attribute 'dft_opcg_assert_domain' should only be
specified on data input ports. This attribute setting will
be ignored.
DFT-284 Test clock source feeds a data pin. It is expected that the source of all test clock domains
will only drive clock pins in the design. If the data pin is
not a clock, confirm the connection from the clock
source to the data pin is correct. If the data pin is a
clock pin, the attribute 'dft_opcg_domain_clock_pin'
may not be set to true in the scan abstract.
DFT-285 A data pin feeds a scan abstract
test clock pin.
It is expected that all pins specified as a test clock in a
scan abstract will be driven by source pins of defined
test clocks. Confirm the connection between the data
pin and the scan abstract clock pin is correct. A pin is
specified in a scan abstract as a clock pin by setting the
'dft_opcg_domain_clock_pin' to 'true'.
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May 2013 80 Product Version 12.2
DFT-286 A data pin feeds a blocking
shift_enable signal on an abstract
block.
It is expected that all pins specified as a blocking
shift_enable in a scan abstract will be driven by a
defined blocking shift_enable. Confirm the connection
between the data pin and the blocking shift_enable is
correct. A pin is considered to be a blocking
shift_enable in the scan abstract if it is specified as the
value of the 'dft_opcg_domain_se_input' attribute for
one of the test clock inputs.
DFT-287 Test clock and blocking
shift_enable mismatch.
The message is issued when a test clock / blocking
shift_enable pair are not connected to a corresponding
test clock / blocking shift_enable pair on a scan
abstracted block. Verify these ports of the scan
abstracted block are connected properly. The pair in the
scan abstract is specified with the
'dft_opcg_domain_se_input' attribute.
DFT-301 DFT Clock Rule Violation. Clock signal is not controllable. Affected registers will be
excluded from scan design.
DFT-302 DFT Async Rule Violation. Async signal is not controllable. Affected registers will
be excluded from scan design.
DFT-304 DFT Abstract Segment Test Mode
Rule Violation.
Abstract Segment Test Mode signal is not controllable.
Affected abstract segments will be excluded from scan
design.
DFT-305 Conflicting value asserted for a
test signal.
Use the 'get_attribute dft_constant_value <net>'
command to check the current value on the net
connecting to the referenced pin. The logic value could
be due to a tied constant in the netlist or a test signal
value that was either propagated from a top-level signal
or specified through a 'dft_controllable' attribute on the
pin.
DFT-307 TDRC data not available. Test Design Rule Check (TDRC) data is not available.
Either check_dft_rules has not been run or some other
operation has caused TDRC data to be invalidated, for
example, netlist changes, modification of test clocks or
signals, etc.
DFT-308 Both edges of a clock are used to
trigger the registers.It may be
necessary to gate the clock to turn
it OFF during scan shift mode in
Clocked LSSD or Clocked Scan
styles.
ClockedLSSD and ClockedScan styles require the
system clock to be OFF during scan shift mode. If a
clock is triggering registers at both edges, the OFF
states for the two sets of registers may be in conflict -
and may require gating logic to be active during scan
shift mode.
DFT-309 Conflicting off-state requirements
for a clock signal.
In clocked-LSSD and clocked-scan style, system clock
needs to be held OFF during shift-scan mode. The
off-state requirement for different registers require this
clock net to be at both logic 0 and logic 1
simultaneously. Test points are necessary to satisfy this
requirement, or some registers may be excluded from
scan chains.
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Warning Messages
May 2013 81 Product Version 12.2
DFT-312 DFT Shift Register Segment
Violation.
Affected shift register segments will be excluded from
scan design.
DFT-313 Cannot fix violation. The current version of the tool cannot fix violations
reported for shift registers or potential race condition
violations or violations reported for the test mode signal,
clock or other clock of abstract segments.
DFT-314 Suppressed printing of details of
some DFT violations.
Limited printing of details on DFT violations to avoid
excessive data in the log file. To control the number of
violations printed to the log file, use the
'-max_print_violations' option. To print all details to the
log file, use '-max_print_violations -1'. To print the
output to a file, use '>' to redirect the file.
DFT-315 DFT Tristate net contention
Violation.
To remove the net contention violation in scan-shift
mode, either modify the RTL, or use the '-tristate_net'
option of the 'fix_dft_violations' command.
DFT-316 Potential Race Condition Violation. A potential race condition exists in the design that could
affect ATPG. This design error should be corrected to
get better results.
DFT-317 Potential X-source Violation. A potential x-source generator exists in the design that
could affect ATPG. Fix the problem by inserting shadow
logic or use the command 'fix_dft_violations'.
DFT-318 Cannot fix violation. Bidirectional pins will be realised for an unresolved
instance modeled as a black-box. To model the pin
directions, the unresolved instance should be read into
the tool as a logic abstract model.
DFT-319 Compression clock violation. Run 'connect_compression_clocks' to connect the
compression clocks and rerun the command
'check_dft_rules'.
DFT-400 Empty scan chain. Attempting to use an empty scan chain. This may
indicate an unnecessary or somewhat forgotten
declaration.
DFT-405 Ignoring register from scan
connection as it belongs to an
invalid segment.
DFT-406 Ignoring a register from scan
connection as it belongs to a
preserved module but not to any
user defined scan_segment.
DFT-408 Total number of configured chains
differs from specified minimum
number of chains.
Additional chains were required to satisfy the scan
chain configuration constraints, such as
maximum-length, number of incompatible clock
domains, etc.
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Warning Messages
May 2013 82 Product Version 12.2
DFT-410 Cannot connect an instance in the
list of elements specified to be
connected in a chain.
A specified instance on '-elements' option cannot be
connected as it may be failing TDRC, or be already
connected in a chain when using '-incremental' option.
Such instances will get ignored for scan connection.
DFT-415 Could not connect scan chains. Check if the status of the flops indicates they failed the
DFT rule checker or were marked dont scan. If the flops
passed the DFT rule checker, check if they are part of a
preserved module. Also check to see if all the elements
have been assigned to a configuration mode in which
case rerun the command using the
-dft_configuration_mode option. Lastly, check if the
flops were already connected.
DFT-416 Excluded segment from scan
connection.
To include this segment, all elements of the segment
must pass the DFT rule checks, and be instantiated in
the hierarchical instance specified with the '-elements'
option of the 'connect_scan_chains' command.
DFT-417 Cannot connect element in a chain
for specified power domains.
To be included in a scan chain an element specified
with the '-element' option must belong to one of the
specified power domains.
DFT-418 Cannot prepend an instance/
segment in the list of elements to
the existing chain.
A specified instance on '-elements' option cannot be
connected as it may be failing TDRC, or set to dont
scan or not mapped for DFT, or be already connected
in a chain. Such instances will get ignored for scan
connection.
DFT-510 Could not find a scan-equivalent
cell.
A scan-equivalent cell was not found. A potential
scan-equivalent library cell is considered not usable if it
has a 'dont_use' or a 'dont_touch' attribute set to true in
the .lib files. In this case, use 'set_attribute preserve
false <scan_libcell>' and 'set_attribute avoid false
<scan_libcell>' to make the cell usable. A potential
scan-equivalent library cell is excluded if it does not
follow the Scan Cell Requirements described in the
'Library Guide for Encounter RTL Compiler'. This
requires fixing the library.
DFT-511 Scan mapped flop fails DFT rule
check - will not be considered for
scan connection.
DFT-512 Non-scan flop conversion to scan
is done using the replace_scan
command. The following register
will not be included on a chain.
DFT-513 Scan mapped flop marked
dont_scan - will not be considered
for scan connection.
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Warning Messages
May 2013 83 Product Version 12.2
DFT-514 Scan flop is mapped for non-DFT
functional operation. It will not be
considered for scan connection.
The identified flop seems to be mapped to a scan
register for non-DFT purpose, i.e. functional operation.
Its shift-enable is hooked up to a signal that has not
been identified as a DFT shift_enable signal using
'define_dft shift_enable' command. Use 'replace_scan'
to convert this flop into a MUX + scan flop combination.
DFT-515 Scan mapped flop marked
dont_scan because abstract
segment defined across it or
across a parent module - will not
be considered for scan
connection.
DFT-516 Flip-flop marked dont_scan is in a
non-uniquified subdesign.
Use edit_netlist dedicate_subdesign <instance> to
uniquify the subdesign if you do not want this attribute
to be set on all instances.
DFT-517 Scan-flop fails the DFT rule
checks.
Scan flops must pass the DFT rule checks to reliably
shift ATPG data through the scan chains.
DFT-521 Lockup flop inserted may not
satisfy clock skew requirements.
DFT-522 Lockup latch inserted may not
satisfy clock skew requirements.
DFT-561 Unpreserving a preserved net.
DFT-565 Excluding testpoint flop. Flop will be ignored from update if the flop is preserved.
Flop will be ignored if it was not inserted by command
insert_dft test_points or insert_dft rrfa_testpoints.Flop
will also be ignored from update if the specified location
is preserved, part of a segment, is part of a compressed
scan chain or the dft_clock_edge of the location does
not match the flops dft_clock_edge. If a location is not
specified for the flop, flop will be ignored if unable to find
a location automatically that satisfies the above
condition. Specify the option '-force' or set the root level
attribute 'ui_respects_preserve' or the attribute
'dft_mix_clock_edges_in_scan_chains' to false to relax
these conditions.
DFT-567 Cannot wrap pin/port.
DFT-568 Cannot honor '-shared' option for
pin/port.
DFT-602 No chains present in CTL file. This could be because: 1. there are no scan chains
defined in the ScanStructures section of the CTL file 2.
the scan chains defined cannot be referenced from the
CTLMode block with TestMode InternalTest. Check if
they are referred from the DomainReferences section of
that CTLMode.
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May 2013 84 Product Version 12.2
DFT-611 Replacing scan chain. If you do not want scan chains in an unnamed
ScanStructure block from being replaced with a scan
chain with the same name in a named ScanStructure
block then rename the scan chain to have a unique
name.
DFT-651 No test clocks identified for
dedicated wrapper cell.
A test clock has not been identified from the fanin/
fanout analysis of the port. Will use the first available
test clock source from the dft vdir.
DFT-652 Multiple test clocks identified for
dedicated wrapper cell.
Multiple test clock sources have identified from the
fanin/fanout analysis of the port. Will use the most
occurring test clock source from the list of these
available dft test clock sources.
DFT-711 Found no shift enable signal for
analyzed scan chain element.
Ensure that the shift-enable pin of the analyzed scan
chain element is driven by a pin or port that has been
defined as a shift-enable test signal. If the analyzed
scan chain contains elements driven by different
shift-enable test signals, the DFT-711 message will
continue to be issued for all elements whose
shift-enable test signal is not detected to be the
chain-specific shift enable test signal. In most
situations, the chain-specific shift-enable signal will be
associated to the shift-enable test signal belonging to
the first element in the actual scan chain.
DFT-712 Element of analyzed chain has
opposite SE polarity.
When different elements of a scan chain are driven by
the same shift enable signal but with opposite polarity,
the scan chain might not shift correctly during testing.
Check if the shift enable path contains any unwanted
inverting logic.
DFT-714 Could not insert lockup elements
in a preserved sub block of an
analyzed scan chain.
Lockup elements cannot be inserted in a sub-block
whose instance or subdesign was marked preserve. To
ensure lockup element insertion, set the 'preserve'
attribute to 'false' on the instance or subdesign that was
reported preserved before rerunning the 'insert_dft
lockup_element' command.
DFT-716 Found no scan clock a signal for
analyzed scan chain element.
Make sure that the scan clock a pin of the analyzed
scan chain element is connected to a pin or port that
was specified as driver of a scan clock a signal.
DFT-717 Found no scan clock b signal for
analyzed scan chain element.
Make sure that the scan clock b pin of the analyzed
scan chain element is connected to a pin or port that
was specified as driver of a scan clock b signal.
DFT-718 Terminal Lockup element insertion
not required.
The chain already has a terminal lockup at the end of
the chain or the tail segment of the chain was specified
with a -skew_safe option.
DFT-719 Terminal lockup insertion will not
be done for analyzed scan chain.
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Warning Messages
May 2013 85 Product Version 12.2
DFT-720 Cannot overlay segment on
analyzed scan chain.
If the segment contains combinational elements then
scan chain analysis may not be able to trace through it
unless it knows what is the scan in and scan out of this
instance. Instead of specifying a combinational instance
as part of a segment specify it as a combination of its
sdi and sdo pins. Also If the scan chain was analyzed
without specifying the -sdi option then the trace of the
chain may be terminated at an internal pin of the
design. If this pin happens to be in the middle of a user
defined segment then the segment cannot be overlaid
as it would not be possible to overlay all elements of the
scan chain. Specify either the -sdi option to the
command or specify the right test mode values so that
the trace proceeds beyond the middle of the segment.
DFT-722 Could not insert inverter in a
preserved sub block of a scan
chain.
Inverters cannot be inserted in a sub-block whose
instance or subdesign was marked preserve. To ensure
inverter insertion, set the 'preserve' attribute to 'false' on
the instance or subdesign that was reported preserved
before rerunning the 'fix_scan_path_inversions'
command.
DFT-802 Did not find a -min_wire_length
option specified with the -physical
option.
Specify the desired min wire length with the
-min_wire_length option.
DFT-804 Ignoring the -physical and
-min_wire_length options as a
large number of scan flops do not
have physical information.
Make sure that the DEF file has physical information for
all the scan flops that are to be put onto scan chains.
DFT-909 Cannot find instruction register. Check to see if instruction register exists in dft/
boundary_scan vdir.
DFT-925 Tap Port not yet defined. All the tap ports need to be defined using the command
'define_dft tap_port' for the rest of the flow to
understand the jtag_macro.
ECCD-410 Input sdc file not specified. Specify the input sdc if automatic generation is not
desired.
ECCD-411 Input netlist not specified. Specify the input netlist if automatic generation is not
desired.
ECO_MANIPULATION-103 ECO command ignored. ECO Manipulate command ignored.
ECO-150 SDC file not specified. Synthesis will proceed without any timing constraints.
ELABUTL-101 Inout/Output ports of an instance
cannot be driven by supply0/
supply1.
Check port connectivity of an instance.
ELABUTL-102 Port connections on the instance
are lesser than the number of
declared ports on the module.
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Warning Messages
May 2013 86 Product Version 12.2
ELABUTL-123 Undriven module output port. Use the 'hdl_undriven_output_port_value' attribute to
control treatment of undriven output port during
elaboration.
ELABUTL-124 Unconnected instance input port
detected.
Use the 'hdl_unconnected_input_port_value' attribute
to control treatment of unconnected input port during
elaboration.
ELABUTL-125 Undriven signal detected. Use the 'hdl_undriven_signal_value' attribute to control
treatment of undriven net during elaboration.
ELABUTL-127 Undriven module input port. Use the 'hdl_undriven_signal_value' attribute to control
treatment of undriven input port during elaboration.
ENC_MSV-201 A domain in RC has been skipped. The specified domain has not been written. Encounter
currently does not support domain names starting with
an integer.
ENC-2 Encounter executable not found. The Encounter executable was not found. Assure that
'encounter' is in the path if Encounter based operations
are desired.
ENC-3 Configuration file construct
ignored.
The specified construct is not supported.
ENC-6 Problems detected during
configuration file generation. See
logfile for details.
One of more problems where detected as a result of
generating the configuration file. The file contents may
not be as expected.
ENC-10 Unrecognized floorplan or
placement format based on file
extension.
The physical data file format specified by the file
extension is not recognized.
ENC-15 Preferred Encounter mode or
command not available.
The preferred Encounter mode of operation or
command was not found. Less optimal command(s) will
be used or the operation will be skipped. This will result
in a less than optimal result.
ENC-23 CPU number more than default.
Additional EDI licenses will be
checked out.
By default 2 CPUs are permitted to be used by EDI.
Additional EDI licenses will be checked out if more than
2 CPUs are specified to be used through attribute
'enc_cpu_usage'.
ENV_PA-31 Overwrote the leakage power of
instance.
The user-defined leakage power value will be used for
power analysis for this instance.
ENV_PA-32 Overwrote the internal power of
instance.
The user-defined internal power value will be used for
power analysis for this instance.
ENV_PA-33 Cannot overwrite the leakage
power of hierarchical instance.
The user-defined leakage power value can only be set
on leaf instances.
ENV_PA-34 Cannot overwrite the internal
power of hierarchical instance.
The user-defined internal power value can only be set
on leaf instances.
ENV_PA-35 Overwriting libcell level attribute
with instance level attribute.
The instance level attribute takes precedence over the
libcell level attribute and will be used for power analysis
for this instance.
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Warning Messages
May 2013 87 Product Version 12.2
FILE-101 Cannot access file. Permissions are not set correctly.
FILE-102 Specified path is not a directory.
FILE-103 Cannot access directory. Permissions are not set correctly.
GB-5 Some input/output ports required
to write out the GENERIC and
GENERIC_REAL modules are
missing.
The lec friendly netlist should be written out before
removing ports from datapath subdesigns. One
possible command which does the same is
'delete_unloaded_undriven'. Kindly check your RC
script.
GG_CLONE-102 The instance is preserved. Set the attribute 'ui_respects_preserve' to false to
enable it for clock gating cloning.
GG_CLONE-103 The clock gating instance is not
good for cloning.
GLO-26 Setting attribute
optimize_constant_0_seq only
allowed for sequential instances.
Attribute optimize_constant_0_seq is evaluated only for
sequential instances. Therefore changing it for other
instances is ignored.
GLO-27 Setting attribute
optimize_constant_1_seq only
allowed for sequential instances.
Attribute optimize_constant_1_seq is evaluated only for
sequential instances. Therefore changing it for other
instances is ignored.
GLO-28 Setting attribute
optimize_merge_seq only allowed
for sequential instances.
Attribute optimize_merge_seq is evaluated only for
sequential instances. Therefore changing it for other
instances is ignored.
GLO-29 Setting attribute
optimize_constant_feedback_seq
only allowed for sequential
instances.
Attribute optimize_constant_feedback_seq is evaluated
only for sequential instances. Therefore changing it for
other instances is ignored.
GLO-44 No usable cell in library. Make sure library has usable cells.
GSC-100 Unique pins should have the same
polarity value.
Two pins that have the same value for gsc_pin_function,
with a gsc_pin_type of unique must have the same
value for the attribute gsc_pin_polarity.
GSC-101 Disconnected a constant driver. Default constant connection is being replaced by dft
functional connection.
GSC-102 Unique pins have different polarity
values.
Two pins that have the same value for gsc_pin_function,
with a gsc_pin_type of have different values for the
attribute gsc_pin_polarity. An inverter will be inserted.
HDL-4 Options not supported with
'read_hdl -netlist'.
The following options are ignored when they are given
in combination with the 'read_hdl -netlist' command:
-top, -v1995, -v2001, -sv, -vhdl, -lib.
HDL-7 Unusual option(s) specified with
the 'update_hdl_input' command.
HDL-8 File has been modified.
HDL-9 File has been modified.
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Warning Messages
May 2013 88 Product Version 12.2
HDL-10 File not read through read_hdl
command.
HF-110 Output directory already exists. The directory to be used to store output data already
exists. The data will be overwritten with new generated
data.
HPT-5 Multiple versions of module found
in module pool during elaboration.
HPT-62 NULL handle passed to routine.
HPT-76 Replacing previously read Verilog
module or VHDL entity.
A newly read VHDL entity replaces any previously read
Verilog module or VHDL entity in the same library if its
name matches (case-insensitively) the existing module
or entity.
For instance:
VHDL 'foo' replaces VHDL {'FOO' or 'foo' or 'Foo'
or ...} in the same library
VHDL 'foo' (in any library) replaces Verilog {'FOO'
or 'foo' or 'Foo' or ...} in the same library
A newly read Verilog module replaces any previously
read Verilog module if its name matches
(case-sensitively) that module. Further, it replaces any
previously read VHDL entity in the same library if its
name matches (case -insensitively) that entity.
For instance:
Verilog 'foo' replaces VHDL {'FOO' or 'foo' or 'Foo'
or ...} in the same library
Verilog 'foo' replaces Verilog 'foo' only
In addition:
Verilog 'foo' does not replace Verilog 'FOO' and the
two remain as distinct modules.
HPT-84 Ignoring conflicting instance
configuration.
An instance has been configured through two
conflicting configuration constructs.
HPT-85 Redundant instance configuration. An instance has been configured the same way twice.
HPT-86 Previous configuration.
HPT-87 File does not contain the VHDL
entity for ChipWare component.
The VHDL entity declaration corresponding to a given
ChipWare component was not found in the file specified
via the 'location' attribute on the component vdir. Check
that the file contains the entity declaration, and that the
entity name is identical to the component name.
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May 2013 89 Product Version 12.2
HHPT-83 Missing synthesis model for a
ChipWare component.
The synthesis model corresponding to a particular
implementation of a ChipWare component was not
found in the specified file. The file was specified via the
'location' attribute on the implementation directory.
Check that the file contains the synthesis model, and
that the model follows the required naming convention.
A Verilog synthesis model should be named:
'<component_name>__<implementation_name>'. A
VHDL synthesis model should have an architecture
named '<implementation_name>'.
INCRSYN-2 Turned off incremental synthesis
and switched back to regular
synthesis flow.
INCRSYN-3 Unable to access the read_cache
directory.
Check the existence and access permission of the
directory.
INCRSYN-8 Turned off OVF recording.
INCRSYN-11 "-no_incremental" option does not
match with previous run.
ISO-101 Cannot define isolation rule. Power domains are not created.
ISO-104 Skipping isolation rule definition for
pin/port.
Power domain is not associated with one of the drivers
of pin/port.
ISO-105 Skipping isolation rule definition for
pin/port.
Power domain is not associated with one of the loads of
pin/port.
ISO-106 Skipping isolation rule definition for
pin/port.
One of the drivers power domain is different than from
power domain list specified.
ISO-107 Skipping isolation rule definition for
pin/port.
One of the loads power domain is different than to
power domain list specified.
ISO-108 Skipping isolation rule definition for
pin/port.
One of the drivers and loads are having command
power domain.
ISO-109 Skipping isolation rule definition for
pin/port.
ISO-114 Multiple enable drivers are
specified.
ISO-201 Cannot insert isolation cells. Power domains are not created.
ISO-202 Invalid isolation cell. The cell should have 2 inputs and 1 output.
ISO-203 Skipped isolation cell insertion. No appropriate isolation cell available for insertion.
ISO-204 Uniquifying the multiple
instantiated subdesign to prepare
for isolation cell insertion.
ISO-205 Cannot insert isolation cell. To insert an isolation cell on a pin or (sub)port, it must
have a load or a driver.
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May 2013 90 Product Version 12.2
ISO-206 No cell found that is an isolation
cell and level shifter.
Other cell will be used as isolation cell.
ISO-207 No appropriate isolation cell is
available.
ISO-210 Cannot insert isolation cell.
ISO-211 Cannot insert isolation cell.
ISO-212 Cannot insert isolation cell.
ISO-213 Could not find matching isolation
cell.
The tool will try to synthesize the required isolation logic
using available cells. Depending on whether it finds
suitable cells, the tool may or may not insert isolation
logic.
ISO-215 Cannot insert isolation cell. Set the variable 'lp_insert_isolation_cell_on_input_pin'
to 1 to insert isolation cell from 'ON' to 'OFF' power
domain. By default, in CPF flow, the insertion is valid.
ISO-218 Cannot insert isolation cell. To insert an isolation cell on a pin or (sub)port, it must
have a load or a driver.
ISO-219 Cannot insert isolation cell. Isolation cells cannot be inserted on pins inside level
shifter hierarchy.
ISO-220 Cannot insert isolation cell. Isolation cells cannot be inserted on pins inside
isolation hierarchy.
ISO-221 Cannot insert isolation cell. Isolation cells cannot be inserted on pins inside level
shifter hierarchy.
ISO-222 Cannot insert isolation cell. Isolation cells cannot be inserted on pins inside
operand isolation hierarchy.
ISO-223 Cannot insert isolation cell.
ISO-224 Cannot insert isolation cell. Remove the isolation cell using 'isolation_cell remove'
to make the insertion possible.
ISO-225 Cannot insert isolation cell. Remove the level shifter using 'level_shifter remove' to
make the insertion possible.
ISO-226 Cannot insert isolation cell. Set attribute 'power_domain' of all the fan-ins of the pin.
ISO-227 Cannot insert isolation cell. Set attribute 'power_domain' of all the fanouts of the
pin.
ISO-228 Cannot insert isolation cell. To insert isolation cells, the load and the driver must
belong to different power domains.
ISO-229 Could not insert isolation cell. To allow isolation cell insertion, remove the existing
isolation cells using the 'isolation_cell remove'
command.
ISO-230 Could not insert isolation cell. To allow isolation cell insertion, remove the existing
level shifter cells using the 'level_shifter remove'
command.
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Warning Messages
May 2013 91 Product Version 12.2
ISO-231 Cannot insert isolation cell.
ISO-232 Cannot insert isolation cell.
ISO-233 No cell is available that is level
shifter and isolation cell.
In CPF flow, only combo cell can be inserted in 'to'
location across library domains. The tool will try to
synthesize the required isolation logic using available
cells. Depending on whether it finds suitable cells, the
tool may or may not insert isolation logic.
ISO-234 No cell is available that is level
shifter and isolation cell.
The tool will try to synthesize the required isolation logic
using available cells. Depending on whether it finds
suitable cells, the tool may or may not insert isolation
logic.
ISO-235 No proper isolation cell is
available.
ISO-236 Cannot insert isolation cell.
ISO-237 Cannot insert isolation cell. The tool will try to invert the enable of isolation cell to
meet the requirements. If required cell and inverter are
found, isolation logic insertion will be successful.
ISO-238 Could not find matching isolation
cell.
The tool will try to synthesize the required isolation logic
using available cells. Depending on whether it finds
suitable cells, the tool may or may not insert isolation
logic.
ISO-239 Cannot insert isolation cell.
ISO-240 Cannot insert isolation cell. The tool will try to invert the enable of isolation cell to
meet the requirements. If required cell and inverter are
found, isolation logic insertion will be successful.
ISO-241 Cannot insert isolation cell. The tool will try to invert the enable of isolation cell to
meet the requirements. If required cell and inverter are
found, isolation logic insertion will be successful.
ISO-242 Unusable cell found in cell list for
isolation rule.
Cells specified with '-cells' must be usable.
ISO-243 No isolation type found for cell. Cells specified with '-cells' must have valid isolation
type.
ISO-244 Could not insert combo cell. Ensure appropriate isolation cells are given in the
isolation rule cells list.
ISO-245 Could not find matching isolation
cell.
The tool will try to synthesize the required isolation logic
using available cells. Depending on whether it finds
suitable cells, the tool may or may not insert isolation
logic.
ISO-246 Cannot insert isolation cell.
ISO-247 Cannot insert isolation cell. The tool will try to invert the enable of isolation cell to
meet the requirements. If required cell and inverter are
found, isolation logic insertion will be successful.
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Warning Messages
May 2013 92 Product Version 12.2
ISO-248 Cannot insert isolation cell.
ISO-249 Cannot insert isolation cell.
ISO-250 Cannot insert isolation_cell. Isolation insertion would happen at power domain
boundary. To enable isolation insertion, set
'lp_pin_and_parent_power_domain_mismatch' to 0.
ISO-302 Standard cell is not available in the
library domain.
ISO-303 Standard cell is not available in the
library.
ISO-401 Cannot remove isolation cell. Power domains are not created.
ISO-402 Cannot remove isolation cell.
ISO-404 Cannot remove isolation cell.
ISO-405 Cannot remove isolation cell. The tool cannot remove the reported instance because
it is not recognized as a valid isolation cell. For more
information on isolation cell criteria, refer to the
'isolation_cell remove' command description in the
Command Reference for Encounter RTL Compiler.
ISO-608 Cannot import instance as
isolation cell.
Library domain of the instance and its one of the drivers'
library domain is different.
ISO-609 Instances is not valid for isolation
import.
ISO-610 Isolation cell not found for mux.
ISO-901 Instance is not a valid isolation
cell.
ISO-902 Instance has no load. It is not a
valid isolation cell.
ISO-903 Instance has no driver. It is not a
valid isolation cell.
ISO-904 Empty isolation cell hierarchy.
ISO-905 Isolation cell hierarchy contains
unmapped cell(s).
ISO-906 Complex isolation cell hierarchy.
ISO-907 Found no isolation cell instances in
the design to report.
Isolation logic is only inserted in designs that use the
power shut off methodology.
LBR-6 Loading libraries. Empty string found for power_gating_pin_class/
retention_pin_class attribute. This power_gating_pin/
retention_pin construct cannot be used for SRPG
synthesis.
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Warning Messages
May 2013 93 Product Version 12.2
LBR-10 The specified wireload selection
string matches both a mode and a
wireload selection table name.
The mode will be used.
If instead you want the wireload selection table to be
used, specify the full path to the table (as returned by
the find command).
LBR-19 Library name multiply defined. No further action is required, or you can change the
name of one of the libraries.
LBR-20 No compatible timing arc defined
with library delay model.
Refer to 'timing group attributes' in 'Setting Constraints
and Performing Timing Analysis Using Encounter RTL
Compiler' for more information.
LBR-21 Timing attributes intrinsic_rise and
intrinsic_fall are not expected and
will be ignored.
Although the delay model for this library is table lookup,
it appears that linear delay model parameters are also
present.
LBR-22 Multiply-defined library cell. Library cell names must be unique. Any duplicates will
be deleted. Only the first (as determined by the order of
libraries) will be retained.
LBR-23 Multiple definitions of the same
attribute detected.
The last definition of each attribute within a group will be
maintained. Delete all but one definition to avoid this
warning.
LBR-25 Empty Wireload selection. Empty wireload selection, ignored by the tool.
LBR-26 Multiple values were detected. Multiple values were detected in this library, using the
last values.
LBR-34 Missing a setup timing arc for
next-state library pin.
Pins used in next-state functions must have setup
timing arcs. Otherwise, the library cell will be treated as
a timing-model.
LBR-36 Libpin with the given name not
found.
LBR-37 Invalid tree-type specified. Acceptable tree-types are 'worst_case_tree',
'best_case_tree', 'balanced_tree' and 'binary tree'.
LBR-38 Libraries have inconsistent
nominal operating conditions.
This is a common source of delay calculation confusion
and is strongly discouraged.
LBR-39 Relaxing an attribute value in the
library.
Relaxing one of the library's attribute value (e.g. a
library-cell's dont_use or dont_touch attribute) should
be done with caution.
LBR-43 Libcell has no area attribute.
Defaulting to 0 area.
Specify a valid area value for the libcell.
LBR-44 Unsupported bus-pin format found
in library.
Valid format is A[0]|A[0:1] or the one specified by
bus_naming_style attribute.
LBR-55 Library has missing capacitive
unit.
Current library has missing capacitive unit.
LBR-57 Library has bad unit. Assuming a different value.
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Warning Messages
May 2013 94 Product Version 12.2
LBR-58 Ignoring internal library pin with no
incoming timing arcs.
Check to make sure that the definition of this library pin
is correct.
LBR-61 Found pin with an unspecified
direction.
All pins must have a direction specified using the
'direction' attribute in the library. A libcell is ignored if
this information is missing for one of its pins.
LBR-63 Lookup tables are only supported
in 'table_lookup' libraries.
Verify that the delay_model for this library is
table_lookup.
LBR-64 Malformed test_cell. Review the definition of the test_cell's function or its
parent library-cell's function. An inconsistency between
the two may exist.
LBR-65 Different var1/var2 names in
test_cell and scanned cell.
According to the library format specification, it is unclear
whether this is acceptable. However, other third party
tools seem to generate such constructs, and we parse
them at our customer's request.
LBR-66 Library cell only has usable
test_cell function.
This library has a valid test_cell function, but its regular
cell function is either missing or not completely
understood (e.g. if the cell has a state_table construct).
LBR-67 Incomplete timing specification of
library pin.
LBR-73 Automatically disabling an arc
which forms loop at output.
Check to see whether the timing arc in question is
crucial for synthesis. If it is, disable a proper arc in the
loop.
LBR-75 Detected a combinational timing
arc in a sequential cell.
The library cell will be treated as a timing-model. Make
sure that the timing arcs and output function were
described correctly. If the cell was intended to have
dual-functionality this may be ok, but this cell cannot be
unmapped or automatically inferred.
LBR-76 Detected a sequential timing arc in
a combinational cell.
The library cell will be treated as a timing-model. Make
sure that the timing arcs and output function were
described correctly. If the cell was intended to have
dual-functionality this may be ok, but this cell cannot be
unmapped or automatically inferred.
LBR-79 An obsoleted attribute was
detected in this library.
The attribute will be recognized in this release, but
support will be dropped in a future release.
LBR-81 Non-monotonic wireload model
found.
Non-monotonic wireload models can cause problems
during synthesis and/or mapping. Raising some of the
points in the curve to give it a monotonic shape.
LBR-89 Overwrote internal power
characterized in the .lib.
The user defined value will be used for power analysis.
LBR-90 Power units. This unit is used only for reporting (default nW).The
possible unit values are mW, uW, nW, pW.
LBR-91 Scaling power value. Suspicious scaled power value.
Message-ID Title Help
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Warning Messages
May 2013 95 Product Version 12.2
LBR-92 Non-mutually exclusive when
conditions detected.
Ignore the invalid state-dependent leakage power
model and use the default cell leakage power for
leakage power analysis.
LBR-93 In PLE mode. This attribute will be
ignored.
If you want, set attribute 'interconnect_mode' to
'wireload' first.
LBR-96 Duplicate when conditions found. Ignoring the earlier when conditions and using the latest
condition.
LBR-97 'set_attribute area' does not
change libcell area in PLE mode.
Use 'set_attribute area_multiplier' to change libcell area
in PLE mode.
LBR-98 Incorrect gating function for
combinational clock-gating
integrated cell.
The combinational clock-gating integrated cell must be
either an AND or OR type gate.
LBR-99 Cannot process state table for
clock-gating integrated cell.
The input node names in the state table must match the
cell input pin names.
LBR-100 Unusable clock gating integrated
cell.
Check to make sure that clock gating cell has all its pin
attributes set correctly.
LBR-101 Unusable clock gating integrated
cell.
To use the cell in clock gating, Set cell attribute
'dont_use' false in the library.
LBR-105 The cell is not a clock gating
integrated cell.
Only a cell with 'clock_gating_integrated_cell' attribute
set in the library is supported for clock gating insertion.
LBR-106 Invalid object for attribute when
using library domains.
Set this attribute on a library_domain object instead.
LBR-117 Bus and related_pin bus bitwidths
do not match.
The bus and its related bus must have matching
bitwidths so that timing arcs can be built between
corresponding bits.
LBR-121 Cell not found in the power library. To perform accurate power analysis, all library cells in
the timing library must also appear in the power library.
LBR-124 Cannot use power models from
another library.
The library cell in the timing library and the cell in the
power library must have identical names and same pin
definitions.
LBR-126 Found a combinational arc in a
sequential cell.
The timing arc connects two pins that are already
connected by a sequential arc. It is not recommended
to mix combinational arcs with sequential arcs in a
sequential cell.
LBR-129 Could not recognize a vector of
pins as a bus.
For a vector of pins to be recognized as a bus, either
number the pins continuously, or define a 'bus' group for
the pins. For more information on 'bus' groups, refer to
the Liberty Reference Manual.
LBR-136 Error declaring a 'pin'. The 'pin' of a 'bus_type' will be treated as a 'bus' and not
a 'pin'.
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Warning Messages
May 2013 96 Product Version 12.2
LBR-139 Could not resolve pin-bundle
names.
Ensure that the identifiers specified in the parameter
string correspond to the pin bundles that are present in
the libcell.
LBR-140 Sequential cell function definition
makes cell unusable.
The sequential cell cannot be inferred because its
function is unknown.
LBR-141 Clock function definition makes
cell unusable.
The sequential cell cannot be inferred because its clock
function is unknown.
LBR-142 Async-clear function definition
makes cell unusable.
The sequential cell cannot be inferred because its
async-clear function is unknown.
LBR-143 Async-preset function definition
makes cell unusable.
The sequential cell cannot be inferred because its
async-preset function is unknown.
LBR-146 Invalid pin name used.
LBR-147 Unable to parse a timing/power arc
'when' function.
Check the arc's 'when' statement in the library source.
LBR-148 Some mapped instances became
unresolved.
Some library cells were found in the original library
domain but not in the new library domain. Instances of
such library cells were replaced with unresolved
hierarchical instances. The corresponding subdesign
was named after the missing library cell. Choose a
library domain that contains these library cells to
convert the unresolved instances.
LBR-150 Improperly defined
'leakage_power' group.
To take the 'leakage_power' group into account during
power estimation, fix the library first and restart. For
more information, refer to the Liberty Reference
Manual.
LBR-151 Pin with a setup timing arc is not in
the support set of the next-state
function.
Pin with a setup timing arc must be in the support set of
the next-state function. Otherwise, the library cell will be
treated as a timing-model.
LBR-152 Pin has more than one setup arc. Pin should not have more than one setup arc.
Otherwise, the library cell will be treated as a
timing-model.
LBR-153 Missing 'default_power_rail' in the
'power_supply' group.
The value of the 'default_power_rail' attribute identifies
a default power supply. For more information on this
attribute, refer to the Liberty Reference Manual.
LBR-156 Cannot assign library domain to
this unresolved subdesign.
The library cell with the same name as the subdesign is
not a timing model in the new library domain.
LBR-157 Detected a pin with itself as the
related_pin in a combinational cell.
This timing-arc of the cell will be ignored.
LBR-158 Libcell will be treated as a timing
model.
Ensure that the relevant timing arcs are defined in the
Liberty model of the libcell.
LBR-159 Missing 'value' in 'leakage_power'
group.
Missing 'value' will be taken as 0.0 for cells with multiple
rails.
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Warning Messages
May 2013 97 Product Version 12.2
LBR-173 Found too large cell leakage
power value.
The cell leakage power value in the library is most likely
wrong. The tool will use the maximum value that it can
handle for power analysis.
LBR-199 Poorly formatted statetable in
library.
Make legitimate values for table inputs.
LBR-200 Multiple definitions of the same
power rail.
The last definition of each power rail within a group will
be maintained. Delete all but one definition to avoid this
warning.
LBR-201 Invalid level shifter pin. The level
shifter is not usable.
Make sure the signal level attribute for the pin is
properly set.
LBR-203 Bad bus_naming_style attribute
value.
The string must contain substrings '%s' and '%d' in that
order.
LBR-205 Ignoring undefined mode in timing
construct.
The 'mode_definition' group must be defined for timing
mode in the cell.
LBR-210 Cannot create/rename level shifter
group.
The level shifter group with the specified name already
exists.
LBR-211 Incompatible level shifter cells
found.
Cannot put level shifter cells with different functionality
in the same level shifter group.
LBR-212 Cannot determine the functionality
of the level shifter cell.
Check 'Level Shifter Requirements' section in the
Library Guide for Encounter RTL Compiler.
LBR-219 Level shifter cell defined
previously.
Each level shifter cell can only be defined in one level
shifter group.
LBR-220 Level shifter cells within a group
must be from the same library
domain.
LBR-221 Level shifter cell will be used as a
normal functional cell.
Set cell attribute 'is_level_shifter' true in library to avoid
this error.
LBR-223 Libcell is not a level shifter. Check RC doc for a level shifter requirements.
LBR-224 Level shifter has wrong voltage
range.
Maximum input and output voltage should not be less
than minimum input and output voltage respectively.
LBR-225 Libcell is not a level shifter or
isolation cell.
Check RC doc for a level shifter and isolation cell
requirements.
LBR-227 Libcell is not a pure isolation cell. The attribute is valid only for pure isolation cell. It cannot
be set on any other cell.
LBR-242 Found Boolean AND expression
for async-clear function using
retention pin.
When an AND expression is found for the async-clear
function which includes the retention pin,the tool ties off
the retention pin to 0 or 1 and the async-clear function
is degenerated to a buffer or inverter.
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Warning Messages
May 2013 98 Product Version 12.2
LBR-243 Found boolean AND expression
for async-preset function using
retention pin.
When an AND expression is found for the async-preset
function which includes the retention pin, the tool ties off
the retention pin to 0 or 1 and the async-preset function
is degenerated to a buffer or inverter.
LBR-301 Unusable isolation cell. To use the cell for isolation cell insertion, set cell
attribute 'dont_use' and 'dont_touch' to 'false' in the
library.
LBR-350 Cannot determine the functionality
of the isolation cell / level shifter.
LBR-351 Isolation cell / level shifter does not
have the enable pin.
LBR-352 Cannot set
'isolation_cell_enable_pin'
attribute.
LBR-353 Data pin of isolation cell / level
shifter is inverted.
LBR-401 Empty type string in power gating
cell.
LBR-403 Ignoring unsupported
lu_table_template.
Ignoring lu_table_template of dc_current construct.
LBR-404 Loading libraries. Found extra '}' in the current library.
LBR-405 Multiple definitions of the same
voltage map.
The last definition of each voltage map within a group
will be maintained. Delete all but one definition to avoid
this warning.
LBR-408 Found CCS construct in the cell. Currently, CCS constructs are only parsed & ignored.
LBR-413 Improperly defined sequential
function.
LBR-414 Sequential cell cannot be treated
as MSFF.
The libcell will be marked as timing model. To make
sure that the sequential cell is treated as a master-slave
flip-flop, use either different clocks or different clock
edges of the same clock for the master and slave
clocks.
LBR-416 Found bit count mismatch in cell. The bit count of a multibit register bank and the bundle/
bus pin of the cell should be the same.
LBR-417 Cannot relax the design rule
constraint of a library pin.
Set the 'override_library_max_drc' root attribute to
'true', if you want to override the library design rule
constraint values.
LBR-418 Could not set avoid attribute. A libcell cannot be unavoided if it was internally marked
avoided by the tool, for example because the cell lacks
physical data.
LIC-5 Limited access feature
unavailable.
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Warning Messages
May 2013 99 Product Version 12.2
LIC-6 Beta feature unavailable.
LS-101 Cannot remove level shifter. The tool cannot remove the reported instance when the
corresponding library cell is a complex cell, or it does
not fulfill the valid level shifter criteria. For more
information on level shifter criteria, refer to the
'level_shifter check' command description in the
Command Reference for Encounter RTL Compiler.
LS-108 Cannot remove level shifter.
LS-109 Cannot remove level shifters. Level shifters can only be inserted in and removed from
a Multiple Supply Voltage (MSV) design.
LS-111 Imported user level shifter
hierarchy contains additional logic
to level shifter logic.
LS-202 Ignored level shifter insertion from
a library domain to another library
domain with lower or same
operating voltage.
LS-203 Wrong location value specified. Allowed values of location are 'from' and 'to'.
LS-204 Invalid level shifter cell. The cell should have one data pin, one output pin and at
most one enable pin.
LS-205 Invalid level shifter cell instance. The instance is either not a mapped instance or it is not
an instance of a standard isolation cell.
LS-215 Could not insert level shifter.
LS-216 'level_shifter insert' command
cannot proceed, as it is non MSV
design.
LS-217 Invalid level shifter cell. Data pin of level shifter is inverted.
LS-218 Invalid dedicated cell. Data pin dedicated cell is inverted.
LS-219 Cannot determine the functionality
of the dedicated cell.
LS-224 One or more pin/port drivers do
not lie in library domains given with
-from_library_domain option.
The specified pins' drivers and loads must have library
domains given with -from_library domain and
-to_library_domain respectively.
LS-225 One or more pin/port loads do not
lie in library domains given with
-to_library_domain option.
The specified pins' drivers and loads must have library
domains given with -from_library domain and
-to_library_domain respectively.
LS-226 Pin/port has no drivers. Valid pins/ports for level shifter insertion must have
driver(s) and load(s).
LS-227 Pin/port has no loads. Valid pins/ports for level shifter insertion must have
driver(s) and load(s).
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Warning Messages
May 2013 100 Product Version 12.2
LS-228 One or more pin/port drivers do
not lie in path of instances given in
-instance_from option.
For more information on -instance_from option, consult
'level_shifter insert' in user guide.
LS-229 One or more pin/port loads do not
lie in path of instances given in
-instance_to option.
For more information on -instance_from option, consult
'level_shifter insert' in user guide.
LS-230 Pin/port parent has library domain
different from library domain of its
one or more drivers.
Inserting level shifters in 'from' location require pin's
parent to be in same library domain as its drivers.
LS-231 Pin/port parent has library domain
different from library domain of its
one or more loads.
Inserting level shifters in 'to' location require pin's parent
to be in same library domain as its loads.
LS-232 Pin/port has drivers and loads in
same library domain.
Level shifters are inserted across library domains.
LS-235 No other option should be given
with '-cpf_only' in 'level_shifter
insert'.
All other options with 'level_shifter insert -cpf_only' are
ignored.
LS-236 Always on level shifter cannot be
inserted.
When level shifter needs to be inserted in switchable
domain and it is to drive an always on pin, an always on
level shifter cell is required.
LS-237 Level shifter cannot be inserted.
LS-238 Always on level shifter cannot be
inserted.
When level shifter needs to be inserted in switchable
domain and it is to drive an always on pin, an always on
level shifter cell is required.
LS-239 Level shifter cannot be inserted.
LS-240 Always on level shifter cannot be
inserted.
When level shifter needs to be inserted in switchable
domain and it is to drive an always on pin, an always on
level shifter cell is required.
LS-241 Level shifter cannot be inserted.
LS-242 Always on level shifter cannot be
inserted.
When level shifter needs to be inserted in switchable
domain and it is to drive an always on pin, an always on
level shifter cell is required.
LS-243 Level shifter cannot be inserted.
LS-244 Could not insert level shifter.
LS-401 'level_shifter check' command
cannot proceed, as it is non MSV
design.
LS-503 'level_shifter update' command
cannot proceed, as it is non MSV
design.
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Warning Messages
May 2013 101 Product Version 12.2
LS-601 'level_shifter import' command
cannot proceed.
LS-608 Cannot import level shifter with
unmapped cells.
LS-903 Instance is not a valid level shifter.
LS-904 Instance fanning out to multiple
power domains.
MAP-5 Unable to map register to specified
libcells.
Specify different set of libcells for this register.
Otherwise mapper will use most cost effective cell.
MAP-8 Logic optimization has modified
the design's clock network. Clock
signals have changed at a
sequential clock pin.
Some timing optimization has already been performed
using clocking information that is no longer valid. Better
synthesis results may be achieved by setting the
post-optimization clock waveforms directly on the
sequential clock pins before mapping. You can see
what the clock signals at each sequential pin are before
and after mapping by using the attribute
'propagated_clocks'.
MAP-11 Incremental optimization is
stopped by abnormal interruption.
MAP-13 Specified libcells do not match
specified instance.
It might only be possible to map to these libcells if
properties change during the mapping process, e. g.
signals resolve to a constant.
MAP-16 Invalid cell type specified. Only sequential libcells are allowed for the
'map_to_register' attribute.
MAP-17 Specified libcells are not functional
equivalent.
The libcells specified for the 'map_to_register'/
'map_to_multibit_register' attribute must be functionally
equivalent.
MAP-18 Specified libcell is not a multibit
sequential cell.
Only multibit sequential libcells can be specified for the
'map_to_multibit_register' attribute.
MAP-19 Specified libcell is either avoided
or not usable.
Check if the 'avoid' libcell attribute is set to 'true'. If so,
change the attribute value to 'false'. Check if the 'usable'
libcell attribute is set to 'false'. If so, remove the cell from
the 'map_to_register' attribute value.
MAP-20 Specified libcell is avoided. Check if the 'avoid' libcell attribute is set to 'true'. If so,
change the attribute value to 'false'.
MAP-21 Library domain difference prevents
mapping to requested libcell.
The tool can only map an instance to the requested
libcell if the library domain of the instance and the
requested libcell are the same.
MAP-22 Attribute 'lp_map_to_srpg_cells' is
set to true either on this instance
or its parent module.
Although attribute 'lp_map_to_srpg_cells' is set to true,
this instance will not be mapped to cost effective srpg
libcell. It will be mapped to libcells specified in
'map_to_register' attribute. 'map_to_register' attribute
does not contain srpg cells.
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Warning Messages
May 2013 102 Product Version 12.2
MAP-23 Attribute 'lp_map_to_srpg_cells' is
in conflict with attribute
'map_to_register'.
Attribute 'lp_map_to_srpg_cells' is set at either instance
of its parent module and having srpg libcell as value,
and this libcell is not contained in 'map_to_register'
attribute. Libcell specified in 'map_to_register' attribute
will be used.
MAP-27 Mapping was done using
-feasible_targets_only option.
This option MUST NOT be used for production, but only
for constraint debugging.
MAP-125 The row or column with constraint
should have all instances with
similar type of libcells.
MAP-126 The instance is having some
special setting (e.g preserve )
which inhibits sizing.
MAP-129 Skip Parallel Incremental
Optimization.
Specify directory path with write permission for attribute
iopt_temp_directory.
MAP-131 Skip Parallel Incremental
Optimization.
Reverting to single thread Incremental Optimization.
MBIST-56 No target groups found in the
configuration file.
MBIST-60 No corresponding write enable pin
found.
No corresponding write enable pin found for a write
enable mask on a memory cell. Ensure a write enable
exists for each corresponding memory port with a write
enable mask.
MBIST-67 Memory cell is redefined in liberty
file.
The previous cell definition found in liberty file is
ignored. Ensure either only one definition is provided for
each memory cell or the desired definition is provided
last.
MBIST-69 The number of clock pins is
inconsistent.
The number of clock pins associated with bist enable
pin of memory cell is inconsistent. Check the .lib file to
ensure there are two clocks related to bist enable pin
only if memory supports test wrapped clock port.
Otherwise functional clock should be the only related
clock to bist enable pin.
MBIST-70 Multiple clock pins are associated
with bist enable pin.
Clock pins are not evenly divided among test wrapped
and non test wrapped clocks. Check .lib file to ensure
that functional and test clocks are related to specified
bist enable pin.
MBIST-71 Cannot find the clock pin related to
pin/bus.
Check .lib file for related clock pin attribute for
referenced pin/bus. Cannot insert BIST to any instances
of memory cell.
MBIST-72 Clock pin is not connected for the
MBIST inserted block.
Make sure that clock pin is connected to the top level
port and re-run.
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Warning Messages
May 2013 103 Product Version 12.2
MBIST-81 Unable to determine all the BIST
related details.
MBIST is not inserted for any instances of this cell.
Verify all the previous messages related to the memory
cell are resolved.
MBIST-82 Cannot define waveform for the
specified mbist clock.
Determine if the internal mbist clock can be traced back
to a primary input pin. If so, the mbist clock waveform
for the internal clock is derived from the root clock that
drives the internal mbist clock. If the internal clock
cannot be traced back to a primary input, and is
controllable in MBIST mode, specify the '-controllable'
option with the 'define_dft mbist_clock' command. In the
latter case, you can define the mbist clock waveform.
MBIST-87 Liberty file does not have an
associated clock statement.
Pin of memory cell is set to clock either by the user or
based on the default naming convention, but the liberty
file does not have an associated clock statement. The
pin is treated as a clock. Verify the referenced pin is
supposed to be a clock pin. If so, add the clock
statement to the pin definition in the corresponding .lib
file.
MBIST-94 Memory cell is not a supported
memory structure.
MBIST is not inserted for this cell. Ensure all target
memory cells are valid memory structures.
MBIST-95 Unable to find the number of ports
on the memory cell.
MBIST is not inserted for this cell. Ensure each port has
a distinct address bus and a clock pin.
MBIST-97 Cannot determine the initial and
final bus indices.
MBIST is not inserted for this cell. Verify the indices are
specified in the liberty file.
MBIST-98 Cannot determine type and or
functionality of pin.
Either the 'memory_read/memory_write' section is
missing for this pin/bus in the liberty file or 'port_alias/
port_action' statement is missing in the configuration
file. MBIST is not inserted for this cell. Correct the
liberty file or the configuration file and re-run.
MBIST-99 MBIST is not inserted for this cell. MBIST insertion requires the clock to have active high
polarity to synchronize the memory cell. Memory cell
uses a clock with active low polarity so MBIST is not
inserted for this cell. Ensure the memory cell has an
active high clock.
MBIST-101 Exactly 1 top level design is
required for checking MBIST rules.
There are none or multiple designs present and design
is not specified. Either specify the design or make sure
there is only one top level design.
MBIST-103 Instance specified in the MBIST
specific interface files is deleted.
The above mentioned instance is deleted. Interface files
may have incorrect instance specified. Either modify the
interface files to point to the proper instance or disable
'synthesize' command and re-run.
MBIST-900 MBIST insertion supports read or
write data bus.
The direction or functionality of data bus memory cell is
not compatible. Cannot BIST instances of memory cell.
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Warning Messages
May 2013 104 Product Version 12.2
MBIST-902 Cannot determine the associated
address bus.
Cannot determine the associated test wrapped address
bus for system write bus of memory cell. No instances
of this memory cell have BIST inserted. Ensure the test
wrapped address bus exists and is related to the same
clock, in the .lib file, as the system address bus and
rerun.
MBIST-914 Cannot determine the associated
clock and address pin.
Cannot determine the associated clock and address pin
related to read bus of memory cell. No instances of this
memory cell have BIST inserted. Verify both the
address and read bus, for the port, use the same
related clock attribute and rerun.
MBIST-915 Number of write ports is more than
number of clock pins.
No instances of this memory cell have BIST inserted.
Each write port must have a separate clock pin
associated with it. Ensure that the number of clock pins
is more than or equal to the number of write ports and
rerun.
MBIST-930 No test wrapped address bus
found.
No test wrapped address bus found that corresponds to
clock and system address bus of memory cell. No
instances of this memory cell have BIST inserted.
Ensure a test wrapped address bus exists for each
system address bus in the test wrapped memory and
rerun.
MBIST-931 No test wrapped output enable pin
found.
No test wrapped output enable pin found that
corresponds to system output enable pin for the port of
memory cell clocked by pin. No instances of this
memory cell have BIST inserted. Ensure a test wrapped
output enable pin exists for each system output enable
pin on a test wrapped memory and rerun.
MBIST-933 Library file appears to be .srule
format.
The required format is .lib format. Replace the file with
a .lib format and type and rerun.
MBIST-935 Test wrapped and functional read
bus not related to same clock pin.
Ensure each port of a test wrapped memory cell has a
unique clock pin and that functional read bus and test
wrapped read bus are related to same clock pin.
MBIST-936 Cannot determine the associated
address bus.
Cannot determine the associated address bus for the
data bus of memory cell. No instances of this memory
cell have BIST inserted. Ensure that the 'address'
attribute is specified in the 'memory_read/
memory_write' section of this bus in the liberty file and
re-run.
MBIST-937 Cannot determine the size of the
address bus for the memory cell.
No instances of this memory cell have BIST inserted.
Ensure that the 'address_width' attribute is specified in
the 'memory' section of this memory cell in the liberty
file and re-run.
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Warning Messages
May 2013 105 Product Version 12.2
MBIST-938 Cannot determine the size of the
data bus for the memory cell.
No instances of this memory cell have BIST inserted.
Ensure that the 'word_width' attribute is specified in the
'memory' section of this memory cell in the liberty file
and re-run.
MBIST-939 Consistency checks cannot be
performed on the specified set of
interface files.
Make sure that the right set of interface files are
provided.
MBIST-1001 Cannot determine the size of the
address bus for memory cell.
The default cell name format is used to determine the
size. Ensure the cell name either conforms to the
default format or the address size is specified in the
configuration file.
MBIST-1002 The memory cell contains no
redundancy information.
The target group has redundancy enabled, but the
memory cell has no redundancy information.
Redundancy analysis will not be possible on this
memory cell. Ensure the memory cell's redundancy
information is provided in the configuration file, if it
exists.
MBIST-1003 The memory cell has zero length
address bus.
Memory BIST is not inserted for this cell. Correct the
specified file and rerun if necessary.
MBIST-1004 Cannot determine the exact
address size of memory cell.
The cell's max address value and the computed
address value do not agree. Memory BIST is not
inserted for this cell. Specify the address explicitly in
the configuration file.
MBIST-1005 Cannot BIST redefined memory
instance of memory cell.
The ignore group in configuration file has a priority over
target group.
MBIST-1006 Ignoring premodel attribute file
keyword and value.
Keyword is not be used because specified value
conflicts with the value required. This value cannot be
changed.
MBIST-1008 Inserted a two input OR gate. Pin was originally connected to a JTAG pin. Ensure an
addition of a logic gate on the JTAG attention path is a
desired result.
MBIST-1009 No write enable pin associated
with write clock found.
Chip select/enable pin associated with the write clock is
used as the ports write enable pin. Ensure no memory
vendor guidelines are violated.
MBIST-1010 No read enable pin associated
with read clock found.
Chip select/enable pin associated with the read clock is
used as the ports read enable pin. Ensure no memory
vendor guidelines are violated.
MBIST-1011 Memory cell not found in netlist. Memory cell was specified in the configuration file, but
was not found in the netlist.
MBIST-1012 Unable to determine connection to
the pad cell.
Unable to determine connection to the pad cell, either 0
or more than 1 drivers of the port found.
MBIST-1013 Unable to determine connection to
the pad cell.
Unable to determine connection to the pad cell, no
functional information present in the pad cell.
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Warning Messages
May 2013 106 Product Version 12.2
MBIST-1015 Timing optimization failed to
achieve zero negative slack.
Could not eliminate negative slack for target frequency.
Specify at most the highest frequency as a target
frequency in the configuration file and rerun.
MBIST-1017 Memory module/instance is not a
recognizable memory cell.
Either the 'memory' section is missing from the cell
description in the liberty (.lib) file or the instance
hierarchy is not completely specified. Ensure that the
correct liberty file is provided and check for syntax
errors pertaining to the liberty file in the log. Also verify
that the instance hierarchy is completely specified in the
configuration file, and rerun.
MBIST-1018 Conflicting comparator input latch
requirements.
Ensure multiply used memory cells have consistent
comparator input latch requirements.
MBIST-1019 Cannot identify the type of
memory cell.
Refer to the Supported Memory Structures section in
the reference document. Ensure the liberty (.lib) file
corresponding to the referenced cell clearly specifies
the type attribute.
MBIST-1020 Cannot BIST any instance of
targeted memory cell.
Refer to the previous message(s) and resolve the
conflicts for the referenced memory cell and rerun.
MBIST-1021 Found constant when tracing to
locate a port.
Make sure the constant connection is expected.
MBIST-1022 Found 'JTAG_MODULE' but
'-connect_to_jtag' option is
missing.
Option 'connect_to_jtag' is missing. No attempt will be
made to connect to TAP interface.
MBIST-1023 Clock gating macros cannot be
mapped to clock gating integrated
cells.
Either the attribute 'clock_gating_integrated_cell' on the
libcell is not of type 'latch_posedge_precontrol' or the
library domain of the libcell does not match the library
domain of the clock gating macro. Make sure that the
proper clock gating integrated cell exists and re-run.
MBIST-1025 Memory cell not specified in the
configuration file.
Specified memory cell is being used in the design but is
not mentioned in the configuration file. Make sure this is
intended.
MBIST-1026 Interface file does not exist. Specified interface file directory does not contain the
interface files. Ignoring the specified interface file
directory.
MBIST-1027 Missing shift enable signal in the
block level flow.
Memory BIST is being inserted for this design at a block
level. If scan insertion is occurring on this design and
simulation of MBIST patterns is planned at the block
level, any shift enable controlling MBIST logic must be
set inactive. Either use define_dft shift_enable prior to
memory BIST insertion or correct the generated pattern
control file 'scan_enable' entry prior to running
'create_embedded_test'.
MBIST-1028 Unable to determine the driving
port for the clock-pin of the block.
Found multiple-input block in the path of the clock pin.
Manually correct the pattern control file to continue
processing.
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Warning Messages
May 2013 107 Product Version 12.2
MBIST-1029 Interface files deleted. Found interface files that match the design name. The
files with the same name will be generated in the
current session.
MBIST-1030 Test enable pin of the BIST engine
is not controllable from a port.
Test enable pin of the BIST engine must be controllable
from a port. In case it is not controllable then the
patterns generated by 'create_embedded_test' will
need to be modified accordingly.
MBIST-1031 Clock pin of the BIST engine is not
controllable from a port.
Clock pin of the BIST engine must be controllable from
a port. In case it is not controllable then boundary scan
verification or simulation may fail. To debug this further,
first run 'set_dft_configuration_mode
-dft_configuration_mode <mbist mode>' and then run
'dft_trace_back -through -mode 1 -print -continue
-polarity' command with the above mentioned pin name.
MBIST-1032 Clock pin of the BIST engine is not
in phase with the driving port.
Clock pin of the BIST engine must be in phase with the
driving port. In case it is not in phase with the driving
port then boundary scan verification or simulation may
fail. To debug this further, first run
'set_dft_configuration_mode -dft_configuration_mode
<mbist mode>' and then run 'dft_trace_back -print
-through -mode 1 -continue -polarity' command with the
above mentioned pin name.
MBIST-1033 Test enable pin of the BIST engine
is not held low.
State of the test enable port must be low at the BIST
engine pin. In case it is not low at the BIST engine pin
then memory BIST will not operate properly. To debug
this further, first run 'set_dft_configuration_mode
-dft_configuration_mode <mbist mode>' and then run
'dft_trace_back -mode 1 -print -continue' command with
the above mentioned pin name.
MBIST-1034 Clock pin of the BIST engine is not
connected to the port specified in
the configuration file.
Clock pin is not connected as specified. It may lead to
failure in the boundary scan verification or simulation.
MBIST-1035 Unable to run 'check_mbist_rules'. Correct the issue mentioned above and re-run.
MBIST-1036 Option 'bitmap' specified for
ROMs.
Stop after read diagnostics is not supported for ROMs.
Ignoring this option.
MBIST-1037 Could not find any memory cell in
the design for BIST.
Ensure that the design is correct, or all the liberty files
are provided or the design has some non-bisted
memories and re-run.
MBIST-1038 Clock source is not defined as
'mbist_clock'.
The port driver of the specified clock pin must be
defined as 'mbist_clock'. Check the 'mbist_clock'
definition or make sure that the clock connections are
correct.
MBIST-1039 Unable to locate 'mbist_clock'. Make sure that the 'mbist_clock' is defined prior to
running 'insert_dft mbist' and re-run.
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Warning Messages
May 2013 108 Product Version 12.2
MBIST-1040 No 'hookup_pin' is associated with
'mbist_clock'.
Make sure that the proper 'hookup_pin' is being used.
MBIST-1041 Algorithm list is empty for the
specified memory.
Make sure that the proper algorithms are specified in
the configuration file and they are compatible with the
memory type.
MBIST-1042 Redundant option specified. Specified option is not required and will be ignored.
MBIST-1043 Unable to find the connection till
TAP specific port.
TAP specific port definition is needed to set the LEC
constraints on the MBIST inserted block pins otherwise
LEC may report issues. Make sure that the specified
TAP port is defined using 'define_dft jtag_port'
command and re-run.
MBIST-1044 Functions 'poweron_run' and
'burnin_run' are missing but
'monitor' is specified.
Make sure that at-least one of the above mentioned
function is specified otherwise 'monitor' is not required.
MBIST-1045 Direct access requested but port
not associated with direct access
function.
Direct access functions should specify ports. Make sure
that either the ports exist or user supplied mode
initialization sequence is required for the downstream
commands.
MBIST-1046 Function 'monitor' is missing but
'poweron_run' is specified.
Make sure that the 'monitor' is specified otherwise
results of 'poweron_run' cannot be verified.
MBIST-1047 Clock gating macros cannot be
mapped to user defined clock
gating integrated cells.
User defined clock gating integrated cell is not of type
'latch_posedge_precontrol'.
MBIST-1048 Option 'bitmap' specified for a
target group with an internal
'mbist_clock'.
Stop after read diagnostics is not supported with
internal clocks. Ignoring this option.
MBIST-1049 Memory bus is incorrectly aliased. Correct the aliased bus and re-run.
MBIST-1050 Library domains do not match. Ensure that the domains are specified correctly.
MBIST-1051 Option 'logic_test' specified for
ROMs.
Option 'logic_test' requested for ROMs. Only
observation logic and no shadow logic is inserted for
ROMs. Use ROM data load file to test read port during
ATPG.
MBIST-1052 Consistency checking of interface
files may fail because attribute
'hdl_infer_unresolved_from_logic_
abstract' is set to 'false'.
The 'false' value of the above mentioned attribute
makes sure that the abstract module is not set to
unresolved. This may have caused the error messages
reported earlier. Correct the value of this attribute and
re-run.
MBIST-1053 Unable to check TDR for some
instructions.
TDR for the above mentioned instructions are part of
the black-boxed hierarchies.
MBIST-1054 TDR length does not match. TDR length does not match. Make sure that the
'insert_dft mbist' completed successfully.
MBIST-1055 Unable to check TDR for MBIST
instruction.
The specified attribute is not set on the above
mentioned instruction. Set this attribute and re-run.
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Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 109 Product Version 12.2
MBIST-3032 Unable to find chip select pin and/
or read enable pin.
The cell does not have a read enable and/or a chip
select pin associated with clock pin. Make sure that this
is intended.
MBIST-3056 Specified instance does not have a
corresponding 'libcell' attribute.
Ensure the correct liberty (.lib) file is provided and
check for syntax errors pertaining to the liberty file in the
log. Also verify the instance hierarchy is completely
specified, and rerun.
MESG-10 Unknown message ID.
MESG-2 Overwriting messages. Specify a
different ID or group to avoid
overwriting the existing message.
Specify different id/group to avoid overwriting of existing
message.
MESG-6 Message truncated because it
exceeds the maximum length of
4096 characters.
By default messages are limited to 4096 characters. All
characters after the 4096 character limit are truncated.
To remove this limit, set the message attribute 'truncate'
to 'false'. However, this may dramatically increase the
size of the log file.
MESG-11 Maximum message print count
reached.
MM_FE-1 Max Try has been reached while
creating file.
MSV_FE-1 Max Try has been reached while
creating file.
MSV_FE-2 Max Try has been reached while
creating directory.
MSV_FE-3 No shifter table file has been
found.
MSV_FE-5 No FE config file specified.
MSV_FE-11 Failed locate file name for library.
MSV_FE-13 No FE LEF file name has been
specified.
MSV_FE-15 Specified name of LEF file list is
not a file.
MSV_FE-17 There is no RC inserted level
shifter cells in the design.
MSV_FE-19 There is no LEF file list provided to
write_fe_msv.
MSV_FE-20 There is no output pin defined for
level shifter.
MSV_FE-21 The specified reference config file
is not a file.
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Warning Messages
May 2013 110 Product Version 12.2
MSV_FE-22 The specified LEF list file is not a
file.
MSV_FE-23 Command 'write_fe_msv' will be
obsolete in a future release.
MSV_FE-24 There is no input voltage defined
for level shifter.
MTDCL-11 Missing inverter/2-input gate in
library set.
Check whether the library cell to be used is avoided or
preserved.If not, provide a library set with atleast an
inverter and a 2 i/p gate.Remapping will fail without
inverter and a 2 input gate.
MTDCL-21 Forbidden Case Identified: Clock
tree has logic not mapped to
clock_library_cells.
MTDCL-22 Forbidden Case Identified: Path
exists with mismatch in
clock_library_cells of launch and
capture clocks.
MTDCL-23 No compatible one-to-one
replacement found for instance on
clock-path.
If a library set has missing match for any instance on
clock-path, we try to remap the cells. The
predefined_vt_map_effort attribute is set to high, so
remapping will be done.
MTDCL-25 Unable to form temporary
hierarchy for clock-path instances'
remapping.
MTDCL-26 Unable to form temporary design
for clock-path instances'
remapping.
MTDCL-31 Failed to find any suitable
replacement for clock-path
instance.
Check if the library-cells to be used are not avoided and
correspond to library-domain of the clock-path
instances.
MTDCL-32 No compatible one-to-one
replacement found for instance on
clock-path.
If a library set has missing match for any instance on
clock-path, we try to remap the cells.But partial
one-to-one replacement does not allow
remapping.Remove partial_one_to_one_replacement
option and set the attribute predefined_vt_map_effort to
high to allow remapping.
NAME_SCOPE-101 Cannot find the object. Check whether the object name and the rtl_scope are
correctly specified.
NAME_SCOPE-102 Cannot find the rtl scope. Check whether the object name for which rtl scope is to
be searched is correctly specified.
OVF-103 Failed to dump traces because
there are multiple top designs.
Traces can only be generated if there is exactly one top
design.
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Warning Messages
May 2013 111 Product Version 12.2
OVF-104 Failed to dump traces because
there is no top designs.
Traces can only be generated if there is exactly one top
design.
OVF-301 Failed to generate G0 netlist
because there are multiple top
designs.
G0 netlist can only be generated if there is exactly one
top design.
OVF-302 Failed to generate G0 netlist
because there is no top design.
G0 netlist can only be generated if there is exactly one
top design.
PA-3 Set the toggle rate for the clock net
to '2/ns'.
The toggle rate of a clock net is determined as 2/
clock_period. A clock period of '0' results in an infinite
toggle rate, which is not realistic. To achieve better
accuracy for power analysis, define the clock with a
meaningful value for the period.
PA-4 Set 'nanos_per_period_scale' to 1. The value must be an integer greater than or equal to 1.
PA-5 Cannot set probability or toggle
rate on a clock net.
The switching activities for a clock net are derived from
the clock definition.
PA-11 Asserted probability and/or toggle
rate is not present on the enable
signal of a power domain.
The power domain will be assumed to be always-on. If
the power domain is not always on, set the appropriate
asserted probability on the enable pin.
PA-13 Could not perform a meaningful
RTL clock power estimation.
No clocks are defined in the design. Clock power
cannot be estimated if the clock frequency is not known.
Make sure at least one clock is defined in the design.
PA-14 RTL power modeling is less
accurate without the
'-clean_up_netlist' option.
Use option '-clean_up_netlist' in command
'build_rtl_power_models' to remove unreachable logic
for more accurate RTL power modeling.
PA-15 Failed in building detailed power
models.
Failed in building detailed power models for accurate
RTL power analysis.
PA-16 Could not build detailed power
models.
For accurate RTL power estimation, set attribute
'lp_power_analysis_effort' to 'medium' or 'high', then
use command 'build_rtl_power_models' to build
detailed power models.
PA-17 Did not find power models for RTL
power analysis.
The RTL power analysis results are more accurate
when detailed power models are used. Use command
'build_rtl_power_models' to build detailed power
models.
PA-19 Performing RTL power analysis
without power models.
For more accurate results, perform RTL power analysis
using detailed power models after 'synthesize
-to_generic' step followed by the
'build_rtl_power_models' command.
PA-20 Skipping build_rtl_power_models
command.
To build detailed power models you must synthesize the
design to generic logic before using the
'build_rtl_power_models' command.
PD-801 No power domains are created. 'report power_domain' works for designs that use power
shut-off methodology.
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Warning Messages
May 2013 112 Product Version 12.2
PD-802 No power modes are created.
PD-803 No design elaborated.
PHYS-10 There is no capacitance,
resistance specified.
Check the wire parasitics section.
PHYS-12 The variant range of wire
parameters is too large.
Make sure to check the consistency of the parameters.
PHYS-13 The value of the wire parameter is
too big.
Check the consistency of this wire parameter.
PHYS-14 The value of the wire parameter is
too small.
Check the consistency of this wire parameter.
PHYS-15 Wire parameter is missing. Check the parameter in technology section.
PHYS-16 Scaled capacitance per unit length
is too large.
You can use max_cap_per_unit_length to increase
maximum capacitance per unit length.
PHYS-17 Scaled resistance per unit length
is too large.
You can use max_res_per_unit_length to increase
maximum resistance per unit length.
PHYS-18 No placement site information in
LEF file(s).
Placement site information is used to set the 'site_size'
attribute used by PLE.
PHYS-20 None of the loaded LEF files have
MACRO statements.
The LEF file containing the cell specific information was
not loaded. The LEF MACRO construct is used to set
the physical data on cells in the timing library. It is likely
that only the technology LEF file was loaded. Load all
the associated LEF files.
PHYS-22 Area per unit length is too large. You can use max_area_per_unit_length to increase
allowed maximum area per unit length.
PHYS-23 Site size is too large. You can use max_site_size to increase allowed
maximum site size.
PHYS-24 Lef has more layers than cap
table.
Check lef and cap table file. Set attribute
'lef_cap_consistency_check_enable' false to skip the
check.
PHYS-25 Minimum width of layer in lef does
not match minimum width of layer
in cap table.
PHYS-26 No nominal temperature specified
in cap table file.
Nominal temperature is used for calculating the
temperature dependent resistance.
PHYS-27 Cap table has more layers than lef.
PHYS-28 Only one file is allowed for the
'cap_table_file' attribute. In case
multiple files are specified, only
the first is picked, and the other
files are ignored.
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Warning Messages
May 2013 113 Product Version 12.2
PHYS-29 File specified in 'cap_table_file'
attribute has been ignored by the
tool.
PHYS-30 Only one file is allowed for the
technology file attribute. In case
multiple files are specified, only
the first is picked, and the other
files are ignored.
PHYS-56 Option '-physical' is going to be
obsoleted.
The reported area is computed using LEF cell area.
Without '-physical' option, 'report area' command
reports area computed using LEF cell area if the
physical library has been loaded, otherwise, it reports
area computed using LIB cell area.
PHYS-57 Cells with no LEF definition. Some cells in design have no definition in LEF.
PHYS-58 Option ignored. The specified option will be treated as indicated above.
PHYS-59 Problem(s) encountered when
restoring attributes.
One or more problems were encountered during the
attribute restoration process. See the log file for detailed
information on which attributes were skipped and for
what reason.
PHYS-61 Expected data not found. The inclusion of this data is not required, however it is
highly recommended in order to achieve the best result.
Rerun the command after supplying the data.
PHYS-64 Could not write RC setup script. The RC setup script was not written for the above
reason.
PHYS-67 Could not reload constraint. RCP could not reload a saved constraint. This generally
happens when the netlist has changed due to
optimization in Encounter.
PHYS-68 Could not find object in constraint. An object in constraint file could not be found. RCP will
try to load the rest of the constraint.
PHYS-91 Program version used to generate
the design database is different
than the current version.
The different program versions could potentially lead to
inconsistent results.
PHYS-92 Design state before and after
restore is inconsistent.
The design state (slack or area) has changed as a
result of the design export and restore process.
PHYS-93 The design is not fully mapped. The original design intent derived from the RTL may no
longer be available upon restoration.
PHYS-101 LEF File Interface.
PHYS-103 Marking library cell 'avoid'. To prevent the library cell from being set to 'avoid', set
attribute 'lib_lef_consistency_check_enable' to 'false'.
PHYS-104 Cannot find physical definition. Set attribute 'avoid' to true on this cell or set attribute
'lib_lef_consistency_check_enable' to 'true'.
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Warning Messages
May 2013 114 Product Version 12.2
PHYS-105 Area mismatch for macro
(between timing and physical
library).
PHYS-106 Site already defined before,
duplicated site will be ignored.
PHYS-107 Macro already defined before, the
previous macro will be overridden.
PHYS-108 This layer has been read already
before, duplicated layer will be
ignored.
PHYS-109 Routing layers are defined in
previous LEF file already.
PHYS-111 There are no vertical or horizontal
layers.
PHYS-112 Physical area of cell is zero. Set attribute 'avoid' to true on this cell or set attribute
'lib_lef_consistency_check_enable' to 'true'.
PHYS-113 Pin names are not consistent in lib
and LEF files.
PHYS-114 Routing layers need to be defined
in the first LEF file.
PHYS-115 Bus bits are not ordered in LEF
file.
Check LEF file for correctness.
PHYS-118 Region already set on instance.
PHYS-119 Region already set on parent
instance.
PHYS-120 MASTERSLICE layer found after
ROUTING or CUT layer.
Masterslice layers are typically polysilicon layers. You
must define layers in process order from bottom to top.
Correct the layer order in the LEF file.
PHYS-121 DEF file has not been loaded yet. Load DEF file first.
PHYS-122 The proper ple mode is required
for this command.
Using attribute ple_mode to change.
PHYS-123 A non-orthogonal polygon
segment is found.
Currently only orthogonal polygon shapes are
supported.
PHYS-124 Pin has no direction specified.
Defaulting to 'input'.
PHYS-125 Cannot add power pin to a library
cell that is currently instantiated in
a netlist.
PHYS-126 Cannot add ground pin to a library
cell that is currently instantiated in
a netlist.
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Warning Messages
May 2013 115 Product Version 12.2
PHYS-128 Library cell pin 'use' attribute is
inconsistent between lib and LEF.
Overriding lib value with LEF value. To use .lib as
golden do: 'set_attr use_power_ground_pin_from_lef
false'.
PHYS-131 The utilization of design exceeds
the threshold defined by attribute
utilization_threshold and
Incremental Optimization step will
be limited.
Incremental Optimization may be limited due to high
utilization in design.
PHYS-132 The proper placement status is
required for this command option.
PHYS-141 Netlist has library cells with no
physical information in LEF. This
may lead to incorrect area
calculation.
To prevent this, add physical information for this library
cell to LEF, or set 'use_area_from_lef' attribute to false.
PHYS-142 Pin with no geometry. Location
offsets set to zero.
PHYS-143 Macro resized due to mismatch
between width/height and overlap
boundary.
PHYS-147 Pin type in .lib and LEF files is not
consistent.
The tool cannot override the value of the pin 'USE'
attribute in the LEF library.
PHYS-150 Pin does not exist in the netlist.
PHYS-152 Component is outside the die.
PHYS-155 DEF parser message.
PHYS-169 Replacing existing row definition.
PHYS-170 Skipping existing row definition.
PHYS-171 Component not present in netlist. This message has a default max print count of '25',
which can be changed by setting the 'max_print'
attribute.
PHYS-172 Read hierarchical DEF to resolve
the component.
PHYS-175 Unmapped component cannot be
placed.
PHYS-176 Components in hierarchical DEF
must be fixed or unplaced.
This message has a default max print count of '10',
which can be changed by setting the 'max_print'
attribute.
PHYS-178 Metal fill present.
PHYS-179 Scan chain present. The tool does not support defining or importing scan
chains using this method.
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Warning Messages
May 2013 116 Product Version 12.2
PHYS-183 The command requires an
'RTL_Compiler_Adv_Phys_Option'
or 'RTL_Compiler_Physical'
license.
PHYS-187 Overlapping guide detected.
PHYS-189 Cover bump macro present. This message has a default max print count of '10',
which can be changed by setting the 'max_print'
attribute.
PHYS-191 Row site does not match LEF
data.
The rows in the DEF file are defined using a site name
that does not exist in the LEF data. This could cause
placement problems if the rows are being used to define
the placement area. In other words, if the rows are used
to derive implicit blockages instead of using blockage
statements. Make sure the LEF and DEF go together.
PHYS-193 Via layer does not match LEF
data.
PHYS-195 Group member not in netlist.
PHYS-196 No defined netlist members in
group.
PHYS-197 Large instance in netlist with no
placement.
PHYS-199 Skipping component with core
spacer macro.
PHYS-203 Skipping component with core
welltap macro.
PHYS-207 Cannot find this net in netlist. Check this net name in the nets directory.
PHYS-208 Cannot find this port in netlist. Check this port name in the port directory.
PHYS-209 Cannot find this instance in netlist. Check this instance name in the instance directory.
PHYS-210 Unrecognizable text found in
SPEF file.
Check the SPEF file for correct syntax.
PHYS-211 Physical cell not created due to
missing macro.
PHYS-212 Bump cell not created due to
missing macro.
PHYS-214 Library cell not defined in physical
library.
Ensure that the proper LEF files are available and have
been imported.
PHYS-217 No GCELLGRID statements
defined.
PHYS-219 Instance in netlist with no LEF
data.
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Warning Messages
May 2013 117 Product Version 12.2
PHYS-225 Incremental mode found existing
group.
PHYS-226 Coincident pins detected.
PHYS-227 Incremental mode found existing
region.
PHYS-228 SPECIALNET connection not
found.
PHYS-231 Via does not exist in LEF or DEF
data.
PHYS-240 Hierarchical instance contains
unmapped logic.
PHYS-241 Instance is unmapped.
PHYS-252 Cannot find this net name, or is
driven by constant.
Check this net name in the nets directory.
PHYS-253 Cannot find this pin or port name. Check this pin name in the pin directories.
PHYS-254 Cannot annotate physical data on
this net.
PHYS-255 Cannot find mapped name. Check map table in SPEF file.
PHYS-256 Annotated physical data will be
ignored for timing analysis.
PHYS-257 Found a hierarchical pin. Currently, the driver to load physical delay can be
annotated to leaf pins only.
PHYS-258 Reduced net information will be
ignored.
PHYS-259 Not pre routed net will be ignored,
when pre_routed_nets option
specified.
PHYS-260 Not ndr net will be ignored, when
ndr_nets option specified.
PHYS-261 Net without pre routed and ndr
information will be ignored, when
pre_routed_nets and ndr_nets
options specified.
PHYS-300 Cannot set physical capacitance to
a net without driver or driven by
constant.
Use a 'ls -a' to confirm that the net has no driver or
constant.
PHYS-301 Cannot set physical delay/
resistance to hierarchical pin.
Set physical delay/resistance to leaf load or driver or
driver-load pair.
PHYS-302 Cannot set physical delay/
resistance to this leaf load.
Set physical delay/resistance to leaf load or driver or
driver-load pair.
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Warning Messages
May 2013 118 Product Version 12.2
PHYS-305 Cannot set physical delay/
resistance using set_attribute to
driver pin.
Set pin physical delay/resistance attribute to leaf load
only.
PHYS-350 The version of the imported DEF is
greater than the version specified
for the exported DEF.
The format version number specified in the DEF that
has been imported into the current session is newer
than the version number that has been specified for the
exported DEF. This may result in illegal constructs in the
exported DEF.The suggested methodology is to convert
the DEF to the proper version prior to importing into RC.
PHYS-351 The specified DEF version does
not fall within the allowed range.
The DEF format version number specified newer or
older than the allowed version range. This may result in
illegal constructs in the exported DEF.
PHYS-353 Incomplete blockage definition. A required parameter is missing from the blockage
definition. The blockage will not be included in the DEF.
PHYS-356 Port direction not specified. The port direction is unknown therefore 'inout' is
assumed.
PHYS-359 Port or instance placement status
is not specified.
The placement location is specified, however, the
placement status is not. This could indicate a problem
with the floorplan. A value of 'placed' is assumed.
PHYS-360 Port or instance placement
orientation is not specified.
The placement location is specified, however, the
orientation is not. This could indicate a problem with the
floorplan. A value of 'N' is assumed.
PHYS-361 DEF construct not supported by
the specified DEF version.
The DEF construct is not supported by the specified
version of the DEF standard. The construct will be
ignored.
PHYS-363 SPECIALNET component not
present in netlist.
PHYS-365 NET component not present in
netlist.
PHYS-370 Power domain boundary is outside
core.
PHYS-413 No view definition file present, the
worst_corner switch is ignored.
Since there is no view definition file present in the
database, the worst_corner switch will be ignored.
PHYS-429 The GUI must be visible before
'def_move' highlighting.
Use the 'gui_show' command to make the GUI visible.
PHYS-433 Some of the derate commands
could not be applied.
Some of the derate commands in the timing derate sdc
file could not be applied in RC.
PHYS-443 A fully Placed design has been
imported. Timing computation will
not consider the cell placement.
Current mode is 'PLE', and NOT 'placement'. Run
'synthesize -to_placed' to account for placement in
delay calculation.
PHYS-500 Skipping Morphing, current
utilization is too high (>90%).
Morphing is not performed since current utilization of
the design is > 90%. For very high utilization designs
morphing can lead to timing degradation.
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May 2013 119 Product Version 12.2
PHYS-501 Skipping Morphing, more than
30% of the grid-cells in the design
are congested.
Morphing is not performed since more than 30% of the
grid-cells in the design are congested. This could mean
design is globally congested. Morphing is not a good
methodology to fix global congestion issues.
PHYS-599 Data from existing technology file
cannot be overwritten by
'cap_table_file'.
Reset technology file attribute to empty string first.
PHYS-600 Inconsistent data. Input data used to create PLE correlation file is different
from data used in this session. This might lead to invalid
results. Check design data.
PHYS-601 Data from existing 'cap_table_file'
is overwritten by technology file.
Technology file has higher precedence over
'cap_table_file'.
PHYS-800 Threshold value not supported for
ECO synthesis.
A threshold value below 0.90 is not supported for ECO
placement and optimization. The final timing and
congestion numbers can degrade appreciably.
PHYS-1211 Exception occurred while invoking
kits.
PHYS-1212 Exception occurred while invoking
kit.
PHYS-1405 Cannot set probabilistic extraction
based capacitance due to no route
data.
Check routable nets exist first.
PHYS-6185 The technology file name given is
incorrect.
PHYS-6186 Layer number is incorrect.
PI-401 Possibly inconsistent power intent. Check the power intent file. The power intent may be
incorrect.
PI-402 Could not find a object. Ensure that the object name is correct.
PI-403 An object has inherited a power
domain from which it was excluded
in power intent file.
The object was marked to be excluded from a power
domain but it was not assigned a proper power domain
explicitly. The object has inherited the same power
domain from power intent semantics. There may be a
problem in power intent specification.
PI-500 Cannot apply power intent on the
design.
There was a problem applying power intent on the
design. The power intent may be incorrect.
PLC-2 Placement Warning.
PLC-3 Placement Error.
PMBIST-56 No target groups found in the
configuration file.
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Warning Messages
May 2013 120 Product Version 12.2
PMBIST-60 No corresponding write enable pin
found.
No corresponding write enable pin found for a write
enable mask on a memory cell. Ensure a write enable
exists for each corresponding memory port with a write
enable mask.
PMBIST-67 Memory cell is redefined in liberty
file.
The previous cell definition found in liberty file is
ignored. Ensure either only one definition is provided for
each memory cell or the desired definition is provided
last.
PMBIST-69 The number of clock pins is
inconsistent.
The number of clock pins associated with bist enable
pin of memory cell is inconsistent. Check the .lib file to
ensure there are two clocks related to bist enable pin
only if memory supports test wrapped clock port.
Otherwise functional clock should be the only related
clock to bist enable pin.
PMBIST-70 Multiple clock pins are associated
with bist enable pin.
Clock pins are not evenly divided among test wrapped
and non test wrapped clocks. Check .lib file to ensure
that functional and test clocks are related to specified
bist enable pin.
PMBIST-71 Cannot find the clock pin related to
pin/bus.
Check .lib file for related clock pin attribute for
referenced pin/bus. Cannot insert BIST to any instances
of memory cell.
PMBIST-72 Clock pin is not connected for the
MBIST inserted block.
Make sure that clock pin is connected to the top level
port and re-run.
PMBIST-81 Unable to determine all the BIST
related details.
MBIST is not inserted for any instances of this cell.
Verify all the previous messages related to the memory
cell are resolved.
PMBIST-87 Liberty file does not have an
associated clock statement.
Pin of memory cell is set to clock either by the user or
based on the default naming convention, but the liberty
file does not have an associated clock statement. The
pin is treated as a clock. Verify the referenced pin is
supposed to be a clock pin. If so, add the clock
statement to the pin definition in the corresponding .lib
file.
PMBIST-94 Memory cell is not a supported
memory structure.
MBIST is not inserted for this cell. Ensure all target
memory cells are valid memory structures.
PMBIST-95 Unable to find the number of ports
on the memory cell.
MBIST is not inserted for this cell. Ensure each port has
a distinct address bus and a clock pin.
PMBIST-97 Cannot determine the initial and
final bus indices.
MBIST is not inserted for this cell. Verify the indices are
specified in the liberty file.
PMBIST-101 Exactly 1 top level design is
required.
There are none or multiple designs present and design
is not specified. Either specify the design or make sure
there is only one top level design.
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Warning Messages
May 2013 121 Product Version 12.2
PMBIST-103 Instance specified in the MBIST
specific interface files is deleted.
The above mentioned instance is deleted. Interface files
may have incorrect instance specified. Either modify the
interface files to point to the proper instance or disable
'synthesize' command and re-run.
PMBIST-900 MBIST insertion supports read or
write data bus.
The direction or functionality of data bus memory cell is
not compatible. Cannot BIST instances of memory cell.
PMBIST-902 Cannot determine the associated
address bus.
Cannot determine the associated test wrapped address
bus for system write bus of memory cell. No instances
of this memory cell have BIST inserted. Ensure the test
wrapped address bus exists and is related to the same
clock, in the .lib file, as the system address bus and
re-run.
PMBIST-914 Cannot determine the associated
clock and address pin.
Cannot determine the associated clock and address pin
related to read bus of memory cell. No instances of this
memory cell have BIST inserted. Verify both the
address and read bus, for the port, use the same
related clock attribute and re-run.
PMBIST-915 Number of write ports is more than
number of clock pins.
No instances of this memory cell have BIST inserted.
Each write port must have a separate clock pin
associated with it. Ensure that the number of clock pins
is more than or equal to the number of write ports and
re-run.
PMBIST-930 No test wrapped address bus
found.
No test wrapped address bus found that corresponds to
clock and system address bus of memory cell. No
instances of this memory cell have BIST inserted.
Ensure a test wrapped address bus exists for each
system address bus in the test wrapped memory and
re-run.
PMBIST-931 No test wrapped output enable pin
found.
No test wrapped output enable pin found that
corresponds to system output enable pin for the port of
memory cell clocked by pin. No instances of this
memory cell have BIST inserted. Ensure a test wrapped
output enable pin exists for each system output enable
pin on a test wrapped memory and re-run.
PMBIST-933 Library file appears to be .srule
format.
The required format is .lib format. Replace the file with
a .lib format and type and re-run.
PMBIST-935 Test wrapped and functional read
bus not related to same clock pin.
Ensure each port of a test wrapped memory cell has a
unique clock pin and that functional read bus and test
wrapped read bus are related to same clock pin.
PMBIST-936 Cannot determine the associated
address bus.
Cannot determine the associated address bus for the
data bus of memory cell. No instances of this memory
cell have BIST inserted. Ensure that the 'address'
attribute is specified in the 'memory_read/
memory_write' section of this bus in the liberty file and
re-run.
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Warning Messages
May 2013 122 Product Version 12.2
PMBIST-937 Cannot determine the size of the
address bus for the memory cell.
No instances of this memory cell have BIST inserted.
Ensure that the 'address_width' attribute is specified in
the 'memory' section of this memory cell in the liberty
file and re-run.
PMBIST-938 Cannot determine the size of the
data bus for the memory cell.
No instances of this memory cell have BIST inserted.
Ensure that the 'word_width' attribute is specified in the
'memory' section of this memory cell in the liberty file
and re-run.
PMBIST-939 Consistency checks cannot be
performed on the specified set of
interface files.
Make sure that the right set of interface files are
provided.
PMBIST-1015 Timing optimization failed to
achieve zero negative slack.
Could not eliminate negative slack for target frequency.
Specify at most the highest frequency as a target
frequency in the configuration file and re-run.
PMBIST-1022 Found 'JTAG_MODULE' but
'-connect_to_jtag' option is
missing.
Option 'connect_to_jtag' is missing. No attempt will be
made to connect to TAP interface.
PMBIST-1025 Memory cell not specified in the
configuration file.
Specified memory cell is being used in the design but is
not mentioned in the configuration file. Make sure this is
intended.
PMBIST-1026 Unable to find the information of
memory cells in the database.
Specified memory cell is being used in the design but is
not read using 'read_memory_view' command. Make
sure this is intended.
PMBIST-1037 Could not find any memory cell in
the design for BIST.
Ensure that the design is correct, or all the liberty files
are provided or the design has some non-bisted
memories and re-run.
PMBIST-1038 Clock source is not defined as
'mbist_clock'.
Check the 'mbist_clock' definition or make sure that the
clock connections are correct.
PMBIST-1039 Unable to locate 'mbist_clock'. Make sure that the 'mbist_clock' is defined prior to
running 'insert_dft pmbist' and re-run.
PMBIST-1056 Configuration file contains 'module'
section. This will be ignored.
All the memory cells, specified using 'module' section,
must be read using 'read_memory_view' command.
The current command will ignore these sections.
POPT-14 Cannot create control port
automatically to improve
clock-gating testability.
Specify an existing test signal using 'set attribute
lp_clock_gating_test_signal <test signal name>'.
POPT-18 Flip-flop to be excluded from clock
gating is in a non-uniquified
subdesign.
Use edit_netlist dedicate_subdesign <instance> to
uniquify the subdesign if you do not want this attribute
to be set on all instances.
POPT-19 User defined clock-gating module
is not complete.
Check if all ports required are present.
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Warning Messages
May 2013 123 Product Version 12.2
POPT-20 Failed to connect test-control logic
for clock-gating.
The test signal cannot be connected if the path to either
the test driver or the clock-gating instance contain an
instance or subdesign that is marked preserved. To
ensure the connection, set the 'preserve' attribute to
'false' on the subdesign or instance that was reported
preserved, then run the 'clock_gating connect_test'
command.
POPT-21 User defined test signal cannot be
found.
Make specify the correct test signal and then re-set
attribute lp_clock_gating_test_signal.
POPT-24 Test pin of clock-gating instance is
already connected.
Will not re-connect.
POPT-26 Inserting hierarchical clock-gating. The addition of new ports at the subdesign boundaries
might cause issues during formal verification. If this is
not acceptable, set the attribute
'lp_clock_gating_hierarchical' to 'false' to turn off
hierarchical clock-gating and restart synthesis.
POPT-31 Failed to connect testability logic
for clock-gating.
The clock gating logic has no test logic inside.
POPT-32 Asynchronous reset pin is missing
from Clock-gating instance.
POPT-33 Failed to connect test signal to
clock-gating logic.
Define the test signal using the 'define_dft test_mode'
or the 'define_dft shift_enable' command. Set the
'lp_clock_gating_test_signal' attribute on the design or
clock-gating instance(s). Then rerun the 'clock_gating
connect_test' command.
POPT-36 Failed to connect test-control logic
for clock-gating.
The test signal cannot be connected if the net
connected to it is marked preserve. To ensure the
connection, set the 'preserve' attribute to 'false' on the
net that was reported preserved, then run the
'clock_gating connect_test' command.
POPT-38 Failed to connect test-control logic
for clock-gating.
To ensure the connection configure scan chains first,
then run the 'clock-gating connect_test' command.
POPT-39 Failed to connect test-control logic
for clock-gating.
While deriving test-control logic from the shift enable
signals of the flop loads connected in scan chains, only
inverters and buffers lying between the gated clock of
the clock-gating instance and the actual flop loads can
be skipped.
POPT-40 Setting clock-gating integrated cell
on a non-uniquified subdesign.
Use edit_netlist dedicate_subdesign <instance> to
uniquify the subdesign if you do not want this attribute
to be set on all instances.
POPT-42 Dropping exception on flop or one
of its pins during clock-gating.
This occurs when the clock-gating logic that is gating
the flop is purely combinational.
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Warning Messages
May 2013 124 Product Version 12.2
POPT-43 Cannot use the specified module
for clock gating.
Refer to the Clock Gating chapter in Low Power in
Encounter RTL Compiler for a list of the required pin
names.
POPT-44 Setting clock-gating module on a
non-uniquified subdesign.
Use edit_netlist dedicate_subdesign <instance> to
uniquify the subdesign if you do not want this attribute
to be set on all instances.
POPT-45 Cannot set 'lp_clock_gating_cell'
attribute for design or subdesign.
Specify a clock-gating integrated cell which belongs to
the same library domain as the design or subdesign. In
case of a library domain mismatch, by default, the tool
proceeds with clock-gating insertion using a suitable
clock-gating integrated cell.
POPT-47 Requested clock gating cell no
longer available.
Reset the 'lp_clock_gating_cell' attribute to point to a
clock gating cell of a library that is loaded.
POPT-48 Changed the 'lp_clock_gating_cell'
attribute value.
The library to which the original requested clock-gating
cell belonged, does no longer correspond to the target
library for the specified design or subdesign. This can
happen if the target library for the design or subdesign
is changed after the 'lp_clock_gating_cell' attribute was
set.
POPT-49 Clock gating is inserted with the
objective to maximize the number
of registers gated because the
power analysis is in low effort
mode.
To insert clock gating with the objective to maximize the
power savings do not only set the attribute
'lp_clock_gating_optimize_power' to true but also set
the attribute 'lp_power_analysis_mode' to either
medium (default) or high.
POPT-80 Could not insert shared
clock-gating logic.
Insert clock-gating logic in the design and re-run the
'clock_gating share' command.
POPT-81 Could not insert shared
clock-gating logic.
The design or hierarchical instance should have at least
2 or more clock-gating instances that share an enable
subfunction for 'clock_gating share' to insert shared
clock-gating logic.
POPT-82 Could not insert shared
clock-gating logic.
Make sure that the design or hierarchical instance in
which you want to insert shared clock-gating logic for
clock-gating logic is not preserved.
POPT-85 Could not consider clock-gating
instance for 'clock_gating share'.
Make sure that the enable logic cone of clock-gating
instance is not preserved.
POPT-90 Could not recognize instance as a
clock gating instance.
Instance should have the enable, ck_in, ck_out pins to
be considered as a clock gating instance.
POPT-91 Could not recognize instance as a
clock gating instance.
Instance should have only the enable, ck_in, ck_out,
test, a_rst, s_rst, obs, scan_en pins to be considered as
a clock gating instance.
POPT-94 A clock gate with a connected test
port is undergoing incremental
gating.
The test signal will need to be re-connected to any new
or altered clock gates. It will also not be re-implemented
as part of an ungated flop's enable logic.
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May 2013 125 Product Version 12.2
POPT-95 Many clock gates were excluded
from incremental clock gating.
This is most often due to preserved flops, clock nets, or
clock gates. It can also be due to complex flop cells.
POPT-97 An automatic timing adjustment or
grouping could not be applied to
one or more clock gate enable
paths.
POPT-209 Could not evaluate operand
isolation instance for power
savings.
The operand isolation instance will be considered as
committed. To evaluate it for power savings, set
'preserve' to false on the instance.
POPT-501 Ignoring dynamic power during
power optimization.
To also take dynamic power into account during power
optimization, set the 'lp_power_optimization_weight' to
a value between 0 and 1.
POPT-502 Total power has skewed
contributions from leakage and
dynamic power.
Dynamic power is typically calculated/specified for
some 'active period'. For combination of leakage and
dynamic power lp_power_optimization_weight must
specify the percentage of overall time for which the
design is not in the 'active period' but in 'idle mode', i.e.
no dynamic power but only leakage power is consumed.
For a reasonable optimization across dynamic and
leakage power, leakage contribution is expected to be
above 5% and below 95%. A contribution of less than
5% will result in limited leakage optimization and
contribution of more than 95% will result in limited
dynamic optimization. Adjust
'lp_power_optimization_weight' so that leakage
contribution comes to an intermediate value if you
intend both optimizations to occur.
POPT-503 Detected a zero cell power value. It might not make sense to set the
'lp_power_optimization_weight' if the dynamic or
leakage (or both) power value(s) of the library cells are
zero. Check the library for the power values and disable
'max_leakage_power' or 'max_dynamic_power' (or
both) attribute(s) if the respective power value(s) of all
cells are zero.
POPT-512 Cannot map a preserved flip-flop
to its state retention equivalent.
To map the flop to its state retention equivalent, set the
'preserve' attribute to 'false' on the instance and then
use the 'state_retention swap' command.
POPT-518 Cannot use a library cell which is
not a state retention cell as the
value for the attribute
'lp_map_to_srpg_cells'.
Only state retention library cells can be used as the
value for the 'lp_map_to_srpg_cells' attribute.
POPT-519 The state retention cell has been
marked 'avoid'.
The state retention cell which can potentially replace a
normal cell has been marked 'avoid'. To use this state
retention cell, remove the 'avoid' attribute setting on the
cell with 'set_attr avoid false <cell>'.
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Warning Messages
May 2013 126 Product Version 12.2
POPT-520 The 'lp_map_to_srpg_cells'
attribute cannot be set on this
object.
The 'lp_map_to_srpg_cells' attribute can be set on
designs, hierarchical instances, and sequential
instances.
POPT-522 Set polarity of power gating pin
driver to 'active_high'.
Valid polarity values are 'active_high' and 'active_low'.
POPT-526 Cannot find corresponding driver
for power gating pin specified.
Provide a proper driver for this power pin to enable the
power gating pin to be connected.
POPT-527 No state retention cell with all
matching power pins specified by
the user found in the library.
Provide correct power pin information corresponding to
state retention cells in the library.
POPT-528 Could not find a single driver to
connect to the power gating pin for
this instance.
Specify a valid unique driver either at the top level or on
the instance specifically to make connections.
POPT-529 Could not find an inverter in the
library to feed the driver for this
instance.
Load a proper library which contains inverter cells.
POPT-530 Found no flops to be swapped to
state retention flops.
Flops in the hierarchy are either already mapped to
state retention cells, marked preserve or do not have
any state retention map attribute settings on them. Set
the map attribute settings on the flops or unpreserve
them to map them to state retention flops.
POPT-531 Could not swap any flops with
state retention flops.
You need to define the flops to be mapped before you
can swap them. To define the mapping, you can use the
'state_retention define_map' command, or set the
'lp_map_to_srpg_cells' attribute to 'true' on the design
or on specific instances, or set the
'lp_map_to_srpg_type' attribute to a specific power
gating cell type in the library on specific instances.
POPT-532 Could not find a buffer in the library
to feed the driver for this instance.
Load a proper library which contains buffer cells.
POPT-533 Resetting the attribute
'lp_map_to_srpg_cells' to '{}' might
affect the attribute
'lp_map_to_srpg_type' and vice
versa. This might have impact on
the state retention mapping
process.
Be aware of this behavior when you reset either the
'lp_map_to_srpg_cells' attribute or the
'lp_map_to_srpg_type' attribute to '{}'.
POPT-534 The state retention cell that is
being used to replace the original
cell lies in a library domain
different from that of the original
cell.
Ensure that state retention cells from same library
domain are used for proper state retention cell
replacement.
POPT-535 A library cell from an incompatible
library domain used for state
retention attribute setting.
Ensure that library cells from same library domain as
that of the instance are used for proper attribute
settings.
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May 2013 127 Product Version 12.2
POPT-537 Cannot apply state-retention map
attribute setting.
You can only set the 'lp_map_to_srpg_cells' and
'lp_map_to_srpg_type' attributes on an instance if the
value of the 'power_gating_cell_type' attribute of the
library cell specified for the 'lp_map_to_srpg_cells'
attribute corresponds to the type specified for the
'lp_map_to_srpg_type' attribute. Otherwise, the first
specified attribute takes precedence.
POPT-538 Could not connect to the power
gating pins.
Use the 'define_state_retention_cell' command in the
CPF file to identify the power gating pin in the reported
cell that has the save or restore function.
POPT-553 No valid scopes could be
determined for monitoring.
Specify valid scopes with the
'lp_dynamic_analysis_scope' attribute for analysis.
Valid scopes would include hierarchies under the scope
specified with the '-vcd_instance' option to 'read_vcd' or
the whole hierarchy if '-vcd_instance' option was not
specified.
POPT-555 There is no information to display
in this scope.
Only those scopes which are present in the design
hierarchy or have been parsed by the 'read_vcd'
command can be monitored with the
'lp_dynamic_analysis_scope' attribute.
POPT-556 The start time and the end time
are equal.
The start and end times have not been specified by the
user and the VCD file does not have the initial value
specifications. Without initial value specifications, the
start time will be assumed to be the same as the first
value change specification or zero if no value change
specification exists. Specify the start and end times
explicitly or correct the VCD file to include proper value
change specifications.
POPT-999 Obsoleted clock-gating root
attributes.
Use the same attributes on design in the future.
PROTO_FT-1 Mapping was done using feasible
target feature due to attribute
proto_feasible_target.
This option MUST NOT be used for production, but only
for constraint debugging.
PROTO_FT-2 The -feasible_target_only option
with synthesize command is
obsolete.
Use proto_feasible_target attribute to enable the
feasible target feature.
PROTO_HDL-1 Extra port found during
instantiation is being added to the
module.
PROTO_HDL-2 Connecting complex ports in the
instance with bit-blasted or
field-blasted ports in the module.
PROTO_HDL-3 Ignoring case mismatch for
module instantiation in Verilog.
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May 2013 128 Product Version 12.2
PROTO_HDL-4 Ignoring case mismatch for port in
module instantiation in Verilog.
PTAM-100 Pin not specified. A pin was not specified on the command line, and no
default pins were found in test_signals directory.
PTAM-101 Power domain does not have a
shutoff signal.
The power domain for the isolation rule does not have a
shutoff signal. This power domain will not be included.
PTAM-102 Isolation rule pin traced to a
constant.
The isolation rule has a pin which traced to a constant.
The power domain for this pin will not be included for
this isolation rule.
PTAM-103 Isolation rule pin has no net/sink. The power domain for this pin will not be included for
this isolation rule.
PTAM-104 Pin already has value for attribute. Setting an attribute on a pin which already has an
existing value for the attribute.
PTAM-105 Could not find the specified power
mode in the CPF file.
Either correct the power mode name specified with the
'-power_mode' option and rerun the 'insert_dft ptam'
command or add the information for the specified power
mode to the CPF file and reload the CPF file using the
'reload_cpf' command.
PTAM-106 Isolation rule pin has no net/src. The power domain for this pin will not be included for
this isolation rule.
PTAM-107 Found constant when tracing to
locate a port.
Make sure the constant connection is expected.
PTAM-108 Invalid option specified. The option specified is not honored for this access type,
it will be ignored.
PTAM-109 Found tap instance, but
-connect_to_jtag not specified.
The tap will not be connected to. Specify the
-connect_to_jtag option to connect to the tap instance.
PTAM-110 Power domain for isolation rule
has an external shutoff condition,
this power domain is ignored.
The power domain for the isolation rule is ignored.
PTAM-111 All power domains for isolation rule
have been ignored due to external
shutoff conditions.
All power domains ignored.
PTAM-112 Power domain for srpg control
signal has an external shutoff
condition, this power domain is
ignored.
The power domain for the srpg control signal is ignored.
PTAM-113 Power shutoff signal and its driver
are in different power domains.
The power shutoff signal and its driver should be in the
same power domain.
PTAM-114 Power domain for isolation rule is
externally controlled, and does not
have a shutoff condition.
The power domain for the isolation rule is assumed
always on for test purposes.
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May 2013 129 Product Version 12.2
PTAM-115 All power domains for isolation rule
are externally controlled, this
isolation rule must be forced
inactive.
All the power domains for the isolation rule are
externally controlled and assumed always on for test
purposes.
PTAM-116 Power domain for srpg control
signal is externally controlled, and
does not have a shutoff condition.
The power domain for the srpg control signal is
assumed always on for test purposes.
PTAM-117 All power domains for srpg control
signal are externally controlled,
and do not have shutoff conditions,
this srpg control signal must be
forced inactive.
All the power domains for the srpg control signal are
externally controlled without shutoff conditions.
PTAM-118 Power domain for isolation rule is
externally controlled and has a
shutoff condition.
The power domain for the isolation rule is assumed
always on for test purposes.
PTAM-119 Power domain for srpg control
signal is externally controlled and
has a shutoff condition.
The power domain for the srpg control signal is
assumed always on for test purposes.
PTAM-120 Internal pin specified for the
shift_enable test_signal, but no
port specified.
Ensure the shift_enable internal pin is properly
controlled in the pin assign file or sequence file used for
mode initialization.
PTAM-121 The power domains for isolation
rule are a mixture of internally
controlled and externally
controlled. This isolation rule is
not supported.
All the power domains for the isolation rule must be
internally or externally controlled, not a combination.
PTAM-122 The enable_driver attribute is
empty for the isolation rule. No
logic is inserted for this isolation
rule.
Only isolation rules with a valid enable driver are
supported.
RCLP-204 File already exists. File will be overwritten.
RCLP-208 Could not launch Conformal Low
Power with default license.
Trying with license 'lpgxl'.
RETIME-103 The design has unmapped
combinational logic.
Synthesize it before retiming or specify the '-prepare'
option.
RETIME-110 Retiming not supported for
unresolved references.
Unresolved references cannot be handled by retiming.
RETIME-111 The design has mapped flops. Unmap the flops using retime_decompose command.
RETIME-301 The design contains latches. Latches cannot be handled by retiming.
RETIME-302 The design contains flops which
are not simple flops.
Flops can only be retimed if they are simple flops.
RETIME-303 The design contains flops with
connected inverted output pins.
Flops with inverted output pin cannot be handled by
retiming.
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Warning Messages
May 2013 130 Product Version 12.2
RETIME-304 The design contains flops with
control signals.
Set the attribute 'retime_async_reset' to 'true' to retime
flops with control signals.
RETIME-305 The design contains sequential
timing models.
Sequential timing models cannot be handled by
retiming.
RETIME-306 The design contains flops without
a clock source.
Make sure that all flops are connected to defined
clocks.
RETIME-307 The design contains preserved
retimeable flops.
Make sure that the flops you want to retime are not
preserved.
RETIME-309 The design contains flops with a
timing exception.
Flops with timing exceptions cannot be handled in
retiming.
RETIME-310 The design contains flops clocked
by negative phase.
Flops clocked by negative phase cannot be handled in
retiming.
RETIME-311 The design contains flops that are
part of a path group.
Retiming cannot maintain the path group on a flop. Set
the dont_retime attribute on a flop to keep it in the path
group.
RETIME-312 The design contains flops that
cannot be unmapped.
Flops that cannot be unmapped cannot be handled in
retiming.
RETIME-313 The design contains flops that
have a reset and set signal.
Flops can only be retimed if they have either reset or set
signals.
RETIME-314 The design contains flops with
data and control interaction.
Flops with data and control interaction cannot be
handled in retiming.
RETIME-315 The design contains scan flops
that cannot be unmapped.
Set unmap_scan_flops attribute to true to allow
unmapping scan flops.
RETIME-405 Timing exceptions are not
considered in the retiming
optimization.
Timing exceptions are not supported in retiming.
RETIME-409 The design contains flops with
multiple clock pins.
Flops with multiple clock pins cannot be handled in
retiming.
RMSENA-1 Ignored invalid inserted
synchronous enable.
Valid inserted synchronous enable signal should be an
output pin of a hierarchical instance, should not be
driven by constant, should not be unconnected and
should have at least one flop in its transitive fanout.
RPT_CG-3 Mapped portions of the design will
be ignored for preview.
Preview clock-gating only explores generic logic in the
design.
RPT_CG-4 All options of report clock_gating
cannot be used with the preview
option.
Options other than -clock, -clock_pin, -gated_ff and
-refresh are ignored if the -preview option is specified in
report clock_gating.
RPT_CG-5 Only the -detail and the -preview
options can be used with report
clock_gating -clock; all other
options will be ignored.
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Warning Messages
May 2013 131 Product Version 12.2
RPT_CG-6 Only the -detail and the -preview
options can be used with report
clock_gating -clock_pin; all other
options will be ignored.
RPT_CG-7 The -cg_instance has been used;
all other options will be ignored.
RPT_CG-8 The -refresh option works only
with the -preview option; the
-refresh option will be ignored.
RPT_CG-10 Found overlapping ranges in the
step input.
For instance, consider {{1 5} {2 6}} as the input. Values
in the histogram for the overlapping range {3 5} will be
counted more than once.
RPT_CWD-101 Invalid operator passed with
-operator option.
RPT_CWD-102 Invalid component passed with
-component option.
RPT_DP-100 The filename, column and line
number information will not be
available in the report.
You must set the 'hdl_track_filename_row_col' attribute
to 'true' (before elaborate) to enable filename, column,
and line number tracking in the datapath report.
RPT_DP-103 Information about datapath
subdesign is incomplete.
RPT_DP-104 The information about embedded
operators in the csa tree will not be
displayed.
The attribute rtlopto_group_info returned null. This will
prevent displaying embedded operators for the csa tree.
RPT_DP-106 Ignoring the user specified width
for the invalid report datapath
column name.
The option '-max_width' is used to control the width of
the various columns in report datapath output. The valid
columns names are Operator, Signedness, Inputs,
Outputs, CellArea, Line, Col, Filename.
RPT-4 The legacy option
'-build_power_models' is used.
Option '-build_power_models' should be mutually
exclusive to other options, and it will be obsolete in a
next major release. Use command
'build_rtl_power_models' instead to build detailed
models for RTL power analysis.
RPT-5 Invalid option specified. Not supported with -rtl option.
RPT-10 No clock. Clock is not defined.
RPT-23 Instance ignored for report. There is no more help available in this message. If the
help in this message was insufficient, contact customer
support with this message ID.
RPT-38 Cannot estimate clock tree power. Specify the missing information for clock tree power
estimation.
RPT-39 Estimated die width and height not
specified.
Specify them using -width and -height command line
options or set them implicitly by reading in a floorplan
using the read_def command.
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Warning Messages
May 2013 132 Product Version 12.2
RPT-41 Power of clock cannot be
estimated.
The clock does not drive any flops. Tracing from the
source of the clock did not find any flops.
RPT-900 Both the driver and load pins/ports
are not on the same net.
It is not possible to calculate the net delay between both
the pins/ports.
RPT-903 The specified pin/port is not a valid
driver.
This pin/port will not be considered during delay
calculation.
RPT-904 The specified pin/port is not a valid
load.
This pin/port will not be considered during delay
calculation.
RPT-910 Cannot calculate delay/slew for
this tech element.
The library information is encrypted for this tech
element and hence the delay/slew information cannot
be displayed.
RPT-911 Cannot calculate delay/slew for
this tech element.
The instance under consideration is not a tech element.
RPT-912 File already exists. File with the given name already exists. It will be
overwritten.
RPT-913 Not mapped to State Retention
cell.
Reported cells are not mapped to State Retention cell.
SAIF-2 Path not found.
SAIF-4 Unable to assert activity on net/
port.
Make sure that the specified probability and toggle rate
have valid values.
SAIF-5 Duration/time unit not specified.
SAIF-6 Invalid scaling factor specified.
SAIF-7 Invalid Weight factor specified. Setting weight factor to default value(1).
SDC-200 Unsupported SDC command. The current version does not support this SDC
command and ignores it. However, future versions may
be enhanced to support this command. This SDC
command will be added to the Tcl variable
$::dc::sdc_unsupported_commands_write_sdc. The
contents of this variable will be written out during
write_sdc.
SDC-201 Unsupported SDC command
option.
The current version does not support this SDC
command option. However, future versions may be
enhanced to support this option.
SDC-208 Could not find requested search
value.
Use the 'cd' and 'ls' commands to browse the virtual
directories to find the object because the specified
name and/or location does not exist.
SDC-209 One or more commands failed
when these constraints were
applied.
You can examine the failed commands or save them to
a file by querying the Tcl variable
$::dc::sdc_failed_commands.
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Warning Messages
May 2013 133 Product Version 12.2
SDC-214 SDC command overridden. The indicated command is already defined. To get the
built-in SDC command behavior, remove or change the
name of the existing command with the 'rename'
command.
SDC-219 No output is available to return.
SDC-229 Obsolete SDC command option or
object type.
This option or object type will soon be obsolete for the
indicated SDC command. Check the SDC command
and contact Cadence customer support if you believe
this option or object type should be supported.
SDC-230 The 'read_sdc' command has
been called with the no_compress
option on a large design.
This could result in huge runtime during synthesis. Use
'read_sdc' without no_compress to avoid any potential
runtime increase.
SRPG-100 Unused message.
SRPG-101 Unused message.
SRPG-102 Unused message.
SRPG-103 Unused message.
SRPG-110 Unused message.
SRPG-111 Unused message.
SRPG-112 Unused message.
SRPG-120 Unused message.
ST-111 Failed to establish connection with
super-threading server.
RC is exiting super-threading mode and failed to
establish a connection with a CPU server process. This
could be due to a high cpu load on that host or a
networking issue. If a job queueing mechanism (such
as LSF) is being used, perhaps the job was held up in
the queue.
ST-113 A connection to a super-threading
server has been lost unexpectedly.
Probably some error happened in
the background job. Rerun after
setting the attribute
'super_thread_debug_directory'
for more information.
The tool will attempt to continue without that server.
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Warning Messages
May 2013 134 Product Version 12.2
ST-114 Rsh does not seem to work to one
of the super-threading hosts.
Likely causes for this problem are: 1) the host name
was misspelled or 2) rsh to the given machine requires
a password. You can see if the password is required by
executing the unix command 'rsh <host>' and seeing if it
prompts you for a password. If it does prompt you for a
password, you should read the unix manpage for the
rsh command to eliminate the password requirement.
This usually involves adding a file ~/.rhosts to your
home directory. Until you can rsh to the host without a
password prompt, that host will not work as a super
thread server.
ST-115 Executing jobs using the
foreground process until a
background server becomes
available.
No background server processes have been detected
yet. The most common cause for this is that a queueing
mechanism (such as LSF) is being used and the jobs
are waiting in a queue.
ST-116 Not enough licenses are available
for all of the super-thread servers
requested.
Super-threading will continue with fewer servers than
requested.
ST-118 The full path to the current
executable could not be
determined.
This is unexpected. Report the problem to Cadence.
As a workaround try using an absolute pathname when
invoking RC.
ST-119 Super-threading attempted to
launch a server process into a job
queueing system, but the launch
command failed.
Either the launch command returned error status, or it
wrote information to its stderr filehandle. Double-check
that the root attribute 'super_thread_batch_command'
has been set correctly and that any environment
variables needed by the job queueing system have
been set.
ST-122 Cannot set attribute
'auto_super_thread' to 'true'.
Either RC is not running with an 'RTL_Compiler_Ultra'
or 'RTL_Compiler_Physical' or
'C_to_Silicon_Compiler_L' license, this host has a
single processor or RC could not determine the number
of processors on this host. You can still achieve the
same effect by typing 'set_attribute
super_thread_servers {localhost localhost} /'.
ST-152 File too large for super-threading
cache.
A file (either send or result script) is larger than 10Mb
and will not be stored in the super-threading cache.
ST-155 A RTL_Compiler_Ultra is required
to enable super-threading caching
and none is available.
Optimization will continue without caching.
STRUCT-110 GBB.
STRUCT-111 Variable has multiple drivers.
STRUCT-112 Connection too wide.
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Warning Messages
May 2013 135 Product Version 12.2
STRUCT-113 There are multiple top-level
modules in this design.
If there is more than one top-level module in the
structural netlist, you must specify the name of the
top-level module using the -top option. For example,
`read_netlist -top mytop1 $file_list'.
STRUCT-114 Multiple ports with same name in
module definition.
Duplicate ports will be ignored.
STRUCT-115 Inout ports of an instance cannot
be driven by supply0/supply1.
Check port connectivity of an instance.
STRUCT-116 Detected an empty module. Empty modules are treated as logic abstracts by
default. A logic abstract is an unresolved reference with
defined port names and directions. Use 'set_attribute
hdl_infer_unresolved_from_logic_abstract false /' to
treat an empty module as a defined module.
STRUCT-117 Detected an instantiation of a
parameterized module.
Instances of a parameterized module will be linked to
the corresponding module with default parameter
values. Overriding parameter values are not supported
in the netlist reader flow.
STRUCT-142 Linking to Physical only cell in
absence of timing library. Paths
involving these cells will not be
timed.
Struct: Read in .lib file for timing information.
STRUCT-147 An attempt to replace the top
module in the user netlist by a
library cell with the attribute setting
'hdl_use_techelt_first' set to TRUE
was ignored in mixed input
elaboration flow (read_hdl -netlist,
elab).
Struct: Remove the attribute setting
hdl_use_techelt_first.
TCF-2 Path not found.
TCF-4 Unable to assert TCF on net/port. Make sure that the specified probability and toggle rate
have valid values.
TCF-5 Duration/time unit not specified.
TCF-6 Invalid scaling factor specified.
TCF-7 Invalid Weight factor specified.
TCF-8 Invalid instance(s) specified. Multiple instances present in design for the instance
arg. Provide an unambiguous path with -instance
option.
TCF-11 Found a vcd2tcf-generated TCF
file.
The TCF parser may not be able to parse the contents
of this TCF file correctly. Use the 'read_vcd' command
to directly read in the original VCD file.
TCF-14 Invalid tcf instance(s) specified. Multiple instances present in tcf for the tcf instance arg.
Provide an unambiguous path with -tcf_instance option.
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Warning Messages
May 2013 136 Product Version 12.2
TCF-15 No Net/Pin is annotated. Check the TCF file OR try '-instance' / '-tcf_instance'
option.
TIM-11 Possible timing problems have
been detected in this design.
Use 'report timing -lint' for more information.
TIM-20 A combinational loop has been
found.
You can set case constants or disable cell arcs to break
a combinational loop. For detailed information see the
'Setting Constraints and Performing Timing Analysis
Using Encounter RTL Compiler' documentation.
TIM-40 Could not report Elmore delay. Make sure use 'set_attribute ple_mode placement /'
first.
TIM-41 The pin specified is not a leaf pin. Only leaf driver and load will be accepted for reporting
Elmore delay.
TIM-42 Could not find location of this pin. Make sure read DEF file first.
TIM-43 An internal failure was identified
during Timing Analysis.
To avoid this problem, turn off the feature to break
timing path by mode by using 'set_attribute
enable_break_timing_paths_by_mode false /' first.
TIM-50 Skipping budgeting due to non
default behavior of hidden attribute
simple_latch_analysis.
Avoid setting simple_latch_analysis to false.
TIM-87 The specified wireload string
matches both a mode and a
wireload model name. The mode
will be used.
If instead you want the wireload model to be used,
specify the full path to the model (as returned by the
find command).
TIM-101 Replacing existing clock definition. A new clock has been defined with the same name as
an existing clock.
TIM-104 Removing clock source. If this clock source is being removed unexpectedly, you
should investigate the cause for its removal. Possible
causes would be that an instance in the design is being
deleted, or a hierarchical instance is being ungrouped.
TIM-108 Clock skew attributes are not valid
on this type of object.
Clock skew attributes cannot be set on output ports,
logic constants, or unmapped combinational pins.
TIM-118 Ungrouping an instance will
remove timing break points.
The 'break_timing_paths' attribute is set to 'true' on an
ungrouped hierarchical instance.
TIM-126 The given attribute is not valid on a
port of this direction.
Check the port and attribute to see which one was
incorrect.
TIM-129 Case analysis is not supported on
this type of object.
Only input ports, hierarchical pins, output pins of
sequential instances, or pins of mapped/unmapped
logic are currently supported.
TIM-130 Logic constant is not supported on
this type of object.
Only input ports are currently supported.
Message-ID Title Help
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Warning Messages
May 2013 137 Product Version 12.2
TIM-136 Unresolving a hierarchical
instance which has timing paths
broken on one of its pins.
The value of the 'break_timing_paths' attribute has
been set to 'false' on this pin.
TIM-137 The timing paths cannot be broken
at the specified pin.
Only pins of hierarchical or leaf instances can be used.
TIM-139 An inconsistency in attribute
values has been detected.
Check whether the new value that was specified is
indeed correct.
TIM-140 Only arcs of mapped instances
can be disabled.
Map the design to the technology library before
disabling a timing arc for a specified instance. See
'Disabling Timing Arcs' in the 'Setting Constraints and
Performing Timing Analysis Using Encounter RTL
Compiler' for more information.
TIM-293 Could not set the default mode. Default mode can be set only once. It cannot be
changed.
TIM-308 Removing exception that can no
longer be satisfied.
This occurs when from, through, or to points for the
exception are deleted.
TIM-309 Cannot unpreserve instance since
exceptions or clocks are active on
its pins or on itself.
In order to unpreserve the instance the exceptions or
clocks will have to be removed.
TIM-311 Invalid startpoint. The specified from_point will be treated as a
through-point instead.
TIM-312 Invalid endpoint. The specified to_point will be treated as a through-point
instead.
TIM-314 The objects specified are from
different designs.
Only objects within the same design may be specified.
Use the 'find' command to precisely specify the
intended objects.
TIM-315 Invalid timing exception attribute. The 'user_priority' attribute can only be used for
'path_adjust' exceptions. Use the 'delay_value' attribute
to return the delay constraint for a 'path_delay' timing
exception.
TIM-316 At least one from-point is not a
timing startpoint.
If the from-point does not become a valid timing
startpoint later on (perhaps as a result of a
set_max_delay constraint or set_disable_timing), then
the exception will not be applied to this from-point.
TIM-317 At least one to-point is not a timing
endpoint.
If the to-point does not become a valid timing endpoint
later on (perhaps as a result of a set_max_delay
constraint or set_disable_timing), then the exception will
not be applied to this to-point.
TIM-328 Cannot unpreserve the instance
since a timing case constant has
been set on one of its pins.
In order to unpreserve the instance, the attribute
'timing_case_logic_value' must first be set to 'no_value'
on the indicated pin.
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Warning Messages
May 2013 138 Product Version 12.2
TIM-332 Removing a clock generation
point.
If this clock generation point is being removed
unexpectedly, you should investigate the cause for its
removal. Possible causes would be that an instance in
the design is being deleted, or a hierarchical instance is
being ungrouped.
TIM-333 Ungrouping an instance will cause
case values on its pins to be
deleted.
TIM-334 Deleting case value on pin.
TIM-337 The waveform generation script for
a clock object encountered an
error.
The clock does not have a valid waveform at this time.
The 'generate_script' attribute on the clock is the script
that failed to execute.
TSY-37 No JTAG Instructions defined. A set of JTAG instructions has not been defined and
therefore, no BSDL file will be generated. In order to
generate a BSDL file, define a set of JTAG instructions
using the 'define_dft jtag_instruction' command and
also be sure to define the ports that will have boundary
cells inserted on them upon execution of 'insert_dft
boundary_scan'.
TSY-106 Removed a JTAG port. The options '-tck, -tdi, -tdo, -tms, -trst' of the 'insert_dft
boundary_scan' command have precedence, and may
result in the removal of existing JTAG ports when their
previous definitions are inconsistent with the usage of
the port specified with its TAP specific option.
TSY-382 Clock gating macros cannot be
mapped to clock gating integrated
cells.
Clock gating integrated cell of type
'latch_posedge_precontrol' not found in target libraries.
TSY-391 Missing pin on test receiver cell. Ensure that all test receiver cells that require boundary
cell insertion have the required test receiver
'trcell_acmode' pin and either a 'trcell_clock' or
'trcell_lsen' pin specified. Boundary scan verification will
fail without control of these pins.
TSY-394 Found an I/O cell keyword in
speclist file.
Instead of using the I/O cell speclist keywords, the
preferred approach is to use the instance-level
'user_from_core_data', 'user_to_core_data', and
'user_from_core_enable' attributes to identify these pins
for I/O cells with single or multiple PAD pins. The
instance-level attributes will take precedence over the
speclist keywords.
TSY-396 Clock gating macros cannot be
mapped to user defined clock
gating integrated cells.
User defined clock gating integrated cell is not of type
'latch_posedge_precontrol'.
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Warning Messages
May 2013 139 Product Version 12.2
TSY-402 Unconnected pin
'JTAG_MODULE/
JTAG_ENABLE_TDO'.
The JTAG Macro will be inserted without pad logic.
Having also specified the additional option
'-dont_create_DFT_TDO_enable_port', the
DFT_TDO_ENABLE port will not be created. Hence,
the 'JTAG_MODULE/JTAG_ENABLE_TDO' pin which
would normally be connected to this port will be left
unconnected in the design. To pass boundary scan
verification, it is the user's responsibility to connect the
'JTAG_MODULE/JTAG_ENABLE_TDO' pin to the
appropriate logic in the design to control the three-state
pin of the JTAG TDO pad.
TSY-471 No PAD or PINMAP information
provided.
The PIN_MAP_STRING attribute in the BSDL file maps
a design port to its physical package pin. This
information needs to be provided through either the
PAD or PINMAP keywords in the IOSpecList file or
through the Pinmap file. Since this information was not
provided, the specified attribute in the BSDL file will be
left unassigned. Specify the PAD or PINMAP
information if the PIN_MAP_STRING attribute must be
assigned in the BSDL.
TSY-472 Unable to determine pin on I/O
cell.
Identify the input, output, and enable pins of the I/O cell
by setting the following attributes , using the
'set_attribute' command, on the I/O cell instance/pin
that has the liberty attribute 'is_pad', set to 'true'. Set the
'user_from_core_data' attribute to the input pin name
value, the 'user_to_core_data' attribute to the output pin
name value, and the 'user_from_core_enable' attribute
to the enable pin name value.
TSY-473 IEEE 1149.1 TRST port not found. The TRST port is not a mandatory TAP port. But it is
necessary to ensure that during power-on reset, the
TAP controller starts in a known state. If this port is not
present then the user must connect the JTAG_POR pin
on the TAP controller to a power-on reset signal to
ensure predictable behavior. If the TRST port was
intentionally omitted, then no response is needed. But
if this was not the intention, then the TRST port must be
specified and the command rerun.
TSY-474 IEEE 1149.1 TRST port defined as
active high test_mode.
The TRST port is not a mandatory TAP port. But if
present, it is supposed to be defined as an active low
test signal.
TSY-477 Unable to determine functional use
of iocell instance.
All the functional pins on an iocell instance must have
nets attached to them and these nets must be present
and hooked up at the top-level of the design. A
boundary cell will only be inserted on a functional net
existing at the top-level of the design. Ensure the iocell
is functionally connected to the core logic and the
functional nets connected to the iocell must be present
in the top-level of the design.
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Warning Messages
May 2013 140 Product Version 12.2
TSY-478 Unable to determine iocell
connected to port.
Every functional port on the design must have an iocell
connected to it and this iocell must then be connected
to the functional logic. The specified port either does
not have an iocell connected to it, or else the connected
iocell was not recognized. The port must be connected
to a pin on the iocell that has the liberty attribute
is_pad=true. Ensure an iocell is functionally connected
to the port and the core logic. Ensure the iocell pin
connected to the port has the liberty attribute
is_pad=true on it.
TSY-479 Port connects to non-pad pin. Every functional port on the design must have an iocell
connected to it and this iocell must then be connected
to the functional logic. The specified port is connected
to a pin on the iocell that does not have the liberty
attribute is_pad=true. Ensure the iocell pin connected to
the port has the liberty attribute is_pad=true on it.
TSY-482 Unable to determine functional use
of port.
All the functional pins on an iocell instance must have
nets attached to them and these nets must be present
and hooked up at the top-level of the design. A
boundary cell will only be inserted on a functional net
existing at the top-level of the design. Ensure the iocell
is functionally connected to the core logic and the
functional nets connected to the iocell must be present
in the top-level of the design.
TSY-483 JTAG_TRST pin on
JTAG_MACRO is unconnected.
The JTAG_TRST pin on the JTAG_MACRO must ideally
be connected to a top-level TRST port, to ensure that
during power-on reset, the TAP controller starts in a
known state. Alternatively, a power-on reset signal can
be connected to the JTAG_POR pin on the
JTAG_Macro to reset the TAP controller. If neither of
these options are available, both the JTAG_TRST pin
and the JTAG_POR pin will be tied to their inactive
value of logic 1. If the JTAG_TRST pin is desired to be
tied to logic 1 value, then no response is needed. But if
this is not the intention, then either a top-level TRST
port or a power-on reset signal must be specified to the
'insert_dft boundary_scan' command.
TSY-484 Core side pin on iocell already
connected to TAP port.
The core side pin of the iocell on the specified TAP port
is already hooked up to some net. Hence it is assumed
that the specified TAP port is already connected either
to a JTAG_MACRO pin or to some other controlling
logic. Hence no additional connections will be made. If
the existing connection is correct, then no response is
needed. If not, then ensure that there is no net
connected to the core side pin of the iocell on the
specified port.
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Warning Messages
May 2013 141 Product Version 12.2
TSY-486 The TDO port on the TAP
controller is already connected.
The core side pin of the iocell on the specified TAP port
is already hooked up to some net. Hence it is assumed
that the specified TAP port is already connected either
to a JTAG_MACRO pin or to some other controlling
logic. Hence no additional connections will be made.
Ensure that the existing connection is correct. The user
must manually connect the specified iocell pin to the
JTAG_MACRO.
TSY-487 Already connected core pin. The core pin of the iocell on the TDO TAP port is
currently connected to the core or some other logic.
The preserve_tdo_connection command line option
was not specified and therefore the existing connection
will be broken and the iocell pin will be connected to the
JTAG_MACRO. Ensure that the existing connection is
correct.
TSY-550 Port already specified with another
keyword.
The keyword value specified in the speclist will be
overwritten with a new value obtained from information
inferred from the command line. Ensure that the
information in the speclist properly matches the options
specified on the command line.
TSY-589 Port must have a sys_enable port
defined.
The sys_enable attribute is required for jtag_ports with
bidirectional or tristate pads. The sys_enable pin
controls the enable pin of bidirectional and tristate pads.
System or functional I/O enable pins can be driven
either from internal core logic or from another signal
coming on-chip through a top-level port.
TSY-815 Ignoring port specified in
IOSpecList.
Tap ports which are already defined will be ignored if
present in the IOSpecList.
TUI-25 The attribute is not applicable to
the object.
To see the usage/description for this attribute, type
'set_attribute -h <attr_name> *'.
TUI-30 Obsolete attribute. This attribute does not affect the tool behavior and will
be removed in next major release. Remove all usages.
TUI-31 Obsolete command. This command is no longer supported.
TUI-32 This attribute will be obsolete in a
next major release.
TUI-34 Disabled attribute. This attribute does not affect the tool behavior.
TUI-37 This command will be obsolete in
a next major release.
TUI-42 This command option will be
obsolete in a next major release.
TUI-43 The 'prune_unused_logic' attribute
can only be set on hierarchical
pins.
The given pin is not hierarchical.
TUI-51 Bad options to 'find' command. Review help text for the 'find' command.
Message-ID Title Help
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Warning Messages
May 2013 142 Product Version 12.2
TUI-57 Directory was deleted. If an operation deletes the current directory (with the
'rm' command), the current-directory will subsequently
be reset to the root directory.
TUI-67 The attribute is not applicable to
the object.
To see the description and usage for this attribute, type
'set_attribute -h <attr_name> *'.
TUI-70 The attribute has no default value. Check its default function.
TUI-77 Inefficient use of 'find' searching
from root directory.
Rewriting 'find' command as 'find <path> -object
<name>' is more efficient than 'find / -object <path>/
<name>'.
TUI-78 An inefficient number of
super-thread servers was
specified.
Specifying only one super-thread server will usually
slow down synthesis. One exception to this would be if
you are running on a 64-bit machine for capacity
reasons and are using a faster 32-bit machine as the
server. Otherwise you are probably better off not using
super-threading at all (by setting the root attribute
super_thread_servers to {}) or by specifying two or
more servers.
TUI-79 Multiple names specified for 'find'
command.
'find' no longer allows multiple names by default. To
enable this behavior set the
'find_takes_multiple_names' root attribute to true.
TUI-82 Enabling message severity
downgrade.
TUI-92 Cannot set probability or toggle
rate on a constant net.
TUI-93 A toggle percentage greater than
1.0 is specified.
A large toggle percentage should not be assigned
except when the circuit has lots of glitches.
TUI-94 The asserted TCF on an undriven
hierarchical pin will not be used for
TCF propagation.
TUI-205 Option ignored.
TUI-211 Cannot preserve non-sequential
instances.
Only sequential leaf instances can be preserved to
map_size_ok.
TUI-213 Cannot preserve net without a
non-constant driver.
Use a 'ls -a' to confirm that the net cannot be preserved.
TUI-220 The 'clock_ports' command did not
find any clock ports.
This is usually due to the design being combinational or
having clock gating or clock generation logic.
TUI-224 Specified shift values are
equivalent to the default timing
relationship.
Unless this exception is intended to override prior
exceptions, it will have no effect.
TUI-249 Cannot preserve internal pin. .
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Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 143 Product Version 12.2
TUI-253 At least one of the specified ports
is not valid for the given external
delay.
Use the 'external_delay' command to specify and output
delay on output ports or to specify an input delay on
input ports. See the 'Specifying the Timing and Delay
Constraints' Chapter in the 'Setting Constraints and
Performing Timing Analysis Using Encounter RTL
Compiler' manual for detailed information.
TUI-255 Resetting preserve attribute
because an unmapped instance is
being inserted.
TUI-266 The requested object name is
already in use.
A different name for the object is chosen to avoid a
name conflict. By storing the newly created object in a
variable you can access it directly without having to look
for it by name. The code to do that would look
something like this: 'set var [edit_netlist ...]'.
TUI-268 Cannot resize an unmapped (i.e.
hierarchical or generic) instance.
Map the design first or specify a mapped instance.
TUI-273 Black-boxes are represented as
unresolved references in the
design.
To resolve the reference, either load a technology
library containing the cell by appending to the 'library'
attribute, or read in the hdl file containing the module
before performing elaboration. As the design is
incomplete, synthesis results may not correspond to the
entire design.
TUI-281 The requested product license is
not currently available.
TUI-288 The requested feature is not
available with current license.
Choose a new startup license with more capability.
TUI-295 Cannot dedicate fully preserved
module.
Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
TUI-298 The user visible name of the net is
different from the requested name.
The given net is connected to a (sub)port, hence
derives its name from the (sub)port.
TUI-299 Ignoring the in_prefix/out_prefix
option(s).
You can remove these unused options.
TUI-302 The design name specified
already exists for another design.
A new name is being created
using the derived instance and its
sub-design names.
The derive_environment command will return the newly
created design object. That result can be examined to
see what the new design's name is.
TUI-305 The constant connectivity is not
the same on other instantiations of
this sub port.
To resolve this either make sure that the same constant
is connected to all instantiations of the port or dedicate
the sub design of the instance with the 'edit_netlist
dedicate_subdesign' command.
TUI-501 Unknown command.
TUI-502 Command already exists.
Message-ID Title Help
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Warning Messages
May 2013 144 Product Version 12.2
TUI-503 Value is out of legal bounds.
TUI-504 Could not open file. Check permissions of the file and directory.
TUI-602 Invalid instance for setting user
speed grade.
TUI-607 Ignored the 'map_to_mux'
instance attribute because the
library does not have any usable
mux cells.
To map this instance to a mux, either load a library with
a mux cell that is not specified 'dont_use', or set the
'avoid' attribute of a library mux cell to 'false'.
TUI-613 The attribute is not applicable to
the object.
The user_speed_grade is only applicable to datapath
subdesigns.
TUI-666 Potential variable name conflict. Some Tcl variables are used internally to enable
features that are not officially supported. If this variable
was set as a part of a script that was not intended to
change the tool's behavior (perhaps as a temporary
variable to store a command result), choose another
variable name. Otherwise, this variable name could
produce unintended results. If you are setting this
variable to change the tool's behavior, this warning can
be ignored.
TUI-667 Variable will be obsolete in a future
release.
The use of a Tcl variable will be discontinued in a future
release.
TUI-668 Internal Tcl control variable has
been changed.
Some Tcl variables are used internally to enable
features that are not officially supported.
TUI-699 Ungrouping a hierarchical instance
which is also a power domain
boundary.
The tcl variable to force ungrouping of a hierarchical
instance is turned on and has caused this ungrouping.
This behavior is neither recommended nor supported. It
can lead to serious power intent violations and can
cause the tool to crash.
TUI-701 Changing power domain in CPF
flow.
Changing power domain in CPF flow can invalidate the
intent of original CPF file.
TUI-702 Unused message.
TUI-703 Unused message.
TUI-705 Unused message.
TUI-706 Unused message.
TUI-708 Unused message.
TUI-718 Unused message.
TUI-719 Creating isolation rules in CPF
flow.
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Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 145 Product Version 12.2
TUI-721 Base mode is not set. You should set the 'base_mode' attribute on a design
before invoking the 'synthesize' command if the
'library_domain_by_mode' attribute is set on any power
domain.
TUI-722 The library domain of some
instances were changed.
The library domain was changed to the library domain
specified for the mode by the 'library_domain_by_mode'
attribute.
TUI-724 Cannot start DVFS flow.
Continuing without DVFS support.
Make sure that all library domains have at least one
usable inverter and one usable 2-input AND, NAND, OR
or NOR gate.
TUI-727 The specified instance was
converted to black box as suitable
library cell was not found new
library domain.
Make sure that the target library domain has a library
cell with same name, same number of pins, same pin
names and same pin directions.
TUI-733 Cannot translate constraints from
one voltage to another. DVFS
synthesis will not be performed.
The supply voltage of this library is less than the
estimated threshold voltage of this library. This is
physically impossible. Check the nominal voltage of the
library.
TUI-734 Unused message.
TUI-735 Unused message.
TUI-738 Timing analysis will be done by
mode.
Worst paths will be shown in each mode for all modes.
TUI-754 Cannot define rule for internal pin. .
TUI-755 Cannot define an isolation rule for
the specified pin/port.
You should not list a pin or port as the enable driver and
as a pin to be isolated. As a result, the isolation rule is
created with the pin specified to drive the enable signal,
but the pin is not added to the list of pins to be isolated.
TUI-756 Cannot set enable_driver attribute
for the pin/port.
Same pin/port cannot be in both pins and enable_driver
attribute for the isolation rule.
TUI-758 Cannot define an isolation rule for
the specified enable driver.
Enable driver belongs to different netlist than the current
design.
TUI-759 Cannot define an isolation rule for
the specified pin/port.
The pin/port belongs to different netlist than the current
design.
TUI-760 Unused message.
TUI-761 Removing isolation rule. Removing the libcell makes the isolation rule invalid if it
depends on this libcell.
TUI-762 Disabling the isolation rule. Removing the dedicated pin makes the isolation rule
disabled.
TUI-763 Cannot define isolation rule. The scope must either be design or a hierarchical
instance.
Message-ID Title Help
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Warning Messages
May 2013 146 Product Version 12.2
TUI-764 Cannot define isolation rule. The vdir for '-within_hierarchy' must be a hierarchical
instance.
TUI-765 Creating isolation rules in design.
TUI-771 Cannot define level shifter rule. The vdir with '-within_hierarchy' must be a hierarchical
instance.
TUI-774 Unused message.
TUI-775 Removing level shifter rule. Removing the libcell makes the level shifter rule invalid
if it depends on this libcell. Rule is removed when 'cells'
list becomes empty.
TUI-776 Disabling the level shifter rule. Removing the dedicated pin of a level shifter rule makes
the rule invalid.
TUI-779 Cannot define level shifter rule as
pin's netlist and rule's netlist does
not matches.
Level shifter rules are defined for pins belonging to
same netlist.
TUI-780 Cannot define level shifter rule as
power domain's netlist and rule's
netlist does not matches.
Level shifter rules are defined for power domains
belonging to same netlist.
TUI-781 Cannot define level shifter rule. If '-cpf_pins' is given, it must contain at least one valid
pin|port.
TUI-782 Cannot define level shifter rule. If '-from_power_domain' is given, it must contain at least
one valid power domain.
TUI-783 Cannot define level shifter rule. If '-to_power_domain' is given, it must contain at least
one valid power domain.
TUI-784 Cannot define level shifter rule. The threshold value must be positive.
TUI-785 Cannot define level shifter rule. The scope must either be design or a hierarchical
instance.
TUI-789 No library domains present in
loaded design.
TUI-790 Cell(s) specified with rule is/are
not valid.
TUI-793 Cannot find a suitable inverter.
TUI-794 Could not find libcell(s) specified
with rule.
Skipping insertion for this rule.
TUI-795 Cannot find a suitable level shifter.
TUI-797 Cannot find a suitable enabled
level shifter.
TUI-800 Missing macro model port name in
CPF.
Design ISO rule will apply on this port/pin.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Warning Messages
May 2013 147 Product Version 12.2
TUI-801 Duplicate power domain command
in Macro model.
Use the 'create_power_domain -name' command to
create a unique power domain name.
TUI-850 Not a valid IO cell pad port. Correct 'define_pad_cell -pad_ports' command with
correct pad port names.
TUI-851 Creating isolation rule in Macro
Model.
TUI-852 Looking for Enabled level shifter
cell.
TUI-854 Looking for Level shifter cell.
TUI-855 Looking for Isolation cell.
TUI-859 Isolation rule does not specify
'-isolation_signal' with it.
TUI-861 No isolation rules defined.
TUI-862 No level shifter rules defined.
TUI-900 Elaborated designs already exist
in memory.
See 'set_attribute -h uniquify_naming_style root' for
help.
UTUI-100 Cannot ungroup preserved
instance.
Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
UTUI-103 Cannot ungroup instance with
exception on a bidirectional pin.
To ungroup this instance move the exception to a
different pin or use 'edit_netlist ungroup'.
UTUI-114 No usable buffer available in the
library.
The buffers are present in the library but the avoid or
preserve attribute on them is set to true preventing them
from being used.
UTUI-115 No buffer available in the library. The library does not contain any buffer cells.
UTUI-116 No usable inverter available in the
library.
The inverters present in the library have the avoid or
preserve attribute on them set to true preventing them
from being used.
UTUI-117 No inverter available in the library. The library does not contain any inverter cells.
UTUI-118 Always-on buffer is not found to
remove assigns on power domain
boundaries.
Check if the always-on buffer is provided and is not
avoided.
UTUI-121 Incorrect instance specified. This instance will not be removed as it is not a loop
breaker.
UTUI-127 Conflicting options
'-skip_unconstrained_paths' and
'-dont_skip_unconstrained_paths'
used.
Option '-dont_skip_unconstrained_paths' will override
the default option '-skip_unconstrained_paths'. Use any
one option.
UTUI-128 Looking for inverters instead. Looks for inverters as there are no usable buffers in
library.
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Warning Messages
May 2013 148 Product Version 12.2
UTUI-129 Use -no_buffers_use_inverters
option to look for inverters in
library.
Option -no_buffers_use_inverters looks for inverters if
there are no buffers in library.
UTUI-131 No inverters will be added. Libcell specified with -buffer_or_inverter option is buffer.
UTUI-204 No tie hi/lo cell found for tiecell
insertion.
Possible reason is that the tiecells in library are avoided,
if present. Unavoid them to use for tiecell insertion.
UTUI-205 Cannot identify the output pin of
tiecell.
UTUI-208 Skipping tiecell insertion on
design/subdesign because of
preserve.
Set 'ui_respects_preserve' attribute to 'false' or
'ignore_preserve_in_tiecell_insertion' attribute to true to
insert tiehilo cells ignoring the preserve.
UTUI-209 Skipping tie hi/lo cell insertion for
module.
UTUI-218 Adding unplaced Tie-cell.
UTUI-219 Libcell invalid for consideration as
tie-cell.
VCD-4 None of '-static' or '-activity_profile'
options given.
The '-static' option has been selected by default. To
specify explicitly, use at least one of '-static' or
'-activity_profile' options.
VCD-5 Start time specified is less than
'0.0'.
Always specify a start time through the '-start_time'
option as greater than or equal to '0.0' to do meaningful
power analysis.
VCD-6 End time specified is less than
'0.0'.
Always specify an end time through the '-end_time'
option as greater than '0.0' to do meaningful power
analysis.
VCD-14 Output directory to dump SST2
data does not exist.
You can create a directory to dump data with the 'mkdir'
command in UNIX.
VCD-25 Both -module and -instance
supplied.
Provide either -module of -instance with the command.
The option -module is deprecated will be obsolete soon,
use -instance instead.
VCD-26 Both -vcd_module and -vcd_scope
supplied.
The option -vcd_module had been renamed as
vcd_scope, we support both at present but vcd_module
will soon be discarded.
VCD-27 Use -vcd_scope option instead of
-vcd_module.
The option -vcd_module had been renamed as
vcd_scope, we support both at present but vcd_module
will soon be discarded.
VCD-28 Use -instance option instead of
-module.
The option -module is deprecated will be obsolete soon,
use -instance instead.
VCD-29 Invalid scaling factor specified.
VHDL-217 Cannot redefine existing vhdl
library.
To specify that vhdl library 'lib2' is an alias for 'lib1', do:
read_hdl -vhdl -library lib2=lib1 <files>.
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Warning Messages
May 2013 149 Product Version 12.2
VHDL-218 Invalid Entity. Entity is invalid because it is potentially out-of-date with
respect to packages used. Check the specified entity
and package and re-analyze the entity using the
'read_hdl -vhdl filename' command.
VHDL-230 Deleting previously analyzed units
due to redefinition of VHDL
libraries.
Redefining a VHDL library after using 'read_hdl -vhdl'
can invalidate previously created VHDL design units.
The following command can change the definitions of
VHDL libraries:
'set_attribute hdl_vhdl_environment <common |
synergy> /'.
VHDL-616 Ignoring 'after' clause in signal
assignment. This may result in a
mismatch between simulation and
synthesis.
Check the 'HDL Modeling in Encounter RTL Compiler'
for a list of supported constructs.
VHDL-618 'Timeout' clauses in 'wait'
statements are ignored for
synthesis. This may cause
mismatches between simulation
and synthesis.
See 'HDL Modeling in Encounter RTL Compiler' for a
list of supported VHDL constructs.
VHDL-619 Potentially illegal attribute
reference.
The attribute name cannot be resolved to a static value.
For example, consider the enumeration type:
type COLOR is (RED, BLUE, GREEN);
The following attribute references are illegal:
COLOR'succ(RED)
COLOR'pred(COLOR'left).
VHDL-621 Ignoring resolution function. This
may cause mismatches between
simulation and synthesis.
The 'resolved' function defined in package IEEE
STD_LOGIC_1164 is the only supported resolution
function. See 'Resolution Function Directives' in 'HDL
Modeling in Encounter RTL Compiler' for information on
how to use the RESOLUTION function directives.
VHDL-625 Signal occurring in attribute prefix
not listed in sensitivity list.
VHDL-637 File declarations are not supported
for synthesis.
VHDL-639 Initial values are ignored for
synthesis.
The specified construct has no effect on synthesis. In
some cases (such as 'after' clauses in signal
assignments) may cause a mismatch between and
simulation.
VHDL-640 Delay mechanisms in signal
assignments are ignored for
synthesis.
The specified construct has no effect on synthesis. In
some cases (such as 'after' clauses in signal
assignments) may cause a mismatch between and
simulation.
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May 2013 150 Product Version 12.2
VHDL-641 Statements in an entity are
ignored for synthesis.
The specified construct has no effect on synthesis. In
some cases (such as 'after' clauses in signal
assignments) may cause a mismatch between and
simulation.
VHDL-643 Report statements are ignored for
synthesis.
The specified construct has no effect on synthesis.
Some constructs (such as 'after' clauses in signal
assignments) may cause a mismatch between
simulation and synthesis.
VHDL-644 Assertion statements are ignored
for synthesis.
The specified construct has no effect on synthesis.
Some constructs (such as 'after' clauses in signal
assignments) may cause a mismatch between
simulation and synthesis.
VHDL-645 Concurrent assertion statements
are ignored for synthesis.
The specified construct has no effect on synthesis. In
some cases (such as 'after' clauses in signal
assignments) may cause a mismatch between and
simulation.
VHDL-664 Unable to find package body for
subset validation.
When a VHDL file is read using the 'read_hdl -vhdl'
command, it is simultaneously checked for the
synthesizable RTL subset. For references to
subprograms declared in packages, the corresponding
subprogram body in the package body is also validated.
If the package body has not been analyzed, any
references to subprograms in the body will not be
subset checked. For this reason, it is recommended that
all packages and their bodies be analyzed before any
entities/architectures are analyzed.
VHDL-667 Declaration is ignored for
synthesis.
Signals, constants and variables must have a subtype
that is supported for synthesis.
VHDL-668 A 'wait' statement that is not the
first statement of the process may
result in simulation mismatches.
Processes that have a 'wait' statement must have it as
the first statement, otherwise simulation mismatches
may result between RTL and netlist. Processes with
multiple 'wait' statements are not supported.
VHDL-671 Potential simulation mismatch in
call to STD_MATCH.
The attribute ENUM_ENCODING is used to map
non-synthesizable values of std_ulogic to synthesizable
values. Because the STD_MATCH function depends
on the exact values passed in, this mapping may cause
a simulation mismatch.
VHDL-672 Overriding earlier builtin pragma
on function.
VHDLPT-512 Library name WORK is defined as
a permanent name.
VHDLPT-518 Generic warning.
VHDLPT-522 VHDL Parser internal warning.
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Warning Messages
May 2013 151 Product Version 12.2
VHDLPT-523 VHDL Parser unimplemented
feature.
VHDLPT-532 Aggregate length mismatch.
VHDLPT-544 Non-matching array elements.
VHDLPT-548 Overflow in computation of
attribute.
VHDLPT-588 Character does not belong to
string element subtype.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-604 Direction mismatch.
VHDLPT-631 Expression value is out of range. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-646 Process with no sensitivity list, wait
statements, or procedure calls will
run forever.
VHDLPT-649 A negative exponent is allowed
only for a left operand of a floating
point type.
VHDLPT-651 Invalid array selector expression. To increase the severity of this message set its severity
attribute to error.
VHDLPT-661 Operands have different lengths.
VHDLPT-663 Math error.
VHDLPT-668 Missing choices in case statement
or selected signal assignment.
To increase the severity of this message to Error, do:
set_attr severity error /messages/VHDLPT/
VHDLPT-668
A VHDL case statement must include a case alternative
(using then 'WHEN' keyword) for every possible value of
the case selector expression. Alternatives may be
specified individually, with ranges, or with the OTHERS
keyword. For example:
variable x : integer range 0 to 15;
begin
case x is
when 1 =>-- individual
when 2 to 10 =>-- range
when others =>-- includes 0 and 11 to 15
end case.
VHDLPT-680 Time value must be non-negative.
VHDLPT-704 Function has no return statement. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-715 Illegal null range. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-738 Range does not lie within subtype. Invalid or unsupported VHDL syntax is encountered.
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Warning Messages
May 2013 152 Product Version 12.2
VHDLPT-754 The string literal length does not
match index range length.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-756 Subtype mismatch. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-758 Too many elements in array
aggregate.
To increase the severity of this message set its severity
attribute to error.
VHDLPT-774 Times in successive waveform
elements must be increasing.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-787 Comment does not match any
meta-comment.
VHDLPT-788 Input file contains no design units. A VHDL file must contain at least one design unit.
VHDLPT-797 Signal has multiple sources. There are two cases in which a VHDL signal is
prohibited from having multiple sources. First, any
unresolved signal is not allowed to have multiple
sources. Second, any signal declared BUFFER is not
allowed to have multiple sources. (A resolved BUFFER
signal is still not allowed to have multiple sources.)
A signal can be declared as resolved in one of two
ways. A signal can be declared with a resolved
subtype. For instance, subtype std_logic is a resolved
subtype (while std_unlogic is unresolved). Or, a signal
can include a resolution function in its declaration.
For instance:
signal s1 : std_ulogic; -- unresolved
signal s2 : std_logic; -- resolved
signal s3 : buffer std_logic; -- resolved, but
BUFFER
signal s4 : resolved std_ulogic; -- resolved
A source for a signal is one of the following:
1. an association with an INOUT, OUT, BUFFER, or
LINKAGE port in a component instantiation or block
statement
2. a concurrent signal assignment statement
3. an association with an INOUT or OUT parameter of a
procedure
4. a process statement which contains an assignment
to a signal
Note that multiple assignments or procedure
associations within one process statement count as
only one source (the process statement as a whole
counts as one source for a given signal).
VHDLPT-799 Ignoring duplicate pragma. When multiple identical pragmas are applied to a
construct, all but the first are ignored.
VHDLPT-800 Replacing existing design unit. A previously analyzed unit is being replaced.
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May 2013 153 Product Version 12.2
VHDLPT-801 Marking out-of-date unit as invalid. A unit is considered out-of-date when a unit that it
depends on is re-analyzed.
VHDLPT-802 Instantiating non-visible entity. The entity being instantiated is not visible. Normally
this is illegal, but is allowed when strict lrm compliance
is disabled. Because the referenced entity is not visible
to the parser, no checks can be done on generic and
port types, and subelement association is therefore not
supported.
VHDLPT-805 Missing case choices for type
CHARACTER in VHDL-1987
mode.
In VHDL-1987, type CHARACTER has 128 values.
However, the parser treats type CHARACTER as
having 256 values, as in VHDL-1993.
VHDLPT-807 Ignoring illegal empty generic
clause.
VLOGPT-2 Ignoring unimplemented construct.
VLOGPT-6 Replacing previously read Verilog
description.
A Verilog description is replaced when a new
description of the same name and same library is read
again.
Verilog descriptions are:
module
macromodule
SystemVerilog adds the following descriptions:
interface
program
package.
VLOGPT-10 Ignoring real number.
VLOGPT-12 Ignoring non-printable character. A non-printing character which is not a whitespace or
format control character is ignored.
VLOGPT-13 Ignoring Null Statement.
VLOGPT-14 Unrecognized escape sequence in
string.
VLOGPT-16 Truncation in sized number. The number of bits specified is larger than the number
of declared bits, e.g. 3'b1001. In this case, the resulting
number will be pruned to 3'b001 which may not be the
intent of the user.
VLOGPT-18 Ignoring zero width in sized
number.
VLOGPT-19 Use of 'signed' or 'unsigned'
keyword in Verilog-1995 mode.
The keywords 'signed' and 'unsigned' are supported in
Verilog-1995 mode. Verification tools may need to be
run in Verilog-2001 mode to support this design.
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Warning Messages
May 2013 154 Product Version 12.2
VLOGPT-21 Suspicious implicit wire
declaration.
An implicit wire is declared for an undeclared symbol
occurring within a module instance or within the target
of an assign statement. If an undeclared symbol occurs
within a subexpression in one of these contexts, it may
be a coding error.
VLOGPT-24 Reference to undeclared symbol in
pragma.
A variable must be declared before it can be referenced.
VLOGPT-27 Conflict between reg/wire and
instance.
Normally a name conflict between a variable (reg or
wire) and a module or gate instance label is an error. To
enable the default error behavior, do: set_attribute
hdl_allow_instance_name_conflict false /.
VLOGPT-31 Unsupported system task or
function: assuming value 1'b1.
The $signed and $unsigned system functions are
always supported, and synthesizable SystemVerilog
system functions are supported when SystemVerilog
parsing is enabled. No other system functions are
supported.
VLOGPT-33 Ignoring unsynthesizable
declaration.
VLOGPT-35 Ignoring delay specifier. A delay specifier, either in an assignment or as a
separate statement, is not synthesizable. This warning
is issued only once per module.
VLOGPT-38 Port direction defaults to inout. In SystemVerilog, a port declared without any direction
defaults to inout.
VLOGPT-37 Ignoring unsynthesizable
construct.
The following constructs will be ignored:
- initial block
- final block
- program block
- property block
- sequence block
- covergroup
- gate drive strength
- system task enable
- reg declaration with initial value
- specify block.
VLOGPT-40 Unsupported expression:
assuming value 1'b0.
Expressions such as the constructor new() are not
supported for synthesis.
VLOGPT-43 Implicit net declaration not allowed
with `default_nettype none.
When `default_nettype is none, each input and inout
port declaration requires a corresponding net type.
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Warning Messages
May 2013 155 Product Version 12.2
VLOGPT-51 Ignoring range on integer type. A (packed) range on an integer type is ignored. For
instance:
integer [63:0] x;
The apparent intent is to get a 64-bit integer, but this is
not legal Verilog. To get a 64-element array of integers,
do this:
integer x [63:0];
VLOGPT-76 The trireg net is being treated as
wire.
VLOGPT-103 Black-boxes found in module.
VLOGPT-105 Out-of-range bit-select or
part-select.
An out-of-range bit-select or part-select was detected.
Reading results in an x value, writing has no effect.
VLOGPT-106 Found black-box instance.
VLOGPT-107 Using synthesizable equivalent of
non-synthesizable operator.
Verilog operators === and !== are not synthesizable.
VLOGPT-111 Ignoring explicit sensitivity list. Sensitivity lists for always_comb and always_latch
processes are inferred by the tool. Any explicitly
specified sensitivity list for these processes is ignored.
VLOGPT-112 Level-sensitive always_ff process
will be treated as non-sequential
behavior.
The signals listed in the sensitivity list for an always_ff
process must be edge-sensitive in order to model
sequential behavior. In the absence of edge-sensitive
signals, the behavior within the always_ff process will
be synthesized as either combinational or latched logic.
VLOGPT-115 Assignment operation in
conditional context.
An assignment operator in a conditional context may be
a typo. To disable this message, enclose the assignm
ent in an extra level of parentheses. For instance, this
assignment operator in an if condition:
if (x = y) ...
may be a typo for the intended:
if (x == y) ...
To make it clear that an assignment operator is wanted,
add an extra set of parentheses:
if ((x = y)) ...
VLOGPT-122 Ignoring 'static' lifetime qualifier. All subprogram-local variables are treated as automatic.
Therefore an explicit 'static' lifetime qualifier has no
effect.
VLOGPT-209 Keyword 'generate' is not allowed
within a generate statement.
VLOGPT-210 Standalone generate blocks are
not supported in the IEEE
standard.
Keyword 'begin' is not allowed at the beginning of
generate region.
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Warning Messages
May 2013 156 Product Version 12.2
VLOGPT-416 Inconsistent reference of edge
signal.
If the set signal 'set_sig' is a posedge signal, the if
statement should use ( set_sig ) as the testing
condition.
e.g.
always @(posedge clk or posedge set_sig)
if ( set_sig)
If the set signal 'set_sig' is a negedge signal, the if
statement should use (! set_sig ) as the testing
condition.
e.g.
always @(posedge clk or negedge set_sig)
if ( ! set_sig).
VLOGPT-417 Ignoring redundant edge check.
VLOGPT-425 Implementing 'iff' condition in
level-sensitive always block as a
latch.
This may cause simulation mismatches between the
original and synthesized designs.
VLOGPT-434 Ignoring else clause after check for
clock.
An else clause after an if statement that checks for the
clock edge is never executed, and therefore is ignored
for synthesis.
VLOGPT-502 Unrecognized pragma. Refer to the documentation for supported pragmas.
VLOGPT-503 Unsupported pragma. This pragma is recognized but not supported.
VLOGPT-504 Pragma ignored since placed at
the wrong spot.
Refer to the documentation on where to place pragmas.
VLOGPT-506 Unused attribute.
VLOGPT-507 Syntax error in pragma. Pragma will be ignored.
VLOGPT-52 Ignoring range and sign attributes.
VLOGPT-612 Bad value for global variable
hdl_verilog_vlogpt_arg.
VLOGPT-643 Syntax error in `line directive. The syntax of the `line directive is: `line <number> <file>
<level>.
VLOGPT-646 Unterminated translate pragma. A `translate_off' or `synthesis_off' pragma must be
matched by a corresponding `translate_on' or
`synthesis_on' pragma. See `Synthesizing Verilog
Designs' in 'HDL Modeling in Encounter RTL Compiler'
for more information.
VLOGPT-647 Redefinition of macro. The latest definition of the macro will be used.
VLOGPT-652 Mixed elaboration Flow - Structural
module read in replaces previously
read module in default library with
the same name.
A Verilog description is replaced when a new
description of the same name is read again (in the
same library). Remove the duplicate module definitions
from the files being read in.
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Warning Messages
May 2013 157 Product Version 12.2
VLOGPT-656 Unterminated `begin_keywords
directive.
Each `begin_keywords directive may be matched by a
corresponding `end_keywords directive. These
directives may be nested.
VLOGPT-658 Renamed port. A module port is renamed when it conflicts with another
port name. This can happen when a port name is
duplicated in the port list, or when a port of a complex
data type is split into sub-ports, and the name of
sub-port conflicts with an existing port.
VLOGPT-659 Duplicate Verilog-2001 attribute
ignored.
The latest Verilog-2001 attribute with the same name
for this object would survive, others would be ignored.
VLOGPT-660 Primitive output port has multiple
bits.
All but the least significant bit are ignored.
VLOGPT-661 Duplicate module definition. To modify the behaviour, do : set_attribute
hdl_keep_first_module_definition false.
VLOGPT-662 Declarations tri0, tri1, trireg. The following declarations will be treated as wire
declarations for synthesis:
-tri0
-tri1
-trireg
VLOGPT-663 Reference to predefined compiler
directive.
VRO-14 Detected a logic abstract in the
design.
A logic abstract is an unresolved reference with defined
port names and directions. By default, such modules
are written in the netlist. Use 'set_attr
write_vlog_empty_module_for_logic_abstract false /' to
prevent writing empty modules in the netlist for a logic
abstract.
VRO-17 Detected a conflict, Found a
module having same name as of a
libcell in the design.
It is recommended to change the name of the
conflicting module as it might lead to incorrect mapping
of instances later in the flow.
VTIM-102 Input sdc file not specified. Specify the input sdc if automatic generation is not
desired.
VTIM-103 Input netlist not specified. Specify the input netlist if automatic generation is not
desired.
WDO-105 Output of the LEC run will not be
kept in a logfile.
WDO-106 Conflicting specification of hier vs
flat compare.
WDO-107 Retiming LEC comparison cannot
be hierarchical.
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Warning Messages
May 2013 158 Product Version 12.2
WDO-108 Cannot identify a checkpoint netlist
to generate the last_checkpoint
sub-dofile; Will instead use RTL as
golden to generate a one-shot
dofile.
Golden design of the last sub-dofile has to be a
checkpoint netlist file with a .v suffix in the checkpoint
directory. To use the RTL code as the golden design,
either set the checkpoint_flow root attr to false, or do
'-golden_design RTL' instead. To use an alternative
golden netlist, do '-golden_design' with its filename.
WDO-109 Cannot find an expected LEC
sub-dofile.
Following the documented naming convention, a
sub-dofile of this name is expected but not available (at
the checkpoint directory). Possibly something is wrong.
WDO-110 Cannot find an expected LEC
logfile.
Following the documented naming convention, a LEC
logfile of this name is expected but not available (at the
checkpoint directory). Possibly something is wrong.
WDO-111 Cannot find simulation model of a
ChipWare component.
If a ChipWare component is instantiated in the RTL
code, the generated dofile needs to read in its
simulation model to verify the design. But this
component is not registered with any simulation model
in the ChipWare Developer registration. With loading its
simulation model, this component will become a black
box in LEC operation.
WDO-121 There is a library filename with .lbr
suffix.
A .lbr library file is often an RC binary library file, which
Conformal LEC does not recognize. If this is indeed an
RC binary library file, the LEC 'read library' command
will error out. In such case, update the generated dofile
with an equivalent .lib file or the corresponding
simulation library file(s).
WDO-122 File exists.
WDO-201 There is a library filename with .lbr
suffix.
A .lbr library file is often an RC binary library file, which
Conformal LEC does not recognize. If this is indeed an
RC binary library file, the LEC 'read library' command
will error out. In such case, update the generated dofile
with an equivalent .lib file or the corresponding
simulation library file(s).
WDO-202 The undriven setting in RC is not
uniform.
There are three undriven-related attrs in RC. There is
only one undriven setting in LEC. To make sure RC and
LEC interpret the RTL code consistently, setting of
these three RC attrs must be uniform.
WDO-205 The parameter naming style is not
LEC-friendly.
To correctly translate the parameter naming style, value
of the hdl_parameter_naming_style attr must end with
'%d'. There should not be anything after the '%d'
descriptor. Should there be black boxes in the design,
the incorrect translation may induce false negative in
LEC comparison.
WDO-207 Fail to open a file for writing.
WDO-208 Verilog include file assumed to be
in v1995.
If a loaded HDL file is not found in the hdl_filelist attr, it
must be a Verilog include file, and is assumed to be in
Verilog-1995.
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Warning Messages
May 2013 159 Product Version 12.2
WDO-209 Multiple LEC pin constraints.
WDO-210 Unknown design view. This attr expects a design view specification of 'both',
'golden', or 'revised'.
WDO-213 The dofile is incomplete.
WDO-214 Attribute
boundary_optimize_invert_hier_pi
ns_renaming_extension is empty
string. No renaming rule
generated for LEC.
WDO-401 Cannot find an expected timing
report.
A timing report is expected but not available. Possibly
something is wrong.
WDO-403 Initialization sequence file not
specified.
Specify an initialization sequence file to include MCP
validation.
WDO-404 There is a library filename with .lbr
suffix.
A .lbr library file is often an RC binary library file, which
CCD does not recognize. If this is indeed an RC binary
library file, the CCD 'read library' command will error
out. In such case, update the generated dofile with an
equivalent .lib file or the corresponding simulation
library file(s).
WDO-405 Output sdc filename is not
specified.
Use '-out_sdc' option to control the output sdc filename
generated by CCD.
WDO-407 Rule instance file not specified. Specify a rule instance file with '-rule_instance_file' if
default behavior is not desired.
WDO-650 Checkpoint/Restart facility is not
supported in GUI mode. Review
the set of limitations before using
the CHECKPOINT command.
WMT-100 Could not determine test mode
signal.
No test mode signal present, make sure a test mode
signal has been specified.
WMT-101 Could not determine JTAG pin. A chip level flow was detected (a JTAG_MACRO was
found), but a jtag pin could not be found.
WMT-102 Could not determine JTAG pin. A block level flow was detected (no JTAG_MACRO was
found), and a required pin could not be found.
WMT-103 The dft_hdl_filelist attribute is
empty, using hdl_filelist instead.
For an RTL flow (indicated by the attribute
dft_rtl_insertion being true), the netlist normally used
for simulation is gotten from the dft_hdl_filelist attribute.
In this case, the attribute is empty, so hdl_filelist will be
used instead.
WMT-104 Multiple instructions have been
defined for MBIST, and both MDA
(direct access) and JTAG patterns
have been requested. Only MDA
patterns will be created.
Both pattern types cant be created by
create_embedded_test at the same time. Only MDA
patterns will be created.
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Warning Messages
May 2013 160 Product Version 12.2
WSDF-104 Default value for an option has
changed in this release.
Specify the option explicitly.
WSDF-201 No delay description exists for cell. Cell could be a loop breaker or its inputs could be driven
by constants.
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May 2013 161 Product Version 12.2
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3
Error Messages
Message Reference for Encounter RTL Compiler
Error Messages
May 2013 162 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
List of Error Messages
Message-ID Title Help
1801-1 There was an error while applying
power intent of 1801 file.
Update the 1801 file appropriately and restart the
session with fixed 1801 file.
1801-100 Detected error in 1801 power
intent file.
Fix the error and read the 1801 power intent file again.
For more information on the syntax of commands, refer
to the 1801 command reference.
CDFG-1 Unexpected NULL handle. Error during elaboration.
CDFG-2 Unexpected NULL string. Error during elaboration.
CDFG-3 Unexpected NULL pointer. Error during elaboration.
CDFG-4 Failed assertion. Error during elaboration.
CDFG-10 Fatal error. Error during elaboration.
CDFG-100 Reals are not supported. Error during elaboration.
CDFG-101 '(Min:typ:max)' expressions are not
supported.
Error during elaboration.
CDFG-102 References or assignments to
floating point variables are not
supported.
Error during elaboration.
CDFG-103 Unimplemented feature. Error during elaboration.
CDFG-104 Arrays with more than 2
dimensions are not supported.
Error during elaboration.
CDFG-105 Unsupported use of VHDL 'event'
construct.
See the 'Modeling Flip-Flops' section in 'HDL Modeling
in Encounter RTL Compiler' for examples of supported
uses of the VHDL 'event' construct.
CDFG-106 Unsupported use of Verilog
'posedge' or 'negedge' construct.
See the 'Modeling Flip-Flops' section in HDL Modeling
in Encounter RTL Compiler for examples of supported
modeling styles.
CDFG-108 Wait statement (VHDL) not
supported for this release.
Error during elaboration.
CDFG-110 Unsupported resolution function. Error during elaboration.
CDFG-111 Unsupported assignment to loop
index.
The variable was used to index a 'for' loop and then
assigned within the loop itself, which is not allowed.
Remove the assignment from the loop or use a different
variable to index the loop.
CDFG-112 Prefix for multi-concatenations
must be constant valued.
The prefix expression of a multi-concatenation must
evaluate to a positive constant at compile time.
Message Reference for Encounter RTL Compiler
Error Messages
May 2013 163 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
CDFG-113 Unsupported assignment to a
variable on a FALSE branch of an
if edge statement.
Error during elaboration.
CDFG-114 Unsupported use of multiple clock
edges in one process or block.
Error during elaboration.
CDFG-122 Attribute must be constant valued. The attribute expression must evaluate to a constant at
compile time.
CDFG-123 Multi-dimensional array is not
supported for port declarations.
Error during elaboration.
CDFG-124 Global reference to
multi-dimensional array is not
supported in subprogram.
Error during elaboration.
CDFG-126 Unsupported construct. See the 'Synthesizing VHDL Designs' chapter in 'HDL
Modeling in Encounter RTL Compiler' for a list of
supported VHDL constructs.
CDFG-128 Unsupported division: numerator
or denominator is less than 2 bits
wide.
Error during elaboration.
CDFG-129 Unsupported exponentiation. Only the following styles of exponentiation are
supported:
const ** const
var ** const
(2^N) ** var.
CDFG-130 Illegal Assignment Pattern. Error during elaboration.
CDFG-131 Illegal assignment to constant. A constant value cannot be the target of an assignment
or be connected to an output or an inout port.
CDFG-138 Redeclaration of port with
inconsistent bounds.
Error during elaboration.
CDFG-144 Illegal return_port_name pragma
on task.
Error during elaboration.
CDFG-159 Illegal target type. Specify a valid target for the assignment and reload the
design.
CDFG-160 Unknown expression type. Error during elaboration.
CDFG-161 Illegal port association. Output and inout ports of instantiated modules and
functions can be connected to variables, bit-selects,
part-selects, or concatenations.
CDFG-162 Unknown concurrent statement. Error during elaboration.
CDFG-163 Unknown declaration. Error during elaboration.
CDFG-164 Unknown binary operator. Error during elaboration.
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Error Messages
May 2013 164 Product Version 12.2
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CDFG-165 Unknown unary operator '%s'. Error during elaboration.
CDFG-167 Unknown resolution function. Error during elaboration.
CDFG-168 Unknown statement. Error during elaboration.
CDFG-170 Unknown case item type. Error during elaboration.
CDFG-171 Unknown case type. Error during elaboration.
CDFG-172 Unknown primitive type. Error during elaboration.
CDFG-173 Unknown builtin operator. Error during elaboration.
CDFG-178 Real value cannot be rounded to
nearest integral value.
Error during elaboration.
CDFG-179 Illegal use of real type in packed
declaration.
A real data type may not be used in the declaration of a
packed struct or union.
CDFG-180 Illegal use of unpacked type in
packed declaration.
An unpacked data type may not be used in the
declaration of a packed struct, union, or array.
CDFG-181 Element width mismatch in packed
union.
All the elements of a packed union must have the same
width.
CDFG-182 Incompatible array element type. An expression in an array must be castable to the type
of the array element.
CDFG-183 Incompatible struct element type. An expression in a struct must be castable to the type
of the corresponding struct element.
CDFG-184 Illegal index or slice of unpacked
struct.
An unpacked struct type may not be indexed or sliced.
Perhaps the struct type should be declared packed.
CDFG-200 Could not resolve complex
expression.
Error during elaboration.
CDFG-201 Could not find hierarchical name. Error during elaboration.
CDFG-203 Could not find function. Error during elaboration.
CDFG-204 Could not find subprogram. Error during elaboration.
CDFG-205 Could not find return value for
function.
Error during elaboration.
CDFG-206 Could not find instance reference. Error during elaboration.
CDFG-207 Could not find clock signal. Error during elaboration.
CDFG-209 Could not find a pin. Ensure that the desired pin is specified correctly in the
HDL.
CDFG-210 Could not find an HDL design. Ensure that the design exists or the correct file was
loaded.
CDFG-211 Could not find a port. Ensure that the desired port is specified correctly in the
HDL.
CDFG-212 Could not find state vector. Error during elaboration.
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Error Messages
May 2013 165 Product Version 12.2
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CDFG-213 Could not find function return port. Error during elaboration.
CDFG-214 Unknown parameter. Ensure that the desired parameter is specified correctly
in the HDL.
CDFG-215 Cannot build an HDL design with
unconstrained ports.
Constrain all ports in the design and synthesize the
design again.
CDFG-216 Cannot build an HDL design with
generics that lack a default value.
Specify a default value for the generic in the HDL.
CDFG-218 Exceeded the maximum memory
address range limit.
The maximum addressable range specifies the
maximum number of memory elements that can be
indexed using an address. This limit can be set by
'set_attribute hdl_max_memory_address_range <limit>
/'.
CDFG-219 Width of slice must be a positive
constant.
The width of a slice must evaluate to a positive constant
at compile time.
CDFG-220 Index out of range. Correct the index or the range in the HDL.
CDFG-221 Slice out of range. Correct the slice or the range in the HDL.
CDFG-222 Invalid context for streaming
concatenation.
A streaming concatenation may only appear in an
assignment statement or in a cast expression.
CDFG-224 Invalid assignment. Error during elaboration.
CDFG-226 Illegal 'divide by zero' operation. Correct the operation in the HDL.
CDFG-227 Illegal 'modulus by zero' operation. Correct the operation in the HDL.
CDFG-228 Constant propagation failed. Error during elaboration.
CDFG-229 'x' is not allowed in casez items. Correct the casez construct in the HDL.
CDFG-230 Illegal enum identifier. Error during elaboration.
CDFG-231 Could not synthesize non-constant
range values.
The left and right range must be constant valued
expressions.
CDFG-232 Invalid expression. An expression or an operand within an expression
could not be evaluated.
CDFG-233 Number of rows in inferred
memory must be greater than 1.
Error during elaboration.
CDFG-234 Could not elaborate array
reference.
Specify all the values of the array assignment pattern.
See 'HDL Modeling in Encounter RTL Compiler' for
examples of legal array references.
CDFG-235 Could not synthesize declaration
with empty range.
Error during elaboration.
CDFG-238 Illegal mix of blocking and
non-blocking assignments.
Error during elaboration.
CDFG-240 Incompatible array dimensions. Error during elaboration.
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Error Messages
May 2013 166 Product Version 12.2
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CDFG-241 Latch inferred. To allow latches, set the 'hdl_error_on_latch' attribute to
'false'.
CDFG-242 Size for builtin type conversion
must be a positive constant.
The size expression of a type conversion must evaluate
to a positive constant at compile time.
CDFG-244 Specified value is out of range. Correct the value or the range in the HDL.
CDFG-245 Alias size mismatch. Error during elaboration.
CDFG-246 Missing 'return_port_name'
pragma for function mapped to
synthetic operator or module.
A function annotated with the 'map_to_operator' or the
'map_to_module' pragma requires a
'return_port_name' pragma to specify the name of the
module port giving the function return value.
CDFG-247 Function annotated with
'map_to_module' must have
constant width.
Error during elaboration.
CDFG-249 Constant expression required. See the 'HDL Modeling in Encounter RTL Compiler' for
more information.
CDFG-251 Could not assign to localparam
with parameter association.
Error during elaboration.
CDFG-252 Could not determine bounds. Error during elaboration.
CDFG-253 Could not instantiate module. Error during elaboration.
CDFG-254 Could not determine port type for
blackbox.
Error during elaboration.
CDFG-255 Could not find global signal. Error during elaboration.
CDFG-256 Illegal number of output ports for
gate.
Error during elaboration.
CDFG-257 Illegal number of input ports for
gate.
Error during elaboration.
CDFG-258 Incomplete structure. Error during elaboration.
CDFG-259 Port has more than one driver. Error during elaboration.
CDFG-260 Undetermined constant data type. Error during elaboration.
CDFG-261 Could not make connection. Error during elaboration.
CDFG-262 Could not find conditional
construct.
Error during elaboration.
CDFG-263 Undefined instance type. Error during elaboration.
CDFG-264 Undefined signal type. Error during elaboration.
CDFG-266 Width mismatch for streaming
operator.
A streaming operator as the source of an assignment
must not be wider than the target of the assignment. A
streaming operator as the target of an assignment must
not be wider than source of the assignment.
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Error Messages
May 2013 167 Product Version 12.2
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CDFG-267 Missing association in aggregate
or assignment pattern.
Error during elaboration.
CDFG-268 Duplicate association in aggregate
or assignment pattern.
Error during elaboration.
CDFG-269 Assignment pattern appears in
inappropriate context.
An assignment pattern may only appear in a place
where its type is constrained to be an array or struct
type.
CDFG-270 Dimension argument exceeds
array dimension.
Ensure that the array is accessed correctly in the HDL.
CDFG-271 Non-negative argument required. Error during elaboration.
CDFG-272 Illegal use of unpacked array as
operand.
Error during elaboration.
CDFG-273 Array size mismatch in type
conversion.
Error during elaboration.
CDFG-274 Type mismatch. SystemVerilog requires certain types to match. For
instance, if the target of an assignment is of an
unpacked type then the source must be of the same
type.
CDFG-275 Too many elements in struct
assignment pattern.
The assignment pattern ('{...}) has too many elements
for the struct type. There must be one element in the
assignment pattern for each field defined in the struct.
CDFG-276 Invalid use of value member key
for struct assignment pattern.
A value member key may only be used to specify a
member when the assignment pattern is of an array
type.
CDFG-280 An assignment pattern is required
in this context.
A concatenation is being used in a context where an
assignment pattern is required. A concatenation can
only be assigned to a bit or integer type. An
assignment pattern ('{...}) must be used instead when
the target is a non-packed array or struct type.
CDFG-283 Incompatible bitwidths in
assignment.
Use 'set_attribute hdl_vhdl_assign_width_mismatch
true /' to allow such assignments with mismatching
widths of lhs and rhs.
CDFG-294 Unsupported architecture. Error during elaboration.
CDFG-298 Could not find field. The HDL references a field which does not belong to
the struct type.
CDFG-299 Missing element(s) in struct
assignment pattern.
The assignment pattern ('{...}) must specify a value for
each field defined in the specified struct type.
CDFG-307 No top level design has been
specified.
For mixed RTL and structural input based flow, the top
level design name should be provided with the
'elaborate' command.
CDFG-320 No design entity specified. Error during elaboration.
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Error Messages
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CDFG-321 No design architecture specified. Specify the name of the preferred architecture to use
for the entity with the 'hdl_vhdl_preferred_architecture'
command.
CDFG-323 No subprogram body specified. Error during elaboration.
CDFG-324 Could not find specified
architecture.
Error during elaboration.
CDFG-326 Problem in processing the internal
representation of the design.
Error during elaboration. The internal representation of
the design is in an inconsistent state.
CDFG-351 Too many parameters for design. Error during elaboration.
CDFG-352 Could not resolve parameter. Error during elaboration.
CDFG-355 Missing default value for
parameter.
Error during elaboration.
CDFG-356 Constant array not supported. Error during elaboration.
CDFG-369 Multibit edge is not allowed. A posedge or negedge signal in an event list must be
one bit wide.
CDFG-400 No actual for interface port. Error during elaboration.
CDFG-403 Could not connect named port. Error during elaboration.
CDFG-404 Could not connect positional port. Error during elaboration.
CDFG-405 Could not connect gate port. Error during elaboration.
CDFG-406 Could not connect subprogram
port.
Error during elaboration.
CDFG-407 Too many arguments to
subprogram.
Error during elaboration.
CDFG-408 Too few arguments to subprogram. Error during elaboration.
CDFG-411 Recursive module instantiation is
not supported.
Error during elaboration.
CDFG-412 Reached maximum recursion limit
for instantiation.
The maximum recursion limit specifies the maximum
allowed number of recursively instantiated
subprograms to prevent infinite recursion. This limit can
be set by 'set_attribute hdl_max_recursion_limit <limit>
/'.
CDFG-413 Cannot associate a constant to an
output or inout port.
Use 'set_attribute hdl_allow_inout_const_port_connect
true /' to allow connection of a constant to an inout port.
CDFG-414 Too many arguments to instance. Error during elaboration.
CDFG-415 Generic instantiation cannot be
linked to a non-generic module
definition.
Either supply a parameterized module definition or a
non-parameterized instantiation.
CDFG-429 Width of argument is not a multiple
of instance array width.
Error during elaboration.
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CDFG-430 Arrays are not supported in port
lists.
Error during elaboration.
CDFG-431 Could not resolve reference. Use 'set_attribute hdl_error_on_blackbox false /' to
cause a warning, rather than an error, when a blackbox
is found.
CDFG-432 Illegal port expression in port list. Error during elaboration.
CDFG-433 Illegal port identifier in port list. Error during elaboration.
CDFG-434 Indexed identifier must have
constant index.
Error during elaboration.
CDFG-435 Unresolved generic interface. Error during elaboration.
CDFG-437 Could not create port. Error during elaboration.
CDFG-438 Interface conflict. Error during elaboration.
CDFG-439 Modport conflict. Error during elaboration.
CDFG-442 Duplicate association to port. Error during elaboration.
CDFG-443 Cannot instantiate a blackbox
interface.
Error during elaboration.
CDFG-444 Could not find matching modport. Error during elaboration.
CDFG-445 Could not find a declaration in the
interface.
Error during elaboration.
CDFG-446 Could not find matching interface. Error during elaboration.
CDFG-447 Could not find matching port in the
corresponding module definition.
Error during elaboration.
CDFG-450 Invalid for statement. Error during elaboration.
CDFG-451 Unresolved 'for loop' parameters. The 'for loop' parameters of a 'for' statement must
evaluate to a constant at compile time. See 'HDL
Modeling in Encounter RTL Compiler' for more
information.
CDFG-452 Unable to unfold for statement. Error during elaboration.
CDFG-453 Unsupported 'for' statement
initialization assignment.
The initialization expression in a 'for' statement must
evaluate to a constant when synthesizing the design.
CDFG-454 Unsupported condition expression. The condition expression of a 'for' or 'while' loop
statement must evaluate to a constant when
synthesizing the design. See 'HDL Modeling in
Encounter RTL Compiler' for more information.
CDFG-455 Unsupported step assignment in
'for' statement.
The step assignment of a 'for' statement must evaluate
to a constant at compile time.
CDFG-457 Reached maximum loop limit while
unrolling loop.
The maximum loop limit specifies the maximum number
of iterations allowed for unrolling loops. This limit can
be set by 'set_attribute hdl_max_loop_limit <limit> /'.
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Error Messages
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CDFG-460 Instance resolves to a logic
abstract.
Use 'set_attribute hdl_error_on_logic_abstract false /'
to cause a warning, rather than an error, when a logic
abstract is found.
CDFG-461 Invalid conditional statement in if/
case clause.
Error during elaboration.
CDFG-462 Could not create case item. Error during elaboration.
CDFG-463 All assignments within a
conditional statement should be
either all blocking or all
non-blocking
The following example shows an unallowed mix of
blocking and non-blocking assignments.
if (in)
out = data1;
else
out <= data2;
CDFG-486 This could be due to a previous
elaboration error.
Try reading the structural netlist again.
CDFG-510 Array has multiple drivers. Error during elaboration.
CDFG-550 Dimensions of formal and
argument do not match.
Error during elaboration.
CDFG-551 Missing actual for deferred or
unconstrained port.
Error during elaboration.
CDFG-553 No actual corresponding to implicit
port.
In a module instance, every port specified using implicit
('.name') notation must have a matching signal in the
instantiating module.
CDFG-554 Actual in array of instances does
not match width of formal.
Either the width of the actual must match the width of
the corresponding formal, or the width of the actual
divided by the number of instances must match the
width of the corresponding formal.
CDFG-557 Missing actual for interface port. Error during elaboration.
CDFG-561 Port direction differs between
component and implementation.
Error during elaboration.
CDFG-601 Parameter specification error. A parameter given to the 'elaborate' command may
have one of the following forms:
- integer: 3, -10
- Verilog bit string: 1'b1, 8'hff, 9'so777
- string literal: "hello, world"
CDFG-810 Port mismatch for instance. An instantiation has a connected port that is not
specified in the module definition. This can happen if
ports are removed from the original module definition or
if too many ports are specified in the instantiation.
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CDFG-813 Could not find definition for name
specified in map_to_module
pragma.
The name specified in map_to_module pragma has not
yet been read.
CDFG-816 Attempt to override localparam
definition.
Localparams cannot be overridden by module instance
parameter value assignments or Defparam.
CDFG-817 Illegal positional port association
for instantiation of cell with power
and ground pins.
Only named port association is allowed for
instantiations of cells with power and ground pins.
CDFG2G-200 Could not create implementation. Final netlist will not contain the referenced node.
CDFG2G-201 Could not connect node. Final netlist will not contain connections to the
referenced node.
CDFG2G-203 Could not create implementation
for variable. Variable indexes
larger than 32 bits are not
supported.
Error during elaboration.
CDFG2G-204 Could not process alias names for
complex port.
Error during elaboration.
CDFG2G-209 DCset overlaps with (ONset u
OFFset).
Error during elaboration.
CDFG2G-211 Could not set library domain. Load the libraries into the library domain first.
CDFG2G-212 Number of pins on a positional
instantiation exceeds the number
of pins present on the module
definition for the instantiation.
Error during elaboration.
CDFG2G-213 Could not find pin in module
definition.
Error during elaboration.
CDFG2G-215 Inferred a flip-flop triggered by a
falling clock edge.
Use 'set_attribute hdl_error_on_negedge false' to allow
falling edge-triggered flip-flops.
CDFG2G-416 Could not connect ports. The connection between the referenced ports will not
be implemented in the final netlist.
CDFG2G-700 Could not create ET RAM. Error during elaboration.
CG-101 Failed to insert clock-gating logic. Make sure you have permission to write to /tmp/
directory. It is required to create discrete clock-gating
logic.
CG-201 Failed to insert observability logic. Read and elaborate the design. Insert clock-gating
logic with observability logic. Rerun the 'clock_gating
insert_obs' command to insert observability logic.
CG-207 Failed to insert observability logic. Make sure the clock pin of the clock-gating instance is
connected.
CG-209 Failed to insert observability logic. Make sure there is a clock input pin on the clock-gating
instance.
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CG-215 Failed to insert observability logic. Make sure that the library cell name specified using
'-libcell' option is correct, and that it exists in all the
defined library domains. Skip the '-libcell' option to allow
RC to pick up appropriate library cell for gating the
observability flops automatically.
CG-216 Failed to insert observability logic. Currently, only an AND gate can be specified using
'-libcell' option for gating observability flops. Skip the
'-libcell' option to allow RC to pick up appropriate library
cell for gating the observability flops automatically.
CG-300 Failed on clock_gating share. The '-max_stage' option of the 'clock_gating share'
command specifies the maximum number of shared
stages of clock-gating logic. It should be either a
positive number or a list of lists, where each of these
lists is a 2-tuple of the form '{<clock> <positive
number>}'.
CG-301 Failed on clock-gating share. Make sure that there is a clock input pin on the
clock-gating instance.
CG-406 Cannot remove clock-gating logic
from subdesign.
You can only remove clock-gating logic from the design
or from a hierarchical instance.
CG-426 Could not remove clock gating
instance.
The specified clock gating instance gates a flop whose
Q pin or out pin does not drive any logic.
CG-500 Bad value for option '-start_from'. The value has to be a valid path for a hierarchical
instance.
CG-701 Could not find clock to insert
dummy clock-gating logic.
Define a clock using the command define_clock.
CHECK_CWD-107 The location attribute for the
hdl_comp is set to null.
Specify the valid location attribute through the attribute
set_attr location.
CHECK_CWD-108 The bit_width attribute for the
hdl_pin is set to empty.
Specify the valid bit width through set_attr bit_width
attribute.
CHECK_CWD-109 The formula attribute for the
hdl_param is set to empty.
Specify the valid non_null expression for the formula
attribute.
CHECK_CWD-111 The file size set by
default_location attribute in zero.
Check whether the file name specified exists or specify
the correct file name.
CHECK_CWD-112 The file specified by the location
attribute is either empty or does
not exist.
Specify the correct file name through set_attr location
<path>.
CHECK_CWD-113 The file specified by the location
attribute is either empty or does
not exist.
Check whether the file name specified exists or specify
the correct file name.
CHECK_CWD-114 The file specified by the
pre_elab_script attribute is either
empty or does not exist.
Check whether the file name specified exists or specify
the correct file name.
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Error Messages
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CHECK_CWD-115 The module/architecture name of
the hdl_impl synthesis model is
not the same as what is defined in
the registration script.
Module name specified in the synthesis model should
be same as what is defined in the registration script.
CHECK_CWD-116 No pin_association is found for
hdl_binding.
Specify a valid non null pis_association for hdl_binding.
CHECK_CWD-117 Parameter order for hdl
architecture is not the same as hdl
component.
Specify the correct parameter order.
CHECK_CWD-118 Pin order for hdl architecture is not
the same as hdl component.
Specify the correct pin order.
CHECK_CWD-119 The parameter used in the
bit_width formula attribute does
not exist.
Specify the valid parameter name in the bit_width
formula.
CHECK_CWD-120 The parameter defined in the
legality formula does not exist.
Specify the valid parameter name.
CHECK_CWD-122 The direction of the operator pin
associated with the component pin
is not same.
Specify the correct direction.
CHECK_CWD-123 The hdl_operator output pin is
associated with multiple output pin
of the component.
The hdl_operator output pin must always associated
with one output pin of the component.
CHECK_CWD-124 The hdl_comp output pin is
associated with multiple output
pins of the operator.
The hdl_component output pin must always associated
with only one output pin of the operator.
CHECK_CWD-125 The direction of the operator pin
associated with the component pin
is not same.
Specify the correct direction.
CHECK_CWD-128 At least one hdl_operator output
pin is associated with one output
pin of the component.
Specify the correct pin_association.
CHECK_CWD-129 At least one hdl_operator input pin
is associated with one input pin of
the component.
Specify the correct pin_association.
CHECK_CWD-132 Pins specified in the bit_width
formula is not a valid synthetic
operator pin.
The operator pin specified in the bit_width formula is
not correct. Specify the valid operator pin.
CHECK_CWD-150 All of the report column widths
specified with -max_width option
are set to zero.
The list specifying the maximum column width for the
Checkpoint_name, Check_name, Effort, Description
sets all the columns to zero. A zero specification hides
the column. To see the desired columns, set the
-max_width option to a non-zero value for each column
to be viewed.
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CHECK_CWD-151 Format of list specified with
-max_width option is incorrect.
To control the width of a column of a report using
-max_width option specify the width as follows
-max_width {{<column_name1> <width1>}
{<column_name2> <width2>}}.
CHECK_CWD-152 Checkpoint name specified with
-checkpoint option is incorrect.
Specify the correct checkpoint name. The valid
checkpoints are AT_OPER_PIN AT_BIND AT_ARCH
AT_COMP DONE_COMP_BINDS DONE_ARCH_PINS
DONE_ARCH_PARAMS DONE_COMP_IMPLS
AT_ARCH_PIN AT_COMP_PIN DONE_IMPL_ELAB
DONE_IMPL_READ DONE_OPER_BINDS AT_OPER
AT_ARCH_PARAM AT_PACK AT_COMP_PARAM
DONE_OPER_PINS DONE_COMP_PINS AT_IMPL
DONE_COMP_PARAMS.
CHECK_CWD-153 Check proc name specified with
the checkname option is incorrect.
Specify the correct check_proc name.
CHECK_CWD-154 Incorrect options specified. Specify single command at one time.
CHECK_CWD-155 Check name specified with the
checkname option is incorrect.
Specify the correct check_name.
CHECK_CWD-156 Invalid combination of options
supplied to check cwd command.
The options specified while invoking check cwd
command are not compatible. Remove the conflicting
options and execute check cwd again.
CHECK_CWD-158 Format of list specified with
-checklist option is incorrect.
Specify the checklist option as follows -checklist
{{<checkpoint_name1> <check_proc1>}
{<checkpoint_name2> <check_proc2>}}.
CHECK_CWD-160 Failed on read_hdl. The design does not read successfully.
CHECK_CWD-161 Failed on create_check command.
The effort level specified while
creating a check should be either
equal to or less than the effort level
of checkpoint at which the check
needs to be registered.
Specify the correct effort level to create a check.
CHIPWARE-102 Source file specified with -src_file
option does not exist or current
user does not have read
permissions.
The path specified with -src_file option is not correct.
This can be cause if the file does not exist or user does
not have read permissions in the src_file path.
CHIPWARE-103 Encrypted file not created due to
error in writing file.
Encrypted file could not be created. This can be cause
if current user does not have write permissions in
src_file or dest_file path.
CHIPWARE-104 Error encountered while installing
ChipWare component.
A ChipWare component could not be installed due to an
error in the TCL proc for installation of the component.
Check the installation script of the component library for
syntax errors. The installation script is located at
$CDN_SYNTH_ROOT/lib/chipware/syn/<LIBRARY>/
install.tcl.
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CHIPWARE-105 TCL proc for installation of
ChipWare component not found.
Check whether the installation script for the library in
which the component exists contains a reference to the
component. The installation script is located at
$CDN_SYNTH_ROOT/lib/chipware/syn/<LIBRARY>/
install.tcl.
CHIPWARE-106 Error encountered while installing
ChipWare library.
A ChipWare library could not be installed due to
installation script not being available.
CHIPWARE-107 Error encountered while creating
ChipWare library.
The ChipWare installation script was not found at the
location $CDN_SYNTH_ROOT/lib/chipware/install/
install.tcl. Check if the tool was correctly installed.
CHIPWARE-108 Error encountered during
ChipWare libraries installation.
Continuing without installing
ChipWare.
The ChipWare libraries installation script could not be
found at the location $CDN_SYNTH_ROOT/lib/
chipware/install/install.tcl. Installation of ChipWare will
quit. This should not effect the execution of the tool as
long as HDL files do not contain references to
ChipWare library components. Check if the tool was
correctly installed.
CHLNK-101 Something is wrong with the
command options.
Check the options and try again.
CHLNK-102 Pin map not found. Either specify '-lenient' option to skip the pin and leave
it unconnected <or> specify a pinmap using '-pin_map'
option.
CHLNK-103 The number of pins is different. Specify pin map using '-pin_map' option with
change_link.
CHLNK-202 The instance whose link is to be
changed appears in a non
uniquified subdesign.
Either uniquify the subdesign first or try
-change_in_non_uniq_subd option with change_link.
CHNM-109 Failed to change names. Could not change names.
CPF-100 Detected error in CPF file. Fix the error and read the CPF file again. For more
information on the CPF commands, refer to the
Common Power Format Language Reference.
CPF-101 Detected a problem with instance
specified with 'set_instance'
command.
There was a problem with the specified 'set_instance'
command. Fix the error and ready the CPF file again.
CPF-102 Could not open specified file. Ensure that the specified file exists and is readable.
CPF-109 Design read by RC should not be
testbench.
A testbench design is not meant for synthesis tool.
CPF-290 Could not open the specified
library file(s).
Ensure that the library file(s) exist in the current path.
CPF_ISO-102 Wrong argument to
-enable_polarity.
-enable_polarity can take 'active_high' or 'active_low'.
CPF_ISO-103 Wrong argument to -output_value. -output_value can take 'high', 'low' or 'hold'.
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CPF_ISO-104 Wrong argument to -location. -location can take 'from' or 'to'.
CPF_ISO-105 Wrong argument to -off_domain. -off_domain can take 'from' or 'to'.
CPF_ISO-107 Enable pin/port specified is
hanging and not a driver pin/port.
An enable pin/port must either be a driver, or have a
driver. To use the driver of enable given as the enable
driver for isolation rule, set the variable
'lp_select_enable_driver' to 1.
CPF_ISO-108 Given set of options are not
accepted with '-default' switch.
The options '-to_power_domain', '-cpf_pins' and
'-exclude_pins' cannot be given with default isolation
rule.
CPF_ISO-300 Found invalid location on low
power lib cell.
Allowed valid_locations are: from|to|on|off|either|any.
CT-101 Failed to find any clocks. To report clock tree power, you must define a clock on
the design.
CT-102 Unable to find any flops in the
design.
To report clock tree power, there should be flops in the
design.
CT-104 Cannot find any buffers or
inverters in the libraries.
To create a virtual buffer tree for a clock in the design,
one of your libraries must contain either buffers or
inverters.
CTP-8 No usable clock buffers were found
in the library.
Ensure that buffer cells do not have the avoid attribute
set to true.
CTP-13 The library does not have the
minimum required usable libcells.
Clock topology planning will not continue.
CTP-17 Clock topology planning (CTP)
requires a power simulation effort
level of 'medium' or 'high'.
Set the lp_power_analysis_effort attribute
appropriately.
CTP-19 Clock topology planning (CTP) has
not been initialized and related
data is not available.
Run or pre-initialize CTP to manipulate related
information.
CTSTCH-3 No designs are available. Load the design before importing the clock specification
file.
CTSTCH-4 Specify a valid design object. Use the -design argument to indicate to which design
the clock specification should apply.
CTSTCH-5 Unmapped design. The design must be fully mapped before appending
clock tree specification information to the netlist.
CWD-1 Conflicting options were specified. Some commands allow only a single option out of a
group of mutually-exclusive options to be specified. The
list of mutually-exclusive options for each command can
be found in the detailed description of that command in
the user manual.
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CWD-2 A required option was not
specified.
Some commands require that at least one option out of
a group of essential options be specified. The list of
essential options for each command can be found in
the detailed description of that command in the user
manual.
CWD-3 Synthetic operator is not defined. Ensure the operator name was spelled correctly. You
can find the set of synthetic operators that are
registered with the tool by using the 'ls' command on
the '/hdl_libraries/synthetic/operators' directory.
CWD-4 The implicit vdir object is invalid. Specify a valid vdir object.
CWD-12 Synthetic operator pin does not
exist.
Specify a valid Synthetic operator pin. You can find the
set of pins for the given synthetic operator by using the
'ls pins' command on the '/hdl_libraries/synthetic/
operators/<synthetic_operator_name>' directory.
CWD-13 Syntax error in the list of name and
value pairs.
The correct syntax for specifying a list of name and
value pairs is { {<name_1> <value_1>} {<name_2>
<value_2>} ... {<name_k> <value_k>} }.
CWD-14 Invalid expression specified. A constant-valued bitvector is expected in this context.
CWD-16 Missing input component pin. The specific pin mapping that was assigned with the
attribute 'pin_association' for this particular binding is
invalid because it does not list a mapping for each input
component pin. Use 'pin_association' to specify a
mapping for each input component pin.
CWD-17 Unknown pin names in pin
association list.
The pin map being assigned to pin_association
attribute of the given binding is invalid since it contains
unknown pin names.
CWD-18 Failed to evaluate an expression. Syntax error in expression specified. First fix the errors
in the expression to proceed.
CWD-20 A non-existent parameter was
specified.
Ensure that the correct parameter is specified or create
the parameter using 'hdl_create parameter' command.
CWD-22 An output pin cannot be specified. The specified operation cannot be performed on output
pins.
CWD-25 The pin directions do not match. The directions specified for the pins is incorrect.
CWD-27 Could not find a parameter in the
synthesis model.
Ensure that the parameter exists in the synthesis model
or the correct file was loaded.
CWD-28 Failed to build a netlist for the
implementation.
To check for errors in the synthesis model, synthesize
only the synthesis model for the problematic parameter.
CWD-30 A pin is missing in the synthesis
model.
Ensure that the pin specified exists in the synthesis
model.
CWD-33 Could not locate file. Ensure that the file exists or the correct file path is
specified.
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CWD-34 Missing option for a builtin
implementation.
Specify a speed grade for the implementation. The
speed grade can be specified with the '-speed_grade'
option of the 'hdl_create implementation' command.
CWD-35 Invalid speed grade specified. Specify a valid speed grade value for the
implementation.
CWD-44 No formula has been specified for
the parameter.
Specify a formula for the 'width' parameter.
CWD-45 Failed to source pre-elaboration
script for implementation.
Ensure that the pre-elaboration script exists or specify
the correct path for the pre-elaboration script.
CWD-47 Failed to source post-elaboration
script for implementation.
Ensure that the post-elaboration script exists or specify
the correct path for the post-elaboration script.
CWD_INSTALL-101 Error encountered while creating
library.
Check if the tool was correctly installed.
CWD_INSTALL-102 TCL proc for installation of library
component not found.
Check whether the installation script for the library in
which the component exists contains a reference to the
component. The installation script is located at
$CDN_SYNTH_ROOT/lib/cdn/rc/cwd/
<LIBRARY>_install.tcl.
CWD_INSTALL-103 Error encountered while installing
library component.
The component could not be installed due to an error in
the TCL proc for installation of the component. Check
the installation script of the component library for
syntax errors. The installation script is located at
$CDN_SYNTH_ROOT/lib/cdn/rc/cwd/
<LIBRARY>_install.tcl.
DATABASE-104 An error has occurred.
DATABASE-106 While reading the database, an
item was expected but not found.

DATABASE-110 While reading the database, a
library cell was expected but not
found.
Load all the necessary libraries before reading a
database.
DATABASE-114 The setup script belonging to this
database must be sourced before
loading this database.
This database was written along with a setup script.
That setup script needs to be sourced before this
database can be read.
DATABASE-115 The database can only be written
to a regular file when option -script
is given.
Do not specify the -script option or write the database
to a regular file.
DATABASE-116 While reading the database, a
database written in a newer
version was encountered.

DATABASE-119 Command read_db requires either
a file name argument or option
-from_tcl.
To read a database from a file, specify the file name
and do not use option -from_tcl. To read a database
from a Tcl variable, specify option -from_tcl and do not
give a file name.
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DATABASE-121 The netlist was not found in
memory.
The database was written with option -dft_only and it
contains only DFT information and no netlist.
DEX-1 No remote servers were specified. Specify remote servers to be used using the attribute
'super_thread_servers'.
DEX-2 Could not launch any remote
servers.
Check remotes specified in the attribute
'super_thread_servers' and make sure that they are
correct and reachable.
DEX-3 Only hierarchical instance can be
specified.
Make sure that all instance specified are hierarchical
instances.
DEX-4 No instances can be given with a
default exploration power domain.
Either remove the '-default' option or remove the
specified instances.
DEX-5 Instances are not in same design. All specified instances should be in same design.
DFM-100 No 'cell_probability' found. There is no 'cell_probability' section in the coefficient
file.
DFM-202 Invalid probability value. Probability values must be in the range: (0.0 >=
<value> <= 1.0).
DFT-105 Found existing scan segment or
chain with same name.
You cannot redefine an existing scan segment (or
chain). To redefine it, use the 'rm' command to first
remove the existing scan segment (or chain) from the
'dft/scan_segments' (or 'dft/scan_chains') directory.
Then redefine the scan segment (or chain).
DFT-106 Found existing test clock (or
domain) with same name.
You cannot redefine an existing test clock (or domain).
To redefine it, use the 'rm' command to first remove the
existing test clock (or domain) from the 'dft/
test_clock_domains' directory. Then redefine the test
clock (or domain).
DFT-107 Found invalid value for
shift-register auto-identification
command option.
The value of the '-min_length' option cannot be less
than 2 (default value). The value of the '-max_length'
option must be greater than or equal to the value of the
'-min_length' option.
DFT-112 Failed to connect scan chains. The library has no flop or latch that is considered
usable. A library cell is considered not usable if it has a
'dont_use' or a 'dont_touch' attribute set to 'true' in the
.lib files. Use 'set_attribute preserve false <libcell>' and
'set_attribute avoid false <libcell>' to make a flop or
latch usable for lockup insertion.
DFT-114 Cannot insert DFT logic. The scan configuration engine excludes flip-flops from
a scan chain if these flip-flops belong to a subdesign or
hierarchical instance that is marked preserved. To
include these flip-flops on a scan chain, set the
'preserve' attribute to 'false' on the reported subdesign
or instance, then rerun the 'connect_scan_chains'
command.
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DFT-116 Failed to connect scan chains. Scan chain connection requires the definition of at least
one shift enable signal to globally connect the shift
enable pins of the scan flip-flops, or to control shared
scan data output ports. First specify a shift enable
signal using the 'define_dft shift_enable' command,
then rerun the 'check_dft_rules' command before you
rerun the 'connect_scan_chains' command.
DFT-119 Cannot find pin replacement. An instance was replaced during optimization but the
new instance did not have an equivalent for some of the
original pins. You can prevent such replacement by
specifying the element to be preserved (e.g. via
"set_attr preserve true <object>").
DFT-120 Could not identify the top design. If no design is loaded, first load and elaborate the
design before specifying the command again. If multiple
designs are loaded, respecify the command with the
'-design' option to uniquely identify the top design.
DFT-121 Found existing test signal with
same name.
You cannot redefine an existing test signal. If you need
to redefine it, use the 'rm' command to first remove the
existing test signal from the 'dft/test_signals' directory.
Then redefine the test signal.
DFT-123 Object already used in existing
scan segment or chain.
You cannot add an object (instance, segment, or pin)
that is already part of an existing scan segment or scan
chain.
DFT-124 Period of test clock and test clock
domain are incompatible.
All test clocks in a particular test clock domain should
have the same period. You can change the 'period'
attribute of the test clock to make the test clocks
compatible.
DFT-125 Bad port/pin for DFT. The port/pin cannot be used as the driving pin of a test
signal, as a driving SDI or as a load SDO. For the
intended core-side driver pin, ensure that a function
definition exists for the pin in the libcell description. The
signals associated with the function input pins should
be driven to meaningful logic values such that under
test mode setup, the function of the core-side pin
evaluates to a buffer or inverter function of the pad pin.
DFT-131 Cannot transfer dft_controllable
attribute.
An instance whose output had a dft_controllable
attribute was (re)mapped, but the new instance did not
have a corresponding input.
DFT-132 Could not add scan chain. The test signal specified with '-shift-enable' option must
refer to an existing shift-enable signal.
DFT-133 Cannot redefine a unique scan
clock signal.
A design can have only one scan clock A and one scan
clock B.
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DFT-134 Port or pin is already used for DFT
purposes.
A pin or port can only be associated with one test
signal, test clock, mbist clock or scan chain. If you want
to use the pin or port for another test signal, test clock,
mbist clock or scan chain, use the 'rm' command to first
remove the existing test signal, test clock, mbist clock
or chain from the 'dft/test_signals', 'dft/
test_clock_domains', 'dft/mbist' or 'dft/scan_chains'
directory.
DFT-135 Scan segment is already
referenced by another segment.
A scan segment can only be referenced by one scan
segment. To make it part of another segment, first
remove its current parent segment from the 'dft/
scan_segments' directory using the 'rm' command.
DFT-139 Unmapped module. One or more modules contain generic gates. The
command that triggered this message requires the
module(s) to be mapped. Look at command
"synthesize" for information on how to map a design.
DFT-141 Failed to connect scan chains. The mux inserted to share a functional output with a
scan data output requires to specify a control signal for
the mux. If the control signal was not yet defined, use
the 'define_dft test_mode' command to define the
control signal and rerun the 'check_dft_rules'
command. Next, remove the offending scan chain,
before redefining it and specifying the control signal
using the '-shared_select' option of the 'define_dft
scan_chain' command. Rerun the
'connect_scan_chains' command.
DFT-142 Could not obtain the required
license.
A command or option requires a license that could not
be obtained.
DFT-143 Invalid license requested. A command or option requested an invalid license.
DFT-150 Could not create scan chain. Refer to the Command Reference for Encounter RTL
Compiler for more information about the options of the
'define_dft scan_chain' command. Then rerun the
command after specifying the options correctly.
DFT-154 Cannot write out the scanDEF
information for the design.
Run the 'connect_scan_chains' command to connect
the chains and then rerun the 'write_scandef'
command.
DFT-156 Cannot remove core-wrapper-cell
segment.
Removal of core wrapper cell segments can result in
loss of information on inserted core-wrapper cells.
Hence removal of core-wrapper segments is not
allowed.
DFT-157 An object in segment being
defined is not compatible with the
segment definition.
Some objects may not be included in a segment, e.g.
combinational elements in a floating segment, or
complex sequential elements in a segment.
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DFT-159 Cannot generate dft abstraction
model due to definition of internal
test-signal.
Test related signals are expected to be controllable
from the top module ports to write out a valid model
Test related objects are test_clocks, test_signals,
scan-data input and output signals.
DFT-165 Test clock has no source pin. A test clock must have a source pin identified.
DFT-167 Cannot define an internal clock as
equivalent to another clock.
Current version of this tool does not support defining an
internal clock equivalent to another clock.
DFT-169 Could not define abstract
segment.
The current tool version only supports abstract
segments for the muxed scan style.
DFT-172 Failed to connect scan chains. Scan chain connection requires the definition of the
scan clock A signal to globally connect the
corresponding pin of the scan flip-flops. First specify
the missing scan clock signal using the 'define_dft
scan_clock_a' command, then rerun the
'check_dft_rules' command before you rerun the
'connect_scan_chains' command.
DFT-173 Failed to connect scan chains. Scan chain connection requires the definition of the
scan clock B signal to globally connect the
corresponding pin of the scan flip-flops. First specify
the missing scan clock signal using the 'define_dft
scan_clock_b' command, then rerun the
'check_dft_rules' command before you rerun the
'connect_scan_chains' command.
DFT-174 Failed to run the DFT rule checker. When the attribute 'map_to_master_slave_lssd' is true,
only scan style applicable is clocked_lssd. Change the
scan style by setting the attribute 'dft_scan_style' to
clocked_lssd and rerun the 'check_dft_rules' command.
DFT-175 Could not define shift_register
segment.
Ensure that the start and end flops of a shift register
segment are different, that all elements of the segment
are flops, and that there is a shift path under test mode
from the start flop to the last flop.
DFT-178 Invalid shift register segment. A shift register is considered a valid scan segment if the
tool can trace back through all flops in the register.
Check if the connection to the input of the reported
register is missing or if it is driven by combinational
logic that cannot be reduced to a buffer or inverter. Fix
the connection problem and redefine the segment.
DFT-181 Found an invalid shift-register
element.
To include the shift-register segment during scan chain
connection, reset the 'dft_dont_scan' or 'preserve'
attribute on the specified flop to 'false', rerun the
'check_dft_rules' command, then run the
'replace_scan' command before you rerun the
'connect_scan_chains' command.
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DFT-183 Invalid shift register segment. A shift register is considered a valid scan segment if the
set, reset, and preset pins of all its flops are held at
their inactive value and the enable pin is held to its
active value. Ensure that test mode signals are
specified for the synchronous pins of the flops in the
shift register.
DFT-184 Could not define segment. A scan segment cannot contain top level ports as its
elements. Refer to the Command Reference for
Encounter RTL Compiler for more information on the
type of elements that can be specified for this type of
segment.
DFT-188 Could not define shift_register
segment.
Shift register segments are only supported for the
muxed scan style.
DFT-194 Could not write scanDEF
information for design.
If the actual scan chains were built for multi-mode
configuration using the 'connect_scan_chains
-dft_configuration_mode' options, use the
-dft_configuration_mode option to the write_scandef
command to generate the scanDEF output.
DFT-195 Failed to generate ATPG interface
files.
Check to see whether you have specified the correct
options to the write_atpg command. The -compression
option is only valid with the -cadence option. Exactly
one of -mentor, -stil and -cadence options must be
specified.
DFT-197 Failed to perform compression. To add masking logic, you must specify the '-mask'
option along with any other masking options.
DFT-198 Failed to perform compression. To add 'WIDE2' channel mask register, you must
specify a list of two enable signals with the
'-mask_enable' option. To add a 'WIDE1' channel mask
register, you must specify one enable signal with the
'-mask_enable' option.
DFT-200 Found invalid value for command
option.
Correct the value for the specified option and rerun the
command.
DFT-201 Found incompatible options. Refer to the Command Reference for Encounter RTL
Compiler for more information about the options of this
command. Then rerun the command after specifying
the options correctly.
DFT-202 Required option missing. One or more specified options additionally require an
option that is not specified. Add the missing option and
rerun the command.
DFT-203 Same signal specified for multiple
purposes.
The same signal (test_signal, pin, or port) has been
specified for two options which must be set to different
signals. Select a different signal for one of the options
and rerun the command.
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DFT-205 Shared compression clock. The mask or misr clock should be a dedicated clock pin
since it will be used for loading the channel mask
registers or resetting the MISR. Only if the test clock
being shared has been gated off during these test
sequences can the clock be shared with compression.
If this gating logic is already in place, specify the
-allow_shared_clock option to allow the clock to be
used for compression.
DFT-206 Invalid test signal. The specified test signal cannot be used. Determine
why the test signal cannot be used or specify a different
test signal.
DFT-207 Invalid test clock. The specified clock cannot be used. Determine why
the clock cannot be used or specify a different clock.
DFT-208 Scan chain cannot be
compressed.
A scan chain requested for compression cannot be
compressed. Remove this chain from the list of chains
to compress and rerun the command.
DFT-209 No scan chains to compress. Use connect_scan_chains to create scan chains, or
select a different set of scan chains to compress.
DFT-210 Too few scan chains for OPMISR
compression.
Include more scan chains for compression or use XOR
compression instead of OPMISR compression.
DFT-213 Cannot use OPMISR
compression.
The design is not compatible with OPMISR
compression.
DFT-214 Shared compression enable
signal.
To proceed with scan chain compression, you must
specify the '-master_control' option. This option is
required to disable the test path in system mode to
guarantee proper system mode operation.
DFT-215 Could not mark object as DFT
controllable.
The dft_controllable attribute is used to specify the
logical connectivity across a set of input and output pins
belonging to the same instance (of a blackbox, logic
abstract or timing model reference). To set the
dft_controllable attribute across pins of multiple
instances, specify the attribute separately for each
instance.
DFT-216 Found an uncontrollable
compression clock.
If the compression clock is driven by an output pin of a
black-box instance, you can specify the logical
connectivity across the pins of the instance using the
'dft_controllable' attribute. If the compression clock is
not driven by a black-box output pin, you must define
the compression clock as a test clock using the
'define_dft test_clock' command and specify its internal
hookup pin using the 'hookup_pin' option.
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DFT-217 Incompatible test clocks drive the
scan chains that are selected for
compression.
Two scan chains targeted for compression are driven by
test clocks that are incompatible. Scan chains that are
compressed at the same must all be driven at the same
test clock frequency. Ensure all test clocks used in
compression mode have the same period or select a
different set of scan chains to compress.
DFT-218 An incorrect hookup pin was
specified.
The 'define_dft scan_chain' command expects the pin
specified for the '-hookup_pin_sdi' option to be a driver
and the pin specified for the '-hookup_pin_sdo' option
to be a load. To query the direction of the pin, use the
'get_attribute direction <Pin>' command.
DFT-219 Cannot generate dft abstraction
model because chains have TDRC
errors.
Fix the TDRC errors in all the chains before writing out
the abstraction model. Use the 'report dft_chains -chain
<chainName>' to list the elements of the scan chain. A
scan flop in the chain that fails TDRC will have a 'Fails
DFT rules' entry in the scan report besides it.
DFT-221 Did not specify the required
Verilog library files.
The library files are required to write the netlist and pin
assignment files which are used by Encounter Test
software to validate the mapped design.
DFT-222 MISR compression is only
supported for muxed_scan.
There is no more help available in this message. If the
help in this message was insufficient, contact customer
support with this message ID.
DFT-223 Cannot ungroup instance. The JTAG_MACRO instance is referenced by other
DFT commands such as 'insert_dft MBIST[PTAM]', and
therefore its reference must be maintained to complete
the DFT insertion flow. Additionally, its reference is also
used by the write_do_lec command to validate the final
design.
DFT-225 DFT configuration mode exists. To update the test signal values specified for the
existing dft configuration mode, you must first remove
the configuration mode and then redefine it by
specifying the test signals with their updated test mode
active values.
DFT-227 Failed to compress scan chains. The library has no latch that is considered usable. A
library cell is considered not usable if it has a 'dont_use'
or a 'dont_touch' attribute set to 'true' in the .lib files.
Use 'set_attribute preserve false <libcell>' and
'set_attribute avoid false <libcell>' to make a latch
usable for lockup insertion.
DFT-228 Cannot create port. Specify a valid port name and rerun the command.
DFT-229 Could not define jtag_macro. Only one JTAG Macro can be defined. Define a JTAG
Macro using 'define_dft jtag_macro' on an instance in
the design or on a libcell or module that is only
instantiated once in the design.
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DFT-231 Required pin is missing on the
JTAG macro.
A required pin or definition of a pin for the JTAG macro
instance is missing. If the pin is present make sure it is
included in the definition of the JTAG macro.
Instruction-specific JTAG Macro pins, such as the
instruction-decode pin and the input pin that the custom
register TDO connects to, must be defined using the
'define_dft jtag_instruction' command. All other JTAG
Macro pins must be defined using the 'define_dft
jtag_macro' command.
DFT-232 Required attribute is missing on
the JTAG instruction.
A required attribute defining an instruction specific pin
for the JTAG macro instance is missing. If the pin is
present make sure it is included in the definition of the
JTAG instruction.
DFT-233 Found existing mbist clock with
same name.
You cannot redefine an existing mbist clock. To redefine
it, either use the '-name' option or use the 'rm'
command to first remove the existing mbist clock from
the 'dft/mbist/mbist_clocks' directory. Then redefine the
mbist clock.
DFT-234 JTAG instruction specified as
mode control before JTAG macro
is defined.
Insert the JTAG Macro in your design using either the
insert_dft boundary_scan command or the insert_dft
jtag_macro command. This will automatically set the
tap decode pin for the instruction. If you have a third
party JTAG macro already as part of your design then
identify it using the define_dft jtag_macro command
and respecify the define_dft jtag_instruction command
taking care to identify the decode pin corresponding to
this instruction with the -tap_decode option of the
command.
DFT-237 Cannot remove test signal. To remove the test signal, you must first remove the
actual scan chain. If after deleting the actual scan chain
you then remove the test signal, the scan configuration
mode that was defined using the test signal will also be
removed.
DFT-239 Osc Source already defined. To redefine the osc source, you must first delete any
opcg domains and opcg triggers that are using the osc
source and then delete the offending osc source.
DFT-240 Incorrect reference clock pin for
osc source.
Redefine the osc source so that the reference clock is
either a top level port or the output pin of another osc
source.
DFT-241 Domain Macro Parameter already
defined.
To redefine the domain macro parameter, you must first
delete any opcg domains that are using the domain
macro parameter and then delete the offending domain
macro parameter.
DFT-242 Opcg Trigger already defined. To redefine the opcg trigger, you must first delete any
opcg domains that are using the opcg trigger and then
delete the offending opcg trigger.
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DFT-243 Opcg Domain already defined. To redefine the opcg domain, you must first delete the
offending opcg domain and then redefine.
DFT-244 Opcg Mode already defined. To redefine the opcg mode, you must first delete the
existing opcg mode.
DFT-245 Invalid oscillator source
parameters.
To specify oscillator source parameters, provide a 3
element list in the following format: <osc source name>
<osc source output operating period> <reference clock
period>.Parameters for a single oscillator source may
only be specified once per opcg mode definition.
DFT-246 Oscillator source parameter
specified for opcg mode is out of
range.
The reference clock period and the oscillator source
operating period specified to the
'-osc_source_parameter' option to the 'define_dft
opcg_mode' command must fall between the range of
acceptable values defined on the 'osc_source' objects
in the 'dft/opcg/osc_sources' directory.
DFT-249 Could not set custom se. The test signal specified for 'dft_custom_se' attribute
must refer to an existing shift-enable signal.
DFT-250 Cannot remove Osc Source. Remove the opcg triggers or opcg domains in which the
osc source is being used before attempting to remove
the osc source.
DFT-251 Cannot remove Opcg Trigger. Remove the Opcg Domains in which the opcg trigger is
being used before attempting to remove the opcg
trigger.
DFT-252 Cannot remove Domain Macro
Parameter.
Remove the Opcg Domains in which the domain macro
parameter is being used before attempting to remove
the domain macro parameter.
DFT-253 Cannot remove OPCG vdir object. Remove the OPCG logic and the abstract segments
defined on the OPCG logic before attempting to remove
the OPCG vdir objects.
DFT-256 Unsupported max trigger delay
value.
Specify a max trigger delay value that is at most 254
times the minimum target period.
DFT-259 Found preserved pin/port/net/
subdesign for OPCG insertion.
To proceed with OPCG insertion, the 'preserve'
attribute for the pin/port/net/subdesign must be set to
'false'.
DFT-260 Invalid test signal. The specified test signal cannot be used as OPCG
edge mode signal.
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DFT-261 Cannot insert OPCG logic. OPCG insertion is not possible in case the scan style is
anything other than muxed scan style or in case the
scan chains are already compressed. In case OPCG
insertion failed because the preserved attribute on an
instance or module is set to true then remove that to
proceed with OPCG insertion. In case OPCG insertion
failed because OPCG domains are not defined then
use the define_dft opcg_domain command to define
the OPCG domains and then proceed with OPCG
insertion. In case scan segments are defined on the
domain, trigger and divider macros, remove them also
to proceed with OPCG insertion.
DFT-262 Hookup pin for OPCG port not
found.
If there is an unconfigured pad connected to the OPCG
port then configure it with the 'configure_pad_dft'
command before rerunning the 'insert_dft opcg'
command.
DFT-263 Cannot write out Encounter Test
files for OPCG.
The '-delay' option to 'write_et_atpg' may only be
specified if OPCG logic has been inserted using the
'insert_dft opcg' command and connected using the
'connect_opcg_segments' command. An OPCG mode
must also be defined using 'define_dft opcg_mode'.
DFT-265 Did not find any user-defined or
actual scan chains in the design.
To proceed, specify the number of scan chains to be
built and analyzed using the '-chains' option.
DFT-266 Cannot define the scan chain. All elements of a scan chain (pins, flops, segments)
must belong to the same design to which the scan
chain is defined.
DFT-267 Failed to analyze specified scan
chain or scan segment.
To proceed, you must set the instance level attribute for
the register to 'dft_dont_scan false' and rerun the
check_dft_rules command before defining the scan
chain or scan segment with the '-analyze' option.
DFT-268 The minimum scanned flop
threshold is not met.
To proceed, connect the remaining registers into scan
chains, or specify a lower threshold using the switch
'-minimum_scanned_flop_percentage'.
DFT-269 The minimum scannable flop
threshold is not met.
To proceed, correct any DFT rule violations, replace
any non-scan flops to scan flops using the
'replace_scan' command, or specify a lower threshold
using the '-minimum_scanned_flop_percentage' option.
DFT-272 TDRC data not available. Test Design Rule Check (TDRC) data is not available.
Either check_dft_rules has not been run or some other
operation has caused TDRC data to be invalidated, for
example, netlist changes, modification of test clocks or
signals, etc.
DFT-273 Bad compression ratio. To proceed, specify a compression ratio value greater
than or equal to '2'.
DFT-274 Scan chains not found. To proceed, specify the number of scan chains to be
built using the '-chains' option.
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DFT-277 Unmapped module. One or more modules contain generic gates. The
command that triggered this message requires the
module(s) to be mapped. Look at command
"synthesize" for information on how to map a design.
DFT-278 Incorrect power mode. To proceed, ensure that the string provided for the
'-power_mode' option is the same string (case
sensitivity applies) listed for the 'CpfPowerMode'
identifier in the TCF file.
DFT-279 Long list of library files. Some
systems may not support a list of
library files longer than 1024
characters.
To include a long list of library files, put the list into a file
using 'include and specify that file as the library.
DFT-280 Invalid net for OPCG insertion. Ensure that there is a valid net at the location at which
the OPCG domain macro is to be inserted and it is not
undriven. If required redefine the location at which the
macro is to be inserted using the define_dft
opcg_domain command.
DFT-288 Multiple Test clocks found. Multiple test clocks are not supported in smartscan
flow. Use a single test clock instead.
DFT-289 Logic BIST cannot be inserted. Correct the information mentioned and retry insertion.
DFT-320 Hookup polarity of test signal
conflicts with the actual polarity.
Redefine the test signal or disable the conflict check by
setting the attribute 'dft_verify_test_signal_hookup' to
false.
DFT-404 Invalid segment configuration. Identified segment has invalid configuration.
DFT-407 Could not satisfy scan
configuration constraints.
If the design has both positive and negative edge
triggered flops that you intend to put into the same scan
chains, ensure that you allow merging of the mixed
edges by specifying the design level attribute
'dft_mix_clock_edges_in_scan_chains true'.
Otherwise, you may need to define additional scan
chains, or use the '-auto_create_chains' option to the
'connect_scan_chains' command to automatically
create the required number of scan chains.
DFT-409 Invalid or missing TDRC data on a
scan register.
Invalid or missing TDRC data could be due to manual
editing of netlist, or not running check_dft_rules after
inserting DFT logic, such as user_testpoints. Rerun
check_dft_rules to restore valid TDRC data on all
registers.
DFT-411 Primary pins used as scan-in or
scan-out of segment.
A segment cannot have a primary pin as its end pins.
Hence using scan_chain definition is more appropriate.
DFT-412 Failed to connect scan chains
because of an invalid segment
configuration.
Do a get_attr dft_violation on the segment to know all
the violations for this segment.The problem requires
that you fix your HDL files.
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Error Messages
May 2013 190 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
DFT-413 Cannot connect the specified
segment to a scan chain.
If you need to keep the existing chain, use the 'rm'
command to remove the segment causing the problem
and rerun 'connect_scan_chains' in incremental mode.
Refer to 'Removing Scan Segment Constraints' in the
'Controlling Scan Configuration' chapter of the Design
For Test in Encounter RTL Compiler guide for more
information. If you do not need to keep the existing
chain, rerun 'connect_scan_chains' without the
'-incremental' option.
DFT-414 Invalid shift-register segment
configuration.
By definition, all of the elements of a shift-register
segment should be triggered by the same test clock
and same active edge. Different test clocks can only be
accepted if you define these clocks as equivalent
before scan chain connection. Different clock edges
can never be accepted in a shift-register segment.
DFT-419 Could not connect scan chains. To use the
'-dont_exceed_min_number_of_scan_chains' option,
you must first set the design attribute
'dft_min_number_of_scan_chains'.
DFT-420 Could not connect scan chains. To proceed, either revise the design attribute
'dft_min_number_of_scan_chains', or dont specify the
option '-dont_exceed_min_number_of_scan_chains'.
DFT-421 Failed to analyze connectivity of
preserved segment.
If the preserved segment has combinational logic in its
scan path, ensure that you have defined the test mode
control signals to properly configure the test path for
these combinational logic gates.
DFT-422 Cannot concatenate a chain. A specified chain specified on '-chains' option cannot
be concatenated. Remove the chain from the option
value and rerun the command.
DFT-423 Cannot concatenate a chain. A specified chain specified on '-chains' option cannot
be concatenated. Set the attribute
'dft_mix_clock_edges_in_scan_chains' to true or
remove the chain from the option value and rerun the
command.
DFT-500 Invalid scan element. The element cannot be used in scan chain/segment.
Possible causes for this are flip-flops not yet mapped to
scan equivalent cells, instances with missing scan pins
in the library, or improperly specified scan segments.
DFT-533 Cannot satisfy clock skew
requirements during scan shift.
To satisfy clock skew requirements during scan shift,
you can either set the design level attribute,
'dft_lockup_element_type' to 'preferred_edge_sensitive'
or 'preferred_level_sensitive', not allow mixing of clock
edges in the same scan chain or remove segments that
might have flops with mixed clock edges.
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Error Messages
May 2013 191 Product Version 12.2
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DFT-551 Could not connect scan chains. Rerun the DFT rule checker to update the DFT status of
the registers that belong to the instance for which the
abstract segment was defined. If a DFT violation is
detected for the segment, fix the violation using the
'fix_dft_violations' command and rerun the
'connect_scan_chains' command.
DFT-560 Could not connect scan chains. Rerun the 'connect_scan_chains' command with the
-mode_high_pins or -mode_low_pins options to
connect multimode abstract segments that share SDI
or SDO pins. Alternately specify only non multimode
abstract segments with the 'connect_scan_chains'
command.
DFT-562 Could not disconnect net. Rerun the 'connect_scan_chains' command after
unpreserving the net marked as preserved by user.
DFT-563 Wrong no. of values for option. The no. of values passed to '-location' should be the
same as passed to '-flops'.
DFT-566 No scan chains to update. Use connect_scan_chains to create scan chains, or if
actual scan chains are present, make sure they are not
compressed.
DFT-600 The IEEE 1500 wrapper insertion
could not proceed because the
command encountered pin or port
locations which could not be
wrapped.
To continue, rerun the command with the
'-skipped_locations_variable' option.
DFT-601 Failed to read CTL scan abstract
model.
Correct the syntax error and read the CTL file back in
with the 'read_dft_abstract_model -ctl' command.
DFT-603 Scan chain information missing in
CTL file.
Add the missing information in the 'ScanChain' block for
the chain and read the CTL file back in with the
'read_dft_abstract_model -ctl' command.
DFT-604 CTL file has multiple
'ScanStructures' blocks with same
name.
Change your CTL file to ensure that each
'ScanStructures' block has a unique name, then read
the CTL file back in with the 'read_dft_abstract_model
-ctl' command.
DFT-605 CTL file has multiple 'ScanChain'
blocks with same name.
Change your CTL file to ensure that each 'ScanChain'
block within a 'ScanStructures' block has a unique
name, then read the CTL file back in with the
'read_dft_abstract_model -ctl' command.
DFT-606 Polarity of ScanEnable in
ScanStructures block differs from
polarity in CTLMode InternalTest
block.
Change your CTL input so that the polarity is the same
in both the blocks.
DFT-607 Could not find a libcell or
subdesign of the required name.
Change your CTL input so that the name of the
Environment block corresponds to a subdesign in the
design or a libcell in the library.
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Error Messages
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DFT-608 Complex or Gated ScanEnable
signal found.
Change your CTL input so that the ScanEnable signal
is simple (like 'a' or '~a'). You can also remove the
ScanEnable statement from the ScanChain block to
generate an abstract model with the
-connected_shift_enable option.
DFT-609 Found Environment blocks with
the same name.
Change your CTL input so that there are no two
Environment blocks with the same name.
DFT-610 CTL file has multiple 'CTLMode'
blocks with same name.
Change your CTL file to ensure that each 'CTLMode'
block has a unique name, then read the CTL file back in
with the 'read_dft_abstract_model -ctl' command.
DFT-612 Could not determine the clock
edge for the chain.
This could be because the clock edge for the chain is
derived from the entry for the SDI port in the CTLMode
block that is attributed with a 'TestMode InternalTest'
statement. Modify your CTL input file so that ports are
defined in a CTLMode block attributed with the above
statement.
DFT-702 Specified chain is not an analyzed
scan chain.
Data lockup elements can only be inserted in analyzed
scan chains. Analyzed chains are chains that were
defined in the current session using the 'define_dft
scan_chain -analyze' command.
DFT-713 Cannot insert lockup elements in
analyzed scan chain.
If the elements in the analyzed chain belong to different
test clock domains, you must declare them compatible
using the 'set_compatible_test_clocks' command
before inserting lockup elements. If the elements are
clocked by opposite edges of the same test clock or
different test_clocks which have been defined
compatible, and mixing of clock edges is allowed, set
the design attribute
'dft_mix_clock_edges_in_scan_chains' to 'true'. If some
elements failed the DFT rule checker, use the 'report
dft_violations' command to list the violations, fix the
violations, then rerun the 'check_dft_rules' command. If
an element is marked dft_dont_scan, set the
'dft_dont_scan' attribute to 'false' on the reported
element. In all cases, rerun the 'insert_dft
lockup_element' command as the last step.
DFT-721 Scan path analysis failed. If there is combinational logic in the scan path, ensure
that you have defined the test mode control signals to
properly configure the test path for these combinational
logic gates.
DFT-800 Cannot connect scan chains in
physical mode without placement
information.
Read in the DEF file using the read_def command to
proceed with placement information based scan
stitching.
DFT-801 The -min_wire_length option is not
allowed without the -physical
option.
Specify the -physical option and the -min_wire_length
option for physical information based scan stitching.
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Error Messages
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DFT-803 Incorrect value of
-min_wire_length specified.
Specify the -min_wire_length option with a value that is
greater than 0.0 and less than the height/width of the
core.
DFT-901 JTAG Port already defined. Delete the JTAG port and then respecify using the
define_dft jtag_port command.
DFT-902 Cannot create port for non TAP
Controller JTAG Port.
Create the port using the edit_netlist command and
then redefine the jtag port using the define_dft jtag_port
command without the -create option.
DFT-903 Cannot define jtag instruction. Define the jtag instruction after defining the jtag
instruction register using the define_dft
jtag_instruction_register command.
DFT-904 Cannot define additional jtag
instructions.
Delete all the existing jtag instructions and jtag
instruction register and then redefine the jtag
instruction register with an increased length.
DFT-905 Cannot redefine jtag instruction. Delete the existing jtag instruction with the same name
and then redefine.
DFT-906 Cannot redefine jtag instruction. Delete the existing jtag instruction with the same
opcode and then redefine.
DFT-907 Invalid opcode. Specify an opcode value so that the number of bits in its
binary representation is equal to the length of the
instruction register.
DFT-908 Cannot redefine jtag instruction
register.
Delete the existing jtag instruction register and jtag
instructions and then redefine using the new instruction
register.
DFT-910 Invalid jtag instruction register
definition.
Redefine the jtag instruction register using the
define_dft jtag_instruction_register command.
DFT-911 Invalid capture value. Specify a capture value so that the number of bits in its
binary representation is less than or equal to the length
of the instruction register.
DFT-912 Invalid opcode. Valid opcodes are a string of 0's and 1's optionally
preceded by a number of x's.
DFT-913 Invalid capture value. Redefine the jtag instruction register so that the binary
representation of its capture value has at least two bits.
DFT-914 Invalid capture value. Redefine the jtag instruction register so that the last two
bits in the binary representation of its capture value is
always '01'.
DFT-915 Invalid custom register length. Redefine the jtag instruction so that the length of the
custom register is at least one.
DFT-916 Invalid instruction register length. Set the instruction register length to be greater than or
equal to the number of bits required to representation
the capture value of the register.
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Error Messages
May 2013 194 Product Version 12.2
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DFT-917 Invalid opcode. Redefine the jtag instruction so that its opcode is not
the all 1's pattern. Only the BYPASS instruction is
allowed to have the all 1's pattern as its opcode.
DFT-918 Name of the custom data register
of jtag instruction is same as jtag
instruction register name.
Redefine the jtag instruction so that the name of its
custom data register is not the same as the name of the
jtag instruction register.
DFT-919 Boundary-scan segment already
defined.
Delete the boundary-scan segment and then respecify
using the define_dft boundary_scan_segment
command.
DFT-920 Boundary scan insertion failed. The DEF file must include placement information for the
pad connected to the TDI port. The DEF file must also
contain the physical locations for the pad cell instances
for the listed ports. If these ports are not to be included
in the boundary register chain, rerun boundary scan
insertion and list these ports to be excluded using the
'-exclude_ports' option. Otherwise, read in a DEF file
which contains the physical location of all the ports and
their pad cell instances, and then rerun the 'insert_dft
boundary_scan -physical' command.
DFT-921 JTAG Macro already defined. Delete the JTAG Macro and then respecify using the
define_dft jtag_macro command.
DFT-922 Instruction must access boundary
register.
The 'extest_pulse' and 'extest_train' instructions may
only access the 'boundary' register. Redefine the
instruction by specifying the 'boundary' register.
DFT-923 Boundary Scan Logic already
inserted.
The IOSpecList input file is used to customize the
architecture of the boundary-scan register to be
built.For its information to be used, the file must be read
prior to inserting the boundary-scan logic.If the
boundary-scan logic was inserted prior to reading this
file, you must exit the tool and rerun the commands in
the proper order of execution.
DFT-924 The boundary-scan logic has
already been inserted in the
design.
Boundary-scan insertion will not be run to avoid
inserting redundant boundary-scan cells into the
system path of the functional I/O cells.If the
boundary-scan logic does not meet your expectations,
you must exit the tool and re-insert the logic.
ECCD-412 Unable to run CCD. Set the environment variables
VERPLEX_HOME_CCD/PATH appropriately.
ECCD-413 Unable to complete CCD run. Check the log to proceed further.
ECCD-415 Errors reported by CCD. This may result in design errors.
ECCD-416 Unable to run CCD. Make sure that the required license is available before
using the command.
ECO-100 File/Directory not found. Check if the file/directory exists.
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Error Messages
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ECO-101 Error while reading in file. Check if the file/directory exists and change
permissions if necessary.
ECO-102 Invalid effort level for syn -to_map. The valid effort levels are 'low','medium' and 'high'.
ECO-103 Error while opening file for writing. Check if the file/directory exists and change
permissions if necessary.
ECO-104 Error while executing the contents
of the file.
Check the syntax of the file contents.
ECO_MANIPULATION-100 Addition of the object not possible. Addition of the object does not possible as the object
already exists.
ECO_MANIPULATION-101 Deletion of the object not possible. Deletion of the object not possible as the object does
not exist.
ECO_MANIPULATION-102 ECO command failed. ECO Manipulate command failed.
ELABUTL-120 Inout/Output ports of an instance
cannot be driven by supply0/
supply1.
Check port connectivity of an instance.
ELABUTL-121 Too many port connections on the
instance.
Check port connectivity of an instance.
ELABUTL-122 Invalid port name in module/cell. Check if technology libraries are specified correctly.
ELABUTL-126 Invalid bit position of port. Check port details.
ENC-1 Encounter executable not found. The Encounter executable was not found. Assure that
'encounter' is in the path and retry the command.
ENC-9 Encounter failed to launch. The Encounter executable could not launch. Ensure
that you have the ENCOUNTER environment variable
properly defined or that the Encounter executable is in
your path. Restart the tool after you have properly
defined the variable or set up the path.
ENC-14 Encounter batch job did not finish
properly.
An error occurred with the Encounter batch job. Check
log for details on the errors. Run the command again
after correcting the errors.
ENC-16 Encounter command failed. The cited Encounter command failed. See the logfile for
additional details.
ENC-22 Specified library file is a directory. The cited library file is a directory. Mention individual
library file names instead.
ENC_MSV-101 There was a problem accessing
the given file.
Give a different file name.
ENC_MSV-102 Unable to create temporary files. There are too many files with the temporary prefix.
ENC_MSV-103 A design with the given design
name does not exist.
Supply a valid design name.
ENC_MSV-104 The design is not supported by
Encounter.
Make sure that all instances in a power domain are in a
single library domain.
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Error Messages
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ENCRYPT-1 Invalid combination of arguments. The specified combination of arguments to this
command is not valid. Consult the documentation to
determine valid argument combinations.
ENCRYPT-3 The file to be encrypted does not
exist or the current user does not
have read permissions.
Verify the specified encryption file exists and has proper
read permissions.
FILE-100 File error. Make sure that the file is a readable regular file and has
the specified name.
FILE-104 Cannot gunzip old binary. Regenerate a newer version of this binary.
GSC-300 Exactly 2 pins should be present
for unique gsc_pin_type.
If pins have the same gsc_pin_function, and are of the
gsc_pin_type unique, there must be exactly 2 pins.
GSC-301 More than 1 driver pin found for
shared gsc_pin_function.
There must be exactly 1 driver pin for pins having the
same gsc_pin_function.
GSC-302 No driver pin found for shared
gsc_pin_function.
There must be exactly 1 driver pin for pins having the
same gsc_pin_function.
GSC-303 No receiver pins pin found for
shared gsc_pin_function.
At least 1 receiver pin should be specified.
GSC-304 2 terminal pins must exist for a
daisy chained network.
For pins of daisy chained network having the same
gsc_pin_function, there must be exactly 2 pins with a
gsc_pin_type of terminal.
GSC-305 No terminal pins found for a daisy
chained network.
For pins of daisy chained network having the same
gsc_pin_function, there must be exactly 2 pins with a
gsc_pin_type of terminal.
GSC-306 An even number of chained pins
are required.
For pins of daisy chained network having the same
gsc_pin_function, there must be an even number of
pins with a gsc_pin_type of chained.
GSC-307 No primary driver pin for daisy
chained network.
For pins of a daisy chained network having the same
gsc_pin_function, there must be a main driver pin with
a gsc_pin_type of terminal.
GSC-308 No primary receiver pin for daisy
chained network.
For pins of a daisy chained network having the same
gsc_pin_function, there must be a main receiver pin
with a gsc_pin_type of terminal.
GSC-309 Chained driver/receiver pins must
be equal.
For pins of a daisy chained network having the same
gsc_pin_function, there must be an equal number of
receiver and driver pins with a gsc_pin_type of chained.
GSC-310 Could not create file. Verify permissions are correct, and that there is enough
disk space.
GSC-311 Could not create temporary
directory.
Verify permissions are correct, and that there is enough
disk space.
GSC-312 No pins specified. No pins specified and no starting location specified.
Specify a starting location with -start <instance>.
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Error Messages
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GSC-313 No parent module found. Attempting to get parent module for top level design.
This module does not have a parent module.
GSC-314 A user specified pin order has
been specified via the
gsc_pin_order attribute, but not all
pins in the daisy chained network
have a value set for the
gsc_pin_order attribute.
Specify a valid gsc_pin_order on all pins that belong to
the daisy chained network.
GSC-315 The minimum gsc_pin_order value
for a user specified pin order has a
non zero value.
The minimum value is required to be zero.
GSC-316 The minimum and maximum
gsc_pin_order values cannot be
the same.
The minimum and maximum values are required to be
different.
GSC-317 All values for gsc_pin_order must
be accounted for in the range from
minimum to maximum.
Make sure all pins in the network have the correct
gsc_pin_order value specified.
GSC-318 The same gsc_pin_order has been
specified on multiple pins.
Make sure all pins in the network have the correct
gsc_pin_order value specified.
GSC-319 The terminal head pin must use
the maximum value gsc_pin_order
value (n) and the tail pin must use
the minimum gsc_pin_order value
(0).
Make sure all pins in the network have the correct
gsc_pin_order value specified.
GSC-320 The receiver pin in the shared
network is already being driven.
Receiver pins in a shared network must not have
existing drivers.
GSC-321 The receiver pin in the shared
network is already connected to
another receiver pin.
Receiver pins in a shared network must not already be
connected to each other.
GSC-322 Attempting to connect to an
existing pin that is not on the path
from the main driver for the
network.
Connecting the specified shared network would make
an invalid connection. Ensure the receiver pins for the
shared network are correctly specified. If reused
modules are present, perform uniquification to resolve
the issue.
GSC-323 A connection has been found on a
pin with the gsc_pin_type of open.
If the open attribute is correct, this is probably due to
reused modules. Perform uniquification on the logic
first, and then rerun.
GSC-324 Multiple pin order values found for
the gsc_pin_order attribute. Could
not find the pin order value for the
specified gsc_pin_function.
If a common head pin (or driver) is being used for
multiple daisy chained networks and a pin order has
been specified via the gsc_pin_order attribute, then a
pin order must be specified for all networks. The order
of the networks and the order of the pin order values in
their respective attributes must be consistent. Ensure
that all pin orders have been specified and then rerun.
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GSC-325 The number of pin order values
must equal the number of pin
functions specified for the pin.
If a common head pin (or driver) is being used for
multiple daisy chained networks and a pin order has
been specified via the gsc_pin_order attribute, then a
pin order must be specified for all networks. The order
of the networks and the order of the pin order values in
their respective attributes must be consistent. Ensure
that all pin orders have been specified and then rerun.
GSC-326 Multiple pin orders can only be
specified on the head pin for a
daisy chained network.
If a common head pin (or driver) is being used for
multiple daisy chained networks and a pin order has
been specified via the gsc_pin_order attribute, then a
pin order must be specified for all networks. The order
of the networks and the order of the pin order values in
their respective attributes must be consistent. Ensure
that all pin orders have been specified and then rerun.
GSC-327 An inverter is required between the
driver and receiver pin, but a
connection already exists between
the driver and receiver pin that is
not inverted.
The most likely cause of this is reused modules. If
reused modules are present, ensure the polarities are
consistent for each instance.
GSC-328 An inverter is not required between
the driver and receiver pin, but an
inverter already exists between the
driver and receiver pin.
The most likely cause of this is reused modules. If
reused modules are present, ensure the polarities are
consistent for each instance.
GSC-329 Exactly one driver pin and one
receiver pin is allowed for a unique
network.
Specify one driver pin (output pin or input port) and one
receiver pin (input pin or output port). If two input pins
or two output pins are to be connected, use the
gsc_pin_class attribute to designate one pin as the
driver and the other as the receiver.
GSC-330 The receiver pin in the unique
network is already being driven.
The receiver pin in a unique network must not have
existing drivers.
GSC-331 A output pin was specified for a
constant connection. Only input
pins are allowed.
Specify an input pin to have a constant connection.
GSC-332 The pin specified to have a
constant connection is already
connected to a non constant value,
or the opposite constant value.
The pin can only have an existing connection to a
constant of the same value that is desired.
GSC-333 The receiver pin in the
daisy-chained network is already
being driven.
Receiver pins in a daisy-chained network must not have
existing drivers.
GSC-334 A mixture of gsc_pin_type values
were found for the
gsc_pin_function.
All pins for a gsc_pin_function have to be of the same
type. Only pins in a daisy-chained network may have 2
types of pins specified: terminal and chained.
GSC-335 An invalid value was given to the
gsc_pin_type attribute.
Valid values are: chained terminal open constant
shared unique.
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Error Messages
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GSC-336 The object specified already has
an existing value for the
gsc_pin_type attribute.
If a different value is required, first clear the value by
setting it to an empty string, and then specify the new
value.
GSC-337 An invalid character was found in
the gsc_pin_function string. The /
character is not allowed.
Specify a gsc_pin_function without / characters.
GSC-338 Could not create work directory. Verify permissions are correct, and that there is enough
disk space.
HDL-2 Argument to '-lib' must be an
identifier or assignment.
Specify the VHDL library name using the 'read_hdl -lib'
argument. For example,
'read_hdl -vhdl -lib lib1 test1.vhdl'
'read_hdl -vhdl -lib lib3=lib2=lib1 test2.vhdl'.
HDL-3 Conflicting options specified with
the 'read_hdl' command.
Use either the '-vhdl', '-v1995', '-v2001', or the '-sv'
option to read in HDL files. For more information on
Hardware Description Languages, see 'HDL Modeling
in Encounter RTL Compiler'.
HDL-5 Conflicting options specified with
the 'read_hdl -netlist' command.
The option '-v2001' can only be used with 'read_netlist'
command.
HDL-6 Bad option(s) specified with the
'update_hdl_input' command.
Use 'update_hdl_input -h' for valid options.
HF-100 No unique design found. Check if there is a design provided in the command
arguments. If not, there should be only one design
loaded in RC.
HF-101 Partition subdesign has multiple
instances.
Check if there exists multiple instances of subdesign
provided as partition. If so uniquify the partition module.
HF-111 Data directory not found. The ILM data directory could not be found. Check the
path again.
HF-112 Input file not found. The file could not be found. Check the path again and
check if the file exists.
HPT-41 Cannot open file. The specified file could not be opened. Check the path
of the file.
HPT-67 NULL file information passed to
routine.
Error during Parsing.
HPT-74 Ambiguous module reference. Error during Parsing.
HPT-81 Non-structural construct. Only structural HDL input is supported in this mode.
HPT-82 VHDL entity declaration not
specified for ChipWare
component.
A file containing the VHDL entity declaration must be
specified for a ChipWare component if any of the
component implementations are written in VHDL. The
path to the entity declaration file is specified via the
'location' attribute on the component vdir.
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Error Messages
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INCRSYN-4 Unable to create the write_cache
directory.
Check the permission to create the directory.
INCRSYN-5 Invalid cache directory specified. Make sure the directory contains the cache file(s) from
previous run(s).
INCRSYN-6 Cannot perform incremental
synthesis.
Make sure the cache file and DB exist in the
read_cache directory.
INCRSYN-7 Cache file is in wrong format. Make sure this cache file is not corrupted.
INCRSYN-9 Unable to write file to the
write_cache directory.
Check the writing permission of the directory.
INCRSYN-10 Unable to open file to dump cache
information.
Cache file will not be available for next run.
INCRSYN-13 Library does not match. Incremental synthesis does not reuse the netlist from
different library domain.
ISO-110 Wrong argument to
-enable_polarity.
-enable_polarity can take 'active_high' or 'active_low'.
ISO-111 Wrong argument to -output_value. -output_value can take 'high', 'low' or 'hold'.
ISO-112 Wrong argument to -location. -location can take 'from' or 'to'.
ISO-113 Wrong argument to -off_domain. -off_domain can take 'from' or 'to'.
ISO-115 Enable pin/port specified is
hanging and not a driver pin/port.
An enable pin/port must either be a driver, or have a
driver. To use the driver of enable given as the enable
driver for isolation rule, set the variable
'lp_select_enable_driver' to 1.
ISO-217 Cannot insert isolation cell. DFT test mode signal can have one unique value out of
'active_high' or 'active_low'.
LBR-2 Conflicting delay models detected. The delay model should be the same one used in the
library.
LBR-4 Loading libraries. Unrecognized phase/retention_disable_value for state
retention power gating pin/retention pin. The cell cannot
be used for SRPG synthesis.
LBR-5 Duplicated library name. Check the library name in the library file.
LBR-7 Loading libraries. Multiple power_gating_pin/retention_pin specifications
in the library cell. Specify only one power_gating_pin/
retention_pin construct for a pin in the library cell.
LBR-17 A test_cell group is missing the ff
group.
Check the 'Scan Cell Requirements' section in the
Library Guide for Encounter RTL Compiler for more
information.
LBR-24 Multiple unit definitions detected. A library can only have one definition for
capacitive_load_units. Delete the incorrect value. You
might need to regroup the contents of the library (into
multiple files) based on their appropriate units.
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Error Messages
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LBR-28 Loading libraries. Syntax error in the current library.
LBR-29 Failed to reset a libcell's avoid
attribute.
An attempt was made to unavoid a library cell that did
not succeed. This is usually due to another attribute on
the lib-cell that is causing it to remain avoided (e.g. the
lib-cell is preserved (dont-used) or its function/timing
may be too complex).
LBR-32 Invalid operating_conditions name. Use ls to see the valid operating_conditions in the
libraries.
LBR-33 Non-unique operating_conditions
name.
Use a more unique name to ensure that a single
operating_conditions object is specified.
LBR-35 Invalid library arc name. Use ls to see the valid arcs for the library pin.
LBR-45 Dis-parity in pin direction within a
bus in library definition.
A libcell is ignored if 'direction' attribute is missing or
wrong for one of its pins.
LBR-50 Inconsistent number of rows in
lookup-table.
Examine the lookup-table and its associated
lu_template to make sure that the dimensions and size
match.
LBR-51 Inconsistent lookup-table row
cardinality.
Correct the .lib source for the specified lookup-table.
All rows in a table must have the same size.
LBR-52 Inconsistent lookup-table row size. Examine the lookup-table and its associated
lu_template to make sure that sizes match.
LBR-53 Library has bad unit. Current library has bad unit.
LBR-56 Computed internal power unit is 0. Current library has either bad time unit or capacitance
unit or voltage unit. Bad library.
LBR-59 Pin was declared as a bus, but it is
missing a 'bus_type' qualifier.
Ensure that all busses have a corresponding 'bus_type'
in the loaded library.
LBR-60 Pin was declared as a bus with an
undefined 'bus_type'.
Libcell will be ignored. Ensure that all bus_types that
are declared are defined in the appropriate library cell
of the loaded library.
LBR-62 Pin has unsupported pin direction. A libcell is ignored if 'direction' attribute is missing or
wrong for one of its pins.Refer to the Liberty Guide for
more information on how to resolve this error.
LBR-68 A library file does not exist. Make sure that the library file exists or check for a typo
in the file name.
LBR-69 A library file does not have the
correct format.
Check whether the file is corrupted or if it follows the .lib
format.
LBR-78 Unable to parse
lu_table_template.
Correct the lu_table_template to standard acceptable
format to proceed.
LBR-80 Invalid syntax. Ensure the syntax specified in the attribute conforms to
Liberty standards.
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LBR-82 Internal node not found. Ensure that the 'internal_node' name corresponds to a
node identifier specified on a 'statetable' in the loaded
library.
LBR-94 Multiple leakage power groups are
missing 'when' attribute.
To take the 'leakage_power' group into account during
power estimation, fix the library first and restart your
synthesis session. For more information, refer to the
Liberty Reference Manual.
LBR-95 Order in which attributes were
specified was incorrect.
The attribute needs to be set before reading the library.
LBR-107 Library domain creation error. Failed to create library domain.Cannot create library
domains if libraries have already been loaded by setting
the 'library' attribute on root.
LBR-108 Library domain creation error. Failed to create library domain because domain with
same name exists.
LBR-112 Cannot set is_default attribute to
false.
Set the is_default attribute on another library domain to
true to change the default library domain.
LBR-113 Cannot set is_default attribute to a
library domain without loading
libraries first.
Load the libraries first by setting 'library' attribute on this
library domain.
LBR-115 Cannot process libraries loaded
into the domain.
Ensure the loaded libraries contain only valid and
supported syntax and your operating conditions are
supported by the loaded libraries.
LBR-116 Failed to execute command. Set the root 'library' attribute to a (list of) library
name(s).
LBR-125 Option '-flexible' not supported for
renaming library domains.
Rename the object with the desired name so that the
target name is available.
LBR-130 Parsing error. Invalid liberty syntax is parsed, or unsupported liberty
syntax is encountered.
LBR-131 Processing error. Problem processing timing group.
LBR-132 Processing error. Problem processing internal_power group.
LBR-133 There was a bundle error in the
loaded library.
Refer to the Liberty Guide for more information on how
to resolve bundle errors.
LBR-138 Duplicated definition for a variable. Ensure the loaded library does not contain any cells
with multiple declarations of the same variable.
LBR-144 The loaded library contained
syntax or constructs that did not
conform to Liberty standards.
Refer to the Liberty Guide for more information on how
to resolve this error.
LBR-145 The delay_model specification
either did not conform to the
Liberty standards or was
ill-formed.
Ensure that all models in the loaded library conform to
the Liberty standards.
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LBR-154 Invalid operator. Use valid boolean operators.
LBR-171 Cannot perform synthesis
because libraries do not have
usable inverters.
Inverters are required for mapping. Ensure that the
loaded libraries contain at least one usable inverter.
LBR-172 Cannot perform synthesis
because libraries do not have
usable basic gates.
At least one usable two-input and/or/nand/nor gate
(modulo inversion at inputs) is required for mapping.
Ensure that the loaded libraries contain at least one
such cell.
LBR-214 Incorrect level shifter location
specified.
The valid values are { from | to }.
LBR-354 Incorrect Argument passed. Check if technology libraries are specified correctly.
LBR-406 Improperly defined
'leakage_power' group.
To take the 'leakage_power' group into account during
power estimation, fix the library first and restart. For
more information, refer to the Liberty Reference
Manual.
LBR-407 Improperly defined
'internal_power' group.
To take the 'internal_power' group into account during
power estimation, fix the library first and restart. For
more information, refer to the Liberty Reference
Manual.
LBR-411 Found incorrect pin specification. If the pin name is specified within double quotes, extra
blanks and parentheses are not allowed inside the
double quotes.
LBR-419 Found group statement outside of
its group.
A group statement defined outside of its group will be
ignored by the tool.
LEX-1 Syntax error. Invalid syntax is parsed, or unsupported syntax is
encountered.
MAP-1 Unable to map design without a
tristate buffer or inverter.
Check the libraries for necessary tristate cell. The cell
could be marked unusable.
MAP-2 Unable to map design without a
suitable flip-flop.
Check the libraries for necessary flop cell. The cell
could be marked unusable.
MAP-3 Unable to map design without a
suitable latch.
Check the libraries for necessary latch cell. The cell
could be marked unusable.
MAP-12 Cannot create multibit cell. A multibit flop can be created only for those 1-bit flop
library cells that belong to the same subdesign and are
not marked preserved.
MAP-14 Attribute
boundary_optimize_hier_pin_inver
tible only defined for hierarchical
boundary pins.
Access this attribute only for hierarchical boundary
pins.
MAP-28 A generated PLE model is
required for physical aware
mapping.
Use generate_ple_model command in a separate
session to generate a PLE model and source it in a new
session before running physical aware mapping.
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MAP-132 The create_timing_budgets
command failed.
The timing budget is not created if appropriate license
is not present.
MBIST-100 Could not open input file. The specified file could not be found when the
application attempted to open it for input. Ensure the
path and file name are correct.
MBIST-102 Compressed files are not
supported in RTL flow.
Make sure that the compressed files are not specified
in RTL flow. Correct the issue and re-run.
MBIST-112 Configuration file error. Correct the problem identified by the line and column.
MBIST-113 Configuration file error. Correct the problem identified by the line and columns.
MBIST-114 Memory allocation errors. Configuration file parsing detected memory allocation
errors. Check the system for the load and available
memory.
MBIST-115 Configuration file contains no valid
target group.
Ensure that at least one valid target group exists.
MBIST-116 Memory module ignored. Configuration file module group specification
re-specifies memory module. It is ignored. Verify all the
memory related information is provided in a single
module group.
MBIST-117 Memory module group ignored. Configuration file module group specification contains
only re-specified memory modules. It is ignored. Verify
all the memory related information is provided in a
single module group.
MBIST-118 Configuration file module address
partition specification error.
Address partition specification contains a non-zero
least significant column address bit. Ensure column
keyword contains at least one zero-valued address
index.
MBIST-119 Configuration file module address
partition specification error.
Address partition specification contains an order
keyword with too many address values. Ensure the
number of values in the address partition are less than
or equal to the column address.
MBIST-120 Configuration file module address
partition specification error.
Address partition specification contains an order
keyword with non-power of two address values. Ensure
the order size is a power of two.
MBIST-121 Configuration file module address
partition specification error.
Address partition specification contains an order
keyword with invalid or missing address values.
MBIST-122 Configuration file module address
partition specification error.
Address partition specification contains an invalid least
significant row address bit. Ensure the least significant
row address bit is one greater than the column's most
significant bit.
MBIST-123 Configuration file module address
partition specification error.
Address partition specification contains an invalid least
significant bank address bit. Verify the bank least
significant address bit is one greater than the row's
most significant bit.
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MBIST-124 Position based binding used
during instance connections but
order information does not exist for
ports.
Order information does not exist for the specified
module. Use name based binding during instantiation
for the instances of this modules and re-run.
MBIST-125 MBIST direct access function
exists.
Specified MBIST direct access function already exists.
To update this function, you must first remove this direct
access function and then redefine it.
MBIST-126 Missing direct access specific pin
on the block.
Specified MBIST direct access function is missing on
the specified block. Block must have the superset of the
direct access functions required at the current level.
MBIST-127 Conflicting clock requirements for
the direct access specific function
on the block.
Specified MBIST direct access function clock of the
specified block differs than that of the current MBIST
direct access function clock. Clock requirements for the
direct access functions on the blocks being merged
must be same as that of direct access functions
required at the current level.
MBIST-128 Consistency check failed. Correct the above mentioned issue and re-run.
MBIST-129 Configuration file contains
group(s) other than module
definition.
Ensure that only module definition exists with '-preview'
option.
MBIST-713 Dynamic memory allocation failed. Ensure sufficient memory is available on the system
and re-run.
MBIST-730 Cannot read required
configuration file.
Check the appropriate read permissions.
MBIST-731 No configuration file provided. Provide a valid configuration file.
MBIST-737 Cannot create a temporary file for
internal processing.
Check the available disk space and the proper
permissions for the directory structure.
MBIST-738 Cannot create directory. Check the available disk space and the proper
permissions for the directory structure.
MBIST-739 Cannot determine the current
working directory.
Ensure proper environment settings.
MBIST-749 Errors found in the configuration
file.
Correct the configuration file and re-run.
MBIST-750 Duplicate definition found. Correct the problem identified by the line and columns.
MBIST-790 No clock specified for the target
group.
Correct the configuration file and specify the mandatory
keyword 'clock'.
MBIST-791 Missing JTAG instruction from vdir
structure.
Define the JTAG instruction using 'define_dft
jtag_instruction' command and re-run.
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MBIST-792 Common clock source at the chip
level for blocks having different
clock frequencies at the block
level.
The interface files being merged have different clock
frequencies at the block level. But the source clock at
the chip level is same. Make sure that correct set of
interface files have been specified. Correct this problem
and re-run.
MBIST-793 Missing MBIST specific ports on
the block.
Cannot merge the specified block because this does
not have MBIST specific ports. Either the provided
interface files are not proper or the 'insert_dft mbist'
command was not run without both the options
'-connect_to_jtag' and '-dont_create_mbist_ports' on
this block.
MBIST-794 Could not check the block for
validity.
Missing MBIST specific ports on the block.
MBIST-795 MBIST clock has no hookup pin. Option '-internal_clock_source' requires a hookup pin.
Either provide a hookup pin or remove option
'-internal_clock_source' and re-run.
MBIST-796 Conflicting options given to the
command.
Conflicting options are given to the command. Only one
option can be specified from the options listed above.
Make sure that the correct options are given and re-run.
MBIST-797 MBIST clock has no associated
name.
In case of internal clock, MBIST clock must have an
associated name. Either provide a name or remove
option '-internal_clock_source' and re-run.
MBIST-954 Cannot determine the output
enable pin structure.
Contact Cadence Customer Support for assistance.
MBIST-955 Netlist does not match the
provided interface files.
Provide correct interface files and re-run.
MBIST-956 Bus indices do not match with bus
size.
MBIST is not inserted for this cell. Verify that the
correct indices are specified in the liberty file and
re-run.
MBIST-998 An unexpected condition occurred
in the program.
Contact customer support to report this error and give
them the information.
MBIST-3001 Could not determine test mode
signal.
Zero or more than one test mode signals present, use
the '-test_control' option to specify the test mode signal.
MBIST-3002 Could not determine shift enable
signal.
Zero or more than one shift enable signals present, use
the '-shift_enable' option to specify the shift enable
signal.
MBIST-3003 Could not check out a
Encounter_Test_Architect license.
Make sure a valid license is available.
MBIST-3004 Could not free a
Encounter_Test_Architect license.
Make sure a valid license is available.
MBIST-3005 Cannot create directory for storing
generated output.
Check to ensure the file permissions allow creation of
directories and that there is available disk space. Fix
the environment and rerun.
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MBIST-3006 Cannot copy file. Check the source file to ensure it exists; check the file
permissions and the available disk space to ensure you
have the ability to create the copy, and then rerun.
MBIST-3007 Cannot create the diagnostics Test
Data Register map file.
Fix the file permissions and/or the available disk space
and rerun.
MBIST-3008 Cell contains an unsupported
combination of port types.
Check the reference document for the supported
memory cell configurations.
MBIST-3009 Cannot insert memory BIST for
memory cell.
Too many ports on memory cell. Correct the memory
cell and rerun.
MBIST-3010 Cannot create the pattern control
file.
Fix the file permissions and/or the available disk space
and rerun.
MBIST-3011 Cannot find the test enable signal. Make sure that a valid test enable signal exists. Correct
the test enable specification and re-run.
MBIST-3012 Instance not found in current
directory.
Could not determine the full name for the user specified
name in the design. Ensure the user specified name is
correct and re-run.
MBIST-3013 Cant close the program's
temporary internal file.
Ensure file permissions and available disk quota.
MBIST-3014 Enable port contains hierarchy. Port must be at the user core level. Ensure port location
is on the user core and rerun.
MBIST-3015 Different reference clock frequency
in target groups.
Target groups with the same reference clock (refclk) pin
cannot have different refclk frequencies. Verify all
target groups containing the same refclk pin have
specified the same frequency, and rerun.
MBIST-3016 Unable to determine function
information for I/O cell.
This could indicate some information is missing from
the liberty file.
MBIST-3017 Cannot connect instances of cells
using same BIST engine.
The memory instances have different memory classes,
and cannot be connected using the same BIST engine.
Ensure the target group contains memories of the
same device class, either combinations of read and
write ports or the same number of read-write ports.
MBIST-3018 Cannot insert a BIST engine for
memory instance.
BIST engine location should be either in the same or in
the parent hierarchical block of the referenced memory
instance location.
MBIST-3019 Cannot create a temporary file for
internal processing.
Check the available disk space and the proper
permissions for the directory structure.
MBIST-3020 Cannot determine the number of
ports on memory cell.
Ensure each port contains a unique pair of address bus
and clock pin and rerun.
MBIST-3021 Conflicting input pipeline stage
requirements.
Module containing memory instance of memory cell is
used multiple times and has conflicting input pipeline
requirements. Uniquely instantiate the netlist or specify
consistent input pipeline requirements.
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MBIST-3022 Multiple instances have conflicting
diagnostics requirements.
Ensure multiply used memory cells have same
diagnostics BIST requirements.
MBIST-3023 Multiple instances have conflicting
BIST requirements.
Ensure either all multiply used memory cells require
BIST or none of them requires BIST.
MBIST-3024 Multiple instances have conflicting
bypass requirements.
Ensure multiply used memory cells have consistent
memory bypass requirements.
MBIST-3025 Multiple instances have conflicting
bypass xoring requirements.
Ensure multiply used memory cells have consistent
memory bypass xor requirements.
MBIST-3026 Conflicting output pipeline stage
requirements.
Module containing memory instance of memory cell is
used multiple times and has conflicting output pipeline
requirements. Uniquely instantiate the netlist or specify
consistent output pipeline requirements.
MBIST-3027 Specified BIST engine location is
not found in the netlist.
Specify a valid BIST engine location and rerun.
MBIST-3028 Cannot find user core in the given
netlist.
Verify the user core name is correct and rerun.
MBIST-3029 Cannot BIST memory cell. The number of ports on memory cell is not among the
supported ports. Refer to Supported Memory
Structures in the Memory Built-In Self Test Reference.
MBIST-3030 Conflicting requirements for
memory instances.
Module containing memory instance of memory cell is
used multiple times and has conflicting BIST
requirements. Uniquely instantiate the netlist or specify
consistent BIST requirements.
MBIST-3031 Cannot add BIST to instances of
memory cell.
The cell does not have a write enable or a chip select
pin associated with clock pin. Verify the write port has
either write enable or chip select and rerun.
MBIST-3033 BIST engine is in a multiply used
module.
Ensure each BIST engine instance location contains
the same number of memories or uniquify the netlist
and rerun.
MBIST-3035 Cannot find the specified clock pin. Could not find the pin on the targeted memory cells.
Verify the clock pin exists on at least one of the memory
cells targeted by the target group and rerun.
MBIST-3036 Specified clock net is not found in
the user core.
Ensure the location and the existence of the net.
MBIST-3037 Specified clock source net is not
found.
Clock net not found in the same block as the associated
BIST engine nor in a parent hierarchical block. Verify
the source clock net is in a same block as the BIST
engine or in its parent hierarchical block and rerun.
MBIST-3038 No functional clock net is
connected to memory instance.
Ensure the functional net is connected to the memory
cell in the module and rerun.
MBIST-3040 All required JTAG pins not found
on JTAG macro.
Verify the names of the pins are correct on the JTAG
macro and in the speclist (if used for any preceding
commands run).
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MBIST-3041 Specified test enable is not in the
correct location.
The test enable is not in the same block as the
associated BIST engine nor in a parent hierarchical
block. Verify the test enable is in a same block as the
BIST engine or in its parent hierarchical block and
rerun.
MBIST-3042 An unexpected condition occurred
in the program.
Re-run the command with '-debug' option. Report this
error to customer support and provide the logfile
generated with '-debug' option.
MBIST-3043 Specified instance name is not a
design.
Ensure that the user specified instance name is correct
and re-run.
MBIST-3044 Missing jtag_instruction
information.
Could not locate any jtag_instruction under directory: /
designs/<design>/dft/boundary_scan/jtag_instructions.
Ensure that 'define_dft jtag_instruction' has been
executed and re-run.
MBIST-3045 Specified signal is not a valid test
mode signal.
Make sure that the specified signal name is correct and
it is not defined as shift_enable signal.
MBIST-3046 Specified signal is not a valid shift
enable signal.
Make sure that the specified signal name is correct.
MBIST-3047 Existing instruction values do not
match required values.
One or more of the existing instruction values do not
match the values required by MBIST insertion. Ensure
the existing values are correct.
MBIST-3048 Configuration file does not exist. Configuration file does not exist. Make sure that the file
name is correct and it exists.
MBIST-3049 Exactly 1 top level design is
required for insert_dft mbist.
-design option is not specified and the current hierarchy
is also not a design hierarchy. In this case, top level
design will be used for MBIST insertion. Found more
than 1 top level design, make sure there is only one top
level design.
MBIST-3050 Could not find 'JTAG_MODULE'. Either the 'JTAG_MODULE' does not exist, or the
'JTAG_MODULE' does exist but cannot be found. You
can use the 'find' command to search for the
'JTAG_MODULE' instance in the design.
MBIST-3051 Could not find the required jtag
instruction.
Required jtag instruction is not present in the vdir
structure. Make sure that the instruction has been
specified using 'define_dft jtag_instruction' and re-run.
MBIST-3052 Conflicting options given to the
command.
Conflicting options are given to the command. Only one
option can be specified from the options listed above.
Make sure that the correct options are given and re-run.
MBIST-3053 Associated register with
'continue_mbist' command is
invalid.
The register name associated with 'continue_mbist'
command must be 'BYPASS'.
MBIST-3054 More than one entry exists for the
specified instance name.
Specify the full hierarchical path of the instance/design
and re-run.
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Error Messages
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MBIST-3055 No target memory instance to
BIST.
Check the configuration file for target groups and ignore
groups. Ignore groups have priority over the target
groups. Also check for any previous messages
regarding not fully specified memory cell.
MBIST-3057 Cannot insert a BIST engine for
memory instance.
Test enable location should be either in the same or in
the parent hierarchical block of the referenced memory
instance location.
MBIST-3058 All the options '-config_file',
'-preview' and '-interface_file_dirs'
are missing.
At least one of the options must be present.
MBIST-3059 Blocks with different instruction
sets specified with option
'-interface_file_dirs' for merging at
block level.
Blocks with different instruction sets can only be
merged at the chip level. This means that either the
JTAG macro must exist and '-connect_to_jtag' option is
specified or '-dont_create_mbist_ports' option is
specified and JTAG macro will be inserted after the
current run of MBIST.
MBIST-3060 Interface files are missing for some
or all of the BIST engines present
in the netlist.
Specify the interface files for the missing block(s) which
contain the specified BIST engines and re-run.
MBIST-3061 Redundancy analysis is not
supported for the specified
memory device.
Redundancy analysis is not supported for the memory
devices having more than one read and one write port.
MBIST-3062 Unable to apply attribute on the
specified instance.
MBIST has already been executed on some parent
block containing the specified instance. The above
mentioned attribute can only be specified on those
instances which are not yet merged. Remove this
attribute from this instance and re-run.
MBIST-3063 Could not find any interface file. Interface files are not found in the specified locations.
Make sure that the location of interface files is correct
and re-run.
MBIST-3064 Redundant jtag instruction
specified at command line.
Specified jtag instruction is not required. This may lead
to failure of boundary scan verification. Make sure that
the specified instruction is required and re-run.
MBIST-3065 Redundancy analysis is not
supported in this flow.
Redundancy analysis is not supported in the bottom-up
flow that is MBIST insertion is done on a block and then
later merged using the interface files. Redundancy
analysis is supported only if either 'connect_to_jtag' or
'dont_create_mbist_ports' option is given and interface
files are not provided.
MBIST-3066 Interface file does not exist. Verify that the provided interface file directory is correct
and re-run.
MBIST-3067 Instruction missing with attribute
'mbist_instruction_set'.
Specify the missing instruction while setting the
attribute and re-run.
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MBIST-3068 Spurious instruction provided with
attribute 'mbist_instruction_set'.
Remove the specified instruction while setting the
attribute and re-run.
MBIST-3069 A required option is missing. Specify the required option and re-run.
MBIST-3070 Attributes required with TAP
instruction are missing.
Specify the required attributes with TAP instruction and
re-run.
MBIST-3071 Clock mentioned in the
configuration file is not defined as
'mbist_clock'.
Specify the proper 'mbist_clock' in the configuration file
and re-run.
MBIST-3072 No functional clock net is
associated with the 'hookup_pin'.
Ensure that the functional net is connected to the
'hookup_pin' of the 'mbist_clock' and rerun.
MBIST-3073 Zero or more than one driver exists
for the net.
Ensure that the specified net is properly driven and
rerun.
MBIST-3074 Enable of the PAD associated with
measure port is in-active.
PAD cell enable is tied to a constant value and the
value is opposite of its active value. Correct the problem
mentioned above and re-run.
MBIST-3075 RTL flow is not supported with
VHDL files.
Input design has RTL in VHDL. RTL flow is supported
only with Verilog files. Set attribute 'dft_rtl_insertion' to
'false' and re-run.
MBIST-3076 RTL flow is not supported with
multiple measure ports.
Measure ports are specified at the command line. RTL
flow is not supported with multiple measure ports.
Either remove the measure ports or set attribute
'dft_rtl_insertion' to 'false' and re-run.
MBIST-3077 Different work directories are
required for different DFT insertion
commands in RTL flow.
Make sure that the directories are different and re-run.
MBIST-3078 Verilog files are already present in
the work directory.
Make sure that the directory does not contain any
Verilog files and re-run.
MBIST-3079 Functions 'poweron_run' and
'burnin_run' are missing but
'monitor' is shared.
Make sure that either 'poweron_run' and/or 'burnin_run'
is specified or 'monitor' is not shared and re-run.
MBIST-3080 Multiple drivers exist for the
hookup pin of 'monitor' function.
Make sure that 'monitor' is not multiply driven and
re-run.
MBIST-3081 Multiple instances have conflicting
BIST requirements.
Ensure either all multiply used memory cells require
multiplexer for clock or none of them requires
multiplexer and re-run.
MBIST-3082 Memory instances associated with
a BIST engine have different
clocks.
Make sure that either 'no_clock_mux' is not specified in
the configuration file for the specified memories or all
clock pins of the specified memories are driven from
the same clock source and re-run.
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Error Messages
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MBIST-3083 Source of the clock pin of the
memory is different than that of the
'mbist_clock' specified for this
memory.
Make sure that either 'no_clock_mux' is not specified in
the configuration file for the specified memory or all
clock pins of the specified memory are driven from the
source of its 'mbist_clock'. Correct the issue mentioned
above and re-run.
MBIST-3084 Conflicting '-direct_access_only'
option requirements.
Option '-direct_access_only' requested but cannot be
satisfied. Make sure that all the target groups in the
configuration file have 'redundancy_analysis',
'diagnostics', 'record', 'bitmap' set to 'no'. If any of these
requirements must be 'yes', then proceed with MBIST
insertion using a JTAG macro.
MBIST-3085 Direct access requested but port
not associated with direct access
function.
Direct access functions must specify ports during block
level flow. Make sure that either the flow is not block
level or ports must exist and re-run.
MBIST-3086 Required pin on the block does not
exist.
Specified pin must exist on the block. Make sure that
either the block is not created from previous version of
the tool or pin is not modified manually and re-run.
MBIST-3087 Conflicting '-direct_access_only'
option requirements.
Option '-direct_access_only' requested but cannot be
satisfied. Make sure that 'burnin_run' and/or
'poweron_run' functions have been defined using
'define_dft mbist_direct_access'.
MBIST-3088 Conflicting requirements for direct
access function.
Keyword 'mtclk' is missing from the target group but the
specified direct access function is clocked by 'mtclk'.
Make sure that either the 'mtclk' keyword is present in
all the target groups or the direct access function is not
clocked by 'mtclk' and rerun.
MBIST-3089 All required JTAG ports not found
on the design.
Verify that all the required JTAG ports are present on
the design and re-run.
MBIST-3090 Memory instance specified
multiple times.
The configuration file contains multiple specifications of
the memory instance. Ensure only one BIST
requirement is specified per memory instance and
re-run.
MBIST-3091 Frequency of the clock at the
hook-up pin does not match with
the frequency of the clock pin of
the block.
The source clock at the chip level has different
frequency at the hook-up pin than that of the clock pin
of the block. Make sure that the clock connections are
correct and re-run.
MBIST-3092 Conflicting 'logic_test bypass'
option requirements.
Option 'logic_test bypass' requested but cannot be
satisfied. Make sure that either 'logic_test bypass' is not
specified or the test specific data read port is
unconnected.
MBIST-3093 Invalid port specified. Correct the above mentioned issue and re-run.
MBIST-3094 Could not find any register
associated with the jtag
instruction.
Register associated with the specified jtag instruction is
not present in the vdir structure. Make sure that the
register has been specified with the command
'define_dft jtag_instruction' and re-run.
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Error Messages
May 2013 213 Product Version 12.2
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MBIST-3095 Missing source port/pin for
'monitor'.
The source can be absent only if it is a pin on the JTAG
macro which will be inserted after MBIST. Correct the
above mentioned issue and re-run.
MBIST-3096 More than one control signal found
on the memory.
Make sure that the above mentioned control signals are
properly specified in the 'port_action' or 'port_alias'
section of the configuration file and re-run.
MBIST-3097 Functions 'poweron_run' and
'burnin_run' are missing but PAD
enable associated with the
'monitor' needs to be controlled.
Make sure that either 'poweron_run' and/or 'burnin_run'
is specified or 'monitor' is not a port and re-run.
MBIST-3098 MBIST instruction is specified as
'private'.
MBIST instruction should not be specified as 'private'
otherwise downstream tools may fail. Make sure that
the MBIST instructions are not specified as 'private' and
re-run.
MBIST-3099 Unable to determine the required
pin of memory.
Look for the pin mapping/usage table of this memory in
the logfile to determine the usage of different type of
pins. Make sure that the pins are properly specified in
the 'port_action' or 'port_alias' section of the
configuration file and re-run.
MBIST-3100 More than one memory cell found
with the name specified in the
target/ignore group.
Ensure that the name specified in the target/ignore
group is correct and re-run.
MBIST-3101 Unable to find any memory cell
with the name specified in the
'module' group.
Ensure that the name specified in the module group is
correct and re-run.
MBIST-3102 Memory cell/instance, specified in
the target/ignore group, is not
present.
Either the name specified in the target/ignore group is
not correct, or all the liberty files are not provided.
Correct the problem mentioned above and re-run.
MBIST-3103 No instance of the memory cell,
specified in the target/ignore
group, is present in the design.
Either remove this entry from the target/ignore group or
make sure that the name specified in the target/ignore
group is correct and re-run.
MBIST-3104 Memory module/instance,
specified in the 'module' or 'target'
or 'ignore' group, is not a
recognizable memory cell.
Either the 'memory' section is missing from the cell
description in the liberty (.lib) file or the instance
hierarchy is not completely specified. Ensure that the
correct liberty file is provided and check for syntax
errors pertaining to the liberty file in the log. Also verify
that the instance hierarchy is completely specified in
the configuration file, and rerun.
MBIST-3105 Pin specified in the 'port_action' or
'port_alias' section of the
configuration file is not present on
the memory cell.
Either remove this entry from the 'port_action'/
'port_alias' section or make sure that the name
specified in the 'port_action'/'port_alias' section is
correct and re-run.
MBIST-3106 Invalid value specified. Correct the problem mentioned above and re-run.
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Error Messages
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MBIST-3107 Cannot connect instances of cells
using same BIST engine.
The memory instances have different library domains,
and cannot be connected using the same BIST engine.
Ensure that either the target group contains memories
of the shared library domain set or correct the value of
the attribute 'mbist_enable_shared_library_domain_set'
and re-run.
MBIST-3108 Clock source is not defined as
'mbist_clock'.
The specified clock pin must be driven from an
'mbist_clock' otherwise the downstream processing
may fail. Check the 'mbist_clock' definition or make sure
that the clock connections are correct.
MBIST-3109 Unable to locate 'mbist_clock'. Make sure that the 'mbist_clock' is defined properly and
re-run.
MBIST-3110 Hookup pin of the 'mbist_clock' is
not controllable from its source
port.
Hookup pin of the 'mbist_clock' must be controllable
from its source port. In case it is not controllable then
boundary scan verification or simulation may fail. To
debug this further, first run 'set_dft_configuration_mode
-dft_configuration_mode <mbist mode>' and then run
'dft_trace_back -through -mode 1 -print -continue'
command with the above mentioned hookup pin name.
Make sure that either this pin is controllable in 'mbist'
configuration mode or 'dft_controllable' attribute is
properly set so that it becomes controllable and re-run.
MBIST-3111 Unable to determine any design/
subdesign from the interface files.
Verify that the provided interface file directory is correct
and re-run.
MBIST-3112 Unable to find any design or
instance of the sub-design
mentioned in the interface files.
Verify that the provided interface file directory is correct
and re-run.
MBIST-3113 Incorrect 'pipeline_stages'
expression encountered in the
configuration file.
In case 'pipeline_stages' expression is used, then the
memories specified in this expression must match the
entries specified in its target specification. Correct this
expression and re-run.
MBIST-3114 Multiple instances have conflicting
BIST requirements.
Ensure that all the instances of a memory cell, that are
specified for BIST, have same diagnostic requirements
and re-run.
MBIST-3115 Invalid weights specified. Ensure that all the weights sum up to '1' and re-run.
MBIST-3116 Clock source is not defined as
'mbist_clock'.
Option '-optimize_mbist_grouping' is specified but clock
source of the specified memories is not defined as
'mbist_clock'. In order to estimate pipeline stages, clock
source of memories must be defined as 'mbist_clock'.
Ensure that the 'mbist_clock' is defined properly and
re-run.
MESG-1 Invalid group. Use a group other than internal groups.
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Error Messages
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MESG-3 You specified more than on
severity flag for the messages.
Specify one of: ERROR,
WARNING, or INFO.
Specified more than one severity (flag).
MESG-4 Invalid priority specified. Invalid priority specified.
MESG-5 Invalid severity. Valid severity flags
are ERROR, WARNING, or INFO.
Invalid severity specified.
MESG-8 Cannot overwrite internal
message with a user message.
Cannot overwrite internal message with a user
message.
MESG-9 Internal group does not exist. Specify an existing internal group when using the
'-internal_group' option.
MM_FE-61 Not all the instances are mapped. Cannot write data unless all instances are mapped.
MM_FE-62 Cannot export any files for
Encounter.
Multiple designs have been found.
MM_FE-63 Cannot export any files for
Encounter.
No design has been loaded.
MM_FE-65 Failed to create fe_path. Make
sure you have the write permission
to the parent path.
Specify a writable directory for the '-output_directory'
option.
MM_FE-67 RC does not have write
permission to file.
Check file permissions and rerun the command.
MM_FE-68 RC does not have read permission
to file.
Check file permissions and rerun the command.
MM_FE-69 Failed to generate FE file since
output FE path does not exist.
Specify a writable directory for the '-output_directory'
option.
MSV_FE-80 Failed to create fe_path. Make
sure you have the write permission
to the parent path.
The directory specified with '-output_directory' option is
not writable.
MSV_FE-81 No design top has been specified. If multiple designs exist, specify one using the '-design'
option.
MSV_FE-82 Failed to generate FE file since
output FE path does not exist.
Specify a writable output directory with the
'-output_directory' option.
MSV_FE-83 No FE output path directory has
been specified.
An output directory could no be created. Specify one
using the '-output_directory' option.
MSV_FE-84 File name is not one. Specify only one file name.
MSV_FE-85 No libraries have been loaded. A design library must be available. Specify a library
using the 'library' attribute.
MSV_FE-86 No path name has been found. Specify a writable output directory with the
'-output_directory' option.
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Error Messages
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MSV_FE-87 RC does not have write
permission to file.
Make sure directory and file permissions allow writing.
MSV_FE-88 RC does not have read permission
to file.
Make sure directory and file permissions allow reading.
MSV_FE-89 It is not a MSV design. This command can only be used with Multiple Supply
Voltage designs.
MSV_FE-92 There is no library domain
information associate with the
hierarchical instance.
Library domains must be specified for all hierarchical
instances.
MSV_FE-94 Cannot export any files for
Encounter.
No design has been loaded.
MSV_FE-95 Cannot export any files for
Encounter.
Multiple designs have been found.
MSV_FE-96 Not all the instances are mapped. This command only operates on fully mapped designs.
MSV_FE-97 Found illegal level shifters. No legal domain for level shifter.
MSV_FE-98 Command 'write_fe_msv' is not
supported in multi-mode
environment.
This command only operates for non multi-mode
designs.
MTDCL-13 Design is in generic state. No
replacement is possible.
Map the design first using synthesize command and
then run this command.
MTDCL-16 Unknown Error. Internal error. Report to Cadence.
MTDCL-24 No compatible one-to-one
replacement found for instance on
clock-path.
If a library set has missing match for any instance on
clock-path, we can try to remap the cells. Set the
attribute predefined_vt_map_effort to high to allow
remapping.
MTDCL-27 Error occurred when trying to
remap the clock-path instances.
First fix the problem reported above to run this
command. Or check if clock_library_cells are not
avoided and match library-domain of instances on
clock-path.
MTDCL-28 Unable to find a unique design to
run the command.
Provide the design-name in argument list or run the
command from design directory.
OVF-101 Failed to set the
ovf_verification_directory attribute.
An acceptable value must have zero or one '%s' plus
zero or one '%d', in any order.
OVF-102 Failed to set the
ovf_datapath_info_file attribute.
An acceptable value must not include any '%s' or '%d'.
OVF-201 Failed to open or create directory. Make sure you have write permission for the specified
directory.
OVF-202 Failed to open a file for writing. Make sure you have write permission for the specified
file.
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Error Messages
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PA-9 Could not perform a meaningful
RTL power analysis.
Make sure that you have a library that contains the
above specified cell or cells to create power models for
unmapped gates in the netlist. A library cell is
considered not usable if it has a 'dont_use' or a
'dont_touch' attribute set to 'true' in the .lib files. In this
case, use 'set_attribute preserve false <libcell>' and
'set_attribute avoid false <libcell>' to make the cell
usable.
PA-12 Cannot disable instance. Only leaf instances which are instances of clock gating
integrated cells can be disabled.
PHYS-50 Floorplan not found. A floorplan is required for this command or operation.
Load the floorplan using 'read_def'.
PHYS-51 Design utilization is not feasible. The size of the design is impossibly small or is greater
than what can fit into the specified floorplan. Increase
the floorplan size to accommodate the design.
PHYS-54 Design not placed. A placed design is required for this command or
operation. Place the design using 'predict_qos' or load
the placement using 'read_def'.
PHYS-55 Timing and physical libraries are
not consistent.
One or more cells from the timing library is not defined
in the physical library and is not marked 'avoid'.
PHYS-60 Required data not found. A piece of required data (file or constraint) is missing.
The data is required in order for proper operation.
Rerun the command after supplying the data.
PHYS-62 Mapped design not found. A mapped design is required for this command or
operation. Use the 'synthesize -to_mapped' command
to map the design.
PHYS-65 Padding value cannot be negative. Provide positive integer value for the padding.
PHYS-66 Padding value should be integer
number, not floating or negative.
Provide integer padding value to the libcell specified.
PHYS-100 LEF File Interface. Check the LEF file and rerun the command.
PHYS-102 The design core box must lie
within the die box.
Wrong coordinates were specified for the core box.
PHYS-110 The LEF parser encountered an
error.
Check the syntax of the LEF file and rerun the
command.
PHYS-116 Bus bits are missing in LEF file. Check LEF file for correctness.
PHYS-117 Wrong number of coordinates
were specified.
Coordinates are specified as: {llx lly urx ury}.
PHYS-130 DEF writer API internal error. The DEF writer has detected an error with the supplied
data.
PHYS-149 No LEF files have been read. Set the 'lef_library' attribute before doing 'read_def'.
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Error Messages
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PHYS-151 DEF parser encountered an error. Check the syntax of the DEF file and rerun the
command.
PHYS-177 Parent instance for hierarchical
DEF not found.
Check the design name in the hierarchical DEF.
PHYS-190 Pin layer does not match LEF
data.
Pin layers must be consistent with the LEF defined
data.
PHYS-192 Track layer does not match LEF
data.
DEF track layers must be consistent with the LEF
defined data.
PHYS-198 Undefined property referenced. Update the DEF file and rerun the command.
PHYS-200 Unable to open the SPEF file. Could not read SPEF file.
PHYS-201 Design in SPEF file is not
available.
A design must first be read in with 'read_hdl' command
and elaborated with 'elaborate' command.
PHYS-202 Not a valid SPEF file. Could not read SPEF file, invalid SPEF.
PHYS-204 Empty SPEF file. SPEF file size is 0 bytes.
PHYS-205 Unexpected end of file. SPEF file is incomplete.
PHYS-206 Option -capacitance_comparison
not specified.
Option -capacitance_comparison must be used
whenever option -cap_ratio_threshold is used for
read_spef command.
PHYS-213 Library cell instantiation does not
match the floorplan.
The inconsistency between the design and the
floorplan must be resolved. To disable error, do: 'set
read_def_libcell_mismatch_error 0'.
PHYS-220 Invalid port direction. The port connected to the net has a direction other than
in/out/inout.
PHYS-221 Unknown load/driver connected to
the net.
The load or driver connected to the net is neither a
combinational libcell, a sequential libcell, a port nor a
constant.
PHYS-222 Unable to get a corresponding
libcell for the combinational or
sequential instance connected to
the net.
Failed on get_attribute libcell on the combinational or
sequential instance connected to the net.
PHYS-250 This is the unrecognized
capacitance unit.
Make sure to use PF or FF and scale in SPEF file.
PHYS-251 This is the unrecognized
resistance unit.
Make sure to use OHM or KOHM and scale in SPEF
file.
PHYS-352 Rectilinear floorplan shapes are
not supported.
Non-rectangular floorplan shapes are only supported
by DEF version 5.6 or later.
PHYS-354 DEF character limit exceeded. A character count limit specified by the DEF standard
has been exceeded. Use a shorter name for the object
and reissue the command.
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Error Messages
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PHYS-380 Encounter DB Directory not found. Could not find the specified encounter database
directory.
PHYS-381 Provide valid worst delay_corner. A valid worst delay_corner from the view definition file
needs to be provided in case a view-def file is present.
PHYS-382 Error in view definition file. Error in parsing view definition file.
PHYS-384 Failed in setting libraries from view
definition file.
Failed to set the libraries associated with the
worst_corner from view definition file.
PHYS-385 Failed in setting cap-table from
view definition file.
Failed to set the cap-table associated with the
worst_corner from view definition file.
PHYS-386 Failed in handling the config file. Failed to successfully load the config file into RC.
PHYS-387 Failed in handling the encounter
mode file.
Failed to correctly handle the enc_mode_file.
PHYS-388 Failed in handling the avoided
libcells present in netlist.
Failed to set avoid false on all the libcells that are
present in netlist despite being avoided originally.
PHYS-389 Failed in handling the clock-pins. Could not successfully preserve all the clock-related
pins in netlist.
PHYS-390 Failed to preserve all the
sdc-gates.
Could not successfully preserve all the gates that
appear in the sdc.
PHYS-391 Could not find library-set for
specified delay-corner.
Could not find the library set for the specified
delay-corner in the view definition file.
PHYS-392 Could not find rc_corner for
specified delay-corner.
Could not find the corresponding rc_corner for the
specified delay-corner in the view definition file.
PHYS-393 Could not find specified
delay-corner.
Could not find the specified delay-corner in the view
definition file.
PHYS-394 Could not find corresponding
cap-table for rc_corner in view
definition file.
Could not find the corresponding cap-table for the
rc_corner the view definition file.
PHYS-395 Could not find file. File could not be found.
PHYS-396 Config file does not exist. Could not find the config file in encounter database.
PHYS-397 Error loading config file. Could not load the config file into RC.
PHYS-409 Error in handling DEF file. Could not read the specified DEF file.
PHYS-411 Could not find DEF file in
encounter database.
Could not locate the DEF file in the encounter
database. Kindly provide one.
PHYS-412 User specified DEF file does not
exist.
Could not locate the DEF file specified by the user.
PHYS-415 Could not find timing_derate value. The timing derate value was not present in the view
definition file.
PHYS-416 Could not set timing derate. Encountered an error in setting timing derate.
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Error Messages
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PHYS-417 Encountered an error while
processing the view definition file
for timing derate information.
Could not process the timing derate information in the
view definition file correctly.
PHYS-418 Encountered an error while
processing the view definition file
for analysis views.
The above error occurred while processing the view
definition file.
PHYS-426 The option initialize cannot be
coupled with any other switch.
Initialize must be used alone.
PHYS-427 The option highlight has to be
used with min_distance.
The option min_distance must be used only along with
the highlight option.
PHYS-428 The command has to be run with
the '-initialize' switch first.
Before highlighting movement the '-initialize' switch has
to be used.
PHYS-430 Wrong options used for restore
design.
Re-run using correct options.
PHYS-436 Could not read the Encounter
mode file.
The mode file from Encounter could not be read
correctly because of the above reason.
PHYS-441 The CPF file was not found in the
cpfdb file.
The CPF file was not found in the cpfdb file use the -cpf
switch to provide a valid cpf file.
PHYS-442 Failed on read_cpf. The cpf file provided was in-valid, provide a legal cpf
file.
PHYS-445 Could not find corresponding QRC
tech file for rc_corner in view
definition file.
Could not find the corresponding QRC tech file for the
rc_corner the view definition file.
PHYS-446 Failed in setting QRC Tech File
from view definition file.
Failed to set the QRC Tech File associated with the
worst_corner from view definition file.
PHYS-602 SPEF file not found. The SPEF file provided cannot be found. Either the
name or the path of input filename is incorrect.
PHYS-603 Average RC file not found. The Average RC file provided cannot be found. Either
the name or the path of input filename is incorrect.
PHYS-605 Capacitance and Resistance per
unit data not available to proceed.
Provide Average RC file from encounter using the
option "-average_rc_file".
PHYS-606 Sampled nets too few to be able to
proceed.
Generating PLE model for small number of routable
nets is not supported.
PHYS-700 No remote servers were specified. Specify remote servers to be used using the attribute
'super_thread_servers'.
PHYS-1213 Exception occurred while
generating capacitance data from
technology file.
Third party function call failure.
PHYS-1214 Error occurred while invoking kits.
You are running 32 bit executable.
Third party function call failure.
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Error Messages
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PHYS-6187 Lef files are read when design
exists.
Set the 'lef_library' attribute before doing 'elab'.
PI-100 Detected error in power intent file. Fix the error and read the power intent file again.
PI-300 Cannot ungroup instance due to
power intent constraints.
Power intent specification disallows ungrouping of this
instance.
PMBIST-98 Cannot determine type and or
functionality of pin.
Either the 'memory_read/memory_write' section is
missing for this pin/bus in the liberty file or 'port_alias/
port_action' statement is missing in the configuration
file. MBIST is not inserted for this cell. Either correct the
liberty file or use the 'wrapper' statement in the
configuration view file and fully specify the memory
ports and re-run.
PMBIST-99 MBIST is not inserted for this cell. MBIST insertion requires the clock to have active high
polarity to synchronize the memory cell. Memory cell
uses a clock with active low polarity so MBIST is not
inserted for this cell. Ensure the memory cell has an
active high clock.
PMBIST-100 Could not open input file. The specified file could not be found when the
application attempted to open it for input. Ensure the
path and file name are correct.
PMBIST-102 Compressed files are not
supported in RTL flow.
Make sure that the compressed files are not specified
in RTL flow. Correct the issue and re-run.
PMBIST-104 Configuration file module address
partition specification error.
Address partition specification must contain 'row' bits.
Ensure that the 'row' bits are specified and re-run.
PMBIST-112 Configuration file error. Correct the problem identified by the line and column.
PMBIST-113 Configuration file error. Correct the problem identified by the line and columns.
PMBIST-114 Memory allocation errors. Configuration file parsing detected memory allocation
errors. Check the system for the load and available
memory.
PMBIST-115 Configuration file contains
group(s) other than algorithm/
algorithm_constraint/testplan
definition.
Ensure that only test conditions exist while reading test
conditions specific file.
PMBIST-116 Memory module ignored. Configuration file module group specification
re-specifies memory module. It is ignored. Verify all the
memory related information is provided in a single
module group.
PMBIST-117 Memory module group ignored. Configuration file module group specification contains
only re-specified memory modules. It is ignored. Verify
all the memory related information is provided in a
single module group.
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PMBIST-118 Configuration file module address
partition specification error.
Address partition specification contains a data-bit value
which is outside the range of the word width. Ensure
that the data bit value specified in the address partition
section are with-in the range and re-run.
PMBIST-119 Configuration file module address
partition specification error.
Address partition specification contains a bank value
which is outside the range of the banks. Ensure that the
bank value specified in the address partition section are
with-in the range and re-run.
PMBIST-120 Configuration file module address
partition specification error.
Address partition specification contains an order
keyword with non-power of two address values. Ensure
the order size is a power of two.
PMBIST-121 Configuration file module address
partition specification error.
Address partition specification contains an order
keyword with invalid address values.
PMBIST-122 Configuration file module address
partition specification error.
Address partition specification contains an order
keyword with invalid number of address values. Ensure
the order size is proper and re-run.
PMBIST-123 Configuration file module address
partition specification error.
Invalid logical address range specified. Ensure that the
range is non-overlapping across 'row', 'columns' and
'banks' and lies with-in the valid address range of the
memory cell.
PMBIST-124 Cannot determine the size of the
address bus for the memory cell.
Ensure that the 'address_width' attribute is specified in
the 'memory' section of this memory cell in the liberty
file and re-run.
PMBIST-125 MBIST direct access function
exists.
Specified MBIST direct access function already exists.
To update this function, you must first remove this direct
access function and then redefine it.
PMBIST-126 Missing direct access specific pin
on the block.
Specified MBIST direct access function is missing on
the specified block. Block must have the superset of the
direct access functions required at the current level.
PMBIST-127 Conflicting clock requirements for
the direct access specific function
on the block.
Specified MBIST direct access function clock of the
specified block differs than that of the current MBIST
direct access function clock. Clock requirements for the
direct access functions on the blocks being merged
must be same as that of direct access functions
required at the current level.
PMBIST-128 Consistency check failed. Correct the above mentioned issue and re-run.
PMBIST-129 Configuration file contains
group(s) other than module
definition.
Ensure that only module definitions exist with
'read_memory_view'.
PMBIST-130 Memory module already exists. Specified memory module already exists. To update
this module, you must first remove this module and
then redefine it.
PMBIST-131 Duplicate entry found in the
configuration file.
Specified entry exists multiple times. Remove the
duplicate definitions and re-run.
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PMBIST-132 The specified data-bit is missing in
the configuration file.
Make sure that all the data bits are specified in the
configuration file and re-run.
PMBIST-133 Configuration file module
redundancy specification error.
Correct the error mentioned above and re-run.
PMBIST-134 Specification for
'address_partition' is missing from
the configuration file.
Make sure that the 'address_partition' is properly
specified in the 'module' section and re-run.
PMBIST-135 Configuration file contains
group(s) other than algorithm
definition.
Ensure that only algorithm definitions exist while
reading algorithm specific file.
PMBIST-136 The specified range is incorrect. Specified range is outside of the valid range. Remove
the invalid range and re-run.
PMBIST-713 Dynamic memory allocation failed. Ensure sufficient memory is available on the system
and re-run.
PMBIST-730 Cannot read required
configuration file.
Check the appropriate read permissions.
PMBIST-731 No configuration file provided. Provide a valid configuration file.
PMBIST-737 Cannot create a temporary file for
internal processing.
Check the available disk space and the proper
permissions for the directory structure.
PMBIST-739 Cannot determine the current
working directory.
Ensure proper environment settings.
PMBIST-749 Errors found in the configuration
file.
Correct the configuration file and re-run.
PMBIST-750 Duplicate definition found. Correct the problem identified by the line and columns.
PMBIST-790 No clock specified for the target
group.
Correct the configuration file and specify the mandatory
keyword 'clock'.
PMBIST-791 Missing JTAG instruction from vdir
structure.
Define the JTAG instruction using 'define_dft
jtag_instruction' command and re-run.
PMBIST-792 Common clock source at the chip
level for blocks having different
clock frequencies at the block
level.
The interface files being merged have different clock
frequencies at the block level. But the source clock at
the chip level is same. Make sure that correct set of
interface files have been specified. Correct this problem
and re-run.
PMBIST-793 Missing MBIST specific ports on
the block.
Cannot merge the specified block because this does
not have PMBIST specific ports. Either the provided
interface files are not proper or the 'insert_dft pmbist'
command was not run without both the options
'-connect_to_jtag' and '-dont_create_mbist_ports' on
this block.
PMBIST-794 Could not check the block for
validity.
Missing MBIST specific ports on the block.
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PMBIST-795 MBIST clock has no hookup pin. Option '-internal_clock_source' requires a hookup pin.
Either provide a hookup pin or remove option
'-internal_clock_source' and re-run.
PMBIST-797 MBIST clock has no associated
name.
In case of internal clock, MBIST clock must have an
associated name. Either provide a name or remove
option '-internal_clock_source' and re-run.
PMBIST-954 Cannot determine the output
enable pin structure.
Contact Cadence Customer Support for assistance.
PMBIST-955 Netlist does not match the
provided interface files.
Provide correct interface files and re-run.
PMBIST-956 Bus indices do not match with bus
size.
MBIST is not inserted for this cell. Verify that the
correct indices are specified in the liberty file and
re-run.
PMBIST-3005 Cannot create directory for storing
generated output.
Check to ensure the file permissions allow creation of
directories and that there is available disk space. Fix
the environment and re-run.
PMBIST-3013 Cannot close the program's
temporary internal file.
Ensure file permissions and available disk quota.
PMBIST-3018 Cannot insert a BIST engine for
the memory instance.
BIST engine is in a multiply used module. In such cases
BIST engine location should be either in the same or in
the parent hierarchical block of the referenced memory
instance location.
PMBIST-3019 Cannot create a temporary file for
internal processing.
Check the available disk space and the proper
permissions for the directory structure.
PMBIST-3023 Conflicting BIST requirements for
memory instances.
Module containing memory instance of memory cell is
used multiple times and has conflicting BIST
requirements. Uniquely instantiate the netlist or specify
consistent BIST requirements.
PMBIST-3027 Specified BIST engine location is
not found in the netlist.
Specify a valid BIST engine location and re-run.
PMBIST-3032 Unable to find chip select pin. The memory cell does not have a chip select pin
associated with a port. Correct the issue mentioned
above and re-run.
PMBIST-3033 Instance of a multiply used module
is specified as 'location' for BIST
engine inside the configuration file.
Correct the issue mentioned above and re-run.
PMBIST-3034 Instance of a multiply used module
is specified as 'location' for
algorithm memory unit.
Correct the issue mentioned above and re-run.
PMBIST-3042 An unexpected condition occurred
in the program.
Re-run the command with '-debug' option. Report this
error to customer support and provide the logfile
generated with '-debug' option.
PMBIST-3048 The specified file does not exist. Make sure that the file name is correct and it exists.
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PMBIST-3050 Could not find 'JTAG_MODULE'. Either the 'JTAG_MODULE' does not exist, or the
'JTAG_MODULE' does exist but cannot be found. You
can use the 'find' command to search for the
'JTAG_MODULE' instance in the design.
PMBIST-3051 Could not find the required jtag
instruction.
Required jtag instruction is not present in the vdir
structure. Make sure that the instruction has been
specified using 'define_dft jtag_instruction' and re-run.
PMBIST-3052 Conflicting options given to the
command.
Conflicting options are given to the command. Only one
option can be specified from the options listed above.
Make sure that the correct options are given and re-run.
PMBIST-3053 Register associated with
programmable MBIST instruction
is invalid.
Ensure that each programmable instruction uses a
unique/non-default register and re-run.
PMBIST-3056 Specified instance does not have a
corresponding 'libcell' or
'subdesign' attribute.
Ensure that either the correct liberty (.lib) file is
provided and check for syntax errors pertaining to the
liberty file in the log or 'wrapper' is specified during
'read_memory_view'. Also verify the instance hierarchy
is completely specified, and re-run.
PMBIST-3064 Redundant jtag instruction
specified.
Specified jtag instruction is not required. This may lead
to failure of boundary scan verification. Make sure that
the specified instruction is required and re-run.
PMBIST-3066 Interface file does not exist. Verify that the provided interface file directory is correct
and re-run.
PMBIST-3071 Clock mentioned in the
configuration file is not defined as
'mbist_clock'.
Specify the proper 'mbist_clock' in the configuration file
and re-run.
PMBIST-3082 Memory instances associated with
a BIST engine have different
clocks.
Make sure that either 'clock_mux' is specified in the
configuration file for the specified memories or all clock
pins of the specified memories are driven from the
same clock source and re-run.
PMBIST-3083 Source of the clock pin of the
memory is different than that of the
'mbist_clock' specified for this
memory.
Make sure that either 'clock_mux' is specified in the
configuration file for the specified memory or all clock
pins of the specified memory are driven from the source
of its 'mbist_clock'. Correct the issue mentioned above
and re-run.
PMBIST-3087 Conflicting '-direct_access_only'
option requirements.
Option '-direct_access_only' requested but cannot be
satisfied. Make sure that 'burnin_run' and/or
'poweron_run' functions have been defined using
'define_dft mbist_direct_access'.
PMBIST-3089 All required JTAG ports not found
on the design.
Verify that all the required JTAG ports are present on
the design and re-run.
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PMBIST-3090 The configuration file contains
multiple specifications of the
memory instance in the 'target' or
'ignore' section.
The instance may have been specified using module
name as well as instance name. Ensure that each
instance is specified only once in the 'target' or 'ignore'
section and re-run.
PMBIST-3094 Could not find any register
associated with the jtag
instruction.
Register associated with the specified jtag instruction is
not present in the vdir structure. Make sure that the
register has been specified with the command
'define_dft jtag_instruction' and re-run.
PMBIST-3096 More than one control signal found
on the memory.
Make sure that the above mentioned control signals are
properly specified in the 'port_action' or 'port_alias'
section of the configuration file and re-run.
PMBIST-3098 Programmable MBIST instruction
is specified as 'private'.
Programmable MBIST instruction should not be
specified as 'private' otherwise downstream tools may
fail. Make sure that the programmable MBIST
instructions are not specified as 'private' and re-run.
PMBIST-3100 More than one memory cell found
with the name specified in the
'target' or 'ignore' group.
Ensure that the name specified in the 'target' or 'ignore'
group is correct and re-run.
PMBIST-3101 Unable to find any memory cell
with the name specified in the
'module' group.
Either the name specified in the configuration file is not
correct, or the 'memory' section is missing from the
liberty file. Either correct the liberty file or use the
'wrapper' statement in the configuration view file and
fully specify the memory ports and re-run.
PMBIST-3102 Memory cell/instance, specified in
the configuration file, is not
present.
Either the name specified in the configuration file is not
correct, or all the liberty files are not provided. Correct
the problem mentioned above and re-run.
PMBIST-3103 No instance of the memory cell,
specified in the target/ignore
group, is present in the design.
Either remove this entry from the target/ignore group or
make sure that the name specified in the target/ignore
group is correct and re-run.
PMBIST-3104 Memory module/instance,
specified in the 'module' or 'target'
or 'ignore' group, is not a
recognizable memory cell.
Either the 'memory' section is missing from the cell
description in the liberty (.lib) file or the instance
hierarchy is not completely specified. Ensure that the
correct liberty file is provided and check for syntax
errors pertaining to the liberty file in the log. Also verify
that the instance hierarchy is completely specified in
the configuration file, and re-run.
PMBIST-3105 Pin specified in the 'port_action' or
'port_alias' section of the
configuration file is not present on
the memory cell or wrapper
module.
Either remove this entry from the 'port_action'/
'port_alias' section or make sure that the name
specified in the 'port_action'/'port_alias' section is
correct and re-run.
PMBIST-3106 Invalid value specified. Correct the problem mentioned above and re-run.
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PMBIST-3107 Library domains do not match. Comparators, memory instances and associated BIST
engine must belong to either same library domain or
library domains of same set. The library domains which
belong to same set are specified with the help of
'mbist_enable_shared_library_domain_set' attribute.
Ensure that the domains are specified correctly and
re-run.
PMBIST-3110 Hookup pin of the 'mbist_clock' is
not controllable from its source
port.
Hookup pin of the 'mbist_clock' must be controllable
from its source port. In case it is not controllable then
boundary scan verification or simulation may fail. To
debug this further, first run 'set_dft_configuration_mode
-dft_configuration_mode <pmbist mode>' and then run
'dft_trace_back -through -mode 1 -print -continue'
command with the above mentioned hookup pin name.
Make sure that either this pin is controllable in 'pmbist'
configuration mode or 'dft_controllable' attribute is
properly set so that it becomes controllable and re-run.
PMBIST-4000 The wrapper module specified in
the configuration file is not present
in the design.
Make sure that the specified module exists in the
design and re-run.
PMBIST-4001 Instances of the memory module
specified in the configuration file
are not inside the specified
wrapper module.
Make sure that the proper wrapper module exists
around all the memory instances and re-run.
PMBIST-4002 The wrapper module specified in
the configuration file contains zero
or more than one memory
instance.
Make sure that the wrapper module contains exactly
one memory instance and re-run.
PMBIST-4003 Unable to find the information of
memory cells in the database.
Make sure that the 'read_memory_view' command has
been run before proceeding.
PMBIST-4004 Missing definition of the
'mbist_clock' in the configuration
file.
Make sure that the 'mbist_clock' is properly specified in
the configuration file before proceeding.
PMBIST-4005 The hookup pin of the specified
clock is inside of a multiply used
module.
Ensure that the clock hookup pin is not inside the
multiply used module or uniquify the netlist and re-run.
PMBIST-4006 The selected algorithms do not fit
into the constraints specified for
the algorithms.
Ensure that either the correct set of algorithms is
selected or modify the algorithm constraints and re-run.
PMBIST-4007 The conflicting requirements
specified for comparator.
Ensure that either the correct set of requirements are
specified for comparator or uniquify the design and
re-run.
PMBIST-4008 Cannot insert a comparator for the
memory instance.
Comparator is in a multiply used module. In such cases
comparator location should be either in the same or in
the parent hierarchical block of the referenced memory
instance location.
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PMBIST-4009 Conflicting BIST requirements for
comparator instances.
Module containing comparator instances is used
multiple times and has conflicting BIST requirements.
Uniquely instantiate the netlist or specify consistent
BIST requirements.
PMBIST-4010 Duplicate entry found. Specified entry exists multiple times. Remove the
duplicate definitions and re-run.
PMBIST-4011 No test conditions found in the
input file.
Specify the proper test conditions and re-run.
PMBIST-4012 Improper test conditions found in
the input file.
Specify the proper test conditions and re-run.
PMBIST-4013 Improper write enable mask
binding specified.
Specify the proper write enable mask binding and
re-run.
PMBIST-4014 Bypass enable pin of the memory
is not connected.
Ensure that the bypass enable pin of memory is
properly connected. This is required to ensure that the
memory data is not visible during ATPG. This is also
required to ensure that the bypass enable is disabled
functionally. Correct the above mentioned problem and
re-run.
PMBIST-4015 Control signal is not associated
with any port of the memory.
Make sure that the above mentioned control signals are
properly specified in the 'port_action' or 'port_alias'
section of the configuration file and re-run.
PMBIST-4016 Unable to find the information of
interface files in the database.
Make sure that the 'insert_dft pmbist' command has
been run before proceeding.
PMBIST-4017 Improper 'wrapper' specification. Correct the 'wrapper' specification and re-run.
PMBIST-4018 Improper usage of
'algorithm_constraints' section.
Ensure that either the specified constraint is not
provided in this section or at-least one testplan is
specified as programmable. Correct the above
mentioned problem and re-run.
POPT-1 Failed to execute features not
implemented yet.
Change the transformation setup and rerun the
command.
POPT-15 A clock-gating integrated cell
name must be specified for this
attribute.
Use a valid clock-gating integrated cell name and then
re-set the attribute.
POPT-16 Cannot find a clock-gating
integrated cell with the given
name.
Use a valid clock-gating integrated cell name or load in
the proper library and then re-set the attribute.
POPT-23 Failed to set the test signal for
clock-gating.
If multiple designs are loaded when you set the
'lp_clock_gating_test_signal' attribute, make sure that
the test signal belongs to the design you are setting the
attribute on.
POPT-37 Failed to set the test signal for
clock-gating.
The test signal can only be set either on the top design
or on the clock-gating instances.
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POPT-41 Failed to insert clock-gating logic
in the netlist.
Specify a clock-gating integrated cell which belongs to
the same library domain as the design or subdesign.
POPT-46 Failed to connect test-control logic
for clock-gating.
Make sure that the library has at least one usable
inverter. If library domains are defined, make sure that
each of these library domains has a usable inverter.
POPT-59 Could not insert clock-gating logic
in unmapped netlist.
Unmap the design using the 'synthesize -to_generic'
command and re-run the 'clock_gating insert_in_netlist'
command.
POPT-60 Could not insert clock-gating logic
in mapped netlist.
Map the design using the 'synthesize -to_mapped'
command and re-run the 'clock_gating insert_in_netlist'
command.
POPT-70 User defined test signal is defined
with -shared_in option.
Specify a test signal which is not shared and then
re-set attribute lp_clock_gating_test_signal.
POPT-84 Could not insert shared
clock-gating logic.
Map the design using the 'synthesize -to_mapped'
command and re-run the 'clock_gating share'
command.
POPT-93 The library does not have the
minimum required usable libcells.
Ensure that the library has the minimum required
usable libcells and re-run the command.
POPT-203 Operand Isolation will not be
performed.

POPT-516 More than one library cell matches
the given wildcard pattern.
Specify the full path of the library cell to be used, or
refine the wildcard pattern so that it matches a single
library cell.
POPT-517 No library cells matches the given
wildcard pattern.
Give the full path to the library cell to be used, or a
wildcard pattern that matches a library cell.
POPT-521 Cannot specify driver for power
gating pin.
You can only set the 'lp_srpg_pg_driver' instance
attribute on leaf sequential instances like flops and
latches.
POPT-524 Invalid string specified for either
the 'lp_map_to_srpg_cells'
attribute or the
'lp_map_to_srpg_type' attribute.
If the intention was to specify the string with the
'lp_map_to_srpg_cells' attribute, no matches could be
found. You can refine the setting with a new string. If the
intention was to specify the string with the
'lp_map_to_srpg_type' attribute, specify a proper power
gating cell type corresponding to a sequential cell in the
library.
POPT-540 Cannot apply
'lp_map_to_srpg_cells' attribute
on a state retention cell which is
not sequential.
Specify a proper state retention cell which is also
sequential in nature for the 'lp_map_to_srpg_cells'
attribute. A sequential cell will always have a clock pin.
The cell being passed to the attribute here does not
have a clock pin specification.
POPT-545 The cell being used is not a state
retention cell.
Only state retention library cells can be used for state
retention mapping. Provide a cell with the
'power_gating_cell' attribute 'true' to use it for state
retention synthesis.
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Error Messages
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POPT-550 Syntax error in input VCD file. Correct the error at indicated line number.
POPT-551 Either the scope specified is not
found or it is empty.
Ensure that the scope being monitored is present in the
VCD file.
POPT-552 The output TCF file could not be
generated.
Check that proper permissions are set to write to the
TCF file.
POPT-554 The scope to be monitored is not
uniquified.
If you pass '-module' option to 'read_vcd' make sure
that it is uniquified and refers to only a single instance
in the hierarchy.
PTAM-300 Could not create file. Verify permissions are correct, and that there is enough
disk space.
PTAM-301 Could not create output directory. Verify permissions are correct, and that there is enough
disk space.
PTAM-302 Pin specification is invalid. Verify the pin name is correct.
PTAM-303 Could not find pin on the specified
block.
Verify that the block and pin names are correct.
PTAM-304 There must be exactly 1 net
connected to pin specified.
Verify that the pin is only connected to 1 object.
PTAM-305 There must be exactly 1 driver for
the net.
For the pin specified, the associated net must have
exactly 1 driver. Verify that the net has only 1 driver.
PTAM-306 There must be exactly 1 receiver
for the net.
For the pin specified, the associated net must have
exactly 1 receiver. Verify that the net has only 1
receiver.
PTAM-307 Unable to determine function
information.
Could not determine function information for the I/O cell
specified. This could indicate some information is
missing from the liberty file.
PTAM-308 There must be exactly 1 port for
the pin.
Did not find exactly 1 port for the pin. Make sure the pin
traces to exactly 1 port.
PTAM-309 There must be exactly 1 input pin
for the module.
For the module containing the output pin, there must be
1 input pin. Make sure there is 1 input pin on the
module.
PTAM-310 One or more objects specified to
set_attribute are empty.
Trying to set one or more of the attributes on the pin to
an empty value.
PTAM-311 Exactly 1 top level design is
required for insert_dft ptam.
Found more than 1 top level design, make sure there is
only one top level design.
PTAM-312 Required pin not specified. A pin required was not specified on the command line.
Specify the pin name on the command line.
PTAM-313 Pin not specified. A pin was not specified on the command line, and too
many default pins were found in test_signals directory.
PTAM-314 Containing module for shutoff
signal is a black box.
Only hierarchical instances are currently supported.
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PTAM-315 Containing module for shutoff
signal is a libcell or primitive.
Only hierarchical instances are currently supported.
PTAM-316 Containing module for ice signal is
a black box.
Only hierarchical instances are currently supported.
PTAM-317 Containing module for ice signal is
a libcell or primitive.
Only hierarchical instances are currently supported.
PTAM-318 Containing module for the
lp_srpg_pg driver signal is a black
box.
Only hierarchical instances are currently supported.
PTAM-319 Containing module for the
lp_srpg_pg driver signal is a libcell
or primitive.
Only hierarchical instances are currently supported.
PTAM-320 No valid power domains found for
isolation rule.
Could not find any valid power domains for the isolation
rule. There must be at least 1 valid power domain.
PTAM-321 Could not find a valid pin for port. If an I/O cell is present for the port, ensure the liberty
file has been loaded for the cell.
PTAM-322 Could not find JTAG_MODULE. When the -connect_to_jtag option is specified, a
JTAG_MODULE is required. Ensure a JTAG_MODULE
is present in the design.
PTAM-323 Could not check out an
Encounter_Test_Architect license.
Make sure a valid license is available.
PTAM-324 Could not free an
Encounter_Test_Architect license.
Make sure a valid license is available.
PTAM-325 Missing information about the
PTAM instruction.
Values required include: instruction name, associated
register and opcode. Make sure this information is
available.
PTAM-326 Missing insert_dft boundary_scan
information.
Could not locate the directory containing
jtag_instruction information: /designs/test/dft/
boundary_scan/jtag_instructions. Ensure insert_dft
boundary_scan has been executed.
PTAM-329 No enable pins found for power
domain.
There must be at least one valid enable pin for the
power domain. Ensure the power domains are fully
described in the cpf.
PTAM-330 No shutoff signal found for any of
the power domains.
There must be at least one valid shutoff signal
specified. Add the information for the shutoff signals to
the CPF file and reload the CPF file using the
'reload_cpf' command.
PTAM-331 Existing instruction values do not
match command line values.
One or more of the existing instruction values do not
match the values specified on the command line.
Ensure the values specified are correct.
PTAM-332 Required options missing. Ensure all required options have been specified.
PTAM-334 Invalid polarity value specified. Valid values are: high, low. Specify a valid value.
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Error Messages
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PTAM-338 Black box found when tracing pin. While tracing a pin, a black box was encountered.
Cannot trace through the black box.
PTAM-339 The tap instance specified is
invalid.
The tap instance must be at the same level of hierarchy
or higher than any logic inserted by ptam. Specify a
valid tap instance.
PTAM-340 Missing insert_dft boundary_scan
information.
Could not locate the directory containing jtag_ports
information: /designs/test/dft/boundary_scan/
jtag_ports. Ensure insert_dft boundary_scan has been
executed.
PTAM-341 Could not determine test mode
signal.
Zero or more than one test mode signals present, make
sure exactly one test mode signal has been specified.
PTAM-342 Could not determine scan enable
signal.
Zero or more than one scan enable signals present,
make sure exactly one scan enable signal has been
specified.
PTAM-343 There must be exactly 1 output pin
for the module.
For the module containing the input pin, there must be
1 output pin. Make sure there is 1 output pin on the
module.
PTAM-344 No libcell found for sequential
element.
The pins on sequential elements with the lp_srpg_pg
attribute are analyzed to determine the
power_gating_cell attribute. A library cell could not be
found for the sequential element mentioned. Make sure
the design has been mapped to a technology.
PTAM-345 No default power mode found. A default power mode is required in order to create the
proper power mode transitions. Make sure a default
power mode has been defined.
PTAM-346 No driver found. Power domain shutoff signals, isolation control enable
signals, and power gate enable signals must be
specified as pins driven by instance/pins or top-level
ports. Ensure that the correct signal has been specified
in the CPF file and ensure that the specified pins are
driven in the netlist.
PTAM-347 The power domains for isolation
rule are a mixture of internally
controlled and externally
controlled. This isolation rule is
not supported.
All the power domains for the isolation rule must be
internally or externally controlled, not a combination.
PTAM-348 A shift_enable test_signal was not
found.
A shift_enable test_signal was not specified on the
command line, and no default pins were found in the
test_signals directory. This signal is required when
retention flops are present in the design. Specify a
valid shift_enable test_signal on the command line or
with the define_dft test_signal command.
RCLP-101 Something is wrong with the
command options.
Check the options and try again.
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Error Messages
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RCLP-201 CLP did not run successfully. Check the logfile.
RCLP-202 Conformal not found. Set the environment variables VERPLEX_HOME/PATH
appropriately or set the attribute 'lec_executable'
appropriately.
RCLP-203 Low Power rule check did not
finish successfully.
This may result in design errors.
RCLP-205 Failed to Launch Conformal Low
Power.
Specify one of the following values for the '-license'
option of the 'check_cpf' command: 'lp', 'lpxl' or 'lpgxl' .
RCLP-206 Could not launch Conformal Low
Power with specified license.
Make sure that the license specified with the '-license'
option of the 'check_cpf' command is available.
RCLP-207 Could not launch Conformal Low
Power.
Make sure that the license to run Conformal Low Power
is available.
RETIME-101 The '-min_area' and '-min_delay'
options are mutual exclusive.
Use only one of them at a time.
RETIME-102 One of the following options must
be specified:
'-<min_area|min_delay|prepare>'.
Specify one of these options.
RETIME-104 Cannot meet the timing
requirements.
Increase the target delay or use the min_period option.
RETIME-105 Cannot synthesize the inserted
flops.
Make sure that a suitable library cell is available.
RETIME-106 Cannot synthesize the decompose
logic.
Make sure that a suitable library cell is available.
RETIME-107 Unable to run the retiming feature. Check that you have the correct license.
RETIME-108 The '-min_area', '-min_delay',
'-forward' and '-backward' options
are mutual exclusive.
Use only one of them at a time.
RETIME-109 Unable to run the retiming feature. Check that you have the correct license.
RETIME-201 This attribute can only be set on
sequential instances.
Use this attribute on sequential instances to specify
which combinational instances should be retimed.
RETIME-401 The retimeable flops are clocked
with different clocks.
Make sure that the retimeable flops are all clocked with
the same clock.
RETIME-402 The design does not contain
retimeable flops.
Make sure that the design contains flops with the
attribute 'dont_retime' set to 'false'. Some of the flops
could have been excluded for retiming implicitly, as
opposed to explicitly with the 'dont_retime' attribute.
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RETIME-403 There is an interaction between
data and control signals of
retimeable flops.
Make sure that retimeable flops do not drive any control
signals of other retimeable flops. For example, check
whether there are enables for the retimeable flops
being driven by another flop. If this is the case, set the
'retime' attribute on the enable driver flop to 'false'.
Otherwise, all the other flops will be implicitly marked
as dont_retime and they will not be retimed.
RETIME-404 The retimeable flops are driven by
different clock sources.
Retiming will not occur if the flops are driven by multiple
clocks. Find the main clock source and then set the
'retime' attribute to 'false' on the flops triggered by other
clocks. If all the clock domains need to be retimed, you
can repeat this process on each clock source.
RETIME-407 There are instances with negative
delay in the design.
Instances with negative delay are not supported in
retiming.
RETIME-408 All retimeable flops are floating. Make sure that there are retimeable flops in the design
which drive something.
RETIME-502 No designs/subdesigns were
specified for clock scheduling.
Specify designs/subdesigns for clock scheduling.
RETIME-503 Multiple designs were found for
clock scheduling.
Specify a single design for clock scheduling.
RETIME-504 A different design has gone
through clock latency scheduling.
Cannot switch to a different design in the following clock
latency scheduling.
RETIME-505 The command 'clock_schedule
-indirect_method' is not allowed
when the attribute
'use_multi_clks_latency_uncertain
ty_report' is 'false'.
Set the attribute
'use_multi_clks_latency_uncertainty_report' to 'true'.
RETIME-506 Only clock schedule calculated by
the indirect method can be
dumped.
Specify -indirect_method.
RETIME-602 Unable to perform incremental
retiming due to following reason.
Refer to RC documentation for further details.
RPT-1 Invalid depth. Depth must be positive.
RPT-2 Invalid sort mode. The valid sort modes for nets are 'load', 'net', 'prob',
'rate', and 'dynamic'. The valid sort modes for instances
are 'internal', 'leakage', 'net', and 'dynamic'. For RTL
power analysis, you can also sort the report for
instances by 'file'.
RPT-3 Not a hierarchical instance. Specified instance is not a hierarchical instance & it is
being skipped from reporting.
RPT-6 HDL cross referencing not
enabled.
Set the 'hdl_track_filename_row_col' attribute to true
before running 'report power -rtl'.
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Error Messages
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RPT-8 HDL not found. Ensure that the HDL files that were read in are still
present.
RPT-9 Multiple options specified. Specify multiple hierarchical instances OR specify a
single instance with option '-hierarchy'.
RPT-12 Invalid sort mode. The valid sort modes for RTL power analysis are
'file'(default), 'leakage', 'dynamic' and 'total'. The valid
sort modes for RTL power analysis with '-detail' option
are 'file'(default), 'leakage', 'internal' and 'net'. The valid
sort modes for RTL power analysis with '-verbose'
option are 'file'(default), leakage', 'internal', 'dynamic',
'net', 'dynamic', and 'total'.
RPT-20 Invoke this command after loading
a design.
See the Command Reference for Encounter RTL
Compiler for more information.
RPT-21 Invoke this command from a
design.
See the Command Reference for Encounter RTL
Compiler for more information.
RPT-31 Invalid option. See the command help or the Command Reference for
Encounter RTL Compiler for more information.
RPT-32 Invalid sort option. See the command help or the Command Reference for
Encounter RTL Compiler for more information.
RPT-35 Invalid option. Cannot specify both '-instance_hier' and '-hier' options.
RPT-36 A required object parameter could
not be found.
Check to make sure hierarchical instance name is
entered for '-instance_hier' option.
RPT-37 Invalid option. See the command help or the Command Reference for
Encounter RTL Compiler for more information.
RPT-40 Failed to report the deleted
sequential elements.
To report the deleted sequential elements, specify the
command with the '-deleted_seqs' option and without
any other options.
RPT-44 Found two mutually exclusive
options.
Refer to the command description in the Command
Reference for Encounter RTL Compiler for more
information about the options of this command.
RPT-60 Invalid option. Specify both '-startpoint' and '-endpoint' options to
report levels.
RPT-61 Invalid option. Cannot specify '-startpoint' or '-endpoint' with
'-num_paths' or '-slack' option.
RPT-100 No design available. Load a design before using this command.
RPT-101 Option value is invalid. Check the type of value expected by this option.
RPT-901 Improper/null wireload mode
defined.
The wireload_mode attribute is neither top,enclosed
nor segmented.
RPT-902 Invalid option combination. The options specified are not appropriate to the
command under consideration.
RPT-905 Invalid instance type specified. The specified instance is not a libcell.
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Error Messages
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RPT-906 Invalid driver pin specified. The specified pin is not a valid output pin.
RPT-907 The specified pin/port is not a valid
driver.
The specified pin/port is not a valid output pin.
RPT-908 The specified pin/port is not a valid
load.
The specified pin/port is not a valid input pin.
RPT-909 Both the driver and load pins/ports
are not on the same net.
It is not possible to calculate the net delay between
both the pins/ports.
RPT_CG-1 Could not preview the design. Preview clock-gating works for either completely
unmapped or partially mapped designs.
RPT_CG-2 Could not report clock gating for
the specified clock.
To specify a clock with the -clock option, you must have
defined the clock either with the define_clock command
or through an SDC constraint. If no clocks were
defined, use the -clock_pin option.
RPT_CG-9 Could not generate the
clock-gating report.
The value for the step option must be a list of lists. Each
list should have two positive integers; the first entry
should be less than or equal to the second. In addition,
the start point of each range must be larger than the
stop point of the previous range.
RPT_CWD-100 Invalid combination of options
supplied to report cwd command.
The options specified while invoking report cwd
command are not compatible. Remove the conflicting
options and execute report cwd again.
RPT_DP-101 All of the report column widths
specified with -max_width option
are set to zero.
The list specifying the maximum column width for the
Module, Instance, Operator, Signedness, Architecture,
Inputs, Outputs, CellArea, Line, Col, Filename sets all
the columns to zero. A zero specification hides the
column. To see the desired columns, set the
-max_width option to a non-zero value for each column
to be viewed.
RPT_DP-105 Invalid combination of options
supplied to report datapath.
The options specified while invoking report datapath
command are not compatible. Remove the conflicting
options and execute report datapath again.
RPT_DP-107 Format of list specified with
-max_width option is incorrect.
To control the width of a column of a report using
-max_width option specify the width as follows
-max_width {{<column_name1> <width1>}
{<column_name2> <width2>}}.
SAIF-1 Parse error. The SAIF parser could not continue parsing the SAIF
file. The most common reason for a parse error is
mismatched parenthesis.
SAIF-3 SAIF file does not exist. Ensure that the SAIF file exists in the current path.
SAIF-8 Invalid instance(s) specified. Multiple matches found for instance.
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Error Messages
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SDC-19 The design contains constraints
which have no SDC equivalent.
If the design constraints were created using the
'derive_environment' command, the '-sdc_only' option
of that command should be used so that only
constraints that can be expressed in SDC are
generated. By default 'derive_environment' uses the
more powerful RC constraints which cannot always be
converted to SDC.
SDC-20 The 'write_sdc' command requires
the '-mode' option.
Specify the '-mode' option for multi-mode timing
designs to write out the constraints for each mode
individually.
SDC-21 The specified '-mode' option does
not match the given design.
The given mode should be in the same design specified
with the 'write_sdc' command. There are multiple
designs so you must specify a design and the mode to
write out the constraints for that design. Use the 'find'
command to retrieve all the modes in the given design
and choose one at a time for writing out SDC
constraints. For example: 'write_sdc -mode foo /
designs/d2'.
SDC-22 Invalid option combination for
write_sdc.
This option is not valid for the indicated SDC command.
SDC-202 Could not interpret SDC
command.
The 'read_sdc' command encountered a problem while
trying to evaluate an SDC command. This SDC
command will be added to the Tcl variable
$::dc::sdc_failed_commands.
SDC-203 Option missing for SDC command. This SDC command requires the indicated options.
Check the SDC command and contact Cadence
customer support if you believe this option combination
should be supported.
SDC-204 Invalid SDC command option
combination.
This option is not valid for the indicated SDC command.
Check the SDC command and contact Cadence
customer support if you believe this option combination
should be supported.
SDC-205 Incorrect option value. Check the option value given to this command because
the one given is not valid.
SDC-210 One or more commands failed
when these constraints were
applied.
You can examine the failed commands or save them to
a file by querying the Tcl variable
$::dc::sdc_failed_commands. By default, the 'read_sdc'
command will not stop if it encounters an error and if
the '-stop_on_errors' option is not used.
SDC-211 A given object is not suitable for
this exception.
The indicated object cannot be used in this exception
specification. In order to process this exception, the
object needs to be removed from the specification.
SDC-212 SDC command requires a mode
specification.
The indicated command requires that a mode be
specified. Use the 'set_mode' or 'read_sdc -mode'
option to indicate the mode for the command.
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SDC-213 Mode mismatch for SDC
command.
The indicated command requires that a mode option
matching the clock be specified.
SDC-215 Cannot read SDC file(s) for
non-default mode.
An RTL_Compiler_Ultra_II_Option license is required
to invoke this feature.
SDC-216 Invalid object type. The object type specified is not a valid one for the
specified property.
SDC-217 Invalid property. The property specified is invalid. Specify a valid
property name.
SDC-218 Invalid option combination. Specified option combination is not valid.
SDC-220 No inputs provided. Specify one of the required inputs.
SDC-221 Invalid collection. The indicated command does not support the specified
object collection.
SDC-222 The number of collections for the
command should be two.
Specify two collection.
SDC-223 The given index is not valid. The indicated command does not support the index.
SDC-224 The base collection should be an
existing or non-existing collection
name.
Specify a valid input to base collection.
SDC-225 Invalid collection. Base collection does not support object list.
SDC-226 Invalid collection. Specify a valid input.
SDC-227 Expecting single object but found
multiple objects.
Command does not support multiple objects.
SDC-228 The indicated command need two
valid collections.
Specify valid inputs.
SDC-231 Could not interpret an embedded
SDC command.
The 'read_sdc' command encountered a problem while
trying to evaluate an embedded SDC command. This
embedded SDC command will be added to the Tcl
variable $::dc::embedded_sdc_failed_commands.
SDP-1 Wrong SDP group is specified. The specified SDP group already exists.
SDP-11 Wrong SDP row is specified. The specified SDP row already exists.
SDP-12 Wrong SDP column is specified. The specified SDP column already exists.
SDP-13 Wrong SDP datapath is specified. The specified SDP datapath already exists.
SDP-14 Wrong SDP skip is specified. The specified SDP skip already exists.
SDP-15 Wrong SDP skip is specified. The specified SDP skip must be next to the existing
SDP group/row/column/instance.
SDP-20 Invalid instance is specified. The instance does not exist.
SDP-21 Wrong SDP instance is specified. The specified SDP instance already exists.
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Error Messages
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SDP-30 Wrong SDP group is specified. The specified SDP group already exists.
SDP-31 Wrong SDP row is specified. The specified SDP row already exists.
SDP-32 Wrong SDP column is specified. The specified SDP column already exists.
SDP-33 Wrong SDP datapath is specified. The specified SDP datapath already exists.
SDP-34 Wrong SDP instance is specified. The specified SDP instance already exists.
STAT-1 Specified 'stage_id' is not unique. Use 'statistics run_stage_ids' command for the
'stage_id' names currently used.
STAT-5 Invalid filename specified. The filename specified was not found.
STAT-8 Invalid metric name. Only user defined metrics can be removed using
'remove_metric' command.
STAT-9 Invalid 'run_id' specified. Run 'statistics run_stage_ids' command to get a list of
valid run id's and their corresponding stage id's.
STAT-10 Invalid 'stage_id' specified. Run 'statistics run_stage_ids' command to get a list of
valid run id's and their corresponding stage id's.
STAT-11 Invalid command option
combination.
Specified option combination is not valid.
STAT-15 Invalid option specified. Only 'header' or 'footer' options can be specified.
STAT-25 RC db not populated with
statistics.
The RC database is not populated with statistics data.
STRUCT-120 GBB. Struct: Error during Verilog Netlist Parsing/Elaboration.
STRUCT-121 Port has no type. Specify the port as either an input, output, or inout port.
STRUCT-122 Unknown instance port name. An instantiation has a named connected port, which is
not specified in the module definition or in technology
cell definition. This can happen if too many ports are
specified in the instantiation or if the port name is
misspelled. Check the module definition or Technology
Library for the instance to determine the valid ports.
STRUCT-124 Cannot define an implicit wire with
a range.
Only a wire without a range can be implicitly defined.
STRUCT-125 Port not declared in the module
interface.
Struct: Error during Verilog Netlist Parsing/Elaboration.
STRUCT-126 Port declared more than once in a
module.
Struct: Error during Verilog Netlist Parsing/Elaboration.
STRUCT-128 Could not find port. Struct: Error during Verilog Netlist Parsing/Elaboration.
STRUCT-129 Too many arguments to instance. Struct: Error during Verilog Netlist Parsing/Elaboration.
STRUCT-130 Multiple definitions. An instance name cannot be defined more than once in
the same module. Make the instance name unique.
STRUCT-131 Illegal constant format. Struct: Error during Verilog Netlist Parsing/Elaboration.
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STRUCT-132 Out-of-range bit-select or
part-select.
Struct: Error during Verilog Netlist Parsing/Elaboration.
STRUCT-133 Invalid inout connection. An inout port cannot be driven by a constant value.
STRUCT-135 Inconsistent unresolved module
instantiation.
Check if technology libraries are specified correctly.
STRUCT-136 Invalid port name in module/cell. Check if the module ports or technology library ports
are specified correctly.
STRUCT-137 Output ports of an instance cannot
be driven by supply0/supply1.
Check port connectivity of an instance.
STRUCT-138 Given top level module not found. Select correct module name using -top option in
structural mode.
STRUCT-139 Recursive module instantiation is
not supported.
Struct: Error during Verilog Netlist Parsing/Elaboration.
STRUCT-141 Could not connect positional port. Struct: Error during Verilog Netlist Parsing/Elaboration.
STRUCT-143 Port range of slice port present in
module interface not falling in
range in corresponding port
declaration.
Struct: Correct the slice range.
STRUCT-144 Port direction of slice port present
in module interface mismatches
that of its corresponding port
declaration .
Struct: Correct the slice direction.
STRUCT-145 A module with slice or complex
ports instantiated with named
connections.
Struct: Remove the formal name association from
instantiation.
STRUCT-146 The top module in the user netlist
has been replaced by a library cell
since the attribute
'hdl_use_techelt_first' set to TRUE
in structural flow (read_netlist).
Struct: Remove the attribute setting
hdl_use_techelt_first.
STRUCT-148 Illegal positional port association
for instantiation of cell with power
and ground pins.
Struct: Only named port association is allowed for
instantiations of cells with power and ground pins.
STRUCT-149 Could not resolve reference. Use 'set_attribute hdl_error_on_blackbox false /' to
cause a warning, rather than an error, when a blackbox
is found.
TCF-1 Found error while parsing TCF file. The most common reasons for a parse error are
mismatched delimiters or missing quotes.
TCF-3 Could not open specified TCF file. Ensure that the TCF file exists in the current path.
TCF-9 Found error while parsing TCF
header.
The 'type' value must be a double quoted string with
one of the following values: 'master', 'slave' or 'regular'.
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Error Messages
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TCF-10 Unable to find the corresponding
master TCF file.
Read the corresponding master TCF file first.
TCF-12 Invalid instance(s) specified. TCF top not found. Provide an unambiguous path with
-tcf_instance option.
TCF-13 Invalid instance(s) specified. Design top not found. Provide an unambiguous path
with -instance option.
TIM-30 Could not perform a meaningful
RTL delay analysis.
Make sure that your library contains at least one
inverter and one 2-input library cell to create timing
models for unmapped gates in the netlist. A library cell
is considered not usable if it has a 'dont_use' or a
'dont_touch' attribute set to 'true' in the .lib files. In this
case, use 'set_attribute preserve false <libcell>' and
'set_attribute avoid false <libcell>' to make the cell
usable.
TIM-31 Not a hierarchical instance. Specify an instance that is hierarchical.
TIM-32 Atleast one option should be used. Either of -top or -instance should be used.
TIM-33 Cannot use both option at the
same time.
Either of -top or -instance should be used.
TIM-103 Cannot remove a clock object. This clock object cannot be removed because it is
generated by an instance of a library cell. Remove the
instance that generates this clock to delete this clock.
TIM-119 The value specified for the
'max_transition' attribute is overly
restrictive for this technology.
Set a larger value for the 'max_transition' attribute.
TIM-122 'ideal_driver' not valid for this pin. The 'ideal_driver' attribute is supported for drivers only.
TIM-125 Invalid port
'external_non_tristate_drivers'
attribute value.
Specify a value greater than or equal to zero.
TIM-127 'ideal_network' not valid for this
pin.
The 'ideal_network' attribute is supported for drivers
only.
TIM-145 Instance/libarc mismatch. Use the 'find' command to get the libarc objects for the
instance.
TIM-233 Invalid path specification. A
'through' object is invalid.
The following types of objects may be used in a
'through' path specification: sequential instances and
their pins, mapped combinational instances and their
pins, ports, hierarchical pins, unmapped instance pins
that are timing startpoints or endpoints.
TIM-234 Invalid path specification. A 'to'
object is invalid.
The following types of objects may be used in a 'to' path
specification: external delays, clocks, output ports,
sequential instances, and pins which are timing
endpoints.
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TIM-235 Invalid path specification. A
'capture_clock_pins' object is
invalid.
Only clock pins of sequential instances may be used in
a 'capture_clock_pins' path specification.
TIM-290 Timing mode creation error. Use the 'create_mode -name' command to create a
unique timing mode name.
TIM-291 Timing mode creation error. Failed to create timing mode because a clock,
exception, or external delay exists in the timing
directory. Remove the object using the 'rm' command
before creating modes.
TIM-295 Timing mode creation error. Cannot create a timing model outside of CPF files in a
CPF flow, modify your CPF files accordingly.
TIM-302 Incompatible objects. The objects belong to different designs or timing
modes.
TIM-303 Invalid path specification. A 'from'
object is invalid.
The following types of objects may be used in a 'from'
path specification: external delays, clocks, input ports,
sequential instances, and pins which are timing
startpoints.
TIM-305 Unspecified mode. In multi-mode timing, a mode must be specified using
the '-mode' option if an exception does not include an
implicit reference to its mode. A reference to a mode is
implicit if a clock or external delay object is used as an
argument to the '-from', '-through', '-to', or other similar
option.
TIM-310 At least one from point, through
point, or to point must be specified.
Specify at least one from point, through point,or to
point.
TIM-319 Invalid timing exception attribute
value.
The specified value for the 'attribute name' can only
contain path_adjust objects.
TIM-323 Only lower priority exceptions may
be set here.
The 'priority' attribute indicates the priority of
exceptions.
TIM-324 The 'user_priority' attribute cannot
be set on 'path_adjust' exceptions.
Use the attribute 'precluded_path_adjusts' to control
'path_adjust' exception priorities.
TIM-330 Ungrouping this instance would
change the timing exception
requirements of this design.
Before you ungroup an instance, set the
'ui_respects_preserve' attribute to 'false' to allow netlist
editing commands to modify preserved instances.
TIM-331 Rise and fall pin transitions are not
supported for timing exceptions in
unmapped logic.
Instantiating a mapped gate instead and then applying
the exception on the mapped gate is one possible
workaround.
TIM-335 Unspecified mode. In multi-mode timing, if the '-clock' option is not
specified when using the 'external_delay' command,
then the '-mode' option must be specified.
TIM-600 Unused message. Unused message.
TIM-602 Unused message. Unused message.
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Error Messages
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TSY-26 Cannot use reserve words as port
names.
Ensure that all port names are not reserved words (i.e.
in BsdlReservewords list).
TSY-32 Top module name cannot be
identified.
The command requires that a design is loaded and that
a unique top module name can be identified and
currently, one cannot be. One option is to specify the
global keyword 'TOP_MODULE_NAME' in the speclist
in order to generate a proper BSDL file and one has not
been specified.
TSY-56 Unable to identify and/or
understand iocell on TAP port.
Error during iocell identification for the specified TAP
port. The iocell for a TAP port is essential for the
boundary scan logic to be inserted correctly.
TSY-57 Did not find the correct iocell
connected to the tap port.
For a TAP port, it is essential to have an iocell, of the
correct cell type, connected to it. Specifically, the
correct pad cell types for JTAG input ports (tdi, tms, tck,
trst) are: input only or bidir I/O whose pad cell is
configured into input mode during test. The correct pad
cell types for the JTAG tdo port are: three-state, or bidir
I/O whose pad cell is configured into output mode
during test. If the pad cell type is incorrect, you must
edit the pad cell type in the netlist. If the iopad cell is
missing, you can specify the pad cell to be inserted
during boundary scan using the 'set_attribute cell
designs/<designName>/boundary_scan/jtag_ports/
<portName>' command.
TSY-59 TAP port of required type not
found.
If a TAP port is not present in the design or has not
been specified through the inputs (command-line or
IOSpecList) then Boundary Scan connections will be
incomplete since there is no way of knowing which
iocell to use for that port. Hence the TAP port name and
corresponding iocell to be instantiated in the design
must be specified in the input IOSpecList. Specify the
TAP port information in either the input IOSpecList or
the command line and rerun the insert_dft
boundary_scan command.
TSY-60 Incorrect iocell for TAP port. TAP ports need to have a specific type of iocell on
them. A TDO TAP port must have a tri-state iocell on it,
whereas the other TAP ports must have an iocell
capable of input mode. Specify the correct iocell on the
specified TAP port in the input IOSpecList and rerun the
insert_dft boundary_scan command.
TSY-61 Port connects to non-pad pin. Every functional port on the design must have an iocell
connected to it and this iocell must then be connected
to the functional logic. The specified port is connected
to a pin on the iocell that does not have the liberty
attribute is_pad=true. Ensure the iocell pin connected
to the port has the liberty attribute is_pad=true on it.
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TSY-63 Boundary scan processing
terminated.
To continue, you must either exclude the ports in Table
2 by using the '-exclude_ports' option of the 'insert_dft
boundary_scan' command, or they must be excluded
by specifying the 'bdy_use=none, sys_use=none,
test_use=none' keywords for each port in the input
IOspeclist file, or you must correct the errors for these
ports in the design.
TSY-100 Cannot insert the JTAG_Macro. To insert the JTAG_Macro, set the 'preserve' attribute
on the instance to 'false' using the 'set_attribute'
command.
TSY-101 Did not specify a custom cell
directory.
Rerun the 'insert_dft boundary_scan' command and
specify a custom boundary cell directory, in which the
Verilog RTL files for the custom boundary cells reside,
using the '-custom_cell_directory' option.
TSY-102 Cannot insert the JTAG_Macro. To insert the JTAG_Macro, set the 'preserve' attribute
on the parent subdesign to 'false' using the
'set_attribute' command.
TSY-103 Could not write out BSDL file. Boundary scan logic is inserted using the 'insert_dft
boundary_scan' command, while a standalone
JTAG_MACRO is inserted using the 'insert_dft
jtag_macro' command.
TSY-104 Could not define test signal as
compliance enable signal.
Only dedicated test or functional-only ports can be
defined as a compliance enable signal.
TSY-105 TAP port redefined with different
port.
The TAP port should have the same top level port for
each type if redefined.
TSY-108 Could not insert the
'JTAG_MACRO'.
To insert the 'JTAG_MACRO' logic, an empty module
description (with port definitions) must be read for the
JTAG_MACRO design. Additionally, the empty module
description cannot be viewed as a logic abstract model.
Hence, the root-level attribute
'infer_unresolved_from_logic_abstract' must be set to
'false' prior to reading in the RTL.
TSY-109 Could not find a mandatory pin on
the 'JTAG_MACRO' instance.
Since an instance of a JTAG_MACRO exists in the
design, the RC-DFT engine expects that it has all of the
required pins that would exist for an RC-generated
JTAG Macro built with the mandatory JTAG instructions.
TSY-365 The iocell on the TDO TAP port
must be either BIDIR or
OUTPUT3.
Specify a BIDIR or an OUTPUT3 iocell on the TDO TAP
port in the input IOSpecList and rerun the insert_dft
boundary_scan command.
TSY-366 An iocell has not been found on
the TDO TAP port.
There must be an iocell on the TDO TAP port. Specify a
BIDIR or an OUTPUT3 iocell on the TDO TAP port in
the input IOSpecList and rerun the insert_dft
boundary_scan command.
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TSY-367 Unable to determine the polarity of
the enable pin on an iocell.
Specify the polarity of the enable pin on BIDIR or
OUTPUT3 cells by using the IOSpecList keyword
'iocell_enable'. Prefix the value with the '!' character to
specify active low logic.
TSY-368 Enable pin for iocell has different
polarities for different ports of the
design.
All ports controlled by the enable port must have the
same enable polarity. Ensure that all ports controlled by
the enable port have the same enable polarity.
TSY-369 Unable to determine hookup pin. The specified pin on the JTAG_MACRO needs to be
connected to a top level port. Either the top level port
does not have an iocell, or it is a complex iocell whose
pins need to be defined in the speclist using the
IOCELL_INPUT, IOCELL_OUTPUT, etc. keywords.
Ensure that the top level port exists, has a iocell on it,
and the iocell is understood by the command.
TSY-370 The specified pin on the
JTAG_MACRO needs to be
connected to a top level port.
Even though the top level port has the specified
keyword, it also needs to satisfy the specified condition.
Since the condition is not satisfied the connection will
not be made. Ensure that the top level port exists, has
the specified keyword and satisfies the specified
condition.
TSY-371 The specified pin on the
JTAG_MACRO needs to be
connected to a top level port that
satisfies the specified condition.
There is no port in the design that satisfies the specified
condition. Hence the connection is not made. Ensure
that a port exists in the IOSpecList satisfying the
specified condition.
TSY-372 Unable to determine core side
iocell hookup pin.
The specified pin on the JTAG_MACRO needs to be
connected to a top level port. Either the top level port
does not have an iocell, or it is a complex iocell whose
pins need to be defined in the IOSpecList using the
IOCELL_INPUT, IOCELL_OUTPUT, etc. keywords.
Ensure that the top level port has a iocell on it, and the
iocell is understood by the command.
TSY-373 Could not locate required port on
the design.
The specified pin on the JTAG_MACRO needs to be
connected to the specified top level port. But there is no
port specified in the speclist. Hence the connection is
not made. Ensure that the port is specified in the
speclist for the connection to be made.
TSY-374 Unable to determine core side pin
for JTAG port.
The specified pin on the JTAG_MACRO needs to be
connected to the specified pin type on the TAP port. But
the command is unable to trace through the design and
identify the correct pin on the iocell. This could be
because the iocell is not present in the design or it is a
complex iocell whose pins need to be identified using
the IOCELL_INPUT, IOCELL_OUTPUT, etc. global
keywords in the speclist. Ensure that the iocell exists in
the design and its pins are specified in the speclist if
necessary.
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TSY-376 The 'JTAG_MACRO' instance
contains pins that are not on the
module.
The 'JTAG_MACRO' instance cannot have more pins
than the module. If the module has more pins than the
instance, then the RC-DFT engine will add the
additional pins to the instance.
TSY-377 A mandatory pin was not found on
the boundary cell.
The specified pin needs to be present on the boundary
cell. The list of pins that need to be present on the
specified boundary cell can be found in the user guide.
Note that the boundary cell can have more pins on it
than needed. Update the Verilog for the boundary cell
to ensure that the pin exists on the boundary cell.
TSY-378 There was an error while
elaborating the boundary cell.
Errors were encountered while elaborating the
specified boundary cell. If needed, fix the errors by
updating the Verilog for the boundary cell and rerun the
command.
TSY-379 Could not load custom boundary
cell.
To proceed, ensure that the Verilog file for the custom
boundary cell exists in the custom boundary cell
directory prior to inserting the boundary-scan logic.
TSY-380 Pin JTAG_POR on the
JTAG_MACRO could not be
located.
Ensure that the JTAG_POR pin exists on the
JTAG_MACRO if a power-on-reset is being used to
reset the TAP controller.
TSY-381 An unsupported I/O cell has been
detected.
I/O cells with multiple pad pins are not supported by the
boundary scan insertion engine. To continue with
boundary scan insertion, you must specify the port as
an exclude port using the '-exclude_ports' option to the
'insert_dft boundary_scan' command.
TSY-383 An instance named
JTAG_MODULE has been
detected.
The instance name 'JTAG_MODULE' has been
reserved for instances of a JTAG_MACRO. Define this
instance as a pre-instantiated JTAG_MACRO in the
design by using the 'define_dft jtag_macro' command.
TSY-384 Support for features outside the
scope of the IEEE 1149.1
architecture have been requested.
To specify an IEEE 1149.6 boundary-scan architecture,
either change the design-level attribute 'boundary_type'
to 'IEEE_11496' or pass the '-boundary_type
IEEE_11496' option to the 'insert_dft boundary_scan'
command. For IEEE 1149.1 boundary-scan design, set
the 'aio_pin' attribute on all ports in the 'jtag_ports' vdir
to 'false'.
TSY-385 Incorrect IEEE 1149.6 input port
specification.
If the desired behavior is to have an ACTR boundary
cell on the port, then there must be a 'tr_cell' attribute
on the port in the 'jtag_ports' vdir and the 'sys_use'
attribute must be either 'input' or 'clock' or 'bidir'.
TSY-386 Missing 'tr_bdy_in' specification. If the intent is to insert a BC_11496_ACTR boundary
cell on this port, set the 'tr_bdy_in' attribute to the
appropriate 'instance/pin' value for the port in the
'jtag_ports' vdir. If there is no TR cell associated with
the port, set the 'tr_cell' attribute to 'NULL'.
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TSY-387 Incorrect TR cell specification. Ports with a tr_cell must have a 'sys_use' attribute value
of either 'input' or 'clock' or 'bidir' in the 'jtag_ports' vdir.
TSY-388 Required pin is missing. To perform boundary-scan insertion, the pins
associated with the '-mode_a, -mode_b, -mode_c,
-bsr_shiftdr, -bsr_clockdr, -bsr_updatedr' options to the
'define_dft jtag_macro' command must be specified. To
perform IEEE 1149.6 boundary-scan insertion, the pins
associated with '-dot6_acdcsel, -dot6_preset_clock,
-dot6_trcell_enable, -dot6_acpulse' options will
additionally have to be specified to 'define_dft
jtag_macro'. Either remove the user-defined
JTAG_Macro, and then redefine it and specify the pins
for the missing options, or use the 'set_attribute'
command to specify the missing pins on the
JTAG_Macro object.
TSY-389 Test receiver cell is not embedded. The 'insert_dft boundary_scan' command expects that
the test receiver cell is embedded within the I/O cell
macro. The only supported value for the 'tr_cell'
attribute is 'embedded'.
TSY-390 There is no net on which to insert
boundary cell.
Ensure that the insertion point for all boundary cells are
connected to some logic in the netlist.
TSY-392 JTAG port found. JTAG ports with standard pin names 'tdi', 'tdo', 'tck',
'tms', and 'trst' that exist in the design or are created
using an IOSpeclist flow will prevent the creation of new
ports using the '-create_ports' option to the 'insert_dft
jtag_macro' command.
TSY-393 Could not trace through the pad
logic connected to the TRST port.
Use the 'configure_pad_dft' command to configure the
pad into input mode. The core-side pin of the pad logic
needs to evaluate to either a buffer or inverter function
of the PAD pin in test mode. If the tool cannot identify
the from-core, to-core, and three-state enable pins of
the libcell, you can specify these pins using the
'user_from_core_data', 'user_to_core_data', and
'user_from_core_enable' attributes respectively.
TSY-395 Identified an invalid boundary-scan
cell hookup pin.
Ports feeding non-differential I/O cells with multiple PAD
pins must have unique boundary-scan cell hookup pins.
To proceed, remove the 'jtag_ports' vdir and then
specify these pins using the instance-level
'user_from_core_data', 'user_to_core_data', and
'user_from_core_enable' attributes. Additionally,
differential PAD pin pairs must be identified using the
'user_differential_negative_pin' attribute.
TSY-400 Cannot insert boundary-scan cell. Ensure that such an instance exists in the design.
TSY-401 Cannot insert boundary-scan cell. To use this location, set the attribute preserve or
inherited preserve of this object to false or set the root
level attribute ui_respects_preserve to false.
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TSY-460 Could not write out IOSpecList file. Boundary scan information can be defined by running
the 'insert_dft boundary_scan' command with the
'-preview' option, by reading in an IOSpecList input file
using the 'read_io_speclist' command, and by defining
the JTAG instruction information using 'define_dft
jtag_instruction' and 'define_dft
jtag_instruction_register' commands.
TSY-464 The specified global does not have
a keyword and value specified with
it.
A global keyword must have both a keyword and a
value specified and they must be separated by an '='
sign. Ensure that all globals have both a keyword and a
value separated by an '=' sign.
TSY-465 Incorrect speclist line. A speclist must consist of either ports, global variables
or BSDL_INLINE|JTAG_INLINE|WRAPPER_INLINE
sections. Ensure that all globals, ports and
BSDL_INLINE|JTAG_INLINE|WRAPPER_INLINE
sections are specified in the appropriate formats.
TSY-500 The BSDL abstract was not
specified in the correct format.
Respecify the BSDL abstract in the correct format.
TSY-501 The boundary-scan segment
definition is incomplete.
Specify the BSDL abstract using the '-bsdl_file' option.
TSY-502 The boundary-scan segment
definition includes an incomplete
differential_pair specification.
Specify all differential pin pairs on the boundary-scan
segment, with the positive leg of the pair followed by the
negative leg.
TSY-503 Reference made to undefined
boundary-scan segment.
Ensure that a boundary-scan segment specified for a
port has been defined using the 'define_dft
boundary_scan_segment' command.
TSY-504 Pin specified in BSDL abstract file
was not found on boundary-scan
segment.
Ensure that pin names specified in the BSDL abstract
file are present on the module, instance, or libcell on
which the boundary-scan segment was defined.
TSY-505 Pin specified on boundary-scan
segment does not connect to a
top-level port.
Ensure that the pins specified in the BSDL abstract and
the differential pairs specification for a boundary-scan
segment connect to a top-level port.
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TSY-506 Functional intent of a port
connected to a boundary-scan
segment cannot be determined.
If the port is the negative leg of a differential port pair,
you must define the boundary-scan segment by
identifying the segment-specific pins associated with
the differential port pair using the '-differential_pairs'
option. To proceed, remove the boundary-scan
segment and redefine the segment to also include the
differential pin pairs by specify the '-differential_pairs'
option to the 'define_dft boundary_scan_segment'
command. Alternatively, you can set the 'differential'
attribute for the port associated with the positive leg of
the differential port pair with its corresponding
negative-leg port. This is done using the 'set_attr
differential <negativeLegPortName> dft/
boundary_scan/jtag_ports/<positiveLegPortName>'.
Afterwards, rerun boundary scan insertion using the
'insert_dft boundary_scan' command.
TSY-559 JTAG instruction register is not
defined.
Boundary-scan and MBIST logic insertion require the
JTAG instruction register to be defined. Use the
'define_dft jtag_instruction_register' command to define
the instruction register.
TSY-560 JTAG instruction is not defined. To use an existing JTAG_MACRO subdesign, the
following mandatory instructions 'extest', 'sample',
'preload', and 'bypass' must be defined for an IEEE
1149.1 compliant boundary-scan design. The
'extest_pulse' and 'extest_train' instructions must also
be defined for an IEEE 1149.6 compliant
boundary-scan design. If the existing JTAG_MACRO
was built with custom or user-defined instructions,
these instructions should also be defined. You must first
define the JTAG instruction register using the
'define_dft jtag_instruction_register' command, prior to
defining the JTAG instructions using the 'define_dft
jtag_instruction' command.
TSY-900 Cannot write out BSDL for the
design.
There are no jtag ports and/or jtag instructions defined.
Define the jtag ports and jtag instructions using the
insert_dft boundary_scan and define_dft
jtag_instruction commands respectively. Alternatively
read in a IOSpecList with the required information and
then rerun the write_bsdl command.
TUI-6 A Tcl command has encountered
an error.
Check the syntax and rerun.
TUI-7 Tcl 'set' command has
encountered an error.
Check the syntax and rerun.
TUI-8 Tcl interpreter encountered an
invalid command.
Check the syntax and rerun.
TUI-9 Tcl command has wrong number
of arguments.
Check the syntax and rerun.
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TUI-10 No designs are available. A design
must first be read in and
elaborated.
A design must first be read in with 'read_hdl' command
and elaborated with 'elaborate' command.
TUI-11 Value must not be negative. Specify a non-negative number.
TUI-12 Value must be greater than zero. Specify a positive number.
TUI-13 Value is too large. Specify a smaller number.
TUI-14 One of the following options must
be specified.
At least one option must be specified.
TUI-15 Only one of the following options
may be specified.
Only one option can be specified.
TUI-16 Invalid attribute value. To see the usage/description for this attribute, type
'set_attribute -h <attr_name> *'.
TUI-17 Multiple designs are available.
Specify the design you want to
use.
Specify a design by using the cd command to change
to that design's directory or specify the design as an
argument for the command.
TUI-18 A badly formed Tcl list was
specified.
Consult a Tcl reference for information about Tcl lists.
TUI-19 The object for this attribute is
missing or invalid.
To see the usage/description for this attribute, type
'set_attribute -h <attr_name> *'.
TUI-20 Invalid attribute name. Use 'get_attribute -h' to see a list of all valid attributes.
TUI-21 Attribute not set. Cannot set the attribute value.
TUI-22 The 'map_to_mux' attribute can
only be set on a binary mux
instance.
Use the 'map_to_mux' pragma in the HDL to force the
binary mux implementation.
TUI-23 Failed to parse attribute string. To see the usage/description for this attribute, type
'set_attribute -h <attr_name> *'.
TUI-24 The data value for this attribute is
invalid.
To see the usage/description for this attribute, type
'set_attribute -h <attr_name> *'.
TUI-26 The attribute is read-only. Cannot set or reset read-only attributes.
TUI-27 The attribute name is ambiguous. To see the usage/description for this attribute, type
'set_attribute -h <attr_name> *'.
TUI-33 A flagged command option was
incorrectly repeated.
Check the command usage and correct the input to the
command.
TUI-35 The given Tcl list is the wrong
length.
Consult a Tcl reference for information about Tcl lists.
TUI-36 A null string command option was
found.
This command only accepts non-null string values for
the indicated option.
TUI-38 Invalid object for attribute. To see the usage/description for this attribute, type
'reset_attribute -h <attr_name> *'.
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TUI-39 Invalid or missing object for the
attribute.
To see the usage/description for this attribute, type
'get_attribute -h <attr_name> *'.
TUI-40 Invalid attribute name. Use 'set_attribute -h' to see a list of all valid attributes
that can be set.
TUI-41 Invalid attribute name. Use 'reset_attribute -h' to see valid attributes.
TUI-44 Bad object type for attribute. A wrong object type was specified for accessing the
attribute.
TUI-45 Multiple object types for attribute. Only one must be specified.
TUI-46 Bad data type for attribute. The wrong data type was specified for setting the
attribute value.
TUI-47 Duplicate name for attribute. Another attribute already exists with the same name.
Choose a different name.
TUI-48 The attribute or the value for this
attribute is not allowed at this
moment.
Cannot change the value of the attribute.
TUI-49 The Tcl proc option has the wrong
number of arguments or is
undefined.
The Tcl proc must have the correct number of
arguments and be defined before calling the
'define_attribute' command.
TUI-50 Bad path. A bad path was supplied to a command.
TUI-52 Cannot remove object. Use 'rm -help' to see the list of valid removable object
types.
TUI-53 Cannot rename/move object. Only certain object-types allow renaming.
TUI-56 Directory stack is empty. 'popd' command cannot be issued when the
directory-stack is empty.
TUI-60 A required argument is missing for
a flagged command option.
Check the command usage and correct the input to the
command.
TUI-61 A required object parameter could
not be found.
Check to make sure that the object exists and is of the
correct type. The 'what_is' command can be used to
determine the type of an object.
TUI-62 A single object was expected, but
multiple objects were found.
Use the 'find' command to narrow the list down to a
single object.
TUI-63 A given option flag matches
multiple possibilities.
A flag option can be abbreviated as long as it does not
match multiple possibilities. Spell out more of the
desired flag so that it is unique.
TUI-64 A command argument did not
match any of the acceptable
command options.
Check the command usage and correct the input to the
command.
TUI-65 The file specified for redirection
could not be opened for writing.
Check to see whether the directory exists and is
writable.
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TUI-66 A command argument is of the
wrong type.
Check the command usage and correct the input to the
command.
TUI-68 A command argument overflows
the given type.
Check the command value and correct the input to the
command.
TUI-71 Failed to rename an object
because the target name is
already in use.
Use 'mv -flexible' to allow RC to choose a
non-conflicting name or rename the object with the
desired name so that the target name is available.
TUI-76 A super-thread server was not
found.
Specify super-thread servers that do actually exist.
TUI-80 The command is not licensed. Restart the tool with the appropriate license.
TUI-81 The attribute is not licensed. Restart the tool with the appropriate license.
TUI-87 The 'mv' command only allows
destination name to contain '/' if
-slash_ok is specified.
Either use -slash_ok, or use a name without the '/'
character.
TUI-90 Invalid probability value. The probability value cannot be less than 0 or greater
than 1.
TUI-91 Invalid toggle rate value. The toggle rate value cannot be less than 0.
TUI-100 A command argument is badly
formatted.
Check the command option formatting and correct the
input to the command.
TUI-110 From point is not a timing
startpoint.
Timing startpoints are normally input ports of a top-level
design or clock pins of sequential elements.
TUI-111 To point is not a timing endpoint. Timing endpoints are normally output ports of a
top-level design or d pins of sequential elements.
TUI-112 Command requires synthesized
design.
Use the 'synthesize (-to_rtl|-to_generic|-to_mapped)'
command to synthesize the design. Then retry the
command.
TUI-200 File redirection failed. This
command does not support file
redirection.
The 'redirect' command can be used instead. Try
'redirect -h'.
TUI-201 No objects were specified. At least one object must be specified.
TUI-202 A required argument was not
specified.
Rerun the command specifying all required arguments.
TUI-203 A filename was not specified.
Rerun the command specifying a
filename.
Rerun the command specifying a filename.
TUI-204 An invalid option was specified. Rerun the command after checking the option names.
TUI-206 The specified object cannot be
removed.
Verify that the intended object was specified correctly.
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TUI-209 Cannot preserve partially
unmapped or empty design or
subdesign.
You can only change the value of the 'preserve'
attribute of a fully mapped non-empty design or
subdesign to one of the following values: true,false,
size_ok, delete_ok, or size_delete_ok.
TUI-210 Cannot preserve unmapped leaf
instance.
You can only change the value of the 'preserve'
attribute of mapped, non-hierarchical instances to one
of the following values: true, false, size_ok, delete_ok,
or size_delete_ok.
TUI-214 Cannot preserve partially mapped
hierarchical instance.
You can only change the value of the 'preserve'
attribute of fully mapped, hierarchical instances to one
of the following values: true, false, size_ok, delete_ok,
or size_delete_ok.
TUI-219 The mode specified does not
match the design specified.
The mode specified with the '-mode' option must be
under the design specified with the clock sources or
'-design' option.
TUI-221 Multiple designs are available.
Specify the design you want to use
by either using the cd command to
go to the design directory or use
the define_clock ?define option.
You can specify a design by cd'ing into that design's
directory, or by using the -design option of define_clock.
TUI-222 Clock and port/pin objects must
belong to the same design.
Specify a clock in the same design as the port/pin.
TUI-223 Clock sources specified are in
different designs. Specify clock
sources in a single design.
Only specify clock sources in a single design.
TUI-225 Clock sources do not belong to the
design specified.
If a design is specified using the -design option, it has
to match the one that the clock sources belong to.
TUI-226 A mode needs to be specified. In multi-mode timing, a mode must be specified using
the -mode option.
TUI-227 Specified cost group name change
is not permitted. The system
default groups cannot be replaced
by user cost groups.
System default group(s) cannot be replaced by user
cost groups.
TUI-228 The -paths option argument was
not created using the
specify_paths command.
The -paths argument should be created using the
specify_paths command. This is best accomplished by
embedding the specify_paths command using the Tcl []
notation. For example, 'path_disable -paths
[specify_paths -to out]'. Or to specify paths using the
paths attribute of a timing exception, 'report timing
-paths [eval [get_attribute paths dis_5]]'.
TUI-229 Cannot copy attributes. Attributes can only be copied between sequential
instances, pins of sequential instances, ports or
subports; both source and destination objects must
reside in the same level of hierarchy.
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Message Reference for Encounter RTL Compiler
Error Messages
May 2013 254 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
TUI-230 All instances do not share the
same sub-design.
Use the 'subdesign' attribute on each instance to see
what subdesign the instance refers to.
TUI-231 The specified instance is not
hierarchical. Either use the
command/attribute to make the
selected instance hierarchical or
specify a different instance that is
hierarchical.
The 'edit_netlist dedicate_subdesign' command cannot
operate on leaf instances.
TUI-232 Cannot ungroup preserved object. Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
TUI-233 Cannot group within preserved
module.
Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
TUI-234 Not all instances belong to the
same hierarchy.
The 'edit_netlist group' command can only group
instances contained within the same hierarchy.
TUI-235 An object cannot be connected to
itself. Pins, ports, and sub-ports
can only be connected to other
objects.
Pins, ports, or subports may only be connected to other
objects.
TUI-236 Objects that are in different levels
of the hierarchy cannot be
connected to each other. Pins,
ports, and sub-ports can only be
connected to objects in the same
level of the design hierarchy.
Pins, ports, or subports may only be connected to
objects in the same level of design hierarchy.
TUI-237 The specified objects are already
connected to each other. Try
connecting to another object.
Only objects not yet connected can be connected.
TUI-238 Connection failed. The requested
connection would require
connecting a logic constant to
another driver.
If a net is driven by a logic constant, it cannot be
connected to a net driven by another driver.
TUI-239 Instantiation failed because it
would have created a hierarchical
loop. A sub-design cannot
instantiate a sub-design that is
already instantiated.
A subdesign may not instantiate a subdesign in which it
is instantiated itself.
TUI-240 Modification failed because the pin
affected is preserved.
Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
TUI-241 The connection attempted was
within an unresolved reference.
The two given pins cannot be connected to each other.
TUI-242 Cannot dedicate fully preserved
module.
Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
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Error Messages
May 2013 255 Product Version 12.2
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TUI-243 Modification failed because the
parent sub-design has a preserved
instantiation.
Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
TUI-244 Failed to remove instance because
it is preserved.
Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
TUI-245 Failed to resize instance because
it is preserved.
Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
TUI-248 Modification failed because the net
affected is preserved.
Use the root attribute 'ui_respects_preserve' if you want
to override this behavior.
TUI-250 Multiple external delays have to be
created and -name option was
specified.
Run the command without the -name option.
TUI-251 At least one of the specified pin is
not compatible for defining
external delays.
External delays can be defined on hierarchical or
top-level ports and pins with the break_timing_paths
attribute set and timing startpoints or endpoints.
TUI-252 A design already exists with that
name. Specify a unique design
name.
Every design must have a unique name. Use 'ls [find /
-design *]' to see design names.
TUI-254 The instance specified is not
hierarchical. Specify a hierarchical
instance.
The 'subdesign' attribute indicates what subdesign an
instance refers to. Only instances that refer to
subdesigns may be used here.
TUI-256 Invalid primitive function. Use the
-help option for the command to
see valid function types.
Use the -help option of the command to view the valid
function types.
TUI-257 An input number was not specified
for the function type. Use the
-inputs option to specify the
number of inputs to build.
Use the -inputs option to provide the number of inputs
to build.
TUI-258 The requested function cannot be
built using the given number of
inputs.
Specify the correct number of inputs (or do not specify
the number).
TUI-259 The required minimum of 2 inputs
was not included with the function
type. Rerun the command with an
input count greater than one.
Specify an input count greater than 1. Using the - option
to specify the input count.
TUI-260 The number of requested inputs is
too high.
The function may be implemented by breaking it down
into smaller primitives.
TUI-261 The naming style is not legal. The string must contain substrings '%s' and '%d' in that
order.
TUI-262 Connections to internal pins are
not allowed.
The 'edit_netlist' command cannot be used to connect
internal pins.
TUI-263 Cannot create instance inside
unresolved reference.
The 'edit_netlist' command cannot be used to create a
new instance inside an unresolved instance.
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Error Messages
May 2013 256 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
TUI-264 Cannot create new instance
because the library cell to be
instantiated does not match the
library domain of the parent
(sub)design.
Pick up the library cell from the library domain of the
parent (sub)design and try it again.
TUI-265 Cannot ungroup instance because
it is a library domain boundary.
The command cannot be used to ungroup library
domain boundary instances.
TUI-270 Instance incompatible with
specified libcell.
Specify a different library cell.
TUI-272 A net that is connected to a port or
subport cannot be renamed.
Instead you can rename the connected port or subport.
TUI-274 Cannot reset 'unresolved' attribute
on instance.
Once an instance has the 'unresolved' attribute set to
'true' it cannot be reset to 'false'.
TUI-275 The sequential members naming
style is not legal.
The string must contain substrings '%s' and '%d' in that
order.
TUI-282 The given license name is not
valid.
Choose one of the valid license names instead.
TUI-283 The requested license cannot be
checked in.
The option licenses cannot be checked in once
checked out.
TUI-285 The requested license is not
currently checked out.
Only checked out licenses can be checked back in.
Use the 'license list' command to see which licenses
you have checked out.
TUI-286 Invalid format for specified Beta
feature.
Choose a valid Beta feature value.
TUI-289 Objects that are in different
designs cannot be connected to
each other. Pins, ports, and
sub-ports can only be
(hierarchically) connected to
objects in the same design.
Pins, ports, or subports may only be (hierarchically)
connected to objects in the same design.
TUI-290 Non-uniquified objects cannot be
hierarchically connected. Pins,
ports, and subports can only be
hierarchically connected if they are
uniquified.
Pins, ports, or subports may only be hierarchically
connected if they are uniquified.
TUI-291 Specified path group is not
permitted. The cost group and the
path specifications have different
netlists.
The cost group and the path specifications should
belong to the same design.
TUI-292 Unsupported logic function. The 'edit_netlist' command cannot be used to create a
complex primitive.
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Error Messages
May 2013 257 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
TUI-293 Cannot disconnect a constant pin. The 'edit_netlist' command cannot be used to
disconnect a constant pin. Try disconnecting the loads
of the constant pin.
TUI-300 (sub)port does not belong to
specified design or hierarchical
instance.
Only (sub)port in specified design or hierarchical
instance can be used.
TUI-303 The environment cannot be
derived because the instance is an
unresolved reference.
The 'derive_environment' command cannot operate on
unresolved references.
TUI-304 Cannot create IOPT partition. The 'iopt_partition' command can only operate on
mapped instances belonging to the same hierarchy and
library.
TUI-500 Invalid command. See the
Command Reference for valid
commands.
Using help command to view a list of all valid
commands.
TUI-505 A unique object is required, but
multiple objects were found.
Use the 'find' command to select only one of the
objects.
TUI-506 The requested object or objects
could not be found.
Either the requested object does not exist or it is of the
wrong type. The 'find' command may be helpful in this
situation.
TUI-600 Invalid speed grade. Valid speed grades are: 'very_fast', 'fast', 'medium',
'slow', and 'very_slow'.
TUI-601 Invalid user sub architecture. Valid sub architectures are: 'booth' and 'non_booth'.
TUI-608 Invalid instance for setting sop
group instance.
Instance must be a case box.
TUI-698 Unused. Unused.
TUI-711 Cannot set library domain without
loading libraries.
Load the libraries into the library domain first.
TUI-713 Cannot set library domain. First set the 'preserve' attribute on the design or
subdesign or instance to 'false'. Then set the
'library_domain' attribute again.
TUI-720 Value for all modes must be given. The value in all modes in the netlist must be given.
TUI-723 No timing mode specified. When performing DVFS synthesis, the '-mode' option
must be given to select the mode to report timing.
TUI-728 Cannot change library domain. Only timing model instances can have a library domain
different from their parent instance. All other
non-hierarchical instances inherit the library domain of
their parent instance.
TUI-729 Cannot set a library domain on
hierarchical instances.
The library_domain attribute can be set only on timing
model instances. To change the library domain of a
hierarchical instance, set the 'library_domain' attribute
on its corresponding subdesign.
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Error Messages
May 2013 258 Product Version 12.2
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TUI-732 Cannot change library domain of
preserved timing model instance.
The instance or the instance's library cell is preserved.
To maintain the intention of preventing optimization of
the instance but allowing to change the library domain
of the instance, set the 'ui_respects_preserve' attribute
to 'false'. Then set the 'library_domain' attribute again
for the timing model instance.
TUI-736 No default mode specified. Default mode is required when
RTL_Compiler_Low_Power_Option license is not
available to do report timing.
TUI-741 The mode specified does not
match the current design.
The mode specified with the '-mode' option must be
under the current design.
TUI-742 Fanin/fanout commands will work
only with -structural option for pg
pins.
Use -struct option when getting fanin/fanout of pg pins.
TUI-750 Cannot create isolation rule. The isolation rule with the specified name already
exists.
TUI-772 Cannot create level shifter rule. The level shifter rule with the specified name already
exists.
TUI-786 Cannot execute design exploration
command.
An RTL_Compiler_Ultra_II_Option license is required
to enable design exploration. Check out the appropriate
license with the 'license checkout' command and retry
the command.
TUI-901 Cannot set options for removing
assigns.
Some of the options may be provided with wrong
argument types.
UTUI-101 Use attribute remove_assigns or
command
remove_assigns_without_optimiza
tion.
The command remove_assigns was obsoleted in 8.1
release and the same functionality is now provided by
attribute remove_assigns. Standalone command based
usage of same is through newly added command
remove_assigns_without_optimization.
UTUI-111 Design is not mapped. Run mapping before removing assigns from the design.
UTUI-112 Option value is invalid. Check the type of value expected by this option.
UTUI-120 No design available. Load a design before using this command.
UTUI-206 Specified tiecell cannot be found in
library-domain of the module.
Specify a cell which is in the corresponding domain
using -hi/-lo/-hilo option <or> do tiecell insertion without
-hi/-lo/-hilo options to pick a tiecell automatically from
the specific domain.
UTUI-211 More than one design found. Specify unique design for tiecell insertion.
UTUI-212 Invalid argument for '-maxfanout'
option.
Specify a value equal to or greater than 1.
UTUI-213 Specify both -tiehicell and -tielocell
together.
These options cannot be set individually.
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Error Messages
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UTUI-214 Specify either -tiehilocell or
-tiehicell/-tielocell.
These options cannot be set together.
UTUI-215 Specify a tiecell which is not
avoided.
Unavoid the tiecells from library.
UTUI-216 Cannot proceed with tiecell
insertion.
Fix the problems reported above.
VCD-1 VCD file does not exist. The file specified on the command line does not exist.
VCD-2 End time is less than or equal to
start time.
Specify an end time as greater than start time to do
meaningful analysis.
VCD-3 Both '-static' and '-dynamic'
options specified.
You cannot specify '-static' and '-dynamic' options
together. Specify only one of them.
VCD-7 Time window specified is less than
or equal to '0.0'.
Specify a time window through the '-time_window'
option as greater than '0.0' to do meaningful dynamic
power analysis.
VCD-8 Time window specified is too large. Specify a time window through the '-time_window'
option as lesser than the difference between start and
end times.
VCD-9 '-time_window' option can only be
specified with '-activity_profile'
option.
Either use the '-time_window' option with
'-activity_profile' or use only the '-static' option.
VCD-10 Both '-activity_profile' and '-static'
options specified.
You cannot specify '-static' and 'activity_profile' options
together. Specify only one of them.
VCD-11 Both '-activity_profile' and
'-dynamic' options specified.
You cannot specify '-dynamic' and '-activity_profile'
options together. Specify only one of them.
VCD-12 Option '-activity_profile' not
specified with '-simvision'.
You can specify '-simvision' option only with
'-activity_profile'.
VCD-13 Option '-activity_profile' not
specified with '-write_sst2'.
You can specify '-write_sst2' option only with
'-activity_profile'.
VCD-15 Failed to create the directory. Make sure you have write permissions to the specified
directory.
VCD-17 The SST2 transition file could not
be loaded.
Make sure SimVision is installed and the transition file
is present.
VCD-22 Option '-dynamic' not supported. The '-dynamic' option was an undocumented feature.
Contact your local cadence representative for more
information.
VCD-23 Incorrect '-instance' option. The instance name specified could not be found in the
design.
VCD-24 Multiple match for '-instance'
option.
The instance name specified matched multiple
instances. Specify one unambiguous instance path.
Message-ID Title Help
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Error Messages
May 2013 260 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
VHDL-111 Unsupported '%s' declaration seen
in module. Only signal
declarations are allowed.
Unsupported VHDL syntax is encountered.
VHDL-112 Statement is of an unsupported
type '%s'. Only component
instantiations and concurrent
assignments are supported.
Unsupported VHDL syntax is encountered.
VHDL-114 Unsupported feature. Unsupported VHDL syntax is encountered.
VHDL-204 Unable to analyze VHDL file(s)
due to an internal error in the
VHDL Analyzer.
An internal error was detected in the VHDL Analyzer. If
any VHDL error messages were reported, fix these
errors before reading in the VHDL files.
VHDL-208 Consistency check failed for VHDL
node.
An inconsistency has been detected for the VHDL
construct reported in the error message. Synthesis will
be aborted at this stage. It may be possible to rewrite
the VHDL code that uses that construct.
VHDL-210 VHDL libraries not found under
$CDN_SYNTH_ROOT/lib/vhdl.
Either CDN_SYNTH_ROOT is not set correctly, or the
VHDL libraries are not installed.
VHDL-211 Cannot open package
STD.STANDARD.
Either CDN_SYNTH_ROOT is not set correctly, or the
VHDL libraries are not installed.
VHDL-214 Too few enum encodings
specified.
The ENUM_ENCODING attribute for an enumeration
type must have an encoding specified for each of the
enumeration literals of that type.
VHDL-216 Undefined VHDL library. Error encountered during VHDL parsing.
VHDL-219 Architecture is invalid since it is
potentially out-of-date with respect
to packages used.
The specified architecture uses a package that has
been re-analyzed and must be re-analyzed.
VHDL-228 Unsupported character seen in
ENUM_ENCODING.
The ENUM_ENCODING attribute is a string that
consists of a series of blank-separated tokens. Each
token can have one or more of the following characters:
'U' - uninitialized value
'D' - don't care value
'Z' - high impedance
'0' - logic zero
'1' - logic one
Any other character in the ENUM_ENCODING string
will result in an error.
VHDL-312 Entity has no synthesizable
architecture specified.
The entity has no architectures associated with it or the
architectures of that entity have been tagged as
unsynthesizable using synthesis off/on.
VHDL-412 Unsupported expression type '%s'
seen.
Unsupported VHDL syntax is encountered.
VHDL-413 Unsupported left/right bound types
seen.
Unsupported VHDL syntax is encountered.
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Error Messages
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VHDL-414 Unable to compute a literal value
for expression. Only integer and bit
values are supported in this
release.
Unsupported VHDL syntax is encountered.
VHDL-415 Unsupported operation type '%s'
seen in expression.
Unsupported VHDL syntax is encountered.
VHDL-416 Unable to evaluate index
specification in block configuration.
Error encountered during VHDL parsing.
VHDL-417 Unable to evaluate subelement
association in binding indication.
Error encountered during VHDL parsing.
VHDL-512 Unsupported multi-dimensional
port seen while writing netlist.
Unsupported VHDL syntax is encountered.
VHDL-516 Unsupported bit type specified for
VHDL netlisting. Only 'std_logic'
and 'std_ulogic' types are
supported.
Unsupported VHDL syntax is encountered.
VHDL-600 Detected VHDL synthesis subset
violations.
Certain VHDL constructs were detected that are
unsynthesizable or not supported in this release. This
error can be avoided by rewriting the VHDL code to
avoid the constructs for which errors were reported.
VHDL-601 Unsupported clock edge construct. See 'Specifying Clock Signals for Flip-Flops' in 'HDL
Modeling in Encounter RTL Compiler' for information on
how to model clock-edge expressions.
VHDL-602 Clock-edge expression must be
the condition of the last clause of a
'conditional assignment'
statement.
See 'Specifying Clock Signals for Flip-Flops' in 'HDL
Modeling in Encounter RTL Compiler' for information on
how to model clock-edge expressions.
VHDL-603 Unsupported use of a clock-edge
expression.
See 'Specifying Clock Signals for Flip-Flops' in 'HDL
Modeling in Encounter RTL Compiler' for information on
how to model clock-edge expressions.
VHDL-606 Unsupported use of 'wait'
statement.
When a 'wait' statement is used, it must be the first
statement in the process. Processes with multiple 'wait'
statements are not supported. See 'HDL Modeling in
Encounter RTL Compiler' for more information.
VHDL-607 The condition clause of a wait
statement must contain an edge
specification.
See 'Specifying Clock Signals for Flip-Flops' in 'HDL
Modeling in Encounter RTL Compiler' for information on
how to model clock-edge expressions.
VHDL-608 Sensitivity clause of a wait
statement can only contain the
signal whose edge specification is
in the condition clause.
See 'Specifying Clock Signals for Flip-Flops' in 'HDL
Modeling in Encounter RTL Compiler' for information on
how to model clock-edge expressions.
VHDL-609 Block statements with ports and
generics are not supported for
synthesis.
Rewrite the VHDL code using supported constructs.
See the 'HDL Modeling Guide for Encounter RTL
Compiler' for a list of supported VHDL constructs.
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VHDL-610 Construct is not synthesizable. The specified construct is not currently supported. See
'Synthesizing VHDL Designs' in the 'HDL Modeling in
Encounter RTL Compiler' manual for a list of supported
synthesis constructs.
VHDL-613 Unsupported predefined attribute. The predefined attribute is not supported. See the 'HDL
Modeling in Encounter RTL Compiler' manual for a list
of supported predefined attributes.
VHDL-614 Attribute is only allowed in the
context of clock-edge expressions.
The attributes 'event' and 'stable' must be used only for
specifying clock-edge expressions. See 'Specifying
Clock Signals for Flip-Flops' in 'HDL Modeling in
Encounter RTL Compiler' for information on how to
model clock-edge expressions.
VHDL-615 Different signals in potential clock
edge expression.
In clock-edge expressions that use the 'event' and
'stable' attributes, the signal used in the attribute names
must be identical to the signal used in the
value-expression. For example:
S'event and S = '1' -- OK
S'event and T = '1' -- ERROR: different signals
S(0)'event and S(1) = '1' -- ERROR: different indexes
S(i)'event and S(i) = '1' -- ERROR: variable indexes.
VHDL-617 Multiple waveforms in signal
assignments are not supported for
synthesis.
See 'HDL Modeling in Encounter RTL Compiler' for a
list of supported VHDL constructs.
VHDL-620 Unable to find package body. Error encountered during VHDL parsing.
VHDL-630 Physical literals are not supported
for synthesis.
The specified construct is not currently supported. To
avoid this error, try and rewrite the VHDL in a different
way or enclose the construct between the
meta-comments: -- cadence translate_off .....
-- cadence translate_on.
VHDL-631 Real literals are not supported for
synthesis.
The specified construct is not currently supported. To
avoid this error, try and rewrite the VHDL in a different
way or enclose the construct between the
meta-comments: -- cadence translate_off .....
-- cadence translate_on.
VHDL-633 Interface objects of mode linkage
are not supported for synthesis.
The specified construct is not currently supported. To
avoid this error, try and rewrite the VHDL in a different
way or enclose the construct between the
meta-comments: -- cadence translate_off .....
-- cadence translate_on.
VHDL-634 Postponed concurrent statements
are not supported for synthesis.
The specified construct is not currently supported. To
avoid this error, try and rewrite the VHDL in a different
way or enclose the construct between the
meta-comments: -- cadence translate_off .....
-- cadence translate_on.
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VHDL-635 Signal assignments with
'unaffected' expression are not
supported for synthesis.
The specified construct is not currently supported. To
avoid this error, try and rewrite the VHDL in a different
way or enclose the construct between the
meta-comments: -- cadence translate_off .....
-- cadence translate_on.
VHDL-636 Block statements with guard
expression are not supported for
synthesis.
The specified construct is not currently supported. To
avoid this error, try and rewrite the VHDL in a different
way or enclose the construct between the
meta-comments: -- cadence translate_off .....
-- cadence translate_on.
VHDL-638 Unconditional loops are not
supported for synthesis.
The specified construct is not currently supported. To
avoid this error, try and rewrite the VHDL in a different
way or enclose the construct between the
meta-comments: -- cadence translate_off .....
-- cadence translate_on.
VHDL-647 Signals of kind 'register' are
unsupported for synthesis.
The specified construct is not currently supported. To
avoid this error, try and rewrite the VHDL in a different
way or enclose the construct between the
meta-comments: -- cadence translate_off .....
-- cadence translate_on.
VHDL-652 Function body has no
synthesizable return statements.
A function body must have at least one return
statement that is synthesizable (i.e. not enclosed
between synthesis off/on directives).
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Error Messages
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VHDL-656 Clock-edge is supported only in
process statements.
A clock-edge expression is supported in the following
contexts only:
o condition clause of 'wait' statement
o condition of last clause in an 'if' statement
Additionally, in VHDL 1993 mode:
o condition of last clause in a 'conditional
assignment'
The following forms of the clock-edge expressions are
supported:
For 'boolean' clock signals:
clk'event and clk = TRUE
not clk'stable and clk = TRUE
For 'bit' clock signals:
clk'event and clk = '1'
not clk'stable and clk = '1'
For 'std_ulogic' or 'std_logic' clock signals:
clk'event and clk = '1'
not clk'stable and clk = '1'
rising_edge(clk)
Additionally, for 'wait' statements:
wait until clk = '1'
The examples above illustrate rising clock edges.
Similar expressions can be constructed for falling clock
edges. Indexed clock signals are not supported.
VHDL-658 Instance has conflicting bindings. Invalid VHDL syntax is encountered.
VHDL-665 Mismatched or unsupported
indexing of signal in potential
clock-edge expression.
In clock-edge expressions that use the 'event' and
'stable' attributes, the signal used in the attribute names
must be identical to the signal used in the
value-expression. For example:
S'event and S = '1' -- OK
S'event and T = '1' -- ERROR: different signals
S(0)'event and S(1) = '1' -- ERROR: different indexes
S(i)'event and S(i) = '1' -- ERROR: variable
indexes.
VHDL-669 Multiple 'wait' statements in a
VHDL process are unsupported.
Processes that have a 'wait' statement must have it as
the first statement. Multiple 'wait' statements in the
same process used to describe implicit state machines
is unsupported.
VHDL-673 Multiple module definitions present
across different libraries in the
module pool.
Try and resolve the instance by providing either a single
definition of its module definition or specifying the
instance linkage (library to link it from) properly.
VHDLPT-500 Cannot open file. The input VHDL file cannot be opened. Make sure that
the directory path and file extension (e.g., .vhdl) are
specified.
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Error Messages
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VHDLPT-501 Cannot open library. Check that the VHDL library is defined and that it maps
to an existing directory.
VHDLPT-502 Cannot open design unit. Error encountered during VHDL parsing.
VHDLPT-503 Cannot save library unit; possibly
an analyzer bug.
Error encountered during VHDL parsing.
VHDLPT-505 Command failed due to syntax
error.
The command option is spelled incorrectly or is
improperly placed in the command line. Correct and
reenter the command.
VHDLPT-511 Attempting to mix VHDL-1987 and
VHDL-1993 units.
Error encountered during VHDL parsing.
VHDLPT-513 Error will occur in elaboration or
simulation.
Error encountered during VHDL parsing.
VHDLPT-516 Cannot open unit because of
invalid dependency.
A previously analyzed unit cannot be opened because
of errors in resolving its dependencies on one or more
units. Possible sources for this error include:
A depended-on unit has been deleted
A depended-on unit has been re-analyzed, making
the dependent unit out-of-date.
VHDLPT-517 Unit has incompatible DLS
version.
Error encountered during VHDL parsing.
VHDLPT-519 Generic error. Error encountered during VHDL parsing.
VHDLPT-521 VHDL Parser internal error. Error encountered during VHDL parsing.
VHDLPT-526 Unexpected end of file. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-527 A VHDL-1987 attribute was
detected in VHDL-1993 mode.
The VHDL-1987 attributes ''BEHAVIOR' and
''STRUCTURE' are not allowed when analyzing in
VHDL-1993 mode.
VHDLPT-528 VHDL-1993 feature detected in
VHDL-1987 mode.
To use VHDL-1993, set the 'hdl_vhdl_read_version'
attribute to '1993'.
VHDLPT-529 VHDL-1993 keyword may not
appear as a subprogram
designator.
The following new operators were introduced in
VHDL-1993. They may be used as identifiers in
VHDL-1987, but in VHDL-1993 they must be quoted,
except when appearing in infix notation:
ROR, ROL, SRA, SRL, SLA, SLL, XNOR.
VHDLPT-530 Interface mode error. VHDL imposes restrictions on the use of interface
objects (ports and subprogram parameters) based on
their modes. Interface objects of mode IN, INOUT, and
BUFFER may be read, and interface objects of mode
OUT, INOUT, and BUFFER may be updated.
VHDLPT-531 Actual designator does not match
formal type.
Invalid or unsupported VHDL syntax is encountered.
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VHDLPT-533 Aggregate target may not contain
discrete range choice.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-534 Aggregate target may not contain
a subaggregate.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-535 Ambiguous actual part. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-536 Cannot determine type of
aggregate.
The type of an aggregate must be determinable from
the context in which the aggregate appears. An
ambiguous aggregate may be resolved using a
qualified expression. For instance, the aggregates
appearing in the following statement:
if ('1', '0', '1') = (x, y, z) then ...
are ambiguous, but they could be resolved as follows:
if bit_vector'('1', '0', '1') = (x, y, z) then ...
or
if ('1', '0', '1') = bit_vector'(x, y, z) then ...
VHDLPT-537 No unique conversion function. A conversion function applied to a formal or actual part
in an association element must have a single argument
of the type of the formal, and return the type of the
actual. Thus a function like To_Bit in package
ieee.std_logic_1164 cannot be a conversion function
since it has two arguments.
VHDLPT-538 Expression has ambiguous type. The alternatives given with the error message specify
possible interpretations for the expression. Some
common reasons for ambiguity:
In VHDL-1993, a bit string literal (e.g., X'FF00') may be
of type BIT_VECTOR or STD_LOGIC_VECTOR, while
in VHDL-1987 it cannot be of type
STD_LOGIC_VECTOR. Thus a bit string literal which
is legal in VHDL-1987 may be ambiguous in
VHDL-1993.
A character literal may belong to several types, e.g., '1'
may be an element of type BIT, CHARACTER, or
STD_ULOGIC.
VHDLPT-539 Ambiguous procedure call;
possible alternatives follow.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-540 More than one possible prefix for
signature.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-541 Cannot determine type of string. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-542 For unconstrained array
conversion function needs
constrained subtype.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-543 Choice length differs from selector
expression length.
Invalid or unsupported VHDL syntax is encountered.
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VHDLPT-545 A range choice is not allowed for a
selector of an array type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-546 Invalid argument to attribute. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-547 Predefined attribute requires an
argument.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-549 Parameter to attribute must be a
static expression.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-550 Attribute parameter out of range. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-551 Invalid prefix of attribute name. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-552 The designated type of an access
type must not be a file type.
Error encountered during VHDL parsing.
VHDLPT-553 Expecting possibly converted
name as actual corresponding to
formal.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-554 An alias may not be declared for
this object.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-555 Name in object alias declaration
must denote an object.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-556 Cannot attribute alias which does
not denote a whole object.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-557 The subtype in an alias declaration
must not denote a
multidimensional array type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-558 A subtype indication in an allocator
must denote a constrained array
subtype.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-559 Choice in array aggregate is not an
expression or discrete range.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-560 Bad prefix for predefined attribute. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-561 An attribute may not be of a file
type or access type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-562 'BASE may appear only as a prefix
of an attribute name.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-563 Character does not belong to
element base type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-564 A constant may not be of a file
type or access type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-565 A constant may not be of a
composite type with a subelement
of an access type.
Invalid or unsupported VHDL syntax is encountered.
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VHDLPT-566 Record type has no such element. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-567 Illegal element type for composite
type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-568 The subtype indication in a file
declaration must denote a file type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-569 The type mark in a file type
definition must not denote a file
type or access type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-570 A variable may not be of a file type. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-571 A sequential signal assignment
cannot be guarded.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-572 In a guarded signal assignment,
GUARD must be a signal.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-573 Implicit signal GUARD may not
have a source.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-574 Illegal unguarded target of
guarded signal assignment.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-575 In a guarded signal assignment,
GUARD must be of type boolean.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-576 A null waveform element may not
appear in a waveform of a
concurrent signal assignment
statement.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-577 Illegal choice in record aggregate. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-578 Name on sensitivity list must be a
static signal name.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-579 A signal may not be of a file type or
access type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-580 A signal may not be of a composite
type with a subelement of an
access type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-581 The given expression cannot be
interpreted as a subaggregate.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-582 Invalid subelement (must be
indexed, slice, or selected name).
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-583 Binding mismatch between
instances.
Error encountered during VHDL parsing.
VHDLPT-584 Signal associated with BUFFER
port has more than one source.
Invalid or unsupported VHDL syntax is encountered.
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VHDLPT-585 Keyword BUS not allowed for
non-signal interface parameters.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-586 Illegal token in this context. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-587 Sequential signal assignment
cannot have conditional
waveforms.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-589 Character literal is not visible at
this point.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-590 Type of choice does not match
index base type in array
aggregate.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-591 Architecture mismatch in
component configuration.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-592 Configuration may not have same
identifier as entity.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-593 A binding indication within a
configuration specification must
contain an entity aspect.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-594 Group template requires
constituent of different class.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-595 Base type of subtype indication
does not match constraining base
type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-596 Declaration in statement part. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-597 Cannot resolve selected name. Error encountered during VHDL parsing.
VHDLPT-598 Error in default map aspect: formal
may not be defaulted.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-599 Error in default map aspect: entity
has no corresponding formal.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-600 Error in default map aspect: formal
does not match local.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-601 A deferred constant declaration
may only occur within a package
declaration.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-602 Invalid reference to deferred
constant before completion.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-603 An attribute specification of a
design unit must occur
immediately within the declarative
part of that design unit.
Invalid or unsupported VHDL syntax is encountered.
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Error Messages
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VHDLPT-605 The '<>' symbol cannot appear in
a discrete_range.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-606 Signal in disconnection
specification is not a guarded
signal.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-607 Item in disconnection specification
is not a signal.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-608 Signal in disconnection
specification is not declared with
correct type mark.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-609 Duplicate association for formal. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-610 Duplicate attribute specification. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-611 Duplicate subprogram body. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-612 Duplicate choice. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-613 Duplicate completion for deferred
constant.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-614 Duplicate configuration. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-615 Configuration specification
attempts to re-bind instantiation.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-616 Cannot impose an index constraint
on a type mark which denotes a
constrained array subtype.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-617 Duplicate disconnection
specification for signal.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-618 Choice has already been
associated in aggregate.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-619 Formal has already been
associated.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-620 Overlap of index specifications in
configuration of generate
statement.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-622 Duplication of choices. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-623 Duplicate subprogram
specification found.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-624 Duplicate or overlapping name in
aggregate target.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-626 Empty '()' is illegal. Unlike C, a VHDL function or procedure with no
arguments has no parentheses.
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VHDLPT-627 Record type definition with no
element declarations.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-628 <> option may only appear in with
final entity class in entry list.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-629 An array aggregate with null or
non-static choice must have
exactly one choice.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-630 Unexpected construct. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-632 Association element does not
correspond to any formal.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-633 Illegal extra ',' detected. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-634 Ending label on unlabeled
statement.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-635 Too many element associations in
record aggregate.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-636 Illegal extra ';' detected. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-637 Illegal type mark in file type
definition.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-638 Wrong number of elements for
group template.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-639 Each scalar subelement of a
guarded composite signal must be
of a resolved subtype or belong to
a resolved composite subtype.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-640 A guarded scalar signal must be of
a resolved subtype.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-641 Duplicate declaration. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-642 Illegal type conversion or
conversion function.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-643 Default expression not allowed. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-644 Invalid reference to incomplete
type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-645 Wrong number of constraints for
array type.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-647 File interface object cannot have
default expression.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-648 Identifier in instantiation list must
be a label.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-650 Invalid actual in subprogram call. Invalid or unsupported VHDL syntax is encountered.
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VHDLPT-652 Configuration specification does
not refer to an instantiation of the
component.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-653 A non-array type mark may not
have an index constraint.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-654 Invalid expression. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-655 A formal conversion is not allowed
for a formal of mode IN.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-656 Invalid open or defaulted
association element for formal.
A formal may be a generic or port, or a subprogram
argument. A generic or a port of mode IN may be
omitted only if it is declared with a default expression.
A port of mode other than IN may be omitted unless it is
of an unconstrained array type. A subprogram
argument of mode IN may be omitted if it is declared
with a default expression.
VHDLPT-657 Invalid class. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-658 Invalid mode. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-659 Invalid primary. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-660 Lexical error. Error encountered during VHDL parsing.
VHDLPT-662 Math error. Error encountered during VHDL parsing.
VHDLPT-664 Illegal mix of logical operators,
suggest adding parentheses.
VHDL disallows unparenthesized sequences of more
than two different logical operators or negating logical
operators. For instance:
A and B and C -- legal
A or B or C -- legal
A xor B xor C -- legal
A nand B nand C-- illegal
A nor B nor C -- illegal
A xnor B xnor C-- illegal (VHDL-1993 operator xnor)
A or B and C -- illegal.
VHDLPT-665 Missing association element(s) for
formal.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-666 Missing subprogram body. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-667 Missing choices in aggregate. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-669 Missing completion for deferred
constant.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-670 Statement must have a label. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-671 Missing association for record
element.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-672 Missing token. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-673 Missing completion for incomplete
type.
Invalid or unsupported VHDL syntax is encountered.
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VHDLPT-674 Cannot mix index constraint and
index subtype definition in an array
type definition.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-675 Guarded and unguarded signals
are mixed in aggregate target.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-676 Cannot mix named and positional
association in aggregate.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-677 Interface file declaration may not
contain a mode keyword.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-678 Signal has multiple sources. There are two cases in which a VHDL signal is
prohibited from having multiple sources. First, any
unresolved signal is not allowed to have multiple
sources. Second, any signal declared BUFFER is not
allowed to have multiple sources. (A resolved BUFFER
signal is still not allowed to have multiple sources.)
A signal can be declared as resolved in one of two
ways. A signal can be declared with a resolved
subtype. For instance, subtype std_logic is a resolved
subtype (while std_unlogic is unresolved). Or, a signal
can include a resolution function in its declaration.
For instance:
signal s1 : std_ulogic; -- unresolved
signal s2 : std_logic; -- resolved
signal s3 : buffer std_logic; -- resolved, but BUFFER
signal s4 : resolved std_ulogic; -- resolved
A source for a signal is one of the following:
1. an association with an INOUT, OUT, BUFFER, or
LINKAGE port in a component instantiation or block
statement
2. a concurrent signal assignment statement
3. an association with an INOUT or OUT parameter of a
procedure
4. a process statement which contains an assignment
to a signal
Note that multiple assignments or procedure
associations within one process statement count as
only one source (the process statement as a whole
counts as one source for a given signal).
VHDLPT-679 This expanded name is not within
current construct.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-681 Block configuration has no
corresponding block.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-682 No common type for left and right
bounds of discrete range.
Invalid or unsupported VHDL syntax is encountered.
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VHDLPT-683 No architecture for configured
entity.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-684 Non-conforming subtype indication
in completion of deferred constant.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-685 Non-conforming subprogram
specification.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-686 No signal GUARD visible at the
point of the guarded signal
assignment statement.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-687 No possible interpretations for
expression.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-688 No such item in package. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-689 No loop for next or exit statement. A next or exit statement may only be used within a loop
statement (including a for loop or while loop).
VHDLPT-690 An array aggregate with a
non-locally-static choice must
have exactly one choice.
In an array aggregate with more than one choice, all the
choices must be constants. Whether an OTHERS
choice is constant depends on the context in which the
aggregate appears. For instance, in signal s :
bit_vector(g1 to g2) := (1 => '1', others => '0'); the
OTHERS choice is constant only if g1 and g2 are
constant.
VHDLPT-691 Non-locally-static name in
aggregate target.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-692 Choice must be static. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-693 Non-static formal name in
individual association.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-694 The condition in an 'if generate'
statement must be a static
expression.
See 'HDL Modeling in Encounter RTL Compiler' for
more information.
VHDLPT-695 The range in a 'for generate'
statement must be a static range.
See 'HDL Modeling in Encounter RTL Compiler' for
more information.
VHDLPT-696 Expression in index specification
must be static.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-697 The default expression of an
interface object must be static.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-698 Static name required. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-699 Range in numeric type definition
must be locally static.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-700 Time expression must be static. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-701 Non-unique symbol. Invalid or unsupported VHDL syntax is encountered.
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VHDLPT-702 OTHERS appears in an array
aggregate in a non-constraining
context.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-703 No such primary unit in library. There are two typical causes for this error: 1) the unit
has not been read in with read_hdl -vhdl; or 2) it has
been read into a different library than the library
referenced in this context.
VHDLPT-705 No prefix matches this signature. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-706 Unknown attribute. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-707 Operand base type is not closely
related to base type of type mark
in type conversion.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-708 No interpretation as discrete type. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-709 Range must be of a discrete type. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-710 Name is not in entity class. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-711 No matching declaration in current
declarative part.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-712 There is a prior configuration
specification for ALL or OTHERS
for this component.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-713 Range must be of a numeric type. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-714 Illegal null waveform element with
non-guarded target.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-716 An OTHERS in a record aggregate
must represent at least one
element.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-717 Parameter association class
mismatch.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-718 A converted formal is not allowed
with an actual of OPEN.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-719 An actual of OPEN may not be
associated with a formal that is
associated individually.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-720 An entity aspect of OPEN may not
be followed by a generic or port
map aspect.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-721 Wrong number of parameters for
operator.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-722 GUARDED may not follow delay
mechanism.
Invalid or unsupported VHDL syntax is encountered.
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Error Messages
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VHDLPT-723 Choice type mismatch. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-724 The choice OTHERS must appear
by itself.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-725 OTHERS must be last choice. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-726 Unit is out of date. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-727 Expression or slice out of range. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-728 Analysis of unit invalidates already
analyzed units.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-729 Physical type definition requires
bounds of integer types.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-730 Port mode mismatch in
association.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-731 Positional association cannot
follow named association.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-732 Attribute specification after ALL or
OTHERS.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-733 Illegal declaration of guarded
signal after disconnection
specification for ALL or OTHERS.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-734 Inappropriate prefix. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-735 Procedure mismatch; no
procedures matched type profile.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-736 Illegal reference within pure
function.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-737 A procedure declaration may not
contain the keywords PURE or
IMPURE.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-739 Identifier mismatch. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-740 An alias of a subprogram or
enumeration literal requires a
signature.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-741 Error in resolution function. Error encountered during VHDL parsing.
VHDLPT-742 Illegal use of a resolution function
in a subtype indication.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-743 A return statement with an
expression may not appear within
a procedure body.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-744 A return statement in a function
must have an expression.
Invalid or unsupported VHDL syntax is encountered.
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Error Messages
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VHDLPT-745 Each secondary unit of a physical
type must be defined, directly or
indirectly, in terms of the primary
unit.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-746 Secondary unit declaration
requires an integer literal.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-747 When prefix of selected name
denotes a library, suffix must
denote a package.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-748 Element subtype of selector base
type is not locally static.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-749 An object alias may not have a
signature.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-750 Converted association is not
allowed for a signal parameter.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-751 Variable assignment target-source
type mismatch.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-752 Statement in declarative part. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-753 Mixup in keyword order. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-755 Attribute of subprogram parameter
cannot be read.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-757 Wrong class for target of
assignment statement.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-759 Invalid type conversion operand. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-760 Only a type mark is allowed. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-761 Type mismatch. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-762 Unassociated local in map aspect. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-763 The subtype indication in the
declaration of a signal of an array
type must be constrained.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-764 Undeclared character literal. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-765 No such element in record type. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-766 Undeclared identifier. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-767 Undeclared library name. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-768 Undeclared operator symbol. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-769 Unexpected construct. Invalid or unsupported VHDL syntax is encountered.
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Error Messages
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VHDLPT-770 OTHERS choice is required for
selector base type of
universal_integer.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-771 Error in use clause syntax. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-772 Expected package name in use
clause.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-773 The subtype indication in the
declaration of a variable of an
array type must be constrained.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-775 Declaration not allowed here. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-776 An index specification is allowed
only for a FOR generate label.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-777 Statement may not contain
keyword POSTPONED.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-778 Invalid primary unit name. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-779 A return statement is allowed only
within a subprogram body.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-780 Invalid selected name. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-781 This specification is not allowed
here.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-782 This statement is not allowed here. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-783 Inappropriate construct in this
context.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-784 Ignoring illegal token. Error encountered during VHDL parsing.
VHDLPT-785 Cannot overwrite existing unit. 'read_vhdl' will not overwrite a write-protected file. This
error typically occurs when a user attempts to overwrite
one of the predefined packages in libraries STD,
AMBIT, or IEEE.
VHDLPT-786 Cannot open unit. Error encountered during VHDL parsing.
VHDLPT-789 Looks like a Verilog file. 'read_hdl -vhdl' has detected an erroneous construct
that resembles a piece of Verilog syntax.
VHDLPT-790 Illegal assignment to non-local
signal within procedure.
If a signal is assigned within a procedure, then either
the signal must be a formal parameter of the procedure,
or the procedure must be declared within a process
statement.
VHDLPT-791 Too many arguments to
subprogram.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-792 Too few arguments to subprogram. Invalid or unsupported VHDL syntax is encountered.
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Error Messages
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VHDLPT-793 No actual corresponding to formal
in call to subprogram.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-794 Bad argument to formal in call to
subprogram.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-795 No subprogram matching
argument type profile.
Invalid or unsupported VHDL syntax is encountered.
VHDLPT-796 Missing END. Invalid or unsupported VHDL syntax is encountered.
VHDLPT-798 Illegal prefix for compound name. The prefix of an indexed name, slice name, selected
name, or attribute name must be a function call or
another name. A type conversion or qualified
expression cannot be a prefix.
VHDLPT-803 OTHERS choice required when
some choices are not locally static.
VHDL requires that each choice in a case statement be
a locally static expression. However, read_hdl allows
globally static choices as well, provided that there is a
final OTHERS choice.
VHDLPT-804 Cannot configure entity
instantiation.
Only a component instantiation may be configured.
VHDLPT-806 Cannot decrypt block. Error encountered during VHDL parsing.
VLOGPT-1 Parsing error. Invalid Verilog syntax is parsed, or unsupported Verilog
syntax is encountered.
VLOGPT-3 Verilog-2001 feature. The design must be read in with 'read_hdl -v2001'.
VLOGPT-4 Verilog-DP feature. The design must be read in with 'read_hdl -vdp'.
VLOGPT-5 Unsupported construct. Unsupported Verilog construct is encountered.
VLOGPT-7 Illegal use of Verilog-2001
reserved word.
Verilog-2001 introduces several new keywords. They
are:
automatic
config
design
endconfig
endgenerate
generate genvar
ifnon
instance
liblist
library
localparam
To use these keywords as identifiers in a design, you
must read the input design with 'read_hdl -v1995'; or
use the pragma:
`begin_keywords "1364-1995".
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VLOGPT-8 Illegal use of SystemVerilog
reserved word.
SystemVerilog introduces many new keywords. They
are:
alias do join_any solve
always_comb endclass join_none static
always_ff endclocking local string
always_latch endinterface logic struct
assert endprogram longint super
assert_strobe endproperty modport this
before endsequence new throughout
bind enum null timeprecision
bit export packed timeunit
break extends priority type
byte extern program typedef
chandle final property union
class first_match protected unique
clocking forkjoin pure var
const iff rand virtual
constraint import randc void
context inside ref wait_order
continue int sequence with
cover interface shortint within
dist intersect shortreal
To use these keywords as identifiers in a design, you
must read the input design with 'read_hdl -v1995' or
'read_hdl -v2001'; or use the pragma:
`begin_keywords "1364-1995"
or `begin_keywords "1364-2001".
VLOGPT-9 SystemVerilog feature. The design must be read in with 'read_hdl -sv'.
VLOGPT-11 Unexpected end of file. Unexpected end of file encountered.
VLOGPT-15 Invalid decimal number. Invalid specification of an integer number, or the integer
number is too large.
VLOGPT-17 Invalid based number. A based number may be a binary 'b, octal 'o, hex 'h, or
decimal 'd based number.
VLOGPT-20 Reference to undeclared variable. A variable must be declared before it can be
referenced.
VLOGPT-22 Illegal redeclaration. A variable cannot be redeclared in the same scope.
VLOGPT-23 I/O signal not declared in portlist. An declared input, output, or inout signal must also be
declared in the port list.
VLOGPT-25 Inconsistent sign or range on
redeclaration.
Multiple declarations of the same object must use the
same sign and range.
VLOGPT-26 Invalid struct member reference. Either the prefix does not represent a struct object or
the suffix is not a member of the prefix struct.
VLOGPT-28 Reference to non-existent
package.
The referenced package does not exist.
VLOGPT-29 Cannot import symbol which is
already in scope.
When importing from a package with 'import pkg::sym;'
it is illegal if a declaration matching 'sym' is visible in the
current scope.
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VLOGPT-30 Feature not supported for
synthesis.
The following features are not supported for synthesis:
- primitive
- configuration
- all 'mos' gates
- all 'rtran' gates
- all 'tranif' gates
- pullup/pulldown gates.
VLOGPT-32 Unsupported declaration. The following declarations are not supported for
synthesis:
- tri0
- tri1
- event
- class
- chandle
- SV string type
- associative array.
VLOGPT-34 Unsynthesizable construct. The following statements are not supported for
synthesis:
- deassign
- procedural assign
- force
- release
- wait
- ->
- fork.
VLOGPT-36 Incomplete typedef needs to be
completed.
An incomplete typedef must be completed in the scope
in which it was declared.
VLOGPT-39 Unsupported procedural
assignment.
'assign' and 'deassign' statements within a sequential
statement are not supported for synthesis.
VLOGPT-41 Implicit net declaration not allowed
with `default_nettype none.
When `default_nettype is none, each input, output, and
inout declaration requires a corresponding net or reg
specification.
VLOGPT-42 Unsupported mix of edge and level
sensitivity.
'always @(non-edged signal or non-edged signal)' is
used for latch referencing or asynchronous set-reset on
a latch.
'always @(edged signal or edged signal)' is used for
asynchronous set-reset on a flip-flop.
VLOGPT-45 Unsupported hierarchical
reference.
Hierarchical reference x.y.x is not supported for
synthesis.
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VLOGPT-46 An 'if' statement is required at the
top of an always block to infer a
latch or flip-flop.
The supported syntax for asynchronous set-reset on a
flop-flop is:
reg data_out;
always @(posedge clock or posedge reset)
if ( reset )
data_out = 1'b1;
else
data_out = 1'b0.
VLOGPT-50 Wrong number of arguments to
system task or function.
Illegal Verilog syntax is encountered.
VLOGPT-53 Illegal multidimensional array
element.
Illegal Verilog syntax is encountered.
VLOGPT-56 Range given in clone declaration. Illegal Verilog syntax is encountered.
VLOGPT-57 Missing required value in
declaration.
Illegal Verilog syntax is encountered.
VLOGPT-58 Instance name required for
module instance.
Illegal Verilog syntax is encountered.
VLOGPT-59 Expecting range in instance name. Illegal Verilog syntax is encountered.
VLOGPT-60 Function cannot call task. Illegal Verilog syntax is encountered.
VLOGPT-61 Array must be indexed. Illegal Verilog syntax is encountered.
VLOGPT-62 Subprogram port not found. Illegal Verilog syntax is encountered.
VLOGPT-63 Positional association may not
follow named association.
If both positional and named arguments are specified in
a single subprogram call, then all positional arguments
must come before the named arguments.
VLOGPT-64 Too few arguments to subprogram. Illegal Verilog syntax is encountered.
VLOGPT-65 Too many arguments to
subprogram.
Illegal Verilog syntax is encountered.
VLOGPT-66 Cannot index or slice a scalar port. Illegal Verilog syntax is encountered.
VLOGPT-67 Illegal dependency in port/
parameter declaration.
Illegal Verilog syntax is encountered.
VLOGPT-68 Defparam requires hierarchical
name.
Illegal Verilog syntax is encountered.
VLOGPT-69 Defparam refers to nonexistent
module instance.
Error encountered during Verilog parsing.
VLOGPT-70 Function may only have input
ports.
Illegal Verilog syntax is encountered.
VLOGPT-71 System task/function called in
inappropriate context.
Illegal Verilog syntax is encountered.
VLOGPT-72 Invalid slice. Only a one-dimensional array wire or reg may be sliced.
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VLOGPT-73 Port expression with
multidimensional slice/index.
Illegal Verilog syntax is encountered.
VLOGPT-74 Cannot index or slice a scalar. Illegal Verilog syntax is encountered.
VLOGPT-75 Prefix/suffix mismatch. Error encountered during Verilog parsing.
VLOGPT-77 Vectored/scalared keyword must
be followed by range.
Illegal Verilog syntax is encountered.
VLOGPT-78 Invalid type definition. Error encountered during Verilog parsing.
VLOGPT-79 Illegal initial assignment for i/o
declaration.
Illegal Verilog syntax is encountered.
VLOGPT-80 Illegal initial assignment for genvar
declaration.
Illegal Verilog syntax is encountered.
VLOGPT-81 Wrong number of terminals for
gate.
Error encountered during Verilog parsing.
VLOGPT-82 Invalid use of void type. Illegal Verilog syntax is encountered.
VLOGPT-83 Gate output pin must be a single
bit.
Illegal Verilog syntax is encountered.
VLOGPT-84 Multiple default choices in 'case'
statement.
See the 'Modeling HDL Designs' chapter in 'HDL
Modeling in Encounter RTL Compiler' for examples on
modeling 'case' statements.
VLOGPT-85 The register declaration is not
allowed in this context.
See the 'HDL Modeling in Encounter RTL Compiler' for
examples on modeling the 'reg' data type.
VLOGPT-86 Net not allowed in this context. A net cannot be assigned within an always block. This
situation may occur because an output port is not
explicitly declared as a reg.
VLOGPT-87 Genvar declaration not allowed in
this context.
See the 'Genvar Declarations' section in the
'Synthesizing Verilog Designs' chapter in 'HDL
Modeling in Encounter RTL Compiler' for examples on
how to model the 'for generate' statement.
VLOGPT-88 Parameter not allowed in this
context.
Illegal Verilog syntax is encountered.
VLOGPT-89 Invalid lvalue. Illegal Verilog syntax is encountered.
VLOGPT-90 Invalid expression. Invalid Verilog syntax is encountered.
VLOGPT-91 Word concatenation may only be
an assignment source.
Illegal Verilog syntax is encountered.
VLOGPT-92 $flatten/$unflatten may only be an
assignment source.
Illegal Verilog syntax is encountered.
VLOGPT-93 Unsized number not allowed in
concatenation.
Illegal Verilog syntax is encountered.
VLOGPT-94 Illegal characters after decimal x/z. Illegal Verilog syntax is encountered.
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VLOGPT-95 Digit required on each side of
decimal point.
Illegal Verilog syntax is encountered.
VLOGPT-96 Illegal use of deferred port. Illegal Verilog syntax is encountered.
VLOGPT-97 Illegal use of deferred type. Illegal Verilog syntax is encountered.
VLOGPT-98 Internal declaration cannot be
deferred.
Illegal Verilog syntax is encountered.
VLOGPT-99 Unsupported parameter/port
dependency.
All parameters are processed before any ports are
processed. Therefore, a parameter may not depend on
a port's value or other attribute. This restriction does
not apply to localparams.
VLOGPT-100 Illegal port/port dependency. Illegal Verilog syntax is encountered.
VLOGPT-101 Non-structural construct. Invalid structural construct encountered during netlist
parsing.
VLOGPT-102 Division by zero. Illegal Verilog syntax is encountered.
VLOGPT-104 Illegal non-blocking assignment
within function.
Illegal Verilog syntax is encountered.
VLOGPT-108 Invalid unsized literal. Valid unsized literals are '0, '1, 'x, 'X, 'z and 'Z.
VLOGPT-109 Unnamed member following
named member in literal.
Illegal Verilog syntax is encountered.
VLOGPT-110 No match for element of struct
literal.
Illegal Verilog syntax is encountered.
VLOGPT-113 Replication operator in array
context requires single expression
in braces.
Illegal Verilog syntax is encountered.
VLOGPT-116 Data type not allowed in this
context.
Illegal Verilog syntax is encountered.
VLOGPT-117 Bad argument for operator. Illegal Verilog syntax is encountered.
VLOGPT-118 Assignment incompatibility. Illegal Verilog syntax is encountered.
VLOGPT-119 Duplicate named parameter
association.
Illegal Verilog syntax is encountered.
VLOGPT-120 Duplicate port association. Illegal Verilog syntax is encountered.
VLOGPT-121 Cannot omit a formal argument to
a subprogram port without a
default value.
Illegal Verilog syntax is encountered.
VLOGPT-123 Illegal 'unique' or 'priority' if
statement in else clause.
The 'unique' or 'priority' keyword must be applied to a
top-level if statement, not to an if statement directly
within an else clause of another if statement. An if
statement can be made into a top-level if statement by
enclosing it in a begin/end block.
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VLOGPT-124 Illegal use of indexed identifier in
named connection.
Illegal Verilog syntax is encountered.
VLOGPT-125 Only genvar allowed as index
variable in generate loop.
Use genvar to declare the index variable of generate
loop.
VLOGPT-201 Port has no type. A port needs to be declared as input, output, or inout.
VLOGPT-203 Unresolved subprogram reference. Error encountered during Verilog parsing.
VLOGPT-204 Disable statement must apply to
containing block or task.
A disable statement may be used to disable the block or
task which (directly or indirectly) contains the disable,
but may not be used to disable any other blocks or
tasks.
VLOGPT-205 A break or continue statement
must occur within a loop
statement.
Illegal Verilog syntax is encountered.
VLOGPT-206 A return statement must occur
within a task or function.
Illegal Verilog syntax is encountered.
VLOGPT-207 A return in a task or void function
must not have an expression.
Illegal Verilog syntax is encountered.
VLOGPT-208 A return in a non-void function
must have an expression.
Illegal Verilog syntax is encountered.
VLOGPT-321 Internal error. Error encountered during Verilog parsing.
VLOGPT-412 No clock is defined in the always
block.
All the signals in the always block are being used as
data. A clock signal is needed to infer an asynchronous
set-reset flip-flop.
e.g.
reg data_out;
always @(posedge clock or posedge reset)
if ( reset )
data_out = 1'b1;
else
data_out = 1'b0.
VLOGPT-413 More than one clock has been
defined in the always block.
More than one signal in the always block are not used
as data, and these signals may be interpreted as clock
signals. However, only one clock can be used in
inferencing an asynchronous set-reset flip-flop.
reg data_out;
always @(posedge clock or posedge reset)
if ( reset )
data_out = 1'b1;
else
data_out = 1'b0.
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VLOGPT-414 An else statement must be
specified for the clocked logic.
The supported syntax for inferencing an asynchronous
set-reset flip-flop is:
reg data_out;
always @(posedge clock or posedge reset)
if ( reset )
data_out = 1'b1;
else
data_out = 1'b0.
VLOGPT-415 Unsupported use of clock signal
as data.
The supported syntax for inferencing a D flip-flop is:
reg data_out;
always @(posedge clock)
data_out = data_in;
The supported syntax for inferencing a synchronous se
t-reset flip-flop is:
reg data_out;
always @(posedge clock)
if (set_sig)
data_out = 1'b1;
else if (reset_sig)
data_out = 1'b0;
else
data_out = data_in.
VLOGPT-418 Inconsistent reference of edge
signal.
If the set signal 'set_sig' is a posedge signal, the if
statement should use ( set_sig ) as the testing
condition.
e.g.
always @(posedge clk or posedge set_sig)
if ( set_sig)
If the set signal 'set_sig' is a negedge signal, the if stat
ement should use (! set_sig ) as the testing condition.
e.g.
always @(posedge clk or negedge set_sig)
if ( ! set_sig).
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VLOGPT-419 Invalid comparison with edge
signal.
Edge signals may only be compared with 0 or 1.
If the set signal 'set_sig' is a posedge signal, the if
statement should use (set_sig) as the testing condition.
e.g.
always @(posedge clk or posedge set_sig)
if ( set_sig == 1 )
If the set signal 'set_sig' is a negedge signal, the if
statement should use (! set_sig) as the testing
condition.
e.g.
always @(posedge clk or negedge set_sig)
if ( set_sig == 0 )
Two or more signals may be checked using a logical
OR
e.g.
always @(posedge clk or negedge set_sig1 or negedge set_sig2)
if ( set_sig1 == 0 || set_sig2 == 0 ).
VLOGPT-424 Edge signal must be identifier or
bit-select.
Only simple identifiers which are single-bit signals are
allowed when posedge or negedge is used.
e.g. always @(posedge clk) is allowed only if clk is a
single-bit signal
e.g. always @(posedge (clock1 | clock2)) is not
allowed.
VLOGPT-426 Unsupported use of 'iff' with
multiple events.
An 'iff' condition is supported for a combinational
process that is sensitive to at most one signal.
VLOGPT-429 Declarations are not allowed in an
unlabeled block statement.
Illegal Verilog syntax is encountered.
VLOGPT-430 Constant expression required. Illegal Verilog syntax is encountered.
VLOGPT-431 Expecting a comparison to a
signal in the edge event list.
All but one of the edge event specifiers in the event list
of an always block should be checked by an
if-condition. The one unchecked edge event is taken to
be the clock.
VLOGPT-432 Dimension mismatch in
assignment.
Illegal Verilog syntax is encountered.
VLOGPT-433 Inconsistent dimensions in word
concatenation.
Illegal Verilog syntax is encountered.
VLOGPT-435 Type mismatch. Illegal Verilog syntax is encountered.
VLOGPT-436 Inappropriate context for concat
member syntax.
Illegal Verilog syntax is encountered.
VLOGPT-437 Unsupported style of sensitivity list
in Verilog.
Both posedge and negedge of the same signal are not
allowed in an always block.
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VLOGPT-501 Enum pragma may only apply to
parameter or reg.
The correct syntax for enum pragma is:
parameter /* cadence enum myenumtype */
S0 = 2'b00;
S1 = 2'b01;
S2 = 2'b10;
S3 = 2'b11;
reg /* cadence enum myenumtype */ r;
Note that the pragma comes between the reg keyword
and the declared variable
VLOGPT-505 Missing comma in identifier list for
pragma.
Refer to the documentation on where to place pragmas.
VLOGPT-600 Unterminated block comment. A block comment beginning with '/*' must be closed with
a '*/'.
VLOGPT-631 Reference to undefined macro. Error encountered during Verilog parsing.
VLOGPT-632 Quoted string expected for
`include.
Illegal Verilog syntax is encountered.
VLOGPT-633 `else/elsif without `ifdef. Illegal Verilog syntax is encountered.
VLOGPT-634 Missing `ifdef directive. See 'Synthesizing Verilog Designs' in HDL Modeling in
Encounter RTL Compiler for examples on how to model
the `ifdef directive.
VLOGPT-636 Argument list required for macro. Illegal Verilog syntax is encountered.
VLOGPT-637 Mismatched parentheses. Illegal Verilog syntax is encountered.
VLOGPT-638 Expecting identifier for macro
name.
Illegal Verilog syntax is encountered.
VLOGPT-639 Missing formal argument in
definition of macro.
Illegal Verilog syntax is encountered.
VLOGPT-640 Duplicated formal argument in
macro definition.
Illegal Verilog syntax is encountered.
VLOGPT-641 Require closing ')' in macro
definition.
Illegal Verilog syntax is encountered.
VLOGPT-642 Expecting identifier for macro
name.
Illegal Verilog syntax is encountered.
VLOGPT-644 Invalid directive. Verify the directive to make sure the syntax is written
correctly or supported.
VLOGPT-645 Unterminated `if or `ifdef directive. An `if or `ifdef directive must be matched by a
corresponding `endif directive. See `Verilog-2001
Extensions' in the `HDL Modeling in Encounter RTL
Compiler' for more information.
VLOGPT-648 Cannot redefine a compiler
directive.
A compiler directive, such as 'define' or 'undef' cannot
be redefined as a macro name.
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VLOGPT-650 Cannot open file. The specified file could not be opened. Check the
value of the hdl_search_path attribute.
VLOGPT-651 Cannot decrypt protected data. The parser detected an error in decrypting a protected
region of the input source. Possibly the protected data
is corrupted.
VLOGPT-653 Quoted string expected for
`begin_keywords.
The `begin_keywords directive requires a quoted string
version specifier.
VLOGPT-654 Unsupported version specifier for
`begin_keywords.
The supported version specifiers for the
`begin_keywords directive are:
"1365-1995", "1365-2001-noconfig", "1365-2001",
"1365-2005", and "1800-2005".
VLOGPT-655 Mismatched `end_keywords
directive.
An `end_keywords directive was encountered without a
corresponding `begin_keywords directive.
VRO-10 Cannot write generic Verilog for
complex libcell.
Use the 'write_hdl' command with no option to write out
mapped Verilog for complex libcells.
VRO-11 Cannot bit blast module because
of name conflict.
Change the bit-blasting naming style or change the
name of the conflicting instance/port.
VRO-12 The design contains a multi-driver
net requiring a unidirectional wire.
Logic optimization has transformed an illegal
multi-driver net into a configuration that cannot be
represented in Verilog. This can occur with
parallel-driven nets (i.e. clock nets where the
clock-source drives two buffers which reconverge to
drive the same net). In such cases (if the design is not
being unmapped), the parallel-drivers of the net should
be preserved. Otherwise, some of the drivers may be
replaced by a wire during optimization. This would
result in a circuit description that cannot legally be
described in Verilog (but which is valid in the tools
internal representation).
VRO-15 Cannot write netlist. This error condition in the netlist may have been
caused by a command that modifies the netlist, such as
'edit_netlist', 'ungroup'.
VRO-16 Cannot write encrypted netlist. This error condition in the netlist may have been
caused by some incorrect handling of the encrypted
design.
VTIM-100 Unable to open file. Check if the file/directory exists and change
permissions if necessary.
VTIM-101 Unable to find ets executable. Set the value of the ets_executable attribute to the ETS
installation path.
VTIM-105 Error while running ETS. Look at the ETS run script and log file for further
information.
VTIM-106 Invalid command option
combination.
This option combination is not valid for the command
under consideration.
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VTIM-107 File not found. Check if the file/directory exists and change
permissions if necessary.
WDO-101 Something is wrong with the
command-line options.
Check options and rerun command.
WDO-102 There is no design to work on. This command requires a design.
WDO-103 There are multiple top designs.
Specify one.
Rerun command with a specific design.
WDO-104 The specified top design does not
exist.
Check specified design name and rerun command.
WDO-206 The clock-gating style is not
supported in LEC.
There are three styles of clock-gating in RC. Among
them, 'latch' is supported in this RC-to-LEC translation,
'ff' and 'none' are not.
WDO-221 Mention a valid design name. The design name is invalid.
WDO-223 CPF file was not read in. CPF file must be read in to generate a dofile for
Conformal Low Power Checks.
WDO-301 Internal error: Cannot locate a
library or design file that was
successfully loaded into RC.
A specified file cannot be found.
WDO-302 Internal error: Unknown HDL file
format.
The known formats are: -v1995, -v2001, -sv, -vhdl1987,
and -vhdl1993.
WDO-303 Internal error: Unknown undriven
setting.
The known undriven settings are '0', '1', 'X', and 'none'.
WDO-304 Internal error: Unknown dofile
type.
The known dofile types are 1, 2, 3, 5, and 6.
WDO-305 Internal error: Unknown type of
clock net.
The known types of clock nets are 'port' and 'pin'.
WDO-306 Internal error: Unknown type of
test signal.
The known types of DFT test signals are 'shift_enable'
and 'test_mode'.
WDO-307 Internal error: Should not be Type
3 when there is no last_checkpoint
netlist.
If Type 3 is prescribed that there is no last_checkpoint
netlist found, the dofile type is automatically changed
from 3 to 5.
WDO-402 Something is wrong with the
command-line options.
Check options and rerun command.
WDO-406 Design does not exist. Check the design name and rerun the command.
WETT-1 The design contains constraints
which have no SDC equivalent.
If the design constraints were created using the
'derive_environment' command, the '-sdc_only' option
of that command should be used so that only
constraints that can be expressed in SDC are
generated. By default 'derive_environment' uses the
more powerful RC constraints which cannot always be
converted to SDC.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Error Messages
May 2013 291 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
WF-100 Output file has not defined. Check options and rerun command.
WF-101 Output file already exist. Define a new file to avoid overwrite in the existing file.
WF-102 Failed to 'old_write_foundation'. Unsupported options.
WMT-300 Could not check out an
Encounter_Test_Architect license.
Make sure a valid license is available.
WMT-301 Could not free an
Encounter_Test_Architect license.
Make sure a valid license is available.
WMT-302 Exactly 1 top level design is
required for
write_mbist_testbench.
Found more than 1 top level design, make sure there is
only one top level design.
WMT-303 Encounter Test needs to be
installed for
write_mbist_testbench.
Could not find the et script along PATH, make sure
there is a valid Encounter Test installation.
WMT-304 Could not create output directory. Verify permissions are correct, and that there is enough
disk space.
WMT-305 Could not access file. Verify permissions are correct, and that there is enough
disk space.
WMT-306 At least a single input and output
port is required.
Make sure at least 1 input and 1 output port exist.
WMT-307 Could not find the
add_eawoffset.sed contrib script.
Since bitmap patterns were
requested, this contrib script is
required to modify the generated
Verilog testbenches.
Make sure the script is installed in the contrib directory
under the Encounter Test installation area.
WMT-308 The runet.write_mbist_testbench
script ended with an ERROR.
If the runet.write_mbist_testbench script was being
executed, check the testresults/logs directory for the log
for the last command being executed for additional
information, otherwise check for preceding Error
messages.
WMT-309 Unable to determine the directory
containing the interface files
generated by insert_dft mbist.
This directory should be registered with the
mbist_interface_files_location attribute when insert_dft
mbist is executed. Make sure insert_dft mbist has
completed successfully.
WMT-310 Unable to determine the type of
flow (topshell or block), and which
types of patterns to create.
When insert_dft mbist is executed, the command
populates the mbist_wmt_parameters attribute with this
information. Make sure insert_dft mbist has completed
successfully.
WMT-311 Multiple instruction sets have been
detected, and only JTAG patterns
have been requested.
When multiple instructions exist, and only JTAG
patterns have been requested, the instruction set to be
used must be chosen using the
create_embedded_test_options keyword.
WRTV-1 Invalid value of depth. Specify a non-negative value.
Message-ID Title Help
Message Reference for Encounter RTL Compiler
Error Messages
May 2013 292 Product Version 12.2
2003-2013 Cadence Design Systems, Inc. All rights reserved.
WRTV-2 Cannot specify both -abstract and
-depth switches.
Rerun the command specifying only one of the options.
WRTV-3 Cannot undo Bus-Net-Blasting. Rerun the command by setting the TCL var for undo bit
blasting to 0.
WSDF-101 The specified top design does not
exist.
Check specified design name and rerun command.
WSDF-102 The value specified for a
command option is incorrect.
Specify one of the possible values.
WSDF-103 Something is wrong with the
command options.
Check the usage of the command.
WT-1 Invalid option. Use '-simple' option to write out a simple template
script.
WT-2 Invalid option. Failed on 'write_template'.
WT-101 Unsupported option(s). This option(s) is not supported in the current version of
this command.
WT-102 Missing file. The file is not present in the path specified.
WT-103 Unable to open file. An error occurred while opening the file.
Message-ID Title Help