/*******************************************************************************

***********************
* Author :IncMimi
* Module_name :apb_slave.v
* Created_Date : <DD> <MM> <YYYY> ----- Description
* 23-09-2013 Initial Draft
* 25-09-2013 Added Write clear
* Revision :00.02
* Description : apb_slave
* Different types of register confguration
* 1. read_back_write
* 2. write_only
* 3. read_only
* (i) read_clear
* (ii) clear by write bit
********************************************************************************
***********************
* +----------------------------------------------------+
* | REG_ADDR | REG_NAME | // description purpo
se only
* +----------------------------------------------------+
* 0x10 | MODULE_CORE_CNTRL
* 0x11 | MODULE_CORE_STATUS
* 0x20 | MODULE_INT_ENABLE
* 0x21 | MODULE_INT_STATUS
*
********************************************************************************
***********************/
`include module_addr_defines.hv // contains register addresses
module apb_slave (
// Inputs
input wire PCLK ,
input wire PRESETn ,
input wire [7:0] PADDR ,
input wire PSEL ,
input wire PENABLE ,
input wire PWRITE ,
input wire [31:0] PWDATA ,
input wire module_0_process_done_pulse ,
input wire module_1_process_done_pulse ,
input wire [7:0] module_0_trans_count ,
input wire [7:0] module_1_trans_count ,
// Outputs
output wire [31:0] PRADATA ,
output wire PREADY ,
output reg module_start_pulse ,
output reg module_mode_sel ,
output wire cpu_int
);
// Local Wires Decleration
wire peripheral_0_int;
wire peripheral_1_int;
reg module_int_enb ;
assign cpu_int = peripheral_0_int | peripheral_1_int; // CPU interrupt
assign peripheral_0_int = (module_0_int_enb & module_0_int_done) ? 1'b1 : 1'b0 ;

assign peripheral_1_int = (module_1_int_enb & module_1_int_done) ? 1'b1 : 1'b0 ;

assign PREADY = 1'b1;
//***********************
// APB WrITE TRANSACTION
//************************
always @(posedge PCLK, negedge PRESETn) begin // APB WRITE TRANSACTION
if(!PRESETn) begin
module_start_pulse <= 1'b0 ;
module_int_enb <= 1'b0 ;
module_mode_sel <= 1'b0 ;
end
else begin
module_start_pulse <= 1'b0 ;
if(PSEL & PENABLE) begin
if(PWRITE) begin
case(PADDR)
`MODULE_CORE_CNTRL: begin
module_mode_sel <= PWDATA[31]; // 1- Write 0- Read operation
module_start_pulse <= PWDATA[30]; // start pulse which triggers som
e X state machine
end
`MODULE_INT_ENABLE: begin
module_0_int_enb <= PWDATA[0] ;
module_1_int_enb <= PWDATA[1] ;
end
`MODULE_INT_STATUS: begin
module_1_clr_done_int <= PWDATA[31];
end
endcase
end
end
end
//***********************
// APB RAED TRANSACTION
//************************
always @(posedge PCLK, negedge PRESETn)begin
if(!PRESETn) begin
PRDATA <= 'b0;
module_int_done <=1'b0;
end
else begin
if(PSEL & !PENABLE & !PWRITE) // APB READ TRANSACTION
case(PADDR)
`MODULE_CORE_STATUS:begin
PRDATA [0] <= module_0_core_status; // READ back written value
PRDATA [1] <= module_1_core_status; // READ back written value
PRDATA [31:24]<= module_0_trans_count; // READ back written value
PRDATA [23:16]<= module_1_trans_count; // READ back written value
end
`MODULE_INT_STATUS: begin
PRDATA[0] <= module_0_int_done;
PRDATA[1] <= module_1_int_done;
module_0_int_done <= 1'b0; // READ CLEAR
end
endcase
end
if(module_0_process_done_pulse)begin
module_0_int_done <= 1'b1; // latch the process done signals to generate
the CPU interrupt
end
if(module_1_process_done_pulse)begin
module_1_int_done <= 1'b1; // latch the process done signals to generate
the CPU interrupt
end
if(module_1_clr_done_int)begin
module_1_int_done <= 1'b0; // Clears the interrupt
end
end
end
endmodule