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Program 9: 8x4 SRAM Behavioral style Program with enable signal

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SRAM8x4 is
generic( width: integer:=4;
depth: integer:=8;
addr: integer:=3);
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in std_logic_vector(addr-1 downto 0);
Write_Addr: in std_logic_vector(addr-1 downto 0);
Data_in: in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0) );
end SRAM8x4;

architecture behavRAM of SRAM8x4 is

-- use array to define the bunch of internal temparary signals
type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
process(Clock, Read) -- Read Functional Section
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
process(Clock, Write) ---- Write Functional Section
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behavRAM;
--: 8x4 SRAM Behavioral style Program with enable signal is used in FIFO (program no: 9)
-- SRAM will be used as component in FIFO.
-- FIFO depth = SRAM depth
-- FIFO width = SRAM width
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Program : 11: 8 Bytes deep x 4-bit FIFO BEH style
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--- First In First Out --- verified for all cases
--- Depth = 8 , width = 8
--- FIFOEMPTY when 0 elements are in FIFO
--- FIFOFULL when all (8) elements in FIFO
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_module is
Port (
Clk : in std_logic;
Reset : in std_logic;
WriteEnable : in std_logic;
ReadEnable : in std_logic;
DataIn : in std_logic_vector(3 downto 0);
DataOut : out std_logic_vector(3 downto 0);
FifoEmpty : out std_logic;
FifoFull : out std_logic );
end FIFO_module; --- end entity

architecture Behavioral of FIFO_module is

component SRAM8x4
generic( width: integer:=4;
depth: integer:=8;
addr: integer:=3);
port (
Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in std_logic_vector(addr-1 downto 0);
Write_Addr: in std_logic_vector(addr-1 downto 0);
Data_in: in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0) );
end component ;

Signal ReadPointer : std_logic_vector(2 downto 0);

Signal WritePointer : std_logic_vector(2 downto 0);
Signal ReadPointer_s : std_logic_vector(2 downto 0);
Signal WritePointer_s : std_logic_vector(2 downto 0);
Signal ByteCounter : std_logic_vector(3 downto 0);
Signal WriteEnable_s : std_logic;
Signal ReadEnable_s : std_logic;
Signal FifoFull_s : std_logic;
Signal FifoEmpty_s : std_logic;
signal enable_s : std_logic ;
Begin --- architecture begins
FifoSRam : SRAM8x4
generic map(
width => 4 ,
depth => 8 ,
addr => 3)
port map (
Clock => Clk,
Enable => enable_s,
 Read => readenable_s,
Write => writeenable_s,
Read_Addr => ReadPointer_s,
Write_Addr => WritePointer_s,
Data_in => DataIn,
Data_out => DataOut ) ;
Process (Clk, Reset)
Begin
IF ( Reset = '1') then
ReadPointer <= "000";
WritePointer <= "000";
ByteCounter <= "0000"; ---- 4 bits not 3 bits
ELSIF (Clk'event and Clk = '1') then
IF ( WriteEnable = '1' and FifoFull_s = '0' and
ReadEnable = '0') then
WritePointer <= WritePointer + 1;
ByteCounter <= ByteCounter + 1;
END IF;
IF ( ReadEnable = '1' and FifoEmpty_s = '0'
and WriteEnable = '0') then
ReadPointer <= ReadPointer + 1;
ByteCounter <= ByteCounter - 1;
END IF;
END IF;
END process; ---- ReadWriteFifo Process ends
-------- Combinatorial Logic
enable_s <= '1' ;
FifoEmpty_s <= '1' when ( ByteCounter = "000") else '0';
FifoFull_s <= ByteCounter(3);
FifoFull <= FifoFull_s;
FifoEmpty <= FifoEmpty_s;
WriteEnable_s <= '1' when ( WriteEnable = '1' and FifoFull_s = '0') else '0';
ReadEnable_s <= '1' when ( ReadEnable = '1' and FifoEmpty_s = '0') else '0';
WritePointer_s <= WritePointer when ( WriteEnable = '1') else "000" ;
ReadPointer_s <= ReadPointer when ( ReadEnable = '1') else "000" ;
END behavioral; --- architecture ends
---------------------------------------------------------------------------------------------------------------
----STACK LIFO (Program No:12)
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----DEPTH=8 WIDTH=4 ; ----FIRST DATA AT stackpointer=1; last data stackpointer=0
---- stackpointer automatically rollsover, rollsback
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stack is
port (clk : in std_logic ;
reset : in std_logic ;
data_in : in std_logic_vector(3 downto 0) ;
push,pop : in std_logic;
data_out : out std_logic_vector(3 downto 0);
stack_full, stack_empty : out std_logic ;
stack_error : out std_logic) ;
end stack;
architecture Behavioral of stack is
type ram_type is array (0 to 7) of std_logic_vector(3 downto 0);
signal stack_ram: ram_type;
begin
mainproc: process( clk, reset)
variable stack_pointer : std_logic_vector(2 downto 0);
variable stack_full_s : std_logic;
variable stack_empty_s : std_logic;
variable stack_error_s : std_logic;
--variable data_out_s : std_logic ;
begin
--if rising_edge(clk) then
if(clk'event and clk ='1') then
if(reset = '1') then
stack_pointer := "000";
stack_full_s := '0';
stack_empty_s := '1';
stack_error_s :='0' ;
data_out <= "ZZZZ" ;
elsif (push = '1' and stack_full_s = '0') then
stack_pointer := stack_pointer + "001" ;
stack_ram(conv_integer(stack_pointer)) <= data_in;
stack_empty_s := '0';
if(stack_pointer = "000") then
stack_full_s := '1';
end if;
elsif (pop = '1' and stack_empty_s = '0') then
data_out <= stack_ram(conv_integer(stack_pointer));
stack_pointer := stack_pointer - "001" ;
stack_full_s := '0';
if(stack_pointer = "000") then
stack_empty_s := '1';
end if;
end if;
end if;
if (stack_full_s = '1' and stack_empty_s='0') then
stack_error <= '1' ; else stack_error <= '1';
end if ;
stack_full <= stack_full_s ;
stack_empty <= stack_empty_s ;
stack_error <= stack_error_s ;
end process;
end Behavioral ;