823c2 Compal LA-7912P

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Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
4019ID
C
SCHEMATIC,MB A7912
Custom
1 63 Friday, February 10, 2012
2011/06/02 2012/06/02
Compal Electronics, Inc.
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Intel Sandy/Ivy Bridge Processor with DDRIII + Panther Point PCH
Q5WV1 M/B Schematics Document
REV:0.3
Compal Confidential
2012-02-03b
Nvidia N13P GS/GL
Model Name :Q5WV1/Q5WS1
File Name : LA-7912P
Compal Confidential
Compal Project Name :
Part Number Description
DA60000SV00 PCB 0N4 LA-7912P REV0 M/B
MB PCB
Part Number Description
DA60000SV00 PCB 0N4 LA-7912P REV0 M/B
MB PCB
ZZZ2
X76344BOL01
1G@ ZZZ2
X76344BOL01
1G@ ZZZ3
X76344BOL02
2G@ ZZZ3
X76344BOL02
2G@

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Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
USB port 10 USB port 11
100MHz
33MHz
100MHz
LS-7911P
100MHz
1GB/s x4
DMI x4
100MHz
FDI x8
page 41
port 5 port 1
Sub-board
page 39
page 13
SPI
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
RTC CKT.
page 13
3.3V 24MHz
LAN(GbE) &
Card Reader
BCM57785
page 35,36
CMOS Camera
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
Dual Channel
2.7GT/s
Power On/Off CKT.
Touch Pad
LPC BUS
page 41
Processor
Int.KBD
page 40
BANK 0, 1, 2, 3
USB 2.0 conn x2
ALC271X/281X
DC/DC Interface CKT.
Sandy/Ivy Bridge
3.3V 48MHz
RJ45
page 39
Fan Control
Power Circuit DC/DC
page 40
204pin DDRIII-SO-DIMM X2
page 43,44
Intel
BIOS ROM
1.5V DDRIII 1066/1333
page 40
HDA Codec
Memory BUS(DDRIII)
PCH
HD Audio
page 42
page 4~10
Panther Point-M
page 11,12
page 40
ENE KB930/KB9012
page 36
page 38 page 38 page 31
rPGA989
Intel
Bluetooth
Conn
port 2
SATA CDROM
Conn.
page 34
SPI ROM (4M)x1
SPI ROM (1M)x1
page 41
page 46~59
USBx14
page 13~21
port 0
page 34
SATA HDD
Conn.
USB 2.0/B 2Port
USB Port1,2
Int. Speaker Phone Jack x 2
USB port 1,2 on
USB/B
989pin BGA
x16 Gen3(N13P-GS)
x16 Gen2(N13P-GL)
x8 Gen2(N13M-GS) PER LANE 100MHz
133MHz
LVDS Conn.
page 31
CRT Conn.
page 32
Nvidia
N13P GS/GL
N13M-GS
page22~30
PEG(DIS)
page 33
HDMI Conn.
CRT(UMA/OPTIMUS)
LVDS(UMA/OPTIMUS)
TMDS(UMA/OPTIMUS)
USB 3.0
page 38
port 1
Card Reader
Conn.
page 35,36
LS-7912P
page 41
PWR/B
port 1
WLAN
mSATA(reserve)
page 34
USB port 8
port 2
eDP
page31
USB3.0
USB 3.0
Fresco FL1009
USB3.0 Conn.
page 17
page 39

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Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
USB 2.0 USB 1.1 Port
3 External
USB Port
Camera
USB/B (Right Side)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
EHCI1
EHCI2
USB Port Table
1101 0010b
ON OFF OFF
Board ID / SKU ID Table for AD channel
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator
+RTCVCC RTC power
+1.5VS
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
+3VS
+5VALW
+3VALW +3VALW always on power rail
+VSB +VSBP to +VSB always on power rail for sequence control ON ON*
ON ON
ON
ON BOARD ID Table
EC SM Bus1 address
Device
OFF
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
+1.5V to +1.5VS switched power rail
+CPU_CORE
STATE
SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Vcc 3.3V +/- 5%
100K +/- 5% Ra/Rc/Re
Board ID
Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID V typ AD_BID VAD_BID max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7 NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
PCH SM Bus address
Device
Clock Generator (9LVS3199AKLFT,
RTM890N-631-VB-GRT)
Address
Address Address
Voltage Rails
VIN
B+
+1.05VS_VTT
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
ON
OFF
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ON
ON
ON ON*
OFF
OFF
0.2
BTO Option Table
BTO Item BOM Structure
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOW LOW LOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGH HIGH HIGH
HIGH
HIGH
HIGH
ON ON*
ON OFF OFF
+3VALW_PCH
+3V_LAN
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
+3VALW to +3V_LAN power rail for LAN
ON ON
ON ON
S1
+5VALW_PCH
S3 S5
ON
ON
ON ON
OFF
N/A N/A N/A
N/A N/A N/A
Power Plane Description
EC SM Bus2 address
Device
Smart Battery
OFF
OFF
+1.5VP to +1.5V power rail for DDRIII ON ON OFF
0.3
0001 011X b
ON*
OFF
DIS@ Dis with OPTIMUS
Blue Tooth BT@
Mini Card 1(WLAN)
+1.5V
+1.05VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH
ON OFF OFF
+VGA_CORE
ON OFF OFF
Core voltage for GPU
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
+3VALW_EC +3VALW always to KBC ON ON ON*
ON*
+3VALW to +3VS power rail
+5VALWP to +5VALW power rail
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
+5VS +5VALW to +5VS switched power rail OFF ON OFF
ON*
UMAO@ UMA Only
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF
Internal USB 3.0 PUSB3@
0.4
GS@ N13P-GS
N13P-GL GL@
Unpop
VRAM
CONN@ Connector
@
X76@
Win8
Audio ALC281X
271X@
Win8@
Audio ALC271X
281X@
PCH HM65 HM65@
PCH HM76 HM76@
BlueTooth
USB/B (Right Side)
USB3.0 colay USB2.0 Conn
eDP eDP@
Internal USB 2.0 PUSB@
USB 2.0 flag PUSB2@
N13P-GS & GL GSGL@
N13M-GS GM@
4319IDBOL01SMT MB A7912 Q5WV1 HM77 QC UMA 3
4319IDBOL02SMT MB A7912 Q5WV1 HM77 QC 13PGL1G 3
4319IDBOL03SMT MB A7912 Q5WV1 HM77 QC 13PGL2G 3
4319IDBOL04SMT MB A7912 Q5WV1 HM77 QC 13PGS1G 3
4319IDBOL05SMT MB A7912 Q5WV1 HM77 QC 13PGS2G 3
4319IDBOL06SMT MB A7912 Q5WV1 HM77 DC UMA 2
4319IDBOL07SMT MB A7912 Q5WV1 HM77 DC UMA 3
4319IDBOL08SMT MB A7912 Q5WV1 HM77 DC 13PGL1G 2
4319IDBOL12SMT MB A7912 Q5WV1 HM77 DC 13MGS1G 2
4319IDBOL13SMT MB A7912 Q5WV1 HM77 DC 13MGS1G 3
4319IDBOL14SMT MB A7912 Q5WV1 HM77 DC 13PGS2G 3
support AC function
no AC function
AC@
NOAC@

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3
2
2
1
1
D D
C C
B B
A A
EDP_COMP
PEG_COMP
PEG_GTX_C_HRX_N0 PEG_GTX_HRX_N0
PEG_GTX_HRX_P0 PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_P8 PEG_GTX_HRX_P8
PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0
PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0
EDP_HPD#
DMI_CTX_PRX_P0 <15>
DMI_CRX_PTX_P0 <15>
DMI_CTX_PRX_N1 <15>
DMI_CRX_PTX_N1 <15>
DMI_CTX_PRX_P3 <15>
DMI_CRX_PTX_P3 <15>
DMI_CTX_PRX_P2 <15>
DMI_CTX_PRX_N0 <15>
DMI_CRX_PTX_N3 <15>
DMI_CRX_PTX_P2 <15>
DMI_CTX_PRX_N3 <15>
DMI_CTX_PRX_P1 <15>
DMI_CRX_PTX_N0 <15>
DMI_CRX_PTX_N2 <15>
DMI_CRX_PTX_P1 <15>
DMI_CTX_PRX_N2 <15>
FDI_CTX_PRX_N0 <15>
FDI_CTX_PRX_N1 <15>
FDI_CTX_PRX_N2 <15>
FDI_CTX_PRX_N3 <15>
FDI_CTX_PRX_N4 <15>
FDI_CTX_PRX_N5 <15>
FDI_CTX_PRX_N6 <15>
FDI_CTX_PRX_N7 <15>
FDI_CTX_PRX_P0 <15>
FDI_CTX_PRX_P1 <15>
FDI_CTX_PRX_P2 <15>
FDI_CTX_PRX_P3 <15>
FDI_CTX_PRX_P4 <15>
FDI_CTX_PRX_P5 <15>
FDI_CTX_PRX_P6 <15>
FDI_CTX_PRX_P7 <15>
FDI_FSYNC0 <15>
FDI_FSYNC1 <15>
FDI_INT <15>
FDI_LSYNC0 <15>
FDI_LSYNC1 <15>
PEG_GTX_HRX_N[0..15] <22>
PEG_HTX_C_GRX_P[0..15] <22>
PEG_HTX_C_GRX_N[0..15] <22>
PEG_GTX_HRX_P[0..15] <22>
EDP_HPD# <31>
EDP_AUXP <31>
EDP_AUXN <31>
EDP_TXP0 <31>
EDP_TXP1 <31>
EDP_TXN0 <31>
EDP_TXN1 <31>
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
eDP_COMPIO and ICOMPO signals should
be shorted near balls,
Trace Width for EDP_COMPIO=4mils,
EDP_ICOMPO=12mils,
and both length less than 500 mils...
should not be left floating
,even if disable eDP function...
PEG_ICOMPI and PEG_RCOMPO signals should be
shorted and routed,
max length = 500 mils,trace width=4mils
PEG_ICOMPO signals should be routed with - max
length = 500 mils,trace width=12mils
spacing =15mils
Add eDP circuit
C533 0.22U_0402_10V6K GSGL@ C533 0.22U_0402_10V6K GSGL@ 1 2
C93 0.22U_0402_10V6K DIS@ C93 0.22U_0402_10V6K DIS@ 1 2
C548 0.22U_0402_10V6K DIS@ C548 0.22U_0402_10V6K DIS@ 1 2
C560 0.22U_0402_10V6K DIS@ C560 0.22U_0402_10V6K DIS@ 1 2
C550 0.22U_0402_10V6K DIS@ C550 0.22U_0402_10V6K DIS@ 1 2
C552 0.22U_0402_10V6K DIS@ C552 0.22U_0402_10V6K DIS@ 1 2
C553 0.22U_0402_10V6K DIS@ C553 0.22U_0402_10V6K DIS@ 1 2
C547 0.22U_0402_10V6K DIS@ C547 0.22U_0402_10V6K DIS@ 1 2
R809
1K_0402_5% EDP@
R809
1K_0402_5% EDP@
1
2
R145
24.9_0402_1%
R145
24.9_0402_1%
1
2
C558 0.22U_0402_10V6K DIS@ C558 0.22U_0402_10V6K DIS@ 1 2
C546 0.22U_0402_10V6K DIS@ C546 0.22U_0402_10V6K DIS@ 1 2
C125 0.22U_0402_10V6K DIS@ C125 0.22U_0402_10V6K DIS@ 1 2
C100 0.22U_0402_10V6K DIS@ C100 0.22U_0402_10V6K DIS@ 1 2
C113 0.22U_0402_10V6K DIS@ C113 0.22U_0402_10V6K DIS@ 1 2
C557 0.22U_0402_10V6K DIS@ C557 0.22U_0402_10V6K DIS@ 1 2
C561 0.22U_0402_10V6K DIS@ C561 0.22U_0402_10V6K DIS@ 1 2
C559 0.22U_0402_10V6K DIS@ C559 0.22U_0402_10V6K DIS@ 1 2
P
C
I

E
X
P
R
E
S
S
*

-

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R
A
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I
C
S
D
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I
n
t
e
l
(
R
)

F
D
I
e
D
P
J CPU1A
TYCO_2013620-2_IVY BRIDGE
CONN@
P
C
I

E
X
P
R
E
S
S
*

-

G
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A
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(
R
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F
D
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e
D
P
J CPU1A
CONN@
DMI_RX#[0]
B27
DMI_RX#[1]
B25
DMI_RX#[2]
A25
DMI_RX#[3]
B24
DMI_RX[0]
B28
DMI_RX[1]
B26
DMI_RX[2]
A24
DMI_RX[3]
B23
DMI_TX#[0]
G21
DMI_TX#[1]
E22
DMI_TX#[2]
F21
DMI_TX#[3]
D21
DMI_TX[0]
G22
DMI_TX[1]
D22
DMI_TX[3]
C21
DMI_TX[2]
F20
FDI0_TX#[0]
A21
FDI0_TX#[1]
H19
FDI0_TX#[2]
E19
FDI0_TX#[3]
F18
FDI1_TX#[0]
B21
FDI1_TX#[1]
C20
FDI1_TX#[2]
D18
FDI1_TX#[3]
E17
FDI0_TX[0]
A22
FDI0_TX[1]
G19
FDI0_TX[2]
E20
FDI0_TX[3]
G18
FDI1_TX[0]
B20
FDI1_TX[1]
C19
FDI1_TX[2]
D19
FDI1_TX[3]
F17
FDI0_FSYNC
J 18
FDI1_FSYNC
J 17
FDI_INT
H20
FDI0_LSYNC
J 19
FDI1_LSYNC
H17
PEG_ICOMPI
J 22
PEG_ICOMPO
J 21
PEG_RCOMPO
H22
PEG_RX#[0]
K33
PEG_RX#[1]
M35
PEG_RX#[2]
L34
PEG_RX#[3]
J 35
PEG_RX#[4]
J 32
PEG_RX#[5]
H34
PEG_RX#[6]
H31
PEG_RX#[7]
G33
PEG_RX#[8]
G30
PEG_RX#[9]
F35
PEG_RX#[10]
E34
PEG_RX#[11]
E32
PEG_RX#[12]
D33
PEG_RX#[13]
D31
PEG_RX#[14]
B33
PEG_RX#[15]
C32
PEG_RX[0]
J 33
PEG_RX[1]
L35
PEG_RX[2]
K34
PEG_RX[3]
H35
PEG_RX[4]
H32
PEG_RX[5]
G34
PEG_RX[6]
G31
PEG_RX[7]
F33
PEG_RX[8]
F30
PEG_RX[9]
E35
PEG_RX[10]
E33
PEG_RX[11]
F32
PEG_RX[12]
D34
PEG_RX[13]
E31
PEG_RX[14]
C33
PEG_RX[15]
B32
PEG_TX#[0]
M29
PEG_TX#[1]
M32
PEG_TX#[2]
M31
PEG_TX#[3]
L32
PEG_TX#[4]
L29
PEG_TX#[5]
K31
PEG_TX#[6]
K28
PEG_TX#[7]
J 30
PEG_TX#[8]
J 28
PEG_TX#[9]
H29
PEG_TX#[10]
G27
PEG_TX#[11]
E29
PEG_TX#[12]
F27
PEG_TX#[13]
D28
PEG_TX#[14]
F26
PEG_TX#[15]
E25
PEG_TX[0]
M28
PEG_TX[1]
M33
PEG_TX[2]
M30
PEG_TX[3]
L31
PEG_TX[4]
L28
PEG_TX[5]
K30
PEG_TX[6]
K27
PEG_TX[7]
J 29
PEG_TX[8]
J 27
PEG_TX[9]
H28
PEG_TX[10]
G28
PEG_TX[11]
E28
PEG_TX[12]
F28
PEG_TX[13]
D27
PEG_TX[14]
E26
PEG_TX[15]
D25
eDP_AUX
C15
eDP_AUX#
D15
eDP_TX[0]
C17
eDP_TX[1]
F16
eDP_TX[2]
C16
eDP_TX[3]
G15
eDP_TX#[0]
C18
eDP_TX#[1]
E16
eDP_TX#[2]
D16
eDP_TX#[3]
F15
eDP_COMPIO
A18
eDP_HPD#
B16
eDP_ICOMPO
A17
C144 0.22U_0402_10V6K DIS@ C144 0.22U_0402_10V6K DIS@ 1 2
C129 0.22U_0402_10V6K DIS@ C129 0.22U_0402_10V6K DIS@ 1 2
C555 0.22U_0402_10V6K DIS@ C555 0.22U_0402_10V6K DIS@ 1 2
C138 0.22U_0402_10V6K DIS@ C138 0.22U_0402_10V6K DIS@ 1 2
C102 0.22U_0402_10V6K DIS@ C102 0.22U_0402_10V6K DIS@ 1 2
C111 0.22U_0402_10V6K DIS@ C111 0.22U_0402_10V6K DIS@ 1 2
C92 0.22U_0402_10V6K DIS@ C92 0.22U_0402_10V6K DIS@ 1 2
C135 0.22U_0402_10V6K DIS@ C135 0.22U_0402_10V6K DIS@ 1 2
C119 0.22U_0402_10V6K DIS@ C119 0.22U_0402_10V6K DIS@ 1 2
C549 0.22U_0402_10V6K DIS@ C549 0.22U_0402_10V6K DIS@ 1 2
C556 0.22U_0402_10V6K DIS@ C556 0.22U_0402_10V6K DIS@ 1 2
C551 0.22U_0402_10V6K DIS@ C551 0.22U_0402_10V6K DIS@ 1 2
C89 0.22U_0402_10V6K DIS@ C89 0.22U_0402_10V6K DIS@ 1 2
R517
24.9_0402_1%
R517
24.9_0402_1%
1
2
C105 0.22U_0402_10V6K DIS@ C105 0.22U_0402_10V6K DIS@ 1 2
C554 0.22U_0402_10V6K DIS@ C554 0.22U_0402_10V6K DIS@ 1 2
C117 0.22U_0402_10V6K DIS@ C117 0.22U_0402_10V6K DIS@ 1 2
C106 0.22U_0402_10V6K DIS@ C106 0.22U_0402_10V6K DIS@ 1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_CATERR#
CLK_CPU_DMI#
CLK_CPU_DMI
H_THRMTRIP#
H_PROCHOT#_R
H_PM_SYNC
PM_DRAM_PWRGD_R
BUF_CPU_RST#
SM_RCOMP1
SM_RCOMP2
SM_RCOMP0
SM_DRAMRST# H_PECI
H_PROCHOT#
BUFO_CPU_RST#
PLT_RST#
H_CPUPWRGD
XDP_DBRESET#
TCK
TMS
TRST#
TDI
TDO
CLK_CPU_DPLL
CLK_CPU_DPLL# CLK_CPU_DPLL
CLK_CPU_DPLL#
PM_DRAM_PWRGD_R PM_SYS_PWRGD_BUF
BUF_CPU_RST# BUF_CPU_RST#
H_PECI <18,40>
H_SNB_IVB# <17>
H_PM_SYNC <15>
H_THRMTRIP# <18>
H_CPUPWRGD <18>
H_PROCHOT# <40,46>
SM_DRAMRST# <6>
CLK_CPU_DMI# <14>
CLK_CPU_DMI <14>
PLT_RST# <17>
XDP_DBRESET# <15>
CLK_CPU_DPLL <14>
CLK_CPU_DPLL# <14>
PM_DRAM_PWRGD <15>
SYS_PWROK <15>
+1.05VS_VTT
+3VS
+1.05VS_VTT
+3VS
+1.05VS_VTT
+3VALW
+1.5VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
DDR3 Compensation Signals
Processor Pullups
SNB_IVB# had changed the name to
PROC_SELCT#,function for future platform,
connect to the DF_TVS strap on the PCH
SM_DRAMPWROK:DRAM power ok
UNCOREPWRGOOD:]COREOK
Buffered reset to CPU
RESET#:ok__CPUreset
For LVDS
If use External Graphic or
use integrated without eDP
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
For eDP
R04 modify
R231 140_0402_1% R231 140_0402_1% 1 2
T6 PAD
@
T6 PAD
@
R90
75_0402_1%
R90
75_0402_1%
1
2
R40
1K_0402_5%
R40
1K_0402_5%
1
2
C2090
0.1U_0402_16V4Z
C2090
0.1U_0402_16V4Z
1
2
C162
0.1U_0402_16V4Z
C162
0.1U_0402_16V4Z
1
2
R88
0_0402_5%
@
R88
0_0402_5%
@
1
2
R203
39_0402_1%
@
R203
39_0402_1%
@
1
2
R516 1K_0402_5% LVDS@ R516 1K_0402_5% LVDS@ 1 2
R204 130_0402_5% R204 130_0402_5%
1 2
C
L
O
C
K
S
M
I
S
C
T
H
E
R
M
A
L
P
W
R

M
A
N
A
G
E
M
E
N
T
D
D
R
3

M
I
S
C
J
T
A
G

&

B
P
M
J CPU1B
CONN@
C
L
O
C
K
S
M
I
S
C
T
H
E
R
M
A
L
P
W
R

M
A
N
A
G
E
M
E
N
T
D
D
R
3

M
I
S
C
J
T
A
G

&

B
P
M
J CPU1B
CONN@
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DRAMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCLK
A28
DPLL_REF_CLK#
A15
DPLL_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THERMTRIP#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRDY#
AP29
PREQ#
AP27
TCK
AR26
TMS
AR27
TRST#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
R518 1K_0402_5% LVDS@ R518 1K_0402_5% LVDS@ 1 2
R205
200_0402_1%
R205
200_0402_1%
1
2
C307
0.1U_0402_16V4Z
C307
0.1U_0402_16V4Z
1
2
R571 200_0402_1% R571 200_0402_1% 1 2
R84 10K_0402_5% R84 10K_0402_5% 1 2
T70 PAD
@
T70 PAD
@
U7
SN74LVC1G07DCKR_SC70-5
U7
SN74LVC1G07DCKR_SC70-5
NC
1
A
2
G
3
Y
4
P
5
T69 PAD
@
T69 PAD
@
R566 25.5_0402_1% R566 25.5_0402_1% 1 2
T68 PAD
@
T68 PAD
@
R87
43_0402_1%
R87
43_0402_1%
1 2
T67 PAD
@
T67 PAD
@
U11
74AHC1G09GW_TSSOP5
U11
74AHC1G09GW_TSSOP5
B
1
A
2
G
3
O
4
P
5
R91 62_0402_5% R91 62_0402_5% 1 2 R92
56_0402_5%
R92
56_0402_5%
1 2
T66 PAD
@
T66 PAD
@

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D63
DDR_A_D62
DDR_A_D8
DDR_A_D3
DDR_A_D4
DDR_A_D7
DDR_A_D5
DDR_A_D6
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D47
DDR_A_D46
DDR_A_D42
DDR_A_D43
DDR_A_D34
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_D35
DDR_A_D41
DDR_A_D40
DDR_A_D38
DDR_A_D36
DDR_A_D37
DDR_A_D32
DDR_A_D33
DDR_A_D61
DDR_A_D60
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_D55
DDR_A_D54
DDR_A_D51
DDR_A_D48
DDR_A_D50
DDR_A_D49
DDR_A_D52
DDR_A_D53
DDR_A_D31
DDR_A_D14
DDR_A_D15
DDR_A_D25
DDR_A_D24
DDR_A_D26
DDR_A_D27
DDR_A_D30
DDR_A_D9
DDR_A_D13
DDR_A_D12
DDR_A_D10
DDR_A_D11
DDR_A_D29
DDR_A_D28
DDR_A_D19
DDR_A_D20
DDR_A_D16
DDR_A_D21
DDR_A_D17
DDR_A_D22
DDR_A_D18
DDR_A_D23
DDR_A_MA15
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DQS1
DDR_A_DQS6
DDR_A_DQS5
DDR_A_DQS4
DDR_A_DQS3
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS#0
DDR_A_DQS#2
DDR_A_DQS#5
DDR_A_DQS#3
DDR_A_DQS#1
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_MA0
DDR_A_MA14
DDR_A_MA5
DDR_A_MA4
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA9
DDR_A_MA7
DDR_A_MA6
DDR_A_MA12
DDR_A_MA13
DDR_A_MA8
DDR_A_MA11
DDR_A_MA10
DDR_B_D33
DDR_B_D14
DDR_B_D42
DDR_B_D59
DDR_B_D63
DDR_B_D43
DDR_B_D55
DDR_B_D53
DDR_B_D29
DDR_B_D24
DDR_B_D34
DDR_B_D4
DDR_B_D26
DDR_B_D13
DDR_B_D10
DDR_B_D21
DDR_B_D11
DDR_B_D57
DDR_B_D44
DDR_B_D0
DDR_B_D7
DDR_B_D46
DDR_B_D3
DDR_B_D15
DDR_B_D27
DDR_B_D30
DDR_B_D35
DDR_B_D40
DDR_B_D49
DDR_B_D23
DDR_B_D25
DDR_B_D19
DDR_B_D37
DDR_B_D48
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D47
DDR_B_D9
DDR_B_D60
DDR_B_D50
DDR_B_D62
DDR_B_D52
DDR_B_D2
DDR_B_D51
DDR_B_D56
DDR_B_D39
DDR_B_D22
DDR_B_D28
DDR_B_D6
DDR_B_D45
DDR_B_D17
DDR_B_D58
DDR_B_D61
DDR_B_D31
DDR_B_D54
DDR_B_D1
DDR_B_D41
DDR_B_D5
DDR_B_D12
DDR_B_D20
DDR_B_D38
DDR_B_D32
DDR_B_D16
DDR_B_MA15
DDR_B_DQS#1
DDR_B_DQS#7
DDR_B_DQS#5
DDR_B_DQS#4
DDR_B_DQS#0
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#2
DDR_B_DQS7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS6
DDR_B_MA0
DDR_B_MA9
DDR_B_MA7
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_B_MA11
DDR_B_MA3
DDR_B_MA5
DDR_B_MA6
DDR_B_MA10
DDR_B_MA8
DDR_B_MA1
DDR_B_MA12
DDR_B_MA14
DIMM_DRAMRST#_R SM_DRAMRST#
DDR_A_D[0..63] <11>
DDR_A_BS0 <11>
DDR_A_BS1 <11>
DDR_A_BS2 <11>
DDR_A_WE# <11>
DDR_A_RAS# <11>
DDR_A_CAS# <11>
SA_CLK_DDR0 <11>
SA_CLK_DDR#0 <11>
DDRA_CKE0_DIMMA <11>
SA_CLK_DDR1 <11>
SA_CLK_DDR#1 <11>
DDRA_CKE1_DIMMA <11>
DDRA_CS0_DIMMA# <11>
DDRA_CS1_DIMMA# <11>
SA_ODT0 <11>
SA_ODT1 <11>
DDR_A_DQS#[0..7] <11>
DDR_A_DQS[0..7] <11>
DDR_B_BS0 <12>
DDR_B_BS1 <12>
DDR_B_BS2 <12>
DDR_B_D[0..63] <12>
DDR_B_WE# <12>
DDR_B_RAS# <12>
DDR_B_CAS# <12>
DDRB_CS1_DIMMB# <12>
DDR_B_DQS[0..7] <12>
DDR_B_DQS#[0..7] <12>
SB_CLK_DDR0 <12>
SB_CLK_DDR#0 <12>
DDRB_CKE0_DIMMB <12>
SB_CLK_DDR1 <12>
DDRB_CS0_DIMMB# <12>
SB_ODT1 <12>
SB_ODT0 <12>
DDRB_CKE1_DIMMB <12>
SB_CLK_DDR#1 <12>
DDR_A_MA[0..15] <11> DDR_B_MA[0..15] <12>
DIMM_DRAMRST# <11,12> SM_DRAMRST# <5>
RST_GATE <11,12,14>
+1.5V
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
CPU_DIMMreset
S0
RST_GATE hgih ,MOS ON
SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH
Dimm not reset
S3
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# HIGH
Dimm not reset
S4,5
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# low
Dimm reset
Follow CRB1.0
R02 modify for ESD
R184
0_0402_5%
@R184
0_0402_5%
@
1 2
G
D S
Q12
S TR SSM3K7002F 1N SC59-3
G
D S
Q12
2
1 3
R155
1K_0402_5%
R155
1K_0402_5%
1 2
R186
4.99K_0402_1%
R186
4.99K_0402_1%
1
2
D
D
R

S
Y
S
T
E
M

M
E
M
O
R
Y

B
J CPU1D
CONN@
D
D
R

S
Y
S
T
E
M

M
E
M
O
R
Y

B
J CPU1D
CONN@
SB_BS[0]
AA9
SB_BS[1]
AA7
SB_BS[2]
R6
SB_CAS#
AA10
SB_RAS#
AB8
SB_WE#
AB9
SB_CLK[0]
AE2
SB_CLK[1]
AE1
SB_CLK#[0]
AD2
SB_CLK#[1]
AD1
SB_CKE[0]
R9
SB_CKE[1]
R10
SB_ODT[0]
AE4
SB_ODT[1]
AD4
SB_DQS[4]
AN6
SB_DQS#[4]
AN5
SB_DQS[5]
AP8
SB_DQS#[5]
AP9
SB_DQS[6]
AK11
SB_DQS#[6]
AK12
SB_DQS[7]
AP14
SB_DQS#[7]
AP15
SB_DQS[0]
C7
SB_DQS#[0]
D7
SB_DQS[1]
G3
SB_DQS#[1]
F3
SB_DQS[2]
J 6
SB_DQS#[2]
K6
SB_DQS[3]
M3
SB_DQS#[3]
N3
SB_MA[0]
AA8
SB_MA[1]
T7
SB_MA[2]
R7
SB_MA[3]
T6
SB_MA[4]
T2
SB_MA[5]
T4
SB_MA[6]
T3
SB_MA[7]
R2
SB_MA[8]
T5
SB_MA[9]
R3
SB_MA[10]
AB7
SB_MA[11]
R1
SB_MA[12]
T1
SB_MA[13]
AB10
SB_MA[14]
R5
SB_MA[15]
R4
SB_DQ[0]
C9
SB_DQ[1]
A7
SB_DQ[2]
D10
SB_DQ[3]
C8
SB_DQ[4]
A9
SB_DQ[5]
A8
SB_DQ[6]
D9
SB_DQ[7]
D8
SB_DQ[8]
G4
SB_DQ[9]
F4
SB_DQ[10]
F1
SB_DQ[11]
G1
SB_DQ[12]
G5
SB_DQ[13]
F5
SB_DQ[14]
F2
SB_DQ[15]
G2
SB_DQ[16]
J 7
SB_DQ[17]
J 8
SB_DQ[18]
K10
SB_DQ[19]
K9
SB_DQ[20]
J 9
SB_DQ[21]
J 10
SB_DQ[22]
K8
SB_DQ[23]
K7
SB_DQ[24]
M5
SB_DQ[25]
N4
SB_DQ[26]
N2
SB_DQ[27]
N1
SB_DQ[28]
M4
SB_DQ[29]
N5
SB_DQ[30]
M2
SB_DQ[31]
M1
SB_DQ[32]
AM5
SB_DQ[33]
AM6
SB_DQ[34]
AR3
SB_DQ[35]
AP3
SB_DQ[36]
AN3
SB_DQ[37]
AN2
SB_DQ[38]
AN1
SB_DQ[39]
AP2
SB_DQ[40]
AP5
SB_DQ[41]
AN9
SB_DQ[42]
AT5
SB_DQ[43]
AT6
SB_DQ[44]
AP6
SB_DQ[45]
AN8
SB_DQ[46]
AR6
SB_DQ[47]
AR5
SB_DQ[48]
AR9
SB_DQ[49]
AJ 11
SB_DQ[50]
AT8
SB_DQ[51]
AT9
SB_DQ[52]
AH11
SB_DQ[53]
AR8
SB_DQ[54]
AJ 12
SB_DQ[55]
AH12
SB_DQ[56]
AT11
SB_DQ[57]
AN14
SB_DQ[58]
AR14
SB_DQ[59]
AT14
SB_DQ[60]
AT12
SB_DQ[61]
AN15
SB_DQ[62]
AR15
SB_DQ[63]
AT15
RSVD_TP[11]
AB2
RSVD_TP[12]
AA2
RSVD_TP[13]
T9
RSVD_TP[14]
AA1
RSVD_TP[15]
AB1
RSVD_TP[16]
T10
SB_CS#[0]
AD3
SB_CS#[1]
AE3
RSVD_TP[17]
AD6
RSVD_TP[18]
AE6
RSVD_TP[19]
AD5
RSVD_TP[20]
AE5
R217
1K_0402_5%
R217
1K_0402_5%
1
2
C2065
0.1U_0402_16V4Z
C2065
0.1U_0402_16V4Z
1
2
D
D
R

S
Y
S
T
E
M

M
E
M
O
R
Y

A
J CPU1C
CONN@
D
D
R

S
Y
S
T
E
M

M
E
M
O
R
Y

A
J CPU1C
CONN@
SA_BS[0]
AE10
SA_BS[1]
AF10
SA_BS[2]
V6
SA_CAS#
AE8
SA_RAS#
AD9
SA_WE#
AF9
SA_CLK[0]
AB6
SA_CLK[1]
AA5
SA_CLK#[0]
AA6
SA_CLK#[1]
AB5
SA_CKE[0]
V9
SA_CKE[1]
V10
SA_CS#[0]
AK3
SA_CS#[1]
AL3
SA_ODT[0]
AH3
SA_ODT[1]
AG3
SA_DQS[0]
D4
SA_DQS#[0]
C4
SA_DQS[1]
F6
SA_DQS#[1]
G6
SA_DQS[2]
K3
SA_DQS#[2]
J 3
SA_DQS[3]
N6
SA_DQS#[3]
M6
SA_DQS[4]
AL5
SA_DQS#[4]
AL6
SA_DQS[5]
AM9
SA_DQS#[5]
AM8
SA_DQS[6]
AR11
SA_DQS#[6]
AR12
SA_DQS[7]
AM14
SA_DQS#[7]
AM15
SA_MA[0]
AD10
SA_MA[1]
W1
SA_MA[2]
W2
SA_MA[3]
W7
SA_MA[4]
V3
SA_MA[5]
V2
SA_MA[6]
W3
SA_MA[7]
W6
SA_MA[8]
V1
SA_MA[9]
W5
SA_MA[10]
AD8
SA_MA[11]
V4
SA_MA[12]
W4
SA_MA[13]
AF8
SA_MA[14]
V5
SA_MA[15]
V7
SA_DQ[0]
C5
SA_DQ[1]
D5
SA_DQ[2]
D3
SA_DQ[3]
D2
SA_DQ[4]
D6
SA_DQ[5]
C6
SA_DQ[6]
C2
SA_DQ[7]
C3
SA_DQ[8]
F10
SA_DQ[9]
F8
SA_DQ[10]
G10
SA_DQ[11]
G9
SA_DQ[12]
F9
SA_DQ[13]
F7
SA_DQ[14]
G8
SA_DQ[15]
G7
SA_DQ[16]
K4
SA_DQ[17]
K5
SA_DQ[18]
K1
SA_DQ[19]
J 1
SA_DQ[20]
J 5
SA_DQ[21]
J 4
SA_DQ[22]
J 2
SA_DQ[23]
K2
SA_DQ[24]
M8
SA_DQ[25]
N10
SA_DQ[26]
N8
SA_DQ[27]
N7
SA_DQ[28]
M10
SA_DQ[29]
M9
SA_DQ[30]
N9
SA_DQ[31]
M7
SA_DQ[32]
AG6
SA_DQ[33]
AG5
SA_DQ[34]
AK6
SA_DQ[35]
AK5
SA_DQ[36]
AH5
SA_DQ[37]
AH6
SA_DQ[38]
AJ 5
SA_DQ[39]
AJ 6
SA_DQ[40]
AJ 8
SA_DQ[41]
AK8
SA_DQ[42]
AJ 9
SA_DQ[43]
AK9
SA_DQ[44]
AH8
SA_DQ[45]
AH9
SA_DQ[46]
AL9
SA_DQ[47]
AL8
SA_DQ[48]
AP11
SA_DQ[49]
AN11
SA_DQ[50]
AL12
SA_DQ[51]
AM12
SA_DQ[52]
AM11
SA_DQ[53]
AL11
SA_DQ[54]
AP12
SA_DQ[55]
AN12
SA_DQ[56]
AJ 14
SA_DQ[57]
AH14
SA_DQ[58]
AL15
SA_DQ[59]
AK15
SA_DQ[60]
AL14
SA_DQ[61]
AK14
SA_DQ[62]
AJ 15
SA_DQ[63]
AH15
RSVD_TP[1]
AB4
RSVD_TP[2]
AA4
RSVD_TP[4]
AB3
RSVD_TP[5]
AA3
RSVD_TP[3]
W9
RSVD_TP[6]
W10
RSVD_TP[7]
AG1
RSVD_TP[8]
AH1
RSVD_TP[9]
AG2
RSVD_TP[10]
AH2
C293
0.047U_0402_16V7K
C293
0.047U_0402_16V7K
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VSSAXG_VAL_SENSE
CFG4
CFG6
CFG5
CFG2
CFG7
VCC_VAL_SENSE
CFG2
CFG0
CFG4
CFG5
CFG6
CFG7
VAXG_VAL_SENSE
VSS_VAL_SENSE
+CPU_CORE +VGFX_CORE
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
AH27 change to VCC_DIE_SENSE
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
PCIE Port Bifurcation Straps
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG7
PEG DEFER TRAINING
0: PEG Wait for BIOS for training
1: (Default) PEG Train immediately following xxRESETB
de assertion
CFG4
Display Port Presence Strap
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG Straps for Processor
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1: Normal Operation; Lane # definition matches
socket pin map definition
*
*
*
AH26
Sandy Ivy
VSS_DIE_SENSE GND
RSVD54 and RSVD55 had changed to
BCLK_ITP and BCLK_ITP#
R102
1K_0402_5% @
R102
1K_0402_5% @
1
2
R108
1K_0402_5% @
R108
1K_0402_5% @
1
2
R109
1K_0402_5%
EDP@
R109
1K_0402_5%
EDP@
1
2
R107
1K_0402_5%
GM@
R107
1K_0402_5%
GM@
1
2
T74 PAD @ T74 PAD @
R112
1K_0402_5%
R112
1K_0402_5%
1
2
T8 PAD
@
T8 PAD
@
R810
49.9_0402_1%
@
R810
49.9_0402_1%
@
1
2
R812
49.9_0402_1%
@
R812
49.9_0402_1%
@
1
2
R813
49.9_0402_1%
@
R813
49.9_0402_1%
@
1
2
R
E
S
E
R
V
E
D
C
F
G
J CPU1E
CONN@
R
E
S
E
R
V
E
D
C
F
G
J CPU1E
CONN@
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL26
CFG[3]
AL27
CFG[4]
AK26
CFG[5]
AL29
CFG[6]
AL30
CFG[7]
AM31
CFG[8]
AM32
CFG[9]
AM30
CFG[10]
AM28
CFG[11]
AM26
CFG[12]
AN28
CFG[13]
AN31
CFG[14]
AN26
CFG[15]
AM27
CFG[16]
AK31
CFG[17]
AN29
RSVD34
AM33
RSVD35
AJ 27
RSVD38
J 16
RSVD_NCTF2
AT34
RSVD39
H16
RSVD40
G16
RSVD_NCTF1
AR35
RSVD_NCTF3
AT33
RSVD_NCTF5
AR34
RSVD_NCTF11
AT2
RSVD_NCTF12
AT1
RSVD_NCTF13
AR1
RSVD_NCTF6
B34
RSVD_NCTF7
A33
RSVD_NCTF8
A34
RSVD_NCTF9
B35
RSVD_NCTF10
C35
RSVD51
AJ 32
RSVD52
AK32
RSVD27
J 15
RSVD16
C30
RSVD15
D23
RSVD17
A31
RSVD18
B30
RSVD20
D30
RSVD19
B29
RSVD22
A30
RSVD21
B31
RSVD23
C29
RSVD37
T8
RSVD8
F25
RSVD9
F24
RSVD11
D24
RSVD12
G25
RSVD13
G24
RSVD14
E23
RSVD32
W8
RSVD33
AT26
RSVD_NCTF4
AP35
RSVD10
F23
RSVD5
AJ 26
VAXG_VAL_SENSE
AJ 31
VSSAXG_VAL_SENSE
AH31
VCC_VAL_SENSE
AJ 33
VSS_VAL_SENSE
AH33
KEY
B1
VCC_DIE_SENSE
AH27
BCLK_ITP
AN35
BCLK_ITP#
AM35
VSS_DIE_SENSE
AH26
RSVD31
AK2
RSVD30
AE7
RSVD29
AG7
RSVD28
L7
RSVD24
J 20
RSVD25
B18
T7 PAD @ T7 PAD @
R811
49.9_0402_1%
@
R811
49.9_0402_1%
@
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VSSIO_SENSE
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
VSSSENSE_R
VCCSENSE_R
H_CPU_SVIDDAT
VCCIO_SENSE <50>
VCCSENSE <52>
VSSSENSE <52>
VR_SVID_ALRT# <52>
VR_SVID_CLK <52>
VR_SVID_DAT <52>
VSSIO_SENSE <50>
+1.05VS_VTT
+1.05VS_VTT
+CPU_CORE
+1.05VS_VTT
+CPU_CORE
+1.05VS_VTT
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
8.5A
QC 53A
DC 53A
SV type CPU
Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.
Place the PU
resistors close to CPU
VSSIO_SENSE
change to
VSS_SENSE_VCCIO
R910 10_0402_5% R910 10_0402_5%
1 2
R447
75_0402_5%
R447
75_0402_5%
1
2
R446 0_0402_5% R446 0_0402_5% 1 2
R442
100_0402_1%
R442
100_0402_1%
1
2
R450
130_0402_1%
R450
130_0402_1%
1
2
R445
100_0402_1%
R445
100_0402_1%
1
2
R443 0_0402_5% R443 0_0402_5% 1 2
R444 0_0402_5% R444 0_0402_5% 1 2
R448
43_0402_1%
R448
43_0402_1%
1 2
POWER
C
O
R
E

S
U
P
P
L
Y
P
E
G

A
N
D

D
D
R
S
E
N
S
E

L
I
N
E
S
S
V
I
D
J CPU1F
TYCO_2013620-2_IVY BRIDGE CONN@
POWER
C
O
R
E

S
U
P
P
L
Y
P
E
G

A
N
D

D
D
R
S
E
N
S
E

L
I
N
E
S
S
V
I
D
J CPU1F
TYCO_2013620-2_IVY BRIDGE CONN@
VCC_SENSE
AJ 35
VSS_SENSE
AJ 34
VIDALERT#
AJ 29
VIDSCLK
AJ 30
VIDSOUT
AJ 28
VSS_SENSE_VCCIO
A10
VCC1
AG35
VCC2
AG34
VCC3
AG33
VCC4
AG32
VCC5
AG31
VCC6
AG30
VCC7
AG29
VCC8
AG28
VCC9
AG27
VCC10
AG26
VCC11
AF35
VCC12
AF34
VCC13
AF33
VCC14
AF32
VCC15
AF31
VCC16
AF30
VCC17
AF29
VCC18
AF28
VCC19
AF27
VCC20
AF26
VCC21
AD35
VCC22
AD34
VCC23
AD33
VCC24
AD32
VCC25
AD31
VCC26
AD30
VCC27
AD29
VCC28
AD28
VCC29
AD27
VCC30
AD26
VCC31
AC35
VCC32
AC34
VCC33
AC33
VCC34
AC32
VCC35
AC31
VCC36
AC30
VCC37
AC29
VCC38
AC28
VCC39
AC27
VCC40
AC26
VCC41
AA35
VCC42
AA34
VCC43
AA33
VCC44
AA32
VCC45
AA31
VCC46
AA30
VCC47
AA29
VCC48
AA28
VCC49
AA27
VCC50
AA26
VCC51
Y35
VCC52
Y34
VCC53
Y33
VCC54
Y32
VCC55
Y31
VCC56
Y30
VCC57
Y29
VCC58
Y28
VCC59
Y27
VCC60
Y26
VCC61
V35
VCC62
V34
VCC63
V33
VCC64
V32
VCC65
V31
VCC66
V30
VCC67
V29
VCC68
V28
VCC69
V27
VCC70
V26
VCC71
U35
VCC72
U34
VCC73
U33
VCC74
U32
VCC75
U31
VCC76
U30
VCC77
U29
VCC78
U28
VCC79
U27
VCC80
U26
VCC81
R35
VCC82
R34
VCC83
R33
VCC84
R32
VCC85
R31
VCC86
R30
VCC87
R29
VCC88
R28
VCC89
R27
VCC90
R26
VCC91
P35
VCC92
P34
VCC93
P33
VCC94
P32
VCC95
P31
VCC96
P30
VCC97
P29
VCC98
P28
VCC99
P27
VCC100
P26
VCCIO1
AH13
VCCIO12
J 11
VCCIO18
G12
VCCIO19
F14
VCCIO20
F13
VCCIO21
F12
VCCIO22
F11
VCCIO23
E14
VCCIO24
E12
VCCIO2
AH10
VCCIO3
AG10
VCCIO4
AC10
VCCIO5
Y10
VCCIO6
U10
VCCIO7
P10
VCCIO8
L10
VCCIO9
J 14
VCCIO10
J 13
VCCIO11
J 12
VCCIO13
H14
VCCIO14
H12
VCCIO15
H11
VCCIO16
G14
VCCIO17
G13
VCCIO25
E11
VCCIO32
C12
VCCIO33
C11
VCCIO34
B14
VCCIO35
B12
VCCIO36
A14
VCCIO37
A13
VCCIO38
A12
VCCIO39
A11
VCCIO26
D14
VCCIO27
D13
VCCIO28
D12
VCCIO29
D11
VCCIO30
C14
VCCIO31
C13
VCCIO_SENSE
B10
VCCIO40
J 23
R449 0_0402_5% R449 0_0402_5% 1 2
R163
10_0402_5%
R163
10_0402_5%
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SB_DIMM_VREFDQ
VCCIO_SEL
+V_SM_VREF
H_VCCSA_VID0
H_VCCSA_VID1
SA_DIMM_VREFDQ
+VCCSA_SENSE +VCCSA
+VCCPLL
VCCIO_SEL
VCC_AXG_SENSE <52>
VSS_AXG_SENSE <52>
+VCCSA_SENSE <51>
H_VCCSA_VID1 <51>
H_VCCSA_VID0 <51>
SA_DIMM_VREFDQ <11>
SB_DIMM_VREFDQ <12>
+VGFX_CORE
+1.5VS
+1.5VS
+VGFX_CORE
+VCCSA
+1.8VS
+3VALW
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
5A
QC 46A
DC 33A
+V_SM_VREF should
have 20 mil trace width
1.2A
INTEL Recommend
1*330uF,3*10uF
from CR PDDG 0.8
1 0
0 1
Sandy Ivy
V
V
V
V X
V
Vout
0.9V
0.8V
0.725V
VCCSA
VID0 VID1
0 0
6A
1 1 V X 0.675V
*
VCCIO_SEL For 2012 CPU support
1/NC : (Default) +1.05VS_VTT
A19
0: +1.0VS_VTT
RSVD26 had changed the name to VCCIO_SEL
Need PH +3VALW 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select
INTEL Recommend
1*330uF,1*10uF and 2*1uF(0402)
from CR PDDG 0.8
INTEL Recommend
1*330uF,6*10uF
from CR PDDG 0.8
R137 0_0402_5% @ R137 0_0402_5% @ 1 2
POWER
G
R
A
P
H
I
C
S
D
D
R
3

-
1
.
5
V

R
A
I
L
S
S
E
N
S
E
L
I
N
E
S
1
.
8
V

R
A
I
L
S
A

R
A
I
L
V
R
E
F
M
I
S
C
J CPU1G
CONN@
POWER
G
R
A
P
H
I
C
S
D
D
R
3

-
1
.
5
V

R
A
I
L
S
S
E
N
S
E
L
I
N
E
S
1
.
8
V

R
A
I
L
S
A

R
A
I
L
V
R
E
F
M
I
S
C
J CPU1G
CONN@
SM_VREF
AL1
VSSAXG_SENSE
AK34
VAXG_SENSE
AK35
VAXG1
AT24
VAXG2
AT23
VAXG3
AT21
VAXG4
AT20
VAXG5
AT18
VAXG6
AT17
VAXG7
AR24
VAXG8
AR23
VAXG9
AR21
VAXG10
AR20
VAXG11
AR18
VAXG12
AR17
VAXG13
AP24
VAXG14
AP23
VAXG15
AP21
VAXG16
AP20
VAXG17
AP18
VAXG18
AP17
VAXG19
AN24
VAXG20
AN23
VAXG21
AN21
VAXG22
AN20
VAXG23
AN18
VAXG24
AN17
VAXG25
AM24
VAXG26
AM23
VAXG27
AM21
VAXG28
AM20
VAXG29
AM18
VAXG30
AM17
VAXG31
AL24
VAXG32
AL23
VAXG33
AL21
VAXG34
AL20
VAXG35
AL18
VAXG36
AL17
VAXG37
AK24
VAXG38
AK23
VAXG39
AK21
VAXG40
AK20
VAXG41
AK18
VAXG42
AK17
VAXG43
AJ 24
VAXG44
AJ 23
VAXG45
AJ 21
VAXG46
AJ 20
VAXG47
AJ 18
VAXG48
AJ 17
VAXG49
AH24
VAXG50
AH23
VAXG51
AH21
VAXG52
AH20
VAXG53
AH18
VAXG54
AH17
VDDQ11
U4
VDDQ12
U1
VDDQ13
P7
VDDQ14
P4
VDDQ15
P1
VDDQ1
AF7
VDDQ2
AF4
VDDQ3
AF1
VDDQ4
AC7
VDDQ5
AC4
VDDQ6
AC1
VDDQ7
Y7
VDDQ8
Y4
VDDQ9
Y1
VDDQ10
U7
VCCPLL1
B6
VCCPLL2
A6
VCCSA1
M27
VCCSA2
M26
VCCSA3
L26
VCCSA4
J 26
VCCSA5
J 25
VCCSA6
J 24
VCCSA7
H26
VCCSA8
H25
VCCSA_SENSE
H23
VCCSA_VID[1]
C24
VCCPLL3
A2
VCCSA_VID[0]
C22
SA_DIMM_VREFDQ
B4
SB_DIMM_VREFDQ
D1
VCCIO_SEL
A19
C
6
5
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
6
5
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
R909
10K_0402_5%
R909
10K_0402_5%
1
2
C
2
1
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
2
1
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
3
6
2
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
6
2
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
R903
10_0402_5%
R903
10_0402_5%
1
2
C
8
2
8
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
8
2
8
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
3
6
3
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
6
3
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
2
1
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
2
1
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C688
0.1U_0402_16V4Z
C688
0.1U_0402_16V4Z
1
2
C
6
5
3
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
6
5
3
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
2
1
3
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
2
1
3
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
6
0
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
6
0
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
R913
10K_0402_5%
@ R913
10K_0402_5%
@
1
2
R904
10_0402_5%
R904
10_0402_5%
1
2
R575
1K_0402_1%
R575
1K_0402_1%
1
2
C
8
3
0
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
8
3
0
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
R138
0_0402_5%
@
R138
0_0402_5%
@
1
2
+ C221
330U_D2_2V_Y
@
+ C221
330U_D2_2V_Y
@
1
2
R582
1K_0402_1%
R582
1K_0402_1%
1
2
C
8
2
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
8
2
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
R528 0_0805_5% R528 0_0805_5%
1 2
C
6
5
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
6
5
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
8
3
1
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
8
3
1
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
3
6
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
6
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
3
4
1
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
4
1
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
+
C
3
5
5
3
3
0
U
_
D
2
_
2
V
_
Y
+
C
3
5
5
3
3
0
U
_
D
2
_
2
V
_
Y
1
2
C
3
6
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
6
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
+
C
6
6
4
3
3
0
U
_
D
2
_
2
V
_
Y
@
+
C
6
6
4
3
3
0
U
_
D
2
_
2
V
_
Y
@
1
2
C
3
6
1
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
6
1
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
VSS
J CPU1H
CONN@
VSS
J CPU1H
CONN@
VSS1
AT35
VSS2
AT32
VSS3
AT29
VSS4
AT27
VSS5
AT25
VSS6
AT22
VSS7
AT19
VSS8
AT16
VSS9
AT13
VSS10
AT10
VSS11
AT7
VSS12
AT4
VSS13
AT3
VSS14
AR25
VSS15
AR22
VSS16
AR19
VSS17
AR16
VSS18
AR13
VSS19
AR10
VSS20
AR7
VSS21
AR4
VSS22
AR2
VSS23
AP34
VSS24
AP31
VSS25
AP28
VSS26
AP25
VSS27
AP22
VSS28
AP19
VSS29
AP16
VSS30
AP13
VSS31
AP10
VSS32
AP7
VSS33
AP4
VSS34
AP1
VSS35
AN30
VSS36
AN27
VSS37
AN25
VSS38
AN22
VSS39
AN19
VSS40
AN16
VSS41
AN13
VSS42
AN10
VSS43
AN7
VSS44
AN4
VSS45
AM29
VSS46
AM25
VSS47
AM22
VSS48
AM19
VSS49
AM16
VSS50
AM13
VSS51
AM10
VSS52
AM7
VSS53
AM4
VSS54
AM3
VSS55
AM2
VSS56
AM1
VSS57
AL34
VSS58
AL31
VSS59
AL28
VSS60
AL25
VSS61
AL22
VSS62
AL19
VSS63
AL16
VSS64
AL13
VSS65
AL10
VSS66
AL7
VSS67
AL4
VSS68
AL2
VSS69
AK33
VSS70
AK30
VSS71
AK27
VSS72
AK25
VSS73
AK22
VSS74
AK19
VSS75
AK16
VSS76
AK13
VSS77
AK10
VSS78
AK7
VSS79
AK4
VSS80
AJ 25
VSS81
AJ 22
VSS82
AJ 19
VSS83
AJ 16
VSS84
AJ 13
VSS85
AJ 10
VSS86
AJ 7
VSS87
AJ 4
VSS88
AJ 3
VSS89
AJ 2
VSS90
AJ 1
VSS91
AH35
VSS92
AH34
VSS93
AH32
VSS94
AH30
VSS95
AH29
VSS96
AH28
VSS98
AH25
VSS99
AH22
VSS100
AH19
VSS101
AH16
VSS102
AH7
VSS103
AH4
VSS104
AG9
VSS105
AG8
VSS106
AG4
VSS107
AF6
VSS108
AF5
VSS109
AF3
VSS110
AF2
VSS111
AE35
VSS112
AE34
VSS113
AE33
VSS114
AE32
VSS115
AE31
VSS116
AE30
VSS117
AE29
VSS118
AE28
VSS119
AE27
VSS120
AE26
VSS121
AE9
VSS122
AD7
VSS123
AC9
VSS124
AC8
VSS125
AC6
VSS126
AC5
VSS127
AC3
VSS128
AC2
VSS129
AB35
VSS130
AB34
VSS131
AB33
VSS132
AB32
VSS133
AB31
VSS134
AB30
VSS135
AB29
VSS136
AB28
VSS137
AB27
VSS138
AB26
VSS139
Y9
VSS140
Y8
VSS141
Y6
VSS142
Y5
VSS143
Y3
VSS144
Y2
VSS145
W35
VSS146
W34
VSS147
W33
VSS148
W32
VSS149
W31
VSS150
W30
VSS151
W29
VSS152
W28
VSS153
W27
VSS154
W26
VSS155
U9
VSS156
U8
VSS157
U6
VSS158
U5
VSS159
U3
VSS160
U2
VSS
J CPU1I
CONN@
VSS
J CPU1I
CONN@
VSS161
T35
VSS162
T34
VSS163
T33
VSS164
T32
VSS165
T31
VSS166
T30
VSS167
T29
VSS168
T28
VSS169
T27
VSS170
T26
VSS171
P9
VSS172
P8
VSS173
P6
VSS174
P5
VSS175
P3
VSS176
P2
VSS177
N35
VSS178
N34
VSS179
N33
VSS180
N32
VSS181
N31
VSS182
N30
VSS183
N29
VSS184
N28
VSS185
N27
VSS186
N26
VSS187
M34
VSS188
L33
VSS189
L30
VSS190
L27
VSS191
L9
VSS192
L8
VSS193
L6
VSS194
L5
VSS195
L4
VSS196
L3
VSS197
L2
VSS198
L1
VSS199
K35
VSS200
K32
VSS201
K29
VSS202
K26
VSS203
J 34
VSS204
J 31
VSS205
H33
VSS206
H30
VSS207
H27
VSS208
H24
VSS209
H21
VSS210
H18
VSS211
H15
VSS212
H13
VSS213
H10
VSS214
H9
VSS215
H8
VSS216
H7
VSS217
H6
VSS218
H5
VSS219
H4
VSS220
H3
VSS221
H2
VSS222
H1
VSS223
G35
VSS224
G32
VSS225
G29
VSS226
G26
VSS227
G23
VSS228
G20
VSS229
G17
VSS230
G11
VSS231
F34
VSS232
F31
VSS233
F29
VSS234
F22
VSS235
F19
VSS236
E30
VSS237
E27
VSS238
E24
VSS239
E21
VSS240
E18
VSS241
E15
VSS242
E13
VSS243
E10
VSS244
E9
VSS245
E8
VSS246
E7
VSS247
E6
VSS248
E5
VSS249
E4
VSS250
E3
VSS251
E2
VSS252
E1
VSS253
D35
VSS254
D32
VSS255
D29
VSS256
D26
VSS257
D20
VSS258
D17
VSS259
C34
VSS260
C31
VSS261
C28
VSS262
C27
VSS263
C25
VSS264
C23
VSS265
C10
VSS266
C1
VSS267
B22
VSS268
B19
VSS269
B17
VSS270
B15
VSS271
B13
VSS272
B11
VSS273
B9
VSS274
B8
VSS275
B7
VSS276
B5
VSS277
B3
VSS278
B2
VSS279
A35
VSS280
A32
VSS281
A29
VSS282
A26
VSS283
A23
VSS284
A20
VSS285
A3

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V_DDR_REFA
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D10
DDR_A_D11
DDR_A_D18
DDR_A_D19
DDR_A_D26
DDR_A_D27
DDR_A0_DM0
DDR_A0_DM3
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_D17
DDR_A_D9
DDR_A_D16
DDR_A_D25
DDR_A_D24
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA12
DDR_A_MA13
DDR_A0_DM5
DDR_A0_DM7
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_BS0
DDR_A_BS2
DDRA_CS1_DIMMA#
SA_CLK_DDR0
SA_CLK_DDR#0
DDRA_CKE0_DIMMA
DDR_A_CAS#
DDR_A_WE#
DDR_A_D33
DDR_A_D48
DDR_A_D36
DDR_A_D37
DDR_A_D45
DDR_A_D46
DDR_A_D52
DDR_A_D53
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_MA2
DDR_A_MA0
DDR_A_MA4
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_A_MA14
DDR_A0_DM4
DDR_A0_DM6
DDR_A_DQS5
DDR_A_DQS7
DDR_A_DQS#5
DDR_A_DQS#7
DDR_A_BS1
DDRA_CS0_DIMMA#
SA_CLK_DDR1
SA_CLK_DDR#1
DDRA_CKE1_DIMMA
DDR_A_RAS#
D_CK_SDATA
D_CK_SCLK
SA_ODT0
SA_ODT1
DDR_A_D63
DDR_A_MA15
+VREF_CA
DDR_A_D39
DDR_A_D54
DDR_A_D38
DDR_A_D47
DDR_A_D44
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D21
DDR_A_D28
DDR_A_D29
DDR_A0_DM1
DDR_A0_DM2
DDR_A_DQS0
DDR_A_DQS3
DDR_A_DQS#0
DDR_A_DQS#3
DDR_A_D23
DDR_A_D31
DDR_A_D13
DDR_A_D20
DDR_A_D30
DDR_A_D14
DDR_A_D15
DDR_A_D12
DDR_A_D22
DDR_A0_DM5
DDR_A0_DM3
DDR_A0_DM7
DDR_A0_DM0
DDR_A0_DM1
DDR_A0_DM6
DDR_A0_DM4
DDR_A0_DM2
DDR3_DRAMRST#
DDRA_CS1_DIMMA# <6>
DDR_A_CAS# <6>
DDR_A_WE# <6>
DDR_A_BS0 <6>
SA_CLK_DDR#0 <6>
SA_CLK_DDR0 <6>
DDR_A_BS2 <6>
DDRA_CKE0_DIMMA <6> DDRA_CKE1_DIMMA <6>
SA_CLK_DDR1 <6>
SA_CLK_DDR#1 <6>
DDR_A_BS1 <6>
DDR_A_RAS# <6>
DDRA_CS0_DIMMA# <6>
SA_ODT0 <6>
SA_ODT1 <6>
D_CK_SDATA <12,14,41>
D_CK_SCLK <12,14,41>
DIMM_DRAMRST# <6,12>
RST_GATE <6,12,14>
SA_DIMM_VREFDQ <9> DDR_A_D[0..63] <6>
DDR_A_DQS[0..7] <6>
DDR_A_DQS#[0..7] <6>
DDR_A_MA[0..15] <6>
+1.5V
+3VS
+0.75VS +0.75VS
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+0.75VS
+1.5V
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
All VREF traces should
<Address(SA1,SA0): 00>
DIMM_1 Reserve H:8mm
M3 support
Layout Note:
Place near JDIMM1.203,204
CHG C407 to oscon
Layout Note:
Place near JDIMM1
R02 modify for ESD
C
2
0
6
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
2
0
6
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
3
9
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
9
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
4
0
8
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
0
8
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
G
D S
Q46
S TR SSM3K7002F 1N SC59-3 @
G
D S
Q46
2
1 3
C
4
0
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
0
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
R320
1K_0402_5%
R320
1K_0402_5%
1
2
R
3
0
2
1
0
K
_
0
4
0
2
_
5
%
R
3
0
2
1
0
K
_
0
4
0
2
_
5
%
1
2
C
4
0
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
4
0
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
3
8
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
8
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
3
7
8
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
7
8
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
4
1
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
4
1
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
4
1
2
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
1
2
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
3
7
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
3
7
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
4
1
6
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
1
6
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
C
3
8
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
8
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
4
1
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
1
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
R
3
0
1
1
0
K
_
0
4
0
2
_
5
%
R
3
0
1
1
0
K
_
0
4
0
2
_
5
%
1
2
C
3
8
3
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
@
C
3
8
3
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
@
1
2
R267
1K_0402_5%
R267
1K_0402_5%
1
2
C
3
7
2
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
C
3
7
2
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
C
3
7
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
7
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
4
1
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
1
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
R266
1K_0402_5%
R266
1K_0402_5%
1
2
C
3
8
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
8
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
J DIMM1
FOX_AS0A626-U8SN-7F
CONN@
J DIMM1
FOX_AS0A626-U8SN-7F
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
R133
0_0402_5%
@R133
0_0402_5%
@
1 2
C
4
1
3
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
1
3
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
3
9
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
9
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
+
C
4
0
7
3
3
0
U
_
D
2
_
2
V
_
Y
@
+
C
4
0
7
3
3
0
U
_
D
2
_
2
V
_
Y
@
1
2
C
4
1
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
1
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
3
9
3
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
9
3
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
R319
1K_0402_5%
R319
1K_0402_5%
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V_DDR_REFC
DDR_B0_DM5
DDR_B0_DM3
DDR_B0_DM7
DDR_B0_DM0
DDR_B0_DM1
DDR_B0_DM6
DDR_B0_DM4
DDR_B0_DM2
D_CK_SDATA
D_CK_SCLK
+VREF_CC
DDR_B0_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D1
DDR_B_D0
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B0_DM3
DDR_B_D26
DDR_B_D27
DDR_B_D5
DDR_B_DQS#0
DDR_B_D4
DDR_B_DQS0
DDR_B_D22
DDR_B_D20
DDR3_DRAMRST#
DDR_B0_DM1
DDR_B_D23
DDR_B_D21
DDR_B_DQS#3
DDR_B_D14
DDR_B0_DM2
DDR_B_DQS3
DDR_B_D7
DDR_B_D6
DDR_B_D15
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D12
DDR_B_D31
DDR_B_D13
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
SB_CLK_DDR0
SB_CLK_DDR#0
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_CS1_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B0_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B0_DM7
DDRB_CKE0_DIMMB
DDR_B_D58
DDR_B_D59
DDR_B_MA15
DDR_B_MA7
SB_ODT0
DDR_B_MA14
DDR_B_MA6
DDRB_CKE1_DIMMB
DDR_B_MA4
DDR_B_BS1
SB_ODT1
SB_CLK_DDR1
DDR_B_RAS#
SB_CLK_DDR#1
DDR_B_MA2
DDR_B_MA11
DDR_B_MA0
DDRB_CS0_DIMMB#
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
DDR_B_D52
DDR_B_D36
DDR_B_D37
DDR_B_D44
DDR_B_D54
DDR_B_D53
DDR_B_D46
DDR_B_D45
DDR_B_D38
DDR_B_D55
DDR_B_D47
DDR_B0_DM6
DDR_B_DQS#5
DDR_B0_DM4
DDR_B_D60
DDR_B_D39
DDR_B_DQS5
D_CK_SDATA <11,14,41>
D_CK_SCLK <11,14,41>
DIMM_DRAMRST# <6,11>
DDRB_CS1_DIMMB# <6>
DDR_B_CAS# <6>
DDR_B_WE# <6>
DDR_B_BS0 <6>
SB_CLK_DDR#0 <6>
SB_CLK_DDR0 <6>
DDRB_CKE0_DIMMB <6>
DDR_B_BS2 <6>
SB_CLK_DDR#1 <6>
DDR_B_BS1 <6>
DDR_B_RAS# <6>
DDRB_CS0_DIMMB# <6>
SB_ODT0 <6>
SB_ODT1 <6>
SB_CLK_DDR1 <6>
DDRB_CKE1_DIMMB <6>
DDR_B_D[0..63] <6>
DDR_B_DQS[0..7] <6>
DDR_B_DQS#[0..7] <6>
DDR_B_MA[0..15] <6>
RST_GATE <6,11,14>
SB_DIMM_VREFDQ <9>
+3VS
+0.75VS
+0.75VS
+0.75VS
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V +1.5V
+3VS
+1.5V
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
All VREF traces should
Layout Note:
Place near JDIMM2.203,204
Layout Note:
Place near JDIMM2
<Address(SA1,SA0): 10>
DIMM_2 Reserve H:4mm
M3 support
CHG C359 to oscon
C
4
5
1
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
5
1
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
C
4
4
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
4
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
4
2
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
2
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
R
3
4
5
1
0
K
_
0
4
0
2
_
5
%
R
3
4
5
1
0
K
_
0
4
0
2
_
5
%
1
2
J DIMM2
FOX_AS0A626-U4RN-7F
CONN@
J DIMM2
FOX_AS0A626-U4RN-7F
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C
4
2
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
2
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
4
2
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
2
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
R350
1K_0402_5%
R350
1K_0402_5%
1
2
R346
0_0402_5%
@R346
0_0402_5%
@
1 2
C
4
5
0
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
5
0
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
4
3
8
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
3
8
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
C
4
4
7
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
4
7
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
4
3
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
4
3
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
4
4
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
4
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
4
4
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
4
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
G
D S
Q47
G
D S
Q47
2
1 3
C
4
3
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
3
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
4
2
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
2
5
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
R341
1K_0402_5%
R341
1K_0402_5%
1
2
C
4
4
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
4
4
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R340
1K_0402_5%
R340
1K_0402_5%
1
2
C
4
3
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
3
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
4
2
6
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
@C
4
2
6
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
@
1
2
C
4
2
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
2
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
R351
1K_0402_5%
R351
1K_0402_5%
1
2
C
4
4
8
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
4
4
8
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
4
3
6
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
3
6
2
.
2
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
+
C
3
5
9
3
3
0
U
_
2
.
5
V
_
M
+
C
3
5
9
3
3
0
U
_
2
.
5
V
_
M
1
2
C
4
4
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
4
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
4
3
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
4
3
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R
3
4
4
1
0
K
_
0
4
0
2
_
5
%
R
3
4
4
1
0
K
_
0
4
0
2
_
5
%
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_RTCX1
PCH_RTCX2
PCH_RTCX1
PCH_RTCRST#
SM_INTRUDER#
PCH_INTVRMEN
SM_INTRUDER#
PCH_SPKR
PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_CS0#_1
PCH_J TAG_TCK
PCH_SATALED#
PCH_SRTCRST#
PCH_J TAG_TMS
PCH_J TAG_TDI
PCH_J TAG_TDO
HDA_SYNC_PCH
HDA_RST_PCH#
HDA_SDIN0
HDA_SDOUT_PCH
PCH_RTCX2
HDA_BITCLK_PCH
LPC_AD2
LPC_FRAME#
LPC_AD0
LPC_AD3
LPC_AD1
SERIRQ
PCH_GPIO19
SATA_COMP
RBIAS_SATA3
SATA3_COMP
HDA_BITCLK_PCH
HDA_RST_PCH#
HDA_SDOUT_PCH
PCH_INTVRMEN
PCH_SPKR
HDA_SDOUT_PCH
HDA_SYNC_PCH
HDA_SYNC_PCH_R
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
SGEN#
SERIRQ
PCH_SATALED#
PCH_GPIO19
+RTCBATT_R
PCH_SPI_MISO_1
PCH_SPI_CS0#_1
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
SPI_WP1#
SPI_HOLD1#
SPI_WP1#
SPI_HOLD1#
PCH_SPI_CLK_1
SGEN#
HDA_SYNC_PCH HDA_SYNC_PCH_R
PCH_SPI_CLK_2
PCH_SPI_CLK
PCH_SPI_CS0#_2
PCH_SPI_MOSI_2
PCH_SPI_MISO_2
SPI_HOLD2#
SPI_WP2#
PCH_SPI_CS0#_2
PCH_SPI_CLK_2
PCH_SPI_MOSI_2
PCH_SPI_MISO_2
SPI_WP2#
SPI_HOLD2#
PCH_SPI_CLK_2
PCH_SPI_VCC
PCH_GPIO23
PCH_GPIO23
PCH_SPKR <42>
HDA_SDIN0 <42>
SERIRQ <40>
SATA_PRX_DTX_P0 <34>
SATA_PTX_DRX_N0 <34>
SATA_PTX_DRX_P0 <34>
SATA_PRX_DTX_N0 <34>
LPC_AD0 <40>
LPC_AD1 <40>
LPC_AD2 <40>
LPC_AD3 <40>
LPC_FRAME# <40>
HDA_SYNC_AUDIO <42>
HDA_SDOUT_AUDIO <42>
HDA_RST_AUDIO# <42>
HDA_BITCLK_AUDIO <42>
PCH_SATALED# <41>
ME_EN <40>
+RTCVCC
+RTCVCC
+1.05VS_VTT
+1.05VS_VTT
+3VS
+3VALW_PCH
+3VALW_PCH
+3VS
+CHGRTC
+RTCVCC
+RTCBATT
+3VS
+3VS
+3VS
+RTCBATT
+3VS
+3VS
+3VS
+3VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
SRTCRST close RAM door
RTCRST close RAM door
HDD
HIntegrated VRM enable
LIntegrated VRM disable
INTVRMEN
*
LOW= Disable (Default)
HIGH= Enable ( No Reboot )
*
*
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
*
(INTVRMEN should always be pull high.)
ME debug mode,this signal has a weak internal PD
HDA_SDO
as Capella ME override (GPIO33)
Boot BIOS GPIO19
0
1
SPI
-
GPIO51
Reserved
LPC
Boot BIOS Strap
1 1
0
*
0
1
0
ODD
20mil
20mil
This part had been re-modified
be careful,if link symbol!!
SPI ROM FOR ME (4MB)
Footprint 200mil
Rserve the 2M ROM for Win8
GPIO21
0
1 *
Switchable GPU
Non-Switchable
SGEN#
Prevent back drive issue.
MSATA
Modify R02
R02 Modify
Modify R03
Co-lay NPCE885N
R04 modify
R04 modify
Modify R04
Delete Co-lay NPCE885N
GPIO23
0
1
USB2.0
USB3.0
USB_config
modify on 7912 V0.3
R555
33_0402_5%
R555
33_0402_5%
1 2
R681 33_0402_5% R681 33_0402_5%
1 2
R667 3.3K_0402_5% R667 3.3K_0402_5% 1 2
R539 1K_0402_5% R539 1K_0402_5% 1 2
U33
BD82HM77 QPRG C1 BGA 989P
HM77@
SA00005AG00
U33
BD82HM77 QPRG C1 BGA 989P
HM77@
SA00005AG00
G
D S
Q36
G
D S
Q36
2
1 3
R557
0_0402_5%
R557
0_0402_5%
1 2
R243 20K_0402_1% R243 20K_0402_1%
1 2
R275 10K_0402_5% R275 10K_0402_5% 1 2
R654 3.3K_0402_5% R654 3.3K_0402_5% 1 2
R585 330K_0402_5% R585 330K_0402_5% 1 2
R624 4.7K_0402_5% R624 4.7K_0402_5% 1 2
R2092
20K_0402_1%
PUSB2@
R2092
20K_0402_1%
PUSB2@
1
2
C360
1U_0603_10V6K
C360
1U_0603_10V6K
1
2
R640 10K_0402_5% R640 10K_0402_5% 1 2
J BATT1
SUYIN_060003HA002G202ZL CONN@
J BATT1
SUYIN_060003HA002G202ZL CONN@
+
1
-
2
U36
32M W25Q32BVSSIG_SO8
U36
32M W25Q32BVSSIG_SO8
CS#
1
SO/SIO1
2
WP#
3
GND
4
VCC
8
HOLD#
7
SCLK
6
SI/SIO0
5
R544
33_0402_5%
R544
33_0402_5%
1 2
R294 1K_0402_5% @ R294 1K_0402_5% @ 1 2
R568 10M_0402_5% R568 10M_0402_5%
1 2
U42
MX25L1606EM2I-12G_SO8
WIN8@ U42
MX25L1606EM2I-12G_SO8
WIN8@
CS#
1
SO
2
WP#
3
GND
4
VCC
8
HOLD#
7
SCLK
6
SI
5
R567 1M_0402_5% R567 1M_0402_5% 1 2
R734 33_0402_5%
WIN8@
R734 33_0402_5%
WIN8@ 1 2
C2049
33P_0402_50V8K
@ C2049
33P_0402_50V8K
@
C682
1
5
P
_
0
4
0
2
_
5
0
V
8
J
C682
1
5
P
_
0
4
0
2
_
5
0
V
8
J
1
2
D13
CHN202UPT_SC70-3
D13
CHN202UPT_SC70-3
1
23
R260
37.4_0402_1%
R260
37.4_0402_1%
1 2
R2050 33_0402_5%
WIN8@
R2050 33_0402_5%
WIN8@ 1 2
J
C
M
O
S
1
S
H
O
R
T

P
A
D
S
@
J
C
M
O
S
1
S
H
O
R
T

P
A
D
S
@
1
2
R248 20K_0402_1% R248 20K_0402_1%
1 2
R866
22_0402_5%
@
R866
22_0402_5%
@
1 2
R2048
22_0402_5%
@ R2048
22_0402_5%
@1 2
R674
51_0402_5%
@R674
51_0402_5%
@
1 2
T76 @ PAD T76 @ PAD
C471
0.1U_0402_16V4Z
C471
0.1U_0402_16V4Z
1
2
R556
1K_0402_5%
@
R556
1K_0402_5%
@ 1 2
R625
750_0402_1%
R625
750_0402_1%
1 2
C893
33P_0402_50V8K
@
C893
33P_0402_50V8K
@
C686
15P_0402_50V8J
C686
15P_0402_50V8J
1
2
T77 @ PAD T77 @ PAD
R241
49.9_0402_1%
R241
49.9_0402_1%
1 2
T75 @ PAD T75 @ PAD
R
T
C
I
H
D
A
S
A
T
A
L
P
C
S
P
I
J
T
A
G
S
A
T
A

6
G
U33A
COUGARPOINT_FCBGA989~D
SA00004EEY0
HM65@
R
T
C
I
H
D
A
S
A
T
A
L
P
C
S
P
I
J
T
A
G
S
A
T
A

6
G
U33A
SA00004EEY0
HM65@
RTCX1
A20
RTCX2
C20
INTVRMEN
C17
INTRUDER#
K22
HDA_BCLK
N34
HDA_SYNC
L34
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SDIN1
G34
HDA_SDIN2
C34
HDA_SDO
A36
SATALED#
P3
FWH0 / LAD0
C38
FWH1 / LAD1
A38
FWH2 / LAD2
B37
FWH3 / LAD3
C37
LDRQ1#/ GPIO23
K36
FWH4 / LFRAME#
D36
LDRQ0#
E36
RTCRST#
D20
HDA_SDIN3
A34
HDA_DOCK_EN#/ GPIO33
C36
HDA_DOCK_RST#/ GPIO13
N32
SRTCRST#
G22
SATA0RXN
AM3
SATA0RXP
AM1
SATA0TXN
AP7
SATA0TXP
AP5
SATA1RXN
AM10
SATA1RXP
AM8
SATA1TXN
AP11
SATA1TXP
AP10
SATA2RXN
AD7
SATA2RXP
AD5
SATA2TXN
AH5
SATA2TXP
AH4
SATA3RXN
AB8
SATA3RXP
AB10
SATA3TXN
AF3
SATA3TXP
AF1
SATA4RXN
Y7
SATA4RXP
Y5
SATA4TXN
AD3
SATA4TXP
AD1
SATA5RXN
Y3
SATA5RXP
Y1
SATA5TXN
AB3
SATA5TXP
AB1
SATAICOMPI
Y10
SPI_CLK
T3
SPI_CS0#
Y14
SPI_CS1#
T1
SPI_MOSI
V4
SPI_MISO
U3
SATA0GP / GPIO21
V14
SATA1GP / GPIO19
P1
J TAG_TCK
J 3
J TAG_TMS
H7
J TAG_TDI
K5
J TAG_TDO
H1
SERIRQ
V5
SPKR
T10
SATAICOMPO
Y11
SATA3COMPI
AB13
SATA3RCOMPO
AB12
SATA3RBIAS
AH1
R733 33_0402_5%
WIN8@
R733 33_0402_5%
WIN8@ 1 2
R259
10K_0402_5%
R259
10K_0402_5%
1
2
J
M
E
1
S
H
O
R
T

P
A
D
S
@
J
M
E
1
S
H
O
R
T

P
A
D
S
@
1
2
R704
3.3K_0402_5%
WIN8@ R704
3.3K_0402_5%
WIN8@ 1 2
R542
33_0402_5%
R542
33_0402_5%
1 2
R792
1M_0402_5%
R792
1M_0402_5%
1
2
R258
10K_0402_5%
@
R258
10K_0402_5%
@
1
2
C356
1U_0603_10V6K
C356
1U_0603_10V6K
1
2
R545
33_0402_5%
R545
33_0402_5%
1 2
R684 33_0402_5% R684 33_0402_5%
1 2
R375
1K_0402_5%
R375
1K_0402_5%
1
2
R540
0_0402_5%
@
R540
0_0402_5%
@
1 2
Y3
32.768KHZ_12.5PF_FC-135
Y3
32.768KHZ_12.5PF_FC-135
1 2
R2128
20K_0402_1%
PUSB3@
R2128
20K_0402_1%
PUSB3@
1
2
R703
3.3K_0402_5%
WIN8@ R703
3.3K_0402_5%
WIN8@ 1 2
R652 33_0402_5% R652 33_0402_5%
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_GPIO11
PCH_SMBCLK
PCH_SMBDATA
XTAL25_IN
XTAL25_OUT
PCH_SML1CLK
PCH_SML1DATA
XCLK_RCOMP
CLK_PCI_LPBACK
CLK_CPU_DMI
CLK_CPU_DMI#
PCH_GPIO46
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2
PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N1
PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1
CLK_PCI_LPBACK
MINI1_CLKREQ#
PCH_GPIO45
XTAL25_OUT
XTAL25_IN
RST_GATE
CLK_FLEX2
LAN_CLKREQ#
MINI2_CLKREQ#
PCH_GPIO44
MINI1_CLKREQ#
USB30_CLKREQ#
PCH_GPIO45
PCH_GPIO46
PCH_SML1CLK
PCH_SML1DATA
EC_SMB_CK2
EC_SMB_DA2
CLKIN_GND1#
CLKIN_GND1
PCH_GPIO73
LAN_CLKREQ#
PEG_CLKREQ#_R
PCH_GPIO73
PCH_GPIO47
PCH_GPIO11
PCH_SMBCLK
PCH_SMBDATA
PCH_SML1CLK
PCH_SML1DATA
RST_GATE
PCH_GPIO47
USB30_CLKREQ#
PCH_GPIO74
PCH_GPIO74
DGPU_PRSNT#
D_CK_SCLK
D_CK_SDATA PCH_SMBDATA
PCH_SMBCLK
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#
CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
CLK_BUF_ICH_14M
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLK_PEG_VGA#
CLK_PEG_VGA
DGPU_PRSNT#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
CLK_FLEX0
PCH_GPIO44
CLK_FLEX1
CLK_CPU_DPLL#
CLK_CPU_DPLL
PEG_CLKREQ#_R
MINI2_CLKREQ#
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
PCIE_PRX_DTX_N1 <35>
PCIE_PTX_C_DRX_N1 <35>
PCIE_PRX_DTX_P1 <35>
PCIE_PTX_C_DRX_P1 <35>
CLK_PCIE_MINI1# <37>
CLK_PCIE_MINI1 <37>
MINI1_CLKREQ# <37>
CLK_PCI_LPBACK <17>
PCH_SMBCLK <37>
PCH_SMBDATA <37>
RST_GATE <6,11,12>
EC_SMB_CK2 <22,40>
EC_SMB_DA2 <22,40>
CLK_PCIE_LAN# <35>
CLK_PCIE_LAN <35>
LAN_CLKREQ# <35>
CLK_PEG_VGA# <22>
CLK_PEG_VGA <22>
D_CK_SDATA <11,12,41>
D_CK_SCLK <11,12,41>
CLK_CPU_DPLL# <5>
CLK_CPU_DPLL <5>
PEG_CLKREQ# <22>
VGA_ON <17,25,44,51,53>
+1.05VS_VTT
+3VALW_PCH
+3VS
+3VS
+3VALW_PCH
+3VS
+3VS
+3VS
+3VS
+3VALW_PCH
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
PCIE LAN
Mini Card 1 (WLAN)
Reserve for EMI please close to U33
Mini Card 1(WLAN)
PCIE LAN
Pull down 10K ohm
for using internal Clock
For DDR
Pull up at EC side.
For VGA,EC
GPIO67
0
1
DIS,OPTIMUS
UMA
DGPU_PRSNT#
120 MHz for eDP
Pull high @ VGA side
for safe
R02 Modify
R02 modify
R159
10K_0402_5%
UMAO@
R159
10K_0402_5%
UMAO@
1
2
Q40B
DMN66D0LDW-7_SOT363-6
Q40B
3 4
5
C675 .1U_0402_16V7K C675 .1U_0402_16V7K 1 2
R608 1K_0402_5% R608 1K_0402_5% 1 2
R234 10K_0402_5% R234 10K_0402_5% 1 2
C631
10P_0402_50V8J
C631
10P_0402_50V8J
1
2
Q38B
Q38B
3 4
5
R662 2.2K_0402_5% R662 2.2K_0402_5% 1 2
R642 2.2K_0402_5% R642 2.2K_0402_5% 1 2
C672 .1U_0402_16V7K C672 .1U_0402_16V7K 1 2
R618 10K_0402_5% R618 10K_0402_5% 1 2
Y2 25MHZ 10PF 7V25000014 Y2 25MHZ 10PF 7V25000014
GND
2
3
3
1
1
GND
4
R670
4.7K_0402_5%
R670
4.7K_0402_5%
1 2
R295 10K_0402_5% R295 10K_0402_5% 1 2
R265 10K_0402_5% R265 10K_0402_5% 1 2
R644
2.2K_0402_5%
@
R644
2.2K_0402_5%
@
1
2
R238 10K_0402_5% R238 10K_0402_5% 1 2
R221 10K_0402_5% R221 10K_0402_5% 1 2
R293 10K_0402_5% R293 10K_0402_5% 1 2
T9 PAD
@
T9 PAD
@
R663
10K_0402_5%
R663
10K_0402_5%
1
2
R563 10K_0402_5% R563 10K_0402_5% 1 2
T73 PAD
@
T73 PAD
@
R638 10K_0402_5% R638 10K_0402_5% 1 2
R527 1M_0402_5% R527 1M_0402_5% 1 2
P
C
I
-
E
*
C
L
O
C
K
S
F
L
E
X

C
L
O
C
K
S
S
M
B
U
S
C
o
n
t
r
o
l
l
e
r
L
i
n
k
U33B
HM65@
P
C
I
-
E
*
C
L
O
C
K
S
F
L
E
X

C
L
O
C
K
S
S
M
B
U
S
C
o
n
t
r
o
l
l
e
r
L
i
n
k
U33B
HM65@
PERN1
BG34
PERP1
BJ 34
PERN2
BE34
PERP2
BF34
PERN3
BG36
PERP3
BJ 36
PERN4
BF36
PERP4
BE36
PERN5
BG37
PERP5
BH37
PERN6
BJ 38
PERP6
BG38
PERN7
BG40
PERP7
BJ 40
PERN8
BE38
PERP8
BC38
PETN1
AV32
PETP1
AU32
PETN2
BB32
PETP2
AY32
PETN3
AV34
PETP3
AU34
PETN4
AY34
PETP4
BB34
PETN5
AY36
PETP5
BB36
PETN6
AU36
PETP6
AV36
PETN7
AY40
PETP7
BB40
PETN8
AW38
PETP8
AY38
CLKOUT_PCIE0N
Y40
CLKOUT_PCIE0P
Y39
CLKOUT_PCIE1N
AB49
CLKOUT_PCIE1P
AB47
CLKOUT_PCIE2N
AA48
CLKOUT_PCIE2P
AA47
CLKOUT_PCIE3N
Y37
CLKOUT_PCIE3P
Y36
CLKOUT_PCIE4N
Y43
CLKOUT_PCIE4P
Y45
CLKOUT_PCIE5N
V45
CLKOUT_PCIE5P
V46
CLKIN_DMI2_N
BJ 30
CLKIN_DMI2_P
BG30
CLKIN_DMI_N
BF18
CLKIN_DMI_P
BE18
CLKIN_DOT_96N
G24
CLKIN_DOT_96P
E24
CLKIN_SATA_N / CKSSCD_N
AK7
CLKIN_SATA_P / CKSSCD_P
AK5
XTAL25_IN
V47
XTAL25_OUT
V49
REFCLK14IN
K45
CLKIN_PCILOOPBACK
H45
CLKOUT_PEG_A_N
AB37
CLKOUT_PEG_A_P
AB38
PEG_A_CLKRQ#/ GPIO47
M10
PCIECLKRQ0#/ GPIO73
J 2
PCIECLKRQ1#/ GPIO18
M1
PCIECLKRQ2#/ GPIO20
V10
PCIECLKRQ3#/ GPIO25
A8
PCIECLKRQ4#/ GPIO26
L12
PCIECLKRQ5#/ GPIO44
L14
CLKOUTFLEX0 / GPIO64
K43
F47
H47
K49
CLKOUT_DMI_N
AV22
CLKOUT_DMI_P
AU22
PEG_B_CLKRQ#/ GPIO56
E6
CLKOUT_PEG_B_P
AB40
CLKOUT_PEG_B_N
AB42
XCLK_RCOMP
Y47
CLKOUT_DP_P / CLKOUT_BCLK1_P
AM13
CLKOUT_DP_N / CLKOUT_BCLK1_N
AM12
CLKOUT_PCIE6N
V40
CLKOUT_PCIE6P
V42
PCIECLKRQ7#/ GPIO46
K12
CLKOUT_PCIE7N
V38
CLKOUT_PCIE7P
V37
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK14
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AK13
SMBALERT#/ GPIO11
E12
SMBCLK
H14
SMBDATA
C9
SML0ALERT#/ GPIO60
A12
SML0CLK
C8
SML0DATA
G12
SML1ALERT# / PCHHOT#/ GPIO74
C13
SML1CLK / GPIO58
E14
SML1DATA / GPIO75
M16
CL_CLK1
M7
CL_DATA1
T11
CL_RST1#
P10
PCIECLKRQ6#/ GPIO45
T13
R668
2.2K_0402_5%
@
R668
2.2K_0402_5%
@
1
2
R669
4.7K_0402_5%
R669
4.7K_0402_5%
1 2
R677 2.2K_0402_5% R677 2.2K_0402_5% 1 2
C630
10P_0402_50V8J
C630
10P_0402_50V8J
1
2
R233 10K_0402_5% R233 10K_0402_5% 1 2
R647 10K_0402_5% R647 10K_0402_5% 1 2
R220 10K_0402_5% R220 10K_0402_5% 1 2
G
D S
Q39
2N7002H_SOT23-3
DIS@
G
D S
Q39
2N7002H_SOT23-3
DIS@
2
1 3
Q38A
Q38A
6 1
2
R653 10K_0402_5% R653 10K_0402_5% 1 2
C642
22P_0402_50V8J
@C642
22P_0402_50V8J
@
1 2
R632
10K_0402_5%
DIS@
R632
10K_0402_5%
DIS@
1
2
T29 PAD
@
T29 PAD
@
R273 10K_0402_5% R273 10K_0402_5% 1 2
R526
90.9_0402_1%
R526
90.9_0402_1%
1 2
R561 10K_0402_5% R561 10K_0402_5% 1 2
R530
33_0402_5%
@R530
33_0402_5%
@
1 2
Q40A
Q40A
6 1
2
C669 .1U_0402_16V7K C669 .1U_0402_16V7K 1 2
R175 10K_0402_5% R175 10K_0402_5% 1 2
R631
0_0402_5%
DIS@
R631
0_0402_5%
DIS@ 1 2
R240 10K_0402_5% R240 10K_0402_5% 1 2
R280 10K_0402_5% R280 10K_0402_5% 1 2
R264 10K_0402_5% R264 10K_0402_5% 1 2
R160
10K_0402_5%
DIS@
R160
10K_0402_5%
DIS@
1
2
C677 .1U_0402_16V7K C677 .1U_0402_16V7K 1 2
R630 10K_0402_5% @ R630 10K_0402_5% @ 1 2
R643 2.2K_0402_5% R643 2.2K_0402_5% 1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_IRCOMP
DMI_CRX_PTX_N1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CRX_PTX_N2
DMI_CRX_PTX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_P2
DMI_CTX_PRX_N1
DMI_CRX_PTX_N0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CRX_PTX_N3
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC1
FDI_LSYNC0
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P5
PCH_GPIO72
RI#
SUSACK#_R
RBIAS_CPY
SUSWARN#
PM_DRAM_PWRGD
PCH_RSMRST#
PBTN_OUT#
PCH_ACIN
DSWODVREN
PCH_PCIE_WAKE#
PCH_RSMRST#
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
SUS_STAT#
H_PM_SYNC
SUSCLK
PCH_GPIO29
XDP_DBRESET#_R
PCH_PCIE_WAKE#
DSWODVREN
PCH_GPIO32
PCH_GPIO32
SYS_PWROK
PCH_PWROK
PCH_GPIO29
PCH_RSMRST#
PCH_GPIO72
SUSWARN#
PCH_ACIN
RI#
PM_DRAM_PWRGD
PCH_PWROK_R
SYS_PWROK
DMI_CTX_PRX_N0 <4>
DMI_CRX_PTX_N2 <4>
DMI_CTX_PRX_N1 <4>
DMI_CTX_PRX_N3 <4>
DMI_CTX_PRX_N2 <4>
DMI_CTX_PRX_P0 <4>
DMI_CTX_PRX_P1 <4>
DMI_CTX_PRX_P3 <4>
DMI_CTX_PRX_P2 <4>
DMI_CRX_PTX_N3 <4>
DMI_CRX_PTX_N1 <4>
DMI_CRX_PTX_N0 <4>
DMI_CRX_PTX_P2 <4>
DMI_CRX_PTX_P3 <4>
DMI_CRX_PTX_P1 <4>
DMI_CRX_PTX_P0 <4>
FDI_CTX_PRX_N0 <4>
FDI_CTX_PRX_N1 <4>
FDI_CTX_PRX_N2 <4>
FDI_CTX_PRX_N3 <4>
FDI_CTX_PRX_N4 <4>
FDI_CTX_PRX_N5 <4>
FDI_CTX_PRX_N6 <4>
FDI_CTX_PRX_N7 <4>
FDI_CTX_PRX_P0 <4>
FDI_CTX_PRX_P1 <4>
FDI_CTX_PRX_P2 <4>
FDI_CTX_PRX_P3 <4>
FDI_CTX_PRX_P4 <4>
FDI_CTX_PRX_P5 <4>
FDI_CTX_PRX_P6 <4>
FDI_CTX_PRX_P7 <4>
FDI_FSYNC1 <4>
FDI_LSYNC0 <4>
FDI_FSYNC0 <4>
FDI_INT <4>
FDI_LSYNC1 <4>
XDP_DBRESET# <5>
PM_DRAM_PWRGD <5>
PCH_RSMRST# <40>
PBTN_OUT# <40>
ACIN <40,44,47,48>
PCH_PCIE_WAKE# <35,37>
H_PM_SYNC <5>
PM_SLP_S3# <40>
PM_SLP_S4# <40>
PM_SLP_S5# <40>
SUSCLK <40>
PCH_PWROK <40>
VGATE <40,52>
SYS_PWROK <5>
+1.05VS_VTT
+RTCVCC
+3VALW_PCH
+3VS
+3VALW_PCH
+3VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
4mil width and place
within 500mil of the PCH
Can be left NC
when IAMT is not
support on the
platfrom
DSWODVREN - On Die DSW VR Enable
HEnable
LDisable
*
ALL power OK
tell PCH all power ok
but cpu core
not support AMT APWROK can mux
with PWROK (check list1.0 P.40)
Ring Indicator CRB1.0 PH 10K +3VALW
not support
Deep S4,S5 can NC
PCH EDS1.2 P.74
not support Deep S4,S5 DPWROK mux with PWROK
check list1.0 P.42
R235 10K_0402_5% @ R235 10K_0402_5% @ 1 2
R635 0_0402_5% R635 0_0402_5%
1 2
R247 10K_0402_5% R247 10K_0402_5% 1 2
R597 200_0402_1% R597 200_0402_1% 1 2
T22 PAD@ T22 PAD@
R613 10K_0402_5% R613 10K_0402_5% 1 2
U35
MC74VHC1G08DFT2G_SC70-5
U35
B
2
A
1
Y
4
P
5
G
3
R607 10K_0402_5% R607 10K_0402_5% 1 2
R218 200K_0402_5% R218 200K_0402_5% 1 2
T20 PAD@ T20 PAD@
T21 PAD@ T21 PAD@
T16 PAD
@
T16 PAD
@
R629
10K_0402_5%
R629
10K_0402_5%
1
2
R622 10K_0402_5% R622 10K_0402_5% 1 2
T23 PAD@ T23 PAD@
R559 10K_0402_5% R559 10K_0402_5% 1 2
T78 PAD @ T78 PAD @
R578 750_0402_1% R578 750_0402_1%
1 2
R678 0_0402_5% R678 0_0402_5%
1 2
R610 10K_0402_5% R610 10K_0402_5% 1 2
D9 CH751H-40PT_SOD323-2 D9 CH751H-40PT_SOD323-2
2 1
D
M
I
F
D
I
S
y
s
t
e
m

P
o
w
e
r

M
a
n
a
g
e
m
e
n
t
U33C
HM65@
D
M
I
F
D
I
S
y
s
t
e
m

P
o
w
e
r

M
a
n
a
g
e
m
e
n
t
U33C
HM65@
DMI0RXN
BC24
DMI1RXN
BE20
DMI2RXN
BG18
DMI3RXN
BG20
DMI0RXP
BE24
DMI1RXP
BC20
DMI2RXP
BJ 18
DMI3RXP
BJ 20
DMI0TXN
AW24
DMI1TXN
AW20
DMI2TXN
BB18
DMI3TXN
AV18
DMI0TXP
AY24
DMI1TXP
AY20
DMI2TXP
AY18
DMI3TXP
AU18
DMI_ZCOMP
BJ 24
DMI_IRCOMP
BG25
FDI_RXN0
BJ 14
FDI_RXN1
AY14
FDI_RXN2
BE14
FDI_RXN3
BH13
FDI_RXN4
BC12
FDI_RXN5
BJ 12
FDI_RXN6
BG10
FDI_RXN7
BG9
FDI_RXP0
BG14
FDI_RXP1
BB14
FDI_RXP2
BF14
FDI_RXP3
BG13
FDI_RXP4
BE12
FDI_RXP5
BG12
FDI_RXP6
BJ 10
FDI_RXP7
BH9
FDI_FSYNC0
AV12
FDI_FSYNC1
BC10
FDI_LSYNC0
AV14
FDI_LSYNC1
BB10
FDI_INT
AW16
PMSYNCH
AP14
SLP_SUS#
G16
SLP_S3#
F4
SLP_S4#
H4
SLP_S5#/ GPIO63
D10
SYS_RESET#
K3
SYS_PWROK
P12
PWRBTN#
E20
RI#
A10
WAKE#
B9
SUS_STAT#/ GPIO61
G8
SUSCLK / GPIO62
N14
ACPRESENT / GPIO31
H20
BATLOW#/ GPIO72
E10
PWROK
L22
CLKRUN#/ GPIO32
N3
SUSWARN#/ SUS_PWR_DN_ACK / GPIO30
K16
RSMRST#
C21
DRAMPWROK
B13
SLP_LAN#/ GPIO29
K14
APWROK
L10
DPWROK
E22
DMI2RBIAS
BH21
SLP_A#
G10
DSWVRMEN
A18
SUSACK#
C12
T47 PAD
@
T47 PAD
@
R577 330K_0402_5% R577 330K_0402_5% 1 2
R223 49.9_0402_1% R223 49.9_0402_1%
1 2
R581 330K_0402_5%
@
R581 330K_0402_5%
@
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_DPB_HPD
SDVO_SDATA
SDVO_SCLK
PCH_TXOUT1-
PCH_TXOUT2-
PCH_TXOUT0+
PCH_TXOUT2+
PCH_TXOUT0-
PCH_TXOUT1+
PCH_TXCLK-
PCH_TXCLK+
PCH_CRT_DATA
PCH_CRT_CLK
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
CRT_IREF
IGPU_BKLT_EN
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
CTRL_CLK
CTRL_DATA
LVDS_IBG
LVD_VREF
PCH_DPB_N3
PCH_DPB_P0
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P3
PCH_DPB_N1
PCH_DPB_P2
PCH_DPB_N0
PCH_CRT_CLK
PCH_CRT_DATA
CTRL_CLK
CTRL_DATA
PCH_LCD_CLK
PCH_LCD_DATA
ENBKL IGPU_BKLT_EN IGPU_BKLT_EN
PCH_DPB_HPD
SDVO_SCLK <33>
SDVO_SDATA <33>
PCH_DPB_HPD <33>
PCH_TXCLK- <31>
PCH_TXCLK+ <31>
PCH_TXOUT0- <31>
PCH_TXOUT1- <31>
PCH_TXOUT2- <31>
PCH_TXOUT0+ <31>
PCH_TXOUT1+ <31>
PCH_TXOUT2+ <31>
PCH_CRT_DATA <32>
PCH_CRT_R <32>
PCH_CRT_G <32>
PCH_CRT_B <32>
PCH_ENVDD <31>
DPST_PWM <31>
PCH_LCD_DATA <31>
PCH_CRT_CLK <32>
PCH_DPB_N1 <33>
PCH_DPB_N3 <33>
PCH_DPB_P1 <33>
PCH_DPB_P3 <33>
PCH_DPB_N0 <33>
PCH_DPB_P0 <33>
PCH_DPB_N2 <33>
PCH_DPB_P2 <33>
ENBKL <40>
PCH_LCD_CLK <31>
PCH_CRT_VSYNC <32>
PCH_CRT_HSYNC <32>
+3VS
+3VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Pull high at LVDS conn side.
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
SDVO_CTRLDATA strap pull high
at level shift page
RF request
R02 Modify
R535 150_0402_1% R535 150_0402_1% 1 2
C2044
10P_0402_50V8J
@
C2044
10P_0402_50V8J
@
1
2
R534 150_0402_1% R534 150_0402_1% 1 2
C2043
10P_0402_50V8J
@
C2043
10P_0402_50V8J
@
1
2
R178
1K_0402_0.5%
R178
1K_0402_0.5%
1
2
R157 2.2K_0402_5% R157 2.2K_0402_5% 1 2
R158 2.2K_0402_5% R158 2.2K_0402_5% 1 2
R156 2.2K_0402_5% R156 2.2K_0402_5% 1 2
R177
0_0402_5%
R177
0_0402_5%
1 2
R522 2.2K_0402_5% R522 2.2K_0402_5% 1 2
R521 2.2K_0402_5% R521 2.2K_0402_5% 1 2
C2076 1U_0402_6.3V6K C2076 1U_0402_6.3V6K 1 2
R189
2.37K_0402_1%
R189
2.37K_0402_1%
1 2
L
V
D
S
D
i
g
i
t
a
l

D
i
s
p
l
a
y

I
n
t
e
r
f
a
c
e
C
R
T
U33D
HM65@
L
V
D
S
D
i
g
i
t
a
l

D
i
s
p
l
a
y

I
n
t
e
r
f
a
c
e
C
R
T
U33D
HM65@
L_BKLTCTL
P45
L_BKLTEN
J 47
L_CTRL_CLK
T45
L_CTRL_DATA
P39
L_DDC_CLK
T40
L_DDC_DATA
K47
L_VDD_EN
M45
LVDSA_CLK#
AK39
LVDSA_CLK
AK40
LVDSA_DATA#0
AN48
LVDSA_DATA#1
AM47
LVDSA_DATA#2
AK47
LVDSA_DATA#3
AJ 48
LVDSA_DATA0
AN47
LVDSA_DATA1
AM49
LVDSA_DATA2
AK49
LVDSA_DATA3
AJ 47
LVDSB_CLK#
AF40
LVDSB_CLK
AF39
LVDSB_DATA#0
AH45
LVDSB_DATA#1
AH47
LVDSB_DATA#2
AF49
LVDSB_DATA#3
AF45
LVDSB_DATA0
AH43
DDPB_0N
AV42
DDPB_1N
AV45
LVD_VREFH
AE48
LVD_VREFL
AE47
DDPD_2N
BF42
DDPD_3N
BJ 42
DDPB_2N
AU48
DDPB_3N
AV47
DDPC_0N
AY47
DDPC_1N
AY43
DDPC_2N
BA47
DDPC_3N
BB47
DDPD_0N
BB43
DDPD_1N
BF44
DDPB_0P
AV40
DDPB_1P
AV46
DDPD_2P
BE42
DDPD_3P
BG42
DDPB_2P
AU47
DDPB_3P
AV49
LVDSB_DATA1
AH49
LVDSB_DATA2
AF47
LVDSB_DATA3
AF43
LVD_IBG
AF37
LVD_VBG
AF36
DDPC_1P
AY45
DDPC_0P
AY49
DDPC_2P
BA48
DDPC_3P
BB49
DDPD_0P
BB45
DDPD_1P
BE44
CRT_BLUE
N48
CRT_DDC_CLK
T39
CRT_DDC_DATA
M40
CRT_GREEN
P49
CRT_HSYNC
M47
CRT_IRTN
T42
CRT_RED
T49
CRT_VSYNC
M49
DAC_IREF
T43
SDVO_CTRLCLK
P38
SDVO_CTRLDATA
M39
DDPC_CTRLCLK
P46
DDPC_CTRLDATA
P42
DDPD_CTRLCLK
M43
DDPD_CTRLDATA
M36
DDPB_AUXN
AT49
DDPC_AUXN
AP47
DDPD_AUXN
AT45
DDPB_AUXP
AT47
DDPC_AUXP
AP49
DDPD_AUXP
AT43
DDPB_HPD
AT40
DDPC_HPD
AT38
DDPD_HPD
BH41
SDVO_TVCLKINP
AP45
SDVO_TVCLKINN
AP43
SDVO_STALLP
AM40
SDVO_STALLN
AM42
SDVO_INTP
AP40
SDVO_INTN
AP39 R532 0_0402_5% R532 0_0402_5% 1 2
R533 150_0402_1% R533 150_0402_1% 1 2
R174 2.2K_0402_5% R174 2.2K_0402_5% 1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USBRBIAS
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
PCH_GPIO4
PCH_GPIO52
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4 USB_OC7#
USB_OC4#
USB_OC5#
SMIB
USB_OC3#
USB_OC1#
USB_OC0#
USB_OC2#
DF_TVS
DF_TVS
PCH_GPIO2
USB_OC4#
USB_OC3#
USB_OC0#
SMIB
USB_OC5#
USB_OC7#
USB_OC2#
USB20_N8
USB20_P8
USB20_N10
USB20_P10
PCH_GPIO55
PCH_GPIO5
PCH_GPIO2
PCH_GPIO4
PCH_GPIO3
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
USB20_N1
USB20_P1
VGA_ON
DGPU_HOLD_RST#
VGA_ON
DGPU_HOLD_RST#
DGPU_HOLD_RST#
PCH_GPIO51
PCH_GPIO52
PCH_GPIO5
PCH_GPIO51
PCH_GPIO53
PCH_GPIO53
PCH_GPIO55
CLK_PCI_LPBACK
CLK_PCI_LPC
USB_OC1#
PLT_RST#
PLT_RST#
PCH_GPIO3
PCH_USB3_RX1_N
PCH_USB3_RX1_P
PCH_USB3_TX1_N
PCH_USB3_TX1_P
PLT_RST#
USB20_P2
USB20_N2
PLT_RST#
PLTRST_VGA#
PLTRST_VGA#
USB20_N0
USB20_P0
USB20_N11
USB20_P11
USB20_P8
PLT_RST_BUF# <35,37,40>
H_SNB_IVB# <5>
PLTRST_VGA# <22>
CLK_PCI_LPBACK <14>
CLK_PCI_LPC <40>
USB20_N8 <37>
USB20_P8 <37>
USB20_N10 <31>
USB20_P10 <31>
USB20_N1 <39>
USB20_P1 <39>
VGA_ON <14,25,44,51,53>
PLT_RST# <5>
PCH_USB3_TX1_P <39>
PCH_USB3_RX1_N <39>
PCH_USB3_RX1_P <39>
PCH_USB3_TX1_N <39>
USB20_N2 <39>
USB20_P2 <39>
SMIB
USB20_N0 <39>
USB20_P0 <39>
USB20_N11 <39>
USB20_P11 <39>
USB_OC0# <39>
+3VS
+1.8VS
+3VALW_PCH
+3VS +3VALW
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Set to Vcc when HIGH
DMI Termination Voltage
DF_TVS
Set to Vss when LOW
Within 500 mils
CLOSE TO THE BRANCHING POINT
CMOS Camera (LVDS)
Mini Card 1 (WLAN)
Bit11
GNT1#/
GPIO51
Boot BIOS Strap bit1 BBS1
Bit10
0
0
1
1
0
0
1
1
Boot BIOS
Destination
Reserved
PCI
SPI
LPC
Some PCH config not support USB port 6 & 7.
DG 1.2 CRB1.0 PH 2.2K series 1K
GPIO51 Internal pull high
USB/B (Right side)
For RF request
USB Conn. Colay USB3.0
R02 modify for ESD
R02 modify
R05 Modify
USB/B (Right side)
R05 Modify
BlueTooth
R05 Modify
for IOAC PCH leakage issue
LA-7912PR03
T30 PAD @ T30 PAD @
R296
100_0402_1%
DIS@ R296
100_0402_1%
DIS@
1 2
R596 10K_0402_5% R596 10K_0402_5% 1 2
C2068 0.1U_0402_16V4Z C2068 0.1U_0402_16V4Z
1 2
R588 10K_0402_5% R588 10K_0402_5% 1 2
R2137 10K_0402_5% @ R2137 10K_0402_5% @ 1 2
R595 10K_0402_5% R595 10K_0402_5% 1 2
R633
2.2K_0402_5%
R633
2.2K_0402_5%
1
2
R590 10K_0402_5% R590 10K_0402_5% 1 2
R281
100K_0402_5%
DIS@ R281
100K_0402_5%
DIS@
1
2
T18 PAD @ T18 PAD @
R
S
V
D
N
V
R
A
M
P
C
I
U
S
B
U33E
HM65@
R
S
V
D
N
V
R
A
M
P
C
I
U
S
B
U33E
HM65@
NV_ALE
AV5
NV_CE#0
AY7
NV_CE#1
AV7
NV_CE#2
AU3
NV_CE#3
BG4
NV_CLE
AY1
NV_DQS0
AT10
NV_DQS1
BC8
NV_DQ0 / NV_IO0
AU2
NV_DQ1 / NV_IO1
AT4
NV_DQ10 / NV_IO10
BB5
NV_DQ11 / NV_IO11
BB3
NV_DQ12 / NV_IO12
BB7
NV_DQ13 / NV_IO13
BE8
NV_DQ14 / NV_IO14
BD4
NV_DQ15 / NV_IO15
BF6
NV_DQ2 / NV_IO2
AT3
NV_DQ3 / NV_IO3
AT1
NV_DQ4 / NV_IO4
AY3
NV_DQ5 / NV_IO5
AT5
NV_DQ6 / NV_IO6
AV3
NV_DQ7 / NV_IO7
AV1
NV_DQ8 / NV_IO8
BB1
NV_DQ9 / NV_IO9
BA3
NV_RB#
AT8
NV_RCOMP
AV10
NV_RE#_WRB0
AY5
NV_RE#_WRB1
BA2
NV_WE#_CK0
AT12
NV_WE#_CK1
BF3
PIRQA#
K40
PIRQB#
K38
PIRQC#
H38
PIRQD#
G38
REQ1#/ GPIO50
C46
REQ2#/ GPIO52
C44
REQ3#/ GPIO54
E40
GNT1#/ GPIO51
D47
GNT2#/ GPIO53
E42
GNT3#/ GPIO55
F46
PIRQE#/ GPIO2
G42
PIRQF#/ GPIO3
G40
PIRQG#/ GPIO4
C42
PIRQH#/ GPIO5
D44
USBP0N
C24
USBP0P
A24
USBP1N
C25
USBP1P
B25
USBP2N
C26
USBP2P
A26
USBP3N
K28
USBP3P
H28
USBP4N
E28
USBP4P
D28
USBP5N
C28
USBP5P
A28
USBP6N
C29
USBP6P
B29
USBP7N
N28
USBP7P
M28
USBP8N
L30
USBP8P
K30
USBP9N
G30
USBP9P
E30
USBP10N
C30
USBP10P
A30
USBP11N
L32
USBP11P
K32
USBP12N
G32
USBP12P
E32
USBP13N
C32
USBP13P
A32
PME#
K10
CLKOUT_PCI0
H49
CLKOUT_PCI1
H43
CLKOUT_PCI2
J 48
USBRBIAS#
C33
USBRBIAS
B33
OC0#/ GPIO59
A14
OC1#/ GPIO40
K20
OC2#/ GPIO41
B17
OC3#/ GPIO42
C16
OC4#/ GPIO43
L16
OC5#/ GPIO9
A16
OC6#/ GPIO10
D14
OC7#/ GPIO14
C14
CLKOUT_PCI4
H40
CLKOUT_PCI3
K42
PLTRST#
C6
TP1
BG26
TP2
BJ 26
TP3
BH25
TP6
AH38
TP7
AH37
TP8
AK43
TP9
AK45
TP16
Y13
TP17
K24
TP18
L24
TP19
AB46
TP20
AB45
TP21
B21
TP22
M20
TP23
AY16
TP25
BE28
TP26
BC30
TP27
BE32
TP28
BJ 32
TP29
BC28
TP30
BE30
TP31
BF32
TP32
BG32
TP33
AV26
TP34
BB26
TP35
AU28
TP36
AY30
TP37
AU26
TP38
AY26
TP39
AV28
TP40
AW30
TP4
BJ 16
TP5
BG16
TP15
AM5
TP14
AM4
TP13
AH12
TP12
H3
TP11
N30
TP10
C18
TP24
BG46
C2075 0.1U_0402_16V4Z C2075 0.1U_0402_16V4Z
1 2
U15
U15
IN1
1
IN2
2
OUT
4
V
C
C
5
G
N
D
3
T10 PAD @ T10 PAD @
C2067 0.1U_0402_16V4Z C2067 0.1U_0402_16V4Z
1 2
R170 10K_0402_5% R170 10K_0402_5% 1 2
R153 10K_0402_5% R153 10K_0402_5% 1 2
R773 10K_0402_5% R773 10K_0402_5% 1 2
R173 10K_0402_5% R173 10K_0402_5% 1 2
U14
DIS@ U14
DIS@
IN1
1
IN2
2
OUT
4
V
C
C
5
G
N
D
3
C632
22P_0402_50V8J @
C632
22P_0402_50V8J @
1
2
R169 10K_0402_5% R169 10K_0402_5% 1 2
R616 10K_0402_5% PUSB@ R616 10K_0402_5% PUSB@ 1 2
R162 10K_0402_5% R162 10K_0402_5% 1 2
R181 10K_0402_5% R181 10K_0402_5% 1 2
R626 1K_0402_5% R626 1K_0402_5%
1 2
R165 8.2K_0402_5% R165 8.2K_0402_5% 1 2
R188 8.2K_0402_5% DIS@ R188 8.2K_0402_5% DIS@ 1 2
R172 10K_0402_5% R172 10K_0402_5% 1 2
R612 10K_0402_5% R612 10K_0402_5% 1 2
R152 10K_0402_5% R152 10K_0402_5% 1 2
R180 10K_0402_5% R180 10K_0402_5% 1 2
R166 10K_0402_5% R166 10K_0402_5% 1 2
C633
22P_0402_50V8J @
C633
22P_0402_50V8J @
1
2
R161 10K_0402_5% R161 10K_0402_5% 1 2
R592 10K_0402_5% R592 10K_0402_5% 1 2
R183 10K_0402_5% R183 10K_0402_5% 1 2
R297
100K_0402_5%
R297
100K_0402_5%
1
2
R529 22_0402_5% R529 22_0402_5% 1 2
T12 PAD @ T12 PAD @
R558 22.6_0402_1% R558 22.6_0402_1%
1 2
R531 22_0402_5% R531 22_0402_5% 1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_THRMTRIP#_R
EC_SCI#
PCH_GPIO39
PCH_GPIO28
PCH_PECI_R
PCH_GPIO71
EC_KBRST#
H_THRMTRIP#
EC_SMI#
DGPU_PWROK
PCH_GPIO6
WL_EN#
OPTIMUS_EN#
PCH_GPIO27
PCH_GPIO57
PCH_GPIO48
PCH_GPIO22
EC_LID_OUT#
PCH_GPIO12
PCH_GPIO27
EC_KBRST#
WL_EN#
PCH_GPIO36
PCH_GPIO22
PCH_GPIO6
BT_ON#
PCH_GPIO48
PCH_GPIO57
EC_LID_OUT#
PCH_GPIO12
PCH_GPIO39
PCH_GPIO36
MSATA_DET#
PCH_GPIO69
PCH_GPIO70
MSATA_DET#
PCH_GPIO0
PCH_GPIO0
PCH_GPIO24
PCH_GPIO69 PCH_GPIO70
OPTIMUS_EN#
PCH_GPIO28
PCH_GPIO68
PCH_GPIO24
PCH_GPIO68
PCH_GPIO36
DGPU_PWROK
WWAN_OFF#
WWAN_OFF#
WWAN_OFF#
WL_OFF#
WL_OFF#
BT_ON#
GATEA20 <40>
EC_SCI# <40>
H_PECI <5,40>
H_CPUPWRGD <5>
EC_KBRST# <40>
H_THRMTRIP# <5>
EC_SMI# <40>
EC_LID_OUT# <40>
WL_EN# <39>
MSATA_DET# <37>
PCH_GPIO71 <31>
WWAN_OFF#
WL_OFF# <37,40>
BT_ON# <37,39,40>
+3VS
+3VS
+3VS
+3VALW_PCH
+3VS +3VS
+3VS
+3VALW_PCH
+3VS
+3VSDGPU
+3VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
No use PD to GND Check list1.0 P.70
Deep S4,S5 wake event signal
RTC alarm,Power BTN,GPIO27
CRB1.0 PH10K to +3VALW
GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.
INIT3_3V
This signal has weak internal
PU, can't pull low,leave NC
Checklist1.0 P.59
TS_VSS1~4
PD to GND
CTRL+ALT+DEL
non CPU power ok
130 degree
shut sown
PECI CPU-EC
1 1
Q5Wxx-QC
x
Q5WE0
Q7YE0
Project ID GPIO70
0
0
GPIO69
0
*
0
0 1
GPIO38
0
1
* OPTIMUS
DIS Only
OPTIMUS_EN#
*
This signal has a weak internal pull up
On-Die PLL Voltage Regulator
LOn-Die PLL Voltage Regulator disable
GPIO28
HOn-Die voltage regulator enable
HDA_SYNC PH(PLL =+1.5VS)
GPIO36/GPIO37 is Strap functionality
that requires internal pull down to be sampled at rising PWROK.
When uses as SATA2GP/SATA3GP for mechanical presence detect
-use a external pull up 150K-200K ohm to Vcc3_3
When used as GP input
-ensure GPI is not driven high during strap sampling window
When Unused as GPIO or SATA*GP
-use 8.2K-10K pull-down
check list page 47
R2122 0_0402_5%
@
R2122 0_0402_5%
@ 1 2
R549
10K_0402_5%
R549
10K_0402_5%
1
2
R274 10K_0402_5% NOAC@ R274 10K_0402_5% NOAC@ 1 2
R672 1K_0402_5% R672 1K_0402_5% 1 2
R627 390_0402_5% R627 390_0402_5%
1 2
R649 10K_0402_5% R649 10K_0402_5% 1 2
R277 200K_0402_5% @ R277 200K_0402_5% @ 1 2
R276 10K_0402_5% R276 10K_0402_5% 1 2
R290 10K_0402_5% R290 10K_0402_5% 1 2
R191 10K_0402_5% R191 10K_0402_5% 1 2
R292 10K_0402_5% R292 10K_0402_5% 1 2
R554
10K_0402_5%
R554
10K_0402_5%
1
2
R771 10K_0402_5% R771 10K_0402_5% 1 2
R620 10K_0402_5% R620 10K_0402_5% 1 2
R2053
10K_0402_5%
R2053
10K_0402_5%
1
2
R239 0_0402_5%@R239 0_0402_5%@
1 2
R
2
0
5
4
1
0
K
_
0
4
0
2
_
5
%
DIS@ R
2
0
5
4
1
0
K
_
0
4
0
2
_
5
%
DIS@
1
2
R623 10K_0402_5% @ R623 10K_0402_5% @ 1 2
R546 10K_0402_5% R546 10K_0402_5% 1 2
R272
1K_0402_5%
@
R272
1K_0402_5%
@
1 2
C2050
0.1U_0402_16V4Z
DIS@
C2050
0.1U_0402_16V4Z
DIS@
1
2
R262 10K_0402_5% R262 10K_0402_5% 1 2
R2123
0_0402_5%
@ R2123
0_0402_5%
@ 1 2
R263 10K_0402_5% R263 10K_0402_5% 1 2
R291 200K_0402_5% @ R291 200K_0402_5% @ 1 2
R661 10K_0402_5% R661 10K_0402_5% 1 2
Q
2
0
0
1
B
D
M
N
6
6
D
0
L
D
W
-
7
_
S
O
T
3
6
3
-
6
DIS@ Q
2
0
0
1
B
D
M
N
6
6
D
0
L
D
W
-
7
_
S
O
T
3
6
3
-
6
DIS@
3
4
5
R639 10K_0402_5% DIS@ R639 10K_0402_5% DIS@ 1 2
R619 10K_0402_5% NOAC@ R619 10K_0402_5% NOAC@ 1 2
R279 10K_0402_5% R279 10K_0402_5% 1 2
Q2001A D
M
N
6
6
D
0
L
D
W
-
7
_
S
O
T
3
6
3
-
6
D
I
S
@
Q2001A D
M
N
6
6
D
0
L
D
W
-
7
_
S
O
T
3
6
3
-
6
D
I
S
@
6
1
2
R641 10K_0402_5% R641 10K_0402_5% 1 2
C
P
U
/
M
I
S
C
N
C
T
F
G
P
I
O
U33F
HM65@
C
P
U
/
M
I
S
C
N
C
T
F
G
P
I
O
U33F
HM65@
GPIO27
E16
GPIO28
P8
GPIO24 / MEM_LED
E8
GPIO57
D6
LAN_PHY_PWR_CTRL / GPIO12
C4
VSS_NCTF_1
A4
VSS_NCTF_2
A44
VSS_NCTF_3
A45
VSS_NCTF_4
A46
VSS_NCTF_5
A5
VSS_NCTF_6
A6
VSS_NCTF_7
B3
VSS_NCTF_8
B47
VSS_NCTF_9
BD1
VSS_NCTF_10
BD49
VSS_NCTF_11
BE1
VSS_NCTF_12
BE49
TACH2 / GPIO6
H36
TACH0 / GPIO17
D40
TACH3 / GPIO7
E38
SATA3GP / GPIO37
M5
SATA5GP / GPIO49
V3
SCLOCK / GPIO22
T5
SLOAD / GPIO38
N2
SDATAOUT0 / GPIO39
M3
SDATAOUT1 / GPIO48
V13
PROCPWRGD
AY11
RCIN#
P5
PECI
AU16
THRMTRIP#
AY10
GPIO8
C10
BMBUSY#/ GPIO0
T7
GPIO15
G2
TACH1 / GPIO1
A42
SATA2GP / GPIO36
V8
INIT3_3V#
T14
STP_PCI#/ GPIO34
K1
GPIO35
K4
SATA4GP / GPIO16
U2
VSS_NCTF_32
F49
A20GATE
P4
TACH4 / GPIO68
C40
TACH6 / GPIO70
C41
TACH7 / GPIO71
A40
TACH5 / GPIO69
B41
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
VSS_NCTF_19
BJ 4
VSS_NCTF_20
BJ 44
VSS_NCTF_21
BJ 45
VSS_NCTF_22
BJ 46
VSS_NCTF_23
BJ 5
VSS_NCTF_24
BJ 6
VSS_NCTF_25
C2
VSS_NCTF_26
C48
VSS_NCTF_27
D1
VSS_NCTF_28
D49
VSS_NCTF_29
E1
VSS_NCTF_30
E49
VSS_NCTF_31
F1
NC_4
AK10
NC_3
AH10
NC_2
AK11
NC_1
AH8
NC_5
P37
VSS_NCTF_13
BF1
VSS_NCTF_14
BF49
VSS_NCTF_15
BG2
VSS_NCTF_16
BG48
R278
10K_0402_5%
R278
10K_0402_5%
1
2
R912 10K_0402_5% R912 10K_0402_5% 1 2
C
2
0
5
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
DIS@ C
2
0
5
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
DIS@
1
2
R548
10K_0402_5%
@
R548
10K_0402_5%
@
1
2
R553
10K_0402_5%
@
R553
10K_0402_5%
@
1
2
R768
4.7K_0402_5%
R768
4.7K_0402_5%
1 2
R
2
0
5
5
1
0
0
K
_
0
4
0
2
_
5
%
DIS@ R
2
0
5
5
1
0
0
K
_
0
4
0
2
_
5
%
DIS@
1
2
R911 10K_0402_5% R911 10K_0402_5% 1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCAFDI_VRM
+VCCAPLLEXP
+1.05VS_VTT
+VCCAFDI_VRM
+VCCAFDI_VRM
+VCCTX_LVDS
+VCCA_LVDS
+1.05VS_VCCAPLL_FDI
+VCCADAC
+1.5VS
+VCCAFDI_VRM
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+3VS
+1.05VS_VTT
+1.8VS
+3VS
+3VS
+3VS
+3VS
+1.8VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
VCCVRM = 160mA detal waiting for newest spec
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
0.1uH inductor, 200mA
1700mA
1mA
1mA
40mA
3711mA
47mA
190mA
10mA
228mA
+VCCADAC should be powered up during S0
system state.Note that Thermal Sensor
shares the same power supply rail with DAC
jHDA_SYNC PH(PLL =+1.5VS)
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
GPIO28
HOn-Die PLL voltage regulator enable
place near AT20
place near AB36
VccDFTERM should PH +1.8VS or +3VS
For SPI control logi
Core Well I/O Buffer
DMI buffer logic
Internal PLL and VRM(+1.5VS)
I/O Buffer Voltage
DMI Clock Buffer Voltage
Spread Modulators Power Supply
Differential Clock Buffers Power Supply
Analog power supply for LVDS (Mobile
Only)
Analog power supply for LVDS (Mobile
Only)
VccSSC 1.05
I/O Buffer Voltage
0.095
1.8 V Internal PLL and VRMs (1.8 V for
Desktop)
VccDIFFCLKN 1.05
PCH Power Rail Table
0.055
Processor I/F
PCH Core Well Reference Voltage
Suspend Well Reference Voltag
3.3
1.05
1.05
1.05
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC
VccADPLLA
VccADPLLB
Display DAC Analog Power. This power is
supplied by the core well.
Voltage Rail
VccCore
VccDMI
1.05
5
3.3
0.001
0.001
0.001
0.266
0.001
0.08
0.08
1.3
0.042
5
Voltage
S0 Iccmax
Current(A)
Display PLL A power
1.05
1.05 VccIO 2.925
1.05 VccASW 1.01
3.3 VccSPI 0.02
3.3 VccDSW 0.003
1.8 0.19 VccpNAND
3.3 VccRTC 6 uA
3.3 VccSus3_3
3.3 / 1.5 VccSusHDA
0.266
0.01
VccVRM 1.8 / 1.5 0.16
1.05 VccCLKDMI
VccALVDS 3.3
1.8 VccTX_LVDS 0.06
0.001
0.02
Display PLL B power
Internal Logic Voltage
DMI Buffer Voltage
Core Well I/O buffers
1.05 V Supply for Intel R Management
Engine and Integrated LAN
3.3 V Supply for SPI Controller Logic
3.3v supply for Deep S4/S5 well
1.8V power supply for DF_TVS
Battery Voltage
Suspend Well I/O Buffer Voltage
High Definition Audio Controller Suspend
Voltage
,VCCAPLLSATA
Trace 20mil
R02 Modify
R02 Modify
R02 Modify
R02 Modify
C344
1U_0402_6.3V6K
C344
1U_0402_6.3V6K
1
2
C
3
4
2
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
4
2
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
3
3
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
3
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
6
2
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
6
2
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C703
1U_0402_6.3V6K
C703
1U_0402_6.3V6K
1
2
C
3
2
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
2
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C308
1U_0402_6.3V6K
C308
1U_0402_6.3V6K
1
2
C322
.1U_0402_16V7K
C322
.1U_0402_16V7K
1
2
C300
22U_0805_6.3V6M
C300
22U_0805_6.3V6M
1
2
L31
4.7UH_LQM18FN4R7M00D_20%
L31
4.7UH_LQM18FN4R7M00D_20%
1 2
C
3
1
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
3
1
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C2064
22U_0805_6.3V6M
C2064
22U_0805_6.3V6M
1
2
C
3
4
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
4
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
R257 0_0603_5% R257 0_0603_5% 1 2
POWER
V
C
C

C
O
R
E
D
M
I
V
C
C
I
O
C
R
T
L
V
D
S
F
D
I
N
A
N
D

/

S
P
I
H
V
C
M
O
S
U33G
HM65@
POWER
V
C
C

C
O
R
E
D
M
I
V
C
C
I
O
C
R
T
L
V
D
S
F
D
I
N
A
N
D

/

S
P
I
H
V
C
M
O
S
U33G
HM65@
VCCCORE[1]
AA23
VCCCORE[2]
AC23
VCCCORE[3]
AD21
VCCCORE[4]
AD23
VCCCORE[5]
AF21
VCCCORE[6]
AF23
VCCCORE[7]
AG21
VCCCORE[8]
AG23
VCCCORE[9]
AG24
VCCCORE[10]
AG26
VCCCORE[11]
AG27
VCCCORE[12]
AG29
VCCCORE[13]
AJ 23
VCCCORE[14]
AJ 26
VCCCORE[15]
AJ 27
VCCPNAND[4]
AJ 17
VCCPNAND[3]
AJ 16
VCCIO[17]
AN21
VCCIO[18]
AN26
VCCIO[19]
AN27
VCCIO[20]
AP21
VCCIO[23]
AP26
VCCIO[24]
AT24
VCCIO[15]
AN16
VCCIO[16]
AN17
VCCIO[21]
AP23
VCCIO[22]
AP24
VCCADAC
U48
VCCTX_LVDS[1]
AM37
VCCTX_LVDS[2]
AM38
VCCALVDS
AK36
VCCVRM[3]
AT16
VCCVRM[2]
AP16
VCCAPLLEXP
BJ 22
VCCFDIPLL
BG6
VCCIO[28]
AN19
VCCTX_LVDS[4]
AP37
VCCTX_LVDS[3]
AP36
VSSADAC
U47
VSSALVDS
AK37
VCCIO[27]
AP17
VCC3_3[6]
V33
VCC3_3[7]
V34
VCC3_3[3]
BH29
VCCPNAND[2]
AG17
VCCPNAND[1]
AG16
VCCDMI[1]
AT20
VCCIO[25]
AN33
VCCIO[26]
AN34
VCCCORE[16]
AJ 29
VCCCORE[17]
AJ 31
VCCSPI
V1
VCCIO[1]
AB36
VCCDMI[2]
AU20
C349
.1U_0402_16V7K
C349
.1U_0402_16V7K
1
2
C310
0.01U_0402_16V7K
C310
0.01U_0402_16V7K
1
2
T48 PAD @ T48 PAD @
C
2
0
6
3
0
.
0
1
U
_
0
4
0
2
_
1
6
V
7
K
C
2
0
6
3
0
.
0
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
C
3
2
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
2
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
T19 PAD @ T19 PAD @
L16
0.1UH_MLF1608DR10KT_10%_1608
L16
0.1UH_MLF1608DR10KT_10%_1608
1 2
R149
0_0603_5%
R149
0_0603_5%
1 2
C
6
4
0
0
.
0
1
U
_
0
4
0
2
_
1
6
V
7
K
C
6
4
0
0
.
0
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
C305
0.01U_0402_16V7K
C305
0.01U_0402_16V7K
1
2
C
3
5
3
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
5
3
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
3
3
2
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
3
2
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C313
.1U_0402_16V7K
C313
.1U_0402_16V7K
1
2
C
3
1
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
1
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C347
1U_0402_6.3V6K
C347
1U_0402_6.3V6K
1
2
C
6
4
4
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
6
4
4
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+PCH_V5REF_RUN
+PCH_V5REF_SUS
+3V_VCCPSUS
+VCCA_USBSUS
+VCCAFDI_VRM
+3VS_VCC_CLKF33
+3VS_VCC_CLKF33
+VCCSUS1
+VCCRTCEXT
+VCCSST
+1.05VM_VCCSUS
+VCCAFDI_VRM
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
+VCCSATAPLL
+VCCAPLL_CPY_PCH
+PCH_V5REF_SUS
+PCH_V5REF_RUN
+PCH_VCCDSW
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
PCH_PWR_EN#
PCH_PWR_EN# <35,44>
+3VS +5VS
+3VALW_PCH +5VALW_PCH
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+3VALW_PCH
+1.05VS_VTT
+3VALW_PCH
+3VALW_PCH
+3VS
+1.05VS_VTT
+1.05VS_VTT
+RTCVCC
+VCCAFDI_VRM
+1.05VS_VTT
+1.05VS_VTT
+3VALW_PCH
+3VALW_PCH
+3VS
+1.05VS_VTT
+1.05VS_VTT
+5VALW_PCH +5VALW
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Have internal VRM
1mA
95mA
1mA
903mA
1mA
80mA
80mA
55mA
130mA
1mA
10mA
Place
near BJ8
Place
near AF33,
AF34,AG34
Place
near AF17
Place
near AG33
suppied by internal
1.05V VR Must NC
Place near
P24
Place near
P24
Place near
AJ2
Place near
T34
Place near
AA16,W16
Close P32
Need +3VALW and 0.1U close PCH
Not support Deep S4,S5
connect to +3VALW
,VCCAPLLSATA
GPIO28
suppied by internal
1.05V VR must NC
,VCCAPLLSATA
GPIO28
suppied by internal
1.05V VR Must NC
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
SGA00001700
220U 2.5V M B2
ESR 35mohm@100Khz
+5VALW TO +5VALW_PCH(PCH AUX Power)
R02 Modify
R02 Modify
R02 Modify
R02 Modify
R02 Modify
R02 Modify
R02 Modify
R03 Modify
C
3
0
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
0
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
D8
CH751H-40PT_SOD323-2
D8
2
1
T11 PAD @ T11 PAD @
R197
0_0603_5%
@
R197
0_0603_5%
@
1 2
T62 PAD @ T62 PAD @
C244
1U_0603_10V6K
C244
1U_0603_10V6K
1
2
+
C
2
7
8
3
3
0
U
_
D
2
_
2
V
_
Y
+
C
2
7
8
3
3
0
U
_
D
2
_
2
V
_
Y
1
2
C321
1U_0402_6.3V6K
C321
1U_0402_6.3V6K
1
2
C
7
0
0
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
7
0
0
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
C318
0.1U_0603_25V7K
C318
0.1U_0603_25V7K
1
2
C352
1U_0402_6.3V6K
C352
1U_0402_6.3V6K
1
2
D7
D7
2
1
C
3
2
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
2
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
POWER
S
A
T
A
U
S
B
C
l
o
c
k

a
n
d

M
i
s
c
e
l
l
a
n
e
o
u
s
H
D
A
C
P
U
R
T
C
P
C
I
/
G
P
I
O
/
L
P
C
M
I
S
C
U33J
HM65@
POWER
S
A
T
A
U
S
B
C
l
o
c
k

a
n
d

M
i
s
c
e
l
l
a
n
e
o
u
s
H
D
A
C
P
U
R
T
C
P
C
I
/
G
P
I
O
/
L
P
C
M
I
S
C
U33J
HM65@
DCPSUSBYP
V12
VCCASW[1]
AA19
VCCASW[2]
AA21
VCCASW[3]
AA24
VCCASW[5]
AA27
VCCASW[6]
AA29
VCCSUSHDA
P32
VCCSUS3_3[6]
P24
VCCIO[34]
T26
VCCIO[4]
AD17
VCCASW[7]
AA31
VCCASW[8]
AC26
VCCASW[9]
AC27
VCCASW[10]
AC29
VCCASW[11]
AC31
VCCASW[12]
AD29
V5REF
P34
VCC3_3[4]
T34
VCCRTC
A22
VCCSUS3_3[10]
V24
VCCSUS3_3[9]
V23
VCCSUS3_3[8]
T24
VCCSUS3_3[7]
T23
VCCIO[2]
AC16
VCCADPLLB
BF47
VCCIO[8]
AF33
V5REF_SUS
M26
VCCIO[3]
AC17
DCPSUS[1]
T17
VCCIO[10]
AG33
VCCADPLLA
BD47
VCCVRM[4]
Y49
VCCACLK
AD49
DCPRTC
N16
VCCASW[4]
AA26
VCCIO[9]
AF34
VCCIO[7]
AF17
DCPSST
V16
VCCIO[5]
AF13
VCCASW[22]
T21
VCCASW[23]
V21
VCCASW[21]
T19
VCC3_3[1]
AA16
VCC3_3[8]
W16
VCCSUS3_3[2]
N20
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
VCCSUS3_3[5]
P22
VCCIO[29]
N26
VCCIO[30]
P26
VCCIO[31]
P28
VCCIO[32]
T27
V_PROC_IO
BJ 8
VCCIO[33]
T29
VCCIO[11]
AG34
VCCASW[13]
AD31
VCCASW[14]
W21
VCCASW[15]
W23
VCCASW[16]
W24
VCCASW[17]
W26
VCCASW[18]
W29
VCCASW[19]
W31
VCCASW[20]
W33
VCCIO[6]
AF14
VCCVRM[1]
AF11
VCCIO[12]
AH13
VCCIO[13]
AH14
VCC3_3[2]
AJ 2
VCCAPLLSATA
AK1
DCPSUS[3]
AL24
VCCIO[14]
AL29
DCPSUS[4]
AN23
VCCSUS3_3[1]
AN24
VCCAPLLDMI2
BH23
DCPSUS[2]
V19
VCCDSW3_3
T16
VCC3_3[5]
T38
L11
10UH_LB2012T100MR_20%
L11
10UH_LB2012T100MR_20%
1 2
C
2
0
6
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
2
0
6
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C333
.1U_0402_16V7K
C333
.1U_0402_16V7K
1
2
T15 PAD @ T15 PAD @
C
2
9
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
2
9
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C317
1U_0402_6.3V6K
C317
1U_0402_6.3V6K
1
2
R
2
0
9
0
2
0
K
_
0
4
0
2
_
1
%
R
2
0
9
0
2
0
K
_
0
4
0
2
_
1
%
1
2
T17 PAD @ T17 PAD @
C354
.1U_0402_16V7K
C354
.1U_0402_16V7K
1 2
R202
100_0402_1%
R202
100_0402_1%
1
2
L14
10UH_LB2012T100MR_20%
L14
10UH_LB2012T100MR_20%
1 2
C
6
9
3
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
6
9
3
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
C
2
9
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
2
9
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
T13 PAD @ T13 PAD @
C330
.1U_0402_16V7K
C330
.1U_0402_16V7K
1
2
C
6
9
4
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
6
9
4
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
C
2
7
7
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
2
7
7
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
L12
10UH_LB2012T100MR_20%
L12
10UH_LB2012T100MR_20%
1 2
C351
1U_0402_6.3V6K
C351
1U_0402_6.3V6K
1
2
C
6
8
5
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
6
8
5
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
C
3
3
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
3
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
R148
100_0402_1%
R148
100_0402_1%
1
2
C
3
3
5
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
C
3
3
5
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
1
2
C312
1U_0402_6.3V6K
C312
1U_0402_6.3V6K
1
2
C
6
8
7
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
6
8
7
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
D
G
S
Q2006
AO3413L_SOT23-3
D
G
S
Q2006
AO3413L_SOT23-3
1
2
3
C704
.1U_0402_16V7K
C704
.1U_0402_16V7K
1
2
C343
.1U_0402_16V7K
C343
.1U_0402_16V7K
1
2
C350
1U_0402_6.3V6K
C350
1U_0402_6.3V6K
1
2
C309
.1U_0402_16V7K
C309
.1U_0402_16V7K
1
2
R808
0_0603_5%
@
R808
0_0603_5%
@
1
2
C315
0.1U_0402_16V4Z
C315
0.1U_0402_16V4Z
1
2
C
3
2
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
2
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C348
.1U_0402_16V7K
C348
.1U_0402_16V7K
1
2
C
3
3
6
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
C
3
3
6
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
1
2
C311
1U_0402_6.3V6K
C311
1U_0402_6.3V6K
1
2
C
3
1
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
1
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
T14 PAD @ T14 PAD @
C340
.1U_0402_16V7K
C340
.1U_0402_16V7K
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
U33H
HM65@
U33H
HM65@
VSS[1]
AA17
VSS[2]
AA2
VSS[3]
AA3
VSS[5]
AA34
VSS[6]
AB11
VSS[7]
AB14
VSS[8]
AB39
VSS[9]
AB4
VSS[10]
AB43
VSS[11]
AB5
VSS[12]
AB7
VSS[13]
AC19
VSS[14]
AC2
VSS[15]
AC21
VSS[16]
AC24
VSS[17]
AC33
VSS[18]
AC34
VSS[19]
AC48
VSS[20]
AD10
VSS[21]
AD11
VSS[22]
AD12
VSS[23]
AD13
VSS[24]
AD19
VSS[25]
AD24
VSS[26]
AD26
VSS[27]
AD27
VSS[28]
AD33
VSS[29]
AD34
VSS[30]
AD36
VSS[31]
AD37
VSS[33]
AD39
VSS[34]
AD4
VSS[35]
AD40
VSS[36]
AD42
VSS[37]
AD43
VSS[38]
AD45
VSS[39]
AD46
VSS[43]
AF10
VSS[44]
AF12
VSS[46]
AD16
VSS[47]
AF16
VSS[48]
AF19
VSS[49]
AF24
VSS[50]
AF26
VSS[51]
AF27
VSS[52]
AF29
VSS[53]
AF31
VSS[54]
AF38
VSS[55]
AF4
VSS[56]
AF42
VSS[57]
AF46
VSS[59]
AF7
VSS[60]
AF8
VSS[61]
AG19
VSS[62]
AG2
VSS[63]
AG31
VSS[64]
AG48
VSS[65]
AH11
VSS[66]
AH3
VSS[67]
AH36
VSS[68]
AH39
VSS[69]
AH40
VSS[70]
AH42
VSS[71]
AH46
VSS[72]
AH7
VSS[73]
AJ 19
VSS[76]
AJ 33
VSS[77]
AJ 34
VSS[78]
AK12
VSS[79]
AK3
VSS[80]
AK38
VSS[81]
AK4
VSS[82]
AK42
VSS[83]
AK46
VSS[84]
AK8
VSS[85]
AL16
VSS[86]
AL17
VSS[87]
AL19
VSS[88]
AL2
VSS[89]
AL21
VSS[90]
AL23
VSS[91]
AL26
VSS[92]
AL27
VSS[93]
AL31
VSS[96]
AL48
VSS[97]
AM11
VSS[98]
AM14
VSS[99]
AM36
VSS[100]
AM39
VSS[102]
AM45
VSS[103]
AM46
VSS[104]
AM7
VSS[105]
AN2
VSS[106]
AN29
VSS[107]
AN3
VSS[108]
AN31
VSS[109]
AP12
VSS[110]
AP19
VSS[111]
AP28
VSS[112]
AP30
VSS[113]
AP32
VSS[114]
AP38
VSS[116]
AP42
VSS[117]
AP46
VSS[118]
AP8
VSS[119]
AR2
VSS[120]
AR48
VSS[121]
AT11
VSS[122]
AT13
VSS[123]
AT18
VSS[124]
AT22
VSS[125]
AT26
VSS[126]
AT28
VSS[127]
AT30
VSS[128]
AT32
VSS[131]
AT42
VSS[132]
AT46
VSS[133]
AT7
VSS[134]
AU24
VSS[135]
AU30
VSS[136]
AV16
VSS[137]
AV20
VSS[138]
AV24
VSS[139]
AV30
VSS[140]
AV38
VSS[141]
AV4
VSS[142]
AV43
VSS[143]
AV8
VSS[144]
AW14
VSS[145]
AW18
VSS[146]
AW2
VSS[147]
AW22
VSS[148]
AW26
VSS[149]
AW28
VSS[150]
AW32
VSS[151]
AW34
VSS[152]
AW36
VSS[153]
AW40
VSS[154]
AW48
VSS[155]
AV11
VSS[156]
AY12
VSS[157]
AY22
VSS[158]
AY28
VSS[40]
AD8
VSS[42]
AE3
VSS[45]
AD14
VSS[115]
AP4
VSS[0]
H5
VSS[58]
AF5
VSS[32]
AD38
VSS[4]
AA33
VSS[74]
AJ 21
VSS[75]
AJ 24
VSS[41]
AE2
VSS[129]
AT34
VSS[130]
AT39
VSS[101]
AM43
VSS[95]
AL34
VSS[94]
AL33
U33I
HM65@
U33I
HM65@
VSS[159]
AY4
VSS[160]
AY42
VSS[161]
AY46
VSS[162]
AY8
VSS[163]
B11
VSS[164]
B15
VSS[165]
B19
VSS[166]
B23
VSS[167]
B27
VSS[168]
B31
VSS[169]
B35
VSS[170]
B39
VSS[171]
B7
VSS[173]
BB12
VSS[174]
BB16
VSS[175]
BB20
VSS[176]
BB22
VSS[177]
BB24
VSS[178]
BB28
VSS[179]
BB30
VSS[180]
BB38
VSS[181]
BB4
VSS[182]
BB46
VSS[183]
BC14
VSS[184]
BC18
VSS[185]
BC2
VSS[186]
BC22
VSS[187]
BC26
VSS[188]
BC32
VSS[189]
BC34
VSS[190]
BC36
VSS[191]
BC40
VSS[192]
BC42
VSS[193]
BC48
VSS[194]
BD46
VSS[195]
BD5
VSS[196]
BE22
VSS[197]
BE26
VSS[198]
BE40
VSS[199]
BF10
VSS[200]
BF12
VSS[201]
BF16
VSS[202]
BF20
VSS[203]
BF22
VSS[204]
BF24
VSS[205]
BF26
VSS[206]
BF28
VSS[207]
BD3
VSS[208]
BF30
VSS[209]
BF38
VSS[210]
BF40
VSS[211]
BF8
VSS[212]
BG17
VSS[213]
BG21
VSS[214]
BG33
VSS[215]
BG44
VSS[216]
BG8
VSS[217]
BH11
VSS[218]
BH15
VSS[219]
BH17
VSS[220]
BH19
VSS[222]
BH27
VSS[223]
BH31
VSS[224]
BH33
VSS[225]
BH35
VSS[226]
BH39
VSS[227]
BH43
VSS[228]
BH7
VSS[229]
D3
VSS[230]
D12
VSS[231]
D16
VSS[232]
D18
VSS[233]
D22
VSS[234]
D24
VSS[235]
D26
VSS[236]
D30
VSS[237]
D32
VSS[264]
K7
VSS[265]
L18
VSS[266]
L2
VSS[267]
L20
VSS[268]
L26
VSS[269]
L28
VSS[270]
L36
VSS[271]
L48
VSS[272]
M12
VSS[273]
P16
VSS[274]
M18
VSS[275]
M22
VSS[276]
M24
VSS[277]
M30
VSS[278]
M32
VSS[279]
M34
VSS[280]
M38
VSS[281]
M4
VSS[282]
M42
VSS[283]
M46
VSS[284]
M8
VSS[285]
N18
VSS[286]
P30
VSS[288]
P11
VSS[289]
P18
VSS[290]
T33
VSS[291]
P40
VSS[292]
P43
VSS[293]
P47
VSS[294]
P7
VSS[295]
R2
VSS[296]
R48
VSS[297]
T12
VSS[298]
T31
VSS[299]
T37
VSS[300]
T4
VSS[301]
W34
VSS[302]
T46
VSS[303]
T47
VSS[304]
T8
VSS[305]
V11
VSS[306]
V17
VSS[307]
V26
VSS[308]
V27
VSS[309]
V29
VSS[310]
V31
VSS[311]
V36
VSS[312]
V39
VSS[313]
V43
VSS[314]
V7
VSS[315]
W17
VSS[316]
W19
VSS[238]
D34
VSS[239]
D38
VSS[240]
D42
VSS[241]
D8
VSS[242]
E18
VSS[243]
E26
VSS[244]
G18
VSS[245]
G20
VSS[246]
G26
VSS[247]
G28
VSS[248]
G36
VSS[249]
G48
VSS[250]
H12
VSS[251]
H18
VSS[317]
W2
VSS[318]
W27
VSS[319]
W48
VSS[320]
Y12
VSS[321]
Y38
VSS[322]
Y4
VSS[323]
Y42
VSS[324]
Y46
VSS[325]
Y8
VSS[328]
BG29
VSS[329]
N24
VSS[330]
AJ 3
VSS[287]
N47
VSS[252]
H22
VSS[253]
H24
VSS[254]
H26
VSS[255]
H30
VSS[256]
H32
VSS[257]
H34
VSS[258]
F3
VSS[262]
K39
VSS[263]
K46
VSS[259]
H46
VSS[260]
K18
VSS[261]
K26
VSS[331]
AD47
VSS[333]
B43
VSS[334]
BE10
VSS[335]
BG41
VSS[337]
G14
VSS[338]
H16
VSS[340]
T36
VSS[342]
BG22
VSS[343]
BG24
VSS[344]
C22
VSS[345]
AP13
VSS[172]
F45
VSS[221]
H10
VSS[346]
M14
VSS[347]
AP3
VSS[348]
AP1
VSS[349]
BE16
VSS[350]
BC16
VSS[351]
BG28
VSS[352]
BJ 28

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
XTALIN
XTAL_OUTBUFF
XTAL_SSIN
XTALOUT
I2CS_SCL
I2CS_SDA
XTALIN XTALOUT XTALIN
I2CS_SCL
I2CB_SCL
VGA_DDC_CLK
VGA_DDC_DATA
I2CB_SDA
VGA_LCD_CLK
VGA_LCD_DATA
I2CS_SDA
VGA_LCD_DATA
VGA_LCD_CLK
I2CS_SDA
I2CS_SCL
I2CB_SDA
I2CB_SCL
VGA_DDC_CLK
VGA_DDC_DATA
PEX_TSTCLK_OUT-
PEX_TSTCLK_OUT+
PEX_TREMP
+GPU_PLLVDD
VID_1
VID_2
VID_3
GPIO8
GPIO9
GPU_ACIN
+GPU_PLLVDD
+PLLVDD
VID_4
GPU_GPIO16
VID_5
VID_0
+PLLVDD
VID_5
VID_2
VID_3
VID_0
VID_4
VID_1
GPU_GPIO16
XTAL_OUTBUFF XTAL_SSIN
GPIO9
GPIO8
PEG_HTX_C_GRX_P2 <4>
PEG_HTX_C_GRX_N0 <4>
PEG_GTX_HRX_P11 <4>
PEG_GTX_HRX_N11 <4>
PEG_GTX_HRX_P4 <4>
PEG_GTX_HRX_N4 <4>
PEG_GTX_HRX_P13 <4>
PEG_GTX_HRX_N13 <4>
PEG_GTX_HRX_P6 <4>
PEG_GTX_HRX_N6 <4>
PEG_GTX_HRX_P15 <4>
PEG_GTX_HRX_N15 <4>
PEG_GTX_HRX_P8 <4>
PEG_GTX_HRX_N8 <4>
PEG_GTX_HRX_P2 <4>
PEG_GTX_HRX_N2 <4>
PEG_GTX_HRX_P10 <4>
PEG_GTX_HRX_N10 <4>
PEG_GTX_HRX_P3 <4>
PEG_GTX_HRX_N3 <4>
PEG_GTX_HRX_P12 <4>
PEG_GTX_HRX_N12 <4>
PEG_GTX_HRX_P5 <4>
PEG_GTX_HRX_N5 <4>
PEG_GTX_HRX_P0 <4>
PEG_GTX_HRX_N0 <4>
PEG_GTX_HRX_P14 <4>
PEG_GTX_HRX_N14 <4>
PEG_GTX_HRX_P7 <4>
PEG_GTX_HRX_N7 <4>
PEG_GTX_HRX_P1 <4>
PEG_GTX_HRX_N1 <4>
PEG_GTX_HRX_P9 <4>
PEG_GTX_HRX_N9 <4>
EC_SMB_DA2 <14,40>
EC_SMB_CK2 <14,40>
PEG_CLKREQ# <14>
CLK_PEG_VGA <14>
CLK_PEG_VGA# <14>
PLTRST_VGA# <17>
GPU_VID3 <53>
GPU_VID4 <53>
GPU_VID5 <53>
GPU_VID1 <53>
GPU_VID2 <53>
GPU_VID0 <53>
GPU_OVERT <40>
GPU_THERMAL_ALERT# <40>
GPU_ACIN <40>
+1.05VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
+3VSDGPU
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
OVERT
GPU_VID4 GPIO0
GPIO5
GPIO1
GPIO2
GPIO3
GPIO4
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
O
I/O
GPIO I/O USAGE
MEM_VDD_CTL(PES)
MEM_VREF_CTL
3D Vision
ALERT
GPU_VID3
LCD_BL_PWM
LCD_VCC
LCD_BLEN
GPU_VID1
GPU_VID2
under GPU
close to ball : AE8,AD7
150mA
O
O
O
O
O
O
I/O
O
O
N13X Design Guide page173
= 180R@100MHz(ESR=0.2)
GPIO20,21
N13P/M = NC;
N13P-PES = GPIO20,21
under GPU
close to ball : AD8
04/06 : Add 6bit VID Function.
O
GPIO15
GPIO16
GPIO17
THERM_LOAD_STEP_DOWN
THERM_LOAD_STEP_UP
SLI_RASTER_SYNC
SLI_SWAPRDY
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
I
I
I
I
O
O
I/O
HPD_C
GPIO12
GPIO13
GPIO14
I
O
I HPD_AB
PWR_LEVEL
HPD_D
HPD_E
HPD_F
Reserved
Reserved
GPU_VID0(Real N13P)
33ohm (ESR:0.05)
for GS4, the boot voltage is 0.975V
for GV4, the boot voltage is 0.85V
R02 Modify
add ADPS function
follow Acer Request
R02 modify
R1027 0_0402_5% DIS@ R1027 0_0402_5% DIS@ 1 2
R1001 10K_0402_5% DIS@ R1001 10K_0402_5% DIS@ 1 2
R
1
0
1
8
1
0
K
_
0
4
0
2
_
5
%
G
M
@
R
1
0
1
8
1
0
K
_
0
4
0
2
_
5
%
G
M
@
1
2
R1007 2.2K_0402_5% DIS@ R1007 2.2K_0402_5% DIS@ 1 2
R1015 200_0402_1% DIS@ R1015 200_0402_1% DIS@
1 2
R1037
10K_0402_5%
GM@
SD028100280
R1037
10K_0402_5%
GM@
SD028100280
R1004 2.2K_0402_5% DIS@ R1004 2.2K_0402_5% DIS@ 1 2
C
1
0
6
1
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
D
I
S
@
C
1
0
6
1
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
D
I
S
@
1
2
C1000
0.1U_0402_16V4Z DIS@
C1000
0.1U_0402_16V4Z DIS@
1 2
R
1
0
1
9
1
0
K
_
0
4
0
2
_
5
%
G
L
@
R
1
0
1
9
1
0
K
_
0
4
0
2
_
5
%
G
L
@
1
2
R
1
0
3
4
1
0
K
_
0
4
0
2
_
5
%
G
S
G
L
@R
1
0
3
4
1
0
K
_
0
4
0
2
_
5
%
G
S
G
L
@
1
2
R1024 1M_0402_5%
@
R1024 1M_0402_5%
@
Y1000
27MHZ 10PF 7V27000050
DIS@
Y1000
27MHZ 10PF 7V27000050
DIS@
GND
2
3
3
1
1
GND
4
R1010 2.2K_0402_5% DIS@ R1010 2.2K_0402_5% DIS@ 1 2
R1028 0_0402_5% DIS@ R1028 0_0402_5% DIS@ 1 2
R
1
0
3
8
1
0
K
_
0
4
0
2
_
5
%
@R
1
0
3
8
1
0
K
_
0
4
0
2
_
5
%
@
1
2
L1003
BLM18PG330SN1_2P
DIS@
L1003
BLM18PG330SN1_2P
DIS@
1 2
R1000 10K_0402_5% DIS@ R1000 10K_0402_5% DIS@ 1 2
U1001
N13P-GS-A2 FCBGA 908P
GS@
SA000051880
U1001
N13P-GS-A2 FCBGA 908P
GS@
SA000051880
R
1
0
1
7
1
0
K
_
0
4
0
2
_
5
%
@
R
1
0
1
7
1
0
K
_
0
4
0
2
_
5
%
@
1
2
R
1
0
3
5
1
0
K
_
0
4
0
2
_
5
%
G
S
@R
1
0
3
5
1
0
K
_
0
4
0
2
_
5
%
G
S
@
1
2
Q2005A
DIS@ Q2005A
DIS@
6 1
2
C
1
0
0
5
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
D
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C
1
0
0
5
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
D
I
S
@
1
2
R1030 0_0402_5% DIS@ R1030 0_0402_5% DIS@ 1 2
R
1
0
3
6
1
0
K
_
0
4
0
2
_
5
%
G
S
@R
1
0
3
6
1
0
K
_
0
4
0
2
_
5
%
G
S
@
1
2
C
1
0
0
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
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C
1
0
0
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
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@
1
2
U1001
N13M-GS FCBGA 908P GPU
GM@
SA000057F20
U1001
N13M-GS FCBGA 908P GPU
GM@
SA000057F20
Q2005B
DIS@ Q2005B
DIS@
3 4
5
R1032 0_0402_5% DIS@ R1032 0_0402_5% DIS@ 1 2
R1003 10K_0402_5% DIS@ R1003 10K_0402_5% DIS@ 1 2
R
1
0
2
2
1
0
K
_
0
4
0
2
_
5
%
D
I
S
@
R
1
0
2
2
1
0
K
_
0
4
0
2
_
5
%
D
I
S
@
1
2
C1009
10P_0402_50V8J
DIS@ C1009
10P_0402_50V8J
DIS@
1
2
R1019
10K_0402_5%
GM@
SD028100280
R1019
10K_0402_5%
GM@
SD028100280
R1016 2.49K_0402_1% DIS@ R1016 2.49K_0402_1% DIS@
1 2
R1026 0_0402_5% DIS@ R1026 0_0402_5% DIS@ 1 2
R
1
0
2
1
1
0
K
_
0
4
0
2
_
5
%
G
S
@
R
1
0
2
1
1
0
K
_
0
4
0
2
_
5
%
G
S
@
1
2
R1011 2.2K_0402_5% DIS@ R1011 2.2K_0402_5% DIS@ 1 2
C1008
10P_0402_50V8J
DIS@ C1008
10P_0402_50V8J
DIS@
1
2
R1006 2.2K_0402_5% DIS@ R1006 2.2K_0402_5% DIS@ 1 2
P
C
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C
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Part 1 of 7
D
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C
G
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U1001A
N13P-PES-A1_FCBGA908
GF108@
P
C
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C
L
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Part 1 of 7
D
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I
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C
G
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U1001A
GF108@
PEX_RX0
AN12
PEX_RX0_N
AM12
PEX_RX1
AN14
PEX_RX1_N
AM14
PEX_RX2
AP14
PEX_RX2_N
AP15
PEX_RX3
AN15
PEX_RX3_N
AM15
PEX_RX4
AN17
PEX_RX4_N
AM17
PEX_RX5
AP17
PEX_RX5_N
AP18
PEX_RX6
AN18
PEX_RX6_N
AM18
PEX_RX7
AN20
PEX_RX7_N
AM20
PEX_RX8
AP20
PEX_RX8_N
AP21
PEX_RX9
AN21
PEX_RX9_N
AM21
PEX_RX10
AN23
PEX_RX10_N
AM23
PEX_RX11
AP23
PEX_RX11_N
AP24
PEX_RX12
AN24
PEX_RX12_N
AM24
PEX_RX13
AN26
PEX_RX13_N
AM26
PEX_RX14
AP26
PEX_RX14_N
AP27
PEX_RX15
AN27
PEX_RX15_N
AM27
PEX_TX0
AK14
PEX_TX0_N
AJ 14
PEX_TX1
AH14
PEX_TX1_N
AG14
PEX_TX2
AK15
PEX_TX2_N
AJ 15
PEX_TX3
AL16
PEX_TX3_N
AK16
PEX_TX4
AK17
PEX_TX4_N
AJ 17
PEX_TX5
AH17
PEX_TX5_N
AG17
PEX_TX6
AK18
PEX_TX6_N
AJ 18
PEX_TX7
AL19
PEX_TX7_N
AK19
PEX_TX8
AK20
PEX_TX8_N
AJ 20
PEX_TX9
AH20
PEX_TX9_N
AG20
PEX_TX10
AK21
PEX_TX10_N
AJ 21
PEX_TX11
AL22
PEX_TX11_N
AK22
PEX_TX12
AK23
PEX_TX12_N
AJ 23
PEX_TX13
AH23
PEX_TX13_N
AG23
PEX_TX14
AK24
PEX_TX14_N
AJ 24
PEX_TX15
AL25
PEX_TX15_N
AK25
PEX_REFCLK
AL13
PEX_REFCLK_N
AK13
PEX_RST_N
AJ 12
PEX_TSTCLK_OUT
AJ 26
PEX_TSTCLK_OUT_N
AK26
PEX_TERMP
AP29
PEX_CLKREQ_N
AK12
PEX_WAKE_N
AJ 11
GPIO0
P6
GPIO1
M3
GPIO2
L6
GPIO3
P5
GPIO4
P7
GPIO5
L7
GPIO6
M7
GPIO7
N8
GPIO8
M1
GPIO9
M2
GPIO10
L1
GPIO11
M5
GPIO12
N3
GPIO13
M4
GPIO14
N4
GPIO15
P2
GPIO16
R8
GPIO17
M6
GPIO18
R1
GPIO19
P3
GPIO20
P4
GPIO21
P1
I2CS_SCL
T4
I2CS_SDA
T3
I2CC_SCL
R2
I2CC_SDA
R3
I2CB_SCL
R7
I2CB_SDA
R6
I2CA_SCL
R4
I2CA_SDA
R5
DACA_HSYNC
AM9
DACA_VSYNC
AN9
DACA_RED
AK9
DACA_GREEN
AL10
DACA_BLUE
AL9
DACA_VDD
AG10
DACA_VREF
AP9
DACA_RSET
AP8
PLLVDD
AD8
SP_PLLVDD
AE8
VID_PLLVDD
AD7
XTAL_SSIN
H1
XTAL_IN
H3
XTAL_OUTBUFF
J 4
XTAL_OUT
H2
R1009 2.2K_0402_5% DIS@ R1009 2.2K_0402_5% DIS@ 1 2
R
1
0
3
3
1
0
K
_
0
4
0
2
_
5
%
D
I
S
@
R
1
0
3
3
1
0
K
_
0
4
0
2
_
5
%
D
I
S
@
1
2
C
1
0
0
6
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
D
I
S
@
C
1
0
0
6
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
D
I
S
@
1
2
R
1
0
3
7
1
0
K
_
0
4
0
2
_
5
%
G
L
@R
1
0
3
7
1
0
K
_
0
4
0
2
_
5
%
G
L
@
1
2
C
1
0
0
7
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
D
I
S
@
C
1
0
0
7
2
2
U
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0
8
0
5
_
6
.
3
V
6
M
D
I
S
@
1
2
R1005 2.2K_0402_5% DIS@ R1005 2.2K_0402_5% DIS@ 1 2
R1023
10K_0402_5%
DIS@
R1023
10K_0402_5%
DIS@
1
2
R1025 0_0402_5% @ R1025 0_0402_5% @ 1 2
R
1
0
2
0
1
0
K
_
0
4
0
2
_
5
%
G
L
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R
1
0
2
0
1
0
K
_
0
4
0
2
_
5
%
G
L
@
1
2
R1014 10K_0402_5%
DIS@
R1014 10K_0402_5%
DIS@ 1 2
Q1000B
DIS@ Q1000B
DIS@
3 4
5
R1029
10K_0402_5%
DIS@
R1029
10K_0402_5%
DIS@
1
2
L1001
BLM18PG181SN1D_2P
DIS@
L1001
BLM18PG181SN1D_2P
DIS@
1 2
C
1
0
0
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
0
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
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D
I
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@
1
2
R1020
10K_0402_5%
GM@
SD028100280
R1020
10K_0402_5%
GM@
SD028100280
U1001
N13P-GL-A1 FCBGA 908P
GL@
SA000051A00
U1001
N13P-GL-A1 FCBGA 908P
GL@
SA000051A00
R1008 2.2K_0402_5% DIS@ R1008 2.2K_0402_5% DIS@ 1 2
R1031 0_0402_5% DIS@ R1031 0_0402_5% DIS@ 1 2
Q1000A
DIS@ Q1000A
DIS@
6 1
2

A
A
1 1
MDA[63..48]
MDA[15..0]
MDA[31..16]
MDA[47..32]
CMDA27
CMDA8
CMDA21
MDA56
MDA62
MDA63
MDA59
MDA61
MDA58
MDA60
MDA45
MDA57
MDA44
MDA40
MDA47
MDA41
MDA46
MDA42
MDA33
MDA35
MDA43
MDA28
MDA38
MDA37
MDA34
MDA39
MDA36
MDA20
MDA23
MDA30
MDA31
MDA32
MDA21
MDA25
MDA22
MDA26
MDA24
MDA29
MDA2
MDA15
MDA13
MDA27
MDA0
MDA18
MDA9
MDA8
MDA12
MDA1
MDA3
MDA16
MDA11
MDA10
MDA5
MDA7
MDA14
MDA19
MDA6
MDA17
MDA4
MDA50
MDA54
MDA55
MDA48
MDA49
MDA52
MDA53
MDA51
CMDA15
CMDA2
CMDA9
CMDA22
CMDA16
CMDA3
CMDA28
CMDA10
CMDA23
CMDA17
CMDA4
CMDA11
CMDA24
CMDA29
CMDA5
CMDA18
CMDA0
CMDA12
CMDA25
CMDA6
CMDA19
CMDA30
CMDA13
CMDA26
CMDA7
CMDA20
CMDA14
CMDA1
MDC0
MDC1
MDC2
MDC56
MDC62
MDC63
MDC59
MDC61
MDC58
MDC60
MDC45
MDC57
MDC44
MDC40
MDC47
MDC41
MDC46
MDC42
MDC33
MDC35
MDC43
MDC28
MDC38
MDC37
MDC34
MDC39
MDC36
MDC20
MDC23
MDC30
MDC31
MDC32
MDC21
MDC25
MDC22
MDC26
MDC24
MDC29
MDC15
MDC13
MDC27
MDC18
MDC9
MDC8
MDC12
MDC3
MDC16
MDC11
MDC10
MDC5
MDC7
MDC14
MDC19
MDC6
MDC17
MDC4
MDC50
MDC54
MDC55
MDC48
MDC49
MDC52
MDC53
MDC51
MDC[63..48]
MDC[15..0]
MDC[31..16]
MDC[47..32]
CMDC27
CMDC8
CMDC21
CMDC15
CMDC2
CMDC9
CMDC22
CMDC16
CMDC3
CMDC28
CMDC10
CMDC23
CMDC17
CMDC4
CMDC11
CMDC24
CMDC29
CMDC5
CMDC18
CMDC0
CMDC12
CMDC25
CMDC6
CMDC19
CMDC30
CMDC13
CMDC26
CMDC7
CMDC20
CMDC14
CMDC1
DQMA0
DQMA1
DQMA2 DQMA2
DQMA3
DQMA4 DQMA4
DQMA5
DQMA6
DQMA7
DQSA3
DQSA2
DQSA1
DQSA0
DQSA4
DQSA5
DQSA6
DQSA7
DQSA#0
DQSA#1
DQSA#3
DQSA#2
DQSA#4
DQSA#5
DQSA#6
DQSA#7
DQSC#5
DQSC#0
DQSC#1
DQSC#3
DQSC#2
DQSC#4
DQSC#6
DQSC#7
DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7
DQSC0
DQSC1
DQSC3
DQSC2
DQSC4
DQSC5
DQSC6
DQSC7
FBA_DEBUG0 FBB_DEBUG0
FBB_DEBUG1
+FB_PLLAVDD
FBA_DEBUG1
+FB_PLLAVDD
+FB_PLLAVDD
MDA[15..0] <27>
MDA[63..48] <28>
MDA[47..32] <28>
MDA[31..16] <27>
CMDA[30..0] <27,28>
MDC[15..0] <29>
MDC[63..48] <30>
MDC[47..32] <30>
MDC[31..16] <29>
CLKC0 <29>
CLKC0# <29>
CLKC1 <30>
CLKC1# <30>
CLKA1 <28>
CLKA1# <28>
CLKA0 <27>
CLKA0# <27>
CMDC[30..0] <29,30>
DQMA[3..0] <27>
DQMA[7..4] <28>
DQSA[3..0] <27>
DQSA[7..4] <28>
DQSA#[3..0] <27>
DQSA#[7..4] <28>
DQSC#[3..0] <29>
DQSC#[7..4] <30>
DQMC[3..0] <29>
DQMC[7..4] <30>
DQSC[3..0] <29>
DQSC[7..4] <30>
+1.5VSDGPU +1.5VSDGPU
+FB_PLLAVDD
+1.05VSDGPU +FB_PLLAVDD
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
VRAM Interface
CV48 Under GPU
close to ball : H17
N13P-PES=1.05V
N13P/M=1.0V
100mA 100mA
Under GPU
close to ball : U27
Under GPU
close to ball : K27
33ohm (ESR:0.05)
300mA
M
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Part 3 of 7
U1001C
GF108@
M
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Part 3 of 7
U1001C
GF108@
FBB_D0
G9
FBB_D1
E9
FBB_D2
G8
FBB_D3
F9
FBB_D4
F11
FBB_D5
G11
FBB_D6
F12
FBB_D7
G12
FBB_D8
G6
FBB_D9
F5
FBB_D10
E6
FBB_D11
F6
FBB_D12
F4
FBB_D13
G4
FBB_D14
E2
FBB_D15
F3
FBB_D16
C2
FBB_D17
D4
FBB_D18
D3
FBB_D19
C1
FBB_D20
B3
FBB_D21
C4
FBB_D22
B5
FBB_D23
C5
FBB_D24
A11
FBB_D25
C11
FBB_D26
D11
FBB_D27
B11
FBB_D28
D8
FBB_D29
A8
FBB_D30
C8
FBB_D31
B8
FBB_D32
F24
FBB_D33
G23
FBB_D34
E24
FBB_D35
G24
FBB_D36
D21
FBB_D37
E21
FBB_D38
G21
FBB_D39
F21
FBB_D40
G27
FBB_D41
D27
FBB_D42
G26
FBB_D43
E27
FBB_D44
E29
FBB_D45
F29
FBB_D46
E30
FBB_D47
D30
FBB_D48
A32
FBB_D49
C31
FBB_D50
C32
FBB_D51
B32
FBB_D52
D29
FBB_D53
A29
FBB_D54
C29
FBB_D55
B29
FBB_D56
B21
FBB_D57
C23
FBB_D58
A21
FBB_D59
C21
FBB_D60
B24
FBB_D61
C24
FBB_D62
B26
FBB_D63
C26
FBB_DQM0
E11
FBB_DQM1
E3
FBB_DQM2
A3
FBB_DQM3
C9
FBB_DQM4
F23
FBB_DQM5
F27
FBB_DQM6
C30
FBB_DQM7
A24
FBB_DQS_WP0
D10
FBB_DQS_WP1
D5
FBB_DQS_WP2
C3
FBB_DQS_WP3
B9
FBB_DQS_WP4
E23
FBB_DQS_WP5
E28
FBB_DQS_WP6
B30
FBB_DQS_WP7
A23
FBB_DQS_RN0
D9
FBB_DQS_RN1
E4
FBB_DQS_RN2
B2
FBB_DQS_RN3
A9
FBB_DQS_RN4
D22
FBB_DQS_RN5
D28
FBB_DQS_RN6
A30
FBB_DQS_RN7
B23
FBB_CMD0
D13
FBB_CMD1
E14
FBB_CMD2
F14
FBB_CMD3
A12
FBB_CMD4
B12
FBB_CMD5
C14
FBB_CMD6
B14
FBB_CMD7
G15
FBB_CMD8
F15
FBB_CMD9
E15
FBB_CMD10
D15
FBB_CMD11
A14
FBB_CMD12
D14
FBB_CMD13
A15
FBB_CMD14
B15
FBB_CMD15
C17
FBB_CMD16
D18
FBB_CMD17
E18
FBB_CMD18
F18
FBB_CMD19
A20
FBB_CMD20
B20
FBB_CMD21
C18
FBB_CMD22
B18
FBB_CMD23
G18
FBB_CMD24
G17
FBB_CMD25
F17
FBB_CMD26
D16
FBB_CMD27
A18
FBB_CMD28
D17
FBB_CMD29
A17
FBB_CMD30
B17
FBB_CMD31
E17
FBB_CMD_RFU0
C12
FBB_CMD_RFU1
C20
FBB_DEBUG0
G14
FBB_DEBUG1
G20
FBB_CLK0
D12
FBB_CLK0_N
E12
FBB_CLK1
E20
FBB_CLK1_N
F20
FBB_WCK01
F8
FBB_WCK01_N
E8
FBB_WCK23
A5
FBB_WCK23_N
A6
FBB_WCK45
D24
FBB_WCK45_N
D25
FBB_WCK67
B27
FBB_WCK67_N
C27
FBB_WCKB01
D6
FBB_WCKB01_N
D7
FBB_WCKB23
C6
FBB_WCKB23_N
B6
FBB_WCKB45
F26
FBB_WCKB45_N
E26
FBB_WCKB67
A26
FBB_WCKB67_N
A27
FBB_PLL_AVDD
H17
L1000
BLM18PG330SN1_2P
DIS@
L1000
BLM18PG330SN1_2P
DIS@
1 2
M
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Part 2 of 7
U1001B
GF108@
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Part 2 of 7
U1001B
GF108@
FBA_D0
L28
FBA_D1
M29
FBA_D2
L29
FBA_D3
M28
FBA_D4
N31
FBA_D5
P29
FBA_D6
R29
FBA_D7
P28
FBA_D8
J 28
FBA_D9
H29
FBA_D10
J 29
FBA_D11
H28
FBA_D12
G29
FBA_D13
E31
FBA_D14
E32
FBA_D15
F30
FBA_D16
C34
FBA_D17
D32
FBA_D18
B33
FBA_D19
C33
FBA_D20
F33
FBA_D21
F32
FBA_D22
H33
FBA_D23
H32
FBA_D24
P34
FBA_D25
P32
FBA_D26
P31
FBA_D27
P33
FBA_D28
L31
FBA_D29
L34
FBA_D30
L32
FBA_D31
L33
FBA_D32
AG28
FBA_D33
AF29
FBA_D34
AG29
FBA_D35
AF28
FBA_D36
AD30
FBA_D37
AD29
FBA_D38
AC29
FBA_D39
AD28
FBA_D40
AJ 29
FBA_D41
AK29
FBA_D42
AJ 30
FBA_D43
AK28
FBA_D44
AM29
FBA_D45
AM31
FBA_D46
AN29
FBA_D47
AM30
FBA_D48
AN31
FBA_D49
AN32
FBA_D50
AP30
FBA_D51
AP32
FBA_D52
AM33
FBA_D53
AL31
FBA_D54
AK33
FBA_D55
AK32
FBA_D56
AD34
FBA_D57
AD32
FBA_D58
AC30
FBA_D59
AD33
FBA_D60
AF31
FBA_D61
AG34
FBA_D62
AG32
FBA_D63
AG33
FBA_CMD3
R34
FBA_CMD8
V28
FBA_CMD2
U29
FBA_CMD21
AA32
FBA_CMD24
Y29
FBA_CMD23
Y28
FBA_CMD26
Y30
FBA_CMD7
U28
FBA_CMD15
Y32
FBA_CMD13
V34
FBA_CMD4
R33
FBA_CMD18
AA28
FBA_CMD29
Y34
FBA_CMD27
AA34
FBA_CMD6
U33
FBA_CMD17
AA29
FBA_CMD19
AC34
FBA_CMD22
AA33
FBA_CMD12
U31
FBA_CMD28
Y31
FBA_CMD10
V30
FBA_CMD25
W31
FBA_CMD9
V29
FBA_CMD1
T31
FBA_CMD11
U34
FBA_CMD0
U30
FBA_CMD5
U32
FBA_DQM0
P30
FBA_DQM1
F31
FBA_DQM2
F34
FBA_DQM3
M32
FBA_DQM4
AD31
FBA_DQM5
AL29
FBA_DQM6
AM32
FBA_DQM7
AF34
FBA_DQS_RN0
M30
FBA_DQS_RN1
H30
FBA_DQS_RN2
E34
FBA_DQS_RN3
M34
FBA_DQS_RN4
AF30
FBA_DQS_RN5
AK31
FBA_DQS_RN6
AM34
FBA_DQS_RN7
AF32
FBA_DQS_WP0
M31
FBA_DQS_WP1
G31
FBA_DQS_WP2
E33
FBA_DQS_WP3
M33
FBA_DQS_WP4
AE31
FBA_DQS_WP5
AK30
FBA_DQS_WP6
AN33
FBA_DQS_WP7
AF33
FBA_CMD16
AA31
FBA_CMD20
AC33
FBA_CMD14
V33
FBA_CMD30
Y33
FBA_CMD31
V31
FBA_CLK0_N
R31
FBA_WCK45_N
AG31
FBA_CLK0
R30
FBA_WCK67
AJ 34
FBA_WCK23
H34
FBA_WCK01_N
L30
FBA_WCK01
K31
FBA_WCK67_N
AK34
FBA_WCK23_N
J 34
FBA_CLK1_N
AC31
FBA_WCK45
AG30
FBA_CLK1
AB31
FBA_WCKB01
J 30
FBA_WCKB01_N
J 31
FBA_WCKB23
J 32
FBA_WCKB23_N
J 33
FBA_WCKB45
AH31
FBA_WCKB45_N
AJ 31
FBA_WCKB67
AJ 32
FBA_WCKB67_N
AJ 33
FBA_PLL_AVDD
U27
FBA_CMD_RFU0
R32
FBA_CMD_RFU1
AC32
FB_VREF
H26
FB_CLAMP
E1
FB_DLL_AVDD
K27
FBA_DEBUG0
R28
FBA_DEBUG1
AC28
R1040 60.4_0402_1% DIS@ R1040 60.4_0402_1% DIS@ 1 2 R1039 60.4_0402_1% DIS@ R1039 60.4_0402_1% DIS@ 1 2
C
1
0
1
4
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
D
I
S
@
C
1
0
1
4
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
D
I
S
@
1
2
R1041 60.4_0402_1% DIS@ R1041 60.4_0402_1% DIS@ 1 2
C
1
0
1
3
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
C
1
0
1
3
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
1
2
C1010
0.1U_0402_16V4Z
DIS@ C1010
0.1U_0402_16V4Z
DIS@
1 2
C
1
0
1
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
C
1
0
1
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
1
2
C
1
0
1
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
1
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
1
2
R1042 60.4_0402_1% DIS@ R1042 60.4_0402_1% DIS@ 1 2
C1011 0.1U_0402_16V4Z
DIS@
C1011 0.1U_0402_16V4Z
DIS@
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ROM_SCLK
ROM_SI STRAP0
ROM_SO
STRAP2
STRAP1
ROM_SCLK
ROM_CS#
ROM_SO
ROM_SI
VSSSENSE_VGA_R
VCCSENSE_VGA_R
J TAG_TDI
J TAG_TDO
J TAG_TRST
J TAG_TMS
J TAG_TCK
STRAP3
STRAP4
STRAP0
STRAP1
STRAP2
MULTI_STRAP_REF0_GND
STRAP3
STRAP4
VCCSENSE_VGA <53>
VSSSENSE_VGA <53>
+3VSDGPU +3VSDGPU
+3VSDGPU
+3VSDGPU
Title
Date: Sheet of
4019ID
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
C
Title
Date: Sheet of
4019ID
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
C
Title
Date: Sheet of
4019ID
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
C
Straps
MULTI LEVEL STRAPS
R
PU 45K
R
PU 45K
R
PD 5K
R
PD 5K
64M* 16* 8
1GB
900 MHz
strap0 strap1 strap2 ROM_SI ROM_SO ROM_SCLK Memory Size
128M* 16* 8
2GB
Frenq. strap3 strap4
For N13P-GS(QS) strap table (PN:SA000051880)
GPU
Hynix
SA000041S40
Memory Config
Hynix
SA00003YO20 N13P-GS
N13P-GS
R
PU 10K
R
PU 10K
R
PD 15K
R
PD 35K
900 MHz
R
PD 5K
R
PD 5K
R
PD 45K
R
PD 45K
R
PU 5K
R
PU 5K
R
PU 45K
R
PU 45K
R
PD 45K
R
PD 45K
64M* 16* 8
1GB
900 MHz
128M* 16* 8
2GB
Frenq. strap3 strap4 GPU
Hynix
SA000041S40
Memory Config
Hynix
SA00003YO20
N13P-GS
N13P-GS R
PD 15K
R
PD 35K
900 MHz
For N13P-GL(QS) strap table (PN:SA000051A00)
R
PD 15K
R
PD 15K
R
PU 10K
R
PU 10K
n/a
n/a
n/a
n/a
R
PD 10K
R
PD 10K
R
PD 15K
R
PD 15K
R
PD 10K
R
PU 10K
900 MHz
128M* 16* 8
2GB
Frenq. strap3 strap4
For N13M-GS(QS) strap table (PN:SA000051A00)
GPU Memory Config
Hynix
SA00003YO20
R
PD 10K
R
PD 10K
N13M-GS R
PU 10K
R
PD 10K
R
PD 10K
STRAP2
ROM_SO
ROM_SCLK
R
PU 10K
STRAP3
STRAP4
R04 modify
R04 modify
R04 modify
STRAP1
R1063 10K_0402_5%
DIS@
R1063 10K_0402_5%
DIS@ 1 2
R1059
10K_0402_1%
GM@
SD034100280
R1059
10K_0402_1%
GM@
SD034100280
R1066 10K_0402_5% DIS@ R1066 10K_0402_5% DIS@ 1 2
Part 4 of 7
L
V
D
S
/
T
M
D
S
N
C
GENERAL
SERIAL
TEST
U1001D
GF108@
Part 4 of 7
L
V
D
S
/
T
M
D
S
N
C
GENERAL
SERIAL
TEST
U1001D
GF108@
IFPA_TXC_N
AN6
IFPA_TXC
AM6
NC
P8
NC
AC6
NC
AJ 28
NC
AJ 4
NC
AJ 5
NC
AL11
NC
C15
NC
D19
NC
D20
NC
D23
NC
D26
NC
H31
NC
T8
IFPA_TXD0
AP3
IFPA_TXD0_N
AN3
IFPA_TXD1
AN5
IFPA_TXD1_N
AM5
IFPA_TXD2
AL6
IFPA_TXD2_N
AK6
IFPA_TXD3
AJ 6
IFPA_TXD3_N
AH6
IFPB_TXC
AJ 9
IFPB_TXC_N
AH9
IFPB_TXD4
AP6
IFPB_TXD4_N
AP5
IFPB_TXD5
AM7
IFPB_TXD5_N
AL7
IFPB_TXD6
AN8
IFPB_TXD6_N
AM8
IFPB_TXD7
AK8
IFPB_TXD7_N
AL8
IFPC_L0
AK1
IFPC_L0_N
AJ 1
IFPC_L1
AJ 3
IFPC_L1_N
AJ 2
IFPC_L2
AH3
IFPC_L2_N
AH4
IFPC_L3
AG5
IFPC_L3_N
AG4
IFPD_L0
AM1
IFPD_L0_N
AM2
IFPD_L1
AM3
IFPD_L1_N
AM4
NC
V32
IFPD_L2_N
AL4
IFPD_L3_N
AK5
IFPD_L2
AL3
IFPD_L3
AK4
IFPE_L0
AD2
IFPE_L0_N
AD3
IFPE_L1
AD1
IFPE_L1_N
AC1
IFPE_L2
AC2
IFPE_L2_N
AC3
IFPE_L3
AC4
IFPE_L3_N
AC5
IFPF_L0
AE3
IFPF_L0_N
AE4
IFPF_L1
AF4
IFPF_L1_N
AF5
IFPF_L2
AD4
IFPF_L2_N
AD5
IFPF_L3
AG1
IFPF_L3_N
AF1
STRAP0
J 2
STRAP1
J 7
STRAP2
J 6
CEC
L3
THERMDP
K3
THERMDN
K4
ROM_CS_N
H6
ROM_SI
H5
ROM_SO
H7
ROM_SCLK
H4
IFPF_AUX_I2CZ_SCL
AF3
IFPF_AUX_I2CZ_SDA_N
AF2
IFPE_AUX_I2CY_SCL
AB3
IFPE_AUX_I2CY_SDA_N
AB4
IFPD_AUX_I2CX_SCL
AK3
IFPD_AUX_I2CX_SDA_N
AK2
IFPC_AUX_I2CW_SCL
AG3
IFPC_AUX_I2CW_SDA_N
AG2
VDD_SENSE
L4
GND_SENSE
L5
BUFRST_N
L2
MULTI_STRAP_REF0_GND
J 1
TESTMODE
AK11
J TAG_TCK
AM10
J TAG_TDI
AM11
J TAG_TDO
AP12
J TAG_TMS
AP11
J TAG_TRST_N
AN11
STRAP3
J 5
STRAP4
J 3
R
1
0
4
6
3
4
.
8
K
_
0
4
0
2
_
1
%
@
R
1
0
4
6
3
4
.
8
K
_
0
4
0
2
_
1
%
@
1
2
T4 PAD
@
T4 PAD
@
R1057
45.3K_0402_1%
GL@
SD034453280
R1057
45.3K_0402_1%
GL@
SD034453280
T3 PAD
@
T3 PAD
@
R1061 10K_0402_5%
DIS@
R1061 10K_0402_5%
DIS@
1 2
R
1
0
5
5
1
5
K
_
0
4
0
2
_
5
%
G
L
@
R
1
0
5
5
1
5
K
_
0
4
0
2
_
5
%
G
L
@
1
2
R1067 40.2K_0402_1%
GSGL@
R1067 40.2K_0402_1%
GSGL@ 1 2
R
1
0
5
0
4
.
9
9
K
_
0
4
0
2
_
1
%
G
S
@
R
1
0
5
0
4
.
9
9
K
_
0
4
0
2
_
1
%
G
S
@
1
2
R
1
0
5
7
4
.
9
9
K
_
0
4
0
2
_
1
%
G
S
@
R
1
0
5
7
4
.
9
9
K
_
0
4
0
2
_
1
%
G
S
@
1
2
R1049
10K_0402_1%
GM@
SD034100280
R1049
10K_0402_1%
GM@
SD034100280
R
1
0
5
9
4
.
9
9
K
_
0
4
0
2
_
1
%
G
S
@
R
1
0
5
9
4
.
9
9
K
_
0
4
0
2
_
1
%
G
S
@
1
2
R
1
0
4
7
1
0
K
_
0
4
0
2
_
1
%
@
R
1
0
4
7
1
0
K
_
0
4
0
2
_
1
%
@
1
2
R1045
10K_0402_1%
GM@
SD034100280
R1045
10K_0402_1%
GM@
SD034100280
R1064 10K_0402_5% DIS@ R1064 10K_0402_5% DIS@ 1 2
R1062 10K_0402_5%
DIS@
R1062 10K_0402_5%
DIS@
1 2
R1060 0_0402_5%
DIS@
R1060 0_0402_5%
DIS@ 1 2
R
1
0
4
5
1
0
K
_
0
4
0
2
_
1
%
G
L
@
R
1
0
4
5
1
0
K
_
0
4
0
2
_
1
%
G
L
@
1
2
R
1
0
5
4
1
0
K
_
0
4
0
2
_
5
%
G
L
@
R
1
0
5
4
1
0
K
_
0
4
0
2
_
5
%
G
L
@
1
2
R
1
0
4
9
1
0
K
_
0
4
0
2
_
1
%
G
S
@
R
1
0
4
9
1
0
K
_
0
4
0
2
_
1
%
G
S
@
1
2
R
1
0
4
8
4
.
9
9
K
_
0
4
0
2
_
1
%
@
R
1
0
4
8
4
.
9
9
K
_
0
4
0
2
_
1
%
@
1
2
T5 PAD
@
T5 PAD
@
R1065 10K_0402_5% @ R1065 10K_0402_5% @ 1 2
R
1
0
5
2
4
5
.
3
K
_
0
4
0
2
_
1
%
G
S
@
R
1
0
5
2
4
5
.
3
K
_
0
4
0
2
_
1
%
G
S
@
1
2
T2 PAD
@
T2 PAD
@
R
1
0
5
1
1
0
K
_
0
4
0
2
_
1
%
G
M
@
R
1
0
5
1
1
0
K
_
0
4
0
2
_
1
%
G
M
@
1
2
R
1
0
5
3
3
4
.
8
K
_
0
4
0
2
_
1
%
X
7
6
@
R
1
0
5
3
3
4
.
8
K
_
0
4
0
2
_
1
%
X
7
6
@
1
2
R
1
0
5
8
1
5
K
_
0
4
0
2
_
5
%
G
S
@
R
1
0
5
8
1
5
K
_
0
4
0
2
_
5
%
G
S
@
1
2
R1052
10K_0402_1%
GM@
SD034100280
R1052
10K_0402_1%
GM@
SD034100280
R1056 0_0402_5%
DIS@
R1056 0_0402_5%
DIS@ 1 2
R
1
0
4
4
1
0
K
_
0
4
0
2
_
1
%
G
M
@
R
1
0
4
4
1
0
K
_
0
4
0
2
_
1
%
G
M
@
1
2
R
1
0
4
3
4
5
.
3
K
_
0
4
0
2
_
1
%
G
S
G
L
@
R
1
0
4
3
4
5
.
3
K
_
0
4
0
2
_
1
%
G
S
G
L
@
1
2
R1055
10K_0402_1%
GM@
SD034100280
R1055
10K_0402_1%
GM@
SD034100280

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VDD33
+PEX_PLLVDD
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
+IFPAB_IOVDD
+IFPEF_PLLVDD
+IFPEF_IOVDD
+IFPAB_PLLVDD
+IFPC_IOVDD
+IFPC_PLLVDD
+PEX_PLL_HVDD
+IFPD_IOVDD
+IFPD_PLLVDD
FB_VDDQ_SENSE
FB_GND_SENSE
+VDD33
3
V
S
d
e
la
y
_
g
a
t
e
3VSdelay_gate
VGA_ON <14,17,44,51,53>
+1.05VSDGPU
+1.05VSDGPU
+1.5VSDGPU
+3VSDGPU
+1.05VSDGPU
+3VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+3VSDGPU
+3VALW
+3VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
370mA
7200mA
150mA
120mA
2700 mA
Near GPU
total 2700mA
Design guide page.68
Design guide no define
N13P
Reference Sch = 300R@100MHz
Design Guide page69 ___
Under GPU
Near GPU
Near GPU
Near GPU
Design guide no define
150mA
Under GPU
Under GPU (one per pin)
Under GPU
Under GPU
Near GPU Under GPU
+3VS to +3VSDGPU for GPU
100mil(1.5A)
Modify R03
Q35A
DIS@
Q35A
DIS@
6
1
2
C
1
0
6
0
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
D
I
S
@
C
1
0
6
0
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
D
I
S
@
1
2
C
5
9
0
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
DIS@ C
5
9
0
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
DIS@
1
2
R1076 10K_0402_5% DIS@ R1076 10K_0402_5% DIS@ 1 2
C
1
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0
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7
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@
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R1131 10K_0402_5% DIS@ R1131 10K_0402_5% DIS@ 1 2
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0
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D
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2
R1079 10K_0402_5% DIS@ R1079 10K_0402_5% DIS@ 1 2
C612
0.1U_0603_25V7K
DIS@
C612
0.1U_0603_25V7K
DIS@
1
2
C
1
0
3
9
1
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_
0
4
0
2
_
6
.
3
V
6
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D
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C
1
0
3
9
1
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0
4
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1
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6
0
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3
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7
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0
6
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1
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1
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0
4
0
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6
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3
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6
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1
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0
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6
.
3
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6
K
D
I
S
@
1
2
R1075 40.2_0402_1%
DIS@
R1075 40.2_0402_1%
DIS@ 1 2
C
1
0
2
7
0
.
1
U
_
0
4
0
2
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1
6
V
4
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D
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S
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C
1
0
2
7
0
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1
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0
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C603
0.1U_0603_25V7K
DIS@
C603
0.1U_0603_25V7K
DIS@
1
2
C
1
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4
1
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0
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0
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6
.
3
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1
0
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0
4
0
2
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6
.
3
V
6
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D
I
S
@
1
2
R515
100K_0402_5%
DIS@
R515
100K_0402_5%
DIS@
1
2
C
1
0
2
3
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
D
I
S
@
C
1
0
2
3
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
D
I
S
@
1
2
R1068
0_0603_5%
DIS@
R1068
0_0603_5%
DIS@ 1 2
C1049 0.1U_0402_16V4Z
DIS@
C1049 0.1U_0402_16V4Z
DIS@ 1 2
C
1
0
3
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
3
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
1
2
R1081 10K_0402_5% DIS@ R1081 10K_0402_5% DIS@ 1 2
R519
4.7K_0402_5%
DIS@
R519
4.7K_0402_5%
DIS@ 1 2
C
1
0
5
6
0
.
1
U
_
0
4
0
2
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1
6
V
4
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D
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S
@
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1
0
5
6
0
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1
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_
0
4
0
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1
6
V
4
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S
@
1
2
C
6
0
2
4
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7
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0
6
0
3
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6
.
3
V
6
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DIS@ C
6
0
2
4
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7
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_
0
6
0
3
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6
.
3
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6
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DIS@
1
2
C
1
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2
8
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0
4
0
2
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6
.
3
V
6
K
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S
@
C
1
0
2
8
1
U
_
0
4
0
2
_
6
.
3
V
6
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S
@
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2
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1
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4
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7
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_
0
6
0
3
_
6
.
3
V
6
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@
C
1
0
1
8
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
D
I
S
@
1
2
L1002
0_0603_5%
GM@
SD013000080
L1002
0_0603_5%
GM@
SD013000080
C
1
0
2
0
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
D
I
S
@
C
1
0
2
0
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
D
I
S
@
1
2
C
1
0
3
0
1
0
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_
0
6
0
3
_
6
.
3
V
6
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D
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S
@
C
1
0
3
0
1
0
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_
0
6
0
3
_
6
.
3
V
6
M
D
I
S
@
1
2
R1078 1K_0402_5% @ R1078 1K_0402_5% @ 1 2
Part 5 of 7
P
O
W
E
R
U1001E
GF108@
Part 5 of 7
P
O
W
E
R
U1001E
GF108@
PEX_IOVDDQ_0
AG13
PEX_IOVDDQ_1
AG15
PEX_IOVDDQ_2
AG16
PEX_IOVDDQ_3
AG18
PEX_IOVDDQ_4
AG25
PEX_IOVDDQ_5
AH15
PEX_IOVDDQ_6
AH18
PEX_IOVDDQ_7
AH26
PEX_IOVDDQ_8
AH27
PEX_IOVDDQ_9
AJ 27
PEX_IOVDDQ_10
AK27
PEX_IOVDDQ_11
AL27
PEX_IOVDDQ_12
AM28
PEX_IOVDDQ_13
AN28
PEX_IOVDD_0
AG19
PEX_IOVDD_1
AG21
PEX_IOVDD_2
AG22
PEX_IOVDD_3
AG24
PEX_IOVDD_4
AH21
PEX_SVDD_3V3
AG12
VDD33_0
J 8
VDD33_1
K8
VDD33_2
L8
VDD33_3
M8
PEX_PLL_HVDD
AH12
FBVDDQ_0
AA27
FBVDDQ_1
AA30
FBVDDQ_2
AB27
FBVDDQ_3
AB33
FBVDDQ_4
AC27
FBVDDQ_5
AD27
FBVDDQ_6
AE27
FBVDDQ_7
AF27
FBVDDQ_8
AG27
FBVDDQ_9
B13
FBVDDQ_10
B16
FBVDDQ_11
B19
FBVDDQ_12
E13
FBVDDQ_13
E16
FBVDDQ_14
E19
FBVDDQ_15
H10
FBVDDQ_16
H11
FBVDDQ_17
H12
FBVDDQ_18
H13
FBVDDQ_19
H14
FBVDDQ_20
H15
FBVDDQ_21
H16
FBVDDQ_22
H18
FBVDDQ_23
H19
FBVDDQ_24
H20
FBVDDQ_25
H21
FBVDDQ_26
H22
FBVDDQ_27
H23
FBVDDQ_28
H24
FBVDDQ_29
H8
FBVDDQ_30
H9
FBVDDQ_31
L27
FBVDDQ_32
M27
FBVDDQ_33
N27
FBVDDQ_34
P27
FBVDDQ_35
R27
FBVDDQ_36
T27
FBVDDQ_37
T30
FBVDDQ_38
T33
FBVDDQ_39
V27
FBVDDQ_40
W27
FBVDDQ_41
W30
FBVDDQ_42
W33
FBVDDQ_43
Y27
PEX_IOVDD_5
AH25
PEX_PLLVDD
AG26
IFPA_IOVDD
AG8
IFPB_IOVDD
AG9
IFPAB_PLLVDD
AH8
IFPAB_RSET
AJ 8
IFPC_IOVDD
AF6
IFPC_PLLVDD
AF7
IFPC_RSET
AF8
IFPD_IOVDD
AG6
IFPD_PLLVDD
AG7
IFPD_RSET
AN2
IFPE_IOVDD
AC7
IFPEF_PLVDD
AB8
IFPEF_RSET
AD6
IFPF_IOVDD
AC8
FB_VDDQ_SENSE
F1
FB_GND_SENSE
F2
FB_CAL_PD_VDDQ
J 27
FB_CAL_PU_GND
H27
FB_CAL_TERM_GND
H25
C
1
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2
2
2
2
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0
8
0
5
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6
.
3
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6
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1
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2
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0
8
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6
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6
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6
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R1073 1K_0402_5% @ R1073 1K_0402_5% @ 1 2
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DIS@
Q33
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DIS@
2
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R1077 42.2_0402_1%
DIS@ 1 2
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1
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0
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D
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R1080 51.1_0402_1%
DIS@
R1080 51.1_0402_1%
DIS@ 1 2
R1082 1K_0402_5% @ R1082 1K_0402_5% @ 1 2
C
1
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6
1
0
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0
6
0
3
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6
.
3
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6
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1
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6
1
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0
6
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3
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6
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3
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6
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D
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@
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R1071 10K_0402_5% DIS@ R1071 10K_0402_5% DIS@ 1 2
C
1
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8
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6
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6
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1
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3
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0
4
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1
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4
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D
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1
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3
3
0
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1
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0
4
0
2
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1
6
V
4
Z
D
I
S
@
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2
R1083 10K_0402_5% DIS@ R1083 10K_0402_5% DIS@ 1 2
C
1
0
5
1
0
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1
U
_
0
4
0
2
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1
6
V
4
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D
I
S
@
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1
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1
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1
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_
0
4
0
2
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1
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4
0
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1
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0
4
0
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1
6
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4
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1
0
5
4
0
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1
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_
0
4
0
2
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1
6
V
4
Z
D
I
S
@
1
2
R1070 10_0402_5% DIS@ R1070 10_0402_5% DIS@
1 2
C
1
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5
1
0
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0
6
0
3
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6
.
3
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6
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D
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1
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0
6
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6
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1
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1
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4
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0
6
0
3
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6
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3
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6
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D
I
S
@
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R514
1K_0402_5%
DIS@ R514
1K_0402_5%
DIS@
1 2
C
1
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0
4
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2
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6
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6
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0
4
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C
1
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_
0
4
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6
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1
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4
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6
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6
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D
I
S
@
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C1050 0.1U_0402_16V4Z
DIS@
C1050 0.1U_0402_16V4Z
DIS@ 1 2
C
1
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R1130 10K_0402_5% DIS@ R1130 10K_0402_5% DIS@ 1 2
C
1
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DIS@
Q35B
DIS@
3
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5
C
1
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4
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1
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6
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L1002
BLM18PG121SN1D_0603
GL@
L1002
BLM18PG121SN1D_0603
GL@
1 2
R1069 1K_0402_5% @ R1069 1K_0402_5% @ 1 2
C
1
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4
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6
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3
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6
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2
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6
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6
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D
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@
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R1072 10_0402_5% DIS@ R1072 10_0402_5% DIS@
1 2
R511
470_0603_5%
DIS@
R511
470_0603_5%
DIS@
1
2
C
1
0
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5
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1
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_
0
4
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6
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6
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1
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8
0
5
_
6
.
3
V
6
M
D
I
S
@
1
2
C
1
0
1
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
D
I
S
@
C
1
0
1
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
D
I
S
@
1
2
R1074 10K_0402_5% DIS@ R1074 10K_0402_5% DIS@ 1 2
C
1
0
5
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
C
1
0
5
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
1
2
C
1
0
5
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
5
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VGA_CORE +VGA_CORE
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
50A
P
O
W
E
R
Part 7 of 7
U1001G
GF108@
P
O
W
E
R
Part 7 of 7
U1001G
GF108@
VDD_0
AA12
VDD_1
AA14
VDD_2
AA16
VDD_3
AA19
VDD_4
AA21
VDD_5
AA23
VDD_6
AB13
VDD_7
AB15
VDD_8
AB17
VDD_9
AB18
VDD_10
AB20
VDD_11
AB22
VDD_12
AC12
VDD_13
AC14
VDD_14
AC16
VDD_15
AC19
VDD_16
AC21
VDD_17
AC23
VDD_18
M12
VDD_19
M14
VDD_20
M16
VDD_21
M19
VDD_22
M21
VDD_23
M23
VDD_24
N13
VDD_25
N15
VDD_26
N17
VDD_27
N18
VDD_28
N20
VDD_29
N22
VDD_30
P12
VDD_31
P14
VDD_32
P16
VDD_33
P19
VDD_34
P21
VDD_35
P23
VDD_36
R13
VDD_37
R15
VDD_38
R17
VDD_39
R18
VDD_40
R20
VDD_41
R22
VDD_42
T12
VDD_43
T14
VDD_44
T16
VDD_45
T19
VDD_46
T21
VDD_47
T23
VDD_48
U13
VDD_49
U15
VDD_50
U17
VDD_51
U18
VDD_52
U20
VDD_53
U22
VDD_54
V13
VDD_55
V15
VDD_58
V20
VDD_59
V22
VDD_60
W12
VDD_61
W14
VDD_62
W16
VDD_63
W19
VDD_64
W21
VDD_65
W23
VDD_66
Y13
VDD_67
Y15
VDD_68
Y17
VDD_69
Y18
VDD_70
Y20
VDD_71
Y22
VDD_56
V17
VDD_57
V18
XVDD_1
U1
XVDD_2
U2
XVDD_3
U3
XVDD_4
U4
XVDD_5
U5
XVDD_6
U6
XVDD_7
U7
XVDD_8
U8
XVDD_9
V1
XVDD_10
V2
XVDD_11
V3
XVDD_12
V4
XVDD_13
V5
XVDD_14
V6
XVDD_15
V7
XVDD_16
V8
XVDD_17
W2
XVDD_18
W3
XVDD_19
W4
XVDD_20
W5
XVDD_21
W7
XVDD_22
W8
XVDD_23
Y1
XVDD_24
Y2
XVDD_25
Y3
XVDD_26
Y4
XVDD_27
Y5
XVDD_28
Y6
XVDD_29
Y7
XVDD_30
Y8
XVDD_31
AA1
XVDD_32
AA2
XVDD_33
AA3
XVDD_34
AA4
XVDD_35
AA5
XVDD_36
AA6
XVDD_37
AA7
XVDD_38
AA8
G
N
D
Part 6 of 7
U1001F
GF108@
G
N
D
Part 6 of 7
U1001F
GF108@
GND_0
A2
GND_1
AA17
GND_2
AA18
GND_3
AA20
GND_4
AA22
GND_5
AB12
GND_6
AB14
GND_7
AB16
GND_8
AB19
GND_9
AB2
GND_10
AB21
GND_11
A33
GND_12
AB23
GND_13
AB28
GND_14
AB30
GND_15
AB32
GND_16
AB5
GND_17
AB7
GND_18
AC13
GND_19
AC15
GND_20
AC17
GND_21
AC18
GND_22
AA13
GND_23
AC20
GND_24
AC22
GND_25
AE2
GND_26
AE28
GND_27
AE30
GND_28
AE32
GND_29
AE33
GND_30
AE5
GND_31
AE7
GND_32
AH10
GND_33
AA15
GND_34
AH13
GND_35
AH16
GND_36
AH19
GND_37
AH2
GND_38
AH22
GND_39
AH24
GND_40
AH28
GND_41
AH29
GND_42
AH30
GND_43
AH32
GND_44
AH33
GND_45
AH5
GND_46
AH7
GND_47
AJ 7
GND_48
AK10
GND_49
AK7
GND_50
AL12
GND_51
AL14
GND_52
AL15
GND_53
AL17
GND_54
AL18
GND_55
AL2
GND_56
AL20
GND_57
AL21
GND_58
AL23
GND_59
AL24
GND_60
AL26
GND_61
AL28
GND_62
AL30
GND_63
AL32
GND_64
AL33
GND_65
AL5
GND_66
AM13
GND_67
AM16
GND_68
AM19
GND_69
AM22
GND_70
AM25
GND_71
AN1
GND_72
AN10
GND_73
AN13
GND_74
AN16
GND_75
AN19
GND_76
AN22
GND_77
AN25
GND_78
AN30
GND_79
AN34
GND_80
AN4
GND_81
AN7
GND_82
AP2
GND_83
AP33
GND_84
B1
GND_85
B10
GND_86
B22
GND_87
B25
GND_88
B28
GND_89
B31
GND_90
B34
GND_91
B4
GND_92
B7
GND_93
C10
GND_94
C13
GND_95
C19
GND_96
C22
GND_97
C25
GND_98
C28
GND_99
C7
GND_100
D2
GND_101
D31
GND_102
D33
GND_103
E10
GND_104
E22
GND_105
E25
GND_106
E5
GND_107
E7
GND_108
F28
GND_109
F7
GND_110
G10
GND_111
G13
GND_112
G16
GND_113
G19
GND_114
G2
GND_115
G22
GND_116
G25
GND_117
G28
GND_118
G3
GND_119
G30
GND_120
G32
GND_121
G33
GND_122
G5
GND_123
G7
GND_124
K2
GND_125
K28
GND_126
K30
GND_127
K32
GND_128
K33
GND_129
K5
GND_130
K7
GND_131
M13
GND_132
M15
GND_133
M17
GND_134
M18
GND_135
M20
GND_136
M22
GND_137
N12
GND_138
N14
GND_139
N16
GND_140
N19
GND_141
N2
GND_142
N21
GND_143
N23
GND_144
N28
GND_145
N30
GND_146
N32
GND_147
N33
GND_148
N5
GND_149
N7
GND_150
P13
GND_151
P15
GND_152
P17
GND_153
P18
GND_154
P20
GND_155
P22
GND_156
R12
GND_157
R14
GND_158
R16
GND_159
R19
GND_160
R21
GND_161
R23
GND_162
T13
GND_163
T15
GND_164
T17
GND_165
T18
GND_166
T2
GND_167
T20
GND_168
T22
GND_169
AG11
GND_170
T28
GND_171
T32
GND_172
T5
GND_173
T7
GND_174
U12
GND_175
U14
GND_176
U16
GND_177
U19
GND_178
U21
GND_179
U23
GND_180
V12
GND_181
V14
GND_182
V16
GND_183
V19
GND_184
V21
GND_185
V23
GND_186
W13
GND_187
W15
GND_188
W17
GND_189
W18
GND_190
W20
GND_191
W22
GND_192
W28
GND_193
Y12
GND_194
Y14
GND_195
Y16
GND_196
Y19
GND_197
Y21
GND_198
Y23
GND_199
AH11
GND_OPT
C16
GND_OPT
W32

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MDA[63..0]
DQMA[7..0]
DQSA[7..0]
DQSA#[7..0]
CMDA[30..0]
CLKA0#
CLKA0
CMDA2
CMDA3
CMDA5
CMDA18
CMDA19
CLKA0
CLKA0#
+MEM_VREF1
DQMA0
DQSA0
DQSA#0
DQSA3
DQMA3
DQSA#3
+MEM_VREF0
+MEM_VREF1
CMDA5
CMDA3
CMDA5
CMDA11
CMDA8
CMDA7
CMDA29
CMDA14
CMDA28
CMDA9
CMDA25
CMDA24
CMDA21
CMDA4
CMDA20
CMDA10
CMDA22
CMDA6
CMDA23
CMDA12
CMDA27
CMDA26
CMDA3
CMDA2
CMDA13
CMDA15
CMDA30
CMDA0
+MEM_VREF0
ZQ1 ZQ0
CMDA11
CMDA8
CMDA7
CMDA29
CMDA14
CMDA28
CMDA25
CMDA9
CMDA24
CMDA21
CMDA4
CMDA20
CMDA10
CMDA22
CMDA6
CMDA23
CMDA12
CMDA27
CMDA26
CMDA13
CMDA15
CMDA30
CMDA0
CMDA2
CLKA0
CLKA0#
MDA0
MDA3
MDA4
MDA2
MDA5
MDA1
MDA7
MDA6
DQSA1
DQSA2
DQMA1
DQMA2
DQSA#1
DQSA#2
MDA17
MDA23
MDA16
MDA21
MDA19
MDA22
MDA20
MDA18
MDA24
MDA26
MDA27
MDA28
MDA31
MDA29
MDA25
MDA30
MDA9
MDA10
MDA15
MDA13
MDA12
MDA8
MDA14
MDA11
DQSA[7..0] <23,28>
DQSA#[7..0] <23,28>
DQMA[7..0] <23,28>
MDA[63..0] <23,28>
CMDA[30..0] <23,28>
CLKA0# <23>
CLKA0 <23>
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
Title
Date: Sheet of
4019ID
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
C
Title
Date: Sheet of
4019ID
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
C
Title
Date: Sheet of
4019ID
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
C
VRAM DDR3 chips (1GB)
310mA
310mA
64Mx16 DDR3 *8==>1GB
A7
A14
RST
A14
A13
A15
LOW HIGH
CMD22
CMD23
CMD30
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD15
Mode D
Address 32..63
CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21 A8
A11
CAS*
A3
A1
WE*
BA0
A4
BA2
A5
RAS*
A12
A5
BA1
ODT_H
A11
A10
CAS*
WE*
A9
BA0
A6
A12
ODT_L
CKE_H
A7
RAS*
A13
BA2
BA1
A2
A0
A4
A9
A3
A1
CS0_H#
A2
A0
A15
CS0_L#
A10
A8
A6
RST
DDR3
Command Bit Default Pull-down
ODTx 10k
CKEx 10k
RST 10k
CS* No Termination
0..31
Not Available
Hynix : SA000041S40 (S IC D3 64MX16 H5TQ1G63DFR-11C FBGA )
CKE
NV recommand 0720
Group1
Group3
Group0
Group2
128Mx16 DDR3 *8==>2GB
R02 modify
Swap MDA13 and MDA14
R04 modify for EMI
Hynix : SA00003YO20 (S IC D3 128M16 H5TQ2G63BFR-11C FBGA)
R1094 10K_0402_5%
DIS@
R1094 10K_0402_5%
DIS@
1 2
C
1
0
7
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
7
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
1
2
C
1
0
7
2
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
C
1
0
7
2
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
1
2
C
1
0
8
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
8
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
1
2
R1095 10K_0402_5%
DIS@
R1095 10K_0402_5%
DIS@
1 2
R1084
240_0402_1%
DIS@
R1084
240_0402_1%
DIS@
R1089
243_0402_1%
DIS@
R1089
243_0402_1%
DIS@
1
2
C
1
0
6
9
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
6
9
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@ 1
2
R1091 10K_0402_5% DIS@ R1091 10K_0402_5% DIS@ 1 2
C
2
0
8
9
0
.
0
1
U
_
0
4
0
2
_
1
6
V
7
K
DIS@ C
2
0
8
9
0
.
0
1
U
_
0
4
0
2
_
1
6
V
7
K
DIS@
1
2
R1092
160_0402_1%
DIS@
R1092
160_0402_1%
DIS@
1
2
C
1
0
8
9
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
8
9
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
1
2
C
1
0
7
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
C
1
0
7
5
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
1
2
R1088
80.6_0402_1%
@
R1088
80.6_0402_1%
@
1 2
C
1
0
7
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
C
1
0
7
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
1
2
R1093 10K_0402_5% DIS@ R1093 10K_0402_5% DIS@ 1 2
R1085
240_0402_1%
DIS@
R1085
240_0402_1%
DIS@
R1086
240_0402_1%
DIS@
R1086
240_0402_1%
DIS@
C
1
0
7
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
7
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
1
2
96-BALL
SDRAM DDR3
U1002
K4B1G1646E-HC12_FBGA96
X76@
96-BALL
SDRAM DDR3
U1002
X76@
WE
L3
RAS
J 3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J 7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J 1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J 9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J 2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
C
1
0
8
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
8
7
0
.
1
U
_
0
4
0
2
_
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R1087
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243_0402_1%
DIS@
R1090
243_0402_1%
DIS@
1
2
C
1
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8
3
1
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4
0
2
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1
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7
8
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1
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2
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4
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1
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7
8
0
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1
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_
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4
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6
V
4
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9
0
0
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1
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_
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2
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1
6
V
4
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1
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9
0
0
.
1
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_
0
4
0
2
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1
6
V
4
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@
1
2
96-BALL
SDRAM DDR3
U1003
X76@
96-BALL
SDRAM DDR3
U1003
X76@
WE
L3
RAS
J 3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J 7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J 1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J 9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J 2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DQSA#[7..0]
MDA[63..0]
CMDA[30..0]
DQMA[7..0]
DQSA[7..0]
ZQ2
CLKA1#
CLKA1
+MEM_VREF2 +MEM_VREF3
CLKA1#
CLKA1
ZQ3
CMDA19
CMDA5
CMDA24
CMDA10
CMDA11
CMDA14
CMDA6
CMDA26
CMDA25
CMDA29
CMDA27
CMDA22
CMDA12
CMDA8
CMDA9
CMDA20
CMDA4
CMDA7
CMDA28
CMDA21
CMDA23
CMDA19
CMDA30
CMDA18
CMDA15
CMDA13
CMDA5
CMDA16
+MEM_VREF2
+MEM_VREF3
CMDA24
CMDA10
CMDA11
CMDA14
CMDA6
CMDA25
CMDA29
CMDA22
CMDA8
CMDA9
CMDA20
CMDA4
CMDA7
CMDA28
CMDA21
CMDA23
CMDA26
CMDA27
CMDA12
CMDA30
CMDA18
CMDA15
CMDA13
CMDA16
CLKA1
CLKA1#
DQSA4
DQSA#4
DQMA6
DQSA6
DQSA#6
DQMA4
MDA32
MDA39
MDA38
MDA36
MDA34
MDA37
MDA33
MDA35
MDA49
MDA48
MDA50
MDA55
MDA51
MDA52
MDA53
MDA54
DQMA5
DQSA#5
DQSA5
DQSA7
DQMA7
DQSA#7
MDA58
MDA60
MDA61
MDA62
MDA63
MDA59
MDA56
MDA57
MDA42
MDA46
MDA47
MDA44
MDA40
MDA43
MDA41
MDA45
DQSA#[7..0] <23,27>
DQSA[7..0] <23,27>
MDA[63..0] <23,27>
DQMA[7..0] <23,27>
CMDA[30..0] <23,27>
CLKA1 <23>
CLKA1# <23>
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
310mA 310mA
64Mx16 DDR3 *8==>1GB
Not Available
A7
A14
RST
A14
A13
A15
LOW HIGH
CMD22
CMD23
CMD30
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD15
Mode D
Address 32..63
CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
0..31
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21 A8
A11
CAS*
A3
A1
WE*
BA0
A4
BA2
A5
RAS*
A12
A5
BA1
ODT_H
A11
A10
CAS*
WE*
A9
BA0
A6
A12
ODT_L
CKE_H
A7
RAS*
A13
BA2
BA1
A2
A0
A4
A9
A3
A1
CS0_H#
A2
A0
A15
CS0_L#
A10
A8
A6
RST
CKE
NV recommand 0720
Group4
Group6 Group7
Group5
128Mx16 DDR3 *8==>2GB
C
1
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R1099
240_0402_1%
DIS@
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R1101
240_0402_1%
DIS@
R1101
240_0402_1%
DIS@
R1106
80.6_0402_1%
@
R1106
80.6_0402_1%
@
1 2
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1
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1
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R1102
243_0402_1%
DIS@
R1102
243_0402_1%
DIS@
1
2
R1104
80.6_0402_1%
@
R1104
80.6_0402_1%
@
1 2
C
1
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1
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DIS@
R1103
243_0402_1%
DIS@
1
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C
1
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@
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2
96-BALL
SDRAM DDR3
U1005
X76@
96-BALL
SDRAM DDR3
U1005
X76@
WE
L3
RAS
J 3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J 7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J 1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J 9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J 2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J 8
VSS
M1
VSS
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VSS
P1
VSS
P9
VSS
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VSS
T9
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C1093
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C1093
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@
1
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R1098
240_0402_1%
DIS@
R1098
240_0402_1%
DIS@
C
1
0
9
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
C
1
0
9
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
1
2
R1100
240_0402_1%
DIS@
R1100
240_0402_1%
DIS@
C
1
1
0
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
C
1
1
0
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
D
I
S
@
1
2
96-BALL
SDRAM DDR3
U1004
X76@
96-BALL
SDRAM DDR3
U1004
X76@
WE
L3
RAS
J 3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J 7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J 1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J 9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J 2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
C
1
1
1
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
1
1
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
1
2
C
1
0
9
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
9
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@ 1
2
R1105
160_0402_1%
DIS@
R1105
160_0402_1%
DIS@
1
2
C
1
0
9
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
C
1
0
9
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
D
I
S
@
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLKC0#
CLKC0
CMDC[30..0]
MDC[63..0]
DQMC[7..0]
DQSC[7..0]
DQSC#[7..0]
+MEM_VREF4
+MEM_VREF5
DQSC#3
DQSC3
DQMC3
CLKC0
CLKC0#
+MEM_VREF5
DQMC0
DQSC0
DQSC#0
CMDC3
CMDC5
CMDC22
CMDC28
CMDC7
CMDC24
CMDC20
CMDC4
CMDC21
CMDC23
CMDC11
CMDC25
CMDC6
CMDC8
CMDC29
CMDC9
CMDC10
CMDC14
CMDC27
CMDC12
CMDC26
CMDC3
CMDC13
CMDC15
CMDC30
CMDC2
CMDC0
CMDC5
ZQ4 ZQ5
CMDC2
CMDC3
CMDC5
CMDC18
CMDC19
+MEM_VREF4
CLKC0
CLKC0#
CMDC22
CMDC28
CMDC7
CMDC24
CMDC20
CMDC4
CMDC21
CMDC23
CMDC11
CMDC25
CMDC6
CMDC8
CMDC29
CMDC9
CMDC10
CMDC14
CMDC27
CMDC12
CMDC26
CMDC13
CMDC15
CMDC30
CMDC2
CMDC0
MDC7
MDC6
MDC3
MDC2
MDC0
MDC4
MDC5
MDC1
MDC30
MDC25
MDC24
MDC28
MDC26
MDC27
DQSC#2
DQSC#1
DQSC2
DQSC1
DQMC2
DQMC1
MDC21
MDC23
MDC18
MDC20
MDC19
MDC16
MDC22
MDC17
MDC31
MDC29
MDC11
MDC14
MDC15
MDC10
MDC13
MDC12
MDC8
MDC9
DQSC[7..0] <23,30>
DQSC#[7..0] <23,30>
DQMC[7..0] <23,30>
MDC[63..0] <23,30>
CMDC[30..0] <23,30>
CLKC0# <23>
CLKC0 <23>
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
Title
Date: Sheet of
4019ID
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
C
Title
Date: Sheet of
4019ID
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
C
Title
Date: Sheet of
4019ID
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
C
310mA
310mA
64Mx16 DDR3 *8==>1GB
10k
DDR3 CKEx
Command Bit Default Pull-down
10k
RST
ODTx
10k
CS* No Termination
Not Available
A7
A14
RST
A14
A13
A15
LOW HIGH
CMD22
CMD23
CMD30
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD15
Mode D
Address 32..63
CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
0..31
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21 A8
A11
CAS*
A3
A1
WE*
BA0
A4
BA2
A5
RAS*
A12
A5
BA1
ODT_H
A11
A10
CAS*
WE*
A9
BA0
A6
A12
ODT_L
CKE_H
A7
RAS*
A13
BA2
BA1
A2
A0
A4
A9
A3
A1
CS0_H#
A2
A0
A15
CS0_L#
A10
A8
A6
RST
CKE
NV recommand 0720
Group0
Group3
Group1
Group2
128Mx16 DDR3 *8==>2GB
R1107
240_0402_1%
GSGL@
R1107
240_0402_1%
GSGL@
R1112
243_0402_1%
GSGL@
R1112
243_0402_1%
GSGL@
1
2
C
1
1
2
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
2
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
2
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
2
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
3
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
3
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
R1118
80.6_0402_1%
@R1118
80.6_0402_1%
@
1 2
C
1
1
2
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
2
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
R1113 10K_0402_5% GSGL@ R1113 10K_0402_5% GSGL@ 1 2
C1115
0.01U_0402_16V7K
@
C1115
0.01U_0402_16V7K
@
1
2
R1119
160_0402_1%
GSGL@
R1119
160_0402_1%
GSGL@
1
2
C
1
1
2
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
2
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
96-BALL
SDRAM DDR3
U1007
X76@
96-BALL
SDRAM DDR3
U1007
X76@
WE
L3
RAS
J 3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J 7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J 1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J 9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J 2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
C
1
1
1
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
1
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
2
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
2
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
R1111
243_0402_1%
GSGL@
R1111
243_0402_1%
GSGL@
1
2
R1115 10K_0402_5%
GSGL@
R1115 10K_0402_5%
GSGL@
1 2
C
1
1
3
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
3
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
R1116 10K_0402_5%
GSGL@
R1116 10K_0402_5%
GSGL@
1 2
C
1
1
1
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
1
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@ 1
2
C
1
1
1
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
1
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
1
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
1
6
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
2
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
2
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
R1109
240_0402_1%
GSGL@
R1109
240_0402_1%
GSGL@
R1108
240_0402_1%
GSGL@
R1108
240_0402_1%
GSGL@
C
1
1
2
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
2
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
2
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
2
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
R1117 10K_0402_5% GSGL@ R1117 10K_0402_5% GSGL@ 1 2
R1120
80.6_0402_1%
@R1120
80.6_0402_1%
@
1 2
96-BALL
SDRAM DDR3
U1006
X76@
96-BALL
SDRAM DDR3
U1006
X76@
WE
L3
RAS
J 3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J 7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J 1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J 9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J 2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
C
1
1
3
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
3
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
3
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
3
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
R1114 10K_0402_5% GSGL@ R1114 10K_0402_5% GSGL@ 1 2
C
1
1
3
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
3
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
1
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
1
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
2
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
2
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
2
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
2
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
1
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
1
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@ 1
2
R1110
240_0402_1%
GSGL@
R1110
240_0402_1%
GSGL@

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DQSC[7..0]
DQSC#[7..0]
MDC[63..0]
CMDC[30..0]
DQMC[7..0]
ZQ6
CLKC1#
CLKC1
+MEM_VREF6
+MEM_VREF7
+MEM_VREF6
+MEM_VREF7
CLKC1#
CLKC1
CMDC19
CMDC5 CMDC5
CMDC27
CMDC29
CMDC22
CMDC6
CMDC4
CMDC23
CMDC24
CMDC7
CMDC11
CMDC26
CMDC14
CMDC20
CMDC25
CMDC12
CMDC10
CMDC28
CMDC9
CMDC21
CMDC8
CMDC30
CMDC18
CMDC19
CMDC15
CMDC16
CMDC13
ZQ7
CLKC1
CLKC1#
CMDC27
CMDC29
CMDC22
CMDC6
CMDC4
CMDC23
CMDC24
CMDC7
CMDC11
CMDC26
CMDC14
CMDC20
CMDC25
CMDC12
CMDC10
CMDC28
CMDC9
CMDC21
CMDC8
CMDC30
CMDC18
CMDC15
CMDC16
CMDC13
DQSC4
DQSC5
DQMC4
DQMC5
DQSC#4
DQSC#5
DQSC7
DQMC7
DQSC#7
DQSC6
DQMC6
DQSC#6
MDC34
MDC33
MDC35
MDC38
MDC32
MDC36
MDC37
MDC39
MDC45
MDC44
MDC46
MDC47
MDC43
MDC41
MDC42
MDC40
MDC54
MDC50
MDC52
MDC49
MDC55
MDC51
MDC53
MDC48
MDC58
MDC62
MDC57
MDC56
MDC60
MDC59
MDC61
MDC63
DQSC#[7..0] <23,29>
DQSC[7..0] <23,29>
MDC[63..0] <23,29>
DQMC[7..0] <23,29>
CMDC[30..0] <23,29>
CLKC1 <23>
CLKC1# <23>
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
+1.5VSDGPU
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
310mA 310mA
64Mx16 DDR3 *8==>1GB
Not Available
A7
A14
RST
A14
A13
A15
LOW HIGH
CMD22
CMD23
CMD30
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD15
Mode D
Address 32..63
CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
0..31
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21 A8
A11
CAS*
A3
A1
WE*
BA0
A4
BA2
A5
RAS*
A12
A5
BA1
ODT_H
A11
A10
CAS*
WE*
A9
BA0
A6
A12
ODT_L
CKE_H
A7
RAS*
A13
BA2
BA1
A2
A0
A4
A9
A3
A1
CS0_H#
A2
A0
A15
CS0_L#
A10
A8
A6
RST
CKE
NV recommand 0720
Group4
Group5
Group7
Group6
128Mx16 DDR3 *8==>2GB
R02 modify
Swap MDC37 and MDC38
96-BALL
SDRAM DDR3
U1008
X76@
96-BALL
SDRAM DDR3
U1008
X76@
WE
L3
RAS
J 3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J 7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J 1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J 9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J 2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
R1129
80.6_0402_1%
@R1129
80.6_0402_1%
@
1 2
C
1
1
4
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
4
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
5
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
5
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
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1
2
C
1
1
4
2
0
.
1
U
_
0
4
0
2
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1
6
V
4
Z
G
S
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L
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1
1
4
2
0
.
1
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_
0
4
0
2
_
1
6
V
4
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G
S
G
L
@
1
2
C
1
1
4
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
4
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
3
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
3
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
4
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
4
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
4
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
4
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
5
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
5
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
5
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
5
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
R1122
240_0402_1%
GSGL@
R1122
240_0402_1%
GSGL@
C
1
1
5
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
5
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
R1128
160_0402_1%
GSGL@
R1128
160_0402_1%
GSGL@
1
2
C
1
1
5
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
5
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
4
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
4
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
R1125
243_0402_1%
GSGL@
R1125
243_0402_1%
GSGL@
1
2
C
1
1
3
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
3
5
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@ 1
2
C
1
1
3
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
3
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
4
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
4
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
3
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
3
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@ 1
2
C
1
1
5
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
5
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
4
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
4
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C
1
1
4
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
C
1
1
4
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
G
S
G
L
@
1
2
C
1
1
5
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
5
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
C1137
0.01U_0402_16V7K
@
C1137
0.01U_0402_16V7K
@
1
2
C
1
1
4
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
C
1
1
4
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
G
S
G
L
@
1
2
R1127
80.6_0402_1%
@R1127
80.6_0402_1%
@
1 2
96-BALL
SDRAM DDR3
U1009
X76@
96-BALL
SDRAM DDR3
U1009
X76@
WE
L3
RAS
J 3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J 7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J 1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J 9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J 2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J 8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
R1123
240_0402_1%
GSGL@
R1123
240_0402_1%
GSGL@
R1121
240_0402_1%
GSGL@
R1121
240_0402_1%
GSGL@
R1124
240_0402_1%
GSGL@
R1124
240_0402_1%
GSGL@
R1126
243_0402_1%
GSGL@
R1126
243_0402_1%
GSGL@
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LCDVDD_ON
INVTPWM
INVTPWM
BKOFF#
EDP_HPD
EDP_HPD
INVTPWM
PCH_LCD_CLK
PCH_LCD_DATA
TZOUT0-
TZOUT0+
USB20_N10
TZOUT1-
TZOUT1+
BKOFF#
PCH_TXOUT1-
PCH_TXCLK-
PCH_TXOUT0+
PCH_TXCLK+
PCH_TXOUT0-
PCH_TXOUT1+
PCH_TXOUT2-
PCH_TXOUT2+
TZCLK-
TZCLK+
USB20_P10
TZOUT1-
TZOUT1+
TZCLK-
TZCLK+
TZOUT0-
TZOUT0+
USB20_P10
USB20_N10
PCH_GPIO71
EDP_HPD
PCH_ENVDD <16>
DPST_PWM <16>
BKOFF# <40>
EDP_HPD# <4>
USB20_N10 <17>
PCH_LCD_CLK <16>
USB20_P10 <17>
PCH_LCD_DATA <16>
PCH_TXOUT0- <16>
PCH_TXOUT0+ <16>
PCH_TXOUT1- <16>
PCH_TXOUT1+ <16>
PCH_TXOUT2- <16>
PCH_TXOUT2+ <16>
PCH_TXCLK- <16>
PCH_TXCLK+ <16>
EDP_TXP1 <4>
EDP_AUXN <4>
EDP_AUXP <4>
EDP_TXP0 <4>
EDP_TXN0 <4>
EDP_TXN1 <4>
PCH_GPIO71 <18>
+3VS
+LCDVDD
+LCDVDD
+3VALW
+INVPWR_B+ B+
+LCDVDD
+3VS
+3VS
+3VS
+3VS
+INVPWR_B+
+LCDVDD
+3VS
+3VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
LCD POWER CIRCUIT
LCD/LED PANEL Conn.
W=60mils
W=60mils
W=60mils
Place closed to J LVDS1
SM010014520 3000ma
220ohm@100mhz
DCR 0.04
eDP
RF request
W=60mils
W=60mils
For Camera
R02 Modify
R02 modify
Modify R02
GPIO71
0
1
eDP
LVDS
PCH_GPIO71
addon7912_0.3
C915 .1U_0402_16V7K EDP@ C915 .1U_0402_16V7K EDP@ 1 2
C6
68P_0402_50V8J
C6
68P_0402_50V8J
1
2
C914 .1U_0402_16V7K EDP@ C914 .1U_0402_16V7K EDP@ 1 2
U13
74AHC1G125GW_SOT353-5
@
U13
74AHC1G125GW_SOT353-5
@
OE#
1
IN
2
GND
3
OUT
4
VCC
5
R480
100K_0402_5%
EDP@
R480
100K_0402_5%
EDP@
1
2
C562
4.7U_0603_6.3V6K
C562
4.7U_0603_6.3V6K
1
2
C480
22P_0402_50V8J
@
C480
22P_0402_50V8J
@
1
2
R550
10K_0402_5%
R550
10K_0402_5%
1
2
C9
680P_0402_50V7K
C9
680P_0402_50V7K
1
2
R2130
0_0402_5%
@ R2130
0_0402_5%
@
1 2
C481
22P_0402_50V8J
@
C481
22P_0402_50V8J
@
1
2
C910 .1U_0402_16V7K EDP@ C910 .1U_0402_16V7K EDP@ 1 2
Q28
AP2301GN-HF_SOT23-3
Q28
AP2301GN-HF_SOT23-3 2
3
1
G
D
S
Q22
SSM3K7002F_SC59-3
EDP@
G
D
S
Q22
SSM3K7002F_SC59-3
EDP@
2
1
3
L1
FBMA-L11-201209-221LMA30T_0805
L1
FBMA-L11-201209-221LMA30T_0805
1 2
C484
0.1U_0402_16V4Z
C484
0.1U_0402_16V4Z
1
2
C911 .1U_0402_16V7K EDP@ C911 .1U_0402_16V7K EDP@ 1 2
C10
0.1U_0402_16V4Z
C10
0.1U_0402_16V4Z
1
2
R2
10K_0402_5%
R2
10K_0402_5%
1 2
R18 10K_0402_5% R18 10K_0402_5% 1 2
G
D
S
Q1
SSM3K7002F_SC59-3 G
D
S
Q1
SSM3K7002F_SC59-3
2
1
3
R6
10K_0402_5%
R6
10K_0402_5%
1
2
G
D
S
Q2
SSM3K7002F_SC59-3 G
D
S
Q2
SSM3K7002F_SC59-3
2
1
3
C8 220P_0402_50V7K C8 220P_0402_50V7K 1 2
C2040
47P_0402_50V8J
@
C2040
47P_0402_50V8J
@
1
2
L2
FBMA-L11-201209-221LMA30T_0805
L2
FBMA-L11-201209-221LMA30T_0805
1 2
C11
0.1U_0402_16V4Z
C11
0.1U_0402_16V4Z
1
2
R85 0_0402_5% R85 0_0402_5%
1 2
R4
100K_0402_5%
R4
100K_0402_5%
1
2
R86
10K_0402_5%
R86
10K_0402_5%
1
2
C5 220P_0402_50V7K C5 220P_0402_50V7K 1 2
C913 .1U_0402_16V7K EDP@ C913 .1U_0402_16V7K EDP@ 1 2
R5
200_0603_1%
R5
200_0603_1%
1
2
J LVDS1
I-PEX_20143-040E-20F
J LVDS1
I-PEX_20143-040E-20F
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
G1
41
G2
42
G3
43
G4
44
G5
45
G6
46
C485
10U_0603_6.3V6M
C485
10U_0603_6.3V6M
1
2
D15
AZC099-04S.R7G_SOT23-6
@ D15
@
I/O4
6
VDD
5
I/O3
4
I/O2
3
GND
2
I/O1
1
G
D
S
Q29
SSM3K7002F_SC59-3
EDP@
G
D
S
Q29
SSM3K7002F_SC59-3
EDP@
2
1
3
C912 .1U_0402_16V7K EDP@ C912 .1U_0402_16V7K EDP@ 1 2
C2
1U_0402_6.3V6K
C2
1U_0402_6.3V6K
1
2
R783
100K_0402_5%
@
R783
100K_0402_5%
@
1 2
C479
4.7U_0603_6.3V6K
C479
4.7U_0603_6.3V6K
1
2

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CRT_HSYNC_2
CRT_VSYNC_2
CRT_R_2
DSUB_12
DSUB_15
CRT_G_2
CRT_B_2
CRT_G_1
CRT_R_1
CRT_B_1
CRT_HSYNC_1
CRT_VSYNC_1
PCH_CRT_R
PCH_CRT_G
PCH_CRT_B
DSUB_12
DSUB_15 PCH_CRT_CLK
PCH_CRT_DATA
CRT_VSYNC
CRT_HSYNC
J CRT1.11
J CRT1.5
PCH_CRT_HSYNC
PCH_CRT_VSYNC
PCH_CRT_DATA <16>
PCH_CRT_CLK <16>
PCH_CRT_HSYNC <16>
PCH_CRT_VSYNC <16>
PCH_CRT_R <16>
PCH_CRT_G <16>
PCH_CRT_B <16>
+CRT_VCC +5VS
+CRT_VCC
+CRT_VCC
+3VS
+CRT_VCC
+R_CRT_VCC
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
W=40mils
CRT Connector
W=40mils
SM010012010 300ma 120ohm@100mhz DCR 0.4
CRB1.0 use 47ohm@100Mhz Bead
R04 modify
C
6
1
3
1
0
P
_
0
4
0
2
_
5
0
V
8
J
C
6
1
3
1
0
P
_
0
4
0
2
_
5
0
V
8
J
1
2
D18
L30ESDL5V0C3-2
@
D18
L30ESDL5V0C3-2
@
2 3
1
C589
100P_0402_50V8J
C589
100P_0402_50V8J
1
2
R510
150_0402_1%
R510
150_0402_1%
1
2
D5
CH491DPT_SOT23-3
D5
CH491DPT_SOT23-3
2 1
G
G
J CRT1
C-H_13-12201513CP
CONN@
G
G
J CRT1
C-H_13-12201513CP
CONN@
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
C
5
9
6
1
0
P
_
0
4
0
2
_
5
0
V
8
J
C
5
9
6
1
0
P
_
0
4
0
2
_
5
0
V
8
J
1
2
C
6
3
7
1
0
P
_
0
4
0
2
_
5
0
V
8
J
C
6
3
7
1
0
P
_
0
4
0
2
_
5
0
V
8
J
1
2
Q11A
Q11A
6 1
2
C
6
3
6
1
0
P
_
0
4
0
2
_
5
0
V
8
J
C
6
3
6
1
0
P
_
0
4
0
2
_
5
0
V
8
J
1
2
C586
68P_0402_50V8J
C586
68P_0402_50V8J
1
2
C
6
2
1
2
2
P
_
0
4
0
2
_
5
0
V
8
J
C
6
2
1
2
2
P
_
0
4
0
2
_
5
0
V
8
J
1
2
C
5
9
7
1
0
P
_
0
4
0
2
_
5
0
V
8
J
C
5
9
7
1
0
P
_
0
4
0
2
_
5
0
V
8
J
1
2
C228 0.1U_0402_16V4Z C228 0.1U_0402_16V4Z 1 2
U9
74AHCT1G125GW_SOT353-5
U9
A
2
Y
4
O
E
#
1
G
3
P
5
T71
PAD
@T71
PAD
@
C215
0.1U_0402_16V4Z
C215
0.1U_0402_16V4Z
1
2
C623
68P_0402_50V8J
C623
68P_0402_50V8J
1
2
C
6
1
4
1
0
P
_
0
4
0
2
_
5
0
V
8
J
C
6
1
4
1
0
P
_
0
4
0
2
_
5
0
V
8
J
1
2
L32
BLM18BA470SN1D_2P
L32
BLM18BA470SN1D_2P
1 2
R524
150_0402_1%
R524
150_0402_1%
1
2
L13 MBC1608121YZF_0603 L13 MBC1608121YZF_0603
1 2
R426
0_0402_5%
R426
0_0402_5%
1 2
Q11B
Q11B
3 4
5
F1
1.1A_6V_SMD1812P110TF
F1
1.1A_6V_SMD1812P110TF
2 1
C
6
0
1
2
2
P
_
0
4
0
2
_
5
0
V
8
J
C
6
0
1
2
2
P
_
0
4
0
2
_
5
0
V
8
J
1
2
C243 0.1U_0402_16V4Z C243 0.1U_0402_16V4Z 1 2
L28
BLM18BA470SN1D_2P
L28
BLM18BA470SN1D_2P
1 2
C
5
8
8
2
2
P
_
0
4
0
2
_
5
0
V
8
J
C
5
8
8
2
2
P
_
0
4
0
2
_
5
0
V
8
J
1
2
C220
10P_0402_50V8J
C220
10P_0402_50V8J
1
2
R142
4.7K_0402_5%
R142
4.7K_0402_5%
1
2
T72
PAD
@T72
PAD
@
R428
0_0402_5%
R428
0_0402_5%
1 2
L30
BLM18BA470SN1D_2P
L30
BLM18BA470SN1D_2P
1 2
U10
U10
A
2
Y
4
O
E
#
1
G
3
P
5
L10 MBC1608121YZF_0603 L10 MBC1608121YZF_0603
1 2
L33
BLM18BA470SN1D_2P
L33
BLM18BA470SN1D_2P
1 2
R520
150_0402_1%
R520
150_0402_1%
1
2
R146
4.7K_0402_5%
R146
4.7K_0402_5%
1
2
R147 10K_0402_5% R147 10K_0402_5% 1 2
L27
BLM18BA470SN1D_2P
L27
BLM18BA470SN1D_2P
1 2
L29
BLM18BA470SN1D_2P
L29
BLM18BA470SN1D_2P
1 2
D17
L30ESDL5V0C3-2
@
D17
L30ESDL5V0C3-2
@
2 3
1
C230
10P_0402_50V8J
C230
10P_0402_50V8J
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D0+
HDMI_R_D0-
HDMI_R_D1+
HDMI_R_D1-
HDMI_R_D2-
HDMI_R_D2+
HDMI_HPD
HDMI_SCLK
HDMI_SDATA
HDMI_GND
HDMI_TX0-
HDMI_TX0+
HDMI_CLK-
HDMI_CLK+
HDMI_TX1-
HDMI_TX1+
HDMI_TX2+
HDMI_TX2-
HDMI_TX0-
HDMI_TX0+
HDMI_CLK-
HDMI_CLK+
HDMI_TX1-
HDMI_TX1+
HDMI_TX2+
HDMI_TX2-
+HDMI_5V
HDMI_SDATA
HDMI_SCLK
HDMI_HPD
HDMI_CLK+
HDMI_CLK-
HDMI_R_CK+
HDMI_R_CK-
HDMI_TX0+
HDMI_TX0- HDMI_R_D0-
HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D1+
HDMI_TX1-
HDMI_TX1+
HDMI_R_D2-
HDMI_R_D2+ HDMI_TX2+
HDMI_TX2-
SDVO_SDATA
SDVO_SCLK
SDVO_SCLK
SDVO_SDATA
PCH_DPB_N3 <16>
PCH_DPB_P3 <16>
PCH_DPB_N2 <16>
PCH_DPB_P2 <16>
PCH_DPB_N1 <16>
PCH_DPB_P1 <16>
PCH_DPB_N0 <16>
PCH_DPB_P0 <16>
PCH_DPB_HPD <16>
SDVO_SCLK <16>
SDVO_SDATA <16>
+HDMI_5V_OUT
+3VS
+3VS
+HDMI_5V_OUT
+5VS
+HDMI_5V_OUT
+3VS
+3VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
SM070001310 400ma 90ohm@100mhz DCR 0.3
HDMI connector
W=40mils
RF request
Place closed to JHDMI1
R
2
5
6
2
.
2
K
_
0
4
0
2
_
5
%
R
2
5
6
2
.
2
K
_
0
4
0
2
_
5
%
1
2
C345
0.1U_0402_16V4Z
C345
0.1U_0402_16V4Z
1
2
R564 680_0402_5% R564 680_0402_5% 1 2
R587 680_0402_5% R587 680_0402_5% 1 2
R574 0_0402_5% R574 0_0402_5% 1 2
R589 680_0402_5% R589 680_0402_5% 1 2
R565 0_0402_5% R565 0_0402_5% 1 2
R579 0_0402_5% R579 0_0402_5% 1 2
R
2
5
5
2
.
2
K
_
0
4
0
2
_
5
%
R
2
5
5
2
.
2
K
_
0
4
0
2
_
5
%
1
2
C285 .1U_0402_16V7K C285 .1U_0402_16V7K 1 2
L39
WCM-2012-900T_0805
@
L39
WCM-2012-900T_0805
@
1
1
2
2
3
3
4
4
R242
0_0603_5%
@R242
0_0603_5%
@
1 2
G
D S
Q16 SSM3K7002F_SC59-3
G
D S
Q16 SSM3K7002F_SC59-3
2
1 3
R250 2.2K_0402_5% R250 2.2K_0402_5% 1 2
L36
WCM-2012-900T_0805
@
L36
WCM-2012-900T_0805
@
1
1
2
2
3
3
4
4
R593 0_0402_5% R593 0_0402_5% 1 2
D10
CH491DPT_SOT23-3
D10
CH491DPT_SOT23-3
2 1
C357
47P_0402_50V8J
@
C357
47P_0402_50V8J
@
1
2
C287 .1U_0402_16V7K C287 .1U_0402_16V7K 1 2
R569 0_0402_5% R569 0_0402_5% 1 2
C282 .1U_0402_16V7K C282 .1U_0402_16V7K 1 2
F2
1.1A_6V_SMD1812P110TF
F2
1.1A_6V_SMD1812P110TF
2 1
C280 .1U_0402_16V7K C280 .1U_0402_16V7K 1 2
R573 680_0402_5% R573 680_0402_5% 1 2
R570 680_0402_5% R570 680_0402_5% 1 2
C
3
2
4
2
2
0
P
_
0
4
0
2
_
5
0
V
7
K
C
3
2
4
2
2
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
R583 680_0402_5% R583 680_0402_5% 1 2
R594 680_0402_5% R594 680_0402_5% 1 2
C281 .1U_0402_16V7K C281 .1U_0402_16V7K 1 2
R198
1M_0402_5%
R198
1M_0402_5%
1
2
J HDMI1
ACON_HMR2E-AK120D
CONN@
J HDMI1
ACON_HMR2E-AK120D
CONN@
D2+
1
D2_shield
2
D2-
3
D1+
4
D1_shield
5
D1-
6
D0+
7
D0_shield
8
D0-
9
CK+
10
CK_shield
11
CK-
12
CEC
13
Reserved
14
SCL
15
SDA
16
DDC/CEC_GND
17
+5V
18
HP_DET
19
GND
20
GND
21
GND
22
GND
23
G
D S
Q17 SSM3K7002F_SC59-3
G
D S
Q17 SSM3K7002F_SC59-3
2
1 3
R253 2.2K_0402_5% R253 2.2K_0402_5% 1 2
L40
WCM-2012-900T_0805
@
L40
WCM-2012-900T_0805
@
1
1
2
2
3
3
4
4
C286 .1U_0402_16V7K C286 .1U_0402_16V7K 1 2
C284 .1U_0402_16V7K C284 .1U_0402_16V7K 1 2
D11
RB751V40_SC76-2
D11
RB751V40_SC76-2
2
1
R219
100K_0402_5%
R219
100K_0402_5%
1
2
G
D
S
Q37
SSM3K7002F_SC59-3
G
D
S
Q37
SSM3K7002F_SC59-3
2
1
3
C283 .1U_0402_16V7K C283 .1U_0402_16V7K 1 2
R785
0_0402_5%
R785
0_0402_5%
1
2
C358
47P_0402_50V8J
@
C358
47P_0402_50V8J
@
1
2
R584 0_0402_5% R584 0_0402_5% 1 2
R591 0_0402_5% R591 0_0402_5% 1 2
R580 680_0402_5% R580 680_0402_5% 1 2
R586 0_0402_5% R586 0_0402_5% 1 2
L38
WCM-2012-900T_0805
@
L38
WCM-2012-900T_0805
@
1
1
2
2
3
3
4
4
G
DSQ14
SSM3K7002F_SC59-3
G
DSQ14
SSM3K7002F_SC59-3
2
1 3
D12
RB751V40_SC76-2
D12
RB751V40_SC76-2
2
1

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PRX_C_DTX_N2
SATA_PRX_DTX_P2
SATA_PRX_DTX_N2
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
SATA_PTX_DRX_P2
SATA_PTX_DRX_N2
+5VS_ODD
SATA_PRX_C_DTX_P2
+5VS_HDD1
+5VS
+3VS
+3VS
+5VS_ODD
+5VS_HDD1
+5VS
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
SATA ODD Conn.
CL 4.0 mm
SATA HDD1 Conn.
100mils
80mils
R02 Modify
R02 Modify
C
7
4
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
7
4
4
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
1
9
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
C
1
9
9
1
0
U
_
0
6
0
3
_
6
.
3
V
6
M
1
2
C
2
0
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
2
0
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
2
0
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
2
0
1
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C708 0.01U_0402_16V7K C708 0.01U_0402_16V7K 1 2
C
7
4
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
7
4
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
7
4
2
1
0
0
0
P
_
0
4
0
2
_
5
0
V
7
K
C
7
4
2
1
0
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
R2052
0_0805_5%
R2052
0_0805_5% 1 2
R2051
0_0805_5%
R2051
0_0805_5% 1 2
C643 0.01U_0402_16V7K C643 0.01U_0402_16V7K 1 2
C711 0.01U_0402_16V7K C711 0.01U_0402_16V7K 1 2
C712 0.01U_0402_16V7K C712 0.01U_0402_16V7K 1 2
J HDD1
OCTEK_SAT-22DD1G
CONN@
J HDD1
OCTEK_SAT-22DD1G
CONN@
GND
1
RX+
2
RX-
3
GND
4
TX-
5
TX+
6
GND
7
3.3V
8
3.3V
9
3.3V
10
GND
11
GND
12
GND
13
5V
14
5V
15
5V
16
GND
17
Rsv
18
GND
19
12V
20
12V
21
12V
22
GND
23
GND
24
T79 PAD @ T79 PAD @
C
1
9
2
1
0
0
0
P
_
0
4
0
2
_
5
0
V
7
K
C
1
9
2
1
0
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
J ODD1
OCTEK_SLS-13SB1G_RV
CONN@
J ODD1
OCTEK_SLS-13SB1G_RV
CONN@
GND
1
A+
2
A-
3
GND
4
B-
5
B+
6
GND
7
DP
8
+5V
9
+5V
10
MD
11
GND
12
GND
13
GND
14
GND
15
GND
17
GND
16
C713 0.01U_0402_16V7K C713 0.01U_0402_16V7K 1 2
C628 0.01U_0402_16V7K C628 0.01U_0402_16V7K 1 2
C624 0.01U_0402_16V7K C624 0.01U_0402_16V7K 1 2
C639 0.01U_0402_16V7K C639 0.01U_0402_16V7K 1 2
C
7
4
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
7
4
0
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C453
0.1U_0402_16V4Z
C453
0.1U_0402_16V4Z
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LAN_XTALI
LAN_XTALO_R
LAN_XTALO
+LAN_AVDDL
+LAN_GPHYPLLVDDL
+LAN_PCIEPLLVDD
LAN_MIDI2-
+LAN_AVDDL
+LAN_PCIEPLLVDD
+LAN_GPHYPLLVDDL
PCIE_PRX_C_DTX_N1
PCIE_PRX_C_DTX_P1
LAN_PME#
LAN_RDAC
+LAN_BIASVDDH
+LAN_XTALVDDH
+LAN_XTALVDDH
+LAN_BIASVDDH
+LAN_AVDDH
LAN_MIDI3+
LAN_MIDI0-
LAN_MIDI1+
LAN_MIDI2+
SPROM_CLK
SPROM_DOUT
+1.2V_LAN_OUT
LAN_XTALO_R
LAN_XTALI
+LAN_AVDDH
CR_DATA0_R
CR_DATA1_R
CR_DATA2_R
CR_DATA3_R
CR_DATA4_R
CR_DATA5_R
CR_DATA6_R
CR_DATA7_R
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
+VDDO_CR
CR_XD_WE#_SD_DETECT_R
CR_XD_DETECT#_R
CR_XD_CE#_MS_INS#_R
CR_WP#_XD_WP#_R
CR_PWR_EN_R
CR_CLK_XD_RY_BY#_R
CR_CMD_XD_CLE_R
CR_XD_WE#_SD_DETECT
CR_XD_DETECT#
CR_XD_CE#_MS_INS#
CR_XD_RE#
CR_WP#_XD_WP#
CR_PWR_EN
CR_CMD_XD_CLE
LAN_MIDI3-
LAN_MIDI1-
LAN_MIDI0+
SPROM_DOUT
CR_XD_RE#_R
+VDDO_CR_R
CR_5IN1_LED#_R
CR_PWR_XD_ALE
CR_5IN1_LED#
CR_CLK_XD_RY_BY#
SPROM_CLK
PLT_RST_BUF#
+VDDO_CR
L
A
N
_
P
W
R
_
E
N
#
EC_PME# <37,40>
PLT_RST_BUF# <17,37,40>
CLK_PCIE_LAN <14>
CLK_PCIE_LAN# <14>
LAN_CLKREQ# <14>
LAN_MIDI2- <36>
LAN_MIDI1- <36>
LAN_MIDI3- <36>
LAN_MIDI3+ <36>
LAN_MIDI2+ <36>
LAN_MIDI1+ <36>
LAN_MIDI0- <36>
LAN_MIDI0+ <36>
LAN_LINK# <36>
LAN_ACTIVITY# <36>
CR_XD_WE#_SD_DETECT <36>
CR_XD_DETECT# <36>
CR_XD_CE#_MS_INS# <36>
CR_WP#_XD_WP# <36>
CR_PWR_EN <36>
CR_CMD_XD_CLE <36>
CR_XD_RE# <36>
CR_CLK_XD_RY_BY# <36>
CR_DATA0 <36>
CR_DATA1 <36>
CR_DATA2 <36>
CR_DATA3 <36>
CR_DATA4 <36>
CR_DATA5 <36>
CR_DATA6 <36>
CR_DATA7 <36>
CR_5IN1_LED# <41>
CR_PWR_XD_ALE <36>
PCH_PWR_EN# <20,44> LAN_PWR_EN# <40>
+3V_LAN
+3V_LAN
+1.2V_LAN
+1.2V_LAN
+1.2V_LAN
+3V_LAN
+1.2V_LAN
+3V_LAN
+3VS
+1.2V_LAN
+3V_LAN
+1.2V_LAN
+3V_LAN
+3V_LAN
+VDDO_CR
+VDDO_CR
+3VALW +3V_LAN
+3V_LAN
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
20mil
20mil
20mil
SM010005500 500ma 600ohm@100mhz DCR 0.38
On chip
AT24C02
SPROM_CLK
(EECLK)
SPROM_DOUT
(EEDATA)
1 1
0 1
20mil
20mil
20mil
40mil
60mil
15mil
40mil
40mil
PLACE NEXT P14
EMI Request...2010/07/27
R824 (CP_PWR_XD_ALE)
for B0 version
For EMI request
R02 modify for ESD
R02 Modify
R02 Modify
R02 Modify
R02 modify
R03 modify
R168 33_0402_5% R168 33_0402_5% 1 2
C656
0.1U_0402_16V4Z
C656
0.1U_0402_16V4Z
1
2
R2120
10K_0402_5%
R2120
10K_0402_5%
1 2
C
6
7
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
7
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
6
7
8
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
6
7
8
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
C
6
7
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
7
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C658
0.1U_0402_16V4Z
C658
0.1U_0402_16V4Z
1
2
R200 0_0402_5% R200 0_0402_5% 1 2
D
G
S
Q2007
AO3413L_SOT23-3
D
G
S
Q2007
AO3413L_SOT23-3
1
2
3
C659
4.7U_0603_6.3V6K
C659
4.7U_0603_6.3V6K
1
2
C299
0.1U_0402_16V4Z
C299
0.1U_0402_16V4Z
1
2
C692
4.7U_0603_6.3V6K
C692
4.7U_0603_6.3V6K
1
2
R229 0_0402_5% R229 0_0402_5% 1 2
C681
15P_0402_50V8J
C681
15P_0402_50V8J
1
2
C306
0.1U_0402_16V4Z
C306
0.1U_0402_16V4Z
1
2
R201 0_0402_5% R201 0_0402_5% 1 2
R2097
0_0805_5%
@ R2097
0_0805_5%
@
1 2
R192 33_0402_5% R192 33_0402_5% 1 2 R207 33_0402_5% R207 33_0402_5% 1 2
C657
0.1U_0402_16V4Z
C657
0.1U_0402_16V4Z
1
2
U31
AT24C04BN-SH-T_SO8
SA00004QG00
@ U31
AT24C04BN-SH-T_SO8
SA00004QG00
@
A0
1
A1
2
A2
3
GND
4
VCC
8
WP
7
SCL
6
SDA
5
R213 0_0402_5% @ R213 0_0402_5% @ 1 2
C329
0.01U_0402_16V7K
@
C329
0.01U_0402_16V7K
@
1
2
R171 33_0402_5% R171 33_0402_5% 1 2
C
6
8
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
8
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R214 0_0603_5% R214 0_0603_5% 1 2
R227 0_0402_5% R227 0_0402_5% 1 2
C634 0.1U_0402_16V4Z C634 0.1U_0402_16V4Z 1 2
R199 33_0402_5% R199 33_0402_5% 1 2
C691
10U_0603_6.3V6M
C691
10U_0603_6.3V6M
1
2
R190 1K_0402_5% R190 1K_0402_5% 1 2
BCM57785XA0KMLG_QFN68_8X8
U32
BCM57785XA0KMLG_QFN68_8X8
U32
AVDDL
51
SR_VDDP
15
TRD1_P
44
AVDDH
42
AVDDH
48
TRD1_N
43
AVDDL
45
TRD2_P
46
VDDO
62
TRD0_N
41
SD_DETECT/XD_WE#
1
TRD3_P
50
TRD3_N
49
VMAIN_PRSNT
58
CR_DATA0
25
AVDDL
39
RDAC
38
BIASVDDH
37
WAKE#
3
SR_VDD
14
SR_LX
16
XTALI
18
XTALO
19
XTALVDDH
17
VDDO_CR
20
VDDO
7
TRD0_P
40
PREST#
11
PCIE_TXD_N
27
SR_VFB
13
PCIE_PLLVDDL
32
PCIE_REFCLK_P
31
PCIE_RXD_P
33
GPHY_PLLVDDL
36
PCIE_REFCLK_N
30
PCIE_PLLVDDL
29
PCIE_RXD_N
34
PCIE_TXD_P
28
TRD2_N
47
VDDC
35
SCLK_SPD1000LED#
66
SPD100LED#_SERIALDO
2
CS#_EECLK
63
TRAFFICLED#_SERIALDI
67
VDDC
61
VDDO
56
CLK_REQ#
12
TEST2
10
TEST1
6
CR_DATA1
24
CR_DATA3
22
CR_DATA2
23
CR_DATA5
53
CR_DATA4
52
CR_DATA6
54
CR_DATA7
55
LOW_PWR
4
GPIO1_LR_OUT
8
GPIO_0
5
SI_EEDATA
64
SO_LINKLED#
65
SR_DISABLE/XD_DETECT#
68
MS_INS#/XD_CE#
59
GPIO2_MEDIA_SENSE/XD_RE#
9
CR_WP#/XD_WP#
57
CR_LED_CR_BUS_PWR/XD_ALE
60
CR_CLK/XD_RY_BY#
21
CR_CMD_XD_CLE
26
G
N
D

P
L
A
N
E
6
9
L37
4.7UH_PG031B-4R7MS_1.1A_20%
L37
4.7UH_PG031B-4R7MS_1.1A_20%
1 2
C684
0.1U_0402_16V4Z
C684
0.1U_0402_16V4Z
1
2
C
6
6
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
6
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R196 0_0402_5% R196 0_0402_5% 1 2
R562
200_0402_1%
R562
200_0402_1%
1
2
L18
BLM18AG601SN1D_2P
L18
BLM18AG601SN1D_2P
1 2
C689
0.1U_0402_16V4Z
C689
0.1U_0402_16V4Z
1
2
C
6
6
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
6
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
Y4
25MHZ 10PF 7V25000014
Y4
25MHZ 10PF 7V25000014
GND
2
3
3
1
1
GND
4
R
5
2
5
1
K
_
0
4
0
2
_
5
%
@
R
5
2
5
1
K
_
0
4
0
2
_
5
%
@
1
2
L15
BLM18AG601SN1D_2P
L15
BLM18AG601SN1D_2P
1 2
R211 33_0402_5% R211 33_0402_5% 1 2
C
6
8
3
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
6
8
3
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
R225 0_0402_5% R225 0_0402_5% 1 2
C679
15P_0402_50V8J
C679
15P_0402_50V8J
1
2
R576 0_0402_5% R576 0_0402_5% 1 2
R179 33_0402_5% R179 33_0402_5% 1 2
R541 1.24K_0402_1% R541 1.24K_0402_1%
1 2
R185 0_0402_5% R185 0_0402_5% 1 2
R
5
3
6
1
K
_
0
4
0
2
_
5
%
R
5
3
6
1
K
_
0
4
0
2
_
5
%
1
2
C
6
9
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
9
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
L17
BLM18AG601SN1D_2P
L17
BLM18AG601SN1D_2P
1 2
C
2
0
7
7
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
2
0
7
7
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
R208 0_0402_5% R208 0_0402_5% 1 2
C
6
6
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
6
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
6
6
2
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
6
6
2
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
C673 .1U_0402_16V7K C673 .1U_0402_16V7K 1 2
R
5
3
7
1
K
_
0
4
0
2
_
5
%
@
R
5
3
7
1
K
_
0
4
0
2
_
5
%
@
1
2
C
2
9
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
2
9
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
3
0
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
3
0
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
L34
BLM18AG601SN1D_2P
L34
BLM18AG601SN1D_2P
1 2
C323
0.1U_0402_16V4Z
C323
0.1U_0402_16V4Z
1
2
L35
BLM18AG601SN1D_2P
L35
BLM18AG601SN1D_2P
1 2
R572 0_0402_5% R572 0_0402_5% 1 2
R215 33_0402_5% R215 33_0402_5% 1 2
R
5
3
8
1
K
_
0
4
0
2
_
5
%
R
5
3
8
1
K
_
0
4
0
2
_
5
%
1
2
C303
4.7U_0603_6.3V6K
C303
4.7U_0603_6.3V6K
1
2
R182 33_0402_5% R182 33_0402_5% 1 2
C
3
0
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
3
0
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C670 .1U_0402_16V7K C670 .1U_0402_16V7K 1 2
R228 4.7K_0402_5% R228 4.7K_0402_5% 1 2
C294
0.1U_0402_16V4Z
C294
0.1U_0402_16V4Z
1
2
R216 0_0402_5% R216 0_0402_5% 1 2
C297
4.7U_0603_6.3V6K
C297
4.7U_0603_6.3V6K
1
2
L20
BLM18AG601SN1D_2P
L20
BLM18AG601SN1D_2P
1 2
R226 4.7K_0402_5% R226 4.7K_0402_5%
1 2
C2069 0.1U_0402_16V4Z C2069 0.1U_0402_16V4Z 1 2
R195 22_0402_5% R195 22_0402_5% 1 2
R209 4.7K_0402_5% @ R209 4.7K_0402_5% @ 1 2
R2131
0_0402_5%
@ R2131
0_0402_5%
@
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RJ 45_MIDI1-
RJ 45_MIDI1+
LAN_MIDI2-
RJ 45_MIDI3-
RJ 45_MIDI3+
LAN_MIDI0-
RJ 45_MIDI2+
RJ 45_MIDI2-
LAN_MIDI3+
RJ 45_GND
LAN_MIDI3-
LAN_MIDI1+
LAN_MIDI1-
RJ 45_MIDI0+
RJ 45_MIDI0-
LAN_MIDI2+
LAN_MIDI0+
RJ 45_MIDI2-
RJ 45_MIDI2+
RJ 45_MIDI1+
RJ 45_MIDI0-
RJ 45_MIDI1-
RJ 45_MIDI0+
LANGND
LAN_ACTIVITY#
LAN_LINK#
RJ 45_MIDI3-
RJ 45_MIDI3+
CR_XD_DETECT#
CR_XD_RE#
CR_PWR_XD_ALE
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
CR_DATA3
CR_DATA2
CR_DATA1
CR_DATA0
CR_DATA1
CR_DATA3
CR_DATA2
CR_DATA0
CR_CLK_XD_RY_BY#
CR_CMD_XD_CLE
CR_CLK_XD_RY_BY#_17
CR_CMD_XD_CLE
RJ 45_GND
CR_XD_CE#_MS_INS#
CR_XD_WE#_SD_DETECT
CR_WP#_XD_WP#
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
LAN_LINK#
LAN_ACTIVITY#
RJ 45_GND
CR_CLK_XD_RY_BY#_17 CR_CLK_XD_RY_BY#
CR_CLK_XD_RY_BY#_23
CR_CLK_XD_RY_BY#_23
LAN_MIDI2- <35>
LAN_MIDI0- <35>
LAN_MIDI3- <35>
LAN_MIDI3+ <35>
LAN_MIDI1- <35>
LAN_MIDI1+ <35>
LAN_MIDI2+ <35>
LAN_MIDI0+ <35>
LAN_LINK# <35>
LAN_ACTIVITY# <35>
CR_PWR_XD_ALE <35>
CR_XD_WE#_SD_DETECT <35>
CR_WP#_XD_WP# <35>
CR_XD_DETECT# <35>
CR_DATA4 <35>
CR_DATA5 <35>
CR_DATA6 <35>
CR_DATA7 <35>
CR_XD_RE# <35>
CR_XD_CE#_MS_INS# <35>
CR_DATA1 <35>
CR_DATA2 <35>
CR_DATA3 <35>
CR_DATA0 <35>
CR_CMD_XD_CLE <35>
CR_PWR_EN <35>
CR_CLK_XD_RY_BY# <35>
+XDPWR_SDPWR_MSPWR
+3VALW
+XDPWR_SDPWR_MSPWR
+VDDO_CR
+3VALW +3VS
+3V_LAN
+3V_LAN
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00
Place close to TCT pin
C474,C475 and D14
ME interefer,do not pop!!
EMI Request
40mil
LAN Connector
40mil
Card Reader Connector
40mil
R04 modify for EMI
R02 modify for SD3.0 issue
R03 Modify
R04 modify
R04 modify
J
P
3
B
8
8
0
6
9
X
9
2
3
1
T
2
0
3
_
4
P
5
X
3
P
2
-
2
@
J
P
3
B
8
8
0
6
9
X
9
2
3
1
T
2
0
3
_
4
P
5
X
3
P
2
-
2
@
1
2
C474 68P_0402_50V8J
@
C474 68P_0402_50V8J
@
1 2
R2088 10_0402_5% R2088 10_0402_5%
1 2
C
6
1
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
1
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C2096
6P_0402_50V8D
@
C2096
6P_0402_50V8D
@
1
2
C2094
6.8P_0402_50V8C
C2094
6.8P_0402_50V8C
1 2
C475
68P_0402_50V8J
@
C475
68P_0402_50V8J
@
1 2 C
4
7
6
2
2
0
P
_
0
4
0
2
_
5
0
V
7
K
C
4
7
6
2
2
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
C
2
0
9
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
2
0
9
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R
4
9
1
7
5
_
0
6
0
3
_
1
%
R
4
9
1
7
5
_
0
6
0
3
_
1
%
1
2
C
6
1
9
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
1
9
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R
4
9
0
7
5
_
0
6
0
3
_
1
%
R
4
9
0
7
5
_
0
6
0
3
_
1
%
1
2
G
D
S Q31
SSM3K7002F_SC59-3
G
D
S Q31
SSM3K7002F_SC59-3
2
1
3
J READ1
TAITW_R013-P17-HM_NR
CONN@
J READ1
TAITW_R013-P17-HM_NR
CONN@
SD_VCC
11
MS_VCC
18
XD_VCC
39
XD_D0
31
XD_D1
32
XD_D2
33
XD_D3
34
XD_D4
35
XD_D5
36
XD_D6
37
XD_D7
38
XD_CD
22
XD_R/B
23
XD_RE
24
XD_CE
25
XD_CLE
26
XD_ALE
27
XD_WE
28
XD_WP-IN
29
SD_GND
6
SD_GND
13
MS_GND
20
XD_GND
30
GND
41
GND
42
MS_DATA0
10
MS_DATA1
9
MS_DATA2
12
MS_DATA3
15
MS_SCLK
17
MS_INS
14
MS_BS
7
SD_WP
2
SD/MMC_DAT0
4
SD/MMC_DAT1
3
SD/MMC_DAT2
21
SD/MMC_DAT3
19
SD_CLK
8
SD_CMD
16
SD_CD
1
XD_GND
40
MS_GND
5
J P2
B88069X9231T203_4P5X3P2-2
@
J P2
B88069X9231T203_4P5X3P2-2
@
1 2
R384 1K_0402_5% R384 1K_0402_5%
1 2
C478 10P_0402_50V8J C478 10P_0402_50V8J 1 2
U16
AP2301MPG-13_MSOP8
U16
AP2301MPG-13_MSOP8
FLG
5
VIN
3
VOUT
6
GND
1
EN
4
VOUT
7
VIN
2
VOUT
8
E
P
A
D
9
R304
300_0603_5%
R304
300_0603_5%
1
2
R2102 0_0402_5% R2102 0_0402_5% 1 2
C
8
3
2
1
0
0
P
_
0
4
0
2
_
5
0
V
8
J
@
C
8
3
2
1
0
0
P
_
0
4
0
2
_
5
0
V
8
J
@
1
2
C
4
7
3
2
2
0
P
_
0
4
0
2
_
5
0
V
7
K
C
4
7
3
2
2
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
C
2
0
9
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
2
0
9
2
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
6
2
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
2
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R
4
9
2
7
5
_
0
6
0
3
_
1
%
R
4
9
2
7
5
_
0
6
0
3
_
1
%
1
2
C
3
8
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
3
8
1
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R
4
9
3
7
5
_
0
6
0
3
_
1
%
R
4
9
3
7
5
_
0
6
0
3
_
1
%
1
2
R385 1K_0402_5% R385 1K_0402_5%
1 2
C
6
1
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
6
1
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R2101
22_0402_5%
R2101
22_0402_5%
1 2
D14
L30ESDL5V0C3-2
@
D14
L30ESDL5V0C3-2
@
23
1
J P1
B88069X9231T203_4P5X3P2-2
@J P1
B88069X9231T203_4P5X3P2-2
@
1 2
C
4
3
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
4
3
4
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
L
5
3
1
0
0
U
H
_
S
S
C
0
3
0
1
1
0
1
M
C
F
_
0
.
1
8
A
_
2
0
%
L
5
3
1
0
0
U
H
_
S
S
C
0
3
0
1
1
0
1
M
C
F
_
0
.
1
8
A
_
2
0
%
1
2
C2097 120P_1206_2KV8J
@
C2097 120P_1206_2KV8J
@
1 2
C
4
3
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
4
3
3
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
D
3
6
L
3
0
E
S
D
L
5
V
0
C
3
-
2
D
3
6
L
3
0
E
S
D
L
5
V
0
C
3
-
2
23
1
R303
0_0805_5%
@
R303
0_0805_5%
@ 1 2
C
4
2
1
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
2
1
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
J RJ 45
SANTA_130451-K
CONN@
J RJ 45
SANTA_130451-K
CONN@
YellowLED-
12
YellowLED+
11
PR4-
8
PR4+
7
PR2-
6
PR3-
5
PR3+
4
PR2+
3
PR1-
2
PR1+
1
Green LED-
10
Green LED+
9
SHLD2
13
SHLD1
14
J 10
J UMP_43X118
@
J 10
J UMP_43X118
@
1
1
2
2
T28
IH-160
SP050006F00
T28
IH-160
SP050006F00
TCT1
1
TD1+
2
TD1-
3
TCT2
4
TD2+
5
TD2-
6
TCT3
7
TD3+
8
TD3-
9
TCT4
10
TD4+
11
TD4-
12
MCT1
24
MX1+
23
MX1-
22
MCT2
21
MX2+
20
MX2-
19
MCT3
18
MX3+
17
MX3-
16
MCT4
15
MX4+
14
MX4-
13

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MINI1_LED#
E51TXD_P80DATA_R
PLT_RST_BUF#
MINI1_SMBCLK
MINI1_SMBDATA
E51RXD_P80CLK_R
WWAN_PTX_C_DRX_N1
WWAN_PTX_C_DRX_P1
WWAN_PRX_C_DTX_P1
WWAN_PRX_C_DTX_N1
WWAN_PRX_C_DTX_N1
WWAN_PRX_C_DTX_P1
WWAN_PTX_C_DRX_N1
WWAN_PTX_C_DRX_P1
WWAN_PRX_C_DTX_P1 SATA_PRX_DTX_P1
SATA_PRX_DTX_N1 WWAN_PRX_C_DTX_N1
SATA_PTX_DRX_N1 WWAN_PTX_C_DRX_N1
WWAN_PTX_C_DRX_P1 SATA_PTX_DRX_P1
E51RXD_P80CLK_R MSATA_DET# WL_OFF#
MINI1_CLKREQ#_R
CLK_PCIE_MINI1#_R
CLK_PCIE_MINI1_R
BT_CTRL SUSP#
BT_CTRL
3VSWLAN_GATE 3VSWLAN_GATE_R
3VSWLAN_R
3VSWLAN_GATE
PCH_PCIE_WAKE#_R
BT_LED#
MINI1_LED# <40>
MINI1_CLKREQ# <14>
CLK_PCIE_MINI1# <14>
CLK_PCIE_MINI1 <14>
PLT_RST_BUF# <17,35,40>
USB20_N8 <17>
USB20_P8 <17>
PCH_SMBDATA <14>
PCH_SMBCLK <14>
E51RXD_P80CLK <40>
E51TXD_P80DATA <40>
MSATA_DET# <18> WL_OFF# <18,40>
BT_ON# <18,39,40>
SUSP# <40,44,47,49,50>
EC_PME# <35,40>
WLAN_ON <40>
WLAN_PME# <40>
BT_LED# <40>
+3VS_FULL
+1.5VS_FULL +3VS_FULL
+3VS_FULL
+3VS +3VS_FULL
+3VS_FULL +3VS_FULL +1.5VS_FULL
+1.5VS +1.5VS_FULL
+3VALW
+3VALW +3VS_FULL
+3VS_FULL
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
(9~16mA)
60mil
60mil
For Wireless LAN or MSATA
Enable Disable
L H
H L
BT
on module
BT
on module
WLAN&BT Combo module circuits
BT_CTRL
BT_ON#
R02 Modify R02 Modify
40mil(1A)
R2060 0_0402_5% PCIE@ R2060 0_0402_5% PCIE@ 1 2
C2098
4.7U_0603_6.3V6K
AC@ C2098
4.7U_0603_6.3V6K
AC@
1
2
R337 0_0402_5% @ R337 0_0402_5% @ 1 2
C2047 0.01U_0402_16V7K
mSATA@
C2047 0.01U_0402_16V7K
mSATA@ 1 2
R2115
1K_0402_5%
AC@R2115
1K_0402_5%
AC@
1 2
R2109
0_0402_5%
@R2109
0_0402_5%
@
1 2
Q2010B
AC@ Q2010B
AC@
3
4
5
R2112 100K_0402_5%
AC@
R2112 100K_0402_5%
AC@1 2
R2108
0_0402_5%
AC@ R2108
0_0402_5%
AC@
1 2
R2134
0_0402_5%
AC@ R2134
0_0402_5%
AC@ 1 2
Q2010A
AC@ Q2010A
AC@
6
1
2
R300
100K_0402_5%
R300
100K_0402_5%
1
2
R2058 0_0402_5%
mSATA@
R2058 0_0402_5%
mSATA@1 2
R299 0_0402_5% R299 0_0402_5% 1 2
R2046 0_0402_5% PCIE@ R2046 0_0402_5% PCIE@ 1 2
R2135 4.7K_0402_5%
@
R2135 4.7K_0402_5%
@ 1 2
R335 0_0402_5% @ R335 0_0402_5% @ 1 2
R702
0_0402_5%
@R702
0_0402_5%
@
1 2
R2047 0_0402_5% PCIE@ R2047 0_0402_5% PCIE@ 1 2
C2045 0.01U_0402_16V7K
mSATA@
C2045 0.01U_0402_16V7K
mSATA@ 1 2
R352 0_0805_5%
NOAC@
R352 0_0805_5%
NOAC@
1 2
R2111 0_0805_5%
@
R2111 0_0805_5%
@
1 2
R2044 0_0402_5% PCIE@ R2044 0_0402_5% PCIE@ 1 2
R2114
470_0603_5%
AC@ R2114
470_0603_5%
AC@
1
2
C441
0.1U_0402_16V4Z
C441
0.1U_0402_16V4Z
1
2
J MINI1
ACES_51711-0520W-001
CONN@
J MINI1
ACES_51711-0520W-001
CONN@
31
31
32
32
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
GND
53
GND
54
R2045 0_0402_5% PCIE@ R2045 0_0402_5% PCIE@ 1 2
C442
0.1U_0402_16V4Z
C442
0.1U_0402_16V4Z
1
2
D
G
S
Q2009
AO3419L_SOT23-3
AC@
D
G
S
Q2009
AO3419L_SOT23-3
AC@
1
2
3
C2046 0.01U_0402_16V7K
mSATA@
C2046 0.01U_0402_16V7K
mSATA@ 1 2
R305
100K_0402_5%
R305
100K_0402_5%
1
2
C466
0.1U_0402_16V4Z
C466
0.1U_0402_16V4Z
1
2
C2099
0.1U_0402_16V7K
AC@ C2099
0.1U_0402_16V7K
AC@
1
2
C443
4.7U_0603_6.3V6K
C443
4.7U_0603_6.3V6K
1
2
R2061 0_0402_5% PCIE@ R2061 0_0402_5% PCIE@ 1 2
G
D
S
Q57
SSM3K7002F_SC59-3
G
D
S
Q57
SSM3K7002F_SC59-3
2
1
3
C2100
0.1U_0402_16V7K
AC@ C2100
0.1U_0402_16V7K
AC@
1
2
R2040 0_0805_5% R2040 0_0805_5%
1 2
C2048 0.01U_0402_16V7K
mSATA@
C2048 0.01U_0402_16V7K
mSATA@ 1 2
R2062 0_0402_5% PCIE@ R2062 0_0402_5% PCIE@ 1 2
C455
4.7U_0603_6.3V6K
C455
4.7U_0603_6.3V6K
1
2
R287 0_0402_5% R287 0_0402_5% 1 2
D32
@
D32
@
2 1
R2113 1K_0402_5%
AC@
R2113 1K_0402_5%
AC@1 2
R288 1K_0402_5%

R288 1K_0402_5%

1 2
C467
0.1U_0402_16V4Z
C467
0.1U_0402_16V4Z
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/13 2012/06/13
4019ID
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/13 2012/06/13
4019ID
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/13 2012/06/13
4019ID

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
BT_ON#
SYSON#
USB20_P2
USB20_N2
USB20_N1
USB20_P1
PCH_USB3_TX1_P_C
U3TXDN1
U3TXDP1
PCH_USB3_TX1_N_C
PCH_USB3_RX1_P
PCH_USB3_RX1_N U3RXDN1
U3RXDP1
U3TXDP1
U3TXDN1
U3RXDN1 U3RXDN1
U3TXDN1
U3RXDP1
U3TXDP1
U3RXDP1
U3TXDP1
U3RXDN1
U2DP0
U3RXDP1
U3TXDN1
U2DN0
U2DP0
U2DN0
U2DP0
U2DN0
BT_ON# <18,37,40>
WL_EN# <18>
USB20_N1 <17>
USB20_P1 <17>
PCH_USB3_TX1_P <17>
PCH_USB3_TX1_N <17>
PCH_USB3_RX1_P <17>
PCH_USB3_RX1_N <17>
U3RXDP1
U3RXDN1
U3TXDP1
U3TXDN1
U2DP0
U2DN0
SYSON# <44>
USB20_N11 <17>
USB20_P11 <17>
USB20_P0 <17>
USB20_N0 <17>
USB_OC0# <17>
USB20_N2 <17>
USB20_P2 <17>
+BT_VCC
+3VS
+BT_VCC
+5VALW
+5VALW
+USB3_VCCA
+USB3_VCCA
+5VALW +USB3_VCCA
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
W=40mils
BT Wire Cable Note:
Pin 3, Pin 4 NC
BT Conn.
(Port 13)
(WLAN_BT_DATA)
(WLAN_BT_CLK)
W=100mils
USB/B Conn.
(Port 0,2)
Deafult use PCH side USB3.0 signal
For USB2.0 ESD request
R02 modify for ESD
Deafult use PCH side USB3.0 signal
For ESD request
W=60mils
USB3.0 Conn.
For USB2.0 ESD request
W=60mils
R02 modify for ESD
R03 modify
R05 modify
R05 modify
R04 modify
Q41
AP2301GN-HF_SOT23-3
BT@
Q41
AP2301GN-HF_SOT23-3
BT@
2
3
1
CI19 0.1U_0402_16V4Z
PUSB3@
CI19 0.1U_0402_16V4Z
PUSB3@
1 2
C417
0.1U_0402_16V4Z
C417
0.1U_0402_16V4Z
1
2
+
C
3
9
0
2
2
0
U
_
6
.
3
V
_
M

+
C
3
9
0
2
2
0
U
_
6
.
3
V
_
M

1
2
L52
WCM-2012-900T_0805
@ L52
WCM-2012-900T_0805
@
1
1
2
2
3
3
4
4
L3
OCE2012120YZF_0805
PUSB3@ L3
OCE2012120YZF_0805
PUSB3@
1
1
2
2
3
3
4
4
R709
300_0603_5%
BT@
R709
300_0603_5%
BT@
1
2
R9 0_0402_5% @ R9 0_0402_5% @ 1 2
G
D
S
Q42
SSM3K7002F_SC59-3
BT@
G
D
S
Q42
SSM3K7002F_SC59-3
BT@
2
1
3
R710
10K_0402_5%
BT@
R710
10K_0402_5%
BT@ 1 2
R314
0_0402_5%
PUSB@
R314
0_0402_5%
PUSB@
1 2
C432
.1U_0402_16V7K
C432
.1U_0402_16V7K
1 2
R10 0_0402_5% @ R10 0_0402_5% @ 1 2
C729
0.1U_0402_16V4Z
BT@
C729
0.1U_0402_16V4Z
BT@
D24
D24
I/O4
6
VDD
5
I/O3
4
I/O2
3
GND
2
I/O1
1
C730
4.7U_0603_6.3V6K
BT@
C730
4.7U_0603_6.3V6K
BT@
1
2
C731
1U_0603_10V6K
BT@
C731
1U_0603_10V6K
BT@
1
2
L4
OCE2012120YZF_0805
PUSB3@ L4
OCE2012120YZF_0805
PUSB3@
1
1
2
2
3
3
4
4
J USB2
ACES_85201-1205N
CONN@
J USB2
ACES_85201-1205N
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
GND
13
GND
14
8
D35
L05ESDL5V0NA-4
@
8
D35
L05ESDL5V0NA-4
@
4
5
1
6
2
7
3
10
9
CI18 0.1U_0402_16V4Z
PUSB3@
CI18 0.1U_0402_16V4Z
PUSB3@
1 2
J BT1
ACES_87213-0800G
CONN@
J BT1
ACES_87213-0800G
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
GND
9
GND
10
R11 0_0402_5% @ R11 0_0402_5% @ 1 2
J USB1
ACON_TARA4-9K1311
CONN@
DC233007O00
J USB1
ACON_TARA4-9K1311
CONN@
DC233007O00
SSTX-
8
SSTX+
9
GND
10
GND
11
VBUS
1
D+
3
D-
2
GND
4
SSRX-
5
SSRX+
6
GND
7
GND
13
GND
12
C738
0.1U_0402_16V4Z
BT@
C738
0.1U_0402_16V4Z
BT@
1
2
R687 0_0402_5%
PUSB@
R687 0_0402_5%
PUSB@ 1 2
R12 0_0402_5% @ R12 0_0402_5% @ 1 2
C
3
9
1
4
7
0
P
_
0
4
0
2
_
5
0
V
7
K
C
3
9
1
4
7
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
C2070
0.1U_0402_16V4Z
C2070
0.1U_0402_16V4Z
1
2
R686 0_0402_5%
PUSB@
R686 0_0402_5%
PUSB@ 1 2
U17
AP2301MPG-13_MSOP8
U17
AP2301MPG-13_MSOP8
FLG
5
VIN
3
VOUT
6
GND
1
EN
4
VOUT
7
VIN
2
VOUT
8
E
P
A
D
9

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
KSO[0..17]
KSI[0..7]
ECAGND
E
C
A
G
N
D
KSO1
KSO2
TP_DATA
TP_CLK
EC_MUTE#
CLK_PCI_LPC
SYSON
EC_SMB_CK1
KSI1
KSO9
BKOFF#
KSI7
FAN_SPEED1
LPC_AD1
AD_BID0
KSI3
KSO4
PLT_RST_BUF#
+V18R EC_XCLK0
PCH_RSMRST#
KSO8
KSO2
EC_SMI#
VR_ON
SUSP#
KSO16
BATT_TEMP
KSI0
KSO1
SERIRQ
FSTCHG
EC_RST#
LPC_AD2
ECAGND
KSO14
EC_KBRST#
EC_SMB_DA1
ADP_I
KSI4
EC_SCI#
LPC_AD3
KSO15
KSO10
KSO0
ACOFF
LPC_AD0
LPC_FRAME#
KSO13
GATEA20
EC_XCLK1
KSI2
KSO11
KSO3
KSI6
BEEP#
+EC_VCCA
KSO12
PM_SLP_S5#
TP_CLK
KSI5
KSO7
E51TXD_P80DATA
TP_DATA
KSO6
KSO5
PM_SLP_S3#
E51RXD_P80CLK
KSO17
KB930_PECI
EC_SMI#
EC_SMB_CK2
EC_SMB_DA2
WLAN_LED#
BATT_AMB_LED#
ME_EN
EC_SCI#
H_PROCHOT#_EC
EC_SMB_DA1
EC_SMB_DA2
EC_SMB_CK2
EC_RST#
CLK_PCI_LPC
EC_MUTE#
VR_HOT#
+3VALW_EC
MINI1_LED#
BKOFF#
EC_SMB_CK1 EC_ACIN
H_PROCHOT#_EC
EC_LID_OUT#
AD_BID0
LID_SW#
SA_PGOOD
ON/OFF
BATT_BLUE_LED#
PWR_LED
EAPD
EC_ACIN
PM_SLP_S4#
PWR_SUSP_LED#
EC_ON
LID_SW#
EC_PME#
+EC_VCC
EC_XCLK1 EC_XCLK0
PLT_RST_BUF#
VGATE
PCH_PWROK
MAINPWON
GPXIOA07
PBTN_OUT#
ENBKL
KB9012_PECI H_PECI
+EC_VCC
GPU_HOT#
EC_PME#
PCH_PWROK_9012
GPU_OVERT
GPU_THERMAL_ALERT#
GPU_THERMAL_ALERT#
GPU_OVERT
GPU_ACIN
PM_SLP_S3#
PM_SLP_S4#
PCH_PWR_EN
WLAN_ON
EN_DFAN1
WLAN_PME#
WL_OFF#
WL_OFF#
BT_ON#
BT_ON#
WLAN_PME#
LAN_PWR_EN# GPIO4B
GPIO4B
BT_LED#
KSI[0..7] <41>
KSO[0..17] <41>
LPC_FRAME# <13>
LPC_AD2 <13>
LPC_AD0 <13>
LPC_AD3 <13>
LPC_AD1 <13>
SERIRQ <13>
TP_CLK <41>
EC_SMB_DA1 <46,47>
EC_SMB_CK1 <46,47>
BEEP# <42>
FSTCHG <47>
EC_SMI# <18>
EC_KBRST# <18>
GATEA20 <18>
BATT_TEMP <46>
FAN_SPEED1 <43>
ADP_I <46,47>
TP_DATA <41>
BKOFF# <31>
PCH_RSMRST# <15>
SYSON <44,49>
VR_ON <52>
CLK_PCI_LPC <17>
EC_SMB_DA2 <14,22>
EC_SMB_CK2 <14,22>
EC_MUTE# <42>
ACOFF <45>
SUSP# <37,44,47,49,50>
EC_SCI# <18>
E51RXD_P80CLK <37>
PLT_RST_BUF# <17,35,37>
E51TXD_P80DATA <37>
H_PECI <5,18>
WLAN_LED# <41>
BATT_AMB_LED# <41>
PM_SLP_S3# <15>
PM_SLP_S5# <15>
SUSCLK <15>
H_PROCHOT# <5,46> VR_HOT# <52>
MINI1_LED# <37>
ACIN <15,44,47,48>
ME_EN <13>
EC_LID_OUT# <18>
SA_PGOOD <51>
BATT_BLUE_LED# <41>
PWR_LED <41>
EC_ON <41,48>
PWR_SUSP_LED# <41>
LID_SW# <41>
EAPD <42>
VGATE <15,52>
PBTN_OUT# <15>
ON/OFF <41>
PM_SLP_S4# <15>
VCIN0_PH <46>
VCIN1_PROCHOT <46>
MAINPWON <46,48>
GPU_HOT# <53>
EC_PME# <35,37>
PCH_PWROK <15>
ENBKL <16>
GPU_THERMAL_ALERT# <22>
GPU_OVERT <22>
GPU_ACIN <22>
PCH_PWR_EN <44>
WLAN_ON <37>
EN_DFAN1 <43>
WLAN_PME# <37>
WL_OFF# <18,37>
BT_ON# <18,37,39>
BT_LED# <37>
LAN_PWR_EN# <35>
+3VALW
+3VS
+5VS
+3VALW
+3VS
+3VS
+3VALW
+3VALW
+3VALW
+3VLP
+3VALW
+3VALW
+3VLP
+3VALW
+3VLP
+3VALW
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/13 2012/06/13
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/13 2012/06/13
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/13 2012/06/13
20mil
Board ID
Ra
Rb
Analog Board ID definition,
Please see page 3.
Latest design guide suggest change to
74LVC1G06.
Follow KB930 checking List
R02 Modify
R02 Modify
R02 Modify
R02 Modify
R02 Modify
R02 Modify
R02 modify for ESD
R04 modify
R02 Modify
R02 Modify
Modify R05
R03 modify
R03 Modify
Co_lay NPCE885N
Modify R04
R04 Modify
Delete Co_lay NPCE885N
R05 Modify
modify on LA7912 V0.3
R807 100K_0402_5% R807 100K_0402_5% 1 2
C2074 0.1U_0402_16V4Z C2074 0.1U_0402_16V4Z 1 2
C721
15P_0402_50V8J
@
C721
15P_0402_50V8J
@
1
2
R363 4.7K_0402_5% R363 4.7K_0402_5% 1 2
R328 47K_0402_5% R328 47K_0402_5% 1 2
R875 0_0402_5%
930@
R875 0_0402_5%
930@ 1 2
R336 47K_0402_5% 930@ R336 47K_0402_5% 930@ 1 2
R2086 10K_0402_5% R2086 10K_0402_5% 1 2
G
D
S
Q26
2N7002H_SOT23-3 G
D
S
Q26
2N7002H_SOT23-3
2
1
3
C
4
5
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
4
5
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R2110 4.7K_0402_5% AC@ R2110 4.7K_0402_5% AC@ 1 2
C454
0.1U_0402_16V4Z
C454
0.1U_0402_16V4Z
1
2
C457
0.1U_0402_16V4Z
C457
0.1U_0402_16V4Z
1
2
R893 0_0402_5% @ R893 0_0402_5% @ 1 2
R317 10K_0402_5% @ R317 10K_0402_5% @ 1 2
R876 0_0402_5%
9012@
R876 0_0402_5%
9012@ 1 2
R2087 10K_0402_5% R2087 10K_0402_5% 1 2
R2126 10K_0402_5%
AC@
R2126 10K_0402_5%
AC@ 1 2
R2133 10K_0402_5% R2133 10K_0402_5%
1 2
C714
22P_0402_50V8J
@
C714
22P_0402_50V8J
@
1 2
C
4
1
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
4
1
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
3
9
9
1
0
0
0
P
_
0
4
0
2
_
5
0
V
7
K
C
3
9
9
1
0
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
R283 0_0402_5% 9012@ R283 0_0402_5% 9012@ 1 2
R2063 10K_0402_5% R2063 10K_0402_5%
1 2
R361 2.2K_0402_5% R361 2.2K_0402_5% 1 2
L23
FBMA-L11-160808-800LMT_0603
L23
FBMA-L11-160808-800LMT_0603
1 2
R367
0_0402_5%
R367
0_0402_5%
1 2
R769 100K_0402_5% R769 100K_0402_5% 1 2
C431 0.1U_0402_16V4Z C431 0.1U_0402_16V4Z 1 2
C
4
0
0
1
0
0
0
P
_
0
4
0
2
_
5
0
V
7
K
C
4
0
0
1
0
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
R2085 200K_0402_5%
9012@
R2085 200K_0402_5%
9012@ 1 2
R359 2.2K_0402_5% R359 2.2K_0402_5% 1 2
R880 0_0402_5%
@
R880 0_0402_5%
@ 1 2
R685 10K_0402_5% R685 10K_0402_5% 1 2
R355 43_0402_1% 930@ R355 43_0402_1% 930@ 1 2
R353
100K_0402_5%
R353
100K_0402_5%
1
2
R697 0_0402_5% R697 0_0402_5%
1 2
R354
100K_0402_5%
R354
100K_0402_5%
1
2
D23 RB751V-40_SOD323-2 D23 RB751V-40_SOD323-2
2 1
C452 100P_0402_50V8J C452 100P_0402_50V8J 1 2
C834 20P_0402_50V8J C834 20P_0402_50V8J
1 2
R2127 10K_0402_5%
@
R2127 10K_0402_5%
@ 1 2
C398
4.7U_0603_6.3V6K
C398
4.7U_0603_6.3V6K
1
2
C
7
2
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
7
2
8
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
L21
FBMA-L11-160808-800LMT_0603
L21
FBMA-L11-160808-800LMT_0603
1 2
R675
33_0402_5%
@
R675
33_0402_5%
@
1 2
R894 0_0402_5% 930@ R894 0_0402_5% 930@ 1 2
R2038
0_0805_5%
R2038
0_0805_5%
1 2
R696 100K_0402_5% R696 100K_0402_5% 1 2
C2072 0.1U_0402_16V4Z C2072 0.1U_0402_16V4Z 1 2
R2125 0_0402_5% R2125 0_0402_5%
1 2
C
7
2
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
7
2
0
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C719 100P_0402_50V8J C719 100P_0402_50V8J 1 2
R691 100K_0402_5% R691 100K_0402_5%
1 2
R735 10K_0402_5% @ R735 10K_0402_5% @ 1 2
R2059 10K_0402_5% R2059 10K_0402_5% 1 2
R676 200K_0402_5%
930@
R676 200K_0402_5%
930@ 1 2
R358 2.2K_0402_5% R358 2.2K_0402_5% 1 2
R339 47K_0402_5% 930@ R339 47K_0402_5% 930@ 1 2
R2124
0_0402_5%
R2124
0_0402_5%
1 2
R364 4.7K_0402_5% R364 4.7K_0402_5% 1 2
R2136 4.7K_0402_5% AC@ R2136 4.7K_0402_5% AC@ 1 2
X1
32.768KHZ_12.5PF_CM31532768DZFT
@
X1
32.768KHZ_12.5PF_CM31532768DZFT
@
1 2
C2071 0.1U_0402_16V4Z C2071 0.1U_0402_16V4Z 1 2
R898 43_0402_1% 9012@ R898 43_0402_1% 9012@ 1 2
LPC & MISC
Int. K/B
Matrix
SM Bus
GPIO
GPIO
AD Input
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPO
GPI
U20
KB9012QF-A2_LQFP128_14X14
LPC & MISC
Int. K/B
Matrix
SM Bus
GPIO
GPIO
AD Input
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPO
GPI
U20
KB9012QF-A2_LQFP128_14X14
GATEA20/GPIO00
1
KBRST#/GPIO01
2
SERIRQ
3
LPC_FRAME#
4
LPC_AD3
5
PM_SLP_S3#/GPIO04
6
LPC_AD2
7
LPC_AD1
8
E
C
_
V
D
D
/
V
C
C
9
LPC_AD0
10
G
N
D
/
G
N
D
1
1
CLK_PCI_EC
12
PCIRST#/GPIO05
13
PM_SLP_S5#/GPIO07
14
EC_SMI#/GPIO08
15
GPIO0A
16
GPIO0B
17
GPIO0C
18
GPIO0D
19
EC_SCII#/GPIO0E
20
GPIO0F
21
E
C
_
V
D
D
/
V
C
C
2
2
BEEP#/GPIO10
23
G
N
D
/
G
N
D
2
4
EC_INVT_PWM/GPIO11
25
GPIO12
26
ACOFF/GPIO13
27
FAN_SPEED1/GPIO14
28
EC_PME#/GPIO15
29
EC_TX/GPIO16
30
EC_RX/GPIO17
31
PCH_PWROK/GPIO18
32
E
C
_
V
D
D
/
V
C
C
3
3
SUSP_LED#/GPIO19
34
G
N
D
/
G
N
D
3
5
NUM_LED#/GPIO1A
36
EC_RST#
37
GPIO1D
38
KSO0/GPIO20
39
KSO1/GPIO21
40
KSO2/GPIO22
41
KSO3/GPIO23
42
KSO4/GPIO24
43
KSO5/GPIO25
44
KSO6/GPIO26
45
KSO7/GPIO27
46
KSO8/GPIO28
47
KSO9/GPIO29
48
KSO10/GPIO2A
49
KSO11/GPIO2B
50
KSO12/GPIO2C
51
KSO13/GPIO2D
52
KSO14/GPIO2E
53
KSO15/GPIO2F
54
KSI0/GPIO30
55
KSI1/GPIO31
56
KSI2/GPIO32
57
KSI3/GPIO33
58
KSI4/GPIO34
59
KSI5/GPIO35
60
KSI6/GPIO36
61
KSI7/GPIO37
62
BATT_TEMP/GPIO38
63
GPIO39
64
ADP_I/GPIO3A
65
GPIO3B
66
E
C
_
V
D
D
/
A
V
C
C
6
7
DAC_BRIG/GPIO3C
68
A
G
N
D
/
A
G
N
D
6
9
EN_DFAN1/GPIO3D
70
IREF/GPIO3E
71
CHGVADJ /GPIO3F
72
ENBKL/GPIO40
73
PECI_KB930/GPIO41
74
GPIO42
75
IMON/GPIO43
76
EC_SMB_CK1/GPIO44
77
EC_SMB_DA1/GPIO45
78
EC_SMB_CK2/GPIO46
79
EC_SMB_DA2/GPIO47
80
KSO16/GPIO48
81
KSO17/GPIO49
82
EC_MUTE#/GPIO4A
83
USB_EN#/GPIO4B
84
CAP_INT#/GPIO4C
85
EAPD/GPIO4D
86
TP_CLK/GPIO4E
87
TP_DATA/GPIO4F
88
FSTCHG/GPIO50
89
BATT_CHG_LED#/GPIO52
90
CAPS_LED#/GPIO53
91
PWR_LED#/GPIO54
92
BATT_LOW_LED#/GPIO55
93
G
N
D
/
G
N
D
9
4
SYSON/GPIO56
95
E
C
_
V
D
D
/
V
C
C
9
6
CPU1.5V_S3_GATE/GPXIOA00
97
WOL_EN/GPXIOA01
98
HDA_SDO/GPXIOA02
99
EC_RSMRST#/GPXIOA03
100
EC_LID_OUT#/GPXIOA04
101
PROCHOT_IN/GPXIOA05
102
H_PROCHOT#_EC/GPXIOA06
103
VCOUT0_PH/GPXIOA07
104
BKOFF#/GPXIOA08
105
PBTN_OUT#/GPXIOA09
106
PCH_APWROK/GPXIOA10
107
SA_PGOOD/GPXIOA11
108
VCIN0_PH/GPXIOD00
109
AC_IN/GPXIOD01
110
E
C
_
V
D
D
0
1
1
1
EC_ON/GPXIOD02
112
G
N
D
0
1
1
3
ON/OFF/GPXIOD03
114
LID_SW#/GPXIOD04
115
SUSP#/GPXIOD05
116
GPXIOD06
117
PECI_KB9012/GPXIOD07
118
SPIDI/GPIO5B
119
SPIDO/GPIO5C
120
VR_ON/GPIO57
121
XCLKI/GPIO5D
122
XCLKO/GPIO5E
123
V18R
124
E
C
_
V
D
D
/
V
C
C
1
2
5
SPICLK/GPIO58
126
PM_SLP_S4#/GPIO59
127
SPICS#/GPIO5A
128
R360 2.2K_0402_5% R360 2.2K_0402_5% 1 2 R2132 0_0402_5% R2132 0_0402_5% 1 2
R891
0_0402_5%
@R891
0_0402_5%
@
1 2
C723
15P_0402_50V8J
@
C723
15P_0402_50V8J
@
1
2
R682 1K_0402_5% R682 1K_0402_5% 1 2

1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
KSI1
KSI6
KSI5
KSI7
KSO1
KSO0
KSO2
KSO4
KSO3
KSO5
KSO6
KSO7
KSO8
KSO12
KSO10
KSO13
KSO11
KSO9
KSO15
KSO14
KSI2
KSI0
KSI3
KSI4
KSO16
KSO17
PWR_SUSP_LED#
PWR_LED#
KSO16
KSO17
KSI3
KSO8
KSI2
KSO9
KSO14
KSO15
KSO13
KSO12
KSI0
KSO10
KSI1
KSO11
KSI6
KSI7
KSI5
KSO0
KSO5
KSO7
KSO4
KSO6
KSO3
KSI4
KSO2
KSO1
KSO[0..17]
KSI[0..7]
RIGHT_BTN# LEFT_BTN#
LEFT_BTN#
RIGHT_BTN#
TP_VDD
TP_DATA
TP_CLK
RIGHT_BTN#
LEFT_BTN#
EC_ON
51ON#
MEDIA_LED#
LID_SW#
PWR_LED#
ON/OFFBTN#
MEDIA_LED#
WLAN_LED#
BATT_GRN_LED#
BATT_AMB_LED#
PWR_LED#
ON/OFFBTN#
D_CK_SCLK
TP_VDD
TP_VDD
D_CK_SDATA
D_CK_SCLK
TP_VDD
LEFT_BTN#
RIGHT_BTN#
KSO[0..17] <40>
KSI[0..7] <40>
TP_DATA <40>
TP_CLK <40>
EC_ON <40,48>
51ON# <45>
ON/OFF <40>
PCH_SATALED# <13>
CR_5IN1_LED# <35>
PWR_SUSP_LED# <40>
LID_SW# <40>
WLAN_LED# <40>
BATT_AMB_LED# <40>
BATT_BLUE_LED# <40>
PWR_LED <40>
D_CK_SCLK <11,12,14>
D_CK_SDATA <11,12,14>
+3VALW
+5VALW
+5VS
+5VS
+3VALW
+3VS
+3VALW
+3VS
+5VS
+3VS
+5VALW
+3VS
+3VLP
+3VS
+3VS
+3VALW
+3VALW
+3VALW
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
PWR/B
ON/OFF BTN
TP Conn.
KB Conn.
EMI request
Test Only
Bottom Side
R03 modify
R04 modify
Delete SW5,SW6
R04 modify
R104
10K_0402_5%
930@
R104
10K_0402_5%
930@
1
2
R376 560_0402_5%
@
R376 560_0402_5%
@ 1 2
C256 100P_0402_50V8J C256 100P_0402_50V8J 1 2
C245 100P_0402_50V8J C245 100P_0402_50V8J 1 2
R379 560_0402_5%
@
R379 560_0402_5%
@ 1 2
C216
100P_0402_50V8J
@
C216
100P_0402_50V8J
@
1
2
C269 100P_0402_50V8J C269 100P_0402_50V8J 1 2
R380 680_0402_5%
@
R380 680_0402_5%
@ 1 2
C253 100P_0402_50V8J C253 100P_0402_50V8J 1 2
A
LED6
LTST-C191TBKT-CA_BLUE
A
LED6
2 1
R2117 51_0402_5% R2117 51_0402_5%
1 2
C265 100P_0402_50V8J C265 100P_0402_50V8J 1 2
C217
100P_0402_50V8J
@
C217
100P_0402_50V8J
@
1
2
C2104
56P_0402_50V8K
GM@
C2104
56P_0402_50V8K
GM@
1
2
C2107
56P_0402_50V8K
GM@
C2107
56P_0402_50V8K
GM@
1
2
R2099 0_0402_5% R2099 0_0402_5% 1 2
C258 100P_0402_50V8J C258 100P_0402_50V8J 1 2
C196
0.1U_0402_16V4Z

C196
0.1U_0402_16V4Z

1
2
R2119 51_0402_5% R2119 51_0402_5%
1 2
C255 100P_0402_50V8J C255 100P_0402_50V8J 1 2
G
D
S
Q32
SSM3K7002F_SC59-3
G
D
S
Q32
SSM3K7002F_SC59-3
2
1
3
G
D
S
Q7
SSM3K7002F_SC59-3
930@
G
D
S
Q7
SSM3K7002F_SC59-3
930@
2
1
3
R2121 390_0402_5% R2121 390_0402_5%
1 2
A
LED4
LTST-C191KFKT-2CA_ORANGE
A
LED4
2 1
C261 100P_0402_50V8J C261 100P_0402_50V8J 1 2
R2118 390_0402_5% R2118 390_0402_5%
1 2
C249 100P_0402_50V8J C249 100P_0402_50V8J 1 2
C260 100P_0402_50V8J C260 100P_0402_50V8J 1 2
C2101
56P_0402_50V8K
GM@ C2101
56P_0402_50V8K
GM@
1
2
C2106
56P_0402_50V8K
GM@
C2106
56P_0402_50V8K
GM@
1
2
U8
U8
B
2
A
1
Y
4
P
5
G
3
C250 100P_0402_50V8J C250 100P_0402_50V8J 1 2
R2116 130_0402_5% R2116 130_0402_5%
1 2
C257 100P_0402_50V8J C257 100P_0402_50V8J 1 2
C251 100P_0402_50V8J C251 100P_0402_50V8J 1 2
SW1
SMT1-05-A_4P
@SW1
SMT1-05-A_4P
@
3
2
1
4
5 6
SW2
SMT1-05-A_4P
SW2
SMT1-05-A_4P
3
2
1
4
56
R374 560_0402_5%
@
R374 560_0402_5%
@ 1 2
R378 390_0402_5% R378 390_0402_5%
1 2
C2102
56P_0402_50V8K
GM@
C2102
56P_0402_50V8K
GM@
1
2
C270 100P_0402_50V8J C270 100P_0402_50V8J 1 2
C2105
56P_0402_50V8K
GM@
C2105
56P_0402_50V8K
GM@
1
2
R2100 0_0402_5% @ R2100 0_0402_5% @
1 2
C263 100P_0402_50V8J C263 100P_0402_50V8J 1 2
SW3
SMT1-05-A_4P
SW3
SMT1-05-A_4P
3
2
1
4
56
R377 390_0402_5%
@
R377 390_0402_5%
@ 1 2
C254 100P_0402_50V8J C254 100P_0402_50V8J 1 2
C246 100P_0402_50V8J C246 100P_0402_50V8J 1 2
C259 100P_0402_50V8J C259 100P_0402_50V8J 1 2
R907
100K_0402_5%
9012@
R907
100K_0402_5%
9012@
1
2
R496
10K_0402_5%
R496
10K_0402_5%
1
2
D4
AZ5125-02S
@
D4
AZ5125-02S
@
23
1
C262 100P_0402_50V8J C262 100P_0402_50V8J 1 2
J KB1
ACES_85201-26051
CONN@
J KB1
ACES_85201-26051
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
G1
27
G2
28
C264 100P_0402_50V8J C264 100P_0402_50V8J 1 2
A
LED7
A
LED7
2 1
D3
AZ5125-02S
@
D3
AZ5125-02S
@
23
1
C248 100P_0402_50V8J C248 100P_0402_50V8J 1 2
R144
100K_0402_5%
930@
R144
100K_0402_5%
930@
1
2
J TP1
ACES_85201-0805N
CONN@
J TP1
ACES_85201-0805N
CONN@
GND
9
GND
10
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
C268 100P_0402_50V8J C268 100P_0402_50V8J 1 2
D6
CHN202UPT_SC70-3

D6
CHN202UPT_SC70-3

1
2
3
C2103
56P_0402_50V8K
GM@
C2103
56P_0402_50V8K
GM@
1
2
R512
100K_0402_5%

R512
100K_0402_5%

1
2
A
LED5
A
LED5
2 1
C266 100P_0402_50V8J C266 100P_0402_50V8J 1 2
C247 100P_0402_50V8J C247 100P_0402_50V8J 1 2
A
LED3
A
LED3
2 1
J PWR1
ACES_85201-0805N
CONN@
J PWR1
ACES_85201-0805N
CONN@
GND
9
GND
10
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
C252 100P_0402_50V8J C252 100P_0402_50V8J 1 2
C267 100P_0402_50V8J C267 100P_0402_50V8J 1 2
A
LED1
A
LED1
2 1
A
LED2
A
LED2
2 1

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MONO_IN
CODEC_VREF
SENSE_B
MONO_IN
MIC1_C_L
HDA_SDIN0_AUDIO
MIC1_C_R
EAPD_R
MIC1_R
MIC1_L
SENSE_A
+3VS_DVDD
+PVDD1_HDA
SPKR+
SPKR-
SPKL-
SPKL+
HP_LEFT
HP_RIGHT
HP_PLUG#
MIC_PLUG#
MIC2J D
+PVDD_HDA
MIC2_C_R
COM_MIC_R
MIC2_C_L
COM_MIC
LINE2_C_R
LINE2_C_L INT_MIC_R
SPK_R-
SPKR+
SPKR-
SPK_R+
SPK_L+
SPK_L- SPKL-
SPKL+
EAPD_R
COM_MIC
MIC2J D
INT_MIC
BEEP# <40>
PCH_SPKR <13>
HDA_SYNC_AUDIO <13>
HDA_SDOUT_AUDIO <13>
HDA_RST_AUDIO# <13>
HDA_BITCLK_AUDIO <13>
HDA_SDIN0 <13>
EC_MUTE# <40>
EAPD <40>
INT_MIC_R <43>
MIC1_L <43>
MIC1_R <43>
MIC_PLUG# <43>
HP_PLUG# <43>
HP_LEFT <43>
HP_RIGHT <43>
COM_MIC <43>
+VDDA
+3VS
+VDDA
+VDDA
+3VS
+MIC2_VREFO
+VDDA
+MIC1_VREFO
+INTMIC_VREFO
+5VS
+VDDA
+AVDD_HDA
+PVDD_HDA
+MIC2_VREFO
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
4.75V
(output =300 mA)
60mil 40mil
External MIC
Place next pin27
Place near Pin1, 9
For EMI
DGND
10mil
10mil
HD Audio Codec
10mil
AGND
10mil
Place near Pin25, 38
20mil
Place near Pin39
Int. Speaker Conn.
Combo MIC
External MIC
Internal MIC
GNDA GND GND GNDA
Place near Pin46
20mil
35mA
68mA 600mA
SM010014520 3000ma 220ohm@100mhz DCR 0.04
SM010030010 200ma 120ohm@100mhz DCR 0.2
SM010030010 200ma 120ohm@100mhz DCR 0.2
SM010014520 3000ma 220ohm@100mhz DCR 0.04
Combo MIC
Internal MIC
10mil
10mil
10mil
20mil
20mil
R03 modify

R02 modify for ESD
R02 Modify
R02 Modify
R02 Modify
R02 Modify
R02 Modify
R713
0_0603_5%
R713
0_0603_5%
1
2
C757
22P_0402_50V8J
@
C757
22P_0402_50V8J
@
1 2
C760 10U_0603_6.3V6M C760 10U_0603_6.3V6M
1 2
R711 0_0805_5% R711 0_0805_5%
1 2
C739 1U_0402_6.3V6K C739 1U_0402_6.3V6K
1 2
L51
BLM18AG121SN1D_0603
L51
BLM18AG121SN1D_0603
1 2
L2006 FBMA-L11-160808-800LMT_0603 L2006 FBMA-L11-160808-800LMT_0603 1 2
R724
560_0402_5%
R724
560_0402_5%
1 2
C772
0.1U_0402_16V4Z
C772
0.1U_0402_16V4Z
1
2
R791
22K_0402_5%
R791
22K_0402_5%
1
2
U41
ALC271X-VB6-CG_QFN48_6X6
U41
ALC271X-VB6-CG_QFN48_6X6
LINE2_L
14
LINE2_R
15
MIC2_R
17
MIC2_L
16
LINE1_L
23
LINE1_R
24
MIC1_L
21
MIC1_R
22
MIC2_VREFO
29
MIC1_VREFO_L
31
MIC1_VREFO_R
30
SENSE A
13
PCBEEP
12
SPK_OUT_L+
40
SPK_OUT_L-
41
MONO_OUT
20
RESET#
11
SYNC
10
BCLK
6
SDATA_OUT
5
SDATA_IN
8
GPIO0/DMIC_DATA
2
GPIO1/DMIC_CLK
3
CBP
36
CBN
35
VREF
27
D
V
D
D
1
D
V
D
D
_
I
O
9
A
V
D
D
1
2
5
A
V
D
D
2
3
8
HPOUT_L
32
EAPD
47
SPDIFO
48
P
V
D
D
2
4
6
DVSS
7
CPVEE
34
HPOUT_R
33
SENSE B
18
LDD_CAP
28
PD#
4
J DREF
19
AVSS1
26
AVSS2
37
SPK_OUT_R+
45
SPK_OUT_R-
44
P
V
D
D
1
3
9
PVSS1
42
PVSS2
43
GND
49
C750
10U_0603_6.3V6M
C750
10U_0603_6.3V6M
1
2
R726 1K_0402_5% R726 1K_0402_5%
1 2
R728
10K_0402_5%
R728
10K_0402_5%
1
2
R2057
0_0402_5%
@
R2057
0_0402_5%
@
1
2
R718 20K_0402_1% 271X@ R718 20K_0402_1% 271X@ 1 2
R2056 0_0402_5% 281X@ R2056 0_0402_5% 281X@ 1 2
D30
D30
2
1
C763
4.7U_0603_6.3V6K
C763
4.7U_0603_6.3V6K
1 2
L46
FBMA-L11-201209-221LMA30T_0805
@
L46
FBMA-L11-201209-221LMA30T_0805
@
1 2
J SPK2
ACES_88266-02001
CONN@
J SPK2
ACES_88266-02001
CONN@
1
1
2
2
G2
4
G1
3
C767 0.1U_0402_16V4Z C767 0.1U_0402_16V4Z 1 2
C764
4.7U_0603_6.3V6K
C764
4.7U_0603_6.3V6K
1 2
C752
0.1U_0402_16V4Z
C752
0.1U_0402_16V4Z
1
2
D2
AZ5125-02S
D2
AZ5125-02S
23
1
PJ 26
J UMP_43X39 @
PJ 26
J UMP_43X39 @
1
1
2
2
C753
10U_0603_6.3V6M
C753
10U_0603_6.3V6M
1
2
C759
1U_0402_6.3V6K
C759
1U_0402_6.3V6K
1 2
J SPK1
ACES_88266-02001
CONN@
J SPK1
ACES_88266-02001
CONN@
1
1
2
2
G2
4
G1
3
R720
22K_0402_5%
R720
22K_0402_5%
1 2
C765
4.7U_0603_6.3V6K
C765
4.7U_0603_6.3V6K
1 2
U40
G9191-475T1U_SOT23-5
@
U40
G9191-475T1U_SOT23-5
@
IN
1
GND
2
SHDN
3
OUT
5
BYP
4
C737
0.1U_0402_16V4Z
C737
0.1U_0402_16V4Z
1
2
R729
2.4K_0402_1%
R729
2.4K_0402_1%
1 2
PJ 25
J UMP_43X39 @
PJ 25
J UMP_43X39 @
1
1
2
2
C746
10U_0603_6.3V6M
C746
10U_0603_6.3V6M
1
2
C762
4.7U_0603_6.3V6K
C762
4.7U_0603_6.3V6K
1 2
C754
0.1U_0402_16V4Z
C754
0.1U_0402_16V4Z
1
2
R723
560_0402_5%
R723
560_0402_5%
1 2
R722
2.2K_0402_5%
R722
2.2K_0402_5%
1
2
C758
2.2U_0402_6.3V6M
C758
2.2U_0402_6.3V6M 1 2
C745
10U_0603_6.3V6M
@
C745
10U_0603_6.3V6M
@
1
2
G
D
S
Q43
BSS138_NL_SOT23-3
271X@
G
D
S
Q43
BSS138_NL_SOT23-3
271X@ 2
1
3
C2054 1000P_0402_50V7K C2054 1000P_0402_50V7K
1 2
D1
AZ5125-02S
D1
AZ5125-02S
23
1
D29
D29
2
1
R731 39.2K_0402_1% R731 39.2K_0402_1%
1 2
PJ 21
J UMP_43X39 @
PJ 21
J UMP_43X39 @
1
1
2
2
R727 20K_0402_1% R727 20K_0402_1%
1 2
C761
0.1U_0402_16V4Z
C761
0.1U_0402_16V4Z
1
2
C755
2.2U_0402_6.3V6M
C755
2.2U_0402_6.3V6M
1
2
R715 0_0402_5% 271X@ R715 0_0402_5% 271X@ 1 2
R721
33_0402_5%
R721
33_0402_5%
1 2
R730 20K_0402_1% R730 20K_0402_1%
1 2
R719 1K_0402_5% R719 1K_0402_5%
1 2
PJ 22
J UMP_43X39 @
PJ 22
J UMP_43X39 @
1
1
2
2
C768 10U_0603_6.3V6M
@
C768 10U_0603_6.3V6M
@
1 2
C769
4.7U_0603_6.3V6K
C769
4.7U_0603_6.3V6K
1 2
C749
0.1U_0402_16V4Z
C749
0.1U_0402_16V4Z
1
2
C
B
E
Q44
2SC2411K_SOT23-3
C
B
E
Q44
2SC2411K_SOT23-3
1
2
3
C741
0.01U_0402_16V7K
@
C741
0.01U_0402_16V7K
@
1 2
C756
10U_0603_6.3V6M
C756
10U_0603_6.3V6M
1
2
PJ 24
J UMP_43X39 @
PJ 24
J UMP_43X39 @
1
1
2
2
C2073 0.1U_0402_16V4Z C2073 0.1U_0402_16V4Z 1 2
R725
10K_0402_5%
R725
10K_0402_5%
1
2
PJ 23
J UMP_43X39 @
PJ 23
J UMP_43X39 @
1
1
2
2
C771
1U_0402_6.3V6K
C771
1U_0402_6.3V6K
1 2
C766
1U_0402_6.3V6K
C766
1U_0402_6.3V6K
1 2
R717 0_0402_5%
@
R717 0_0402_5%
@ 1 2
R712
10K_0402_5%
R712
10K_0402_5%
1
2
L48
BLM18AG121SN1D_0603
L48
BLM18AG121SN1D_0603
1 2
C770
4.7U_0603_6.3V6K
C770
4.7U_0603_6.3V6K
1 2
C748
0.1U_0402_16V4Z
C748
0.1U_0402_16V4Z
1
2
L50
FBMA-L11-201209-221LMA30T_0805
L50
FBMA-L11-201209-221LMA30T_0805
1 2

+VCC_FAN1
+VCC_FAN1
INT_MIC_L INT_MIC_R
INT_MIC_L
HP_PLUG#
MIC_PLUG#
MIC_PLUG#
MIC1_R_R
MIC1_L_R MIC1_L
MIC1_R
MIC1_L_1
MIC1_R_1
COM_MIC
HPOUT_L_2
HPOUT_R_2
HP_PLUG#
HP_LEFT
HP_RIGHT HPOUT_R_1
HPOUT_L_1
COM_MIC
FAN_SPEED1 <40>
EN_DFAN1 <40>
MIC1_L <42>
MIC1_R <42>
HP_LEFT <42>
HP_RIGHT <42>
HP_PLUG# <42>
MIC_PLUG# <42>
COM_MIC <42>
INT_MIC_R <42>
+5VS
+3VS
+INTMIC_VREFO
+MIC1_VREFO
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
FAN1 Conn
40mil
FAN Stand-Off JUSB3 Stand-Off
15mil
For EMI
Int. MIC
15mil
SM010004010 300ma 70ohm@100mhz DCR 0.3
MIC JACK
Singatron 2SJ2326
DC021007151
Headphone Out
R02 Modify
R02 Modify
R02 Modify
R03 modify
U30
APL5607KI-TRG_SO8
U30
APL5607KI-TRG_SO8
EN
1
VIN
2
VOUT
3
VSET
4
GND
8
GND
7
GND
6
GND
5
C598
0.1U_0402_16V4Z
C598
0.1U_0402_16V4Z
1
2
J MIC2
ACES_88266-02001
CONN@
J MIC2
ACES_88266-02001
CONN@
1
1
2
2
G2
4
G1
3
H20
H_4P0
@
H20
H_4P0
@
1
C733
220P_0402_50V7K
C733
220P_0402_50V7K
1
2
H15
H_3P0
@
H15
H_3P0
@
1
H24
H_4P2
@
H24
H_4P2
@
1
L24
FBMA-L11-160808-800LMT_0603
L24
FBMA-L11-160808-800LMT_0603
1 2
D25
AZ5125-02S
D25
AZ5125-02S
23
1
H22
H_4P2
@
H22
H_4P2
@
1
H26
H_3P0N
@
H26
H_3P0N
@
1
R705
4.7K_0402_5%
R705
4.7K_0402_5%
1
2
H3
H_3P4
@
H3
H_3P4
@
1
C500
220P_0402_50V7K
C500
220P_0402_50V7K
1
2
H1
H_3P4
@
H1
H_3P4
@
1
C747
330P_0402_50V7K
C747
330P_0402_50V7K
1
2
D28
AZ5125-02S
D28
AZ5125-02S
2 3
1
FD4
@
FIDUCIAL_C40M80
FD4
@
FIDUCIAL_C40M80
1
L45
FBMA-L11-160808-800LMT_0603
L45
FBMA-L11-160808-800LMT_0603
1 2
J FAN1
ACES_85205-03001
CONN@
J FAN1
ACES_85205-03001
CONN@
1
2
3
D16
AZ5125-02S
@
D16
AZ5125-02S
@
23
1
R714 47_0603_1% R714 47_0603_1% 1 2
H14
H_3P0
@
H14
H_3P0
@
1
H23
H_4P2
@
H23
H_4P2
@
1
R716 47_0603_1% R716 47_0603_1% 1 2
C585
10U_0603_6.3V6M
C585
10U_0603_6.3V6M
1 2
FD3
@
FIDUCIAL_C40M80
FD3
@
FIDUCIAL_C40M80
1
D1001
AZ5125-02S
D1001
AZ5125-02S
23
1
J MIC1
SINGA_2SJ -A960-C01
CONN@
J MIC1
SINGA_2SJ -A960-C01
CONN@
1
2
3
4
5
6
H25
H_7P0N
@
H25
H_7P0N
@
1
C579
1000P_0402_50V7K
C579
1000P_0402_50V7K
1
2
C587
1000P_0402_50V7K
C587
1000P_0402_50V7K
1 2
J HP1
SINGA_2SJ 2326-001111
CONN@
J HP1
SINGA_2SJ 2326-001111
CONN@
1
6
3
4
2
5
H17
H_3P5
@
H17
H_3P5
@
1
D26
D26
2
1
H13
H_3P0
@
H13
H_3P0
@
1
L44
FBMA-L11-160808-800LMT_0603
L44
FBMA-L11-160808-800LMT_0603
1 2
C751
330P_0402_50V7K
C751
330P_0402_50V7K
1
2
H11
H_3P0
@
H11
H_3P0
@
1
H9
H_3P0
@
H9
H_3P0
@
1
C732
220P_0402_50V7K
C732
220P_0402_50V7K
1
2
R509 300_0402_5% R509 300_0402_5%
1 2
H19
H_4P0
@
H19
H_4P0
@
1
FD1
@
FIDUCIAL_C40M80
FD1
@
FIDUCIAL_C40M80
1
H8
H_3P0
@
H8
H_3P0
@
1
R708
4.7K_0402_5%
R708
4.7K_0402_5%
1
2
L47
FBMA-L11-160808-800LMT_0603
L47
FBMA-L11-160808-800LMT_0603
1 2
C580 10U_0603_6.3V6M C580 10U_0603_6.3V6M
1 2
H2
H_3P4
@
H2
H_3P4
@
1
FD2
@
FIDUCIAL_C40M80
FD2
@
FIDUCIAL_C40M80
1
R706 1K_0603_5% R706 1K_0603_5%
1 2
L49
FBMA-L11-160808-800LMT_0603
L49
FBMA-L11-160808-800LMT_0603
1 2
R489
10K_0402_5%
R489
10K_0402_5%
1
2
H21
H_4P2
@
H21
H_4P2
@
1
H7
H_3P4
@
H7
H_3P4
@
1
H16
H_3P0
@
H16
H_3P0
@
1
D27
D27
2
1
H28
H_3P5N
@
H28
H_3P5N
@
1
H27
H_3P5X3P0N
@
H27
H_3P5X3P0N
@
1
H12
H_3P0
@
H12
H_3P0
@
1
R394
10K_0402_5%
R394
10K_0402_5%
1
2
H10
H_3P0
@
H10
H_3P0
@
1
H18
H_3P0
@
H18
H_3P0
@
1
R707 1K_0603_5% R707 1K_0603_5%
1 2

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SUSP
3VS_GATE
SUSP
5VS_GATE
SUSP
SUSP
SUSP
SYSON
SYSON# SUSP SUSP SUSP
3VS_ON
5VS_ON
SUSP#
ACIN
1.5VS_GATE
SUSP
SUSP
ACIN
1.5VSDGPU_GATE
VGA_ON#
3V_GATE
PCH_PWR_EN#
PCH_PWR_EN#
PCH_PWR_EN#
VGA_PWROK#
VGA_PWROK#
VGA_PWROK#
VGA_ON#
VGA_ON#
SUSP# <37,40,47,49,50>
SYSON <40,49>
SYSON# <39>
ACIN <15,40,47,48>
ACIN <15,40,47,48>
VGA_ON <14,17,25,51,53>
PCH_PWR_EN <40>
PCH_PWR_EN# <20,35>
SUSP <49>
VGA_ON# <51>
VGA_PWROK <51,53>
VGA_PWROK# <51>
+5VALW
+3VS
+VSB
+5VS
+1.8VS +1.5V +0.75VS
+VSB
+1.05VS_VTT
+3VALW
+5VALW
+5VALW
+5VALW
+3VALW +3VS
+5VALW
+5VS
+1.5V
+VSB
+1.5VS
+VSB
+1.5VSDGPU +1.5VSDGPUH
+1.5V +1.5VSDGPUH +5VALW
+3VALW
+VSB
+3VALW_PCH
+5VALW
+5VS +5VALW +3VALW
+3VALW
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
+5VALW TO +5VS
20mil
20mil
10mil
10mil
+3VALW TO +3VS

Reserved
20mil 10mil
+1.5V to +1.5VS
+1.5VSDGPUH to +1.5VSDGPU for GPU
10mil
20mil
Use 100k to make sure the
divided voltage is enough!!
+3VALW TO +3VALW(PCH AUX Power)
R02 Modify
R02 Modify
R02 Modify
20mil 10mil
40mil
Modify R03
Modify R02
R02 modify for EMI
R04 modify
R04 modify
R04 modify
R04 modify
R04 modify
Modify R05
U22
DMN3030LSS-13_SOP8L-8
U22
3 6
5
7
8
2
4
1
C
4
6
4
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
6
4
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
J 11 @
J UMP_43X79
J 11 @
J UMP_43X79
1
1
2
2
C
3
3
9
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
3
3
9
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
+
C
8
2
6
3
3
0
U
_
B
2
_
2
.
5
V
M
_
R
1
5
M
@
+
C
8
2
6
3
3
0
U
_
B
2
_
2
.
5
V
M
_
R
1
5
M
@
1
2
C822
.1U_0402_16V7K
C822
.1U_0402_16V7K
1
2
Q2003A
Q2003A
1
2
6
C
4
5
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
5
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
R135
100K_0402_5%
DIS@
R135
100K_0402_5%
DIS@
1
2
C
3
3
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
3
3
8
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
1
5
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
@ C
1
5
7
1
U
_
0
4
0
2
_
6
.
3
V
6
K
@
1
2
G
D
S
Q2004
2N7002E_SOT23-3
G
D
S
Q2004
2N7002E_SOT23-3 2
1
3
C821
1U_0402_6.3V6K
C821
1U_0402_6.3V6K
1
2
R508
470_0603_5%
R508
470_0603_5%
1
2
C29
0.1U_0603_25V7K
@
C29
0.1U_0603_25V7K
@
1
2
C
2
0
5
8
1
U
_
0
6
0
3
_
1
0
V
6
K
C
2
0
5
8
1
U
_
0
6
0
3
_
1
0
V
6
K
1
2
PJ 28
J UMP_43X118
@ PJ 28
J UMP_43X118
@
1
1
2
2
G
D
S
Q23
SSM3K7002F_SC59-3
G
D
S
Q23
SSM3K7002F_SC59-3
2
1
3
C463
0.1U_0603_25V7K
C463
0.1U_0603_25V7K
1
2
C
4
6
1
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
6
1
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
R926
20K_0402_1% @
R926
20K_0402_1% @
1 2
R2075
100K_0402_5%
R2075
100K_0402_5%
1
2
C
2
0
8
2
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
2
0
8
2
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
C
4
6
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
C
4
6
9
1
U
_
0
4
0
2
_
6
.
3
V
6
K
1
2
C
3
7
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
3
7
7
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
2
0
5
7
1
0
U
_
0
8
0
5
_
1
0
V
4
Z
C
2
0
5
7
1
0
U
_
0
8
0
5
_
1
0
V
4
Z
1
2
C2056
10U_0805_10V4Z
C2056
10U_0805_10V4Z
1
2
C
7
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
@ C
7
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
@
1
2
C
8
2
3
.
1
U
_
0
4
0
2
_
1
6
V
7
K
@ C
8
2
3
.
1
U
_
0
4
0
2
_
1
6
V
7
K
@
1
2
R369
150_0603_5%
R369
150_0603_5%
1
2
G
S
D
Q19B
G
S
D
Q19B
6
1
2
C
4
6
5
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
6
5
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
C
2
0
8
1
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
2
0
8
1
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
G
S
D
Q27B
G
S
D
Q27B
6
1
2
G
D
S
Q34
SSM3K7002F_SC59-3
G
D
S
Q34
SSM3K7002F_SC59-3
2
1
3
S
G
D
Q27A
DMN66D0LDW-7_SOT363-6 S
G
D
Q27A
5
3
4
+
C
5
1
4
3
3
0
U
_
2
.
5
V
_
M
_
R
1
5
@
+
C
5
1
4
3
3
0
U
_
2
.
5
V
_
M
_
R
1
5
@
1
2
R246
100K_0402_5%
R246
100K_0402_5%
1
2
C
8
1
9
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
@ C
8
1
9
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
@
1
2
C
3
7
5
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
3
7
5
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
C
3
7
4
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
3
7
4
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
R
2
6
8
5
1
0
K
_
0
4
0
2
_
5
%
@ R
2
6
8
5
1
0
K
_
0
4
0
2
_
5
%
@
1
2
G
D
S
Q8
SSM3K7002F_SC59-3
DIS@
G
D
S
Q8
SSM3K7002F_SC59-3
DIS@
2
1
3
C
2
0
8
4
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
2
0
8
4
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
S
G
D
Q19A
S
G
D
Q19A
5
3
4
R365
470_0603_5%
@R365
470_0603_5%
@
1
2
C
2
0
8
0
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
2
0
8
0
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
C
4
6
0
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
6
0
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
U2006
SI4178DY-T1-GE3_SO8
U2006
SI4178DY-T1-GE3_SO8
3
5
2
4
1
6
7
8
R373
100K_0402_5%
R373
100K_0402_5%
1
2
U12
AO4430L_SO8
U12
AO4430L_SO8
6
2
4
1
3
5
7
8
R134
100K_0402_5%
DIS@
R134
100K_0402_5%
DIS@
1
2
C
1
5
6
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
@ C
1
5
6
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
@
1
2
R2107
0_0402_5%
@ R2107
0_0402_5%
@ 1 2
G
S
D
Q15B
G
S
D
Q15B
6
1
2
R29
470_0603_5%
R29
470_0603_5%
1
2
C953
330P_0402_50V7K @
C953
330P_0402_50V7K @1 2
G
D
S
Q24
SSM3K7002F_SC59-3
@
G
D
S
Q24
SSM3K7002F_SC59-3
@
2
1
3
R383
100K_0402_5%
R383
100K_0402_5%
1
2
U21
U21
3 6
5
7
8
2
4
1
R2106
0_0402_5%
@ R2106
0_0402_5%
@
1 2
C2059
0.1U_0603_25V7K
C2059
0.1U_0603_25V7K
1
2
C954
330P_0402_50V7K @
C954
330P_0402_50V7K @
1 2
R372
20K_0402_1%
R372
20K_0402_1%
1 2
Q3A
@
Q3A
@
6
1
2
Q2003B
Q2003B
4
5
3
R251
10K_0402_5%
R251
10K_0402_5%
1
2
C
8
1
8
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
@ C
8
1
8
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
@
1
2
C
4
5
9
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
5
9
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
G
S
D
Q25B
G
S
D
Q25B
6
1
2
R2076
100K_0402_5%
R2076
100K_0402_5%
1
2
R368
47K_0402_5%
R368
47K_0402_5%
1 2
R269
200K_0402_5%
R269
200K_0402_5%
1 2
R2105
0_0402_5%
@R2105
0_0402_5%
@
1 2
G
D
S
Q5
SSM3K7002F_SC59-3
G
D
S
Q5
SSM3K7002F_SC59-3
2
1
3
R2073
470_0603_5%
R2073
470_0603_5%
1
2
C
2
0
7
9
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
2
0
7
9
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
R245
470_0603_5%
R245
470_0603_5%
1
2
S
G
D
Q25A
S
G
D
Q25A
5
3
4
R27
510K_0402_5%
@
R27
510K_0402_5%
@ 1 2
R927
47K_0402_5%
@
R927
47K_0402_5%
@
1 2
R2103
100K_0402_5%
R2103
100K_0402_5%
1
2
C952
0.1U_0402_16V4Z
@
C952
0.1U_0402_16V4Z
@ 1 2
C470
0.1U_0603_25V7K
C470
0.1U_0603_25V7K
1
2
R2104
0_0402_5%
@ R2104
0_0402_5%
@
1 2
G
D
S
Q21
SSM3K7002F_SC59-3
@ G
D
S
Q21
SSM3K7002F_SC59-3
@
2
1
3
C
3
7
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
C
3
7
6
0
.
1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
G
D
S
Q4
SSM3K7002F_SC59-3
@
G
D
S
Q4
SSM3K7002F_SC59-3
@
2
1
3
R2074 200K_0402_5% R2074 200K_0402_5% 1 2
R366
22_0603_5%
R366
22_0603_5%
1
2
C
4
6
8
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
C
4
6
8
4
.
7
U
_
0
6
0
3
_
6
.
3
V
6
K
1
2
TPS22966DPUR_SON14_2X3~D
U46
@ TPS22966DPUR_SON14_2X3~D
U46
@
GND
11
VIN2
6
VBIAS
4
ON2
5
VOUT2
9
VIN2
7
CT1
12
VOUT1
14
VOUT2
8
VOUT1
13
VIN1
2
ON1
3
VIN1
1
CT2
10
GPAD
15
U2
AO4430L_SO8
@
U2
AO4430L_SO8
@
6
2
4
1
3
5
7
8
G
D
S
Q2008
2N7002E_SOT23-3
G
D
S
Q2008
2N7002E_SOT23-3 2
1
3
C951
0.1U_0402_16V4Z
@
C951
0.1U_0402_16V4Z
@ 1 2
C
2
0
8
3
.
1
U
_
0
4
0
2
_
1
6
V
7
K
C
2
0
8
3
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
Q3B
@ Q3B
@
3
4
5
C380
0.1U_0603_25V7K
C380
0.1U_0603_25V7K
1
2
R26
47_0603_5%
@
R26
47_0603_5%
@
1
2
R382
470_0603_5%
R382
470_0603_5%
1
2
R
2
8
5
1
0
K
_
0
4
0
2
_
5
%
@
R
2
8
5
1
0
K
_
0
4
0
2
_
5
%
@
1
2
PJ 27
J UMP_43X118
@ PJ 27
J UMP_43X118
@
1
1
2
2
S
G
D
Q15A
S
G
D
Q15A
5
3
4
C
8
2
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
@ C
8
2
4
1
U
_
0
4
0
2
_
6
.
3
V
6
K
@
1
2

A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
N1
DC_IN_S2 DC_IN_S1
51ON# <41>
ACOFF <40>
+3VALWP +3VALW +5VALWP
+VSBP +VSB
+0.75VS +0.75VSP
+1.5V +1.5VP
+1.8VSP +1.8VS
+5VALW
VIN
VS
BATT+
+3VLP
+CHGRTC
+1.05VS_VCCPP +1.05VS_VTT
VIN
VIN
B+
Pre_CHG
+VCCSAP +VCCSA
+1.5VSDGPU +1.5VSDGPUP
+1.05VS_DGPUP
+5VALWP
+1.05VSDGPU
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02

4019ID
PC5
0.22U_0603_25V7K
930@ PC5
0.22U_0603_25V7K
930@
1
2
PJ 10
J UMP_43X39
@ PJ 10
J UMP_43X39
@
1
1
2
2
PR8
68_1206_5%
@PR8
68_1206_5%
@
1
2
PJ 2
J UMP_43X118
PJ 2
J UMP_43X118
1
1
2
2
P
R
5
1
0
0
K
_
0
4
0
2
_
5
%
P
R
5
1
0
0
K
_
0
4
0
2
_
5
%
1
2
PR3
1K_1206_5%
PR3
1K_1206_5%
1 2
PQ1
TP0610K-T1-E3_SOT23-3
PQ1
TP0610K-T1-E3_SOT23-3
2
1 3
PJ 5
J UMP_43X118
PJ 5
J UMP_43X118
1
1
2
2
PJ 8
J UMP_43X118
PJ 8
J UMP_43X118
1
1
2
2
PQ2
PDTC115EU_SOT323
PQ2
PDTC115EU_SOT323
2
1
3
PR4
1K_1206_5%
PR4
1K_1206_5%
1 2
PJ 1
J UMP_43X118
PJ 1
J UMP_43X118
1
1
2
2
PR2
1K_1206_5%
PR2
1K_1206_5%
1 2
PR1
1K_1206_5%
PR1
1K_1206_5%
1 2
PQ3
PDTC115EU_SOT323
PQ3
PDTC115EU_SOT323
2
1
3
PJ 7
J UMP_43X118
PJ 7
J UMP_43X118
1
1
2
2
PJ 3
J UMP_43X39
@ PJ 3
J UMP_43X39
@
1
1
2
2
PC6
0.1U_0603_25V7K
@PC6
0.1U_0603_25V7K
@
1
2
PJ 18
J UMP_43X118
PJ 18
J UMP_43X118
1
1
2
2
PC3
100P_0402_50V8J
PC3
100P_0402_50V8J
1
2
PJ 9
J UMP_43X79
@ PJ 9
J UMP_43X79
@
1
1
2
2
PC2
100P_0402_50V8J
PC2
100P_0402_50V8J
1
2
P
R
6
1
0
0
K
_
0
4
0
2
_
5
%
P
R
6
1
0
0
K
_
0
4
0
2
_
5
%
1
2
PR10
100K_0402_1%
930@ PR10
100K_0402_1%
930@
1
2
PD1
LL4148_LL34-2
PD1
LL4148_LL34-2
1 2 PC4
1000P_0402_50V7K
PC4
1000P_0402_50V7K
1
2
PC1
1000P_0402_50V7K
PC1
1000P_0402_50V7K
1
2
PJ 4
J UMP_43X118
PJ 4
J UMP_43X118
1
1
2
2
PR12
0_0402_5%
PR12
0_0402_5%
1 2
PJ 19
J UMP_43X118
PJ 19
J UMP_43X118
1
1
2
2
PL1
SMB3025500YA_2P
PL1
SMB3025500YA_2P
1 2
PJ 11
J UMP_43X118
PJ 11
J UMP_43X118
1
1
2
2
PD4
LL4148_LL34-2
930@ PD4
LL4148_LL34-2
930@
1 2
PD2
BAS40CW_SOT323-3
PD2
BAS40CW_SOT323-3
2
3
1
PQ4
TP0610K-T1-E3_SOT23-3
930@ PQ4
TP0610K-T1-E3_SOT23-3
930@
2
1 3
PJ 6
J UMP_43X79
@ PJ 6
J UMP_43X79
@
1
1
2
2
PJ P1
ACES_50305-00441-001
PJ P1
ACES_50305-00441-001
1
3
4
GND
GND
2
PR7
100K_0402_5%
PR7
100K_0402_5%
1
2
PR9
68_1206_5%
@PR9
68_1206_5%
@
1
2
PD3
LL4148_LL34-2
@ PD3
LL4148_LL34-2
@
1
2
PR11
22K_0402_1%
930@ PR11
22K_0402_1%
930@
1 2

A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
TH
EC_SMCA
EC_SMDA
PI
MAINPWON
MAINPWON
TH
H_PROCHOT#
BATT_S1
SPOK <48>
BATT_TEMP <40>
EC_SMB_CK1 <40,47>
EC_SMB_DA1 <40,47>
H_PROCHOT# <5,40>
ADP_I <40,47>
MAINPWON <40,48>
VCIN0_PH <40>
VCIN1_PROCHOT <40>
B+
+VSBP
VL
+3VALWP
BATT+
VMB
+3VLP
+3VLP
+3VALWP VL VS
VS
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
<45,47>
Recovery at 56 degree C
CPU thermal protection at 92 degree C
PH1 under CPU botten side :
For 65W adapter==>action 70W , Recovery 54W
For 90W adapter==>action 97W , Recovery 75W
4019ID
PR32 @
100K_0402_1%
PR32 @
100K_0402_1%
1
2
PR33
8.87K_0402_1%
90W@ PR33
8.87K_0402_1%
90W@
1
2
PU3
G718TM1U_SOT23-8
PU3
G718TM1U_SOT23-8
VCC
1
GND
2
~OT1
3
~OT2
4
RHYST2
5
TMSNS2
6
RHYST1
7
TMSNS1
8
PC17
1000P_0402_50V7K
9012@PC17
1000P_0402_50V7K
9012@
1
2
G
D
S
PQ5A
DMN66D0LDW-7_SOT363-6 G
D
S
PQ5A
2
6
1
PR36
16.2K_0402_1%
90W@ PR36
16.2K_0402_1%
90W@
1 2
PR21
1K_0402_1%
PR21
1K_0402_1%
1 2
PR19
1K_0402_5%
PR19
1K_0402_5%
1
2
PC9
0.01U_0402_25V7K
PC9
0.01U_0402_25V7K
1
2
PR13
10K_0402_1%
@ PR13
10K_0402_1%
@
1
2
PU1
G718TM1U_SOT23-8
@PU1
G718TM1U_SOT23-8
@
RHYST2
5
OT1
3
OT2
4
GND
2
VCC
1
TMSNS2
6
RHYST1
7
TMSNS1
8
PR26
100K_0402_1%
PR26
100K_0402_1%
1
2
PC15
1U_0402_6.3V6K
PC15
1U_0402_6.3V6K
1
2
P
H
1
1
0
0
K
_
0
4
0
2
_
1
%
_
N
C
P
1
5
W
F
1
0
4
F
0
3
R
C
P
H
1
1
0
0
K
_
0
4
0
2
_
1
%
_
N
C
P
1
5
W
F
1
0
4
F
0
3
R
C
1
2
PR34
1K_0402_5%
PR34
1K_0402_5%
1 2
PR24
1.5M_0402_5%
@ PR24
1.5M_0402_5%
@
1
2
PD5
LL4148_LL34-2
@ PD5
LL4148_LL34-2
@
1
2
PR35
9.53K_0402_1%
PR35
9.53K_0402_1%
1 2
PC8
1000P_0402_50V7K
PC8
1000P_0402_50V7K
1
2
PJ P2
SUYIN_200275GR008G13GZR
CONN@ PJ P2
SUYIN_200275GR008G13GZR
CONN@
1
1
3
3
4
4
5
5
6
6
8
8
2
2
7
7
GND
9
GND
10
PR18 @
47K_0402_1%
PR18 @
47K_0402_1%
1 2
G
D
S
PQ5B
D
S
PQ5B
5
3
4
PC14
0.1U_0603_25V7K
PC14
0.1U_0603_25V7K
1
2
G
D
S
PQ7
2N7002KW_SOT323-3
G
D
S
PQ7
2N7002KW_SOT323-3
2
1
3
PR28
100K_0402_1%
PR28
100K_0402_1%
1
2
PR38
10K_0402_1%
PR38
10K_0402_1%
1
2
PU2A
LM393DR_SO8
@ PU2A
LM393DR_SO8
@
+
3
-
2
O
1
P
8
G
4
PC10
0.022U_0402_16V7K
@ PC10
0.022U_0402_16V7K
@
1 2
PR102
0_0402_5%
PR102
0_0402_5%
1 2
PR22
47K_0402_1%
@ PR22
47K_0402_1%
@
1
2
PR14
10K_0402_1%
@ PR14
10K_0402_1%
@
1
2
PC7
0.1U_0603_25V7K
@ PC7
0.1U_0603_25V7K
@
1
2
PR36
10.5K_0402_1%
65W@ PR36
10.5K_0402_1%
65W@
PR20
6.49K_0402_1%
PR20
6.49K_0402_1%
1 2
PR17
100_0402_1%
PR17
100_0402_1%
1
2
PU2B
LM393DR_SO8
@ PU2B
LM393DR_SO8
@
+
5
-
6
O
7
P
8
G
4
PR16 @
100K_0402_1%
PR16 @
100K_0402_1%
1
2
PH2
100K_0402_1%_NCP15WF104F03RC
@PH2
100K_0402_1%_NCP15WF104F03RC
@
1
2
P
C
1
3
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
P
C
1
3
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
1
2
PQ6
TP0610K-T1-E3_SOT23-3
PQ6
TP0610K-T1-E3_SOT23-3
2
1 3
PC11
100P_0402_50V8J
@ PC11
100P_0402_50V8J
@
1
2
PR33
3.92K_0402_1%
65W@ PR33
3.92K_0402_1%
65W@
PR29
21K_0402_1%
PR29
21K_0402_1%
1
2
PR15
100_0402_1%
PR15
100_0402_1%
1
2
PR37
0_0402_5%
@ PR37
0_0402_5%
@
1 2
PL2
SMB3025500YA_2P
PL2
SMB3025500YA_2P
1 2
PR27
22K_0402_1%
PR27
22K_0402_1%
1 2
PR31
100K_0402_1%
PR31
100K_0402_1%
1
2
PR57
0_0402_5%
@ PR57
0_0402_5%
@
1 2
PR23
10K_0402_1%
@ PR23
10K_0402_1%
@
1
2
P
C
1
2
0
.
2
2
U
_
0
6
0
3
_
2
5
V
7
K
@
P
C
1
2
0
.
2
2
U
_
0
6
0
3
_
2
5
V
7
K
@
1
2
PR25
100K_0402_1%
@ PR25
100K_0402_1%
@
1
2

A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
BQ24725_ACDRV
B
Q
2
4
7
2
5
_
A
C
N
B
Q
2
4
7
2
5
_
A
C
P
BQ24725_BATDRV
BQ24725_BATDRV
BQ24725_CMSRC
B
Q
2
4
7
2
5
_
L
X
BQ24725_LX CHG
C
S
O
N
1
C
S
O
P
1
D
H
_
C
H
G
DH_CHG
DL_CHG
ACDET
B
Q
2
4
7
2
5
_
B
S
T
CSON1
CSOP1 SRP
SRN
DH_CHG-1
ADP_I <40,46>
EC_SMB_CK1 <40,46>
EC_SMB_DA1 <40,46>
ACIN <15,40,44,48>
SUSP# 7,40,44,49,50>
FSTCHG <40>
P2
+3VLP
P1 B+ VIN
+3VALW
VIN
BATT+
VIN
VIN
Pre_CHG
ACDET
CHG_B+
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
2011/06/02
63
2012/06/02
47
Custom
Friday, February 10, 2012
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
2011/06/02
63
2012/06/02
47
Custom
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
2011/06/02
63
2012/06/02
47
Custom
for reverse input protection
Close EC
Min. Typ Max.
L-->H 17.852V 18.063V 18.275V
H-->L 17.476V 17.687V 17.898V
Vin Dectector
ILIM and external DPM
Min. Typ Max.
3.906A 4.006A 4.108A
PC86
0.1U_0402_25V6
PC86
0.1U_0402_25V6
1
2
PR59
2M_0402_1%
PR59
2M_0402_1%
1
2
PC26
0.1U_0402_25V6
PC26
0.1U_0402_25V6
1 2
P
C
4
3
0
.
1
U
_
0
4
0
2
_
1
6
V
7
K
P
C
4
3
0
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
G
D
S
PQ15
2N7002KW_SOT323-3
G
D
S
PQ15
2N7002KW_SOT323-3
2
1
3
PR56
100K_0402_1%
PR56
100K_0402_1%
1 2
P
C
1
6
0
.
1
U
_
0
4
0
2
_
2
5
V
6
P
C
1
6
0
.
1
U
_
0
4
0
2
_
2
5
V
6
1
2
PC87
0.1U_0402_25V6
PC87
0.1U_0402_25V6
1
2
P
R
5
3
4
.
7
_
1
2
0
6
_
5
%
P
R
5
3
4
.
7
_
1
2
0
6
_
5
%
1
2
G
D
S
PQ8
SI1304BDL-T1-E3_SC70-3 G
D
S
PQ8
SI1304BDL-T1-E3_SC70-3
1
2
3
PC33
1U_0603_25V6K
PC33
1U_0603_25V6K
1 2
P
R
4
3
@
0
_
0
4
0
2
_
5
%
P
R
4
3
@
0
_
0
4
0
2
_
5
%
1
2
PR41
0.02_2512_1%
PR41
0.02_2512_1%
1
3
4
2
PQ9
AO4466L_SO8
PQ9
AO4466L_SO8
1
2
3
4
5
6
7
8
PR65
66.5K_0603_0.1%
PR65
66.5K_0603_0.1%
1
2
PR60
280K_0603_0.1%
PR60
280K_0603_0.1%
1 2
PD9
RB751V-40_SOD323-2
PD9
RB751V-40_SOD323-2
1
2
P
C
3
6
0
.
0
1
U
_
0
4
0
2
_
5
0
V
7
K
P
C
3
6
0
.
0
1
U
_
0
4
0
2
_
5
0
V
7
K
1
2
P
C
4
0
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
4
0
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
PC44
100P_0402_50V8J
PC44
100P_0402_50V8J
1 2
PC45
0.1U_0402_16V7K
@PC45
0.1U_0402_16V7K
@
1
2
P
C
3
8
0
.
1
U
_
0
4
0
2
_
2
5
V
6
P
C
3
8
0
.
1
U
_
0
4
0
2
_
2
5
V
6
1
2
P
R
6
1
1
0
0
K
_
0
4
0
2
_
1
%
P
R
6
1
1
0
0
K
_
0
4
0
2
_
1
%
1
2
PU4
BQ24725ARGRR_VQFN20_3P5X3P5
PU4
BQ24725ARGRR_VQFN20_3P5X3P5
ACN
1
ACP
2
CMSRC
3
ACDRV
4
ACOK
5
A
C
D
E
T
6
I
O
U
T
7
S
D
A
8
S
C
L
9
I
L
I
M
1
0
BATDRV
11
SRN
12
SRP
13
GND
14
LODRV
15
R
E
G
N
1
6
B
T
S
T
1
7
H
I
D
R
V
1
8
P
H
A
S
E
1
9
V
C
C
2
0
PAD
21
PD7
RB751V-40_SOD323-2
PD7
RB751V-40_SOD323-2
1
2
P
C
4
2
0
.
0
1
U
_
0
4
0
2
_
2
5
V
7
K
P
C
4
2
0
.
0
1
U
_
0
4
0
2
_
2
5
V
7
K
1
2
P
R
4
6
4
.
1
2
K
_
0
6
0
3
_
1
%
P
R
4
6
4
.
1
2
K
_
0
6
0
3
_
1
%
1
2
PR39
1M_0402_5%
PR39
1M_0402_5%
1 2
P
C
4
1
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
P
C
4
1
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
1
2
P
C
2
4
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
2
4
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
PR40
3M_0402_5%
PR40
3M_0402_5%
1 2
P
R
4
5
4
.
1
2
K
_
0
6
0
3
_
1
%
P
R
4
5
4
.
1
2
K
_
0
6
0
3
_
1
%
1
2
PR58
316K_0402_1%
PR58
316K_0402_1%
1 2
P
C
3
5
1
0
U
_
0
8
0
5
_
2
5
V
6
K
P
C
3
5
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
PL3
1.2UH_PNS40201R2YAF_3A_30%
PL3
1.2UH_PNS40201R2YAF_3A_30%
1 2
P
C
2
3
@
0
.
1
U
_
0
4
0
2
_
2
5
V
6
P
C
2
3
@
0
.
1
U
_
0
4
0
2
_
2
5
V
6
1
2
P
C
3
9
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
3
9
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
PR64
100K_0402_1%
PR64
100K_0402_1%
1 2
P
R
4
2
@
0
_
0
4
0
2
_
5
%
P
R
4
2
@
0
_
0
4
0
2
_
5
%
1
2
PR50
2.2_0402_5%
PR50
2.2_0402_5%
1 2
PQ12
SIS412DN-T1-GE3_POWERPAK8-5
PQ12
4
5
1 2 3
PR62
2M_0402_1%
PR62
2M_0402_1%
1
2
PC32
2.2U_0805_25V6K
@ PC32
2.2U_0805_25V6K
@
1
2
P
C
3
0
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
P
C
3
0
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
1
2
P
C
3
4
1
0
U
_
0
8
0
5
_
2
5
V
6
K
P
C
3
4
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
PR63
154K_0603_0.1%
PR63
154K_0603_0.1%
1
2
P
Q
1
3
S
I
S
4
1
2
D
N
-
T
1
-
G
E
3
_
P
O
W
E
R
P
A
K
8
-
5
P
Q
1
3
S
I
S
4
1
2
D
N
-
T
1
-
G
E
3
_
P
O
W
E
R
P
A
K
8
-
5
4
5
1 2 3
P
C
2
7
0
.
0
1
U
_
0
4
0
2
_
5
0
V
7
K
P
C
2
7
0
.
0
1
U
_
0
4
0
2
_
5
0
V
7
K
1
2
PR52
0.01_1206_1%
PR52
0.01_1206_1%
1
3
4
2
PD6
BAS40CW_SOT323-3
PD6
BAS40CW_SOT323-3
1
2 3
PR66
0_0402_5%
PR66
0_0402_5%
1 2
PQ11
AO4466L_SO8
PQ11
AO4466L_SO8
1
2
3
4
5
6
7
8
PQ10
AO4466L_SO8
PQ10
AO4466L_SO8
1
2
3
4
5
6
7
8
P
C
2
2
1
0
U
_
0
8
0
5
_
2
5
V
6
K
P
C
2
2
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
P
C
2
8
0
.
1
U
_
0
4
0
2
_
2
5
V
6
P
C
2
8
0
.
1
U
_
0
4
0
2
_
2
5
V
6
1
2
PR44
4.12K_0603_1%
PR44
4.12K_0603_1%
1 2
P
C
3
7
0
.
1
U
_
0
4
0
2
_
2
5
V
6
P
C
3
7
0
.
1
U
_
0
4
0
2
_
2
5
V
6
1
2
PL4
10UH_FDVE1040-H-100M=P3_6.5A_20%
PL4
10UH_FDVE1040-H-100M=P3_6.5A_20%
1 2
P
R
4
7
1
0
_
1
2
0
6
_
1
%
P
R
4
7
1
0
_
1
2
0
6
_
1
%
1
2
P
R
4
8
2
.
2
_
0
6
0
3
_
5
%
P
R
4
8
2
.
2
_
0
6
0
3
_
5
%
1
2
PC31
1U_0603_25V6K
PC31
1U_0603_25V6K
1 2
PR55
6.8_0603_5%
PR55
6.8_0603_5%
1 2
PR51
3.3_1210_5%
@ PR51
3.3_1210_5%
@
1
2
P
C
2
5
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
2
5
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
PC29
0.047U_0402_25V7K
PC29
0.047U_0402_25V7K
1 2
PR49
3.3_1210_5%
@ PR49
3.3_1210_5%
@
1
2
PQ14
PDTC115EUA_SC70-3
PQ14
PDTC115EUA_SC70-3
2
1
3
P
C
2
1
1
0
U
_
0
8
0
5
_
2
5
V
6
K
P
C
2
1
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
PR54
10_0603_5%
PR54
10_0603_5%
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ENTRIP1
BST_5V
LX_5V
RT8205_B+
UG_5V
BST_3V
E
N
T
R
I
P
2
LG_5V
E
N
T
R
I
P
1
ENTRIP2
RT8205_B+
LX_3V
UG_3V
LG_3V
SPOK <46>
MAINPWON <40,46>
A
C
I
N
EC_ON <40,41>
+5VALWP
+3VALWP
B+
+3VLP
2VREF_8205
VL
VL
VS
B+
RT8205_B+
2VREF_8205
VIN
VL
VS
Title
Date: Sheet of
C
2011/06/02
2012/06/02
Custom
Title
Date: Sheet of
C
2011/06/02
2012/06/02
Custom
Title
Date: Sheet of
C
2011/06/02
2012/06/02
Custom
SCHEMATIC,MB A7912
VFB=2.0V
Typ: 175mA
Typ: 175mA
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
RT8205
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)
+3.3VALWP Ipeak=7A ; Imax=4.9A
Delta I=1.5836A=>1/2Delta I=0.7918A (F=375K Hz)
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Ilimit_min=(174K*10uA)/(10*18m*1.2)=7.4965A
Ilimit_max=(174K*10uA)/(10*15m*1.2)=10.349A
Iocp=Ilimit+1/2Delta I=7.4965A~10.349A
+5VALWP Ipeak=7A ; Imax=4.9A
Delta I=2.6342A=>1/2Delta I=1.3171A (F=300K Hz)
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Ilimit_min=(174K*10uA)/(10*18m*1.2)=7.4965A
Ilimit_max=(174K*10uA)/(10*15m*1.2)=10.349A
Iocp=Ilimit+1/2Delta I=7.4965A ~ 10.349A
TPS51125A
TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
(2)SMPS2=305KHZ(+3VALWP)
3.3VALWP Delta I = 1.5836A (Freq=305KHz)
Iocp = 7.4965A ~ 10.349A
5VALWP Delta I = 2.6342A (Freq=245KHz)
Iocp = 7.4965A ~ 10.349A
4019ID
PL7
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
PL7
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
1 2
P
C
4
8
5
6
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
4
8
5
6
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
P
R
7
5
4
.
7
_
1
2
0
6
_
5
%
@
P
R
7
5
4
.
7
_
1
2
0
6
_
5
%
@
1
2
P
C
5
6
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
P
C
5
6
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
1
2
PL6
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
PL6
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
1 2
P
C
4
9
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
P
C
4
9
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
1
2
P
C
5
1
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
P
C
5
1
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
1
2
PR74
2.2_0603_5%
PR74
2.2_0603_5%
1 2
P
C
5
0
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
P
C
5
0
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
1
2
PQ18
SI7716ADN-T1-GE3_POWERPAK8-5
PQ18
4
5
123
PD11
LL4148_LL34-2
930@ PD11
LL4148_LL34-2
930@
1 2
P
C
5
7
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
P
C
5
7
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
1
2
G
D
S
PQ20B
D
S
PQ20B
5
3
4
G
D
S
PQ23B
930@
G
D
S
PQ23B
930@ 5
3
4
PR72
174K_0402_1%
PR72
174K_0402_1%
1 2
P
C
6
3
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
@
P
C
6
3
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
@
1
2
PQ22
PDTC115EUA_SC70-3
930@ PQ22
PDTC115EUA_SC70-3
930@ 2
1
3
P
R
8
2
4
0
2
K
_
0
4
0
2
_
1
%
9
3
0
@
P
R
8
2
4
0
2
K
_
0
4
0
2
_
1
%
9
3
0
@
1
2
PR79
100K_0402_1%
PR79
100K_0402_1%
1 2
PR70
20K_0402_1%
PR70
20K_0402_1%
1 2
PR100
2.2K_0402_5%
9012@PR100
2.2K_0402_5%
9012@
1 2
PR68
30K_0402_1%
PR68
30K_0402_1%
1 2
PR84
1M_0402_1%
930@ PR84
1M_0402_1%
930@
1 2
PD10
GLZ5.1B_LL34-2
PD10
GLZ5.1B_LL34-2
1 2
PU5
RT8205LZQW(2) WQFN 24P PWM
PU5
RT8205LZQW(2) WQFN 24P PWM
F
B
1
2
R
E
F
3
VO1
24
E
N
T
R
I
P
1
1
T
O
N
S
E
L
4
F
B
2
5
S
K
I
P
S
E
L
1
4
N
C
1
8
V
R
E
G
5
1
7
VO2
7
VREG3
8
V
I
N
1
6
G
N
D
1
5
UGATE1
21
BOOT1
22
E
N
T
R
I
P
2
6
PGOOD
23
PHASE1
20
LGATE1
19
E
N
1
3
BOOT2
9
UGATE2
10
PHASE2
11
LGATE2
12
P PAD
25
P
R
7
8
1
5
0
K
_
0
4
0
2
_
1
%
P
R
7
8
1
5
0
K
_
0
4
0
2
_
1
%
1
2
PC59
0.1U_0603_25V7K
PC59
0.1U_0603_25V7K
1 2
PR81
1M_0402_1%
930@ PR81
1M_0402_1%
930@
1 2
+ PC60
220U_6.3V_M
+ PC60
220U_6.3V_M
1
2
P
R
8
5
1
0
K
_
0
4
0
2
_
1
%
9
3
0
@
P
R
8
5
1
0
K
_
0
4
0
2
_
1
%
9
3
0
@
1
2
G
D
S PQ23A
930@
G
D
S PQ23A
930@
2
6
1
P
C
6
5
4
.
7
U
_
0
8
0
5
_
1
0
V
6
K
P
C
6
5
4
.
7
U
_
0
8
0
5
_
1
0
V
6
K
1
2
P
C
6
4
1
U
_
0
6
0
3
_
1
0
V
6
K
P
C
6
4
1
U
_
0
6
0
3
_
1
0
V
6
K
1
2
PQ17
PQ17
SIS412DN-T1-GE3_POWERPAK8-5 4
5
1 2 3
PQ19
PQ19
4
5
1 2 3
P
C
6
7
1
U
_
0
6
0
3
_
1
0
V
6
K
P
C
6
7
1
U
_
0
6
0
3
_
1
0
V
6
K
1
2
PC58
0.1U_0603_25V7K
PC58
0.1U_0603_25V7K
1 2
PR69
20K_0402_1%
PR69
20K_0402_1%
1 2
PR67
13.7K_0402_1%
PR67
13.7K_0402_1%
1 2
P
R
7
6
4
.
7
_
1
2
0
6
_
5
%
@
P
R
7
6
4
.
7
_
1
2
0
6
_
5
%
@
1
2
P
C
5
3
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
5
3
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
PL5
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
PL5
1 2
PR71
174K_0402_1%
PR71
174K_0402_1%
1 2
+ PC62
330U_6.3V_M
+ PC62
330U_6.3V_M
1
2
PR80
0_0402_5%
PR80
0_0402_5%
1 2
PR83
316K_0402_1%
930@ PR83
316K_0402_1%
930@
1 2
P
C
4
6
1
U
_
0
6
0
3
_
1
0
V
6
K
P
C
4
6
1
U
_
0
6
0
3
_
1
0
V
6
K
1
2
PQ21
PDTC115EUA_SC70-3
PQ21
PDTC115EUA_SC70-3
2
1
3
P
Q
1
6
S
I
S
4
1
2
D
N
-
T
1
-
G
E
3
_
P
O
W
E
R
P
A
K
8
-
5
P
Q
1
6
S
I
S
4
1
2
D
N
-
T
1
-
G
E
3
_
P
O
W
E
R
P
A
K
8
-
5
4
5
123
PR77
499K_0402_1%
PR77
499K_0402_1%
1 2
P
C
5
5
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
P
C
5
5
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
1
2
P
C
6
6
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
P
C
6
6
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
1
2
P
C
5
2
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
5
2
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
PR73
2.2_0603_5%
PR73
2.2_0603_5%
1 2
P
C
4
7
5
6
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
4
7
5
6
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
P
C
6
1
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
@
P
C
6
1
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
@
1
2
P
C
5
4
4
.
7
U
_
0
8
0
5
_
1
0
V
6
K
P
C
5
4
4
.
7
U
_
0
8
0
5
_
1
0
V
6
K
1
2
G
D
S
PQ20A
D
S
PQ20A
2
6
1

A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
BST_1.5V-1
1.5V_B+
FB_1.8V
LX_1.8V
+1.8VSP_ON
L
X
_
1
.
5
V
U
G
_
1
.
5
V
B
S
T
_
1
.
5
V
1.5V_B+
S
3
_
1
.
5
V
S
5
_
1
.
5
V
PGOOD_1.5V
LG_1.5V
SUSP#
SUSP# <37,40,44,47,50>
SYSON <40,44>
SUSP <44>
+1.5VP
B+
+3VALW
+1.8VSP
+5VALW
+3VALW
+1.5VP
+VTT_REFP
+0.75VSP
+1.5VP
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Rds=2.7m(Typ)
3.3m(Max)
Note:Iload(max)=3.5A
FB=0.6V
4019ID
FB=0.75V
To GND = 1.5V
To VDD = 1.8V
Note: S3 - sleep ; S5 - power off
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
S0
S3
S4/S5
Hi Hi
Hi Lo
Lo Lo
On
On
On
On
On
Off
(Hi-Z)
Off
(Discharge)
Off
(Discharge)
Off
(Discharge)
DCR: 0.82m5%
_Output Cap PAD
Notice: Internal resistance about 500K on 2nd EN pin
P
C
7
3
1
0
U
_
0
8
0
5
_
2
5
V
6
K
P
C
7
3
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
+ PC74
330U_6.3V_M
+ PC74
330U_6.3V_M
1
2
P
C
8
4
0
.
1
U
_
0
4
0
2
_
1
6
V
7
K
P
C
8
4
0
.
1
U
_
0
4
0
2
_
1
6
V
7
K
1
2
PL8
PL8
1 2
PJ 14
J UMP_43X79
@PJ 14
J UMP_43X79
@
1
1
2
2
PC70
560P_0402_50V7K
PC70
560P_0402_50V7K
1
2
PU6
RT8207MZQW_WQFN20_3X3
PU6
RT8207MZQW_WQFN20_3X3
VTTSNS
2
F
B
6
S
5
8
P
G
O
O
D
1
0
VDDP
12
P
H
A
S
E
1
6
B
O
O
T
1
8
VTTREF
4
PGND
14
VTTGND
1
GND
3
VDDQ
5
S
3
7
T
O
N
9
VDD
11
CS
13
LGATE
15
U
G
A
T
E
1
7
V
T
T
2
0
V
L
D
O
I
N
1
9
PAD
21
P
C
8
1
6
8
P
_
0
4
0
2
_
5
0
V
8
J
P
C
8
1
6
8
P
_
0
4
0
2
_
5
0
V
8
J
1
2
PL9
0.36UH_PDME104T-R36MS0R825_37A_20%
PL9
0.36UH_PDME104T-R36MS0R825_37A_20%
1
3
4
2
P
C
8
5
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
8
5
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
P
Q
2
4
M
D
U
1
5
1
6
U
R
H
_
P
O
W
E
R
D
F
N
5
6
-
8
-
5
P
Q
2
4
M
D
U
1
5
1
6
U
R
H
_
P
O
W
E
R
D
F
N
5
6
-
8
-
5
4
5
1 2 3
PC80
22U_0805_6.3VAM
PC80
22U_0805_6.3VAM
1
2
PC79
0.1U_0402_16V7K
@ PC79
0.1U_0402_16V7K
@
1
2
P
C
8
2
2
2
U
_
0
8
0
5
_
6
.
3
V
A
M
P
C
8
2
2
2
U
_
0
8
0
5
_
6
.
3
V
A
M
1
2
P
R
9
6
4
.
7
_
1
2
0
6
_
5
%
P
R
9
6
4
.
7
_
1
2
0
6
_
5
%
1
2
PR91
267K_0402_1%
PR91
267K_0402_1%
1 2
PR95
5.76K_0402_1%
PR95
5.76K_0402_1%
1
2
PR89
5.1_0603_5%
PR89
5.1_0603_5%
1 2
P
C
8
3
2
2
U
_
0
8
0
5
_
6
.
3
V
A
M
P
C
8
3
2
2
U
_
0
8
0
5
_
6
.
3
V
A
M
1
2
P
Q
2
5
M
D
U
1
5
1
1
R
H
_
P
O
W
E
R
D
F
N
5
6
-
8
-
5
P
Q
2
5
M
D
U
1
5
1
1
R
H
_
P
O
W
E
R
D
F
N
5
6
-
8
-
5
4
5
1 2 3
PC325
0.1U_0402_16V7K
PC325
0.1U_0402_16V7K
1
2
PU7
SY8033BDBC_DFN10_3X3
PU7
SY8033BDBC_DFN10_3X3
EN
5
P
G
4
LX
3
FB
6
SVIN
8
T
P
1
1
LX
2
PVIN
10
N
C
7
PVIN
9
N
C
1
PC71
0.1U_0603_25V7K
PC71
0.1U_0603_25V7K
1 2
PR88
9.1K_0402_1%
PR88
9.1K_0402_1%
1 2
PC78
1U_0603_10V6K
PC78
1U_0603_10V6K
1
2
PR87
4.7_1206_5%
@PR87
4.7_1206_5%
@
1
2
PR92
0_0402_5%
PR92
0_0402_5%
1 2
PL10
1UH_NRS4018T1R0NDGJ _3.2A_30%
PL10
1UH_NRS4018T1R0NDGJ _3.2A_30%
1 2
PR86
2.2_0603_5%
PR86
2.2_0603_5%
1 2
PR94
5.9K_0402_1%
@ PR94
5.9K_0402_1%
@
1 2
P
C
7
2
1
0
U
_
0
8
0
5
_
2
5
V
6
K
P
C
7
2
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
PR93
887K_0402_1%
PR93
887K_0402_1%
1 2
G
D
S PQ27
2N7002KW_SOT323-3
G
D
S PQ27
2N7002KW_SOT323-3
2
1
3
PR257
100K_0402_1%
PR257
100K_0402_1%
1 2
PR98
1M_0402_5%
PR98
1M_0402_5%
1
2
P
C
7
7
1
U
_
0
6
0
3
_
1
0
V
6
K
P
C
7
7
1
U
_
0
6
0
3
_
1
0
V
6
K
1
2 P
R
9
0
1
0
K
_
0
4
0
2
_
5
%
@
P
R
9
0
1
0
K
_
0
4
0
2
_
5
%
@
1
2
PC75
680P_0402_50V7K
@PC75
680P_0402_50V7K
@
1
2
P
C
9
0
4
7
P
_
0
4
0
2
_
5
0
V
8
J
@
P
C
9
0
4
7
P
_
0
4
0
2
_
5
0
V
8
J
@
1
2
P
C
6
8
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
P
C
6
8
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
1
2
P
C
6
9
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
P
C
6
9
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
1
2
PJ 13
J UMP_43X79
PJ 13
J UMP_43X79
1
1
2
2
PR97
20K_0402_1%
PR97
20K_0402_1%
1
2
PR99
10K_0402_1%
PR99
10K_0402_1%
1
2
PC76
0.033U_0402_16V7K
PC76
0.033U_0402_16V7K
1
2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BST_+1.05VS_VTTP
LG_+1.05VS_VTTP
UG_+1.05VS_VTTP
SW_+1.05VS_VTTP
+1.05VS_VTTP_5V
EN_+1.05VS_VTTP
TRIP_+1.05VS_VTTP
FB_+1.05VS_VTTP
+1.05VS_VTTP_B+
RF_+1.05VS_VTTP
VCCIO_SENSE <8>
SUSP# <37,40,44,47,49>
VCCPPWRGOOD <51>
VSSIO_SENSE <8>
B+
+1.05VS_VCCPP
+5VALW
+3VS
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
4019ID
VFB=0.7V
Rds=2.7m(Typ)
3.3m(Max)
VFB= 0.704V
Vo=VFB*(1+PR116/PR119)= 1.05V
Freq= 266~314KHz , 290KHz(typ)
Cesr= 15m ohm
Ipeak= 15.37A Imax= 10.759A
Delta I= 3.4368A ==>1/2 Delta I= 1.7184A
Vtrip=Rtrip*10uA= 0.255V
Iocp= 19.108A~29.416A
P
C
9
5
0
.
1
U
_
0
4
0
2
_
2
5
V
6
P
C
9
5
0
.
1
U
_
0
4
0
2
_
2
5
V
6
1
2
PC101
1U_0603_10V6K
PC101
1U_0603_10V6K
1
2
PC99
0.1U_0603_25V7K
PC99
0.1U_0603_25V7K
1 2
PC100
0.1U_0402_16V7K
PC100
0.1U_0402_16V7K
1
2
PR101
0_0402_5%
PR101
0_0402_5%
1 2
PC104
680P_0402_50V7K
@PC104
680P_0402_50V7K
@
1
2
PR115
4.7_1206_5%
@PR115
4.7_1206_5%
@
1
2
PR113
330K_0402_1%
PR113
330K_0402_1%
1 2
P
C
9
6
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
9
6
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2P
C
9
8
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
P
C
9
8
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
1
2
PR118
100_0402_1%
PR118
100_0402_1%
1 2
PQ30
MDU1511RH_POWERDFN56-8-5
PQ30
MDU1511RH_POWERDFN56-8-5
4
5
1 2 3
PR274
0_0402_5%
@PR274
0_0402_5%
@
1
2
PC103
0.1U_0402_16V7K
PC103
0.1U_0402_16V7K
1
2
PR111
2.2_0603_5%
PR111
2.2_0603_5%
1 2
PC105
1000P_0402_50V7K
PC105
1000P_0402_50V7K
1 2
P
C
9
7
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
P
C
9
7
4
.
7
U
_
0
8
0
5
_
2
5
V
6
-
K
1
2
PU9
TPS51212DSCR_SON10_3X3
PU9
EN
3
TRIP
2
V5IN
7
DRVH
9
SW
8
DRVL
6
VBST
10
TST
5
VFB
4
PGOOD
1
TP
11
PL14
1UH_MMD-10DZ-1R0M-X1A_18A_20%
PL14
1UH_MMD-10DZ-1R0M-X1A_18A_20%
1 2
PR116
4.99K_0402_1%
PR116
4.99K_0402_1%
1 2
PR114
470K_0402_1%
PR114
470K_0402_1%
1
2
P
Q
2
9
M
D
V
1
5
2
5
U
R
H
_
P
D
F
N
3
3
-
8
-
5
P
Q
2
9
M
D
V
1
5
2
5
U
R
H
_
P
D
F
N
3
3
-
8
-
5
4
5
1 2 3
PR117
1.2K_0402_1%
PR117
1.2K_0402_1%
1 2
PR276
0_0402_5%
PR276
0_0402_5%
1 2
PR119
10K_0402_1%
PR119
10K_0402_1%
1
2
+ PC102
330U_6.3V_M
+ PC102
330U_6.3V_M
1
2
PL13
FBMA-L11-322513-151LMA50T_1210
PL13
FBMA-L11-322513-151LMA50T_1210
1 2
PR261
10K_0402_1%
PR261
10K_0402_1%
1
2
PR112
38.3K_0402_1%
PR112
38.3K_0402_1%
1 2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCSA_BT_1
+VCCSA_PWR_SRC +VCCSA_PWR_SRC
+VCCSA_EN
+
V
C
C
S
A
_
V
ID
0
+
V
C
C
S
A
_
V
ID
1
+
V
C
C
S
A
_
P
W
R
G
D
+
V
C
C
S
A
_
P
W
R
G
D
DH_1.5VSDGPU
1.5VSDGPU_EN
DL_1.5VSDGPU
1.5VSDGPU_B+
LX_1.5VSDGPU
BST_1.5VSDGPU
+VCCSA_PHASE
SA_PGOOD <40>
H_VCCSA_VID1 <9>
H_VCCSA_VID0 <9>
VCCPPWRGOOD <50>
+VCCSA_SENSE <9>
VGA_ON <14,17,25,44,53>
VGA_ON# <44>
+3VALW
+VCCSAP
GNDA_VCCSA
GNDA_VCCSA
+5VALW
+3VS
B+
+1.5VSDGPUP +5VALW
+3VALW
+1.5VSDGPU
+1.05VS_DGPUP
VGA_ON <14,17,25,44,53>
VGA_PWROK <44,53>
VGA_PWROK# <44>
VGA_PWROK <44,53>
Title
Date: Sheet of
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. ANDCONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFEREDFROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USEDBY OR DISCLOSEDTO ANY THIRDPARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C C
2011/06/02 2012/06/02
SCHEMATIC,MB A7912
Title
Date: Sheet of
C C
2011/06/02 2012/06/02
SCHEMATIC,MB A7912
Title
Date: Sheet of
C C
2011/06/02 2012/06/02
SCHEMATIC,MB A7912
output voltage adjustable network
VID [0] VID[1] VCCSA Vout
0 0 0.9V
0 1 0.8V
1 0 0.725V
1 1 0.675V
4019ID
+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
VFB=0.7V
Rds=13.5m(Typ)
16.5m(Max)
VFB= 0.704V
Vo=VFB*(1+PR248/PR255)= 1.5V
Freq= 266~314KHz , 290KHz(typ)
Cesr= 15m ohm
Ipeak= 10.40A Imax= 7.28A
Delta I= 4.002A ==>1/2 Delta I= 2.001A
Vtrip=Rtrip*10uA= 1.13V
Iocp= 12.464A~14.167A
FB=0.8V
Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW
P
C
1
1
8
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
P
C
1
1
8
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
1
2
PR250
470K_0402_1%
GPU@ PR250
470K_0402_1%
GPU@
1
2
PR266
0_0402_5%
@ PR266
0_0402_5%
@
1 2
PR128
100_0402_5%
PR128
100_0402_5%
1 2
PC330
22U_0805_6.3V6M
GPU@ PC330
22U_0805_6.3V6M
GPU@
1
2
P
C
1
1
4
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
P
C
1
1
4
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
1
2
P
C
1
1
9
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
P
C
1
1
9
0
.
1
U
_
0
6
0
3
_
2
5
V
7
K
1
2
PU16
APL5930KAI-TRG_SO8
GPU@ PU16
APL5930KAI-TRG_SO8
GPU@
VIN
9
EN
8
VCNTL
6
VIN
5
POK
7
G
N
D
1
FB
2
VOUT
4
VOUT
3
P
C
1
1
7
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
@
P
C
1
1
7
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
@
1
2
PC123
3300P_0402_50V7K
PC123
3300P_0402_50V7K
1 2
G
D
S PQ50
2N7002KW_SOT323-3
GPU@
G
D
S PQ50
2N7002KW_SOT323-3
GPU@
2
1
3
P
C
1
2
0
1
0
U
_
0
8
0
5
_
2
5
V
6
K
P
C
1
2
0
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
PR255
1.74K_0402_1%
GPU@ PR255
1.74K_0402_1%
GPU@
1
2
PU10
TPS51461RGER_QFN24_4X4
PU10
TPS51461RGER_QFN24_4X4
V
5
D
R
V
1
8
PGND
20
SW
11
E
N
1
3
SW
9
VIN
24
V
O
U
T
5
P
G
O
O
D
1
6
C
O
M
P
3
V
ID
0
1
4
M
O
D
E
6
SW
10
S
L
E
W
4
PGND
21
PGND
19
SW
8
G
N
D
1
VIN
23
VIN
22
V
R
E
F
2
V
ID
1
1
5
V
5
F
IL
T
1
7
SW
7
BST
12
TP
25
PC317
0.1U_0603_25V7K
GPU@ PC317
0.1U_0603_25V7K
GPU@
1 2
PR125
0_0603_5%
PR125
0_0603_5%
1 2
PL26
GPU@ PL26
GPU@
1 2
PC326
0.022U_0402_25V7K
GPU@ PC326
0.022U_0402_25V7K
GPU@
1
2
PC328
1U_0402_6.3V6K
GPU@ PC328
1U_0402_6.3V6K
GPU@
1
2
PR270
22K_0402_5%
@ PR270
22K_0402_5%
@
1
2
PR123
10_0402_1%
PR123
10_0402_1%
1 2
PL27
1.2UH_1164AY-1R2N=P3_9.8A_30%
GPU@ PL27
1.2UH_1164AY-1R2N=P3_9.8A_30%
GPU@
1 2
P
C
1
1
6
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
P
C
1
1
6
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
1
2
P
C
1
1
2
.1
U
_
0
4
0
2
_
1
6
V
7
K
@
P
C
1
1
2
.1
U
_
0
4
0
2
_
1
6
V
7
K
@
1
2
PR126
4.7_1206_5%
@PR126
4.7_1206_5%
@
1
2
PR251
2.2_0603_5%
GPU@ PR251
2.2_0603_5%
GPU@
1 2
PC107
2.2U_0603_10V7K
PC107
2.2U_0603_10V7K
1 2
P
C
1
1
1
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
@
P
C
1
1
1
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
@
1
2
PR247
4.7_1206_5%
@ PR247
4.7_1206_5%
@
1
2
PC319
680P_0402_50V7K
@ PC319
680P_0402_50V7K
@
1
2
PR127
33K_0402_5%
@PR127
33K_0402_5%
@
1 2
P
C
3
1
6
1
0
U
_
0
8
0
5
_
2
5
V
6
K
G
P
U
@
P
C
3
1
6
1
0
U
_
0
8
0
5
_
2
5
V
6
K
G
P
U
@
1
2
PR246
47K_0402_1%
@ PR246
47K_0402_1%
@
1 2
PQ45
GPU@ PQ45
GPU@
4
5
1 2 3
PC109
680P_0402_50V7K
@ PC109
680P_0402_50V7K
@
1
2
PR121
1K_0402_5%
PR121
1K_0402_5%
1 2
PJ 16
PAD-OPEN1x1m
PJ 16
PAD-OPEN1x1m
1 2
P
C
1
1
5
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
@
P
C
1
1
5
2
2
0
0
P
_
0
4
0
2
_
5
0
V
7
K
@
1
2
PR124
0_0402_5%
PR124
0_0402_5%
1 2
PC323
4.7U_0805_10V6K
GPU@ PC323
4.7U_0805_10V6K
GPU@
1
2
PR248
2K_0402_1%
GPU@ PR248
2K_0402_1%
GPU@
1 2
+ PC320
330U_6.3V_M
GPU@ + PC320
330U_6.3V_M
GPU@
1
2
PR253
137K_0402_1%
GPU@ PR253
137K_0402_1%
GPU@
1 2
PJ 15
PAD-OPEN 43X118
PJ 15
PAD-OPEN 43X118
1 2
P
C
1
2
1
1
0
U
_
0
8
0
5
_
2
5
V
6
K
P
C
1
2
1
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
P
C
1
1
3
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
P
C
1
1
3
2
2
U
_
0
8
0
5
_
6
.
3
V
6
M
1
2
PQ46
GPU@ PQ46
GPU@
4
5
1 2 3
PR259
1.91K_0402_1%
GPU@ PR259
1.91K_0402_1%
GPU@
1
2
PC108
0.22U_0603_16V7K
PC108
0.22U_0603_16V7K
1 2
PR260
6.04K_0402_1%
GPU@ PR260
6.04K_0402_1%
GPU@
1
2
PR256
10K_0402_5%
@PR256
10K_0402_5%
@
1
2
PC122
0.22U_0402_10V6K
PC122
0.22U_0402_10V6K
1 2
PU15
GPU@ PU15
GPU@
EN
3
TRIP
2
V5IN
7
DRVH
9
SW
8
DRVL
6
VBST
10
TST
5
VFB
4
PGOOD
1
TP
11
PR130
0_0402_5%
PR130
0_0402_5%
1 2
P
C
3
1
8
1
0
U
_
0
8
0
5
_
2
5
V
6
K
G
P
U
@
P
C
3
1
8
1
0
U
_
0
8
0
5
_
2
5
V
6
K
G
P
U
@
1
2
PR129
10K_0402_5%
PR129
10K_0402_5%
1 2
PC327
1U_0402_6.3V6K
GPU@ PC327
1U_0402_6.3V6K
GPU@
1
2
PL15
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
PL15
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1 2
P
R
1
2
0
1
0
0
K
_
0
4
0
2
_
5
%
P
R
1
2
0
1
0
0
K
_
0
4
0
2
_
5
%
1
2
P
C
3
2
2
5
6
0
P
_
0
4
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GPU@
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PR263
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GPU@
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PR258
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@ PR258
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@
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5
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D D
C C
B B
A A
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NTCG
CPU_B+
LGATE1G
VSUMG+
SCLK
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PWMG2
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VSUM+
ISEN2
VSUM-
ALERT#
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3
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M
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+
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I
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1
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UGATE1G
LGATE3
PHASE1
I
S
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N
2
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UGATE1
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L
G
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T
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1
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SDA
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P
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UGATE2-1
UGATE3-1
VSUMG-
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BOOT3
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VR_SVID_DAT <8>
VR_SVID_ALRT# <8>
VR_SVID_CLK <8>
VR_ON <40>
VGATE <15,40>
VR_HOT# <40>
VCCSENSE <8>
VSSSENSE <8>
VSS_AXG_SENSE <9>
VCC_AXG_SENSE <9>
+CPU_CORE
+CPU_CORE
+5VS
+CPU_CORE
+3VS
+1.05VS_VTT
+3VS
+5VS
+VGFX_CORE
+CPU_CORE
+VGFX_CORE
+5VS +VGFX_CORE
B+
+5VS
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
4019ID
For 45W 3+2
CPU_CORE LL= -1.9m, OCP ~116A
GFX_CORE LL= -3.9m, OCP ~55A
DCR: 0.82m5%
DCR: 0.82m5%
DCR: 0.82m5%
DCR: 0.82m5%
DCR: 0.82m5%
Close Phase 1 choke
For DC 35W 2+1
CPU_CORE LL= -1.9m, OCP ~70A
GFX_CORE LL= -3.9m, OCP ~40A
P
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1
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@ PR191
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PR135
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0.36UH_PDME104T-R36MS0R825_37A_20%
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P
C
1
5
3
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
@
1
2
PR155
0_0402_5%
DC@ PR155
0_0402_5%
DC@
1 2
PU13
ISL95836HRTZ-T_TQFN40_5X5~D
PU13
ISL95836HRTZ-T_TQFN40_5X5~D
C
O
M
P
G
3
7
R
T
N
G
3
9
F
B
G
3
8
P
G
O
O
D
G
3
6
SDA
7
SCLK
5
I
S
E
N
2
1
2
F
B
1
7
I
S
U
M
P
1
4
I
S
E
N
3
/
F
B
2
1
1
C
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M
P
1
8
NTC
10
VR_HOT#
8
ALERT#
6
P
G
O
O
D
1
9
I
S
U
M
N
1
5
VDD
25
R
T
N
1
6
I
S
E
N
1
1
3
VR_ON
9
B
O
O
T
1
2
0
UGATE1
21
PHASE1
22
LGATE1
23
PWM3
24
VCCP
26
LGATE2
27
PHASE2
28
UGATE2
29
BOOT2
30
P
W
M
2
G
3
5
L
G
A
T
E
1
G
3
4
P
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A
S
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1
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3
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1
G
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1
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4
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M
N
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4
0
ISUMPG
1
ISEN2G
3
ISEN1G
2
TP
41
PR143
154K_0402_1%
DC@ PR143
154K_0402_1%
DC@
PR131 10_0402_1% @PR131 10_0402_1% @
1 2
PR137
2.55K_0402_1%
DC@ PR137
2.55K_0402_1%
DC@
PR160 0_0402_5% PR160 0_0402_5%
1 2
PC162
560P_0402_50V7K
PC162
560P_0402_50V7K
1 2
PC180
330P_0402_50V7K
@PC180
330P_0402_50V7K
@
1 2
P
R
1
4
1
2
.
6
1
K
_
0
4
0
2
_
1
%
P
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1
4
1
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.
6
1
K
_
0
4
0
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1
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P
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1
8
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1
0
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_
0
8
0
5
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6
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1
0
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8
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5
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6
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1
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5
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4
0
2
_
1
%
@
P
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2
0
5
1
0
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_
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4
0
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_
1
%
@
1
2
PR196
10K_0603_1%
PR196
10K_0603_1%
1 2
PR157
10K_0603_1%
QC@ PR157
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QC@
1 2 P
R
1
5
6
4
.
7
_
1
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0
6
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%
@
P
R
1
5
6
4
.
7
_
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2
0
6
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@
1
2
P
R
2
0
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.
7
_
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0
6
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5
%
@
P
R
2
0
0
4
.
7
_
1
2
0
6
_
5
%
@
1
2
PR150
2.2_0603_5%
QC@ PR150
2.2_0603_5%
QC@
1 2
PL22
0.36UH_PDME104T-R36MS0R825_37A_20%
PL22
0.36UH_PDME104T-R36MS0R825_37A_20%
1
3
4
2
P
C
1
8
5
3
3
0
P
_
0
4
0
2
_
5
0
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7
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@
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1
8
5
3
3
0
P
_
0
4
0
2
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5
0
V
7
K
@
1
2
PR181
10K_0603_1%
PR181
10K_0603_1%
1 2
P
R
1
4
4
1
0
K
_
0
6
0
3
_
1
%
Q
C
@
P
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1
4
4
1
0
K
_
0
6
0
3
_
1
%
Q
C
@
1
2
PC156
47P_0402_50V8J
@ PC156
47P_0402_50V8J
@
1
2
PC189
0.22U_0603_16V7K
PC189
0.22U_0603_16V7K 1
2
P
R
1
9
5
4
.
7
_
1
2
0
6
_
5
%
@
P
R
1
9
5
4
.
7
_
1
2
0
6
_
5
%
@
1
2
PC173
0.22U_0402_6.3V6K
QC@ PC173
0.22U_0402_6.3V6K
QC@
1 2
P
C
1
8
4
1
0
U
_
0
8
0
5
_
2
5
V
6
K
P
C
1
8
4
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
PC127
0.01UF_0402_25V7K
PC127
0.01UF_0402_25V7K
1
2
P
R
2
0
2
1
0
K
_
0
6
0
3
_
1
%
Q
C
@
P
R
2
0
2
1
0
K
_
0
6
0
3
_
1
%
Q
C
@
1
2
P
C
1
6
9
0
.
0
6
8
U
_
0
4
0
2
_
1
6
V
7
K
Q
C
@
P
C
1
6
9
0
.
0
6
8
U
_
0
4
0
2
_
1
6
V
7
K
Q
C
@
1
2
PL19
0.36UH_PDME104T-R36MS0R825_37A_20%
QC@ PL19
0.36UH_PDME104T-R36MS0R825_37A_20%
QC@
1
3
4
2
P
C
1
7
2
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
@
P
C
1
7
2
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
@
1
2
PC187
0.22U_0603_16V7K
PC187
0.22U_0603_16V7K
1 2
PC125
1000P_0402_50V7K
@ PC125
1000P_0402_50V7K
@
1
2
PR176
2K_0402_1%
PR176
2K_0402_1%
1 2
PR187
390_0402_1%
DC@ PR187
390_0402_1%
DC@
P
R
1
4
2
1
1
K
_
0
4
0
2
_
1
%
P
R
1
4
2
1
1
K
_
0
4
0
2
_
1
%
1
2
P
R
2
0
3
3
.
6
5
K
_
0
6
0
3
_
1
%
P
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2
0
3
3
.
6
5
K
_
0
6
0
3
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1
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1
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P
Q
3
7
M
D
V
1
5
2
5
U
R
H
_
P
D
F
N
3
3
-
8
-
5

P
Q
3
7
M
D
V
1
5
2
5
U
R
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_
P
D
F
N
3
3
-
8
-
5
4
5
1 2 3
P
C
1
7
5
.
1
U
_
0
4
0
2
_
1
6
V
7
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P
C
1
7
5
.
1
U
_
0
4
0
2
_
1
6
V
7
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1
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PU12
QC@ PU12
QC@
LGATE
5
PWM
3
GND
4
UGATE
1
VCC
6
FCCM
7
PHASE
8
BOOT
2
TP
9
PR198
3.65K_0603_1%
PR198
3.65K_0603_1%
1 2
P
C
1
7
9
1
0
U
_
0
8
0
5
_
2
5
V
6
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P
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1
7
9
1
0
U
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0
8
0
5
_
2
5
V
6
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1
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PC170
33P_0402_50V8J
DC@ PC170
33P_0402_50V8J
DC@
PC174
150P_0402_50V8J
PC174
150P_0402_50V8J
1 2
P
C
1
7
8
1
0
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_
0
8
0
5
_
2
5
V
6
K
P
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1
7
8
1
0
U
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8
0
5
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2
5
V
6
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1
2
P
R
1
4
7
1
.
9
1
K
_
0
4
0
2
_
1
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P
R
1
4
7
1
.
9
1
K
_
0
4
0
2
_
1
%
1
2
PR193
10_0402_1%
@ PR193
10_0402_1%
@
1 2
P
R
1
4
3
1
6
9
K
_
0
4
0
2
_
1
%
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C
@
P
R
1
4
3
1
6
9
K
_
0
4
0
2
_
1
%
Q
C
@
1
2
PR174 1.91K_0402_1% PR174 1.91K_0402_1%
1 2
P
R
1
6
9
1
3
0
_
0
4
0
2
_
1
%
P
R
1
6
9
1
3
0
_
0
4
0
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_
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1
2
PL18
PL18
1 2
P
R
1
7
9
4
.
7
_
1
2
0
6
_
5
%
@
P
R
1
7
9
4
.
7
_
1
2
0
6
_
5
%
@
1
2
PR161 0_0402_5% PR161 0_0402_5%
1 2
P
R
1
7
3
3
.
8
3
K
_
0
4
0
2
_
1
%
P
R
1
7
3
3
.
8
3
K
_
0
4
0
2
_
1
%
1
2
PC168
0.1U_0603_25V7K
DC@ PC168
0.1U_0603_25V7K
DC@
P
Q
4
0
M
D
U
1
5
1
1
R
H
_
P
O
W
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R
D
F
N
5
6
-
8
-
5

P
Q
4
0
M
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1
5
1
1
R
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P
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F
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5
6
-
8
-
5
4
5
1 2 3
P
C
1
5
9
1
0
U
_
0
8
0
5
_
2
5
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6
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P
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1
5
9
1
0
U
_
0
8
0
5
_
2
5
V
6
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1
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PH4
470K_0402_5%_ TSM0B474J 4702RE
PH4
470K_0402_5%_ TSM0B474J 4702RE
1 2
PR166
3.65K_0603_1%
QC@ PR166
3.65K_0603_1%
QC@
1 2
P
C
1
8
8
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
@
P
C
1
8
8
6
8
0
P
_
0
4
0
2
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5
0
V
7
K
@
1
2
PR201
1_0402_5%
PR201
1_0402_5%
1 2
PR132
10_0402_1%
@PR132
10_0402_1%
@
1 2
PR148
10K_0402_1%
@PR148
10K_0402_1%
@
1 2
P
C
1
4
2
6
8
0
P
_
0
4
0
2
_
5
0
V
7
K
@
P
C
1
4
2
6
8
0
P
_
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4
0
2
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5
0
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7
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@
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C
1
7
6
1
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0
8
0
5
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5
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6
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P
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1
7
6
1
0
U
_
0
8
0
5
_
2
5
V
6
K
1
2
PR177
20.5K_0402_1%
DC@ PR177
20.5K_0402_1%
DC@
PR190
267K_0402_1%
PR190
267K_0402_1%
1 2
P
C
1
6
8
0
.
2
2
U
_
0
6
0
3
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6
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7
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P
C
1
6
8
0
.
2
2
U
_
0
6
0
3
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1
6
V
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@
1
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PH3
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PH3
10KB_0402_5%_ERTJ 0ER103J
1
2
P
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1
5
3
0
_
0
6
0
3
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5
%
Q
C
@
P
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1
5
3
0
_
0
6
0
3
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5
%
Q
C
@
1
2
PR188
1_0402_5%
PR188
1_0402_5%
1 2
PR197
10K_0402_1%
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@
1 2
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Q
3
4
M
D
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1
5
1
1
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6
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8
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4
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5
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6
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8
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5
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@
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5
1 2 3
P
C
1
4
6
1
0
U
_
0
8
0
5
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2
5
V
6
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Q
C
@
P
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1
4
6
1
0
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0
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0
5
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5
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@
1
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PQ38

4
5
1 2 3
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1
4
7
1
0
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8
0
5
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@
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PC170
47P_0402_50V8J
QC@ PC170
47P_0402_50V8J
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1 2
P
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3
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5
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5
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3
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8
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@
4
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PR185
3.65K_0603_1%
PR185
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1
8
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1
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PC136
0.22U_0603_16V7K
QC@ PC136
0.22U_0603_16V7K
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1 2
PR135
316_0402_1%
QC@ PR135
316_0402_1%
QC@
1 2
P
R
1
4
9
0
_
0
6
0
3
_
5
%
Q
C
@
P
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1
4
9
0
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6
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3
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Q
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@
1
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PC186
0.01UF_0402_25V7K
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3
3
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6
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%
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3
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6
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3
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%
Q
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@
1
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PC138
330P_0402_50V7K
PC138
330P_0402_50V7K
1
2
P
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2
0
4
1
_
0
4
0
2
_
5
%
P
R
2
0
4
1
_
0
4
0
2
_
5
%
1
2
PR164 0_0402_5% PR164 0_0402_5%
1 2
PR159
0_0603_5%
DC@ PR159
0_0603_5%
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1 2
P
C
1
5
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0
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2
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5
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4
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5
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4
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1
7
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4
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_
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7
.
4
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_
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4
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1
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PR163
10K_0402_1%
@PR163
10K_0402_1%
@
1 2
PR194
2.2_0603_5%
PR194
2.2_0603_5%
1 2
P
Q
3
9
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D
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5
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1
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5
6
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5

P
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3
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1
5
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1
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5
6
-
8
-
5
4
5
1 2 3
PL17
0.36UH_PDME104T-R36MS0R825_37A_20%
QC@ PL17
0.36UH_PDME104T-R36MS0R825_37A_20%
QC@
1
3
4
2
PC163
10P_0402_50V8J
DC@ PC163
10P_0402_50V8J
DC@
1 2
PR139
2K_0402_1%
PR139
2K_0402_1%
1
2
PC135
150P_0402_50V8J
PC135
150P_0402_50V8J
1 2
PR175
0_0402_5%
PR175
0_0402_5%
1 2
PR178
2.2_0603_5%
PR178
2.2_0603_5%
1 2
PC133
47P_0402_50V8J
QC@ PC133
47P_0402_50V8J
QC@
1 2

8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
V2N_VGA
BOOT2_VGA BOOT2_2_VGA
PHASE2_VGA
BOOT1_1_VGA
V1N_VGA
CLK_ENABLE#_VGA
B
O
O
T
1
_
V
G
A
V2N_VGA
V1N_VGA
PHASE1_VGA
LGATE2_VGA
UGATE2_VGA
G
P
U
_
V
ID
6
G
P
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_
V
ID
3
G
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V
ID
2
LGATE1_VGA
UGATE1_VGA
G
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V
ID
0
G
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ID
1
G
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ID
4
G
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ID
5
VGA_PWROK 51>
VCCSENSE_VGA <24>
VSSSENSE_VGA <24>
G
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D
0
<
2
2
>
G
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1
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>
VGA_ON <14,17,25,44,51>
G
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2
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2
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G
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4
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2
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G
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5
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2
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>
GPU_HOT# <40>
+VGA_B+
B+
+VGA_B+
+5VS
+3VS
+5VS
+VGA_B+
+3VS
+VGA_CORE
+VGA_CORE
+VGA_CORE
VSUM-_VGA
VSUM-_VGA
VSUM-_VGA
ISEN2_VGA
ISEN2_VGA
ISEN1_VGA
ISEN1_VGA
VSUM+_VGA
VSUM+_VGA
VSUM+_VGA
VSUM-_VGA
+5VS
+3VS
+5VS
+3VSDGPU
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
C
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
C
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
C
2011/06/02 2012/06/02
Layout Note:
Place near Phase1 Choke
4019ID
LL Disable
1 phase OCP ~33A
2 phase OCP ~57A
DCR: 0.82m5%
DCR: 0.82m5%
N12P GS4
N12P GV4
N13P GV
0.975V
VGA Chipset
0.9V
0
Default
Voltage
1
VID5 VID4 VID0
0 1 1 0
VID1
0
0
VID2
1
VID3
1 0 0
0.9V
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PR232
10_0402_5%
GPU@ PR232
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GPU@
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2.2_0603_5%
GPU@ PR235
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GPU@ PC201
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GPU@
1
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PR249
0_0402_5%
1S@ PR249
0_0402_5%
1S@
1 2
PC221
1000P_0402_50V7K
GPU@ PC221
1000P_0402_50V7K
GPU@
1
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2S@ PL24
0.36UH_PDME104T-R36MS0R825_37A_20%
2S@
1
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PL23
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GPU@ PL23
FBMA-L11-322513-151LMA50T_1210
GPU@
1 2
PR217
10K_0402_5%
2S@ PR217
10K_0402_5%
2S@
1 2
P
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PR228
0_0402_5%
GPU@ PR228
0_0402_5%
GPU@
1 2
PR210
10K_0402_1%
GPU@ PR210
10K_0402_1%
GPU@
1 2
PR219
100K_0402_5%
2S@ PR219
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1 2
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@
1 2
PC198
680P_0402_50V7K
@PC198
680P_0402_50V7K
@
1
2
PR252
0_0402_5%
1S@ PR252
0_0402_5%
1S@
1 2
PC203
470P_0402_50V7K
GPU@ PC203
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GPU@
1 2
P
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2
3
3
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5
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0
4
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@
P
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8
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4
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@
1
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PR209
68K_0402_1%
GPU@ PR209
68K_0402_1%
GPU@
1 2
PR213
2.2_1206_5%
@PR213
2.2_1206_5%
@
1
2
PR231
255K_0402_1%
GPU@ PR231
255K_0402_1%
GPU@
1
2
PL25
0.36UH_PDME104T-R36MS0R825_37A_20%
GPU@ PL25
0.36UH_PDME104T-R36MS0R825_37A_20%
GPU@
1
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4
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P
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1
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PC204
47P_0402_50V8J
GPU@ PC204
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GPU@
1 2
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@ PD12
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@
1 2
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2
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9
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5
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2
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1
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PR229
324K_0402_1%
GPU@ PR229
324K_0402_1%
GPU@
1 2
P
C
9
1
5
6
P
_
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4
0
2
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8
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1
5
6
P
_
0
4
0
2
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5
0
V
8
G
P
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@
1
2
PR227
3.57K_0402_1%
GPU@ PR227
3.57K_0402_1%
GPU@
1 2
P
R
2
1
4
3
.6
5
K
_
0
4
0
2
_
1
%
2
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@
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5
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2
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1
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4
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1
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5
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N
5
6
-
8
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5
2
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@
4
5
1 2 3
PR216
1.91K_0402_1%
GPU@ PR216
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GPU@
1
2
PC199
1U_0603_10V6K
2S@ PC199
1U_0603_10V6K
2S@
1 2
PR215
1_0402_5%
2S@ PR215
1_0402_5%
2S@
1
2
PC215
330P_0402_50V7K
GPU@ PC215
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GPU@
1
2
PR236
0_0402_5%
GPU@ PR236
0_0402_5%
GPU@
1 2
PC205
150P_0402_50V8J
GPU@ PC205
150P_0402_50V8J
GPU@
1 2
PR244
10_0402_5%
GPU@ PR244
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GPU@
1 2
P
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PR245
953_0402_1%
2S@ PR245
953_0402_1%
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@
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5
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PR218
0_0402_5%
GPU@ PR218
0_0402_5%
GPU@
1 2
PR243
0_0402_5%
GPU@ PR243
0_0402_5%
GPU@
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PR208
2.2_0603_5%
2S@ PR208
2.2_0603_5%
2S@
1 2
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2
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1
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PR186
27.4K_0402_1%
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27.4K_0402_1%
@
1 2
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PU14
ISL62883CHRTZ-T_TQFN40_5X5
GPU@ PU14
ISL62883CHRTZ-T_TQFN40_5X5
GPU@
PGOOD
1
PSI#
2
RBIAS
3
VR_TT#
4
NTC
5
VW
6
COMP
7
FB
8
V
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1
7
IS
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1
1
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V
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1
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1
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1
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1
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1
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VSSP1
22
LGATE1
23
PWM3
24
VCCP
25
LGATE2
26
VSSP2
27
PHASE2
28
UGATE2
29
V
ID
0
3
1
V
ID
1
3
2
V
ID
2
3
3
V
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3
3
4
V
ID
5
3
6
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6
3
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8
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9
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10
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1
8
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1
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41
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21
BOOT2
30
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V
6
K
G
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2
1
3
1
0
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0
8
0
5
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2
5
V
6
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G
P
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@
1
2
PC214
0.22U_0603_10V7K
GPU@ PC214
0.22U_0603_10V7K
GPU@
1 2
PC224
0.1U_0402_16V7K
GPU@ PC224
0.1U_0402_16V7K
GPU@
1
2
PR237
2.2_1206_5%
@PR237
2.2_1206_5%
@
1
2
P
R
2
4
0
1
_
0
4
0
2
_
5
%
G
P
U
@
P
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2
4
0
1
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0
4
0
2
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5
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P
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1
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7
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1
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7
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2
S
@
1
2
PR242
10K_0402_5%
2S@ PR242
10K_0402_5%
2S@
1 2
PR278
0_0402_5%
@ PR278
0_0402_5%
@
1 2
PR199
3.83K_0402_1%
@PR199
3.83K_0402_1%
@
1 2
PR225
499_0402_1%
GPU@ PR225
499_0402_1%
GPU@
1 2
PR221
0_0402_5%
GPU@ PR221
0_0402_5%
GPU@
1 2
PC331
0.1U_0402_16V7K
GPU@ PC331
0.1U_0402_16V7K
GPU@
1
2
PC223
680P_0402_50V7K
@PC223
680P_0402_50V7K
@
1
2
PR245
590_0402_1%
1S@ PR245
590_0402_1%
1S@
PH7
10K_0402_1%_TSM0A103F34D1RZ
GPU@ PH7
10K_0402_1%_TSM0A103F34D1RZ
GPU@
1
2
PC200
33P_0402_50V8J
@PC200
33P_0402_50V8J
@
1 2
PR222 0_0402_5% GPU@ PR222 0_0402_5% GPU@
1 2
P
Q
4
1
M
D
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1
5
1
6
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P
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5
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8
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2
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@
4
5
1 2 3

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.05VS_VTT
+CPU_CORE
+CPU_CORE
+VGFX_CORE
+1.05VS_VTT
+CPU_CORE
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
4019ID
Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
Vaxg
PWR Rule
CPU 330uF/9m *5,22uF *16,10uF*10
GFX 470uF/4.5m*1,330uF/9m*1,22uF*12
INTEL Recommend
3*330uF(1 in other page),12*22uF, 5 no stuff
from PDDG 1.0
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DC@ PC271
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DC@
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D D
C C
B B
A A
+VGA_CORE
+VGA_CORE
Title
Date: Sheet of
C
SCHEMATIC,MB A7912
B
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
B
2011/06/02 2012/06/02 Title
Date: Sheet of
C
SCHEMATIC,MB A7912
B
2011/06/02 2012/06/02
Under GPU
Near GPU
4019ID
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D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Version change list (P.I.R. List) Page 1 of 2
for PWR
Reason for change Rev. PG# Modify List Date Phase Fixed Issue Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
S3 sequence @ DC Meet Intel sequence SPEC Change RP91 to 267K
49
2011
1208
DVT
18
19
51
1.5VSDGPU lose Improve FB pin anit-noise Change RP248 to 2K, PR255 to 1.74K, PR253 to 137K
DVT 2011
1208
52
Cut-in SMT memo Add PC182, PC184
DVT 2011
1208
Standard design Change PR138, PR150, PR178, PR194, RP205 , PR235 to 2.2
Change PU16 from G971 to APL5930
51
Vth has risk
DVT 2011
1212
51
Add PR266 Enable select
2011
1217
53
Cut-in EMI solution
2011
1221
Add PC88, PC89, PC91
Change PR277 from 0402 to 0603
2011
1222
51
Consider part rating
Add PC139, PC169
Swap PC271 & PC275
2011
1222
52
2011
1208
DVT
2011
1222
46
Delete PR37, PR57
10
PH1 OTP and ADP_I throttling by H/W control
Tune transient character
55
Add PC313, PC314, PC315
2011
1222
11
Follow Power design
51
12
VGA sequence meet nVidia SPEC
PVT 2011
1223
PVT
PVT
PVT
PVT
PVT
PVT
Swap PR258 & PR263, PR266 & PR264, PR246 & PR265
47
13
Cut-in EMI solution
PVT2 2012
0104
Add PR53, PC40

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D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/06/02 2012/06/02
Version change list (P.I.R. List) Page 2 of 2
for PWR
Reason for change Rev. PG# Modify List Date Phase Fixed Issue Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

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D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31
Page1
Solution Description Rev. Page# Title
Version ChangeList ( P. I. R. List )
Item IssueDescription Date
Request
Owner
1 P.40.13 9/7 EC Change th HDA_SDO to ME_EN
0.2
2 P.40 9/7 HW Add R2085 ,change the EC_ACIN pull high to +3VLP 0.2
3 P.37 9/7 0.2
4 P.38.39.40 9/7 HW 0.2
5 P.22.40 9/7 HW 0.2
Add fl1009 USB3.0 TX coupling capacitor (c2060,c2061)
Add USB chargaer schematic(C2060.C2061.R2077~R2084,R2065~R2072)
Follow ABO request,add ADPS function(Q2005),R2086.R2087)
HW
6 P.20 9/7 HW 0.2 Add +5VALW TO +5VALW_PCH schematic(Q2006.C2062.R2088)
7 P.44 9/7 HW 0.2 Add +3VALW TO +3VALW_PCH schematic(U2006,R2073~R2076,C2056~C2059,Q2003,Q2004)
8 P.43 9/7 HW For FSOV spec,Chang R714,R716 from 75ohm to 47ohm. 0.2
9 P.13 9/7 HW For WIN8,Change R681.R651.R684.R652 to 33ohm 0.2
10 P.44 9/7 HW Delete C817,Change C826 from D2 size to B2 size 0.2
11 P.17.37 9/7 HW Follow chief river common design, please chang Mini-Card 2(port 11) to port 9 0.2
0.2 12 P.38 9/7 HW Delete +1.5V to +1.05V_V128 Transfer(U2002.R2002.R2003.R2005.C2002.C2003.C2005.R2008)
0.2 13 P.38 9/7 HW Delete USB3.0 EEPROM(U2004.R2035.R2034.C2039)
0.2 14 P.37 9/7 HW Reserve Mini-Card 2
0.2 15 P.19 9/7 HW
F2 flick issue on projector P5202 D-sub
Add C2063.C2064
0.2 16 P.22.40 9/8 HW
Change VGA GPIO12 of dGPU connection to EC controlled for the power limited usage
Add EC pin 107-->GPU_ACIN
0.2 17 P41 9/14 HW Add SW5.SW6 for EG project.
18 P27.30 9/14 HW
Swap MDC37 and MDC38
Swap MDA13 and MDA14
0.2
19
P06.11.17.35.
P39.40.42
9/14 HW
For ESD request
Add C2065~C2075
0.2
20 P16
9/16
HW
For HDMI PCH_DPB_HPD noise
Add C2076
0.2
21 P31 9/16 HW
For LVDS power sequence
Change R5 from 300 to 200 ohm
Change R2 from 1k to 10k ohm
change C2 from 0.047uF to 1uF
0.2
22 P18 9/16
HW Delete PCH test ponit(T31~T46,T49~T61,T63~T65) 0.2
23 P21,40 9/19 HW Change Q22,Q26 from SB000008J10 to SB000009080
0.2
24 P14,22,35,38
9/19 HW
For Crystal
Change Y2 ,Y4 from SJ10000DJ00 to SJ10000E800
Change Y1000 from SJ10000DK00 to SJ100009700
Change C630,C631,C2019,C2028,C1008,C1009 to 10pF
Change C681,C679 to 15pF
0.2

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31
Page2
Request
Owner
25 P.44 9/20 EMI For EMI request (Add C2079~C2084)
0.2
26 P.36 9/20 HW For SD3.0 issue (Add R2088.R2089) 0.2
27 P.20 10/17 HW 0.3 Add +5VALW TO +5VALW_PCH schematic(Q2006.C2062.R2090)
28 P.44 10/17 HW 0.3 Add +3VALW TO +3VALW_PCH schematic(U2006,R2073~R2076,C2056~C2059,Q2003,Q2004)
29 P.40 10/17 HW 0.3
Board ID error.
Add R353.
30 P.40 10/17 HW 0.3
Board ID 0.3.
Change R353 to 18K
31 P.17,39 10/17 HW 0.3
Follow Intels suggestion;
Change USB3.0 from port 2 to port 1
Change USB2.0 from port 0,1 to port 2,9
32 P.18 10/18 HW 0.3
Support eDP
GPIO71-->0 (eDP)
GPIO71-->1 (LVDS)
33 P.13.40 10/25 HW Co_lay NPCE885N
Delete U38,C722,R690,R695,C727
Add C2085,R2091~R2096
0.3

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31
Page3
Request
Owner
43 P.41 11/16 ME
Delete SW5,SW6,
Pop SW2,SW3 0.4
44 P.05 11/16 HW Add C2090
0.4
BUF_CPU_RST# noise
45 P.35 11/17 HW
De-pop U31,R537
Pop R538 0.4
LAN SPROM on Chip
46 P.36 11/17 EMI Change C478 to 10P_50V
0.4
47 P.13 11/17 HW Change C682,C686 to 15P
0.4 RTC issue
48 P.31,32,41 11/17 ESD De-pop D3,D4,D17,D18,D15
Pop D24,D36
0.4
49 P.40 11/17 HW De-pop R891,R893 0.4
52 P.13,40 11/21 HW Delete NPCE885N
(R2091.R2092.R2094.R2095.R2096,R698,
R699,R692,C2085)
0.4
50 P.24 11/21 HW N13P_GS
Change strap2 to PD 15k
Change strap4 to PD 10k
0.4
51 P.13 11/21 HW Chip Select
Change R651,R2049 to 0ohm
0.4
53 P.45 11/22 HW Change +1.05VSDGPU JUMP size
PJ19 change to 43x118
0.4
56 P.13 11/23 HW Delete R2093,R2049,R651(0ohm) 0.4
57 P.13 11/23 HW Change N13P-GS to SA000051880
Change U33 to SA00005AG00
0.4
55 P.35,36 11/23 HW Card Reader
Change R216 to 22 ohm
Change R2088 to 47ohm
Change R2089 to 22 ohm
Add C2091~C2093
Change R525,R536,R537,R538 to 1k
0.4
58 P.35, P36 11/23 HW 0.4 Del C2093, R222, R2089,
net(CR_CLK_XD_RY_BY#_23)
Add R2101, C2094
59 P.36 11/24 HW 0.4 ADD R2102, C2096 for EMI ISSUE

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31
Page4
Request
Owner
58 P.24.25 12/02
Change R1057 from 35kohm to 45kohm
Change R1077 from 40.2ohm to 42.2ohm
Change R1080 from 60.4ohm to 51.1ohm
0.4
59 P.22 12/02
for N13P_GS, the boot voltage is 0.9V
pop R1022,R1021,R1036,R1035,R1034,R1033
for N13P_GL, the boot voltage is 0.95V
pop R1022,R1037,R1020,R1019,R1034,R1033
for N13M_GS, the boot voltage is 0.925V
pop R1022,R1037,R1020,R1019,R1018,R1033
0.4
60 P.44 12/02
Change R369 from 470ohm to 150ohm
Pop Q3
0.4
61 P.13 12/02
BIOS ROM(4M)
Change U36 to SA00003K800 0.4
62 P.35 12/06
EMI suggestion for Card Reader
Change C2094 from 6pF to 6.8pF
De-pop C2096
0.4
63 P.36 12/07
EMI request for _j
Add C2097
64 P.39 12/07
For PCH HM70
Change USB port0 to co-lay USB3.0
Change USB port2 to USB2.0
Change USB port 11 to BT
65 P.44 12/07
Change 1.5VSDGPU EN from VGA_ON# to VGA_PWROK#
Add R2103,Q2008
0.5
0.5
0.5
66 P.18 12/09 For eDP
Change Q2007 from SB501380020 to SB501110010
0.5

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31
Page5
Request
Owner
67 12/16 change Q2007 to 2N7002 for eDP_HPD circuit LA-7912
0.2
add WLAN_PME# on pin85.
add wlan_on signal on EC pin38
add AC circuit
reserve Q2007 for open +3V_LAN by
PCH_PWREN#
add R2063 for pull high VCIN0_PH to +3VL 10k
add R2059 for pull low VCIN1 10k
resever R2116 ~ R2119 for change LED power to 3V
resever C2101~C2107 56pF on T/P for EMI
change R384 & R385 power to +3V_LAN
unpop R630 & reserve R2120 to pull high +3V_LAN
change Q43 from 2n7002 to BSS138
unpop R209
change R353 to 56k for board ID 0.2
power request pop R2063, R2059
un-pop R880, R891, R893
L1002 use SM010028800 (for N13P_GL)
use 0ohm on N13P_GS,N13M_GS
68
P.31 EE
P.40 12/16 EE
69 12/16 P.35
LA-7912
0.2
LA-7912
0.2
EE
LA-7912
0.2
70 12/16 P.40 EE
LA-7912
0.2
71 12/20 P.41 EE
LA-7912
0.2
72 12/22 P.36, 14 EE
LA-7912
0.2
73 12/22 P.42, 35 EE
LA-7912
0.2
74 12/23 P.40 PWR
change USB3 signal pass by chock (SM070001600)
R2088 change to 10ohm
12/23 P.39 EMI 75
LA-7912
0.2
Change LED(Blue) SC591NB5A30 to SC591TBKA10
Change LED(AMBEL) SC500007700 to SC500005930
change (R2116=130ohm),(R377,2118,378=390ohm)
(R2117,2119 = 51 ohm)
LA-7912
0.2
12/23 P.41 ME 76
12/23 P.36 EMI 78 LA-7912
0.2
LA-7912
0.2
12/23 P.25 EMI 79
POP R2104, R2106 unpop R2105, R2107
for VGA sequence
LA-7912
0.2
12/24 P.44 EE 80
De-pop C217,C216 EMI request.
add R1019, R1020, R1037 for GM@ (VGA_CORE)
LA-7912
0.2
12/24 P.41,24 EMI,EE 81
change R2059&R2063 to 10k ohm for EC request
C2086~C2089 change bom sturte to DIS@
LA-7912
0.2
12/27 P.40,27 EE 82
add R2125, R2123 for option WL_OFF# to EC or PCH
add R2122, R2124 for option BT_ON# to EC or PCH
reserve R2126 to pull high 3VALW
reserve R2127 to pull high 3VALW
LA-7912
0.3
12/27 P.40 EE 83

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31 Title
Date: Sheet of
4019ID
C
SCHEMATIC,MB A7912
Custom
2011/08/31 2012/08/31
Page6
Request
Owner
reserve R2121 for WLAN_LED connect +3VALW
change C2101~2107 bomstucture to GM@
LA-7912
0.3
01/02 P.41 EE 83
01/09 P.13 EE 84
LA-7912
0.3
add GPIO23 for define USB config.
(R2128 & R2092)
01/09 P.45~56 PWR 85
update power circuit LA-7912
0.3
change R2110 to pull high +3VS_FULL LA-7912
0.3
01/09 P.37 EE 86
01/10 P.31 EE 87 add R2130 reserve for lvds short issue
LA-7912
0.3
01/10 P.40 EE 88 change board ID to 0.3 (R353 100k)
LA-7912
0.3
01/11 P.37 EE 89 change R2110 to pull high +3VALW
LA-7912
0.3
01/11 P.37 EE 90 pop +3VS_FULL _
LA-7912
0.3
01/11 P.13 EE 91
add new bom structer usb2@ for usb flag LA-7912
0.3
01/11 P.44 EE 92
UNPOP +1.5VSDGPUH to +1.5VSDGPU circuit LA-7912
0.3
01/12 P.35, 40 EE 93
add R2131,R2132 for option turn off 3VLAN power
by PCH_PWR_EN# or LAN_PWR_EN# (from EC)
LA-7912
0.3
01/18 P.37, 40 EE 94
add R2134~R2136 reserve for AOIC
for ACER request
LA-7912
0.3
01/18 P.17 EE 95
reserve R2137 pull low USB_P8 for PCH leakage LA-7912
0.3
96 P.32 02/02 EE change R428 & R426 to 0 ohm for CRT issue
LA-7912
0.3

823c2 Compal LA-7912P

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823c2 Compal LA-7912P

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