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Eddie Edwards
eedwards@doc.ic.ac.uk
https://www.doc.ic.ac.uk/~eedwards/compsys/
Heavily based on notes by Naranker Dulay
Computer Architecture (E Edwards) 8.1 Computer Architecture (E Edwards) 8.2
Registers
Program counter (address of next instruction)
Instruction register (holds current instruction)
Stack Pointer (address of top of stack)
Accumulator (holds result of ALU operations)
General purpose registers (hold intermediate results or addresses during instructions)
Computer Architecture (E Edwards) 8.3 Computer Architecture (E Edwards) 8.4
Fetch-Execute Cycle Animated CPU example
Fetch the Instruction
Repeat Forever
Computer Architecture (E Edwards) 8.5 Computer Architecture (E Edwards) 8.6
LOAD R2, [201H] 0001 10 10 0000 0001 00 1000 0000 A=0 0000 0000 0000 0000 10 0000 0000
1 A 0 1 0 8 0 H 0 0 0 0 2 0 0 H
ADD R2, [202H] 0011 10 10 0000 0010 00 1000 0001 B=9 0000 0000 0000 1001 10 0000 0001
3 A 0 2 0 8 1 H 0 0 0 9 2 0 1 H
STORE R2, [200H] 0010 10 10 0000 0000 00 1000 0010 C=6 0000 0000 0000 0110 10 0000 0010
2 A 0 0 0 8 2 H 0 0 0 6 2 0 2 H
MEMORY MEMORY
Computer Architecture (E Edwards) 8.13 Computer Architecture (E Edwards) 8.14
080H
n RAM RAM
Input Reg2 a
l
Control 080H
Program Counter B Bus PC 080H 0
u
Instr. Decoder Instr. Register s Instr. Decoder
3FD 3FD
0
3FE 0 3FE
Control Unit 3FF Control Unit 3FF
1
Computer Architecture (E Edwards) 8.15 Computer Architecture (E Edwards) 8.16
LOAD R2, [201H] R2=Memory[201H] LOAD R2, [201H] R2=Memory[201H]
CPU 000 CPU 000
001 001
002 080H 002
080H
R2 003 R2 003
ALU ALU
RAM RAM
0
PC 080H + 1 0 PC 081H
Instr. Decoder Instr. Decoder
3FD 3FD
3FE 3FE
Control Unit 3FF Control Unit 3FF
2 3
Computer Architecture (E Edwards) 8.17 Computer Architecture (E Edwards) 8.18
201H
ALU 082 2A00H ALU 082 2A00H
1A01H 1A01
RAM RAM
1A01H
200 0000 200 0000
0 201 0009 201 0009
PC 081H 202 0006 PC 081H 0 202 0006
1A01H
Instr. Decoder 1A01H 1A01H
3FD 3FD
0
1, 2, 201H 201H
3FE 3FE
Control Unit 3FF 1, 2, 201H 3FF
4 0 5
Computer Architecture (E Edwards) 8.19 Computer Architecture (E Edwards) 8.20
LOAD R2, [201H] R2=Memory[201H] ADD R2, [202H] R2=R2+Memory[202H]
CPU 000 CPU 000
201H 001 001
0009 201H 081H
R2 0009 R2 0009
080 1A01H 080 1A01H
081 3A02H 081 3A02H
081H
0009
ALU 082 2A00H ALU 082 2A00H
0009 0009
RAM RAM
1A01H
3FD 3FD
0
3FE 0 3FE
1, 2, 201H 3FF 3FF
6 7
Computer Architecture (E Edwards) 8.21 Computer Architecture (E Edwards) 8.22
202H 0009
080 1A01H 080 1A01H
081 3A02H 081 3A02H
3A02
ALU 082 2A00H ALU 0009 082 2A00H
0009 3A02H 3A02H
RAM RAM
3A02H
200 0000 200 0000
201 0009 201 0009
PC 081H + 1 0 202 0006 PC 082H 0 0 202 0006
3A02H
3A02H 3A02H
3FD 3FD
0
3, 2, 202H 202H
3FE 3FE
3FF 3, 2, 202H 3FF
8 0 9
Computer Architecture (E Edwards) 8.23 Computer Architecture (E Edwards) 8.24
ADD R2, [202H] R2=R2+Memory[202H] STORE R2, [200H] Memory[200H]=R2
CPU 000 CPU 000
001 001
000FH 202H 202H 082H
R2 000FH
0009 R2 000FH
000FH
080 1A01 080 1A01H
081 3A02 081 3A02H
082H
ALU 082 2A00 ALU 082 2A00H
0009 0006 0006
000FH ADD RAM RAM
000FH
0006
000FH 0006
200 0000 200 0000
201 0009
082H 201 0009
PC 082H 0 0 202 0006 PC 082H 0 202 0006
3A02H
3FD 3FD
0
3FE 0 3FE
3, 2, 202H 3FF 3FF
10 11
Computer Architecture (E Edwards) 8.25 Computer Architecture (E Edwards) 8.26
200H 000FH
R2 000FH R2 000FH
000F
080 1A01H 080 1A01H
081 3A02H 081 3A02H
ALU 082 2A00H ALU 082 2A00H
2A00
000FH 2A00H
RAM RAM
2A00H
200 0000 200 0000
201 0009 201 0009
PC 082H + 1 0 202 0006 PC 083H 1 1 202 0006
2A00H
2A00H 2A00H
3FD 3FD
1
2, 2, 200H 200H
3FE 3FE
3FF 2, 2, 200H 3FF
12 1 13
Computer Architecture (E Edwards) 8.27 Computer Architecture (E Edwards) 8.28
STORE R2, [200H] Memory[200H]=R2 Think About
CPU 000 Fetch-Execute Cycle
200H 200H 001
Assembly Languages
R2 000FH
080 1A01H Program Representation: Instructions, Instruction Fields,
081 3A02H Instruction Formats
ALU 082 2A00H
00FH 00FH CPU Components: Registers, ALU, Control Unit
RAM Registers: General Purpose Registers, Program
Counter (PC), Instruction Register (IR),
200
ALU Registers
000FH
0000
1 1 201 0009 Buses: Internal, Address, Data, Control
PC 083H 202 0006
3FD
3FE
3FF
14
Computer Architecture (E Edwards) 8.29 Computer Architecture (E Edwards) 8.30