Composition of a CPU

CPU Organisation & Operation

Eddie Edwards
eedwards@doc.ic.ac.uk

https://www.doc.ic.ac.uk/~eedwards/compsys/
Heavily based on notes by Naranker Dulay
Computer Architecture (E Edwards) 8.1 Computer Architecture (E Edwards) 8.2

Composition of a CPU Simple CPU

Control Unit

Generated control/timing signals

Controls decoding/execution of instruction

Arithmetic Logic Unit (ALU)

Used during execution of instructions

Performs mathematical operations (* / + - etc.)

Also logical operations, and/or etc. and also shift/rotate

Registers

Program counter (address of next instruction)

Instruction register (holds current instruction)

Stack Pointer (address of top of stack)

Accumulator (holds result of ALU operations)

General purpose registers (hold intermediate results or addresses during instructions)
Computer Architecture (E Edwards) 8.3 Computer Architecture (E Edwards) 8.4
Fetch-Execute Cycle Animated CPU example

Fetch the Instruction

Increment the Program Counter

Decode the Instruction

Fetch the Operands See http://www.doc.ic.ac.uk/~eedwards/compsys/cpu/iecycle.swf

Perform the Operation

Store the Results

Repeat Forever
Computer Architecture (E Edwards) 8.5 Computer Architecture (E Edwards) 8.6

High-Level/Low-Level Languages, Machine Code The Toy1 Architecture

High-Level Language (e.g. Java, C++, Haskell)
Maximum of 1024 x 16-bit memory words
A=B+C Assignment Statement Memory is Word Addressed

Low-Level Language -> Assembly Language (e.g. Pentium, PowerPC,

ARM etc, Java Bytecode)
Two’s Complement Integer Representation
LOAD R2, B Assembly Language
ADD R2, C Instructions
STORE R2, A
4 General Purpose Registers (16-bit) : R0, R1, R2, R3

(Binary) Machine Code

0001101000000001 Machine Code
Upto 16 “Instructions”, e.g. LOAD, ADD, STORE

0011101000000010 Instructions
0010101000000000
Computer Architecture (E Edwards) 8.7 Computer Architecture (E Edwards) 8.8
Toy1 Instruction Set Toy1 Instruction Format

LOAD Register , [MemoryAddress] Assembly Instruction e.g. ADD R2, C
Register = Memory [MemoryAddress]

STORE Register , [MemoryAddress] Machine Code OPCODE REG ADDRESS

Memory [MemoryAddress] = Register 4-bit 2-bit 10-bit

ADD Register , [MemoryAddress]

Register = Register + Memory [MemoryAddress] Instruction Fields

OPeration CODE (Selects CPU Instruction)

SUB Register , [MemoryAddress]
REGister (Specifies 1st Operand for Instruction)
Register = Register - Memory [MemoryAddress]
ADDRESS (Specifies 2nd Operand for Instruction)

Computer Architecture (E Edwards) 8.9 Computer Architecture (E Edwards) 8.10

Other Possibilities for the Format Instruction Field Encoding

OPCODE REG ADDRESS
ADD R2, C OPCODE ADDRESS REG
4-bit 2-bit 10-bit 16-bit Instruction
4-bit 10-bit 2-bit

REG ADDRESS OPCODE
OPCODE LOAD 0001

(4-bit) STORE 0010
2-bit 10-bit 4-bit ADD 0011
SUB 0100

REG Register 0 00
ADD R2, R3 OPCODE REG REG OPCODE REG REG (2-bit) Register 1 01
Register 2 10
4-bit 2-bit 2-bit 4-bit 2-bit 2-bit
Register 3 11

ADDRESS 10-bit Memory Word Address
Computer Architecture (E Edwards) 8.11 Computer Architecture (E Edwards) 8.12
Memory Placement (Program) Memory Placement (Data)
Assembly Machine Instruction Memory Assembly Data Memory
Instruction OP REG ADDRESS Address Instruction Address

LOAD R2, [201H] 0001 10 10 0000 0001 00 1000 0000 A=0 0000 0000 0000 0000 10 0000 0000
1 A 0 1 0 8 0 H 0 0 0 0 2 0 0 H

ADD R2, [202H] 0011 10 10 0000 0010 00 1000 0001 B=9 0000 0000 0000 1001 10 0000 0001
3 A 0 2 0 8 1 H 0 0 0 9 2 0 1 H

STORE R2, [200H] 0010 10 10 0000 0000 00 1000 0010 C=6 0000 0000 0000 0110 10 0000 0010
2 A 0 0 0 8 2 H 0 0 0 6 2 0 2 H

MEMORY MEMORY
Computer Architecture (E Edwards) 8.13 Computer Architecture (E Edwards) 8.14

CPU Organisation LOAD R2, [201H] R2=Memory[201H]

CPU R0 000 CPU 000
Address 001 001
R1
Bus 002 080H 002
R2 I 003 R2 003
R3 n
t
ALU e ALU
Input Reg1 Data
r Bus
Output Reg

080H
n RAM RAM
Input Reg2 a
l
Control 080H
Program Counter B Bus PC 080H 0
u
Instr. Decoder Instr. Register s Instr. Decoder
3FD 3FD

0
3FE 0 3FE
Control Unit 3FF Control Unit 3FF
1
Computer Architecture (E Edwards) 8.15 Computer Architecture (E Edwards) 8.16
LOAD R2, [201H] R2=Memory[201H] LOAD R2, [201H] R2=Memory[201H]
CPU 000 CPU 000
001 001
002 080H 002
080H
R2 003 R2 003

ALU ALU

RAM RAM

0
PC 080H + 1 0 PC 081H
Instr. Decoder Instr. Decoder
3FD 3FD
3FE 3FE
Control Unit 3FF Control Unit 3FF
2 3
Computer Architecture (E Edwards) 8.17 Computer Architecture (E Edwards) 8.18

LOAD R2, [201H] R2=Memory[201H] LOAD R2, [201H] R2=Memory[201H]

CPU 000 CPU 000
001 001
080H 201H
R2 R2
080 1A01H
1A01 080 1A01H
081 3A02H 081 3A02H

201H
ALU 082 2A00H ALU 082 2A00H
1A01H 1A01
RAM RAM

1A01H
200 0000 200 0000
0 201 0009 201 0009
PC 081H 202 0006 PC 081H 0 202 0006
1A01H
Instr. Decoder 1A01H 1A01H
3FD 3FD

0
1, 2, 201H 201H
3FE 3FE
Control Unit 3FF 1, 2, 201H 3FF
4 0 5
Computer Architecture (E Edwards) 8.19 Computer Architecture (E Edwards) 8.20
LOAD R2, [201H] R2=Memory[201H] ADD R2, [202H] R2=R2+Memory[202H]
CPU 000 CPU 000
201H 001 001
0009 201H 081H
R2 0009 R2 0009
080 1A01H 080 1A01H
081 3A02H 081 3A02H

081H
0009
ALU 082 2A00H ALU 082 2A00H
0009 0009
RAM RAM

200 0000 200 0000

0 201 0009
081H 201 0009
PC 081H 0 202 0006 PC 081H 0 202 0006

1A01H
3FD 3FD

0
3FE 0 3FE
1, 2, 201H 3FF 3FF
6 7
Computer Architecture (E Edwards) 8.21 Computer Architecture (E Edwards) 8.22

ADD R2, [202H] R2=R2+Memory[202H] ADD R2, [202H] R2=R2+Memory[202H]

CPU 000 CPU 000
001 001
081H
081H 0009 202H
R2 0009 R2 0009
0009

202H 0009
080 1A01H 080 1A01H
081 3A02H 081 3A02H
3A02
ALU 082 2A00H ALU 0009 082 2A00H
0009 3A02H 3A02H
RAM RAM

3A02H
200 0000 200 0000
201 0009 201 0009
PC 081H + 1 0 202 0006 PC 082H 0 0 202 0006
3A02H
3A02H 3A02H
3FD 3FD

0
3, 2, 202H 202H
3FE 3FE
3FF 3, 2, 202H 3FF
8 0 9
Computer Architecture (E Edwards) 8.23 Computer Architecture (E Edwards) 8.24
ADD R2, [202H] R2=R2+Memory[202H] STORE R2, [200H] Memory[200H]=R2
CPU 000 CPU 000
001 001
000FH 202H 202H 082H
R2 000FH
0009 R2 000FH

000FH
080 1A01 080 1A01H
081 3A02 081 3A02H

082H
ALU 082 2A00 ALU 082 2A00H
0009 0006 0006
000FH ADD RAM RAM

000FH
0006
000FH 0006
200 0000 200 0000
201 0009
082H 201 0009
PC 082H 0 0 202 0006 PC 082H 0 202 0006

3A02H
3FD 3FD

0
3FE 0 3FE
3, 2, 202H 3FF 3FF
10 11
Computer Architecture (E Edwards) 8.25 Computer Architecture (E Edwards) 8.26

STORE R2, [200H] Memory[200H]=R2 STORE R2, [200H] Memory[200H]=R2

CPU 000 CPU 000
001 001
082H 200H 082H
000FH

200H 000FH
R2 000FH R2 000FH
000F
080 1A01H 080 1A01H
081 3A02H 081 3A02H
ALU 082 2A00H ALU 082 2A00H
2A00
000FH 2A00H
RAM RAM

2A00H
200 0000 200 0000
201 0009 201 0009
PC 082H + 1 0 202 0006 PC 083H 1 1 202 0006
2A00H
2A00H 2A00H
3FD 3FD

1
2, 2, 200H 200H
3FE 3FE
3FF 2, 2, 200H 3FF
12 1 13
Computer Architecture (E Edwards) 8.27 Computer Architecture (E Edwards) 8.28
STORE R2, [200H] Memory[200H]=R2 Think About
CPU 000
Fetch-Execute Cycle
200H 200H 001

Assembly Languages
R2 000FH
080 1A01H
Program Representation: Instructions, Instruction Fields,
081 3A02H Instruction Formats
ALU 082 2A00H
00FH 00FH
CPU Components: Registers, ALU, Control Unit
RAM
Registers: General Purpose Registers, Program
Counter (PC), Instruction Register (IR),
200
ALU Registers
000FH
0000
1 1 201 0009
Buses: Internal, Address, Data, Control
PC 083H 202 0006

3FD
3FE
3FF
14
Computer Architecture (E Edwards) 8.29 Computer Architecture (E Edwards) 8.30