HDL T.-C.

Huang / NCUE Fall 2005 1

Hardware Descriptin Language
-- Lgic Design using !erilg
Tsung-C"u Huang
Dept. # Electrnic Eng.
Natinal C"ang"ua Uni$ersit% # Ed.
E&ail' tc"(cc.ncue.edu.tw
2011/11/0)
HDL T.-C. Huang / NCUE Fall 2005 2
Tutrial using NC*i&

+uic, -ntr. t Cadence Nati$e C&piled .rc"itecture

VHDL
VHDL
VHDL
VHDL
!
!
!
!
!
Compile
tp
Elaborate Simulate
nclaunc" /
HDL T.-C. Huang / NCUE Fall 2005 )
+uic, Tutrial
NCSim
1. NCLunch
2. File Switch to multiple step Set desin director! Create cds.lib
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+uic, Tutrial
NCSim
". File Edit new #ile
$. Select #ile%s& b! riht button Edit
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NCSim
'. File Edit the test(bench #ile
). %I& For simple tas*s+ File Switch to sinle step
a. ,ress Ctrl *e! to select #ile%s&+ press - to mo.e desin #iles riht
b. Launch the airplane
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NCSim
). %II& For /ultiple Lanuae or 0eusin the database Switch to multiple
step
a. Select Verilo desin #iles 1ools Verilo Compiler
b. Select VHDL desin #iles 1ools VHDL Compiler
NCLaunch enerates
nati.e compiled database
in wor*lib and snapshot
#or latter iterati.e use.
Select the top module in
the wor*lib or snapshot+
and then 1ools
Elaborate
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NCSim
c. 1ools Simulator Selected the simulated snapshot #ile
2. Select the le.el and instance and press SimVision
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NCSim
3. ,ress ,L45 - to simulate+ sa.e as VCD #ile #or later use.
6. Debu and edit
17. No need to compile other #iles under the Nati.e Compiled 4rchitecture
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NCSim
11. /ar* time usin 8e.ent to measure time.
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NCSim
11. 0eport the result in SimVision or nc.erilo.lo
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+uic, Tutrial
NCSim
12. 9se repeat %times&+ #or loop to repeat+ s*ip or measure the nth .ariables.
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NCSim
12. :t;s con.enient #or dela! .ariable circuits+ such as VC<+ VCD+ ,=/+ S/D
and dela! line.