module fulladder_ffr(a,b,c,s,ca);

input a,b,c;
output s,ca;
wire s,ca,w1,w2,w3,w4,w6,w7,w5;
wire n1,n2,n3;
not(n1,a);
not(n2,b);
not(n3,c);
and(w1,n1,n2,c);
and(w2,n1,b,n3);
and(w3,a,n2,n3);
and(w4,a,b,c);
and(w5,b,c);
and(w6,c,a);
and(w7,a,b);
or(s,w1,w2,w3,w4);
or(ca,w5,w6,w7);
endmodule
module fulladder_f1(a,b,c,s,ca);
input a,b,c;
output s,ca;
wire s,ca,w1,w2,w3,w4,w6,w7,w5,w;
wire n1,n2,n3;
not(n1,a);
not(n2,b);
not(n3,c);
or(w,1'b1,n2);
and(w1,n1,w,c);
and(w2,n1,b,n3);
and(w3,a,n2,n3);
and(w4,a,b,c);
and(w5,b,c);
and(w6,c,a);
and(w7,a,b);
or(s,w1,w2,w3,w4);
or(ca,w5,w6,w7);
endmodule
module fulladder_f2(a,b,c,s,ca);
input a,b,c;
output s,ca;
wire s,ca,w1,w2,w3,w4,w6,w7,w5,w;
wire n1,n2,n3;
not(n1,a);
not(n2,b);
not(n3,c);
and(w,1'b0,n2);
and(w1,n1,n2,c);
and(w2,w,b,n3);
and(w3,a,n2,n3);
and(w4,a,b,c);
and(w5,b,c);
and(w6,c,a);
and(w7,a,b);
or(s,w1,w2,w3,w4);
or(ca,w5,w6,w7);
endmodule
module fulladder_f3(a,b,c,s,ca);

input a,b,c;
output s,ca;
wire s,ca,w1,w2,w3,w4,w6,w7,w5,w;
wire n1,n2,n3;
not(n1,a);
not(n2,b);
not(n3,c);
and(w,1'b0,n3);
and(w1,n1,n2,c);
and(w2,w,b,n3);
and(w3,a,n2,w);
and(w4,a,b,c);
and(w5,b,c);
and(w6,c,a);
and(w7,a,b);
or(s,w1,w2,w3,w4);
or(ca,w5,w6,w7);
endmodule
module fulladder_f4(a,b,c,s,ca);
input a,b,c;
output s,ca;
wire s,ca,w1,w2,w3,w4,w6,w7,w5,w;
wire n1,n2,n3;
not(n1,a);
not(n2,b);
not(n3,c);
or(w,1'b1,b);
and(w1,n1,w,c);
and(w2,n1,b,n3);
and(w3,a,n2,n3);
and(w4,a,b,c);
and(w5,w,c);
and(w6,c,a);
and(w7,a,b);
or(s,w1,w2,w3,w4);
or(ca,w5,w6,w7);
endmodule
module fulladder_f5(a,b,c,s,ca);
input a,b,c;
output s,ca;
wire s,ca,w1,w2,w3,w4,w6,w7,w5,w;
wire n1,n2,n3;
not(n1,a);
not(n2,b);
not(n3,c);
or(w,1'b1,c);
and(w1,n1,w,c);
and(w2,n1,b,n3);
and(w3,a,n2,n3);
and(w4,a,b,c);
and(w5,b,c);
and(w6,w,a);
and(w7,a,b);
or(s,w1,w2,w3,w4);
or(ca,w5,w6,w7);
endmodule
module fulladder_f6(a,b,c,s,ca);

input a,b,c;
output s,ca;
wire s,ca,w1,w2,w3,w4,w6,w7,w5,w;
wire n1,n2,n3;
not(n1,a);
not(n2,b);
not(n3,c);
and(w,1'b0,b);
and(w1,n1,n2,c);
and(w2,w,b,n3);
and(w3,a,n2,n3);
and(w4,a,b,c);
and(w5,b,c);
and(w6,c,a);
and(w7,a,w);
or(s,w1,w2,w3,w4);
or(ca,w5,w6,w7);
endmodule
module fulladder_faultanalysis(a,b,c,s,ca,s1,ca1,s2,ca2,s3,ca3,s4,ca4,s5,ca5,s6,
ca6);
input a,b,c;
output s,ca,s1,ca1,s2,ca2,s3,ca3,s4,ca4,s5,ca5,s6,ca6;
wire s,ca,s1,ca1,s2,ca2,s3,ca3,s4,ca4,s5,ca5,s6,ca6;
fulladder_ffr i0(.a(a),.b(b),.c(c),.s(s),.ca(ca));
fulladder_f1 i1(.a(a),.b(b),.c(c),.s(s1),.ca(ca1));
fulladder_f2 i2(.a(a),.b(b),.c(c),.s(s2),.ca(ca2));
fulladder_f3 i3(.a(a),.b(b),.c(c),.s(s3),.ca(ca3));
fulladder_f4 i4(.a(a),.b(b),.c(c),.s(s4),.ca(ca4));
fulladder_f5 i5(.a(a),.b(b),.c(c),.s(s5),.ca(ca5));
fulladder_f6 i6(.a(a),.b(b),.c(c),.s(s6),.ca(ca6));
endmodule
module fulladder_testanalysis();
reg a,b,c;
wire s,ca,s1,ca1,s2,ca2,s3,ca3,s4,ca4,s5,ca5,s6,ca6;;
fulladder_faultanalysis a1(.a(a),.b(b),.c(c),.s(s),.ca(ca),.s1(s1),.ca1(ca1),.s2
(s2),.ca2(ca2),.s3(s3),.ca3(ca3),.s4(s4),.ca4(ca4),.s5(s5),.ca5(ca5),.s6(s6),.ca
6(ca6));
initial
begin
#20
a=1'b0;
b=1'b0;
c=1'b0;
#20
c=1'b1;
#20
b=1'b1;
c=1'b0;
#20
c=1'b1;
#20
a=1'b1;
b=1'b0;
c=1'b0;
#20
c=1'b1;
#20
b=1'b1;

c=1'b0;
#20
c=1'b1;
#20;
end
initial
#100 $stop;
endmodule