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Term paper :-Advantages of PAL

Digital Electronics fundamentals (ECE 202)
Varun chadha

A01

+919464193411

Submitted to:- Mr. Randhir Singh

Introduction[4][6]

The term Programmable Array Logic (PAL) is used to describe a family of programmable
logic device semiconductors used to implement logic functions in digital circuits introduced
by Monolithic Memories, Inc. (MMI) in March 1978.

PAL devices consisted of a small PROM (programmable read-only memory) core and
additional output logic used to implement particular desired logic functions with few
components.

Using specialized machines, PAL devices were "field-programmable". Each PAL device was
"one-time programmable" (OTP), meaning that it could not be updated and reused after its
initial programming.

PALs were programmed electrically using binary patterns (as JEDEC ASCII/hexadecimal
files) and a special electronic programming system available from either the manufacturer or
a third-party, such as DATA/IO. In addition to single-unit device programmers, device
feeders and gang programmers were often used when more than just a few PALs needed to be
programmed. (For large volumes, electrical programming costs could be eliminated by
having the manufacturer fabricate a custom metal mask used to program the customers'
patterns at the time of manufacture; MMI used the term "hard array logic" (HAL) to refer to
devices programmed in this way.)

History of PAL[4]

Before PALs were introduced, designers of digital logic circuits would use small-scale
integration (SSI) components, such as those in the 7400 series TTL (transistor-transistor
logic) family; the 7400 family included a variety of logic building blocks, such as gates
(NOT, NAND, NOR, AND, OR), multiplexers (MUXes) and demultiplexers (DEMUXes),
flip flops (D-type, JK, etc.) and others. One PAL device would typically replace dozens of
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such "discrete" logic packages, so the SSI business went into decline as the PAL business
took off. PALs were used advantageously in many products, such as minicomputers, as
documented in Tracy Kidder's best-selling book "The Soul of a New Machine."

PALs were not the first commercial programmable logic devices; Signetics had been selling
its field programmable logic array (FPLA) since 1975. These devices were completely
unfamiliar to most circuit designers and were perceived to be too difficult to use. The FPLA
had a relatively slow maximum operating speed (due to having both programmable-AND and
programmable-OR arrays), was expensive, and had a poor reputation for testability. Another
factor limiting the acceptance of the FPLA was the large package, a 600-mil (0.6", or 15.24
mm) wide 28-pin dual in-line package (DIP).

The project to create the PAL device was managed by John Birkner and the actual PAL
circuit was designed by H. T. ChuaIn a previous job, Mr. Birkner had developed a 16-bit
processor using 80 standard logic devices. His experience with standard logic led him to
believe that user programmable devices would be more attractive to users if the devices were
designed to replace standard logic. This meant that the package sizes had to be more typical
of the existing devices, and the speeds had to be improved.

Programming languages[4]

Though some engineers programmed PAL devices by manually editing files containing the
binary fuse pattern data, most opted to design their logic using a hardware description
language (HDL or VHDL) such as Data I/O's ABEL, Logical Devices' CUPL, or MMI's
PALASM. These were computer-assisted design (CAD) (now referred to as "design
automation") programs which translated (or "compiled") the designers' logic equations into
binary fuse map files used to program (and often test) each device

Explaination Of PAL[1][2][5]

In a PAL device only AND gates are programmable. The OR array in this device is fixed by
the manufacturer. This makes PAL devices easier to program and less expensive than PLA.
On the other hand, since the OR array is fixed, it is less flexible than a PLA device.

Figure A
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Figure B:

Figure B: represents the general structure of a PAL device. It has n input lines which are fed
to buffers/inverters. Buffers/inverters are connected to inputs of AND gates through
programmable links. Outputs of AND gates are then fed to the OR array with fixed
connections. It should be noted that, all the outputs of an AND array are not connected to an
OR array. In contrast to that, only some of the AND outputs are connected to an OR array
which is at the manufacturer's discretion. This can be clarified by Figure 6.23, which
illustrates the internal connection of a four-input, eight AND-gates and three-output PAL
device before programming. Note that while every buffer/inverter is connected to AND gates
through links, F1-related OR gates are connected to only three AND outputs, F2 with three
AND gates, and F3 with two AND gates. So this particular device can generate only eight
product terms, out of which two of the three OR gates may have three product terms each and
the rest of the OR gates will have only two product terms. Therefore, while designing with
PAL, particular attention is to be given to the fixed OR array.
The PAL device is a special case of PLA which has a programmable AND array
and a fixed OR array. The basic structure of PAL is same as PLA. It is cheap compared to
PLA as only the AND array is programmable. It is also easy to program a PAL compared to
PLA as only AND must be programmed. The figure 1 below shows a segment of an
unprogrammed PAL. The input buffer with non inverted and inverted outputs is used, since
each PAL must drive many AND Gates inputs. When the PAL is programmed, the fusible
links (F1, F2, F3…F8) are selectively blown to leave the desired connections to the AND
Gate inputs. Connections to the AND Gate inputs in a PAL are represented by Xs, as shown
here:
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Figure 1: segment of an unprogrammed and programmed PAL.

As an example, we will use the PAL segment of figure 1 to realize the function I1I2’+I1I2.
the Xs indicate that the I1 and I2’ lines are connected to the first AND Gate, and the I1’ and
I2 lines are connected to the other Gate. Typical combinational PAL have 10 to 20 inputs and
from 2 to 10 outputs with 2 to 8 AND gates driving each OR gate. PALs are also available
which contain D flip-flops with inputs driven from the programming array logic. Such PAL
provides a convenient way of realizing sequential networks. Figure 2 below shows a segment
of a sequential PAL. The D flip-flop is driven from the OR gate, which is fed by two AND
gates. The flip-flop output is fed back to the programmable AND array through a buffer.
Thus the AND gate inputs can be connected to A, A’, B, B’, Q, or Q’. The Xs on the diagram
show the realization of the next-state equation.

Q+ = D = A’BQ’ + AB’Q

The flip-flop output is connected to an inverting tristate buffer, which is enabled when EN =
1

Figure 2 Segment of a Sequential PAL

Figure 3 below shows a logic diagram for a typical sequential PAL, the 16R4. This PAL has
an AND gate array with 16 input variables, and it has 4 D flip-flops. Each flip-flop output
goes through a tristate-inverting buffer (output pins 14-17). One input (pin 11) is used to
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enable these buffers. The rising edge of a common clock (pin 1) causes the flip-flops to
change the state. Each D flip-flop input is driven from an OR gate, and each OR gate is fed
from 8 AND gates. The AND gate inputs can come from the external PAL inputs (pins2-9) or
from the flip-flop outputs, which are fed back internally. In addition there are four
input/output (i/o) terminals (pins 12,13,18 and 19), which can be used as either network
outputs or as inputs to the AND gates. When used as an output, each I/O terminal is driven
from an inverting tristate buffer. Each of these buffers is fed from an OR gate and each OR
gate is fed from 7 AND gates. An eighth AND gate is used to enable the buffer.
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Figure 3: logic diagram for 16R4 pal

When the 16R4 PAL is used to realize a sequential network, the I/O terminals are
normally used for the z outputs. Thus, a single 16R4 with no additional logic could
realize a sequential network with up to 8 inputs, 4 outputs, and 16 states. Each next state
equation could contain up to 8 terms, and each output equation could contain up to 7 terms.
As an example, we will realize the BCD to Excess-3 code converter using three flip-flops to
store Q1,Q2 and Q3, and the array logic that drives these flip-flops is programmed to realize
D1, D2 and D3, as shown in figure 3 .The Xs on the diagram indicate the connections to the
AND-gate inputs. An X inside an AND gate indicates that the gate is not used. For D3, three
AND gates are used, and the function realized is

D3 = Q1Q2Q3 + X’Q1Q3’ + XQ1’Q2’

The flip-flop outputs are not used externally, so the output buffers are disabled. Since the Z
output comes through the inverting buffer, the array logic must realize

Z’ = (X + Q3)(X’ + Q3’) = XQ3’ + X’Q3

The z output buffer is permanently enabled in this example, so there are no connections to the
AND gate that drives the enable input, in which case the AND gate output is logic1. When
designing with PALS, we must simplify our logic equations and try to fit them in
one or more PALs. Unlike the more general PLA, the AND terms cannot be shared among
two or more OR gates; therefore, each function to be realized can be simplified by itself
without regard to common terms. For a given type of PAL the number of AND terms that
feed each output OR gate is fixed and limited. If the number of AND terms in a simplified
function is too large, we may be forced to choose a PAL with more OR-gate
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inputs and fewer outputs.

Computer aided design programs for PAL s are widely available. Such programs accept logic
equations, truth tables, state graphs, or state tables as inputs and automatically generate the
required fused patterns. These patterns can then be downloaded into a PLD programmer,
which will blow the required, fuses and verify the operation of the PAL.

Advantages Of PAL[3][7]

• Less board space

• Fewer printed circuit board

• Smaller enclosures

• Lower power requirements(i.e. smaller power supplies)

• Faster and less costly assembly processes

• Higher reliabilty(fewer ICs and circuit connections=>easier troubleshooting)

• Availability of design software

• Increase in speed

• Better security(copying is less likely to take place)

• Low production cost as compare to PLA

• More flexibility to designer

• Modification can be carried out within a short span of time

• Implementation of combinational and sequential circuits can be done with the help of
PAL.

• For given internal complexity, a PAL can have larger inputs and implement a number
of functions.
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• Some PALs have outputs that can be complemented, adding POS functions

• PALs do not require long lead times for prototypes or production parts - the PALs are
already on a distributor's shelf and ready for shipment.

• No multilevel circuit implementations in ROM (without external connections from

output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits easier.

• PALs allow customers to order just the number of parts they need, when they need
them, allowing them to control inventory. Customers who use fixed logic devices
often end up with excess inventory which must be scrapped, or if demand for their
product surges, they may be caught short of parts and face production delays.
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Conclusion

The value of programmable logic has always been its ability to shorten development cycles
for electronic equipment manufacturers and help them get their product to market faster. As
PAL suppliers continue to integrate more functions inside their devices, reduce costs, and
increase the availability of time-saving IP cores, programmable logic is certain to expand its
popularity with digital designers.
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References

[1] .http://www.globalspec.com/reference/4276/348308/Section-6-5-Programmable-Array-
Logic-PAL-Devices

[2.]
http://forum.vtu.ac.in/~edusat/vhdl/krs/PROGRAMMABLE_ARRAY_LOGIC_VHDL_eNot
es.pdf

[3] .http://www.writphotec.com/mano4/PowerPoint_Slides/LCDF4_Chap_06_P4.ppt

[4]. http://en.wikipedia.org/wiki/Programmable_array_logic

[5] .http://www.scribd.com/doc/6567667/Programmable-Array-Logic-Vhdl-Enotes

[6] .http://www.scribd.com/doc/4139730/Programmable-Logic-and-Software

[7] DIGITAL CIRCUITS AND LOGIC DESIGN by J.S.Katre