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Compal Confidential
2

JALA0 M/B Schematics Document


Intel Penryn Processor with Cantiga + DDRII + ICH9M
(With Ati & nVidia MXM/B)

2008-04-18

REV:1.0

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
E

of

50

Compal Confidential
page 36

uPGA-478 Package
(Socket P) page

HDMI Conn.

LCD Conn.

page 20

CRT Conn.

page 18

page 16

4,5,6
1

H_D#(0..63)

page 19

Memory BUS(DDRII)

Intel Cantiga
(PM / GM / GL)

LVDS
SDVO

CH7318
(HDMI/B)
page 25

PCI-Express
16X

MXM II VGA/B

BANK 0, 1, 2, 3

DMI

1.8V DDRII 667 / 800

C-Link

USB conn x2

Bluetooth
Conn

USB port 0, 2

page 17

PCI-Express

Intel ICH9-M

Card Reader

3.3V 48MHz

S-ATA

MINI Card x2
5 in 1
socket

WLAN, Robson2

port 0

port 1

SATA HDD
Conn. page

RJ45

30

CDROM
Conn. page

page 33

DC/DC Interface CKT.

HDA Codec
ALC268
page 34

PCI Bus

30

3.3V 33MHz

Audio AMP
page 35

SPI FLASH ROM (2MB)


ME for iTPM only page 23

CardBus

PWR/B Conn.

Power On/Off CKT.

MDC 1.5
Conn
page 33

page 08

page 28

page 22

HD Audio

GMCH HDA

page 27

page 38

RTC CKT.

Upek TCS4EA

page 21,22,23,24

Broadcom
BCM5764M

page 26

DOCKING
(DVI/LAN/
CRT/USB/AUDIO)

Finger Print

BGA-676

LAN(GbE)

page 29

CMOS
Camera

USB

3.3V 24.576MHz/48Mhz

JMB385
page 26

page 14,15

page 7,8,9,10,11,12,13

nVidia 9MGS(256MB/GDDR2)
nVidia 9PGE2(256MB/GDDR3)
Ati M82M(256MB/GDDR2)
2

200pin DDRII-SO-DIMM X2

Dual Channel

uFCBGA-1329

LVDS
TMDS

Clock Generator
ICS9LPRS387

page 4

FSB
667/800/1066MHz

H_A#(3..35)

Thermal Sensor
SMSC EMC1402-1

Intel Penryn Processor

Fan Control

Model Name : JALA0


File Name : LA-4221P

OZ601

LPC BUS

page 25

page 32

ENE KB926

FUN/B Conn.
SPI FLASH ROM (2MB)
EC BIOS / SYS BIOS / FP(PBA)
page
/ HDCP

USB/B Conn.

page 35

Slot 0

page 31

page 32

Phone Jack x3

page 25

32

USB port 4
page 37

Int.KBD

Touch Pad

page 29

page 32

Power Circuit DC/DC

EC I/O Buffer

page 39,40,41,42
43,44,45,46

page 32

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


E

of

50

SIGNAL

STATE

Voltage Rails

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

Power Plane

Description

S1

S3

S5

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

VIN

Adapter power supply (19V)

N/A

N/A

N/A

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

+0.9VS

0.9V switched power rail for DDR terminator

ON

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

+1.05VS

1.05V switched power rail

ON

OFF

OFF

+1.25VS

1.25V switched power rail

ON

OFF

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+1.8V

1.8V power rail for DDR

ON

ON

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

Vcc
Ra/Rc/Re

+2.5VS

2.5V switched power rail

ON

OFF

OFF

Board ID

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V

3.3V power rail for SB

ON

ON

+3V_LAN

3.3V power rail for LAN

ON

ON

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

0
1
2
3
4
5
6
7

Full ON

Board ID / SKU ID Table for AD channel


3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID Table
Board ID
0
1
2
3
4
5
6
7

External PCI Devices


Device

IDSEL#
AD16

Cardbus OZ601

EC SM Bus1 address
3

REQ#/GNT#

Interrupts
PIRQE

Address

Device

Address

Smart Battery

0001 011X b

ADT7421

1001 100X b

(LAN BCM5764M)

Reserved

GPU(MXM/B)

PCB Revision
0.1
0.2
0.3
1.0
1A

BTO Item
BOM Structure
Discrete_H
PM@
UMA
GM@
UMAGM@
UMA_H
UMA_L
UMAGL@
Kinabalu_H
MAIN@
Kinabalu_L
VALUE@
RTC Batt
45@
ICH9M BASE
ICH9MB@
ICH9M ENHANCE ICH9ME@
SB ROM(2MB)
SPI2MB@
SB ROM(4MB)
SPI4MB@

EC SM Bus2 address

Device

EEPROM(24C16/02) 1010 000X b

BTO Option Table

Kinabalu_L : UMA(GL) & w/o Dock & w/o Mini card 2


& w/o iTPM

1001 111X b

ICH9M SM Bus address


Device

Address

Clock Generator
(ICS9LPRS387)

1101 001Xb

DDR DIMM0

1001 000Xb

DDR DIMM1

1001 010Xb

LAN BCM5764M

Reserved

(MINI CARD_WL_Robson)

Reserved

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


E

of

50

H_A#[3..35]

H_A#[3..35]

H_REQ#[0..4]

7 H_REQ#[0..4]
7

H_RS#[0..2]

H_RS#[0..2]

JCPU1A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

K3
H2
K2
J3
L1

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

H_A20M#
H_FERR#
H_IGNNE#

A6
A5
C4

H_STPCLK#
H_INTR
H_NMI
H_SMI#

D5
C6
B4
A3

7
22
22
22
22
22
22
22

A20M#
FERR#
IGNNE#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

H1
E2
G5

H_ADS#
H_BNR#
H_BPRI#

H5
F21
E1

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

F1

IERR#
INIT#

D20
B3

LOCK#

H4

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

C1
F3
F4
G3
G2

HIT#
HITM#

G6
E4

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

7
7
7

H_BR0#

H_INIT#

22

H_IERR#

H_LOCK# 7
H_RESET#
H_RS#0
H_RS#1
H_RS#2

H_RESET# 7

H_TRDY# 7
H_HIT#
H_HITM#

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

7
7

XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_DBRESET#

XDP_DBRESET# 23
1.05VS

THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#

H_PROCHOT#
H_THERMDA_R
H_THERMDC_R

D21
A24
B25
C7

DVT

XDP_TDI
H_THERMTRIP# 8,22
XDP_TMS

STPCLK#
LINT0
LINT1
SMI#

M4
N5
T2
V3
B2
D2
D22
D3
F6

CONTROL

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

ICH

H_ADSTB#1

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

BR0#

ADDR GROUP_1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

DEFER#
DRDY#
DBSY#

XDP/ITP SIGNALS

H_ADSTB#0

ADS#
BNR#
BPRI#

BCLK[0]
BCLK[1]

DVT

XDP_BPM#5

H CLK
A22
A21

R25

54.9_0402_1%

R18

54.9_0402_1%

R10

54.9_0402_1%

left NC if no ITP

DEL_DVT(ESD)

CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16

RESERVED

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP_0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_PROCHOT#

R42

56_0402_5%

H_IERR#

R41

56_0402_5%

XDP_TRST#

R11

54.9_0402_1%

XDP_TCK

R9

54.9_0402_1%

Layout Note:
H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil

39Ohm

DVT
B

Penryn
CONN@
3VS
C107
0.1U_0402_16V4Z
1
2

JALA0

BSEL1

BSEL0

BCLK

266

1.05VS
H_THERMDA_R

R56
1

R64
0_0402_5% 10K_0402_5%
2 H THERMDA

DVT
@
U9

1
C108

R60
56_0402_5%
@

200
2

BSEL2

166

H_THERMDC_R

H_PROCHOT#

R55
1

2200P_0402_50V7K
2
0_0402_5%
2 H THERMDC

THERM#

DVT
OCP#

23

DVT(JALA0)

Q5
MMBT3904_SOT23-3
@

VDD

SCLK

D+

SDATA

D- ALERT/THERM2

THERM

GND

EC_SMB_CK2 27,31
EC_SMB_DA2 27,31

1
2
@ R652
10K_0402_5%

EMC1402-1-ACZL-TR_MSOP8

2007/09/20

Issued Date

Deciphered Date

Compal Electronics, Inc.


2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SMSC : SA00001Z700(S IC EMC1402-1-ACZL-TR MSOP 8P SENSOR)

Compal Secret Data

Security Classification

3VS

DVT(JALA0)

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

of

50

H_D#[0..63]

H_D#[0..63]

7
7
7

H_DSTBN#0
H_DSTBP#0
H_DINV#0

1.05VS

7
7
7

R318
1K_0402_1%

R366
R365

Trace Close CPU < 0.5'

R319
2K_0402_1%

GTL_REF0
TEST1
1 @ 1K_0402_5%
TEST2
1 @ 1K_0402_5%
TEST3
PAD @
T3
2 @ 0.1U_0402_16V4Z TEST4
TEST5
PAD @
T2
@
TEST6
T18 PAD

2
2

C385 1

Width=4 mil ,
Spacing: 15mil
(55Ohm)

H_DSTBN#1
H_DSTBP#1
H_DINV#1

16
16
16

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

DATA GRP 2

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

DATA GRP 1

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

DATA GRP 3

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

DATA GRP 0

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

JCPU1C

7
CPU_CORE

JCPU1B

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7
COMP0
COMP1
COMP2
COMP3

R334
R330
R12
R15

1
1
1
1

H_PWRGOOD
H_CPUSLP#

2
2
2
2

27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%

H_DPRSTP# 8,22,46
H_DPSLP# 22
H_DPWR# 7
H_PWRGOOD 22
H_CPUSLP# 7
PSI#
46

Penryn
CONN@

TRACE CLOSELY CPU < 0.5'


COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn
CONN@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VSSSENSE

AE7

VSSSENSE

CPU_CORE
D

1.05VS

20mils
1.5VS
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
1
R315

C102
46
46
46 0.01U_0402_16V7K
2
2
46
46
10U_0805_10V4Z
46
46
2
CPU_CORE
100_0402_1%

VCCSENSE 46
VSSSENSE 46

1
R316

1
C101

2
100_0402_1%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

of

50

CPU_CORE

CPU_CORE

2 x 330uF(6mOhm/2)
JCPU1D

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
Penryn
CONN@

1
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

C380

2 x 330uF(6mOhm/2)

C2

330U_D2E_2.5VM_R9
2

C106

330U_D2E_2.5VM_R9
2

C381

330U_D2E_2.5VM_R9
2

330U_D2E_2.5VM_R9
2
D

South Side Secondary

North Side Secondary

CPU_CORE

C407

C406

C397

C73

C74

C66

C29

C400

10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
2
2
2
2
2
2
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M

(Place these capacitors on South side,Secondary Layer)


CPU_CORE

C15

C14

C13

C12

C11

C395

C398

C90

10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
2
2
2
2
2
2
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
C

(Place these capacitors on North side,Secondary Layer)


CPU_CORE

C89

C88

C87

C86

C394

C390

C67

C30

10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
2
2
2
2
2
2
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M

(Place these capacitors on South side,Primary Layer)


CPU_CORE

C399

C396

C392

C393

C403

C391

C404

C405

10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
2
2
2
2
2
2
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M

(Place these capacitors on North side,Primary Layer)

+CPU-CORE
Decoupling
SPCAP,Polymer
MLCC 0805 X5R

C,uF

ESR, mohm

ESL,nH

4X330uF

6m ohm/4

1.8nH/6

32X22uF

3m ohm/32

0.6nH/32

32X10uF

3m ohm/32

0.6nH/32

1.05VS

1
.

+ C33

C17

1
C52

C79

C72

C63

C85

330U_D2E_2.5VM_R15
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

of

50

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

1.05VS

R88

221_0402_1%
H_SWING

wid h=10mil
1

R87

C164
0.1U_0402_16V4Z

100_0402_1%

H_RCOMP

wid h=10mil
R409

24.9_0402_1%

H_SWING
H_RCOMP

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C5
E3

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP

1.05VS

H_A#[3..35]

U30A

H_D#[0..63]

R100

4
5

H_RESET#
H_CPUSLP#

1K_0402_1%

wid h:spacing=10mil:20mil (<0.5")


R96

H_RESET#
H_CPUSLP#

C12
E11

H_AVREF

A11
B11

C172

H_CPURST#
H_CPUSLP#

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

J8
L3
Y13
Y1

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

L10
M7
AA5
AE6

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

L9
M8
AA6
AE5

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

B15
K13
F13
B13
B14

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#_0
H_RS#_1
H_RS#_2

B6
F12
C8

H_RS#0
H_RS#1
H_RS#2

H_AVREF
H_DVREF

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0#
4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 16
CLK_MCH_BCLK# 16
H_DPWR# 5
H_DRDY# 4
H_HIT#
4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

5
5
5
5

5
5
5
5
B

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5
H_REQ#[0..4]

H_RS#[0..2]

CANTIGA ES_FCBGA1329
UMAGM@

0.1U_0402_16V4Z

2K_0402_1%

HOST

DVT

CANTIGA GM: SA00001P930


(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)

PVT

CANTIGA GM: SA00002JT10


(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)

within 100mil to Ball A9,B9

PVT2 CANTIGA GM: SA00002JT50


(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM)

Pre-MP CANTIGA GM: SA00002JTB0


(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)
Security Classification
Compal Secret Data
2007/09/20

Issued Date

Deciphered Date

Compal Electronics, Inc.


2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

of

50

+1.8V

+1.05VS

R681
1K_0402_1%

BG23
BF23
BH18
BF18

RSVD22
RSVD23
RSVD24
RSVD25

R683
1K_0402_1%

NC
GND
+1.05VS
+3VS

8
7
6
5

TDO
TCK
TMS
TDI

JTAG CONN
JTAG@

R684
0_0402_5%

MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_9
MCH_CFG_10

Use VGATE for GMCH_PWROK


VGATE

GMCH_PWROK
2
@ 0_0402_5%
2
0_0402_5%

1
R182
ICH_PWROK 1
R183

16,23,46 VGATE
23 ICH_PWROK

MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

CFG

2 PM_EXTTS#0
10K_0402_5%
2 PM_EXTTS#1
10K_0402_5%
2 MCH_CLKREQ#
10K_0402_5%

1
R142
1
R145
1
R151

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

BC28
AY28
AY36
BB36

DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

BA17
AY16
AV16
AR13

DDRA_SCS0#
DDRA_SCS1#
DDRB_SCS0#
DDRB_SCS1#

SA_ODT_0
SA_ODT_1
SB_ODT_O
SB_ODT_1

BD17
AY17
BF15
AY13

DDRA_ODT0
DDRA_ODT1
DDRB_ODT0
DDRB_ODT1

SM_RCOMP
SM_RCOMP#

BG22
BH21

SMRCOMP
SMRCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

BF28
BH28

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

AV42
AR36
BF17
BC36

R438 1
R437 1

1
1K_0402_1%
2

14
14
15
15

1
R442

14
14
15
15
14
14
15
15

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

CLK_DREF_96M
CLK_DREF_96M#
CLK_DREF_SSC
CLK_DREF_SSC#

PEG_CLK
PEG_CLK#

F43
E43

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

AE41
AE37
AE47
AH39

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AE40
AE38
AE48
AH40

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

AE35
AE43
AE46
AH42

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

AD35
AE44
AF46
AH43

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

R29
B7
N33
P32
AT40
AT11
T20
R32

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

2
B

E
Q24
MMBT3904_SOT23-3

Q25
MMBT3904_SOT23-3

2
B
3

330_0402_5%

2
1

R425
2

MCH_TSATN_EC# 31
1

1
R429
54.9_0402_1%

R441

14
14
15
15

+1.8V

+1.8V

2 80.6_0402_1%
2 80.6_0402_1%

0.01U_0402_16V7K
D

C484
0.01U_0402_16V7K

JALA0

R187
1K_0402_1%

DVT

C227

1
2
+DIMM_VREF
R185 0_0402_5%

R180
1K_0402_1%

0.1U_0402_16V4Z
2

CLK_DREF_96M 16
CLK_DREF_96M# 16
CLK_DREF_SSC 16
CLK_DREF_SSC# 16

C483
<BOM Structure>
2.2U_0603_6.3V6K
2

1K_0402_1%

CLK_DREF_96M
CLK_DREF_96M#

R528 1
R527 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

CLK_DREF_SSC
CLK_DREF_SSC#

R526 1
R525 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

as close as possible to the related balls

CLK_MCH_3GPLL 16
CLK_MCH_3GPLL# 16

Strap Pin Table

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

23
23
23
23

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

23
23
23
23

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

23
23
23
23

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

23
23
23
23

PVT2 CANTIGA GM: SA00002JT50


(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM)

DVT
PVT

0 = DMI x 2
1 = DMI x 4

CFG5

B33
B32
G33
F33
E33

GFX_VR_EN

C34

CFG9

1 = iTPM Host Interface is Disabled


0 = Lane Reversal Enable
1 = Normal Operation * (Default)

CFG10

0 = PCIe Loopback Enable


1 = Disable * (Default)
01
00
10
11

CFG[13 12]

CFG20
(PCIE/SDVO select)

ICH_PWROK

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#

N28
M28
G36
E36
K36
H36

SDVO_SCLK
SDVO_SDATA
MCH_CLKREQ#

TSATN#

B12

MCH_TSATN#

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

B28
B30
B29
C29
A28

HDA_BITCLK_MCH
HDA_RST_MCH#
HDA_SDIN2_MCH
HDA_SDOUT_MCH
HDA_SYNC_MCH

DDPC CTRLDATA

0 = Digital DisplayPort Disable


* (Default)
1 = Digital DisplayPort Device Present

JALA0 (MCH Enable Strap for iTPM)

CL_RST#0 23

CL_VREF

MCH_CFG_5
MCH_CFG_6

C210 1

R154
511_0402_1%

MCH_CFG_7
MCH_CFG_9

SDVO_SCLK 17
SDVO_SDATA 17
MCH_CLKREQ# 16
MCH_ICH_SYNC# 23

0.1U_0402_16V4Z
2

MCH_CFG_10
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16

CANTIGA GM: SA00001P930


(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)
CANTIGA GM: SA00002JT10
(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)

1 GM@ 2
33_0402_5%
HDA_SDOUT_MCH 22 R126
HDA_SYNC_MCH 22

HDA_SDIN2 22

MCH_CFG_19
MCH_CFG_20

2008/09/20

Deciphered Date

1
@ 4.02K_0402_1%
1
@ 4.02K_0402_1%

+3VS

Title

SCHEMATIC MB A4221

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
C

401552

Date

2
R121
2
R120

Compal Electronics, Inc.

Compal Secret Data


2007/09/20

Issued Date

2
1
R134
@ 2.21K_0402_1%
2
1
R113 MAIN@ 2.21K_0402_1%
2
1
R118
@ 2.21K_0402_1%
2
1
R127
@ 2.21K_0402_1%
2
1
R123
@ 2.21K_0402_1%
2
1
R115
@ 2.21K_0402_1%
2
1
R116
@ 2.21K_0402_1%
2
1
R114
@ 2.21K_0402_1%

HDA_BITCLK_MCH 22
HDA_RST_MCH# 22

Notice: Please check HDA power rail to select HDA controller.


Security Classification

L DDC DATA

R153
1K_0402_1%

CL_CLK0 23
CL_DATA0 23

(Default)

0 = Dynamic ODT Disabled


1 = Dynamic ODT Enabled * (Default)
0 = Normal Operation
*(Default)
1 = DMI Lane Reversal Enable
0 = Only PCIE or SDVO is operational.
* (Default)
1 = PCIE/SDVO are operating simu.

ME

AH37
AH36
AN36
AJ35
AH34

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

= All Z Mode Enabled


= Reserved
= XOR Mode Enabled
= Normal Operation *

*(Default)

0 = No SDVO Card Present


* (Default)
1 = SDVO Card Present
0 = LFP Disable
* (Default)
1 = LFP Card Present PCIE disable

SDVO CTRLDATA
+1.05VS

* (Default)

0 = iTPM Host Interface is enabled

CFG6

CFG19
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

CANTIGA ES_FCBGA1329
UMAGM@

CANTIGA GM: SA00002JTB0


(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)

011 = FSB667
010 = FSB800
000 = FSB1067

CFG[2 0]

R241
1K_0402_5%
R231
1K_0402_5%

NC

+1.05VS

MISC

+3VS

HDA

+3VS

Pre-MP

C488

80 Ohm

21,23,26,27,31 PLT_RST#
4,22 H_THERMTRIP#
23,46 PM_DPRSLPVR

R98 1
R112 1
R107 1

PM_SYNC#_R
PM_DPRSTP#_R
PM_EXTTS#0
PM_EXTTS#1
GMCH_PWROK
2 100_0402_5% MCH_RSTIN#
THERMTRIP#_R
2 0_0402_5%
DPRSLPVR_R
0_0402_5%
2
2 0_0402_5%
2 0_0402_5%

PM

23 PM_SYNC#
5,22,46 H_DPRSTP#
14 PM_EXTTS#0
15 PM_EXTTS#1

MCH_TSATN#

SM_RCOMP_VOL

For Cantiga

SM_VREF
R157 1
2 0_0402_5%
R434 1
2 499_0402_1%

B38
A38
E41
F41

SM_DRAMRST# would be 3.01K_0402_1%


needed for DDR3 only

20mil

SM_PWROK
SM_REXT

SM_RCOMP_VOH
1
C489
<BOM Structure>
2.2U_0603_6.3V6K
2

CFG16

R109 1
R94 1

DMI

16 MCH_CLKSEL0
16 MCH_CLKSEL1
16 MCH_CLKSEL2
+3VS

DDRA_CLK0#
DDRA_CLK1#
DDRB_CLK0#
DDRB_CLK1#

R685
22.1K_0402_1%

CLK

1
2
3
4

U41

R680
10K_0402_5%

R679
10K_0402_5%

T43
PAD
@

R682
1K_0402_1%

RSVD20

AR24
AR21
AU24
AV20

R445

AY21

GRAPHICS VID

+3VS

RSVD15
RSVD16
RSVD17

RSVD

+1.05VS

B31
B2
M1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

14
14
15
15

All RSVD balls on GMCH should be left No


Connect.

DDRA_CLK0
DDRA_CLK1
DDRB_CLK0
DDRB_CLK1

PAD
PAD
PAD
PAD

AP24
AT21
AV24
AU20

PVT2 JALA0 (Add Management Engine JTAG pins)

@
@
@
@

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

T39
T40
T41
T42

DDR CLK/ CONTROL/

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

COMPENSATION

U30B
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24

Sheet

Friday, May 16, 2008


1

of

50

DDRA_SDQ[0..63]

DDRA_SMA[0..14]

DDRB_SMA[0..14]

15 DDRB_SMA[0..14]

U30E

SA_BS_0
SA_BS_1
SA_BS_2

BD21
BG18
AT25

DDRA_SBS0# 14
DDRA_SBS1# 14
DDRA_SBS2# 14

SA_RAS#
SA_CAS#
SA_WE#

BB20
BD20
AY20

DDRA_SRAS# 14
DDRA_SCAS# 14
DDRA_SWE# 14

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

A
MEMORY
SYSTEM

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#

14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14

AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2

BC16
BB17
BB33

DDRB_SBS0# 15
DDRB_SBS1# 15
DDRB_SBS2# 15

SB_RAS#
SB_CAS#
SB_WE#

AU17
BG16
BF14

DDRB_SRAS# 15
DDRB_SCAS# 15
DDRB_SWE# 15

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14

U30D
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

MEMORY

14 DDRA_SMA[0..14]

DDRB_SDM[0..7]

15 DDRB_SDM[0..7]

SYSTEM

DDRB_SDQ[0..63]

15 DDRB_SDQ[0..63]

DDRA_SDM[0..7]

14 DDRA_SDM[0..7]

DDR

14 DDRA_SDQ[0..63]

CANTIGA ES_FCBGA1329
UMAGM@

DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

CANTIGA ES_FCBGA1329
UMAGM@

DVT

CANTIGA GM: SA00001P930


(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)

PVT

CANTIGA GM: SA00002JT10


(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)

Pre-MP

CANTIGA GM: SA00002JTB0


(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)

PVT2 CANTIGA GM: SA00002JT50


(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM)

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

of

50

U30C

18 GMCH_LCD_CLK
18 GMCH_LCD_DATA
18 GMCH_ENVDD

R455

GM@

GMCH_TXCLKGMCH_TXCLK
GMCH_TZCLKGMCH_TZCLK

LVDS_IBG
2.37K_0402_1%
2
1
R579
GM@
0_0402_5%
GMCH_TXCLKGMCH_TXCLK
GMCH_TZCLKGMCH_TZCLK

18 GMCH_TXOUT018 GMCH_TXOUT118 GMCH_TXOUT218 GMCH_TXOUT0


18 GMCH_TXOUT1
18 GMCH_TXOUT2
18 GMCH_TZOUT018 GMCH_TZOUT118 GMCH_TZOUT2-

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL

C41
C40
B37
A37

LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

H47
E46
G40
A40

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

GMCH_TXOUT0
GMCH_TXOUT1
GMCH_TXOUT2

H48
D45
F40
B40

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-

A41
H38
G37
J37

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

GMCH_TZOUT0
GMCH_TZOUT1
GMCH_TZOUT2

B42
G38
F37
K37

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA

F25
H25
K25
H24

R119
TV_DCONSEL_0
TV_DCONSEL_1

GM@
GM@
GM@
75_0402_1%
75_0402_1%
75_0402_1%

Change to 0Ohm when use PM chip


19 GMCH_CRT_B

19 GMCH_CRT_R

1
GM@ 150_0402_1%
1
GM@ 150_0402_1%
1
GM@ 150_0402_1%

GMCH_CRT_CLK
GMCH_CRT_DATA

19 GMCH_CRT_CLK
19 GMCH_CRT_DATA

3VS

R147 1 GM@

2 2.2K_0402_5%

GMCH_LCD_CLK

R146 1 GM@

2 2.2K_0402_5%

GMCH_LCD_DATA

R152 1 GM@

2 10K_0402_5%

LCTLB_DATA

R144 1 GM@

2 10K_0402_5%

LCTLA_CLK

R132 1 GM@

2 2.2K_0402_5%

GMCH_CRT_CLK

R124 1 GM@

2 2.2K_0402_5%

GMCH_CRT_DATA

CRT_IREF

1
PM@ 0_0402_5%

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32
J32
J29
E29
L29

2
R125

1
PM@ 0_0402_5%

TV_DCONSEL_0
TV_DCONSEL_1

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

PEG_COMP

1
R156

PEG_COMPI
PEG_COMPO

T37
T36

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

10mils

C236 1

49.9_0402_1%

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

2
2

C246 1

2 PM@

C267 1
C274 1
C258 1

2 PM@
2 PM@
2 PM@
2 PM@

C271 1

2 PM@

C233 1

C240 1

C244 1

2 PM@

C252 1

2 PM@

C260 1

2 PM@

C273 1

2 PM@

C255 1
C270 1

PCIE_MTX_C_GRX_N[0..15] 17
PCIE_MTX_C_GRX_P[0..15] 17
PCIE_GTX_C_MRX_N[0..15] 17
PCIE_GTX_C_MRX_P[0..15] 17

C241 1

C256 1

1.05VS

2 PM@
2 PM@

C225
0.1U_0402_16V7K
C239
0.1U_0402_16V7K
C243
0.1U_0402_16V7K
C251
0.1U_0402_16V7K
C257
0.1U_0402_16V7K
C272
0.1U_0402_16V7K
C266
0.1U_0402_16V7K
C269
0.1U_0402_16V7K

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

C220
0.1U_0402_16V7K
C238
0.1U_0402_16V7K
C242
0.1U_0402_16V7K
C247
0.1U_0402_16V7K
C253
0.1U_0402_16V7K
C263
0.1U_0402_16V7K
C262
0.1U_0402_16V7K
C268
0.1U_0402_16V7K

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

19 GMCH_CRT_VSYNC

2
R131

R143
1K_0402_1%
GM@

19 GMCH_CRT_HSYNC

C31
E32

TV_RTN

VGA

2
R138
2
R139
2
R140

19 GMCH_CRT_G

TVA_DAC
TVB_DAC
TVC_DAC

2
R129

C44
B43
E37
E38

TV

R128

18 GMCH_TZOUT0
18 GMCH_TZOUT1
18 GMCH_TZOUT2

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS

18
18
18
18

L32
G32
M32
M33
K33
J33
M29

GRAPHICS

ENBKL

LBKLT_EN
LCTLA_CLK
LCTLB_DATA
GMCH_LCD_CLK
GMCH_LCD_DATA

PCI-EXPRESS

17,31

18 DPST_PWM
1
2
R141 GM@ 0_0402_5%

DVT

CANTIGA ES_FCBGA1329
UMAGM@

Pre-MP

CANTIGA GM: SA00001P930


(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)

CANTIGA GM: SA00002JTB0


(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)

Change to 0Ohm when use PM chip


PVT
CANTIGA GM: SA00002JT10
(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)
PVT2

R149

GM@

0_0402_5%

TV_DCONSEL_0

R133

GM@

0_0402_5%

TV_DCONSEL_1

R136 1

2 100K_0402_5%

CANTIGA GM: SA00002JT50


(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM)

Compal Electronics, Inc.

Compal Secret Data

Security Classification

LBKLT_EN

2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

10

of

50

U30F

+VGFX_CORE

+1.8V

+VGFX_CORE

@
@

VCC_AXG_SENSE
VSS_AXG_SENSE

AJ14
AH14

VCC_AXG_SENSE
VSS_AXG_SENSE

CANTIGA ES_FCBGA1329
UMAGM@

+1.05VS
1

+ C139

C203

C207

C206

U30G
C202

220U_D2_4VM_R15
0.22U_0603_16V7K
0.1U_0402_16V4Z
2
2
2
10U_0805_10V4Z
0.22U_0603_16V7K

Cavity Capacitors

VCC_AXG: 6326 84mA


(330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)

+VGFX_CORE
1
R103
1
R135
1
R137

+1.05VS

2
GM@ 0_1206_5%
2
GM@ 0_0805_5%
2
GM@ 0_0805_5%

C189

C134

C181 1

C183 1

C177 1

C186 1

GM@
0.47U_0603_16V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
2
2
2
GM@
GM@ 2
GM@
1U_0402_6.3V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
GM@
GM@

R111
0_0402_5%
PM@

JALA0

C188

Cavity Capacitors

1
+

330U_D2E_2.5VM_R15
2
GM@

AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35

POWER

GFX NCTF

+1.05VS

+1.8V

C157

VCC_SM: 2600mA
(330UF*1, 22UF*2, 0.1UF*1)

1
1

C201

C211

C208

330U_D2E_2.5VM_R15
10U_0805_10V4Z
2
2
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z

Place on the edge


Reference PILLAR_ROCK CRB Rev1.0
VCC_SM_BA36
VCC_SM_BB24
VCC_SM_BD16
VCC_SM_AW16
VCC_SM_AT13
1
1
1
1
1
C173
C174
C176
C192
C213
@
@
@
@
@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
1
C169

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

CANTIGA ES_FCBGA1329
UMAGM@
C168

C166

C185

C214

C212

C226

0.1U_0402_16V7K
0.22U_0402_6.3V6K
0.47U_0603_16V4Z
1U_0402_6.3V4Z
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.22U_0402_6.3V6K
1U_0402_6.3V4Z

PVT2

Pre-MP

CANTIGA GM: SA00002JT50


(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM)

CANTIGA GM: SA00002JTB0


(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)

DVT
CANTIGA GM: SA00001P930
(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)
PVT
CANTIGA GM: SA00002JT10
(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

Place close to the GMCH

GFX

PAD
PAD

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

VCC: 1930.4mA (GMCH), 1210 34mA (MCH)


(270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)

+1.05VS

VCC

T9
T10

Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14

Place close to the GMCH

NCTF

VCC_SM_AT13

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

VCC

VCC_SM_AW16

BA36
BB24
BD16
BB21
AW16
AW13
AT13

VCC

VCC_SM_BA36
VCC_SM_BB24
VCC_SM_BD16

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC CORE

SM

Pins BA36, BB24, BD16,


BB21, AW16, AW13, AT13
could be left NC for DDR2
board.

VCC

Reference PILLAR_ROCK CRB Rev1.0

POWER

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC SM LF

2600mA
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

11

of

50

+1.05VS_HPLL
+1.05VS_DPLLA

2
0.1U_0402_16V4Z

C232
GM@

VSSA_DAC_BG

+1.05VS_DPLLA

F47

VCCA_DPLLA

+1.05VS_DPLLB

L48

VCCA_DPLLB

+1.05VS_HPLL

AD1

VCCA_HPLL

+1.05VS_MPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

R597
PM@

64.8mA

VCCA_PEG_BG: 0.414mA
(0.1UF*1)

0.1U_0402_16V4Z
2

+1.05VS_PEGPLL
VCCA_PEG_PLL:
1
C507

AA48

DVT

C175

+1.05VS_A_SM_CK

+3VS_DACBG
+1.05VS

L40
GM@
MBK1608221YZF_0603 1
1
1
C482
C481
C480
GM@
GM@
@
0.1U_0402_16V4Z
10U_0805_6.3V6M
2
2
2
0.01U_0402_16V7K

R440
0_0402_5%
PM@

C184

4.7U_0805_10V4Z
2
2
2
22U_0805_6.3V6M
1U_0402_6.3V4Z

P ease check Power


source if want
support IAMT

1
2
R130
0_0603_5%

VCCA_SM_CK: 24mA
(22UF*1, 2.2UF*1, 0.1UF*1)

1
1
C205
C200
C190
@
2.2U_0805_10V6K
0.1U_0402_16V4Z
2
2
2
22U_0805_6.3V6M

NO_STUFF

Close to Ball A25

VCCA_TV_DAC: 40mA (0.1UF*1,


0.01UF*1 for each DAC)

0.1U_0402_16V4Z
GM@ 2
+1.5VS_TVDAC

M25

VCCD_TVDAC

+1.5VS_QDAC

L28

48.363mA

VCCD_QDAC

AF1

VCCD_HPLL

58.696mA

157.2mA

1
2
L14
MBK1608221YZF_0603

C191

C193

180Ohm@100MHz

C196

0.1U_0402_16V4Z
2
2
0.01U_0402_16V7K

VCCD_LVDS_1
VCCD_LVDS_2

K47

1
1
C216
C217
GM@
GM@
10U_0805_6.3V6M
2
2
1U_0402_6.3V4Z

R159
0_0402_5%
PM@

R117
0_0402_5%
@

2007/09/20

Issued Date

+3VS
1

+1.05VS_DMI
1

1
R194
0_0805_5%

+1.05VS
B

+ C261

C248

10U_0805_10V4Z
2

220U_D2_4VM_R15

1
2
R186
0_0603_5%

C237

+1.05VS

0.1U_0402_16V4Z

Pre-MP

VTTLF_CAP1
A8
VTTLF_CAP2
L1
AB2 VTTLF_CAP3
C153

Please check Power


source if want
support IAMT

0.1U_0402_16V4Z

AH48
AF48
AH47
AG47

+1.8V

C209

VCC_DMI: 456mA
(0.1UF*1)

VTTLF1
VTTLF2
VTTLF3

0.1uH 20%
1

+1.05VS_PEG: 1782mA +1.05VS_PEG


(220UF*1, 22UF*1, 4.7UF*1)

V48
U48
V47
U47
U46

DVT(JALA0)

+1.8V_TX_LVDS

2
R198
1
C278
C282
0_0603_5%
GM@
GM@
GM@
1000P_0402_50V7K
2
2 10U_0805_10V4Z

CANTIGA GM: SA00002JTB0


(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)
1

C434

C450

PVT2

0.47U_0603_16V4Z
0.47U_0603_16V4Z
2
2
2
0.47U_0603_16V4Z

CANTIGA GM: SA00001P930


(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)

CANTIGA GM: SA00002JT50


(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM)

PVT
CANTIGA GM: SA00002JT10
(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)

R54

D6
+1.05VS

+3VS

10_0603_5%
CH751H-40PT_SOD323-2

Deciphered Date

Compal Electronics, Inc.


2008/09/20

Title

Date

+1.05VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DVT (Check)

Please check Power


source if want
support IAMT

1
2
1
2
R436
C461
1_0402_1% 10U_0603_6.3V6M

0.1U_0402_16V4Z

Compal Secret Data

Security Classification

1
2
+1.8V
L37
MBK1608121YZF_0603

R193
PM@
0_0402_5%

VCC_HV: 105.3mA
C35
B35
A35

CANTIGA ES_FCBGA1329
UMAGM@ DVT

+1.8V_LVDS

0.47U_0603_16V4Z

C466

+1.8V_TX_LVDS: 118.8mA
(22UF*1, 1000PF*1)

VCCD_LVDS: 60 311111mA
(1UF*1)

C187

1
2
R110
100_0603_1%

1
R160
0_0603_5%
GM@

50mA

VCCD_PEG_PLL

60.31mA
M38
L37

VCCD_PEG_PLL: 50mA
(0.1UF*1)
+1.8V

VCCD_QDAC: 48.363mA +1.5VS_QDAC


(0.1UF*1, 0.01UF*1)
+1.5VS

Close to AA47
Close to AF1

Also power for internal


Thermal Sensor

0.1U_0402_16V4Z
2
2
0.022U_0402_16V7K

AA47

+1.5VS

+1.05VS_PEGPLL

Please check Power


source if want
support IAMT

DMI

Close to A32

BF21
BH20
BG20
BF20

TV

456mA
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

VCCD_HPLL: 157.2mA (0.1UF*1)

+1.5VS_TVDAC

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

50mA

C493

105.3mA
VCC_HV_1
VCC_HV_2
VCC_HV_3

VCC_HDA

+1.05VS_HPLL

VCCD_TVDAC: 58.696mA
(0.1UF*1, 0.01UF*1)

VCC_TX_LVDS

A32

VCCD_HDA: 50mA
(0.1UF*1)
+1.5VS_HDA

B22
B21
A21

1782mA

VTTLF

1
2
R447
0_0402_5%
R446
GM@
0_0402_5%
PM@

HDA

+1.5VS

R439
0_0402_5%
PM@

1
1
C475
C474
GM@
GM@
0.1U_0402_16V4Z
2
2
0.01U_0402_16V7K

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

VCCA_TV_DAC_1
VCCA_TV_DAC_2

L38 1
2
MBK1608221YZF_0603

C119

VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1) 1uH 30%

118.8mA

87.79mA

+3VS

180Ohm@100MHz GM@

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

B24
A24

+3VS_TVDAC

+3VS_TVDAC

D TV/CRT

+1.8V_SM_CK

24mA
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

C109

1
2
R435
0_0603_5%
1
1
C471
C470
@
10U_0805_6.3V6M
2
2
1U_0402_6.3V4Z

POWER

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

LVDS

C182

+
C431
@
220U_D2 4VM_R15
2

Please check Power


source if want
support IAMT

VCCA_DAC_BG: 2.6833333mA
(0.1UF*1, 0.01UF*1)

1
2
R122
0_0805_5%

PLL

480mA
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

VCCA_SM:
(22UF*2, 4.7UF*1, 1UF*1)

C132

VCC_AXF: 321.35mA
(10UF*1, 1UF*1)

AXF

0.1U_0402_16V4Z

C143

220U_D2 4VM_R15
4.7U_0805_10V4Z
2
2
2
2
4.7U_0805_10V4Z
2.2U_0805_10V6K

(0.1UF*1)

+1.05VS_AXF

HV

+1.05VS

VCCA_PEG_PLL

50mA

+1.05VS_A_SM

DVT

VCCA_PEG_BG

PEG

0.414mA
AD48

50mA

No CIS Symbol

L17 1
2
MBK1608221YZF_0603
2
1
1
2
C245
R181
10U_0805_6.3V6M 1_0402_1%
+1.05VS

Close to Ball A26, B27

13.2mA

A PEG A LVDS

1
R443
0_0402_5%
PM@

C234

139.2mA

SM CK

Please check Power


source if want
support IAMT

+3VS

VCCA_LVDS: 13.2mA
(1000PF*1)

24mA

A CK

+3VS_CRTDAC

1
2
L41 GM@
MBK1608221YZF_0603
1
1
C487
C486
1
GM@
GM@
+
0.1U_0402_16V4Z
C597
2
2
GM@
0.01U_0402_16V7K
220U_D2 4VM_R15
2

+VCCA_PEG_BG

R184
0_0402_5%
1
2

+1.5VS

1
C231
GM@
1000P_0402_50V7K
2

1
C113

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

+1.8V_TX_LVDS

A SM

R179
@ 0_0402_5%
1
2

+3VS

+3VS

C280
2
2
0_0402_5%
10U_0805_10V4Z
0.1U_0402_16V4Z
GM@

DVT

C432
22U_0805_6.3V6M
2

VCCA_DAC_BG

B25

VTT: 852mA
(270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)

1
L18
0_1210_5%
GM@

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

R410
0.5_0603_1%

A25

+3VS_DACBG

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

VTT

C156

B27
A26

2.69mA

+1.05VS_DPLLB

L13 1
2
MBK1608121YZF_0603

VCCA_MPLL: 139.2mA
(22UF*1, 0.1UF*1)

+1.05VS

852mA

73mA

CRT

120Ohm@100MHz

U30H

1
1
C229
R596
+ GM@
C499
PM@
GM@
220U_D2_4VM_R15 2
0_0402_5% +3VS_CRTDAC
2
0.1U_0402_16V4Z

VCCA_DPLLA
VCCA_DPLLB: 64.8mA
(220UF*1, 0.1UF*1)

Please che k Power


source if w nt
support IAMT

+1.05VS_MPLL

1
L42
0_1210_5%
GM@

+1.05VS

4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z

Please check Power


source if want
support IAMT
D

(4.7UF*1, 0.1UF*1)

C436

L32 1
2
MBK1608121YZF_0603
1
C429
VCCA_HPLL: 24mA

+1.05VS

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

12

of

50

VSS

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233

BA16

VSS_235

AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13

VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

VSS

VSS NCTF

U30J
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

VSS SCB

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

VSS_351
VSS_352
VSS_353
VSS_354

U24
U28
U25
U29

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

BH48
BH1
A48
C1
A3

NC

U30I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36

CANTIGA ES_FCBGA1329
UMAGM@

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

CANTIGA ES_FCBGA1329
UMAGM@
A

PVT2

DVT

CANTIGA GM: SA00002JT50


(S IC AC88CTGM QU36 B3 FCBGA 1329 GMCH GM)

CANTIGA GM: SA00001P930


(S IC EB88CTGM QR32 B0 FCBGA 1329 MCH GM)

Pre-MP

PVT

CANTIGA GM: SA00002JTB0


(S IC AC82GM45 SLB94 B3 FCBGA1329 GM ABO!)

CANTIGA GM: SA00002JT10


(S IC AC88CTGM QT62 B2 FCBGA 1329 GMCH GM)

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

13

of

50

+1.8V

+1.8V
+1.8V

JDIMM2

9 DDRA_SDQS0#
9 DDRA_SDQS0

DDRA_SDQ2
DDRA_SDQ3
D

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1

9 DDRA_SDQS1#
9 DDRA_SDQS1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2

9 DDRA_SDQS2#
9 DDRA_SDQS2

DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
C

8
9

DDRA_CKE0

DDRA_CKE0

DDRA_SBS2#

DDRA_SBS2#

DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

9
9

DDRA_SBS0#
DDRA_SWE#

9
8

DDRA_SCAS#
DDRA_SCS1#

DDRA_ODT1

DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
DDRA_ODT1
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4

9 DDRA_SDQS4#
9 DDRA_SDQS4

DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
B

DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49

DDRA_SDQS6#
DDRA_SDQS6

9 DDRA_SDQS6#
9 DDRA_SDQS6

DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
D_CK_SDATA
D_CK_SCLK

15,16,20 D_CK_SDATA
15,16,20 D_CK_SCLK

+3VS

C19

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

+DIMM_VREF

DDRA_SDQ4
DDRA_SDQ5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

20mils

R174

DDRA_SDM0
1

DDRA_SDQ6
DDRA_SDQ7

DDRA_SDQ12
DDRA_SDQ13

1K_0402_1%
C218

20mils

To SODIMM and GMCH

+DIMM_VREF

0.1U_0402_16V4Z

R161

DDRA_SDM1

1K_0402_1%
DDRA_CLK0 8
DDRA_CLK0# 8

DDRA_SDQ14
DDRA_SDQ15
DDRA_SMA[0..14]

9 DDRA_SMA[0..14]

DDRA_SDQ[0..63]

9 DDRA_SDQ[0..63]
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2

+1.8V
DDRA_SDM[0..7]

9 DDRA_SDM[0..7]

PM_EXTTS#0 8

C159

DDRA_SDQ22
DDRA_SDQ23

C140

C149

C110

C123

2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
2
2
2
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K

DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3

DDRA_SDQS3# 9
DDRA_SDQS3 9
+1.8V

DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1

+0.9VS
DDRA_CKE0
1
DDRA_SBS2#
2
RP43

DDRA_CKE1 8

4
3
56_0404_4P2R_5%

C427

C424

C440

C444

DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_SMA13

DDRA_SBS1# 9
DDRA_SRAS# 9
DDRA_SCS0# 8
DDRA_ODT0 8

DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4

DDRA_SMA12
1
DDRA_SMA9
2
RP39

4
3
56_0404_4P2R_5%

DDRA_SMA8
DDRA_SMA5

1
2
RP35

4
3
56_0404_4P2R_5%

DDRA_SMA3
DDRA_SMA1

1
2
RP31

4
3
56_0404_4P2R_5%

DDRA_SMA10
1
DDRA_SBS0#
2
RP27

4
3
56_0404_4P2R_5%

DDRA_SWE#
1
DDRA_SCAS#
2
RP23

4
3
56_0404_4P2R_5%

DDRA_SCS1#
1
DDRA_ODT1
2
RP19

4
3
56_0404_4P2R_5%

DDRA_SMA11
1
DDRA_SMA14
2
RP40

4
3
56_0404_4P2R_5%

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

C111

C112

C124

C135

C144

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5

DDRA_SDQS5# 9
DDRA_SDQS5 9

DDRA_CLK1 8
DDRA_CLK1# 8

1
C131

C141

C162

C154

1
B

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

DDRA_SMA6
DDRA_SMA7

1
2
RP36

4
3
56_0404_4P2R_5%

DDRA_SMA2
DDRA_SMA4

1
2
RP32

4
3
56_0404_4P2R_5%

DDRA_SBS1#
1
DDRA_SMA0
2
RP28

4
3
56_0404_4P2R_5%

C150

DDRA_SCS0#
1
DDRA_SRAS#
2
RP24

4
3
56_0404_4P2R_5%

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z

DDRA_SMA13
1
DDRA_ODT0
2
RP20

4
3
56_0404_4P2R_5%

DDRA_CKE1

2
56_0402_5%

DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53

C122

+0.9VS

C147

C160

DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7

DDRA_SDQS7# 9
DDRA_SDQS7 9

R92

DDRA_SDQ62
DDRA_SDQ63
R32
R26

1
1

2 10K_0402_5%
2 10K_0402_5%

FOX_AS0A426-N2RN-7F
CONN@

+3VS

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

DDRA_SDQS0#
DDRA_SDQS0

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

DDRA_SDQ0
DDRA_SDQ1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

+DIMM_VREF

C18

0.1U_0402_16V4Z
2
2
2.2U_0805_10V6K

DIMM0 REV H:5.2mm (BOT)


2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


1

14

of

50

+DIMM_VREF
+1.8V

DDRB_SDQ0
DDRB_SDQ5
1

9 DDRB_SDQS0#
9 DDRB_SDQS0

DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9

9 DDRB_SDQS1#
9 DDRB_SDQS1

DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11

DDRB_SDQ16
DDRB_SDQ17
9 DDRB_SDQS2#
9 DDRB_SDQS2

DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3

DDRB_SDQ26
DDRB_SDQ27
8

DDRB_CKE0

DDRB_SBS2#

DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

9
9

DDRB_SBS0#
DDRB_SWE#

9
8

DDRB_SCAS#
DDRB_SCS1#

DDRB_ODT1

DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33

9 DDRB_SDQS4#
9 DDRB_SDQS4

DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35

DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49

9 DDRB_SDQS6#
9 DDRB_SDQS6

DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59

14,16,20 D_CK_SDATA
14,16,20 D_CK_SCLK

D_CK_SDATA
D_CK_SCLK
+3VS

+1.8V

+1.8V

JDIMM1
+DIMM_VREF

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

C224
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDRB_SDQ4
DDRB_SDQ1

C219

2.2U_0805_10V6K
2
2
0.1U_0402_16V4Z

1
+

C171

C100

2
330U_D2E_2.5VM_R15
330U_D2E_2.5VM_R15

DDRB_SDM0

DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_CLK0 8
DDRB_CLK0# 8
DDRB_SDQ14
DDRB_SDQ15

9 DDRB_SMA[0..14]
9 DDRB_SDQ[0..63]
9 DDRB_SDM[0..7]

DDRB_SMA[0..14]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]

DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2

PM_EXTTS#1 8

DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3

+1.8V
DDRB_SDQS3# 9
DDRB_SDQS3 9

+0.9VS

DDRB_SDQ30
DDRB_SDQ31

C161
DDRB_CKE0
DDRB_SBS2#

1
2
RP42

4
3
56_0404_4P2R_5%

DDRB_SMA14

DDRB_SMA12
DDRB_SMA9

1
2
RP38

4
3
56_0404_4P2R_5%

DDRB_SMA11
DDRB_SMA7
DDRB_SMA6

DDRB_SMA8
DDRB_SMA5

1
2
RP34

4
3
56_0404_4P2R_5%

DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

DDRB_SMA3
DDRB_SMA1

1
2
RP30

4
3
56_0404_4P2R_5%

DDRB_SMA10
DDRB_SBS0#

1
2
RP26

4
3
56_0404_4P2R_5%

DDRB_SWE#
DDRB_SCAS#

1
2
RP22

4
3
56_0404_4P2R_5%

DDRB_SCS1#
DDRB_ODT1

1
2
RP18

4
3
56_0404_4P2R_5%

DDRB_SMA11
DDRB_SMA14

1
2
RP41

4
3
56_0404_4P2R_5%

DDRB_SMA6
DDRB_SMA7

1
2
RP37

4
3
56_0404_4P2R_5%

DDRB_SMA2
DDRB_SMA4

1
2
RP33

4
3
56_0404_4P2R_5%

DDRB_SBS1#
DDRB_SMA0

1
2
RP29

4
3
56_0404_4P2R_5%

DDRB_CKE1

DDRB_CKE1 8

DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_SMA13

DDRB_SBS1# 9
DDRB_SRAS# 9
DDRB_SCS0# 8
DDRB_ODT0 8

DDRB_SDQ36
DDRB_SDQ37

C152

C136

C105

C126

2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
2
2
2
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K

+1.8V

C115

C104

C165

C145

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5

DDRB_SDQS5# 9
DDRB_SDQS5 9

DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_CLK1 8
DDRB_CLK1# 8
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55

DDRB_SCS0#
DDRB_SRAS#

1
2
RP25

4
3
56_0404_4P2R_5%

DDRB_SMA13
DDRB_ODT0

1
2
RP21

4
3
56_0404_4P2R_5%

DDRB_SDQ60
DDRB_SDQ61
DDRB_CKE1
DDRB_SDQS7#
DDRB_SDQS7

R90

DDRB_SDQS7# 9
DDRB_SDQS7 9

2
56_0402_5%

1
1

2 10K_0402_5%
2 10K_0402_5%

C133

C130

C116

C146

1
3

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

C155

C137

C158

C114

C103

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

C163

C148

C142

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z

DDRB_SDQ62
DDRB_SDQ63
R35
R31

C125

+3VS

FOX_AS0A426-NARN-7F
CONN@

DIMM1 REV H:9.2mm (BOT)


2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


E

15

of

50

FSLC

FSLB

FSLA

CLKSEL2 CLKSEL1 CLKSEL0

CPU
MHz

SRC
MHz

PCI
MHz

266

100

33.3

200

100

33.3

166

100

33.3

Clock Generator

L21 2
1
KC FBM-L11-201209-221LMAT_0805
1
1
1
1
1
1
1
1
C339
C303
C320
C316
C338
C304
C336
C342
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

U18
1

CLK_VDD

D_CK_SDATA

SCLK

10

D_CK_SCLK
CLK_CPU_BCLK

SDATA

D_CK_SDATA 14,15,20

Free-Run

CR#_10(WLAN)

PCIEX10

PC EX0

19

CR#_6(MCH)

PCIEX6

PC EX1

72

VDDCPU

CPUT0_LPR_F

71

CR#_4(NEW CARD)

PCIEX4

12

VDDPCI

CPUC0_LPR_F

70

CLK_CPU_BCLK#

CR#_9(MINI CARDII)

PCIEX9

27

VDDPLL3

55

VDDSRC

SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable]

3VS

R228
10K_0402_5%
@

CLK_PCI2
2
10K_0402_5%

1
R256

mount to Enable ITP_CLK

2
@ 10K_0402_5%

CLK_PCI5
2
10K_0402_5%

38
62

2
G
Q22
2N7002_SOT23
@

CLK_PCI5=0, Pin63,64 is SRC_CLK


CLK_PCI5=1, Pin63,64 is ITP_CLK

CLK_ENABLE# 46

23 H_STP_CPU#

CLK_PCI4
2
10K_0402_5%

1
R247

23 H_STP_PCI#

CLK_PCI4=0, Pin28, 29 is SRC_CLK


Pin24, 25 is DOT96_CLK
2
@ 10K_0402_5%

10P_0402_50V8J CLK_PCI_LPC

C552 1

2 @

10P_0402_50V8J CLK_PCI_ICH

For EMI Requrie 10/9

CLK_DREF_96M#
CLK_DREF_SSC

CLK_DREF_96M 8
CLK_DREF_96M# 8

VDDSRC_IO

VGA: disable this pair by BIOS

31

VDDPLL3_IO

27MHz_NonSS/SRCT1_LPR/SE1

28

66

VDDCPU_IO

27MHz_SS/SRCC1_LPR/SE2

29

CLK_DREF_SSC#

23

VDD96_IO

H_STP_PCI#

54

PCI_STOP#

CLK_DREF_SSC

SRCT2_LPR/SATAT_LPR

32

SRCC2_LPR/SATAC_LPR

33

CLK_PCIE_SATA#

SRCT3_LPR

35

CLK_PCIE_ICH

36

CLK_PCIE_ICH#

CLK_PCIE_SATA 22
2

CLK_PCIE_SATA# 22
CLK_PCIE_ICH

23

CLK_PCIE_ICH#

SRCT4_LPR
SRCC4_LPR

40

31 CLK_PCI_LPC

CLK_PCI_LPC R515 2

1 33_0402_5%

CLK_PCI3

15

PCI3

57

16

SRCT6_LPR

CLK_MCH_3GPLL

CLK_PCI4

PCI4/27_SELECT
SRCC6_LPR

56

CLK_MCH_3GPLL#

CLK_PCI_ICH

R516 2

0_0402_5% 2
0_0402_5% 2

27P_0402_50V8J
MCH_CLKSEL0 8

C308
1
2

23 CLK_ICH_48M

CLK_PCI5

CLK_XTALOUT
Y1
14.31818MHz_20P_FSX8L14.318181M20FDB

23

1 33_0402_5%

CLK_ICH_14M R506 2

1 33_0402_5%

3VS

23,27,29 ICH_SMBDATA

1
R503
0_0402_5%

23,27,29 ICH_SMBCLK

3
S

R512
@ 1K_0402_5%

2
G

R254
4.7K_0402_5%
1
2

Q49
2N7002_SOT23

CLK_PCIE_VGA# 17

UMA: disable this pair by BIOS

CPUT2_ITP_LPR/SRCT8_LPR

63

CLK_PCIE_READER#

SRCT9_LPR

44

CLK_PCIE_MINI2

SRCC9_LPR

45

CLK_PCIE_MINI2#

NC

CLK_PCIE_MINI2

SRCT10_LPR

50

CLK_PCIE_MINI1

SRCC10_LPR

51

CLK_PCIE_MINI1#

SRCT11_LPR

48

CLK_PCIE_LAN

SRCC11_LPR

47

CLK_PCIE_LAN#

26

CLK_PCIE_READER#
29

CLK_PCIE_MINI2#
CLK_PCIE_MINI1

26

29
29

CLK_PCIE_MINI1#

29

REF1

GNDCPU

GNDREF

CR#3

37

18

GNDPCI

CR#4

41

22

GND48

CR#6

58

30

GND

CR7#

65

CR#9

43

CR10#

49

SA000020H10
CR#11
(S IC ICS9LPRS387BKLFT MLF 72P CLK GEN)

46

GND

34

GNDSRC

DVT

59

GNDSRC

42
73

GNDSRC
GND_THERMAL_PAD

CR#A

21

CLK_PCIE_LAN 27
CLK_PCIE_LAN# 27

New Card usage for JAL90


MCH_CLKREQ# 8

(Pull High to +3VS at Page8)

1
R246
1
R244
1
2
R689 0_0402_5%

2
10K_0402_5%
2
10K_0402_5%
2
1 R690
10K_0402_5%

3VS
MINI2_CLKREQ# 29
3VS
MINI1_CLKREQ# 29
3VS

(Pull High to +3VS at ICH side)

LAN_CLKREQ# 27
SATA_CLKREQ# 23

PVT2(JALA0)

MP(JALA0) add part

ICS9LPRS387AKLFT_MLF72_10x10

MCH_CLKSEL2 8

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

CPU_BSEL2 5

2007/09/20

Deciphered Date

2008/09/20

Title

Date:

CLK_PCIE_READER

FSLC/TEST_SEL/REF0

69

26

3VS

CLK_PCIE_READER

CLK_PCIE_VGA 17

CPUC2_ITP_LPR/SRCC8_LPR

FSLB/TEST_MODE

D_CK_SCLK

CLK_PCIE_VGA#

X2

USB_48MHz/FSLA

Q48
2N7002_SOT23

CLK_PCIE_VGA

60

X1

3VS

61

20

D_CK_SDATA

SRCT7_LPR
SRCC7_LPR

CK_PWRGD/PD#

CLKSEL1

CPU_BSEL1 5

2
G

MCH_CLKSEL1 8

R259
4.7K_0402_5%
1
2

CLK_MCH_3GPLL# 8

64

R499
1K_0402_5%
1
2

CLK_MCH_3GPLL 8

PCI_F5/ITP_EN

CLKSEL0

CLKSEL2

New Card usage for JAL90

11

DVT

R505
1K_0402_5%
1
2

17

CK505_PWRGD1

CLK_XTALIN

27P_0402_50V8J
CLK_ICH_48M R529 2

23 CLK_ICH_14M

1 R215
1 R221

C311
1
2

PVT

CPU_BSEL0 5

1 33_0402_5%

13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

VGA: disable this pair by BIOS

CLK_PCIE_SATA

SRCC3_LPR

CLK_DREF_SSC#

PCI2/TME

25

CLK_MCH_BCLK# 7

PCI1

R500
@ 1K_0402_5%

1
2
1

SRCC0_LPR/DOTC_96_LPR

VDDSRC_IO

CPU_STOP#

3VS

CLK_DREF_96M

14

1.05VS

1
R507
@ 0_0402_5%

SRCT0_LPR/DOTT_96_LPR

24

CLK_MCH_BCLK 7

CLK_PCI2

R269
1K_0402_5%
1
2

R266
@ 56_0402_5%

1
R501
0_0402_5%

R504
10K_0402_5%
CLKSEL2 1
2

CLK_MCH_BCLK#

1 33_0402_5%

21 CLK_PCI_ICH

1.05VS

CLK_MCH_BCLK

67

CLK_PCI_PCM R513 2

23 CK_PWRGD
8,23,46
VGATE

1
R270
0_0402_5%

68

25 CLK_PCI_PCM

1
R502
@ 0_0402_5%

CPUT1_LPR_F

CLK_CPU_BCLK# 4

39

1.05VS

CLKSEL1

CLK_CPU_BCLK 4

CPUC1_LPR_F
VDDSRC_IO

53

Cardbus usage for JALA0

2 @

1
2
R265
@ 1K_0402_5%

D_CK_SCLK 14,15,20

VDD48

CK_PWRGD

C300 1

R264
2.2K_0402_5%
CLKSEL0 1
2

VDDREF

H_STP_CPU#

1
R217

52

CLK_VDDSRC

CK505_PWRGD

1
R251

CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed)

3VS

1
R514

CLK_VDD

3VS

CLK_VDDSRC

Table : ICS9LPRS387
Control

L22 2
1
KC FBM-L11-201209-221LMAT_0805
1
1
1
1
1
1
1
1
C340
C302
C301
C323
C335
C309
C337
C343
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

1.05VS

CLK_REQ#

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008
G

Sheet

16

of
H

50

MXM_B
10 PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_N[0..15]

160mil(4A)

PCIE_MTX_C_GRX_P[0..15]

10 PCIE_MTX_C_GRX_P[0..15]
10 PCIE_GTX_C_MRX_N[0..15]

DVT(JALA0)

PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

10 PCIE_GTX_C_MRX_P[0..15]

C500

L43 2
1
KC FBM-L11-201209-221LMAT_0805
PM@
L44 2
1
KC FBM-L11-201209-221LMAT_0805
PM@
1
C498

C503
PM@

SDVO_SCLK
SDVO_SDATA

SDVO_SCLK
R392 1
SDVO_SDATA R400 1

D_EC_SMB_CK1
D_EC_SMB_DA1

1
0.1U_0603_25V7K

JMXM1B
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0
CLK_PCIE_VGA#
CLK_PCIE_VGA

16 CLK_PCIE_VGA#
16 CLK_PCIE_VGA

VGA_ON 33
5VS

21 PLTRST_VGA#
22 HDA_SYNC_VGA
22 HDA_BITCLK_VGA

D_EC_SMB_DA1
D_EC_SMB_CK1
VGA_THERM_ALERT#
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_DDC_CLK
VGA_DDC_DATA
1
2HDA_SDIN3_VGA
R371
33_0402_5%
PM@
R5981
2 100K_0402_5%
@
ACIN_R
1
2

ACER MXM Design Guide V0.5

PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
C

PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2

25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107

PEX_RX15#
PEX_RX15
GND
PEX_RX14#
PEX_RX14
GND
PEX_RX13#
PEX_RX13
GND
PEX_RX12#
PEX_RX12
GND
PEX_RX11#
PEX_RX11
GND
PEX_RX10#
PEX_RX10
GND
PEX_RX9#
PEX_RX9
GND
PEX_RX8#
PEX_RX8
GND
PEX_RX7#
PEX_RX7
GND
PEX_RX6#
PEX_RX6
GND
PEX_RX5#
PEX_RX5
GND
PEX_RX4#
PEX_RX4
GND
PEX_RX3#
PEX_RX3
GND
PEX_RX2#
PEX_RX2
GND

PRSNT2#
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
PEX_TX2#
PEX_TX2

26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108

PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14

JALA0

PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13

31

3VS
EC_ACIN

D31 CH751H-40PT_SOD323-2
@
1
2

PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12

R599 0_0402_5%
@

PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11

PVT(Check)

PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
20,31
DVI_DET
20 VGA_DVI_TXC20 VGA_DVI_TXC

DVI_DET
VGA_DVI_TXCVGA_DVI_TXC

PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4

20 VGA_DVI_TXD220 VGA_DVI_TXD2

VGA_DVI_TXD2VGA_DVI_TXD2

PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3

20 VGA_DVI_TXD120 VGA_DVI_TXD1

VGA_DVI_TXD1VGA_DVI_TXD1

PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2

20 VGA_DVI_TXD020 VGA_DVI_TXD0

VGA_DVI_TXD0VGA_DVI_TXD0

PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5

231

QUASA_CA0481-230N00
CONN@

PEX_RX1#
GND
PEX_RX1
PEX_TX1#
GND
PEX_TX1
PEX_RX0#
GND
PEX_RX0
PEX_TX0#
GND
PEX_TX0
PEX_REFCLK#
PRSNT1#
PEX_REFCLK
TV_C/HDTV_Pr
CLK_REQ#
GND
PEX_RST#
TV_Y/HDTV_Y/TV_CVBS
HDA_SYNC
GND
HDA_BCLK
TV_CVBS/HDTV_Pb
SMB_DAT
GND
SMB_CLK
VGA_RED
THERM#
GND
VGA_HSYNC
VGA_GRN
VGA_VSYNC
GND
HDA_SDI
VGA_BLU
HDA_SDO
GND
IGP_UCLK#
LVDS_UCLK#
IGP_UCLK
LVDS_UCLK
GND
GND
DP_L3#
LVDS_UTX3#
DP_L3
LVDS_UTX3
AC/BATT#
GND
DP_L2#
LVDS_UTX2#
DP_L2
LVDS_UTX2
GND
GND
DP_L1#
LVDS_UTX1#
DP_L1
LVDS_UTX1
GND
GND
DP_L0#
LVDS_UTX0#
DP_L0
LVDS_UTX0
GND
GND
DVI_B_CLK
LVDS_LCLK#
DVI_B_CLK
LVDS_LCLK
DVI_B_HPD/DVI_C_HPD/GND
GND
DP_AUX#
LVDS_LTX3#
DP_AUX
LVDS_LTX3
GND
DP_HPD
DVI_B_TX2#
LVDS_LTX2#/DVI_C_TX2#
DVI_B_TX2
LVDS_LTX2/DVI_C_TX2
GND
GND
DVI_B_TX1#
LVDS_LTX1#/DVI_C_LTX1#
DVI_B_TX1
LVDS_LTX1/DVI_C_LTX1
GND
GND
DVI_B_TX0#
LVDS_LTX0#/DVI_C_LTX0#
DVI_B_TX0
LVDS_LTX0/DVI_C_LTX0
DVI_A_HPD
GND
DVI_A_CLK#
DDCC_DAT
DVI_A_CLK
DDCC_CLK
GND
LVDS_PPEN
DVI_A_TX2#
LVDS_BL_BRGHT
DVI_A_TX2
LVDS_BLEN
GND
DDCB_DAT
DVI_A_TX1#
DDCB_CLK
DVI_A_TX1
2V5RUN
GND
GND
DVI_A_TX0#
3V3RUN
DVI_A_TX0
3V3RUN
GND
3V3RUN

110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230

GND

232

GND

1.05VS

1.05VS

1.05VS

C598

4.7U_0805_10V4Z
PM@ 2
C179
@
0.1U_0402_16V4Z

C230
@
0.1U_0402_16V4Z

C138
@
0.1U_0402_16V4Z

C459
@
0.1U_0402_16V4Z

C170
@
0.1U_0402_16V4Z

For Return Path between GND and 1.05V

2.5VS

5VS

1
C599

C76

0.1U_0402_16V4Z
2 PM@

0.1U_0402_16V4Z
PM@ 2

VGA_CRT_B 19

VGA_TZCLKVGA_TZCLK

VGA_TZCLK- 18
VGA_TZCLK 18

VGA_TZOUT2VGA_TZOUT2

VGA_TZOUT2- 18
VGA_TZOUT2 18

VGA_TZOUT1VGA_TZOUT1

VGA_TZOUT1- 18
VGA_TZOUT1 18

VGA_TZOUT0VGA_TZOUT0

VGA_TZOUT0- 18
VGA_TZOUT0 18

VGA_TXCLKVGA_TXCLK

VGA_TXCLK- 18
VGA_TXCLK 18

VGA_TXOUT2VGA_TXOUT2

VGA_TXOUT2- 18
VGA_TXOUT2 18

VGA_TXOUT1VGA_TXOUT1

VGA_TXOUT1- 18
VGA_TXOUT1 18

VGA_TXOUT0VGA_TXOUT0

VGA_TXOUT0- 18
VGA_TXOUT0 18

I2CC_SDA
I2CC_SCL
ENVDD

I2CC_SDA 18
I2CC_SCL 18
ENVDD
18

ENBKL
VGA_DVI_SDATA
VGA_DVI_SCLK
2.5VS

C504

D_EC_SMB_DA1

0.1U_0402_16V4Z
PM@ 2

D EC_SMB_CK1

Q51
2N7002_SOT23
PM@

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DVT

Compal Electronics, Inc.

Compal Secret Data


2007/09/20

ENBKL
10,31
VGA_DVI_SDATA 20
VGA_DVI_SCLK 20

3VS

31,40 EC_SMB_CK1

Security Classification

VGA_CRT_G 19

VGA_CRT_B

Q50
2N7002_SOT23
PM@

Issued Date

HDA_RST_VGA# 22
VGA_CRT_R 19

VGA_CRT_G

3VS

31,40 EC_SMB_DA1

VGA_CRT_R

DVT

DVT(JALA0)

1V8RUN

1.05VS

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0

QUASA_CA0481-230N00
CONN@

DVT

1.05VS

PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1

2
G

PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15

31 VGA_THERM_ALERT#
9 VGA_CRT_HSYNC
19 VGA_CRT_VSYNC
19 VGA_DDC_CLK
19 VGA_DDC_DATA
22 HDA_SDIN3
22 HDA_SDOUT_VGA

109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229

2
G

1.8VS

1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
RUNPWROK
5VRUN
GND
GND
GND

DVT(JALA0)

L57 2
1
KC FBM-L11-201209-221LMAT_0805
PM@
L58 2
1
KC FBM-L11-201209-221LMAT_0805
PM@

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
GND
GND
GND
GND

1V8RUN

2
4
6
8
10
12
14
16
18
20
22
24

140mil(3.5A)

JMXM1A

1
3
5
7
9
11
13
15
17
19
21
23

MXM_B

GM@ 2 0_0402_5%
GM@ 2 0_0402_5%

680P_0402_50V7K 68P_0402_50V8J
2
2 PM@
PM@

8
8

160mil(4A)

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

17

of

50

+3VS

C372

2
G
1

INVTPWM

Q37
2N7002_SOT23
@

W=60mils
1

+LCDVDD

4.7U 0805_10V4Z
2

For GMCH DPST

C369
0.1U_0402_16V4Z

R307
100K_0402_5%

10K_0402_5%

0.047U_0402_16V7K
2

2N7002DW-T/R7_SOT363-6

R302
+3VS

3
Q39A

DPST_PWM 10

4.7U_0805_10V4Z

Q38
AO3413_SOT23-3

C370

2
6

4
GM@
2 0_0402_5%
PM@
2 0_0402_5%

R311 1

ENVDD

1
1K_0402_5%
1
C373

2
R309

A
3

1
3 2

NC7SZ14P5X_NL_SC70-5
@

2N7002DW-T/R7_SOT363-6

17

R312
100K_0402_5%

Q39B

R310 1

W=60mils
R313
300_0603_5%

10 GMCH_ENVDD

INVTPWM

U22

+3VS

+3V

NC

LCD POWER CIRCUIT

+LCDVDD

TXOUT0TXOUT0+
RP2
TXOUT1TXOUT1+
RP4
TXOUT2TXOUT2+

+3VS

RP6
1

TXCLKTXCLK+
R303
4.7K_0402_5%

31

BKOFF#

DISPOFF#

EMI

L24 2
1
KC FBM-L11-201209-221LMAT_0805

B+
DAC_BR G

L23 2
1
KC FBM-L11-201209-221LMAT_0805
C364

INVTPW

C363

DISPOF #

TZOUT2TZOUT2+

C367 820P_0402_50V7K
1
2
C366 820P_0402_50V7K
1
2
C365 820P_0402_50V7K
1
2

TZCLKTZCLK+

I2CC_SCL
I2CC_SDA

680P_0402_50V7K 68P_0402_50V8J
2
2

RP1

RP3
TXOUT1TXOUT1+

+INVPWR_B+
+3VS
17
17

I2CC_SCL
I2CC_SDA

I2CC_SCL
I2CC_SDA
TZOUT0TZOUT0+
TZOUT1+
TZOUT1TZOUT2+
TZOUT2TZCLKTZCLK+

23
23

USB20_N6
USB20_P6

0_0402_5%
R298 1
R297 1
0_0402_5%

2USB20_CMOS_N6
2USB20_CMOS_P6

GND
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

GND
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

1
2

VGA_TXOUT0VGA_TXOUT0+
0_0404_4P2R_5%
VGA_TXOUT1VGA_TXOUT1+
0_0404_4P2R_5%
VGA_TXOUT2VGA_TXOUT2+
0_0404_4P2R_5%
VGA_TXCLKVGA_TXCLK+
0_0404_4P2R_5%
VGA_TZOUT0VGA_TZOUT0+
0_0404_4P2R_5%
VGA_TZOUT1VGA_TZOUT1+
0_0404_4P2R_5%
VGA_TZOUT2VGA_TZOUT2+
0_0404_4P2R_5%
VGA_TZCLKVGA_TZCLK+
0_0404_4P2R_5%

VGA_TXOUT0- 17
VGA_TXOUT0+ 17
VGA_TXOUT1- 17
VGA_TXOUT1+ 17
VGA_TXOUT2- 17
VGA_TXOUT2+ 17
VGA_TXCLK- 17
VGA_TXCLK+ 17
VGA_TZOUT0- 17
VGA_TZOUT0+ 17
VGA_TZOUT1- 17
VGA_TZOUT1+ 17
VGA_TZOUT2- 17
VGA_TZOUT2+ 17
VGA_TZCLK- 17
VGA_TZCLK+ 17

1
2

GMCH_LCD_CLK
4
GMCH_LCD_DATA
3
GM@ 0_0404_4P2R_5%

2
1

3
4
GM@
3
4
GM@
3
4
GM@
3
4
GM@
3
4
GM@
3
4
GM@
3
4
GM@
3
4
GM@

GMCH_LCD_CLK 10
GMCH_LCD_DATA 10
B

TXOUT0TXOUT0+

JLVDS1
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

1
2

4
3
PM@
4
3
PM@
4
3
PM@
4
3
PM@
4
3
PM@
4
3
PM@
4
3
PM@
4
3
PM@

Change 220P to 820P DVT(JALA0)

LCD/PANEL BD. Conn.

DVT(JALA0)

1
2

1
2
RP10
1
2
RP12
1
2
RP14
1
2
RP16

TZOUT1TZOUT1+

CH751H-40PT_SOD323-2

+INVPWR_B+

W=40mils

D18
BKOFF#

RP8
TZOUT0TZOUT0+

1
2

DAC_BRIG

RP5

DAC_BRIG 31

INVTPWM R301 1
DISPOFF#

2 0_0402_5%

TXOUT2TXOUT2+

INVT_PWM 31

RP7
TXCLKTXCLK+

+LCDVDD

RP9

W=60mils

TZOUT0TZOUT0+

+LCDVDD

TXOUT0TXOUT0+

+3VS

TXOUT2+
TXOUT2-

C1
0.1U_0402_16V4Z

C371
10U_0805_10V4Z

C368

TZOUT2TZOUT2+

0.1U_0402_16V4Z

TXCLKTXCLK+

2
1
2
1

2
1
RP11
2
1
RP13
2
1
RP15
2
1
RP17

TZOUT1TZOUT1+

TXOUT1TXOUT1+

2
1

TZCLKTZCLK+

GMCH_TXOUT0GMCH_TXOUT0+
0_0404_4P2R_5%
GMCH_TXOUT1GMCH_TXOUT1+
0_0404_4P2R_5%
GMCH_TXOUT2GMCH_TXOUT2+
0_0404_4P2R_5%
GMCH_TXCLKGMCH_TXCLK+
0_0404_4P2R_5%
GMCH_TZOUT0GMCH_TZOUT0+
0_0404_4P2R_5%
GMCH_TZOUT1GMCH_TZOUT1+
0_0404_4P2R_5%
GMCH_TZOUT2GMCH_TZOUT2+
0_0404_4P2R_5%
GMCH_TZCLKGMCH_TZCLK+
0_0404_4P2R_5%

GMCH_TXOUT0- 10
GMCH_TXOUT0+ 10
GMCH_TXOUT1- 10
GMCH_TXOUT1+ 10
GMCH_TXOUT2- 10
GMCH_TXOUT2+ 10
GMCH_TXCLK- 10
GMCH_TXCLK+ 10
GMCH_TZOUT0- 10
GMCH_TZOUT0+ 10
GMCH_TZOUT1- 10
GMCH_TZOUT1+ 10
GMCH_TZOUT2- 10
GMCH_TZOUT2+ 10
GMCH_TZCLK- 10
GMCH_TZCLK+ 10

+3VS

ACES_88242-4001
CONN@
A

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

18

of

50

CRT Connector

D24

D23

W=40mils

D22

+5VS

+R_CRT_VCC

+CRT_VCC

D5

DAN217_SC59 DAN217_SC59 DAN217_SC59


F1

2
1.1A_6VDC_FUSE
1

C65
0.1U_0402_16V4Z
2

DVT

JALA0

RB491D_SC59-3

+3VS

L30
CRT_G
L28
L26

R362

1
C419

R348

150_0402_1%

C409
GM@

150_0402_1%
2

L31

CRT G 1
2
FCM2012C-800_0805

L29

CRT_B_1
2
FCM2012C-800_0805

L27

2
FCM2012C-800_0805

CRT_R_2

2
FCM2012C-800_0805

CRT_G_2

2
FCM2012C-800_0805

CRT_B_2

JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

R368

CRT_B

CRT_R_1
2
FCM2012C-800_0805

2
2
10P_0402_50V8J

C401
GM@

C423
GM@

2
10P_0402_50V8J

C418

C408

GM@ 2

GM@ 2
GM@ 2
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J

150_0402_1%

change to 15pf for ATI M82

+CRT_VCC

2
10_0603_5%

CRT_HSYNC_2

1
L1

2
10_0603_5%

CRT_VSYNC_2
1
1
C34

P
2

1
10K_0402_5%

C69
10P_0402_50V8J

R19
100K_0402_5%

1
DSUB_15

2
C75
68P_0402_50V8J 1

CRT_HSYNC_1

CRT_DET# 23
DSUB_12

10P_0402_50V8J

2
1
R653
MAIN@ 0_0402_5%

D_CRT_HSYNC

16
17

SUYIN_070549FR015S208CR
CONN@

2
100P_0402_50V8J

U5

CRT_HSYNC

OE#

2
R39
5

2
0.1U_0402_16V4Z

C28

1
L2

DVT(Check)
C71

C402
10P_0402_50V8J
GM@

change to 12pf for Discrete

DVT(Check)

DVT(Check)

DVT(Check)

10P_0402_50V8J

change to 15pf for Discrete

C420
C410
10P_0402_50V8J 10P_0402_50V8J
GM@ 2
GM@ 2

CRT_R

38
2

SN74AHCT1G125DCKR_SC70-5

W=40mils

C20
+CRT_VCC
68P_0402_50V8J

+CRT_VCC

DVT

2
0.1U_0402_16V4Z

CRT_VSYNC

OE#

C35

CRT_VSYNC_1

2
1
R654
MAIN@ 0_0402_5%

U3
D_CRT_VSYNC

38

SN74AHCT1G125DCKR_SC70-5

+CRT_VCC

Place closed to chipset


pull-up 10k on AMD M82M MXM side

CRT_VSYNC

R83

2 GM@ 30.1_0402_1%

CRT_HSYNC

2 GM@ 0_0402_5%

CRT_B_S

10 GMCH_CRT_B

R374 1

10 GMCH_CRT_G

R378 1

10 GMCH_CRT_R

R390 1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

CRT_G_S
CRT_R_S

R66

2 PM@ 0_0402_5%

CRT_VSYNC

R82

2 PM@ 0_0402_5%

CRT_HSYNC

17 VGA_CRT_B

R375 1

2 PM@ 0_0402_5%

CRT_B_S

17 VGA_CRT_G

R379 1

2 PM@ 0_0402_5%

CRT_G_S

17 VGA_CRT_R

R391 1

2 PM@ 0_0402_5%

CRT_R_S

17 VGA_CRT_HSYNC

DSUB_12

2
G

+5VS

GMCH_CRT_DATA 10

Q52
2N7002_SOT23

U26
28,31,34,38 EC_DOCKIN#

1
15
CRT_R S 4
CRT_G S 7
CRT_B S 9
12

17 VGA_CRT_VSYNC

38 D_DDC_DATA

2
G

2 GM@ 30.1_0402_1%

VGA_DDC_DATA 17

2 R373
PM@ 0_0402_5%

R372 GM@ 0_0402_5%


2
1

SEL
OE#
1A
2A
3A
4A

VCC

16

1B1
2B1
3B1
4B1

2
5
11
14

1B2
2B2
3B2
4B2

3
6
10
13

38

D_DDC_CLK

DSUB_15

3
S

10 GMCH_CRT_HSYNC

R67

10 GMCH_CRT_VSYNC

L : A-->B1
H: A-->B2

NOTE:

pull-up 2.2k on GPU side

R23
4.7K_0402_5%
2

R40
4.7K_0402_5%

+3VS

Q53
2N7002_SOT23

D_CRT_R 38
D_CRT_G 38
D_CRT_B 38

2
1
R377
GM@ 0_0402_5%
1

DVT

GMCH_CRT_CLK 10

2 R380
PM@ 0_0402_5%

VGA_DDC_CLK 17

pull-up 2.2k on GPU side

CRT_R
CRT_G
CRT_B

pull-up 10k on AMD M82M MXM side

GND

FSAV330MTC_TSSOP16
MAIN@
R583 0_0402_5%
1
2 VALUE@
R584 0_0402_5%
1
2 VALUE@
R585 0_0402_5%
1
2 VALUE@

JALA0

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


E

19

of

50

HDMI_5V_OUT

HDMI_HPD

MP

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMI_5V_OUT

R91
4.7K_0402_5%

HDMI_SDATA
HDMI_SCLK

HDMI_SCLK

HDMI_R_CK-

HDMI_R_CK
HDMI_R_D0-

Q8
BSH111_SOT23
1

HDMI_SDATA

HDMI_R_D0
HDMI_R_D1-

DVT

Q47
BSH111_SOT23

VGA_DVI_SDATA

D_DVI_SDATA 38

R86
4.7K_0402_5%

Q7
BSH111_SOT23
1
D

DVT

JHDMI1

3
G

VGA_DVI_SCLK

D_DVI_SCLK 38

VGA_DVI_SDATA

17 VGA_DVI_SDATA

HDMI_5V_OUT

3.3V Level

EC_DOCKIN#_S0

38 EC_DOCKIN#_S0

R84
4.7K_0402_5%

2 4.7K_0402_5%
2 2.2K_0402_5%

MP

3
G

R602 1 PM@
R603 1 @

3VS
5VS

DDC to HDMI CONN

VGA_DVI_SCLK

17 VGA_DVI_SCLK

R85
4.7K_0402_5%

2 4.7K_0402_5%
2 2.2K_0402_5%

EC_DOCKIN

R600 1 PM@
R601 1 @

3VS
5VS

3.3V Level

DDC to Docking

38 EC_DOCKIN

Q6
BSH111_SOT23

HDMI_R_D1
HDMI_R_D2-

Place closed to JHDMI1

HDMI_R_D2

1
R414

2
0_0402_5%

20
21
22
23

TYCO_1939864-1
CONN@

MP:Update HDMI Hot Plug DET circuit.


HDMI_5V_OUT

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

D_DVI_DET 38
HDMI_HPD

1
2
R686 0_0402_5%

PM@

U29

1
R672 @

DVI DET

D7

5VS

D_DVI_SCLK
D_DVI_SDATA

DVT
3VS

3VS

3VS

3VS

2
D21
1
R349

1
R343
1
R351
1
R342
1
R350

1
R345
1
R353
1
R344
1
R352

2
4.7K_0402_5%
2
0_0402_5%

2
@ 4.7K_0402_5%
2
0_0402_5%
2
@ 4.7K_0402_5%
2
0_0402_5%

1
R418

2
0_0402_5%

HDMI_R_CK

HDMI_TX0-

1
R419

2
0_0402_5%

HDMI_R_D0-

D25
SS1040_SOD123

HDMI_SCLK
HDMI_SDATA

L34

3VS_D80

U24

17
17
17
17
17
17
17
17

MS

VGA_DVI_TXC
VGA_DVI_TXCVGA_DVI_TXD0
VGA_DVI_TXD0VGA_DVI_TXD1
VGA_DVI_TXD1VGA_DVI_TXD2
VGA_DVI_TXD2-

VGA_DVI_TXC
VGA_DVI_TXCVGA_DVI_TXD0
VGA_DVI_TXD0VGA_DVI_TXD1
VGA_DVI_TXD1VGA_DVI_TXD2
VGA_DVI_TXD2T16
T15

PAD
PAD

@
@

T17

PAD

A3

SEL_OUT
SEL_IN

19
20

SCL/S3
SDA/S2

OE

1
17
54
56

MS
TEST_OUT
TEST_IN
OE

A0
A1
A2
A3

49
50
51
52

A0/S4
A1/S5
A2/S6
A3/S7

MS
@

A0

NOTE:

D0+
D0D1+
D1D2+
D2D3+
D3-

16
55

14,15,16 D_CK_SCLK
14,15,16 D_CK_SDATA

A2

4
5
7
8
9
10
12
13

L : D-->A
H: D-->B

A1

22

@ WCM-2012-900T_0805

OE
1
CH751H-40PT_SOD323-2
2
4.7K_0402_5%

2
@ 4.7K_0402_5%
2
0_0402_5%
2
@ 4.7K_0402_5%
2
0_0402_5%

HDMI_CLK
3VS

C421

AVDD

8
3
6
4

VCC
1B
2B
GND

HDMI_R_CK-

2
0_0402_5%

L33

C417

0.1U_0402_ 6V4Z
2
2
0.1U_0402_16V4Z

D3-_B
D3+_B
D2-_B
D2+_B
D1-_B
D1+_B
D0-_B
D0+_B

25
26
28
29
31
32
34
35

D3-_A
D3+_A
D2-_A
D2+_A
D1-_A
D1+_A
D0-_A
D0+_A

37
38
40
41
43
44
46
47

NC
T-pad

18
57

HDMI_TX0

1
R421

2
0_0402_5%

HDMI_R_D0

HDMI_TX1-

1
R422

2
0_0402_5%

HDMI_R_D1B

HDMI_TX2HDMI_TX2
HDMI_TX1HDMI_TX1
HDMI_TX0HDMI_TX0
HDMI_CLKHDMI_CLK

L35

@ WCM-2012-900T_0805

D_DVI_TXD2- 38
D_DVI_TXD2 38
D_DVI_TXD1- 38
D_DVI_TXD1 38
D_DVI_TXD0- 38
D_DVI_TXD0 38
D_DVI_TXC- 38
D_DVI_TXC 38

HDMI_TX1

1
R426

2
0_0402_5%

HDMI_R_D1

HDMI_TX2-

1
R430

2
0_0402_5%

HDMI_R_D2-

L36

AVSS

8
3
6
4

23

3VS

1
R357
1
R359 @

1
R415

HDMI_5V_OUT

VCC
1B
2B
GND

3
14
21
27
30
33
39
42
45
53

3VS
B

HDMI_CLK-

@ WCM-2012-900T_0805

SN74CBTD3306CPWR_TSSOP8
@

DVT

1.1A_6VDC_FUSE

MP

2
6
11
15
24
36
48

1A
2A
1OE#
2OE#

W=40mils

C441
0.1U_0402_16V4Z

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

2
5
1
7

HDMI_5V

RB491D_SC59-3

SN74CBTD3306CPWR_TSSOP8
@
HDMI_5V_OUT
U40
VGA_DVI_SCLK
VGA_DVI_SDATA
EC_DOCKIN

F2

1A
2A
1OE#
2OE#

D35
CH751H-40PT_SOD323-2
0.1U_0402_16V4Z
@

EC_DVI_DET 31

U39

2
5
1
7

17 31

C430

OE
2
0_0402_5%

PVT2
VGA_DVI_SCLK
VGA_DVI_SDATA
EC_DOCKIN# S0

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7

74AHCT1G125GW_SOT353-5

R412
100K_0402_5%

HDMI_5V_OUT

3VS

A
G

2
1
R396
2.2K_0402_5%

5
P

0.1U_0402_16V4Z
2

OE#

C435

@ WCM-2012-900T_0805
HDMI_TX2

1
R433

PI3HDMI412ADZBE_TQFN56_8X8

HDMI_R_D2

2
0_0402_5%

SMBus Address: 1100 000X (b)

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

20

of

50

3VS

DMI for ESI-compatible operation


RP44

1
2
3
4
D

PCI_GNT#1

PCI_REQ#2
PCI_FRAME#
PCI_DEVSEL#
PCI_REQ#1

8
7
6
5

Low= DMI for ESI-compatible operation


High= Default* (Internal pull-up)
D

8.2K_1206_8P4R_5%
PCI_PIRQE#
PCI_PERR#
PCI_IRDY#
PCI_PLOCK#

8
7
6
5
8.2K_1206_8P4R_5%

3VS
RP47

1
2
3
4

PCI_PIRQH#
PCI_REQ#0
PCI_PIRQG#
PCI_PIRQB#

8
7
6
5
8.2K_1206_8P4R_5%
RP48

1
2
3
4

PCI_SERR#
PCI_PIRQA#
PCI_PIRQC#
PCI_PIRQF#

8
7
6
5

8.2K_1206_8P4R_5%
RP45

1
2
3
4

PCI_REQ#3
PCI_TRDY#
PCI_STOP#
PCI_PIRQD#

8
7
6
5
8.2K_1206_8P4R_5%

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

A16 Swap Override Strap


Low= A16 swap override Enable
High= Default*

PCI_GNT#3
R420

D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

J5
E1
J6
C4

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI

F1
G4
B6
A7
F13
F12
E6
F6

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2
PCI_REQ#3
PCI_GNT#3

C/BE0#
C/BE1#
C/BE2#
C/BE3#

D8
B4
D6
A5

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

PCI_IRDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLTRST#
PCICLK
PME#

C14
D4
R2

PLT_RST#
CLK_PCI_ICH

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PCI_REQ#0 25
PCI_GNT#0 25
@

PAD

T4

PAD

T22

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

25
25
25
25

PCI_IRDY# 25
PCI_PAR 25
PCI_RST# 25
PCI_DEVSEL# 25

Place closely pin B10


CLK_PCI_ICH

PCI_STOP# 25
PCI_TRDY# 25
PCI_FRAME# 25

1
2
3
4

U10B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

R388
10_0402_5%
@

PLT_RST# 8,23,26,27,31
CLK_PCI_ICH 16

C425
10P_0402_50V8J
@

Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676
ICH9MB@

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

H4
K6
F2
G2

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

DVT

ICH9-M: SA00002AN10
(S IC NH82801IBM QP23 A2 FCBGA 676P ICH9M)

PVT

ICH9-M: SA00002JH00
(S IC AF82801IBM QT09 A3 PBG 676P ICH9M)

25 PCI_AD[0..31]

RP46

PCI_PIRQE# 25

Pre-MP ICH9-M: SA00002JH70


(S IC AF82801IBM SLB8Q A3 676P ICH9M ABO!)

2 1K_0402_5% PCI_GNT#3
@

PCI

LPC*

R382

1
1

@
@

U8
2 B

2 1K_0402_5% PCI_GNT#0
2 1K_0402_5%

1
3VS

Y
A

NC7SZ08P5X_NL_SC70-5

2
R59

1
100_0402_5%
PM@

PLTRST_VGA# 17

For VGA/B

R58
100K_0402_5%
PM@

PM@
SPI_CS#1 23

R93

R57
100K_0402_5%

SPI

PLT_RST_BUF# 29

P
Y

NC7SZ08P5X_NL_SC70-5

Boot BIOS Loaction

SPI_CS#1

U7
2 B

PCI_GNT#0

PLT_RST#

Boot BIOS Strap

3VS

JALA0

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

21

of

50

NC

OUT

NC

IN

C118
18P_0402_50V8J
2
1

RTCVCC

1
2
R394
20K_0402_5%

RTCVCC

close to RAM door

1
2
R395
20K_0402_5%

close to RAM door

1
2
R376
@
10K_0603_5%
C426
1U_0603_10V6K
1
2

R408
332K_0402_1%

RTCVCC

ICH_INTVRMEN

High = Internal VR Enable

RTCRST#
SRTCRST#
INTRUDER#

ICH_INTVRMEN

B22
A22

INTVRMEN
LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14
G13
D14

LAN_RXD0
LAN_RXD1
LAN_RXD2

D13
D12
E13

LAN_TXD_0
LAN_TXD_1
LAN_TXD_2

B10

GPIO56

B28
B27

GLAN_COMPI
GLAN_COMPO

AF6
AH4

HDA_BIT_CLK
HDA_SYNC

1
2

R397

33 HDA_BITCLK_MDC

SATA_LED#

R467

33 HDA_SYNC_MDC

R469

33 HDA_RST_MDC#

R470

3V

34
33
8
17
R77

33 HDA_SDOUT_MDC

GLAN_COMP
2
24.9_0402_1%
HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%

1
1
1
1

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
R468

HDA_SDOUT_ICH
33_0402_5%

10K_0402_5%

AE7
AF4
AG4
AH3
AE5

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

AG5

HDA_SDOUT
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

AG8

SATALED#

SATA for HDD

30 SATA_DTX_C_IRX_N0
30 SATA_DTX_C_IRX_P0

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

AJ16
AH16
AF17
AG17

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA for ODD

30 SATA_DTX_C_IRX_N1
30 SATA_DTX_C_IRX_P1

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

AH13
AJ13
AG14
AF14

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AG7
AE8
32

SATA_LED#

ICH9-M ES_FCBGA676
B

1
R471
1
R473
1
R456
1
R472

HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%
HDA_SDOUT_ICH
2
33_0402_5%

GM@ 1
R457
GM@ 1
R459
GM@ 1
R466
GM@ 1
R458

HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%
HDA_SDOUT_ICH
2
33_0402_5%

34 HDA_BITCLK_AUDIO

HDA for AUDIO

34 HDA_SYNC_AUDIO
34 HDA_RST_AUDIO#
34 HDA_SDOUT_AUDIO

8 HDA_SYNC_MCH

HDA for GMCH

8 HDA_RST_MCH#
8 HDA_SDOUT_MCH

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

K5
K4
L6
K2

FWH4/LFRAME#

K3

LPC_FRAME#

LDRQ0#
LDRQ1#/GPIO23

J3
J1

ICH9MB@

SATA_ITX_DRX_P0

SATA_ITX_DRX_P1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

VCC_HDA_ICH

HDA for VGA

17 HDA_SYNC_VGA
17 HDA_RST_VGA#

17 HDA_SDOUT_VGA

R454
1K_0402_5%
@

ICH_TP3
ICH_TP3
R72
1K_0402_5%
@

23

HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
1K_0402_5%
HDA_SDOUT_ICH
2
33_0402_5%

R423 2

N7
AJ27

EC_GA20
H_A20M#

DPRSTP#
DPSLP#

AJ25
AE23

DPRSTP# R462 1
DPSLP#
R463 1

FERR#

AJ26

FERR#

CPUPWRGD

AD22

H_PWRGOOD

IGNNE#

AF25

H_IGNNE#

INIT#
INTR
RCIN#

AE22
AG25
L3

H_INIT#
H_INTR
EC_KBRST#

NMI
SMI#

AF23
AF24

H_NMI
H_SMI#

STPCLK#

AH27

H_STPCLK#

THRMTRIP#

AG26

THRMTRIP_ICH#

TP12

AG27

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AH11
AJ11
AG12
AF12

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AH9
AJ9
AE10
AF10

SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS

AH18
AJ18
AJ7
AH7

DVT

1 10K_0402_5%
EC_GA20 31
H_A20M# 4

HDA_SDOUT

RSVD

Enter XOR Chain

Normal Operation

Set PCIE port config bit 1

0_0402_5% H_DPRSTP#
0_0402_5% H_DPSLP#

2
2

1
R461

H_DPRSTP# 5,8,46
H_DPSLP# 5

H_FERR#

2
56_0402_5%

H_FERR# 4

H_PWRGOOD 5

2
R475

1
56_0402_5%

2
R428

1
10K_0402_5%

1.05VS

H_IGNNE# 4
H_INIT#
H_INTR

4
4

3VS
EC_KBRST# 31

H_NMI
H_SMI#

4
4

R258 need to place within 2" of ICH9M


R257 must be place within 2" of R258 w/o stub.

H_STPCLK# 4
R460 1

2 54.9_0402_1%

H_THERMTRIP#

2
R474

CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS

H_THERMTRIP# 4,8

1
56_0402_5%

1.05VS

CLK_PCIE_SATA# 16
CLK_PCIE_SATA 16
R162 1

2 24.9_0402_1%

10mils width less than 500mils


ICH9-M: SA00002AN10
(S IC NH82801IBM QP23 A2 FCBGA 676P
ICH9M)

1
C506
1
C505

SATA_ITX_C_DRX_N0
2
0.01U_0402_16V7K
SATA_ITX_C_DRX_P0
2
0.01U_0402_16V7K

1
C502
1
C501

SATA_ITX_C_DRX_N1
2
0.01U_0402_16V7K
SATA_ITX_C_DRX_P1
2
0.01U_0402_16V7K

SATA_ITX_C_DRX_N0

PVT ICH9-M: SA00002JH00


(S IC AF82801IBM QT09 A3 PBG 676P ICH9M)
B

Pre-MP ICH9-M: SA00002JH70


30
(S IC AF82801IBM SLB8Q A3 676P ICH9M ABO!)

SATA_ITX_C_DRX_P0 30

SATA_ITX_C_DRX_N1 30
SATA_ITX_C_DRX_P1 30

R175
@ 330_0402_5%
1
2

DVT(Check)

Q14

2
B

2SC2411K_SOT23
@

Flash Descriptor Security Override Strap

Low= Descriptor Security override


High= Default* (Internal pull-up)

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

56_0402_5%

H_THERMTRIP#

Description

56_0402_5%

3VS

GPIO33

MAINPWON 40,41

XOR Chain Entrance Strap

HDA_SDOUT_ICH

PM@ 1
R480
PM@ 1
R479
PM@ 1
R478
PM@ 1
R481

31
31
31
31

1.05VS
17 HDA_BITCLK_VGA

LPC_FRAME# 31

A20GATE
A20M#

close ICH9
SATA_ITX_DRX_N0

SATA_ITX_DRX_N1
8 HDA_BITCLK_MCH

1.05VS
H_DPRSTP#
R476
H_DPSLP#
R477
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

HDA_RST#

SATA_LED#

ICH_GPIO56

R381

U10A

RTCX1
RTCX2

ICH_GPIO56

1.5VS_PCIE_ICH

Keep ME RTC Registers OPEN

A25
F20
C22

1
2
R381
@
10K_0603_5%
C453
1U_0603_10V6K
1
2

Need check

10K_0402_5%

OPEN

C23
C24

3VS

R163

Keep CMOS

ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#

ICH_RTCX2

TPM Settings

SM_INTRUDER#

Clear ME RTC Registers SHORT

SATA

32.768KHZ_12.5P_MC-306

SHORT

LPC

1M_0402_5%

R376

Clear CMOS

CPU

X1

CMOS Settings

RTC

R411

ICH_RTCX1
R78
10M_0402_5%
2
1

C117
18P_0402_50V8J
2
1

LAN / GLAN

RTCVCC

IHDA

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

22

of

50

+3VS

DVT

1
1

A20

TP11

AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8

GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5

M7
AJ24
B21
AH20
AJ20
AJ21

SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10

C462 2
C465 2

T32
T33
T34
T35

ICH SPI ROM for iTPM & ME

CL_DATA0 8

CL_RST0#
CL_RST1#

@
@
@
@

PAD
PAD
PAD
PAD

N29
N28
P27
P26

PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2

L29
L28
M27
M26
J29
J28
K27
K26

PERN3
PERP3
PETN3
PETP3

26
26
26
26

PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
PCIE_ITX_C_PRX_N5
PCIE_ITX_C_PRX_P5

1
1

PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
0.1U_0402_16V7K
PCIE_ITX_PRX_N5
0.1U_0402_16V7K
PCIE_ITX_PRX_P5

E29
E28
F27
F26

PERN5
PERP5
PETN5
PETP5

C29
C28
D27
D26

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

JALA0 (ICH Enable Strap for iTPM)

1
2

R165
10K_0402_5%

1
1

1
1
21

ICH SPI_MOSI
CH_SPI_MISO

MAIN@

R61
R80

1
1

JALA0
3

2
Q13G
2N7002_SOT23

D23
D24
F23

SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6

2 15_0402_5% ICH_SPI_MOSI_R
2 15_0402_5% ICH_SPI_MISO_R

D25
E23

SPI_MOSI
SPI_MISO

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11

N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3

USB_OC#0

30

USB_OC#2

29

USB_OC#4

GPIO49

Low= Desktop used


High= Mobile* (Internal pull-up)

USBRBIAS
2
1
R158
Within 500 mils
22.6_0402_1%

SPI ROM Footprint 200mil


4MB Flash

+3VS

VDD
SCK
SI
SO

8
6
5
2

MX25L3205DM2I-12G_SO8-S

ICH_SPI_CLK
ICH_SPI_MOSI
ICH_SPI_MISO

PAD

1
2
1
R384

2
@ 10K_0402_5%

U28
ICH_PWROK

JALA0

PAD

T5

PAD

T19

2
1
+3V
R393
100K_0402_5%
2
1
ACIN
D26
CH751H-40PT_SOD323-2

EC_PWROK

VGATE

R176
10K_0402_5%
<BOM Structure>

CL_RST#0 8
ICH_GPIO24 @
ICH_GPIO10
ICH_ACIN
ICH_GPIO9 @

1 0_0402_5%
+3V

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47

AG2
AG1

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

V27
V26
U29
U28

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y27
Y26
W29
W28

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB27
AB26
AA29
AA28

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3

DMI_CLKN
DMI_CLKP

SPI
USB

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

T26
T25

CLK_PCIE_ICH#
CLK_PCIE_ICH

AF29
AF28

DMI_IRCOMP

AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0

8
8
8
8

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1

8
8
8
8

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2

8
8
8
8

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3

8
8
8
8

EC_PWROK 31,33

NC7SZ08P5X_NL_SC70-5
C

@
R199 2
1 0_0402_5%
Q18
MMBT3906_SOT23-3
SB_RSMRST#
1
3

DVT

31,39,42

EC_RSMRST# 31

1
R197

2
4.7K_0402_5%

+3V

D12A
1
6
2
BAV99DW-7_SOT363
D12B
4
3
5

R196
2.2K_0402_5%

BAV99DW-7_SOT363

+3VS

CLK_PCIE_ICH# 16
CLK_PCIE_ICH 16
R150 24.9_0402_1%
1
2

USB20_N0
USB20_P0

R398
3.24K_0402_1%

Within 500 mils


+1.5VS_PCIE_ICH

USB20_N0 30
USB20_P0 30

CL_VREF0_ICH

USB Conn.
New Card usage for JAL90

USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8

USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8

USB20_N10
USB20_P10

30
30
38
38
29
29
30
30
18
18
29
29
29
29

USB20_N10 30
USB20_P10 30

C428

USB Conn.

R399
453_0402_1%

0.1U_0402_16V4Z
2

CMOS Camera
USB/B
Bluetooth

+3V

DOCKING Conn.
Mini Card(Robson)

R70
3.24K_0402_1%

Mini Card(WLAN)
CL_VREF1_ICH

Finger Print

C127

USBRBIAS
USBRBIAS#

R71
453_0402_1%

0.1U_0402_16V4Z
2

ICH9-M ES_FCBGA676
ICH9MB@

SA000021A00 ( MX25L3205DM2I-12G / 32M bit / 86MHz )


ICH_SPI_CLK 32
ICH_SPI_MOSI 32
ICH_SPI_MISO 32

SPI4MB@

JALA0

No Reboot Strap
Low= Default*

SB_SPKRHigh= "No Reboot"

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

2008/09/20

Deciphered Date

Title

SCHEMATIC MB A4221

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
C

401552

Date

EC_PWROK

T6

CL_VREF0_ICH
CL_VREF1_ICH

DMI_ZCOMP
DMI_IRCOMP

2 15_0402_5% ICH_SPI_CLK_R
2 15_0402_5% ICH_SPI_CS0#_R
SPI_CS#1

30

2
10K_0402_5%

ICH9-M: SA00002JH70
R200
(S IC AF82801 BM SLB8Q A3 676P ICH9M ABO!)
10K_0402_5%
DVT ICH9-M: SA00002AN10
PVT ICH9-M: SA00002JH00
(S IC AF82801IBM QT09 A3 PBG 676P ICH9M)
U10D(S IC NH82801IBM QP23 A2 FCBGA 676P ICH9M)

PERN4
PERP4
PETN4
PETP4

R52
R79

1
R386

R385 2
@

A16
C18
C11
C20

2
10K_0402_5%

No used Integrated LAN,


connecting to GND

ICH_PWROK

Pre-MP

G29
G28
H27
H26

ICH_SPI_CLK
ICH_SPI_CS0

CL_DATA0
CL_DATA1

PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4

U6

PVT(Add inner pad length for 150mil)

CL_CLK0 8

F22
C19

MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9

1
1

DMI Termination Voltage

CE#
WP#
HOLD#
VSS

F24
B19

0.1U_0402_16V7K
0.1U_0402_16V7K

High: CRT Plugged

1
3
7
4

CL_CLK0
CL_CLK1

1
1

1K_0402_1%

ICH_SPI_CS0#
ICH_SPI_WP#
ICH_SPI_HOLD#

PM_SLP_M#

C25
A19

CK_PWRGD 16

ICH_PWROK

F21
D18

1
R389

DVT

DVT

CK_PWRGD

R6

CL_VREF0
CL_VREF1

LAN_RST#

C167
10P_0402_50V8J
@

PLT_RST# 8,21,26,27,31

B16

C455 2
C452 2

R27

2
0_0402_5%

C494
10P_0402_50V8J
@

PM_DPRSLPVR 8,46

SLP_M#

PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_C_PRX_N4
PCIE_ITX_C_PRX_P4

C443 2
C445 2

SATA
GPIO

PVT

2
100_0402_5%

PBTN_OUT# 31

1
R407
SB_RSMRST#

R5

CLPWROK

29
29
29
29

Low= Disable*
High= iTPM enable by MCH strap

32 ICH_SPI_CS0#
32 ICH_SPI_WP#
32 ICH_SPI_HOLD#

D22

For Robson2

CRT_DET

3.3K_0402_5%
3.3K_0402_5%

RSMRST#

1
1

+3VS

CRT_DET#

LAN_RST#

C457 2
C456 2

For Card Reader

19

PBTN_OUT#

D20

PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3

USB_OC#9
USB_OC#5
USB_OC#6
USB_OC#7

USB_OC#3
USB_OC#10
USB_OC#11
USB_OC#8

R3

LAN_RST#

CK_PWRGD

+3VS

8
7
6
5

2
2

VRMPWRGD

B13

PWRBTN#

BATLOW#

ICH_PWROK 8

1
R106
PM_BATLOW#

27
27
27
27

Internal TPM Strap

R81
R51

D21

New Card usage for JAL90

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2

DPRSLPVR

For PCIE LAN

10K_1206_8P4R_5%

+3VS

ICH_TP8
ICH_TP9
ICH_TP10

ICH_PWROK

M2

DPRSLPVR/GPIO16

PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
0.1U_0402_16V7K
PCIE_ITX_PRX_N3
0.1U_0402_16V7K
PCIE_ITX_PRX_P3

DVT

RP50

29
29
29
29

For Wireless LAN

10K_1206_8P4R_5%

SPI_MOSI

@
@
@

JALA0 (iTPM physical presence)

DVT(JALA0)

8
7
6
5

1
2
3
4

PAD
PAD
PAD

WAKE#
SERIRQ
THRM#

ICH9-M ES_FCBGA676
ICH9MB@

RP49
1
2
3
4

SB_SPKR

CLKRUN#

PM_SLP_S3# 31
PM_SLP_S4# 31
PM_SLP_S5# 31

34
SB_SPKR
8 MCH_ICH_SYNC#
22
ICH_TP3
T12
T13
T14

S4_STATE#

G20

T11

1
2

ICH_GPIO57
R74
100K_0402_5%
VALUE@

2 USB_OC#1
10K_0402_5%
2 USB_OC#4
10K_0402_5%

1
R431
1
R108

+3V

@
@

C10

PWROK

PAD

CR_WAKE#
PAD
T7
T20 PAD
16 SATA_CLKREQ#

PROJECT_ID0
2
10K_0402_5%
PM_DPRSLPVR
2
100K_0402_5%
ICH_GPIO49
2
1K_0402_5%
@

L4

ICH_GPIO13
ICH_GPIO17
ICH_GPIO18
ICH_GPIO20
CR_WAKE#
ICH_GPIO27
ICH_GPIO28
SATA_CLKREQ#
ICH_GPIO38
ICH_GPIO39
ICH_GPIO48
ICH_GPIO49
ICH_GPIO57

R75
10K_0402_5%
MAIN@

PROJECT_ID1
2
10K_0402_5%

1
R464
1
R105
1
R169

PM_CLKRUN#

1 ICH_VGATE
0_0402_5%
ICH_TP11

S4_STATE#/GPIO26

2
B

26

JALA0 (Project ID 0/1 01)


1
R168

STP_PCI#
STP_CPU#

2
R383

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

CR_CPPE#
EC_SMI#
EC_SCI#

DVT
+3V

A14
E19

OCP#
CRT_DET
CR_CPPE#
EC_SMI#

OCP#

26
31
31

SMBALERT#/GPIO11

H_STP_PCI#
H_STP_CPU#

PAD

T8

ICH_SMBCLK
2
2.2K_0402_5%
ICH_SMBDATA
2
2.2K_0402_5%
EC_SWI#
2
10K_0402_5%
ICH_SMLINK0
2
10K_0402_5%
ICH_SMLINK1
2
10K_0402_5%
LINKALERT#
2
10K_0402_5%
XDP_DBRESET#
2
10K_0402_5%
2 ICH_PCIE_WAKE#
1K_0402_5%
PM_BATLOW#
2
8.2K_0402_5%
EC_LID_OUT#
2
10K_0402_5%
ICH_GPIO10
2
10K_0402_5%
ICH_GPIO13
2
10K_0402_5%
S4_STATE#
2
10K_0402_5%

VGATE

VGATE

A17

E20
M5
AJ23

SUS_CLK

8,16,46

PMSYNC#/GPIO0

EC_LID_OUT#

ICH_PCIE_WAKE#
SERIRQ
EC_THERM#

27,29 ICH_PCIE_WAKE#
25,31
SERIRQ
31 EC_THERM#

P1
C16
E16
G17

25,31 PM_CLKRUN#

M6

SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#

R99
10_0402_5%
@

SUS_STAT#/LPCPD#
SYS_RESET#

R448
10_0402_5%
@

CLK_ICH_14M 16
CLK_ICH_48M 16

16 H_STP_PCI#
16 H_STP_CPU#

R4
G19

PM_SYNC#

PM_SYNC#

31 EC_LID_OUT#

OCP#
2
10K_0402_5%
CR_CPPE#
2
10K_0402_5%
ICH_GPIO17
2
10K_0402_5%
ICH_GPIO18
2
10K_0402_5%
ICH_GPIO20
2
10K_0402_5%
SATA_CLKREQ#
2
10K_0402_5%
ICH_GPIO38
2
10K_0402_5%
ICH_GPIO39
2
10K_0402_5%
ICH_GPIO48
2
10K_0402_5%

+3V
1
R406
1
R62
1
R417
1
R404
1
R403
1
R405
1
R95
1
R416
1
R68
1
R402
1
R401
1
R413
1
R76

SUS_STAT#
XDP_DBRESET#

CLK_ICH_14M
CLK_ICH_48M

CLK_ICH_14M

PAD

T23
4 XDP_DBRESET#

H1
AF3

CLK14
CLK48

clocks

RI#

2 10K_0402_5%

F19

CLK_ICH_48M

EC_SWI#

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

PROJECT_ID1
PROJECT_ID0
R449 1

Direct Media Interface

EC_SWI#

SMB

AH23
AF19
AE21
AD20

PCI - Express

31

DVT

SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1

16,27,29 ICH_SMBCLK
16,27,29 ICH_SMBDATA

Power MGT

G16
A13
E17
C17
B18

SYS / GPIO

1
R453
1
R452
1
R444
1
R101
1
R164
1
R104
1
R465
1
R450
1
R451

Place closely pin AC1

U10C
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

MISC
GPIO
Controller Link

Place closely pin B2

SERIRQ
2
10K_0402_5%
PM_CLKRUN#
2
8.2K_0402_5%
EC_THERM#
2
8.2K_0402_5%
H_STP_PCI#
2
10K_0402_5%
H_STP_CPU#
2
10K_0402_5%
SB SPKR
2
1K_0402_5%
CR_WAKE#
2
10K_0402_5%

1
R432
1
R427
1
R167
1
R69
1
R387
1
R424
1
R166

Sheet

Friday, May 16, 2008


1

23

of

50

1U_0402_6.3V4Z
1
+5VALW

R148

+3V

+5V

100_0402_5%
10_0402_5%
@

D11
CH751H-40PT_SOD323-2

R155

+ICH_V5REF_SUS
C204
1U_0402_6.3V4Z
+1.5VS_PCIE_ICH

L39 2
1
KC FBM-L11-201209-221LMAT_0805

+1.5VS

C469

(220UF*1, 22UF*2, 2 2UF*1)

C460

C473

C464

220U_D2_4VM_R15
10U_0805 10V4Z
2
2
2
10U_0805_10V4Z
2.2U_0805_10V6K

+1.5VS_SATAPLL_ICH
C

L16 1
2
MBK1608301YZF_0603

+1.5VS

(10UF*1, 1UF*1)

1
1
C223
C228
10U_0805 10V4Z
2 1U_0402_6.3V4Z
2

0.1U_0402_ 6V4Z
2

C491

C485

1U_0402_6.3V4Z
2

+5V
1U_0402_6.3V4Z

0.1U_0402_16V4Z
2

+3VS

VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]

AC9

VCC1_5_A[17]

AC18
AC19

VCC1_5_A[18]
VCC1_5_A[19]

AC21

VCC1_5_A[20]

G10
G9

VCC1_5_A[21]
VCC1_5_A[22]

AC12
AC13
AC14

VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]

close to AJ5
2
0.1U_0402_16V4Z
2
1 +VCCLAN1_05_INT_ICH
C438
0.1U_0402_16V4Z
+VCCLAN_ICH

R65

0_0603_5%
C129

2
0.1U_0402_16V4Z

AJ5

VCCUSBPLL

AA7
AB6
AB7
AC6
AC7

VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]

A10
A11

VCCLAN1_05[1]
VCCLAN1_05[2]

A12
B12

VCCLAN3_3[1]
VCCLAN3_3[2]

+1.5VS

+VCC_GLANPLL_ICH
R63

0_0603_5%
1

C121

C120

(10UF*1, 2.2UF*1)10U_0805210V4Z
2.2U_0805_10V6K
+1.5VS

+VCCGLAN_ICH
R89

(4.7UF*1)

0_0603_5%
C151
4.7U_0805_10V4Z

+3VS

A27

VCCGLANPLL

D28
D29
E26
E27

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]

A26

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C467

R29

VCC_DMI[1]
VCC_DMI[2]

W23
Y23

V_CPU_IO[1]
V_CPU_IO[2]

AB23
AC23

VCC3_3[01]
VCC3_3[02]
VCC3_3[07]

AG29
AJ6
AC10

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

AD19
AF20
AG24
AC20

VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

B9
F9
G3
G6
J2
J7
K7

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

+1.5VS_DMIPLL_ICH
L15 1
2
MBK1608301YZF_0603

VCCGLAN3_3
ICH9-M ES_FCBGA676
ICH9MB@

+1.5VS

(10UF*1, 0.01UF*1)

C180
C178
10U_0805_10V4Z
2
0.01U_0402_16V7K

+1.05VS
C463

VCCDMIPLL

U10E

+1.05VS
C468

(4.7UF*1)

4.7U_0805_10V4Z
2

+1.05VS
C454

C476

C479

(4.7UF*1, 0.1UF*2)

4.7U_0805_10V4Z

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

close to AG29

close to AD19

close to G6
+3VS

C492

C495

C496

close to AJ6

VCCHDA

AJ4

VCCSUSHDA

AJ3

C458

C451

close to B9

1
AC8 TP_VCCSUS1_05_ICH_1
F17 TP_VCCSUS1_05_ICH_2

@
@

VCCSUS1_5[1]

AD8 TP_VCCSUS1_5_ICH_1

VCCSUS1_5[2]

F18

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]

A18
D16
D17
E22

VCCSUS3_3[05]

AF1

PAD
PAD
PAD

T24
T21
T25

A24
B24

PM@ 0_0603_5%

R172

GM@ 0_0603_5%

C448
0.1U_0402_16V4Z

+1.5VS

0.1U_0402_16V4Z

+VCCSUS_HDA_ICH

+3VS

C222

R171

PM@ 0_0603_5%

R170

GM@ 0_0603_5%

+3V
+1.5V

C221
0.1U_0402_16V4Z

C472

C477

Check Power Source

0.022U_0402_16V7K

VCCCL3_3[1]
VCCCL3_3[2]

close to K7
R173

+3V

0.1U_0402_16V4Z
2
2
0.022U_0402_16V7K

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

G22
G23

+VCCSUS1_5_ICH_INT_2

VCCCL1_05
VCCCL1_5

C449

+VCC_HDA_ICH

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C439

GLAN POWER

C490

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]

USB CORE

C497

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

VCCSATAPLL

ATX

close to AC7

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

+1.5VS

V5REF_SUS

ARX

C215

AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15

+1.5VS
Q10
AO3413_SOT23-3

SBPWR_EN#

37

AJ19

+5VALW

V5REF

VCCA3GP

MP

AE1
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25

VCCRTC

CORE

C128

+ICH_V5REF_SUS

JALA0

A6

VCCP_CORE

+ICH_V5REF

+ICH_V5REF

PCI

MP

A23

+RTCVCC
1
1
C433
D8
C437
0.1U_0402_16V4Z
CH751H-40PT_SOD323-2
2
0.1U_0402_16V4Z 2

100_0402_5%

U10F

VCCPSUS

R73

+3VS

VCCPUSB

+5VS

close to A18

(0.1UF*1, 0.022UF*2)

close to T1

DVT

ICH9-M: SA00002AN10
(S IC NH82801 BM QP23 A2 FCBGA 676P ICH9M)

PVT

ICH9-M: SA00002JH00
(S IC AF82801 BM QT09 A3 PBG 676P ICH9M)

+VCCCL1_05_INT_ICH
+VCCCL1_5_INT_ICH

+3VS

Security Classification

1
1
C447
C442
@
@
1U_0402_6.3V4Z
2
2
0.1U_0402_16V4Z

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]

(0.1UF*1)
2
0.1U_0402_16V4Z

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

ICH9-M ES_FCBGA676
ICH9MB@

(1UF*1, 0.1UF*1)
Pre-MP ICH9-M: SA00002JH70
(S IC AF82801 BM SLB8Q A3 676P ICH9M ABO!)
Compal Secret Data
2007/09/20

Issued Date

C446

AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29

2008/09/20

Deciphered Date

Compal Electronics, Inc.


Title

SCHEMATIC MB A4221

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
C

401552

Date

Friday May 16 2008

Sheet
1

24

of

50

21 PCI_AD[0..31]

PCI_AD[0..31]

21 PCI_CBE#[0..3]

PCI_CBE#[0..3]

3VS
0.1U_0402_16V4Z
5VS
IDSEL SELECT POWER-ON-STRAPPING
(SEE NOTE & TABLE FOR OPTIONS)

10U_0805_10V4Z
C526

C514

C515

0.1U_0402_16V4Z

C541

64
77
97
115

0.1U_0402_16V4Z

C523

1
20
33

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
IDSEL
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

0.1U_0402_16V4Z

THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME.


IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE
PCI AD LINES OR EXTERNAL IDSEL SIGNAL.
22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE
REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO
SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS.
THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS.
CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS
FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY
CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST
BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC.

VCC5#
(124)

VPP_PGM
(123)

IDSEL SELECT

DOWN

DOWN

AD18

DOWN

UP

AD20

DVT
R651
PCI_AD16

UP

DOWN

AD25

100_0402_5%
UP

UP

PIN F4

4
5
6
7
8
9
10
13
14
15
16
17
18
19
21
22
28
29
30
31
34
35
36
37
38
39
40
41
42
43
44
46
127
11
12
49
50

16 CLK_PCI_PCM
21 PCI_DEVSEL#
21 PCI_FRAME#
21
PCI_IRDY#
21
PCI_TRDY#
21
PCI_STOP#
21
PCI_PAR
34

PCM_SPK#
21
21

PCI_REQ#0
PCI_GNT#0

21

PCI_RST#

23,31 PM_CLKRUN#

2 33K_0402_5%

R509

2 33K_0402_5%

C524

4.7U_0805_10V4Z

PCM_SPK#

1
0_0402_5%
@

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VPP_VCC/VPPD1/IDSEL
C/BE3#
C/BE2#
C/BE1#
C/BE0#

51

PERR#/SPKR_OUT

55
54
53
52

REQ#
GNT#
RST#
PME#/RI_OUT#
MF6
MF4
MF3
MF0

C527

VCC5#/VCCD0#/SDATA
VCC3#/VCCD1#/SCLK
VPP_PGM/VPPD0/SLATCH

124
125
123

D10/CAD31
D9/CAD30
D1/CAD29
D8/CAD28
D0/CAD27
A0/CAD26
A1/CAD25
A2/CAD24
A3/CAD23
A4/CAD22
A5/CAD21
A6/CAD20
A25/CAD19
A7/CAD18
A24/CAD17
A17/CAD16
IOW#/CAD15
A9/CAD14
IORD#/CAD13
A11/CAD12
OE#/CAD11
CE2#/CAD10
A10/CAD9
D15/CAD8
D7/CAD7
D13/CAD6
D6/CAD5
D12/CAD4
D5/CAD3
D11/CAD2
D4/CAD1
D3/CAD0

103
102
101
100
99
110
109
108
106
105
104
118
95
94
93
75
73
74
71
72
70
69
68
85
84
82
83
80
81
78
79
76

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

A16/CCLK
A23/CFRAME#
A15/CIRDY#
A22/CTRDY#
A21/CDEVSEL#
A20/CSTOP#
A13/CPAR
A14/CPERR#
WAIT#/CSERR#
INPACK#/CREQ#
WE#/CGNT#
RDY/IREQ#/CINT#
A19/CBLOCK#
WP/CCLKRUN#
RESET/CRST#
D2/RFU
D14/RFU
A18/RFU
VS1/CVS1
VS2/CVS2
CD1#/CCD1#
CD2#/CCD2#
BVD2/LED/CAUDIO
BVD1/STSCHG#/RI#/CSTSCHG

107
114
117
116
113
61
58
60
91
89
62
88
59
87
119
98
86
63
57
121
56
122
92
90

R508 33_0402_5%
S1_A16
1
2
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A13
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_RDY#
S1_A19
S1_WP
S1_RST
S1_D2
S1_D14
S1_A18
S1_VS1
S1_VS2
S1_CD1#
S1_CD2#
S1_BVD2
S1_BVD1

REG#CCBE3#
A12/CCBE2#
A8/CCBE1#
CE1/CCBE0#

111
112
66
67

S1_REG#
S1_A12
S1_A8
S1_CE1#

VCC/VPP +3.3V
VCC/VPP +3.3V
VCC5#
+5V
VCC3#
GND

4.7U_0805_10V4Z

1
2
3
4

PCMCIA Socket

OZ2210GN-B1_SO8
CONN@
JPCM1

PVT
SA000026P10 (S IC OZ2210GN-B1 SO 8P)

S1_VCC

0.1U_0402_16V4Z
C543

C542

4.7U_0805_10V4Z
1

S1_D3
S1_CD1#
S1_D4
S1_D11
S1_D5
S1_D12
S1_D6
S1_D13
S1_D7
S1_D14
S1_CE1#
S1_D15
S1_A10
S1_CE2#
S1_OE#
S1_VS1
S1_A11
S1_IORD#
S1_A9
S1_IOWR#
S1_A8
S1_A17
S1_A13
S1_A18
S1_A14
S1_A19
S1_WE#
S1_A20
S1_RDY#
S1_A21

S1_VCC

S1_A16
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24
S1_A7
S1_A25
S1_A6
S1_VS2
S1_A5
S1_RST
S1_A4
S1_WAIT#
S1_A3
S1_INPACK#
S1_A2
S1_REG#
S1_A1
S1_BVD2
S1_A0
S1_BVD1
S1_D0
S1_D8
S1_D1
S1_D9
S1_D2
S1_D10
S1_WP
S1_CD2#

22K TO 47K PULL-UPS MUST BE PLACED


ON INTA#, PME#, SERIRQ# & CLKRUN#.

1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68

OZ601TN_TQFP128~D

32
45
65
96
128

DVT(Check)

PCI_VCC
PCI_VCC
PCI_VCC

PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR

126
120
PM_CLKRUN# 2
R489

CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC

26
27
23
24
25
47
48

2
3

23,31
SERIRQ
21
PCI_PIRQE#

5
6
7
8

U34

NOTE: IDSEL SELECTION!


2

0.1U_0402_16V4Z

U35

0.1U_0402_16V4Z

10U_0805_10V4Z

C525

S1_VCC

3VS
C540

R510

GND
GND
GND
GND
GND

0.1U_0402_16V4Z

3VS
C537

C528

GND
GND
DATA3
CD1#
DATA4
DATA11
DATA5
DATA12
DATA6
DATA13
DATA7
DATA14
CE1#
DATA15
ADD10
CE2#
OE#
VS1#
ADD11
IORD#
ADD9
IOWR#
ADD8
ADD17
ADD13
ADD18
ADD14
ADD19
WE#
ADD20
READY
ADD21
VCC
VCC
VPP
VPP
ADD16
ADD22
ADD15
ADD23
ADD12
ADD24
ADD7
ADD25
ADD6
VS2#
ADD5
RESET
ADD4
WAIT#
ADD3
INPACK#
ADD2
REG#
ADD1
BVD2
ADD0
BVD1
DATA0
DATA8
DATA1
DATA9 GND
DATA2 GND
DATA10 GND
WP
GND
CD2#
GND
GND

69
70
71
72

SANTA_130651-E_68P_LT-S
4

Footprint as SANTA_130651-E_68P_LT-S
DVT(JALA0)
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

SCHEMATIC MB A4221

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
C

401552

Date:

Sheet

Friday, May 16, 2008


D

25

of

50

MDIO PULL HIGH/LOW ?


3VS

40mil

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1.8VS

1
C534

1
C521

1
C511

1
C532

0.1U_0402_16V4Z

1.8VS_APVDD

L45
MBK1608121YZF_0603
1
2
@

40mil
1

C529

2
2
10U_0805_10V4Z

0.1U_0402_16V4Z

C512

1
C519

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

3V_MCVCC

1
C522

1
C531

XDWP_SDWP
1
R494

XD_RB

1000P_0402_50V7K

R485

10K_0402_5%

10K_0402_5%
3VS

XD_CLE

XDCD0#_SDCD#
1
R487

XDCD1#_MSCD#
1
R488

XD_RE

U32

3
4

APCLKN
APCLKP

9
8

APRXN
APRXP

11
12

APTXN
APTXP

16 CLK_PCIE_READER#
16 CLK_PCIE_READER
PCIE_ITX_C_PRX_N5
PCIE_ITX_C_PRX_P5

23 PCIE_ITX_C_PRX_N5
23 PCIE_ITX_C_PRX_P5
C517 1
C516 1

23 PCIE_PTX_C_IRX_N5
23 PCIE_PTX_C_IRX_P5

0.1U_0402_16V7K
0.1U_0402_16V7K

2
2

R491 1

PCIE_PTX_IRX_N5
PCIE_PTX_IRX_P5

2 8.2K_0402_5%

APREXT

APREXT 15 mil
38
39

3VS

R496

1
2

23

23

R655
2 0_0402_5% TP_SEEDAT
@ TP_SEECLK
T26 PAD

CR_CPPE#

D33
CH751H-40PT_SOD323-2
1
2
@
@
1
2
R656
0_0402_5%

CR_WAKE#

DVT

PCIES_EN
PCIES

JMB385

32

XRSTN
XTEST

13
14

SEEDAT
SEECLK

XDCD1#_MSCD#
XDCD0#_SDCD#

15
16

CR1_CD1N
CR1_CD0N

MC_PWREN#

17

CR1_PCTLN

MC_PWREN# 40 mil
21

5IN1_LED#

5
10
30

DV33
DV33
DV33
DV18
DV18

19
20
44
18
37

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

NC
NC
NC

34
35
36

APREXT

8,21,23,27,31 PLT_RST#

APVDD
APV18
TAV33

APGND
GND
GND
GND
GND

CR1_LEDN

1.8VS_APVDD
3VS

10K_0402_5%
4.7K_0402_5%
4.7K_0402_5%

1.8VS_APVDD
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
XDCE_SDCLK_MSCLK_R
XDWP_SDWP
XD_CLE
XD_D4
XD_D5
XD_D6
XD_D7
XD_RE
XD_RB
XD_ALE

R497
2 XDCE_SDCLK_MSCLK
33_0402_5%

R490
XD_ALE
R486

JALA0

200K_0402_5%
200K_0402_5%
C

D28

24
31
32
33

XDCD0#_SDCD#

XDCD1#_MSCD#

XD_CD#

DAN202UT106_SC70-3

C510
270P_0402_50V7K

JMB385-LGEZ0A_LQFP48_7X7

DVT

SA00001W910 (S IC JMB385-LGEZ0B LQFP 48P)

4 IN 1 Socket Push Type(New)

JREAD1

3V_MCVCC
U33

1
2
3
4

OUT
OUT
OUT
FLG

8
7
6
5

C536 1

MC_PWREN#

GND
IN
IN
EN#

40mil

1 2

C535 1

SDCMD_MSBS_XDWE# 34
XDWP_SDWP
33
XD_ALE
35
XD_CD#
40
XD_RB
39
XD_RE
38
XDCE_SDCLK_MSCLK 37
XD_CLE
36

2
G
3

MC_PWREN#

C530 1

4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z

TPS2061DRG4_SO8
R493
@
300_0603_5%
@

32
10
9
8
7
6
5
4

11
31

Q42
2N7002_SOT23
@

41
42
A

MC_PWREN#

1
1

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

7 IN 1 CONN

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
7IN1 GND
7IN1 GND

21
28

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

XDCE_SDCLK_MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
(MMC
XD_D4
(MMC
XD_D5
(MMC
XD_D6
(MMC
XD_D7
SDCMD_MSBS_XDWE#
XDCD0#_SDCD#

SD-WP-SW

XDWP_SDWP

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

XDCE_SDCLK_MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#

3V_MCVCC

XDCE_SDCLK_MSCLK
Data
Data
Data
Data

Bit
Bit
Bit
Bit

4)
5)
6)
7)

3VS

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_D4
XD_D5
XD_D6
XD_D7

SD-VCC
MS-VCC

Memory Card Power Switch

XD-VCC

C533
R498
4.7P_0402_50V8C10_0402_5%

3V_MCVCC

1 @

JALA0

7IN1 GND
7IN1 GND
A

TAITW_R015-B10-LM
CONN@

3V_MCVCC

R492 0_0805_5%
C520

Compal Electronics, Inc.

Compal Secret Data

Security Classification

4.7U_0805_10V4Z

2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

SCHEMATIC MB A4221

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
C

401552

Date:

Friday, May 16, 2008

Sheet
1

26

of

50

R347

2
0_1206_5%

+3V_LAN
+3V_LAN

R339 1

2 1_1206_1%

R338 1

2 1_1206_1%

LAN_PM #
4.7K_0402_5%

1
R45

+3VALW

+3V_LAN

+3V_LAN R
1
C9

C21

0.1U_0402_16V4Z
2
2
4.7U 0805_10V4Z

+1.2V_LAN

2
4

LAN_REGCTL12 1
Q2
MMJT9435T1G_SOT223

+3V_LAN

60mil
D

C31

C68

C62

C6

C7

C389

C387

C386

C388

C78

C95

C414

C413

C61

C96
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
2
2
2
2
2
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+3V_LAN

29

16 LAN_CLKREQ#

11

R333 1

31 LAN_LOWPWR

R336 1

2 0_0402_5%

PVT2(JALA0)

2 10K_0402_5%

R328 1

2 1K_0402_5%

53

VMAIN_PRSNT

+3V_LAN

R327 1

2 1K_0402_5%

54

VAUX_PRSNT

23 PCIE_ITX_C_PRX_N3
23 PCIE_ITX_C_PRX_P3
23 PCIE_PTX_C_IRX_N3

C411 1

23 PCIE_PTX_C_IRX_P3

C412 1

59

ENERGY_DET

+LAN_GPHYPLLVDD

35

GPHY_PLLVDD

PCIE_ITX_C_PRX_N3

32

PCIE_RXD_N

PCIE_ITX_C_PRX_P3

31

PCIE_RXD_P

PCIE_PTX_IRX_N3

25

PCIE_TXD_N

PCIE_PTX_IRX_P3

26

PCIE_TXD_P

0.1U_0402_16V7K
0.1U_0402_16V7K

R341 1

8,21,23,26,31 PLT_RST#

R354 1
R355 1

23,29 ICH_PCIE_WAKE#
31
EC_PME#

2
@

0_0402_5% LAN_RESET#

2 0_0402_5%
2 0_0402_5%

LAN_PME#

+3V_LAN
2

LAN_SMBCLK
R20
LAN_SMBDATA
4.7K_0402_5%
1
2
+3V_LAN PVT(JALA0)

R13
1

16,23,29 ICH_SMBDATA
B

1
R16

4,31 EC_SMB_DA2

0_0402_5%
2 6

2N7002DW-T/R7_SOT363-6
1
2
R673 0_0402_5%
@

PVT

+3V_ AN

R14
4.7K_0402_5%
1
2
+3V_LAN

JALA0
R21
1

1 ,23,29 ICH_SMBCLK

0_0402_5%
2 3

4
Q3B

1
R17

4,31 EC_SMB_CK2

2
0_0402_5%

12

LAN_XTALI
XTALO

2N7002DW-T/R7_SOT363-6
1
2
R674 0_0402_5%
@

PVT

SMB_CLK

57

SMB_DATA

65
63
64
62

REGCTL12
REGCTL25/12_IO
RDAC

14
18
37

XTALVDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

23
6
15
19
56
61

VDDP
VDDP/DC

17
68

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

5
13
20
34
55
60

GPIO_0(SERIAL_DO)

GPIO_1(SERIAL_DI)

GPIO_2

UART_MODE

16
1
2
R358
39K_0402_5%
+LAN PCIEVDD
24

DVT
PVT

R364
4.7K_0402_5%

R369
4.7K_0402_5%

R367
4.7K_0402_5%

XTALI

+3V_LAN

LAN_MIDI1- 28
LAN_MIDI2- 28
LAN_MIDI3- 28
LAN_MIDI3+ 28

2
R321
0_0402_5%
2
R322
0_0402_5%
SPROM_CLK
SPROM_DIN
SPROM_DOUT
SPROM_CS

U25
SPROM_DOU
SPROM_CLK

1
2
3
4

LAN_LINK# 28

SO
GND
VCC
WP#

SPROM_DIN

8
7
6
5

+3V_LAN
1

DVT

LAN_ACTIVITY# 28

R323 1

C98
0.1U_0402_16V4Z

Use Flash if support ASF2.0

2 4.7K_0402_5%

PVT

BIASVDD
PCIE_PLLVDD
PCIE_VDD/PLL
PCIE_VDD
AVDD/DC
AVDD/AVDDL
AVDD/DC

XTALO
AVDDL
AVDDL/T1_P
REG_GND/S_IDDQ AVDDL/T2_P
AVDDL
PCIE_GND/VDD
E- PAD

LAN_REGCTL12
LAN_RDAC 1
R356

PVT

2
1.18K_0402_1%

20mil
L11
1
2
BLM18AG601SN1D_0603

+LAN_XTALVDD
+3V_LAN
1

PVT

C94

+Lan_VDDIO_1.2

2
0.1U_0402_16V4Z
+Lan_VDDIO_1.2

C606

0.1U_0402_16V4Z
2

+1.2V_LAN

L4
1
2
BLM18AG601SN1D_0603

+1.2V_LAN

0.1U_0402_ 6V4Z
2
2
4.7U_0805_10V4Z

PVT
C607

0.1U_0402_16V4Z
2

20mil
+LAN_PCIEVDD
1
C80
C84
0.1U_0402_ 6V4Z
2

L3
1
2
BLM18AG601SN1D_0603

+1.2V_LAN

2
4.7U 0805_10V4Z

L8

36 +LAN_BIASVDD
30 +LAN_PCIEPLLVDD
27
33 +LAN_PCIEVDD
38
45 +LAN_AVDDL
52
39
44
46
51
69

+LAN_PCIEPLLVDD
1
C81
C82

+3V_LAN

20mil

1
2
+3V_LAN
BLM18AG601SN1D_0603
C91
C611

C613

0.1U_0402_16V4Z

2
0.1U 0402_16V4Z

C27

0.1U_0402_ 6V4Z
2

2
0.1U_0402_16V4Z

20mil

LAN_MIDI1+ 28
LAN_MIDI2+ 28

+LAN_AVDDL
1

C77

BCM5764MKML_QFN68

C70

0.1U_0402_ 6V4Z
2

SA000025P00
(S IC BCM5764MA0KMLG QFN 68P E-LAN CTRL)

20mil
+LAN_GPHYPLLVDD
1
C97
C99

SA000025P20
(S IC BCM5764MKMLG P20 QFN 68P E-L)

L7
1
2
+3V_LAN
BLM18AG601SN1D_0603

+LAN_AVDD
C83

PVT

+LAN_AVDDL
LAN_MIDI1+
LAN_MIDI2+
+LAN_AVDDL

0.1U_0402_16V4Z

0.1U_0402_ 6V4Z
2

L5
1
2
BLM18AG601SN1D_0603

+1.2V_LAN

2
4.7U_0805_10V4Z

L9
1
2
BLM18AG601SN1D_0603

+1.2V_LAN

2
4.7U 0805_10V4Z
A

Y2
1

SI
SCK
RESET#
CS#

AT45DB011B-SU_SO8~N

R363
200_0402_1%
A

1Mb Flash

+Lan_VDDIO_1.2

22

LAN_XTALI

SCLK(EECLK)
SI
SO(EEDATA)
CS

WAKE

PVT2

XTALO

2
1
67
66

PERST

58

21

LAN_SMBCLK

LAN_MIDI0- 28
LAN_MIDI0+ 28

SPROM_CS
LINKLED
SPD100LED
SPD1000LED
TRAFFICLED

LAN_SMBDATA

Q3A
2
0_0402_5%

10

LAN_MIDI0LAN_MIDI0+
+LAN_AVDD
LAN_MIDI1+LAN_AVDD
LAN_MIDI2LAN_MIDI3LAN_MIDI3+

LOW PWR

+3VS

31 ENERGY_DET

41
40
42
43
48
47
49
50

16 CLK_PCIE_LAN

TRD0_N
TRD0_P
TRD1_N/AVDD
PCIE_REFCLK_P TRD1_P/T1_N
TRD2_N/AVDD
CLKREQ
TRD2_P/T2_N
TRD3_N
TRD3_P
PCIE_REFCLK_N

28

16 CLK_PCIE_LAN#

U23

2 LAN_XTALO

25MHZ_20P
C415
27P_0402_50V8J

1
C416
27P_0402 50V8J
2

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

27

of

50

3V_LAN

L_LAN_LINK#

27

LAN_MIDI0-

LAN_MIDI0-

27

LAN_MIDI1

LAN_MIDI1

27

LAN_MIDI1-

LAN_MIDI1-

27

LAN_MIDI2

LAN_MIDI2

27

LAN_MIDI2-

27
27

0B1
1B1

48
47

D_LAN_MIDI0
D_LAN_MIDI0-

2B1
3B1

43
42

D_LAN_MIDI1
D_LAN_MIDI1-

4B1
5B1

37
36

D_LAN_MIDI2
D_LAN_MIDI2-

6B1
7B1

32
31

D_LAN_MIDI3
D_LAN_MIDI3-

22
23
52

D_LAN_ACTIVITY#
D_LAN_LINK#

46
45

L_LAN_MIDI0
L_LAN_MIDI0-

2B2
3B2

41
40

L_LAN_MIDI1
L_LAN_MIDI1L_LAN_MIDI2
L_LAN_MIDI2-

A0
A1

A2

A3

11

A4

LAN_MIDI2-

12

A5

0LED1
1LED1
2LED1

LAN_MIDI3

LAN_MIDI3

14

A6

0B2
1B2

LAN_MIDI3-

LAN_MIDI3-

19,31,34,38 EC_DOCKIN#

27 LAN_ACTIVITY#
27 LAN_LINK#

15

D_LAN_MIDI1
38
D_LAN_MIDI1- 38

SEL

4B2
5B2

LAN_ACTIVITY#
LAN_LINK#

19
20
54

LED0
LED1
LED2

6B2
7B2

30
29

L_LAN_MIDI3
L_LAN_MIDI3-

0LED2
1LED2
2LED2

25
26
51

L_LAN_ACTIVITY#
L_LAN_LINK#

LAN_MIDI0LAN_MIDI1
MAIN@
LAN_MIDI1LAN_MIDI2
LAN_MIDI2LAN_MIDI3

DVT
LAN_MIDI3T1
L_LAN_MIDI0
L_LAN_MIDI0B

L_LAN_MIDI1
L_LAN_MIDI1L_LAN_MIDI2
L_LAN_MIDI2L_LAN_MIDI3
L_LAN_MIDI3-

TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-

MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-

24
23
22
21
20
19
18
17
16
15
14
13

RJ45_MIDI0
RJ45_MIDI0-

2
1
R314
1K_0402_5%
L_LAN_ACTIVITY#

11

Amber LED-

RJ45_MIDI3-

RJ45_MIDI3

PR4+

RJ45_MIDI1-

PR2-

RJ45_MIDI2-

PR3-

RJ45_MIDI2

PR3+

RJ45_MIDI1

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0

PR1+

2
R317

10
1
1K_0402_5%

SHLD2

16

SHLD1

15

SHLD2

14

SHLD1

13

PR4-

Guide Pin

Green LEDGreen LED+


FOX_JM36113-L2R8-7F
CONN@
2

C384
220P_0402_50V7K

RJ45_GND

LANGND
1

2
1

C5
1000P_1206_2KV7K

C3

40mil

C4
4.7U_0805_10V4Z

0.1U_0402_16V4Z

RJ45_MIDI2
RJ45_MIDI2-

ADD_DVT(JALA0)
B

L_LAN_ACTIVITY#
1
2
C375
68P_0402_50V8J
L_LAN_LINK#

RJ45_MIDI3
RJ45_MIDI3-

C374
220P_0402_50V7K
JRJ45
12 Amber LED+

L_LAN_LINK#
3V_LAN

R594 0_0402_5%
LAN_ACTIVITY# 1
L_LAN_ACTIVITY#
2
VALUE@
R595 0_0402_5%
LAN_LINK#
L_LAN_LINK#
1
2
VALUE@

RJ45_MIDI1
RJ45_MIDI1-

R586 0_0402_5%
L_LAN_MIDI0
1
2
VALUE@
R587 0_0402_5%
L_LAN_MIDI01
2
VALUE@
R588 0_0402_5%
L_LAN_MIDI1
1
2
VALUE@
R589 0_0402_5%
L_LAN_MIDI11
2
VALUE@
R590 0_0402_5%
L_LAN_MIDI2
1
2
VALUE@
R591 0_0402_5%
L_LAN_MIDI21
2
VALUE@
R592 0_0402_5%
L_LAN_MIDI3
1
2
VALUE@
R593 0_0402_5%
L_LAN_MIDI31
2
VALUE@

LAN_MIDI0

1
6
9
13
16
21
24
28
33
39
44
49
53
55

1
2
3
4
5
6
7
8
9
10
11
12

1
38

PAD_GND

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13

57

D_LAN_ACTIVITY#
D_LAN_LINK# 38

3V_LAN

35
34

NC

D_LAN_MIDI3
38
D_LAN_MIDI3- 38

17

L : A-->B1
H: A-->B2

@
PSOT24C-LF-T7_SOT23-3
D19

D_LAN_MIDI2
38
D_LAN_MIDI2- 38

EC_DOCKIN#

NOTE:

A7

@
PSOT24C-LF-T7_SOT23-3
D20

D_LAN_MIDI0
38
D_LAN_MIDI0- 38

LAN_MIDI0

LAN_MIDI0

56
50
38
27
18
10
4
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
D

27

L_LAN_ACTIVITY#

U1
PI3L500-AZFEX_TQFN56_11X5

JALA0

1
2
C383
68P_0402_50V8J

350uH_GSL5009-1 LF

C378

C379

C382

2
0.1U_0402_16V4Z

R7
75_0402_1%

R8
75_0402_1%

C377

R5
75_0402_1%

0.1U_0402_16V4Z

R4
75_0402_1%
0.1U_0402_16V4Z

For EMI

SP050003T10
(S X'FORM GSL5009-1 LF ETHERNET)

RJ45_GND

0.1U_0402_16V4Z

40mil

Place close to TCT pin

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/12/25

Issued Date

Deciphered Date

2007/12/25

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

28

of

50

For Wireless LAN

R538 1

+3VS_WLAN

R542 1

2 0_1206_5%

+3VS

2 0_1206_5%

+3V

LOWER SLOT(SAME AS JAL90)


+3VS_WLAN

+1.5VS

C557
4.7U_0805_10V4Z

C352
0.1U_0402_16V4Z

C315
0.1U_0402_16V4Z

C312
4.7U_0805_10V4Z

C344
0.1U_0402_16V4Z

Mini Card Power Rating


C353

Power

PVT(JALA0)

JMINI2

R278 1
@
R665 1
R666 1
16 MINI1_CLKREQ#

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

16 CLK_PCIE_MINI1#
16 CLK_PCIE_MINI1

1
WLAN_BT_DATA R 3
WLAN_BT_CLK_R 5
7
9
11
13
15

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

DVT
23 PCIE_PTX_C_IRX_N2
23 PCIE_PTX_C_IRX_P2
23 PCIE_ITX_C_PRX_N2
23 PCIE_ITX_C_PRX_P2
+3VS_WLAN

DVT

For MINICARD Port80 Debug

31 E51TXD_P80DATA
31 E51RXD_P80CLK

E51TXD_P80DATA
E51RXD_P80CLK

R517 1

2 0_0402_5% CL_RST#1_R

PVT(JALA0)

+3VS_WLAN

Auxiliary Power (mA)

Peak

Normal

+3VS

1000

750

Normal

+3V

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)

+1.5VS

PVT(JALA0)
WL_OFF#_R R667 1
PLT_RST_BUF#
+3V_WLAN
R275 1
R273 1
MINI1_SMBCLK
MINI1_SMBDATA

R271 1
R267 1

2 0_0402_5%
2 0_0603_5%
2 0_0603_5%

@
@
@

WL_OFF# 31
PLT_RST_BUF# 21
+3VS
+3V

2 0_0402_5% ICH_SMBCLK
2 0_0402_5% ICH_SMBDATA

ICH_SMBCLK 16,23,27
ICH_SMBDATA 16,23,27

USB20_N8 23
USB20_P8 23

(LED_WWAN#)
(LED_WLAN#)

MINI1_LED# 32

(9~16mA)
2

G1
G2
G3
G3

Primary Power (mA)

0.1U_0402_16V4Z

23,27 ICH_PCIE_WAKE#
30 WLAN_BT_DATA
30 WLAN_BT_CLK

53
54
55
56

FOX_AS0B226-S99N-7F
CONN@

For Robson2
UPPER SLOT(SAME AS JAL90)

+3VS

+1.5VS

C345
MAIN@
4.7U_0805_10V4Z

C357
MAIN@
0.1U_0402_16V4Z

C348
MAIN@
4.7U_0805_10V4Z

C349
MAIN@
0.1U_0402_16V4Z

C313
MAIN@
0.1U_0402_16V4Z

To USB/B Connector

PVT(JALA0)
3

JMINI1

16 MINI2_CLKREQ#
16 CLK_PCIE_MINI2#
16 CLK_PCIE_MINI2

DVT
23 PCIE_PTX_C_IRX_N4
23 PCIE_PTX_C_IRX_P4
23 PCIE_ITX_C_PRX_N4
23 PCIE_ITX_C_PRX_P4
+3VS

For MINICARD Port80 Debug


E51TXD_P80DATA
E51RXD_P80CLK

MAIN@
R658 1

2 0_0402_5% CL_RST#2_R

1
3
5
7
9
11
13
15

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3VS
+1.5VS

9
10

1
2
3
GND 4
GND 5
6
7
8

1
2
3
4
5
6
7
8

+5VALW

USB20_N4
USB20_P4

JALA0
3

0_0402_5% R205
MAIN@
2
1
0_0402_5% R209
@
2
1

SYSON#

30,37,38

USB_EN# 30,31

USB20_N4 23
USB20_P4 23
USB_OC#4 23

ACES_87212-08G0L
CONN@
PLT_RST_BUF#

MINI2_SMBCLK R272 1
MINI2_SMBDATA R268 1

@
@

2 0_0402_5% ICH_SMBCLK
2 0_0402_5% ICH_SMBDATA

+5VALW

USB20_N7 23
USB20_P7 23

1
C376
MAIN@
4.7U_0805_10V4Z
2

(LED_WWAN#)
(LED_WLAN#)

53
54
55
56

G1
G2
G3
G3

DVT

(WAKE#)

80mil

JP11

FOX_AS0B226-S99N-7F
CONN@

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


E

29

of

50

+5VS

+3VS
0.1U_0402_16V4Z

C566

+5VS
0.1U_0402_16V4Z

C564

C568

1000P_0402_50V7K

C559

10U_0805_10V4Z

C553

0.1U_0402_16V4Z
1

C551

1000P_0402_50V7K

C254

10U_0805_10V4Z

C250

C259

1000P_0402_50V7K

10U_0805_10V4Z

SATA HDD Conn.

SATA ODD Conn.

JSATA2
1
2
3
4
5
6
7

SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0

22 SATA_ITX_C_DRX_P0
22 SATA_ITX_C_DRX_N0

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+5VS

22 SATA_DTX_C_IRX_N0

SATA_DTX_C_IRX_N0

1
C538

SATA_DTX_IRX_N0
2
0.01U_0402_16V7K

22 SATA_DTX_C_IRX_P0

SATA_DTX_C_IRX_P0

1
C539

SATA_DTX_IRX_P0
2
0.01U_0402_16V7K

JSATA1

GND
HTX+
HTXGND
HRXHRX+
GND

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

SATA_ITX_C_DRX_P1
SATA_ITX_C_DRX_N1

22 SATA_ITX_C_DRX_P1
22 SATA_ITX_C_DRX_N1

SATA_DTX_IRX_N1
SATA_DTX_IRX_P1

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
GND
VCC12
GND

R190 1

2 1K_0402_1%
+5VS

GND
GND

15
14

SANTA_206401-1_13P
CONN@

24
23
22 SATA_DTX_C_IRX_N1

SATA_DTX_C_IRX_N1

1
C281

SATA_DTX_IRX_N1
2
0.01U_0402_16V7K

22 SATA_DTX_C_IRX_P1

SATA_DTX_C_IRX_P1

1
C279

SATA_DTX_IRX_P1
2
0.01U_0402_16V7K

SUYIN_127043FB022GX78ZR_NR

Finger Print Conn.


+3VALW

+3VS

1
R695
0_0603_5%

R692
0_0603_5%
@

+3VALW

USB CONN. (Stack-up Type)


R693
0_0603_5%

R694
0_0603_5%
@

MP

+USB_VCCA

3
G

23
23

1U_0603_10V4Z

Q29
AO3413_SOT23-3

1
1

+BT_VCC
C317

C318

C508 +

G2
G1
4
3
2
1

4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z

CH3

+3VS

Vp

Q27
2N7002_SOT23

2
G

CH4

JUSB2
23
23

USB20_N0
USB20_P0

USB20_N0
USB20_P0

CH2

Vn

CH1

CH3

23
23

USB20_P5
USB20_N5

29 WLAN_BT_DATA
29 WLAN_BT_CLK

1 GND
2
3
4
5
6
7
8 GND

Vp

GND1
GND2
GND3
GND4

+5VALW
CH2

Vn

+USB_VCCA

USB20_P2

USB20_N2

CH4

CH1

C513
USB20_N0

JALA0

@ CM1293-04SO_SOT23-6
29,37,38 SYSON#

ACES_87213-0800G
CONN@

29,31

USB_EN#

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

2007/09/20

Issued Date

8
7
6
5

1
2
R482
10K_0402_5%

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4

R204 0_0402_5%
1
2
R208 0_0402_5%
@
1
2

C509
0.1U_0402_16V4Z

Compal Electronics, Inc.


2008/09/20

Deciphered Date

Title

Date

USB_OC#2 23
USB_OC#0 23

4.7U_0805_10V4Z
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

R483
0_0402_5%
1
2

R484
100K_0402_5%

Compal Secret Data

Security Classification

1
2
3
4

SUYIN_020173MR004G565ZR
CONN@

U31
1
2
3
4

TPS2061DRG4_SO8

10

USB20_N2
USB20_P2

USB20_N2
USB20_P2

+3V

9
+USB_VCCA

5
6
7
8

JUSB1
23
23

80mil

JP10
1
2
3
4
5
6
7
8

VCC
DD+
GND

USB20_N10

D27
USB20_P0

1
2
3
4

SUYIN_020173MR004G565ZR
CONN@

PJUSB208_SOT23-6

+BT_VCC

C235

150U_D2_6.3VM
2
2
470P_0402_50V7K

D32
USB20_P10
R245
300_0603_5%

C478 +

C195

150U_D2_6.3VM
2
2
470P_0402_50V7K

ADD_DVT(JALA0)
Change SC300000O00 to SC300000B00

W=40mils

0.1U_0402_16V4Z
2

6
5
4
3
2
1

ACES_85201-04051
CONN@

C326

C327

BT_ON#

2
10K_0402_5%

31

1
R252

C194
0.1U_0402_16V4Z
2
1
USB20_N10
USB20_N10
USB20_P10
USB20_P10

0.1U_0402_16V4Z
2
3

W=80mils

+USB_VCCA

JALA0

1
JP8

C325

+USB_VCCA

W=80mils

+USB_VCCA

JALA0

+3VS

+3VALW

Bluetooth Conn.

MP

JALA0

CONN@

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


E

30

of

50

For EC Tools

3VALW
L34

3VS

GM@
DVI_DET

R?

20 EC_DVI_DET

R?

GM@ 2
EC_GPIOC
0_0402_5%
GM@ 2
EC_GPIOB
0_0402_5%

1
1

17,40
17,40
4,27
4,27

JALA0

2 EC_SMB_CK1
2.2K_0402_5%
2 EC_SMB_DA1
2.2K_0402_5%
2 EC_SMB_CK2
2.2K_0402_5%
2 EC_SMB_DA2
2.2K_0402_5%
2 LID_SW#
100K_0402_5%

23 PM_SLP_S3#
23 PM_SLP_S5#
23
EC_SMI#
32
LID_SW#
2
WL_SW#
JALA0 32
BT_SW#
27
EC_PME#
8 MCH_TSATN_EC#
36 FAN_SPEED1
30
BT_ON#
33
ON/OFF
32 PWR_SUSP_LED
32
NUM_LED#

JALA0
5VALW

77
78
79
80

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LID_SW#
WL_SW#
BT_SW#
EC_PME#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

83
84
85
86
87
88

EC_MUTE
LAN_LOWPWR
DOCKIN#

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

3S/4S#
65W/90W#
SBPWR EN
EC_GPIOC

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

EC_SPIDI/FWR#
EC_SPIDO/FRD#
EC_SPICLK
EC_SPICS#/FSEL#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

SKU ID

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

SPI Flash ROM

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

GPI

XCLK1
XCLK0

100K_0402_5%

2
A0
A1
A2
GND

1
2
3
4

11
24
35
94
113

VCC
WP
SCL
SDA

122
123

EC MUTE 35
LAN_LOWPWR 27
DOCKIN#
BT_LED# 32
TP_CLK 32
TP_DATA 32

TP_CLK
TP_DATA

KB926QFB1_LQFP128_14X14

65W/90W#
2
R430

Analog Board ID definition,


Please see page 3.

EC_SI_SPI_SO 32
EC_SO_SPI_SI 32
EC_SPICLK 32
EC_SPICS#/FSEL# 32

3VALW

33K_0402_5%

EC_RSMRST# 23
MP
EC_LID_OUT# 23
EC_ON
33
EC_SWI# 23
EC_PWROK 23,33
BKOFF# 18
WL_OFF 2
JALA0
USB_EN# 29,30
EC_DOCKIN#
9,28,34,38

EC_PWROK
BKOFF#
WL_OFF#
USB_EN#
EC_DOCKIN#

PM_SLP_S4# 23
ENBKL
10,17
EAPD
34
EC_THERM# 23
SUSP#
33,37,45
PBTN_OUT# 23
ENERGY_DET 27

ENBKL
EAPD
SUSP#
PBTN_OUT#
ENERGY_DET

Rc

AD_BID0
R248

Rb

C475

2
0.1U_0402_16V4Z

EC_CRY1
C289

15P_0402_50V8J
2

JALA0

C701
0.1U_0402_16V4Z
@
B

C288

15P_0402_50V8J
2

PVT

JALA0
BATT_TEMP
BATT_OVP

2
R704 @

X2
32.768KHZ_12.5P_MC-306

5VALW
USB_EN#

SKU_ID

EC_CRY2

4.7U_0805_10V4Z

L35
ECAGND 2
1
FBM-L11-160808-800LMT_0603

R701
100K_0402_5%
@

R702
0_0402_5%
@

Rd

PVT

For KB926 C0 reversion

JALA0

SKU ID definition,
Please see page 3.

R433
100K_0402_5%

Ra

EC_ACIN 17
FS CHG 42
BATT_GRN_LED# 32
CAPS_LED# 32
BATT_AMB_LED# 32
PWR_LED 32
SYSON
37,43,44
VR_ON
33,46
ACIN
23,39,42

EC_LID_OUT#
EC_ON

1
100K_0402_5%

3VALW

PVT(JALA0)

FSTCHG
BATT_GRN_LED#
CAPS_LED#
BATT_AMB_LED#
PWR_LED
SYSON
VR_ON
ACIN

C286

20mil

AT24C16AN-10SI-2.7_SO8
@

2
4.7K_0402_5%

3VALW

3S/4S# 42
65W/90W# 42
SBPWR_EN 37,44

JALA0

1
R426

JALA0

PVT2(JALA0)

3S/4S#

VGA_THERM_ALERT# 17

DAC_BRIG 18
EN_DFAN1 36
IREF
42
CALIBRATE# 42

SPI Device Interface

AGND

1
100K_0402_5%

ACIN

C479
2
C480
2
C481
2

100P_0402_50V8J
1
100P_0402_50V8J
1
100P_0402_50V8J
1

DVT(JALA0)

2007/09/20

Issued Date

100K_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R705
@

8
7
6
5

EC_CRY1
EC_CRY2
R703

U43
EC_SMB_CK1
EC_SMB_DA1

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

5VALW
C7020.1U_0402_16V4Z
1
2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PWR_SUSP_LED
NUM_LED#

DAC_BRIG
EN_DFAN1
IREF
CALIBRATE#

PS2 Interface

3VALW

1
R234
1
R235
1
R229
1
R230
1
R457

68
70
71
72

GND
GND
GND
GND
GND

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

R699 10K_0402_5% 3VS


1
2
@
JALA0

THERM_ALERT#
2
1
R698 0_0402_5%
@

ACOFF
42
ECAGND
2
1
R700 0_0402_5% C472 0.01U_0402_16V7K
BATT_TEMP_R2
1
BATT_TEMP 40
BATT_OVP
BATT_OVP 42
ADP_I
42
AD_BID0
PVT(JALA0)
EC GPIOB
PVT2(JALA0)
PGD_IN
PGD_IN 46

DVT(JALA0)
63
64
65
66
75
76

69

17,20

INVT_PWM 18
BEEP#
34

2
1
R?
2.2K_0402_5%

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

INVT_PWM
BEEP#
THERM_ALERT#
ACOFF

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

21
23
26
27

ACES_85205-0400
@

PVT2(JALA0)

PWM Output
AD

2 TP_CLK
4.7K_0402_5%
2 TP_DATA
4.7K_0402_5%

1
R431
1
R432

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

E51RXD_P80CLK
E51TXD_P80DATA

5VS

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

1
2
3
4

EC_SCI#

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

Place on MiniCard

3VALW

1
2
3
4

23
EC_SCI#
23,25 PM_CLKRUN#

2
1
R427
47K_0402_5%
2
1
C474
0.1U_0402_16V4Z

3VALW

12
13
37
20
38

E51RXD_P80CLK 29
E51TXD_P80DATA 29

JP5

IN

8,21,23,26,27 PLT_RST#

ACES_85205-0400
@

OUT

16 CLK_PCI_LPC

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

Place on RAM door

E51RXD_P80CLK
E51TXD_P80DATA

NC

R425 2

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

0.1U_0402_16V4Z

AVCC

VCC
VCC
VCC
VCC
VCC
VCC
C473
@ 22P_0402_50V8J
2
1

22
EC_GA20
22 EC_KBRST#
23,25 SERIRQ
22 LPC_FRAME#
22
LPC_AD3
22
LPC_AD2
1 @ 33_0402_5% 22
LPC_AD1
22
LPC_AD0

KSO[0..17] 32

67

9
22
33
96
111
125

U22

KSO[0..17]

C467

1
2
3
4

1
2
3
4

NC

C471
1000P_0402_50V7K

32

2
2
0.1U_0402_16V4Z

C470
000P_0402_50V7K
1
1

KSI[0..7]

2
2
0.1U_0402_16V4Z

EC_PME#
2
10K_0402_5%
@

1
R424

C469

JP4
KSI[0..7]

C468

3VALW

EC_VCCA
1
2
2 FBM-L11-160808-800LMT_0603

0.1U_0402_16V4Z
1
2

3VALW

0.1U 0402_16V4Z
1 C466
1

C465

ECAGND

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

31

of

50

2MB SA00001IT00 (MXIC , S IC FL 16MBIT MX25L1605AM2C-12G SO8 ROM , 85MHz)


2MB SA00001OZ00 (WINBOND , S IC FL 32MBIT W25X32VSSIG SOIC 8P 3.3V , 75MHz)
DVT(JALA0)
C299 1

2
0_0603_5%

2 0.1U_0402_16V4Z

1
3
7
4

+SPI_VCC

VDD
SCK
SI
SO

8
6
5
2

R226
EC_SPICLK_R 1
R232 1
R218 1

0_0402_5%
2
2 0_0402_5%
2 0_0402_5%

(Right)

ACES_85201-0605
CONN@

C198
100P_0402_50V8J

0.1U_0402_16V4Z
ON/OFFBTN# 33

PWR_LED#
PWR_SUSP_LED#

KSO0
LID_SW#

KSI4
KSI3
KSI2
KSO0

31

C58

2 @ 100P_0402_50V8J

KSO17

C59

2 @ 100P_0402_50V8J

KSI2

C64

2 @ 100P_0402_50V8J

KSO9

C45

2 @ 100P_0402_50V8J

KSI3

C53

2 @ 100P_0402_50V8J

KSI5

E-KEY BTN#

KSO8

C44

2 @ 100P_0402_50V8J

KSI6

SYNC

KSI7

LOCK

C36

2 @ 100P_0402_50V8J

KSI1

PRESENTATION

KSI2

Program BTN#

KSI3

EMAIL BTN#

KSI4

IE BTN#

LEFT_BTN# 3

SW1
<BOM Structure>
SMT1-05-A_4P
1

ACES_85201-1205
CONN@

+3VALW

+5VS

+5VALW

To FUN/B(LED/B)
C55

2 @ 100P_0402_50V8J

KSI6

C50

2 @ 100P_0402_50V8J

KSI7

C51

2 @ 100P_0402_50V8J

SW2
SMT1-05-A_4P
1

PWR_LED#

+5VS

KSI5

RIGHT_BTN#3

PWR_SUSP_LED#
3

1
2
3
4
5
6
7
8
9
10
11
12

KSO16

KSO0

D10
@
PSOT24C_SOT23

JP6

JP5
1
2
3
4
5
6
7
8
9
10

ACES_88747-2601
CONN@

KSO0
KSI1
KSI5
KSI6
KSI7

31

Q31A

PWR_LED
R262

CAPS_LED# 31
NUM_LED# 31

MEDIA_LED#

R258

10K_0402_5%

Q31B

31 PWR_SUSP_LED

2N7002DW-T/R7_SOT363-6

28
27

2
C197

31

KSO[0..17] 31

5
6

KSI[0..7]

KSO[0..17]

To POWER/B(BTN/B)

KSI[0..7]

TP_DATA

+5VS

KSO0
G2
KSO1
G1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK

DVT(JALA0)

JP3
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

SPI ROM Footprint 150mil

2MB Flash
SPI ROM Footprint 200mil

INT_KBD Conn.
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

100P_0402_50V8J

MX25L1605AM2C-12G_SOP8

ENE suggestion SPI Frequency over 66MHz


SST: 50MHz
MXIC: 70MHz
ST: 40MHz

(Left)

C199

Reserved for BIOS simulator.


Footprint SO8

EC_SPICLK 31
EC_SO_SPI_SI 31
EC_SI_SPI_SO 31

2N7002DW-T/R7_SOT363-6

10K_0402_5%
2

+3VALW

CE#
WP#
HOLD#
VSS

1
2
3
4
5
6

TP_CLK
TP_DATA
LEFT_BTN#
RIGHT_BTN#

TP_CLK
TP_DATA

5
6

R225 1
R219 1

+5VS
31
31

31 EC_SPICS#/FSEL#

1
3
7
4

VCC
SCLK
SI
SO

MX25L512AMC-12G_SO8
@

U15
EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI WP#
2 4.7K_0402_5% SPI HOLD#

JP7

CS#
WP#
HOLD#
GND

+SPI_VCC
EC_SPICLK_R
EC_SO_SPI_SI
EC_SI_SPI_SO

8
6
5
2

1
R239

EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#

+3VALW

To TP/B Conn.
U17

SYS & EC & FP(PBA) & HDCP

ACES_85201-10051
CONN@
1

2 @ 100P_0402_50V8J

KSO7

C43

2 @ 100P_0402_50V8J

KSO14

C56

2 @ 100P_0402_50V8J

KSO6

C42

2 @ 100P_0402_50V8J

KSO13

C49

2 @ 100P_0402_50V8J

KSO5

C41

2 @ 100P_0402_50V8J

KSO12

C48

2 @ 100P_0402_50V8J

KSO4

C40

2 @ 100P_0402_50V8J

KSI0

C60

2 @ 100P_0402_50V8J

KSO3

C39

2 @ 100P_0402_50V8J

KSO11

C47

2 @ 100P_0402_50V8J

KSI4

C54

2 @ 100P_0402_50V8J

KSO10

C46

2 @ 100P_0402_50V8J

KSO2

C38

2 @ 100P_0402_50V8J

KSI1

C32

2 @ 100P_0402_50V8J

KSO1

C37

2 @ 100P_0402_50V8J

+3VALW

DVT(JALA0)

C57

KSO15

D17
DAN217_SC59
@

+3VALW

JALA0

PVT(JALA0)

1
2
4
R290 453_0402_1%

+5VALW

1
2
2
R291 150_0402_5%

+5VS

3
1

LED1

MP(JALA0)

31

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

ICH_SPI_CLK
ICH_SPI_MOSI
ICH_SPI_MISO

ICH_SPI_CLK 23
ICH_SPI_MOSI 23
ICH_SPI_MISO 23

MX25L512AMC-12G_SO8
6

Wireless SWITCH

Reserved for BIOS simulator.


Footprint SO8

SSS-12R-V-T/R_4P

PWR_SUSP_LED#

SPI ROM Footprint 150mil

SN200001B00 (DIPTRONICS , S DIP SW SSS-12R-V-T/R 1P2T DIPTRO H2 4P)


SN200001G00 (MISAKI , S DIP SW NSS607-212N-EEEG1T 1P2T MISAKI H2 4P)

PWR_LED#

1
3
7
4

SW3

YG

U4
ICH_SPI_CS0#
ICH_SPI_WP#
ICH_SPI_HOLD#

23 ICH_SPI_CS0#
23 ICH_SPI_WP#
23 ICH_SPI_HOLD#
WL_SW#

HT-297DQ-GQ_AMB-YG
A

Compal Footprint

(AMB/GREEN)

PVT(JALA0) Check

+3VS

@
R288
100K_0402_5%

+3VALW

(AMB/GREEN)

BATT_GRN_LED#

BATT_GRN_LED# 31

D16
DAN217_SC59
@

+3VALW

Q11A
2N7002DW-T/R7_SOT363-6

300_0402_5%

LED3
1

300_0402_5%

MINI1_LED#

SW4

31

3
3

BT_SW#

MINI1_LED# 29

HT-191UD_Amber_0603

R292
+5VS

(AMB)

BT SWITCH

26

5IN1_LED#

22

SATA_LED#

SATA_LED#

+3VS

LED4

R296

MP(JALA0)

+3VS
R287
100K_0402_5%

LED2

BATT_AMB_LED# 31

BATT_AMB_LED#

1
2
2
R294 150_0402_5%

+5VALW

YG

1
2
4
R293 453_0402_1%

HT-297DQ-GQ_AMB-YG
+5VALW

SSS-12R-V-T/R_4P

+3VS

(BLUE)
1

BT_LED#

Issued Date

2007/09/20

Deciphered Date

Q11B
2N7002DW-T/R7_SOT363-6

Compal Electronics, Inc.

Compal Secret Data

Security Classification
BT_LED# 31

MEDIA_LED#

2008/09/20

Title

HT-191NBQA_BLUE_0603
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday May 16 2008

Sheet

32

of

50

Power Button
ON/OFF switch

HDA MDC Conn.


+3V
+3VALW

R286
R573

2
@ 10K_0603_5%

22 HDA_SDOUT_MDC

R250

2
@ 10K_0603_5%

22 HDA_SYNC_MDC
22 HDA_SDIN1
22 HDA_RST_MDC#

100K_0402_5%

HDA_SDIN1_MDC
33_0402_5%

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

1
R279
1
R277

+MDC_VCC

2
4
6
8
10
12

+3V

PM@
2
0_0402_5%
2
0_0402_5%
GM@

1
+3V
+1.5V

C355
1

1U_0603_10V4Z

HDA_BITCLK_MDC 22
1

D13
2

ON/OFFBTN#

R276

1
3
5
7
9
11

51ON#

ON/OFF

31

51ON#

39

R280
0_0402_5%

GND
GND
GND
GND
GND
GND

Bottom Side
32 ON/OFFBTN#

20mil

JMDC1

13
14
15
16
17
18

DAN202UT106_SC70-3

ACES_88018-124G
CONN@

TOP Side

C354

Connector for MDC Rev1.5


C321

22P_0402_50V8J

D15
RLZ20A_LL34

For EMI

1
EC_ON

EC_ON

S 2N7002_SOT23

Q28

2
G

31

1000P_0402_50V7K
1

R249
10K_0402_5%

Power ON Circuit
+3VS
+3VALW

+3VALW

14
P

CH751H-40PT_SOD323-2
@
C328
1U_0603_10V6K
@

U19B
SN74LVC14APWLE_TSSOP14
SYS_PWROK

1
R260

2
@ 0_0402_5%

EC_PWROK 23,31

For South Bridge

VR_ON

U19A
SN74LVC14APWLE_TSSOP14

31,46

14

R257
180K_0402_5%
@

D14

+3VS

PVT

+3VALW

+3VALW
+RTCBATT

14
I

VS_ON

R495
1K_0402_5%

43

For +VCCP/+1 05VS

D29

1 1

0.1U_0402_16V4Z

I
G

C341

U19D
SN74LVC14APWLE_TSSOP14

2
1

5
D

SUSP

2
G
Q32
2N7002_SOT23

U19C
SN74LVC14APWLE_TSSOP14

10K_0402_1%

+3VALW

2
G
Q33
2N7002_SOT23
PM@

14

1U_0402_6.3V4Z

14
2

U19F
SN74LVC14APWLE_TSSOP14

10

13

12

VGA_ON

17

JALA0

DVT

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

+CHGRTC

C334
PM@
1U_0402_6.3V6K

C518

SUSP

I
7

For NV

U19E
SN74LVC14APWLE_TSSOP14

11

BAS40-04_SOT23-3

2 0.1U_0402_16V4Z

R261
31.6K_0402_1%
PM@

C324

For ATI

+3VALW

+RTCVCC
+3VS

SUSP

R668
10K_0402_1%
1
2

37,45

SUSP#

31,37,45

R263
14

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


E

33

of

50

+VDDA
+5VAMP

60mil

1
R547
10K_0402_5%

+5VS

C574
1
1U_0402_6.3V4Z

R548

C
2

R549

2
2.4K_0402_1%

2SC2411K_SOT23

40mil

INT_MIC1
C578
1
C579
LINE_L
1
C582
LINE_R
1
C583

R558 1K_0402_1%
INT_MIC_R 2
1

35

LINE_L

35

LINE_R

35

MIC1_L

35

MIC1_R

MIC1_L
C580
MIC1_R
C581

2
2
2
2

35,38 HP_PLUG#

R556 2

1 39.2K_0402_1%

35,38 LINEIN_PLUG#
35,38 MIC_PLUG#

R557 1
R555 2

2 10K_0402_1%
1 20K_0402_1%

31
SPDIF
1
R540

PORT-B (PIN 21, 22)

10K

PORT-C (PIN 23, 24)

EAPD

0_0402_5%

AMP_RIGHT

MIC2_L

HP_OUT_L

39

HP_LEFT

MIC2_R

HP_OUT_R

41

HP_RIGHT

LINE1_L

NC

45

LINE1_R

DMIC_CLK

46

CD_L

NC

43

20

CD_R

NC

44

19

CD_GND

SENSE B

AMP_LEFT 35

HP_LEFT 35
HP_RIGHT 35

For EMI

PORT-D (PIN 35, 36)

39.2K

PORT-E (PIN 14, 15)

20K

PORT-F (PIN 16, 17)

10K

PORT-G (PIN 43, 44)

5.1K

PORT-H (PIN 45, 46)

DVT(JALA0)

1
R541

2
1
0_0402_5%

MIC1_R
PCBEEP

SDATA_IN
MONO_OUT

37

LINE1_VREFO

29

GPIO1

31

MIC1_VREFO_L

28

INT(Analog) MIC
22

MIC1_VREFO_R

32

MIC2_VREFO

30

VREF

27

JDREF

40

NC

33

AVSS1
AVSS2

26
42

SYNC
SDATA_OUT

47

EAPD

1
R543

SPDIFO
DVSS1
DVSS2

D34

HP_PLUG#

1
R659

1
R660

HDA_SDIN0 22

INT_MIC_R
C596

MIC1_VREFO_R
MIC2_VREFO

PVT2(JALA0)

1
2 MIC_R
L59 MBC1608121YZF_0603
GND_R
1
2
R575
0_0603_5%

220P_0402_50V7K
2 MIC_GND_R

MIC1_VREFO_L

CODEC_VREF

15mil
C608
330P_0402_50V7K

1
2
3
4

5
6

G1
G2

ACES_88266-04001
CONN@

10mil

MP(JALA0)

1
1
C562
C560
10U_0805_10V4Z
0.1U_0402_16V4Z
2
2
R522
20K_0402_1%

+3VS

1
R519

2
0_0805_5%

1
R577

2
0_0805_5%

1
R520

2
0_0805_5%

1
R578

2
0_0805_5%

R678
10K_0402_5%

1
R563

2
0_0805_5%

1
R568

2
0_0805_5%

HDA_GPIO3
0_0402_5%

GND

GNDA

GND

GNDA

Use GPIO3 to detect Docking plug or not


(The driver behavior is that when driver
DVT(JALA0) detect low,driver will enable SPDIF out)
Issued Date

Compal Electronics, Inc.

Compal Secret Data


2007/09/20

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC MB A4221
Document Number

Rev
C

401552

Date

1
2
3
4

0_0402_5%

Security Classification

JP4

15mil

10mil

PVT(JALA0)
EC_DOCKIN#

2
33_0402_5%

R576
2.2K_0402_5%

RESET#

GPIO0
GPIO3
SENSE A
SENSE B

HDA_SDIN0_AUDIO

ALC268-GR_LQFP48_9X9
PVT
AGND
SA00001GD10 (S IC ALC268-VB1-GR LQFP 48P)

19,28 31,38 EC_DOCKIN#

MIC2_VREFO

2 C561
22P_0402_50V8J
HDA_BITCLK_AUDIO

CH751H-40PT_SOD323-2

5.1K

AMP_RIGHT 35

BIT_CLK

SENSE A

MIC1_L

2
3
13
34

2SPDIF_R 48
0_0402_5%
4
7

DGND

Codec Signals

20K

AMP_LEFT

36

HDA_GPIO3
SENSE_A

1
R521

35

LINE_OUT_R

10

22 HDA_SDOUT_AUDIO

DVT(JALA0)

LINE_OUT_L

NC

11

22 HDA_SYNC_AUDIO

Place close to Codec

NC

15

MIC1_C_L
21
4.7U_0805_6.3V6K
MIC1_C_R
22
4.7U_0805_6.3V6K
MONO_IN
12

22 HDA_RST_AUDIO#

0.1U_0402_16V4Z
10U_0805_10V4Z
2
2

14

MIC2_C_L
16
4.7U_0805_6.3V6K
MIC2_C_R
17
4.7U_0805_6.3V6K
LINE_C_L
23
4.7U_0805_6.3V6K
LINE_C_R
24
4.7U_0805_6.3V6K
18

+1.5VS

C567

ESD(JALA0)

L47
MBK1608121YZF_0603
1
2

U36

AVDD1

C563

+3VS

R518
0_0603_5%
PM@

+1.5VS_DVDD
1

DVDD

0.1U_0402_16V4Z
1
C550

DVDD_IO

38

C565
10U_0805_10V4Z

PORT-A (PIN 39, 41)

C544

GM@

25

L48 1
2
FBM-L11-160808-800LMT_0603

10mil

AVDD2

+VDDA

39.2K

C549

0.1U_0402_16V4Z
2
2
10U_0805_10V4Z
+AVDD_HDA

Impedance

+3VS DVDD
1

10mil

HD Audio Codec

D30
CH751H-40PT_SOD323-2

R544
10K_0402_5%

Sense Pin

L46
MBK1608121YZF_0603
1
2

560_0402_5%

268@
888VB@
888VC@

C572 1
1U_0402_6.3V4Z

SB_SPKR

C587

4.75V

4.7U_0805_10V4Z

0.01U_0402_16V7K

BOM Option
ALC268
ALC888S-VB
ALC888S-VC

MONO_IN

1
R551

Q43

2
B

560_0402_5%

23

C588

SHDN

G9191-475T1U_SOT23-5

C571 1
1U_0402_6.3V4Z

R550

+VDDA

GND

BEEP#

BYP

40mil

560_0402_5%

31

OUT

C573 1
1U_0402_6.3V4Z

2
1U_0402_6.3V4Z

1
1
L49 1
C586
C585
2
KC FBM-L11-201209-221LMAT_0805
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z

IN

PCM_SPK#

25

R554
10K_0402_5%

Cardbus usage for JALA0

C584

(output = 300 mA)

U38

L50 1
2
KC FBM-L11-201209-221LMAT_0805

Friday, May 16, 2008


G

Sheet

34
H

of

50

+5VAMP

W=40mil
+3VS
1
1

+5VAMP

34

HP_RIGHT

34

HP_LEFT

C577

2
0.01U_0402_16V7K

HPOUT_R
HPOUT_L

VOL_AMP

39K_0402_5%

EC_MUTE 31

C576

4
6

HP_R
HP_L

INR_H
INL_H

26

/SD

28

BEEP

12
14

CP+
CP-

25

BIAS

CVSS

15

VSS

16

GND
PGND
PGND
CGND
GND

2
23
7
13
29

17
18

HP_RIGHT_R
39K_0402_5% HP_LEFT_R

6 1

HP EN

PLUG#

Q46B
2N7002DW-T/R7_SOT363-6

8
9

24

HP_PLUG# 34,38

2
2

VDD

2 100K_0402_5%

LOUT+
LOUT-

SPKL+
SPKL-

R546 1

2
1
2

R552
100K_0402_1%

2 EC_MUTE
G
Q45
2N7002_SOT23

19

/AMP EN

C558
1U_0603_10V4Z
2

20
10

ROUT+
ROUT-

27

11

INR_A
INL_A

2 100K_0402_5%

HP_PLUG#
R565
100K_0402_5%

R564
100K_0402_5%

R545 1

R553
30K_0402_5%

VOL_AMP

SPKR+
SPKR-

22
21

HP_RIGHT_C 1
4.7U_0805_6.3V6K R532
HP_LEFT_C
1
4.7U_0805_6.3V6K R530

+5VAMP
+5VAMP

Q46A
2N7002DW-T/R7_SOT363-6

2
1

JALA0
HP_RIGHT
1
C546
HP_LEFT
1
C545

3
5

HPF Fc = 604Hz

+5VAMP

U37

560_0402_5%

560_0402_5%

JALA0

PVDD
PVDD

AMP_LEFT

34
1

AMP_RIGHT_C
1U_0402_6.3V4Z
AMP_LEFT_C
1U_0402_6.3V4Z

HVDD

AMP_RIGHT_C-1
1
C556
AMP_LEFT_C-1
1
2
1
C547
C555
0.47U_0603_16V4Z
R531
R533

CVDD

C548
0.47U_0603_16V4Z
1
2

AMP_RIGHT

34

C554
C575
0.1U_0402_16V4Z
2
2
4.7U_0805_10V4Z

C569
0.1U_0402_16V4Z
2

PLUG# 2
R661
C570
1U_0603_10V4Z

HP_PLUG#
1
0_0402_5%
@

DVT(JALA0)

APA2057A_TSSOP28

LINE Out/HP Out JACK

2.2U_0805_10V6K
2

JHP1

20mil

Gain= 14dB
2

C589

FSOV MP(JALA0)
Change 75 to 54.9 ohm

Int. Speaker Conn.

SPKL+
SPKL-

R30
R29

1
1

2 0_0603_5%
2 0_0603_5%

SPK_L+
SPK_L-

1
2
3
4

20mil

DVT
MP(JALA0)

1
2

C591
PLUG#

330P_0402_50V7K 330P_0402_50V7K
1
1

R559 54.9_0603_1%
HPOU _R_1 1
2
L51
HPOUT_L 1
HPOU _L_1 1
2
R560 54.9_0603_1%
L52
HPOUT_R 1

JP1

8
7

HPOUT_R_2
2
FBM-11-160808-700T_0603
HPOUT_L_2
2
FBM-11-160808-700T_0603

3
6
2
1

For Docking

Left

38
38

G1
G2

ACES_88266-02001
CONN@

SINGA_2SJ-E351-S03
CONN@
D_HPOUT_L
D_HPOUT_R

D_HPOUT_L
D_HPOUT_R

R304 1 MAIN@ 2 0_0603_5%


R305 1 MAIN@ 2 0_0603_5%

HPOUT_L
HPOUT_R

DVT

Change part

For Docking

JP2
SPKR+
SPKR-

R192 1
R191 1

2 0_0603_5%
2 0_0603_5%
C609
330P_0402_50V7K

SPK_R+
1 1
SPK_R2 2
2 C610
330P_0402_50V7K
3 G1
4 G2
1
ACES_88266-02001
CONN@

38
38

Right

D_LINE_L
D_LINE_R

D_LINE_L
D_LINE_R

R299 1 MAIN@ 2 0_0603_5%


R300 1 MAIN@ 2 0_0603_5%

LINE_L
LINE_R

LINE-IN JACK
JLINE1

For Docking
38
38

D_MIC_L
D_MIC_R

D_MIC_L
D_MIC_R

R306 1 MAIN@ 2 0_0603_5%


R308 1 MAIN@ 2 0_0603_5%

8
7

MIC1_L
MIC1_R
LINEIN_PLUG#

34,38 LINEIN_PLUG#
3

38 AUDIO_GNDA

R2

2 0_0603_5%

34

LINE_R

34

LINE_L

LINE_R

R571 1K_0402_1%
LINE_R_1
2
1

LINE_L

4
LINE_R_R
2
FBM-11-160808-700T_0603
LINE_L_R
2
FBM-11-160808-700T_0603
1
1

1
L55
1
L56

LINE_L_1

R566 1K_0402_1%

C595
220P_0402_50V7K
2

ESD DVT(JALA0)
Change 75 to 1K ohm

3
6
2
1
SINGA_2SJ-E351-S03
CONN@

C594
220P_0402_50V7K

(HDA Jack)

MIC JACK

MIC1_R

34

MIC1_L

1
L53
1
L54

MIC1_L_L

R562 1K_0402_1%

ESD DVT(JALA0)
Change 75 to 1K ohm

MIC_PLUG#

2007/09/20

C592
220P_0402_50V7K

SINGA_2SJ-E351-S01
CONN@

(HDA Jack)

Compal Electronics, Inc.


2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

3
6
2
1

MIC1_L_1
FBM-11-160808-700T_0603
1

C593
220P_0402_50V7K

5
4

MIC1_R_1

FBM-11-160808-700T_0603

Compal Secret Data

Security Classification
Issued Date

34

8
7

34,38 MIC_PLUG#

R569
2.2K_0402_5%
2

R570
2.2K_0402_5%
R561 1K_0402_1%
MIC1_R_R
2
1

JMIC1

MIC1_VREFO_R

MIC1_VREFO_L

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


E

35

of

50

H19
H_3P0
@

+5VS

10U_0805_10V4Z
2

H14
H_3P0

PVT2(JALA0)
1

C8

+5VS

H2
H_3P0

H8
H_3P0

FAN1 Conn

H12
H_3P3
@

H10
H_3P3

H3
H_3P3

H23
H_3P3

H11
H_3P0

H21
H_3P0

PVT2(JALA0)

H6
H_4P2
@

H7
H_4P2
@

H33
H_3P0
@

H34
H_3P0
@

H15
H_4P2

H13
H_3P3

H16
H_3P3

H18
H_3P3

H5
H_3P3

C16
1000P_0402_50V7K
1
2

BAS16_SOT23-3
C10
10U_0805_10V4Z
1
2
+3VS

H17
H_3P0

H20
H_3P0

D3
1

G993P1UF_SOP8

R34
10K_0402_5%
JP12

C26
1000P_0402_50V7K

H9
H_4P1N

1
2
3

31 FAN_SPEED1

ACES_85205-03001
CONN@

H22
H_4P6X4P1N

40mil
+VCC_FAN1

DVT(JALA0)

C601

C602

330P_0402_50V7K
1

330P_0402_50V7K
1

C603

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD5
@

FIDUCIAL_C40M80

FD6
@

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD4

+5VALW

FD3

+5VALW

FD2

+5VALW

FD1

EMI

FIDUCIAL_C40M80

330P_0402_50V7K
1

ADD DVT(JALA0)
EMI

C604
820P_0402_50V7K

+5VS

+5VS

+VCC_FAN1
EN_DFAN1

EN_DFAN1

D1
1SS355_SOD323-2

8
7
6
5

GND
GND
GND
GND

31

VEN
VIN
VO
VSET

U2
1
2
3
4

C605
820P_0402_50V7K

ADD PVT(JALA0)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday May 16 2008

Sheet

36

of

50

+5VALW TO +5VS

+3VALW TO +3V(ICH9M AUX Power)


+3VALW

+5VS

R289
470_0603_5%

C276

S
S
S
G

1
2
3
4

D
D
D
D

C277

AO4466_SO8

C275

R189
470_0603_5%

10U_0805_10V4Z
2
2
1U_0603_10V4Z

SYSON#

29,30,38 SYSON#

Q35A

2
10U_0805_10V4Z

C359

10U_0805_10V4Z
2
2
1U_0603_10V4Z

10U_0805_10V4Z
2
2
10U_0805_10V4Z

8
7
6
5

2
C360

AO4466_SO8

C358

3V_GATE

2
1
R188
200K_0402_5%

SBPWR_EN#

R281
100K_0402_5%

C249

Q16A
SUSP

SBPWR_EN#

0.1U_0603_25V7K
Q36A
2
2N7002DW-T/R7_SOT363-6

0.1U_0603_25V7K
2
2N7002DW-T/R7_SOT363-6

+5VALW
2

2N7002DW-T/R7_SOT363-6

SYSON

+VSB

SUSP

5
4

31,43,44

Q16B
2N7002DW-T/R7_SOT363-6

Q36B
2N7002DW-T/R7_SOT363-6

5VS_GATE

2
1
R285
200K_0402_5%

+VSB

SYSON

C362

1
2
3
4

3 1

R284
100K_0402_5%

U11
S
S
S
G

C361

D
D
D
D

+5VALW

+3V

U21
8
7
6
5

+5VALW

+3VALW TO +3VS

33,45

SUSP

SUSP

+3VALW

R282
100K_0402_5%

+3VS

Q35B

U20
31,33,45
C350

2N7002DW-T/R7_SOT363-6

10U_0805_10V4Z
2
2
1U_0603_10V4Z

AO4468

R274
470_0603_5%

R283
10K_0402_5%

S
5VS_GATE

C351

AO4466_SO8
10U_0805_10V4Z
2
2
10U_0805_10V4Z

SUSP#

S
S
S
G

C346

D
D
D
D

1
2
3
4

1 1

C347

8
7
6
5

2 SUSP
G
Q34
2N7002_SOT23

DVT

+5VALW

+1.8V to +1.8VS

+1.5V to +1.5VS

+1.8VS

+1.5V

R201
100K_0402_5%

+1.5VS

+1.8V

SUSP

C285

SUSP

+VSB

PM@

2
G
Q19
S
2N7002_SOT23

31,44 SBPWR_EN

3
1

R202
100K_0402_5%

SUSP

C297

0.1U_0603_25V7K
2
Q23A
2N7002DW-T/R7_SOT363-6

1
1

1
1

R212
470_0603_5%
@

D
2 SYSON#
G
Q20
2N7002_SOT23

D
2 SUSP
G
Q12
2N7002_SOT23
@

+1.5V

R206
470_0603_5%

D
2 SUSP
G
Q15
2N7002_SOT23

DVT

2 SYSON#
G
Q21
2N7002_SOT23
@

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/09/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SBPWR_EN#

SBPWR_EN#

2
1

R177
470_0603_5%
@

1
S

D
2 SUSP
G
Q1
2N7002_SOT23
PM@

+1.8V

R178
470_0603_5%

1
1

+0.9VS

2
1
3

+1.05VS

R6
470_0603_5%
PM@

R240
470_0603_5%

Q23B
2N7002DW-T/R7_SOT363-6

1.5VS_GATE

2
1
R222
510K_0402_5%

SUSP

24
R236
470_0603_5%

1
+2.5VS

2 SUSP
G
Q26
2N7002_SOT23

SI4856/AO4430

0.1U_0603_25V7K
2 PM@
Q17A
2N7002DW-T/R7_SOT363-6
PM@

+1.5VS

C293

10U_0805_10V4Z
2
2
1U_0603_10V4Z

AO4466_SO8

3
1

C296

C294

1
2
3
4

10U_0805_10V4Z
2
2
10U_0805_10V4Z

Q17B
2N7002DW-T/R7_SOT363-6

1.8VS_GATE

S
S
S
G

C292

2
1
R203
510K_0402_5%
PM@

R195
470_0603_5%
PM@

D
D
D
D

+VSB

10U_0805_10V4Z
2
1U_0603_10V4Z
PM@ 2
PM@

8
7
6
5

C264
SI4856ADY_SO8
10U_0805_10V4Z
PM@
2
PM@ 2
10U_0805_10V4Z
PM@
SI4856/AO4430

C284

C283

1
2
3
4

U13
S
S
S
G

C265

D
D
D
D

U12
8
7
6
5

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Sheet

Friday, May 16, 2008


E

37

of

50

5VS

1
2

Q9A
2N7002DW-T/R7_SOT363-6
MAIN@

20

EC_DOCKIN

19,28,31,34 EC_DOCKIN#

MAIN@

EC_DOCKIN#_S0
Q9B
2N7002DW-T/R7_SOT363-6
MAIN@

10K_0402_5%

R663
10K_0402_5%
@

R102
10K_0402_5%
MAIN@

R97

R662
10K_0402_5%
MAIN@

1
D

R664
10K_0402_5%
@

3VS
3VALW

5VS

3VS

20

C600
@
0.1U_0402_16V4Z

DVT
10/15 Acer DVR 1028 Rev0.3
JDOCK1
C

DOCK_B+
5VALW

ACER DOCK
Normal

67
68

19V_5A
5V_USB_3A

33
34
35
36
37
38
39
40
41
42
43
44
45

LIN_IN_DT#
LIN_IN_L
LIN_IN_R
MIC_DT#
MIC_L
MIC_R
GNDA
DOCK_DT1#
SPDIF
GND
LAN_2
LAN_2#
GND

3VALW

34,35 LINEIN_PLUG#
35
D_LINE_L
35
D_LINE_R
34,35 MIC_PLUG#
35
D_MIC_L
35
D_MIC_R
35 AUDIO_GNDA

R223
10K_0402_5%
MAIN@
31

DOCKIN#

C306
0.1U_0402_16V4Z
MAIN@

34
28 D_LAN_MIDI2
28 D_LAN_MIDI2-

23
USB20_P3
23
USB20_N3
29,30,37 SYSON#

AUDIO_GNDA
DOCKIN#

SPDIF
D_LAN_MIDI2
D_LAN_MIDI2-

USB20_P3
USB20_N3

28 D_LAN_ACTIVITY#
28 D_LAN_LINK#

28 D_LAN_MIDI0
28 D_LAN_MIDI0-

D_LAN_MIDI0
D_LAN_MIDI0-

28 D_LAN_MIDI1
28 D_LAN_MIDI1-

D_LAN_MIDI1
D_LAN_MIDI1-

28 D_LAN_MIDI3
28 D_LAN_MIDI3-

D_LAN_MIDI3
D_LAN_MIDI3-

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

GND
USB
USB#
USB_EN#
RESERVED
VGA_DT#
LAN_PWR
LAN_ACT
LAN_LINK
GND
LAN_0
LAN_0#
GND
LAN_1
LAN_1#
GND
LAN_3
LAN_3#
GND

72
73
74

GND
GND
GND

46 P3
47 (67)
48
49 33
50 34
51 35
52 36
53 37
54 38
55 39
56 40
57 41
58 42
59 43
60 44
61 45
62
63 P4
64 (68)

1
P1
(65) 2
3
20
4
21
5
22
6
23
7
24
8
25
9
26 10
27 11
28 12
29 13
30 14
31 15
32 16
17
P2 18
66) 19

GND
GND

65
66

GND
DVI_CLK
DVI_CLK#
GND
DVI_TX0
DVI_TX0#
GND
DVI_TX1
DVI_TX1#
GND
DVI_TX2
DVI_TX2#
GND
VGA_R
GND
VGA_G
GND
VGA_B
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

D_DVI_TXC 20
D_DVI_TXC- 20
D_DVI_TXD0 20
D_DVI_TXD0- 20
D_DVI_TXD1 20
D_DVI_TXD1- 20
D_DVI_TXD2 20
D_DVI_TXD2- 20

PVT

D_CRT_R_R

R669 1 MAIN@ 2 0_0603_5%

D_CRT_R 19

D_CRT_R_G

R670 1 MAIN@ 2 0_0603_5%

D_CRT_G 19

D_CRT_R_B

R671 1 MAIN@ 2 0_0603_5%

D_CRT_B 19

MAIN@

DOCK_DT2#
HP_L
HP_R
HP_DT#
GNDA
DVI_DT
DVI_DCDT
DVI_DDCCK
VGA_VS
VGA_HS
VGA_DDCCK
VGA_DDCDT
5V_S0

20
21
22
23
24
25
26
27
28
29
30
31
32

GND
GND
GND

69
70
71

ACER DVR1027 Rev: 0.5

DOCK_DT2#

AUDIO_GNDA

R1

1
2 1K_0402_5%
D_HPOUT_L 35
D_HPOUT_R 35
HP_PLUG# 34,35

D_DVI_DET 20
D_DVI_SDATA 20
D_DVI_SCLK 20
D_CRT_VSYNC 19
D_CRT_HSYNC 19
D_DDC_CLK 19
D_DDC_DATA 19
5VS

JAE_SP07-10207-22
CONN@

PVT2

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC MB A4221
Rev
C

401552

Date:

Friday, May 16, 2008

Sheet
1

38

of

50

Place at HW side

VIN

PD11
PDS1040-13_POWERDI5-3
2
1
3

DOCK_B+
SP02000EF00
PJP1

PR2
10K_0402_5%

PR7
10K_0402_5%

PD3
GLZ4.3B_LL34-2

E&T_4510-E04C-01R
<BOM Structure>

PR8
10K_0402_5%
1
2

PU1A
LM358DT_SO8

23,31,42 ACIN

PR6
20K_0402_1%

PC1
1000P_0402_50V7K

PR5
22K_0402_5%
1
2

PC6
0.1U_0603_25V7K
2
1

PC4
100P_0402_50V8J

PD2
1SS355_SOD323-2
2
1 1

1
PC3
1000P_0402_50V7K

PR3
84.5K_0402_1%

PR4
10K_0402_5%
1
2
1

JUMP_43X79
PC2
100P_0402_50V8J

VIN

VS

VIN

PJ1
2DC_IN_S2

DC_IN_S1

PR1
1M_0402_1%
1
2

PL1
SMB3025500YA_2P
1

G1

G2

PC5
1000P_0402_50V7K

RTCVREF

Vin Dectector

Min.
H-->L 16.976V
L-->H 17.430V

PBJ1
2

+RTCBATT
+RTCBATT

Typ
17.525V
17.901V

Max.
17.728V
18.384V

ML1220T13RE
45@

VIN

PJ2
2

+3VALWP

PJ3
1

+3VALW

+1.5VP

JUMP_43X118

+1.5V

JUMP_43X118

PD4
LL4148_LL34-2

N1

PJ7
1

+VSB

+1.8VP

2
2

OUT

IN
GND

PC9
10U_0805_10V4Z

N2

+1.8V

JUMP_43X118

PJ9
1

+1.05VS

+2.5VSP

+2.5VS

JUMP_43X118

PJ16
2

+1.05VSP

PJ17
1

+1.05VS

+1.8VP

JUMP_43X118

+1.8V

JUMP_43X118

PC10
1U_0805_25V4Z

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

PJ8
2

3.3V

+0.9VS

PU2
G920AT24U_SOT89-3

PC8
0.1U_0603_25V7K

PR14
200_0603_5%

PR16
560_0603_5%
1
2

JUMP_43X118

PR15
560_0603_5%
1
2

JUMP_43X79

JUMP_43X39

+1.05VSP

RTCVREF

+CHGRTC

+0.9VSP

PJ6
2

+VSBP

VS
1

PR13
22K_0402_1%
1
2

51ON#

+5VALW

33

PC7
0.22U_1206_25V7K

PR12
100K_0402_1%

PJ5
1

PR10
68_1206_5%

JUMP_43X118

PR9
68_1206_5%
2

PR11
200_0603_5%
1
2

+5VALWP
PQ1
TP0610K-T1-E3_SOT23-3

CHGRTCP

PJ4

PD5
LL4148_LL34-2
2
1

BATT+

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
D

39

of

50

PH1 under CPU botten side :


CPU thermal protection at 96 degree C
Recovery at 60 degree C
VL
VL
VL

TM_REF1

+
-

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

+3VALWP

1
2

LL4148_LL34-2

PR26
1K_0402_1%

PR23
100K_0402_1%
2
1
VL

PU3A
LM393DG_SO8

PR25
100K_0402_1%
2

PC15
1000P_0402_50V7K

PR22
13.3K_0402_1%

PR24
6.49K_0402_1%
2
1

PC14
0.22U_0603_16V7K

PJP2

PD6
O

EC_SMCA

PQ2
DTC115EUA_SC70-3

PR19
13.3K_0402_1%
1
2

MAINPWON 22,41
1

PR18
47K_0402_1%
1
2

PC13
0.01U_0402_25V7K

PR17
47K_0402_1%

1
PC11
0.1U_0603_25V7K

PH1
100K_0603_1%_TH11-4H104FT
2

1
PC12
1000P_0402_50V7K

1
2

BATT+

PL2
SMB3025500YA_2P
1
2

BATT_S1

VMB

BATT_TEMP 31

PR21
2

EC_SMB_CK1 17,31

PH2 near main Battery CONN :


BAT. thermal protection at 79 degree C
Recovery at 47 degree C

100_0402_1%

SUYIN_200109MS020G209ZR

VL
2

PR20
1

EC_SMB_DA1 17,31

@ PR27
@PR27
47K_0402_1%

@PR28
@
PR28
47K_0402_1%
1
2

PQ3
TP0610K-T1-E3_SOT23-3

5
TM_REF1

O
-

@ PR32
@PR32
22.1K_0402_1%

@PD7
@
PD7
LL4148_LL34-2
2
1

PU3B
LM393DG_SO8

@ PC18
@PC18
0.22U_0603_16V7K

PR30
@ 9.09K_0402_1%
1
2

1
2

VL

+VSBP

1
PC17
0.1U_0603_25V7K

PR31
22K_0402_1%
1
2

VL

1
PR29
100K_0402_1%

PC16
0.22U_1206_25V7K

@PH2
@
PH2
100K_0603_1%_TH11-4H104FT

B++

VL

100_0402_1%

EC_SMDA

PR34
0_0402_5%
2

SPOK

PQ4
2N7002W-T/R7_SOT323-3

2
G

41

PC19
0.1U_0402_16V7K

PR33
100K_0402_1%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
D

40

of

50

ISL6237_B+

ISL6237_B+

3
2
1
17

DH5
PR40 2.2_0603_5%
BST5A 2
1

LX3

PHASE2

PHASE1

16

LGATE1

18

DL5

DL3

23

LGATE2

PC25
2200P_0402_50V7K
2
1

PC24
4.7U_1206_25V6K
2
1

PC34
680P_0402_50V7K

1
+ PC35
C
150U_D2E_6.3VM_R18

1
2
3

3
2
1

25

LX5

PC32
0.1U_0603_25V7K

PC31
0.1U_0603_25V7K

PQ8
AO4712_SO8

PR41
61.9K_0402_1%
2

15

BOOT1

PR39
4.7_1206_5%
2
1

UGATE1

PC29
1U_0603_10V6K
1
2

19

PL4
8.2UH_PCMB063T-8R2MS_4.5A_20%
2
1

BOOT2

PVCC

5
6
7
8

UGATE2

24

+5VALWP

26

LDO

TP

VCC

VIN

33

PQ6
AO4466_SO8
4

PC28
4.7U_0805_6.3V6K
2
1

PC27
1U_0603_10V6K
1
2

2
6

PC33
680P_0402_50V7K

DH3
PR37
2
1 BST3A
2.2_0603_5%

2
1

4
1

2
C

VL

1
2
3
PQ7
AO4712_SO8

PR38
0_0402_5%

PC30
330U_D3L_6.3VM_R25M

8
7
6
5

1
PR36
4.7_1206_5%

2
1

PC26
0.1U_0603_25V7K

PQ5
AO4466_SO8
4

PL3
8.2UH_PCMB063T-8R2MS_4.5A_20%
1
2

+3VALWP

PC23
4.7U_1206_25V6K
2
1

8
7
6
5

5
6
7
8

PC22
2200P_0402_50V7K
2
1

PR35
0_0805_5%
1
2

PC21
4.7U_1206_25V6K
2
1

PC20
4.7U_1206_25V6K
2
1

PL13
FBMA-L11-322513-151LMA50T_1210
1
2
PC162
470P_0402_50V7K
2
1

PC160
470P_0402_50V7K
2
1

PC159
470P_0402_50V7K
2
1

B+

PC161
470P_0402_50V7K
2
1

B++

PL12
FBMA-L11-322513-151LMA50T_1210
1
2

FB3
@ PR42
10K_0402_1%

VL

30

OUT2

32

REFIN2

PGND

22

OUT1

10

FB1

11

BYP

SKIP

29

2VREF ISL6237
1
PC36

REF

LDOREFIN

@ PR44
2
PR45
1

20

PR46
100K_0402_1%
1
2

POK2

28

EN_LDO

POK1

13

14

EN1

27

EN2

ILIM1

12

ILIM2

31

ILIM2

GND
21

TON
2

NC

2VREF_ISL6237 1

1
2

2
3

PC38
0.047U_0603_16V7K

@ PR55
47K_0402_5%
1
2

PR54
0_0402_5%
2

PU4
ISL6237IRZ-T_QFN32_5X5

PR53
0_0402_5%

VL

PR48
330K_0402_1%
2
1

40
B

PR49
330K_0402_1%

+5VALWP Ipeak=8.444A ; Imax=5.91A


Choke DCRmax=60m ohm, DCRtyp=54m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
Iocp=Ilimit+Delta I/2
=10.147A ~ 11.980A
Delta I=1.96A (Freq=400KHz)

@ PC39
0.047U_0402_16V7K

PQ35
TP0610K-T1-E3_SOT23-3

0_0402_5%
1
0_0402_5%
2

SPOK
ILM1

2VREF_ISL6237 2

@ PR50
0_0402_5%

PC143
1U_0603_10V6K
1
2

2
PR51
0_0402_5%
2

VL

PR52
806K_0603_1%

22,40 MAINPWON

NC

PC37
0.22U_0603_25V7K

PD12
1SS355_SOD323-2

PR47
200K_0402_5%
1
2

PD8
GLZ5.1B_LL34-2
1
2

FB5

0.22U_0603_10V7K

+3.3VALWP Ipeak=8.444A ; Imax=5.91A


Choke DCRmax=60m ohm, DCRtyp=54m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
VS
Iocp=Ilimit+Delta I/2
=10.134A ~ 11.967A
Delta I=1.934A (Freq=300KHz)

PR43
10K_0402_1%
1
2

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

41

of

50

LX_CHG
PD10
2

Place close to back to back MOS

PR66
0_0402_5%
1
2

ACSET

PR67
340K_0402_1%

ACOP

1
2

1
2
3

2
1

1
3

BATT+

PC54
1U_0603_10V6K

PQ13
AO4466_SO8

DL_CHG

LODRV

23

PGND

22

LEARN

21

CELLS

20

CELLS

PC55
680P_0402_50V7K

1
31

OVPSET

AGND

ACOFF

24751_VREF

VDAC

SE_CHG+

18

SE_CHG-

BAT

17

TP

29

VADJ

VMB

/BATDRV

Vacset=3.3*(50K/(50K+64.9K))=1.436V

ACGOOD

14

BATDRV

SRSET

PR74
340K_0402_1%

SRSET

15

PR72
10_0603_5%
1
2

2
1

3
VADJ

S
24751_VREF

1
PQ19
2N7002W-T/R7_SOT323-3

2
G

CHGEN#
D

PQ18
2N7002W-T/R7_SOT323-3

2
G

FSTCHG

31

PR81
100K_0402_1%
1

@PR177
@
PR177
4.3K_0402_5%

PR82
100K_0402_1%

S
PQ37
SSM3K7002F_SC59-3

2
G

REGN

PR80
0_0402_5%
1

23,31,39

D
@ PQ16
2N7002W-T/R7_SOT323-3

PQ17
SI2301BDS-T1-E3_SOT23-3

PQ36
SSM3K7002F_SC59-3
3

ACIN
ACGOOD#

PC144
100P_0402_50V8J

2
G

2
PR78
887K_0402_1%

31 CALIBRATE#
PR85
100K_0402_1%

24751_VREF

PR84
221K_0402_1%
2
1

PR180
200K_0402_1%
2
1
D

@PR176
@
PR176
0_0402_5%
1

31

PQ15_GATE

2
G
PR181
340K_0402_1%
2
1

1
2

2
ACSET

PC163
0.1U_0402_16V7K
ACOFF 1
2

ADP_I

PR79
105K_0402_1%

6
PC66
0.01U_0402_25V7K

24751_VREF

@PC63
@PC63
0.01U_0402_25V7K

PU1B
LM358DT_SO8
7 0

PR77
10K_0402_1%
1
2

PR76
499K_0402_1%
2

Per cell=3.5V

IREF 31

@ PR75
@PR75
100K_0402_1%

24751_VREF

BATT-OVP=0.1112*VMB

24751_VREF

LI-3S :13.5V----BATT-OVP=1.5012V

PC64
100P_0402_50V8J

PR179
100K_0402_1%
2
1

Fsw : 300KHz

For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A


For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
Icharge=(Vsrset/Vdac)*(0.1/PR62)
IREF*(100k/(100K+17.4K)/3.3)*(0.1/0.02)=Icharge

IREF=0.77448*Icharge

PR73
100K_0402_1%

BQ24751ARHDR_QFN28_5X5

BATT-OVP=0.1112*VMB

PC65
0.01U_0402_25V7K

LI-4S :18.0V----BATT-OVP=2.001V
Input UVP : 17.26V

PR83
64.9K_0402_1%
24751_VREF 1
2

16

VS

Input OVP : 22.3V

PR71
17.4K_0402_1%
2
1

IADAPT

31 BATT OVP

Icharge Setting

ICHG setting

CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A

13

ACGOOD#

65W adapter R=(100K*100K)/(100K+100K)=50K

PC61
0.1U_0603_25V7K

12

VADJ

19

PR70
100K_0402_1%

ACSET

SRP
SRN

CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A

PC62
0.1U_0603_25V7K

90W adapter
Vacset=3.3*(100K/(64.9K+100K))=2.001V

11
1

CP point=Iadapter*85%

RTCVREF

@PC59
@PC59
0.1U_0603_25V7K

PR69
100K_0402_1%
1
2PQ15_GATE
2

VREF

PC60
1U_0603_10V6K

PC58
0.1U_0603_25V7K

PQ15
SI2301BDS-T1-E3_SOT23-3

24751_VREF 10

PR68
54.9K_0402_1%

Cells selector

CP Point Setting

31
1

PC57
0.1U_0402_16V7K
1
2
1

OVPSET

@ PQ14
2N7002W-T/R7_SOT323-3
2
3S/4S#
G

2
PR64
4.7_1206_5%

24
1

PC56
0.47U_0603_16V7K
1
2
7

REGN

CELLS

ACSET

PR63
54.9K_0402_1%

4 Cell

3 Cell

VREF

PC51
LL4148_LL34-2
0.1U_0603_25V7K

REGN

2
1

@ PR65
@PR65
100K_0402_1%

GND

CELLS

PR62
0.02_2512_1%

PL5
10UH_PCMB104T-100MS_6A_20%
1
2

25

PH

PC53
10U_1206_25V6M

HIDRV

5
6
7
8

ACDRV
ACDET

DH_CHG

4
5

27
26

ACN
ACP

ACDRV

BTST

PQ12
SI4835BDY-T1-E3_SO8

/BATDRV

PQ11
AO4466_SO8

PC52
10U_1206_25V6M

2
3

PR57
100K_0402_1%

ACN
ACP

PC44
2200P_0402_25V7K

BTST

PR61
2.2_0603_5%
1
2

PC40
0.01U_0402_25V7K

3
2
1

@PC49
@PC49
0.1U_0603_25V7K

PC48
0.1U_0805_25V7K
1
2

PC43
4.7U_1206_25V6K

28

PVCC

CHGEN

PVCC

PU5
1

ACDET

24751_VREF

CHG_B+

PR60
340K_0402_1%
PC50
2.2U_0805_25V6K

JUMP_43X118
CHGEN#

1
PC47
0.1U_0603_25V7K

PC42
4.7U_1206_25V6K

5
6
7
8

5
6
7
8

2
1 2
@PD9
@
PD9
RLZ24B_LL34

PJ11
1

PC46
0.1U_0402_16V7K
1
2

PR174
3.3_1210_5%

8
7
6
5

PC45
0.01U_0402_25V7K

PR58
3.3_1210_5%

3
2
1

PR56
0.015_2512_1%

3
2
1

8
7
6
5

B+

PQ10
SI4835BDY-T1-E3_SO8

PR59
100K_0402_1%

VIN

3
2
1

PQ9
SI4835BDY-T1-E3_SO8

2
G
PQ20
2N7002W-T/R7_SOT323-3

65W/90W#

PR86
100K_0402_1%

Charger ADJ

31

CP setting

Calibrate#

PR78

PR84

4.0V

4.1V

887K

221K

4.2V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
D

42

of

50

FB1

GND_T

29

PGOOD2

28

PR98
3.3K_0402_5%
2
1

2
VIN2

3
VCC2

4
VCC1

5
VIN1

PR92
18.2K_0402_1%

PR97
22.6K_0402_1%

OCSET_1.05V

10

OCSET1

1.05V_EN

11

EN1

FB2

VO2

26

OCSET2

25

EN2

24

PHASE2

23

6228_1.8VO2

Vref=0.6V
OCSET_1.8V

2
1

5
6
7
8
D
D
D
D

PR108
4.7_1206_5%

+1.8VP
1
+

PQ24
FDS6670AS_NL_SO8

PC88
330U_D2E_2.5VM

PC89
680P_0402_50V7K

S
S
S

+5VALW

PL7
1UH_MSCDRI-104R-1R0N-F_11A_30%
1
2

PC86
1U_0402_6.3V6K

3
2
1

2
1

PR105
10K_0402_1%

DCR 6m ohm(max)

LG_1.8V

Cout ESR=15m ohm

Vo=0.6*((PR87+PR83)/PR83)=1.8V
1.8VP Ipeak=11.93A, Imax=8.351A
Csen=L/(Rocset*DCR)=1uF/(Rocset*6m ohm)=0.022uF
=>Rocset=7.575K, Choose 10K because of thermal factor
Iocp=(Rocset*10uA)/DCR=(10K*10uA)/(0.006*1.3)=12.82A

PR110
0_0402_5%
2
1

1.05V_EN

VS ON

BOOT2

LX_1.8V

LG_1.05V

33

PC82
0.022U_0402_16V7K
1
2

UG_1.8V

PR109
PC87
2.2_0603_5% 0.1U_0402_16V7K
BST_1.8V 1
2
1
2

+5VALW
PC85
1U_0402_6.3V6K

22

21

PVCC2
20

LGATE2
19

PGND2
18

17

Cout ESR=15m ohm

+1.05VSP
OCP Seting is same as ICL50
Vo=Vref*((PR80+PR82)/PR80)
Ipeak=14.02A, Imax=9.81A
Iocp=14.02*1.2=16.824A
Csen=L/(Rocset*DCR)
0.015U=1U/(Rocset*6m) Rocset=11.111K~11.8K
Iocp=(Rocset*10uA)/DCR
Iocp=(11K*10uA)/(6m ohm*1.3) =15.1A

PGND1

UGATE2
LGATE1

BOOT1

15

DCR 6m ohm(max)

PC84
0.1U_0402_16V7K

ISL6228 B+

PQ23
AO4466_SO8

16

1
2
3

UGATE1

PVCC1

S
S
S

1
2

PC83
680P_0402_50V7K

PR106
2.2_0603_5%
1 2
1BST_1.05V
14

UG_1.05V 13

31,37,44

1
2
3
8
7
6
5
D
D
D
D

PC80
330U_D2E_2.5VM

PQ22
FDS6670AS_NL_SO8

SYSON

@ PC78
@PC78
0.01U_0402_25V7K
1
2

PHASE1

PC79
4.7U_1206_25V6K

PR103
0_0402_5%
1
2

12

LX_1.05V

PU6
ISL6228HRTZ-T_QFN28_4X4

PR104
4.7_1206_5%

FB_1.8V

PR100
10K_0402_1%
1
2

PC81
4.7U_1206_25V6K

FB_1.8V-1

27

5
6
7
8

8
7
6
5

VO1

PQ21
AO4466_SO8

PL6
1UH_MSCDRI-104R-1R0N-F_11A_30%
2

+1.05VSP

3
2
1

PR101
11.8K_0402_1%

PC77
4.7U_1206_25V6K

1
2

PC75
0.015U_0402_16V7K
1
2

PC76
4.7U_1206_25V6K
2
1

ISL6228 B+

PC74
1000P_0402_50V7K
1
2

PR99
45.3K_0402_1%
1
2

6228_1.05VO1

PR96
11.8K_0402_1%
1
2

PGOOD1

FB_1.05V-1

ISL6228 B+

PC73
1000P_0402_50V7K
2
1

PR91
22K_0402_1%
2
1

PC71
1000P_0402_50V7K

PR94
60.4K_0402_1%

PR95
45.3K_0402_1%
2
1

FB_1.05V

PR93
3.3K_0402_5%
1
2

PC69
0.1U_0603_25V7K
PR90
10_0603_1%
2
1

PC72
1000P_0402_50V7K
2
1

PR89
10_0603_1%
2
1

ISL6228 B+

+5VALW

FSET2

ISL6228_B+

B+

FSET1

PJ12
JUMP_43X118
2 2
1 1

PR88
2.2_0603_1%
1
2

PC70
0.1U_0603_25V7K

PC68
1U_0402_6.3V6K

PR87
2.2_0603_1%
2
1

+5VALW

PC67
1U_0402_6.3V6K

@ PC90
@PC90
0.01U_0402_25V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
D

43

of

50

@PR178
@
PR178
0_0402_5%
1
2

51117_B+

PQ26

PGOOD

14

LX_1..5V

TRIP

11

V5DRV

10

DRVL

1
2
3
4

D2
D2
G1
S1

AO4932_SO8
<BOM Structure>

G2
S2/D1
S2/D1
S2/D1

PJ13
JUMP_43X118
2 2
1 1

PL8
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2

B+

+1.5VP

1
+

+5VALW

PC95
330U_D2E_2.5VM

2
DL_1.5V

DL_1.5V

TPS51117RGYR_QFN14_3.5x3.5

DH_1..5V

12

VFB

13

LL

VFB=0.75V

DRVH

V5FILT

VBST

15
TP

1
EN_PSV

BST_1..5V

PC98
1U_0603_10V6K

VOUT

PR113
PC93
0_0603_1%
0.1U_0603_25V7K
1
2BST_1..5V-1 1
2

PR115
17.8K_0402_1%

@ PC96
@PC96
47P_0402_50V8J
1
2

TON

PGND

PR114
0_0603_1%
1
2

GND

PU7
@PC94
@PC94
0.1U_0402_16V7K

+5VALW

8
7
6
5

31,37,43 SYSON

PR111
143K_0402_1%
1
2

PR112
0_0402_5%
1
2

31,37 SBPWR_EN

PC91
4.7U_1206_25V6K

PC97
4.7U_0805_10V6K

PR116
10K_0402_1%
1
2

PR117
10K_0402_1%

VFB=0.75V
Vo=VFB*(1+PR87/PR88)=0.75*(1+10K/10K)=1.5V
Ton=19*e-12*143000(((2/3)*Vo+100mV)/19)+50ns
=2.645e-7 us
=>Vo/Vin=D=Ton/Ts =>Ts=3.35us
Fsw=298KHz
B

Cout ESR=15m ohm


Ipeak=4.71A, Imax=3.297A, Iocp=5.652A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=2.107A
=>1/2DeltaI=1.053A
Vtrip=Rtrip*10uA=17.8K*10uA=0.178V
Iocpmin=Vtrip/Rdsonmax*1.2+1.053A
=0.178/(0.027*1.2)+1.053=5.493A+1.053A=6.546A
Iocpmax=(0.178/(0.021*1.1))+1.053A=7.705A+1.053A
=8.758A
Iocp=6.546A~8.758A

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday May 16 2008

Sheet
1

44

of

50

+1.8V

+5VALW

NC

REFEN

VOUT

NC

GND

PC100
1U_0603_6.3V6M

PJ15
JUMP_43X79
PM@PC105
1U_0603_6.3V6M

5
4

VOUT

FB

VIN

PM@PC102
4.7U_0805_6.3V6K

+2.5VSP
1

PM@PC107
0.01U_0402_25V7K

PM@PU11
APL5915KAI-TRL_SO8

PM@PC106
22U_0805_6.3V6M

PM@PC116
0.1U_0402_16V7K

PM@PR122
2.15K_0402_1%
2

EN

VIN
VOUT

VCNTL

1
PM@PR124
0_0402_5%
1
2

GND

1
PC104
10U_0805_6.3V6M

31,33,37 SUSP#

POK

3
2

PC103
0.1U_0402_16V7K

+0.9VSP
2

PR120
1K_0402_1%

PC101
0.1U_0402_16V7K
2
1

PQ27
2N7002W-T/R7_SOT323-3
2
G
1

33,37 SUSP

PR119
0_0402_5%
1
2

RT9173DPSP_SO8

PR118
1K_0402_1%

NC

VCNTL

GND

+3VALW

VIN

PU8

PC99
4.7U_0805_6.3V6K

+3VALW
PJ14
JUMP_43X79

PM@PR123
1K_0402_1%

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday May 16 2008

Sheet
1

45

of

50

+5VS
B+

CPU_B+

CPU_VID6 5

PR125
1_0603_5%

CPU_VID5 5

PL9
FBMA-L18-453215-900LMA90T_1812
2
1

RBIAS

PGND1

33

VR_TT#

NTC

PHASE_CPU1

LGATE1

32

PVCC

31

LGATE2

30

PGND2

29

PQ34
AO4456_SO8

PC133 220P_0402_50V7K
PR163
255_0402_1% PC134 1000P_0402_50V7K
1
2
1
2

3
2
1

PC123
10U_1206_25V6M
2
1

PC132
0.22U_0603_10V7K

ISEN2
CPU_B+

PC135
0.1U_0603_25V7K

1
PR168
2.61K_0402_1%

PR173 4.42K_0402_1%

2
2
PH3
10KB_0603_5%_ERTJ1VR103J
1

PC138
0.01U_0603_50V7K

PC139 180P_0402_50V8J
1
2

PR172 1K_0402_1%

3
2
1

1
1

PR170
20_0402_5%

VSUM

VSUM
1

PC137
@0.022U_0603_50V7K

PR171
11K_0402_1%
2
1

PR169
0_0402_5%
1
2

VSSSENSE

PR156
1_0402_5%
@ PR159
@PR159
0_0603_5%
1
2

PC136 820P_0402_50V7K
1
2

VCC_PRM

+CPU_CORE

PR167
20_0402_5%
1
2

4
+5VS

PC131
1U_0402_6.3V4Z

VCCSENSE

ISEN1
ISEN2
2
1_0603_5%

PR164
10_0603_5%
1
2

1
2
PR165
1K_0402_1%
PR166
0_0402_5%
1
2

1
PR158

2 PR162 1
1K_0402_1%

470P_0402_50V7K
2

@ 0_0402_5%

PR160 97.6K_0402_1% PC130


1
2
2

PR161 2

PC128 1000P_0402_50V7K

CPU_B+

PL11
0.36UH_FDU1040D-R36M_26A_20%
2
1
PR155
10K_0402_1%
2
1

PQ33
AO4456_SO8

24

23

VDD
22

21

VIN
20

19

DFB

VO
18

PR157
3.65K_0805_1%
2
1

25

PC129
PR154
680P_0402_50V7K
6.8_1206_5%
2
1 2
1

NC

3
2
1

FB2

5
6
7
8

12

BOOT_CPU2
1
2
1
2
PR152
2.2_0603_5%
PC127
0.22U_0603_10V7K

5
6
7
8

26

ISEN1

BOOT2
ISEN2

FB
GND

UGATE_CPU2-1

11

VSUM

PHASE_CPU2

27

DROOP

28

RTN

PHASE2
UGATE2

PC122
10U_1206_25V6M
2
1

PQ32
SI7686DP-T1-E3_SO8
4

COMP

17

LGATE_CPU2

VW

16

1
2
1000P_0402_50V7K
PR153 6.81K_0402_1%
1
2

LGATE_CPU1

10

13K_0402_1%
1
2

13

PC126

OCSET

15

PR151

SOFT

VSEN

PC125
0.022U_0603_25V7K
1
2

PU10
ISL6262ACRZ-T_QFN48_7X7

VDIFF

VCC_PRM

ISEN1
0.22U_0603_10V7K

VR_TT#

VSUM

34

PR145
1_0402_5%
@ PR146
@PR146
0_0603_5%
1
2
PC121
1
2

PHASE1

+CPU_CORE

PMON

PQ31
AO4456_SO8

4
4
PQ30
AO4456_SO8

PR144
10K_0402_1%
2
1

35

PR143
3.65K_0805_1%
2
1

PR142
6.8_1206_5%
1 2
1

5
6
7
8
36

PC113
10U_1206_25V6M
2
1

5
6
7
8

38

37
VID0

40

41

42

45

46

39

VID1

VID2

VID3

VID4

VID5

47

48
3V3

49
GND

BOOT1
UGATE1

PC115
220U_25V_M

PC124
2200P_0402_50V7K
2
1

147K_0402_1%

PSI#

UGATE_CPU1

PC120
680P_0402_50V7K

PR149
1

@ 0_0402_5%

PGOOD

PL10
0.36UH_FDU1040D-R36M_26A_20%
2
1

3
2
1

PR138
PC119
2.2_0603_5%
0.22U_0603_10V7K
1
2 1
2

3
2
1

1 PR148

PGD_IN

DPRSTP#

1
2
PR147 0_0402_5%

PSI#

14

31

VGATE

DPRSLPVR

CLK_EN#

8,16,23

BOOT_CPU1

PQ29
SI7686DP-T1-E3_SO8

3
2
1

1
2

PC118
1U_0603_6.3V6M

2
1

1.91K_0402_1%

PR140

PR139

+3VS

499_0402_1%

PC112
10U_1206_25V6M
2
1

1
0_0402_5%
2

43

PR134
1

VID6

16 CLK_ENABLE#

CPU_VID0 5

0_0402_5%
2

2
1
PR129 0_0402_5%
2
1
PR135 0_0402_5%
2
1
PR136 0_0402_5%
2
1
PR137 0_0402_5%
2
1
PR130 0_0402_5%
2
1
PR131 0_0402_5%
2
1
PR132 0_0402_5%
2
1
PR133 0_0402_5%

PR128
1

44

5,8,22 H_DPRSTP#

PC109
0.022U_0402_16V7K

CPU_VID1 5

0_0402_5%
2

PC110
2.2U_0603_6.3V6K

PR127
1

CPU_VID2 5

8,23 PM_DPRSLPVR

+3VS

CPU_VID3 5

PR126
499_0402_1%
1
2

VR_ON

VR_ON

PC114
2200P_0402_50V7K
2
1

CPU_VID4 5
31,33

VCC_PRM
PC140
0.1U_0402_16V7K
1
2

PC141

1
0.22U_0402_6.3V6K
A

2
PC142
0.22U_0603_10V7K

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday May 16 2008

Sheet
1

46

of

50

Version change list (P.I.R. List)


Item
D

1
2
3
4

Delete PD1.

3/5V exit on battery mode shutdown.


PD11 has over temp. issue.
Add snubber in 3/5V by
EMI request.

Reason for change

Rev.

PG#

Modify List

Date

Phase

Because we can cost down and DOCK_B+ has another one.

0.1

39

1 Delete PD1 SCSB540C080 (S SCH DIO B540C-13-F SMC)

20071108

EVT

To prevent 3/5V exit on battery mode shutdown.

0.2

41

Add SC100001K00 (S DIO 1SS355 SOD323 T/R-5K

20071221

DVT

Because PD11 has over temperature issue in JAQ60,


we change it to a 10A diode.

0.2

39

Change PD11 from SCSB540C080

20071221

DVT

to SCS00002F00 .

Add snubber in 3/5V by EMI request.

0.2

41

Add PR36 and PR39 to SD001470B80

20071221

DVT

Down size.

Down size. by sourcer request.

0.2

46

Change PC136 from SE025821K80 to SE000003W00

20071221

DVT

Down size.

Down size. by sourcer request.

0.2

46

Change PC120 and PC129 from SE024681J80 to SE074681K80 20071221

DVT

Down size.

Down size. by sourcer request.

0.2

43

Change PC72 and PC74 from SE068102J80 to SE074102K80

20071221

DVT

2nd source trial run TI controller.

0.2

41

Add PC143 SE080105K80

20071221

DVT

Add snubber in 3/5V by


EMI request.

Add snubber in 3/5V by EMI request.

0.2

41

Add PC33 and PC34 SE074681K80

20071221

DVT

10

To meet Jeta SPEC.

To meet Jeta SPEC.

0.2

42

Add PC144 SE074102K80

20071221

DVT

12

Add EMI solution.

Add 3/5V boost resistor.

0.3

41

Add PR37, PR40 SD013220B80 (S RES 1/10W 2.2 +-5% 0603) 20080102

DVT

13

Add EMI solution.

Add charger boost resistor.

0.3

42

Add PR61 SD013220B80 (S RES 1/10W 2.2 +-5% 0603)

20080102

DVT

14

Add EMI solution.

Add charger snubber.

0.3

42

Add PR64 SD001470B80(S RES 1/4W 4.7 +-5% 1206)


Add PC55 SE074681K80(S CER CAP 680P 50V K X7R 0402 )

20080102

DVT

15

Add EMI solution.

Add 1.05V/1.8V boost resistor.

0.3

43

Add PR106, PR109 SD013220B80 (S RES 1/10W 2.2 +-5% 0603) 20080102

DVT

16

Add EMI solution.

Add 1.05V snubber.

0.3

43

Add PR104 SD001470B80(S RES 1/4W 4.7 +-5% 1206)


Add PC83 SE074681K80(S CER CAP 680P 50V K X7R 0402 )

20080102

DVT

17

Add EMI solution.

Add 1.8V snubber.

0.3

43

Add PR108 SD001470B80(S RES 1/4W 4.7 +-5% 1206)


Add PC89 SE074681K80(S CER CAP 680P 50V K X7R 0402 )

20080102

DVT

18

Add EMI solution.

Add CPU boost resistor.

0.3

46

Add PR138, PR152 SD013220B80 (S RES 1/10W 2.2 +-5% 0603) 20080102

DVT

19

Add EMI solution.

Add 3/5V input capacitor filter..

0.3

41

Add PC159, PC160, PC161, PC162 SE074471K80(S CER CAP


470P 50V K X7R 0402)

20080102

DVT

20

Add EMI solution.

Add 3/5V input beat

0.3

41

Add PL12, PL13 SM010016410(S SUPPRE_ KC FBMA-L11322513-151LMA50T)

20080102

DVT

8
9

Fixed Issue

Page 1 of 2
for PWR

2nd source trial run TI controller.

21
22
A

23

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

47

of

50

PHASE
PAGE
MODIFICATION LIST
PURPOSE
----------------------------------------------------------------------------------------------------------------------------------------------DVT

Change R25 , R18 , R11 , R19 from 56 to 54.9 ohm

P.4

Delete R10

Foe ESD

P.4

Change CPU temp sensor U9 , R55 / R56 from 100 to0 ohm , delete R64 / R652

ADI had issue , for SMSC / Fintek temp sensor , no used for OD output

P.8

Change R525 , R527 connected from +1.05Vs to GND

Reference standard circuit

Change Cantiga GM U30 as SA00001P930 (Ver:B0)


Change Cantiga PM U30 as SA00001ZO30 (Ver:B0)

Revision upgrade
Reference standard circuit

P.12

Change L42 , L18 , C499 , C229 , C280 , C232 as GM@


Change R596 , R597 as PM@
Add C597 (220U)

P.12

Add C597 (220U)

P.12

Change R110 , C187 , C196 as stuff , R117 un-stuff

P.12

C461 down size as 10U_0603

P.16

Change Q30 (dual N-MOS) as Q48 , Q49 (2 single N-MOS)

NA

P.17

C500 down size as 680P_0402

For BOM

P.17

Add L57 , L58 , C598 , C599 for +1V8RUN

+1V8RUN ripple (+1V8RUN is for

P.17

Add R599 as 0ohm

Reserve R598 , D31

P.17

Update JMXM1 footprint

NA

P.17

Change Q41 (dual N-MOS) as Q50 , Q51 (2 single N-MOS)

NA

P.18

C364 down size as 680P_0402

For BOM

P.18

C365 , C366 , C367 change from 220P to 820P

For EMI

P.19

D5 change as RB411DT146_SOT23-3

Common part

P.12

Reference standard circuit

P.4

For UMA CRT


Reserved
Reference standard circuit
DFX
NA

P.19

Change Q40 (dual N-MOS) as Q52 , Q53 (2 single N-MOS)

NA

P.19

Change C401 , C409 , C419

as 15P

For DISCRETE CRT

as 12P

MXM +PEX1V2)

P.19

Change C402 , C410 , C420

P.19

C408 , C418 , C423

For DISCRETE CRT

P.19

Change L1 , L2

P.20

Change Q7 from 2N7002_SOT23(Dual N-MOS) as Q7 & Q47(Single BSH111 N-MOS)

P.20

Add R600 & R602 (4.7K ohm) pull high +3Vs

For DVI SMBUS

P.20

Reserve R601 & R603 (2.7K ohm) pull high +5Vs

For DVI SMBUS

P.20

Reserve U39 & U40 (SN74CBTD3306CPWR_TSSOP8)

For DVI & HDMI SMBUS

P.20

Change D21 from RB751V_SOD323 as CH751H-40PT_SOD323-2

NA

P.22

Change R478 from 33 ohm as 1K ohm

Customer request

P.22

LAN_RST# connect to GND

No used Integrated LAN

P.22

R169 un-stuff

For mobile

P.22

Add CR_CPPE#(GPIO7) & CR_WAKE#(GPIO22)

For JMB385 power management

P.22

Swap PCIE(x1) port 2 & port 4

NA

P.22

R385 un-stuff , U28 stuff

For sequence

P.25

U34.127 is used as externel IDSEL

NA

P.25

R489 un-stuff

For PCMCIA Lan card not support PM_CLKRUN# function

P.25

Update JPCM1 footprint

For DFX

P.26

Reserve R655 , R656 , D33 for CR_CPPE# & CR_WAKE#

For JMB385 power management

P.26

Cantiga JMB385 U32 as SA00001W910 (Ver:B)

Revision upgrade

P.27

Delete BCM5787M co-lay schematic

NA

P.27

Update U25 footprint

For DFX

P.28

Change T1 from GSL5009 as GSL5009-1(SP050003T10)

NA

P.28

Add C375 , C383 (68P)

For EMI

P.29

Add R658

Add 80 port function on JMINI2

P.30

D32(SC300000B00) stuff

For ESD

P.31

Add R604

NA

P.31

R248 change from 0 ohm as 8.2K ohm

Foe Board ID as 1 define

(22P) stuff for UMA only

For UMA CRT only

from FCM1608C-121T_0603 as 10ohm_0603

For CRT
For DVI SMBUS level shifter

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

48

of

50

PHASE
PAGE
MODIFICATION LIST
PURPOSE
----------------------------------------------------------------------------------------------------------------------------------------------DVT

P.31

C286 change from 3.3U as 4.7U

Stable KB926 internal +1.8V regulator , ENE suggestion value

P.32

JP6 pin define reverse

NA

P.32

Change SW3 & SW4 type

NA

P.32

U15 change from 1MB as 2MB capacity SPI ROM

Add Finger print code


Fix ATI MXM sku can't power on for battery mode issue

P.33

R261 change from 10K as 31.6K

P.33

C334 change from 0.1U as 1U

Fix nVIDIA MXM sku power on issue

P.34

Delete Internal(Digital) MIC reserved circuit

NA

P.34

Change R574 (0 ohm) as L59 (MBC1608121YZF)

For EMI

P.34

Add R660 to connect HDA_GPIO3 with DOCKIN#

For docking spdif feature enable

P.34

Change R574 (0 ohm) as L59 (MBC1608121YZF)

For EMI

P.35

R559 / R560 change from 47 ohm as 75 ohm

For Audio precision FSOV

P.35

R561 / R562 / R566 / R571 change from 75 ohm as 1K ohm

For ESD , Realtek suggestion value

P.36

Add C601 , C602 , C603 (330P) on +5VALW

For EMI

P.37

R283 change from 100K to 10K

NA

P.37

R206 , Q20 stuff

For +1.8V discharge

P.38

Add switch to enable/disable EC_DOCKIN#_S0 for HDMI SMBUS

NA

P.38

Update JDOCK1 footprint

NA

P.16

Change C308 / C311 (33P) as 27P

For RTC accuracy

P.23

Use 4MB SPI ROM

For Kinabalu_High & Kinabalu_Low

P.23

Add test point T32 / T33 / T34 / T35

Reserved for PCIE(X1) port 1

PVT1

PVT2

MP
A

P.25

Change U35 as SA000026P10(OZ2210GN-B1)

For B1 version

P.27

Change U23 as SA000025P20(BCM5764MKMLG P20)

For B0 version

P.27

Reserved R673 , R674 (0 ohm)

For Lan SMBUS

P.27

Reserved Lan GPIO0(LAN_ALERT#) / LAN_ALERT#_EC / R675 , R676 , R677 to EC

For Lan ASF workaround

P.27

U23 Pin17 / Pin5 / Pin55 connect to U23 Pin18 for power +Lan_VDDIO_1.2

U23 Pin18 is power source +Lan_VDDIO_1.2 for U23 Pin17 / Pin5 / Pin55

P.27

U23 Pin38 / Pin52 NC

NA

P.29

Change JMINI1 for Robson2 , chnage JMINI2 for Wireless

NA

P.31

Add LAN_ALERT#_EC & EC_ACIN for EC

Reserved for ASF workrund & Nvidia MXM power saving

P.33

Add R668(10K) & reserved R263(10K)

Fine tune +1.05VS timing for UMA boot display flash

P.34

Change U36 as ALC268-VB1-GR(SA00001GD10)

Version upgrade

P.34

Stuff R659 & un-stuff R660

For SPDIF feature on docking

P.36

Add C604 , C605 (820P_0402)

For EMI

P.50

Chipset change as GM(SA00002JT10) / PM(SA00002JJ00) /ICH9M(SA00002JH00)

Version upgrade

P.27

Update U23 CIS symbol

U23 Pin38 , 52 can't be changed as NC

P.34

Add D34 , R678

For ACER docking SPDIF feature (No SPDIF on board)

P.38

Update JDOCK1 CIS symbol

Docking connector modify (add boss x 2) for DFX

P.35

Delete D2 , D4 (Int SPK ESD diode)

NA

P.34

Delete D9 (Int MIC ESD diode)

NA

P.35

Add C609 , C610 (330P_0603) on Right SPK

For EMI

P.34

Add C608 (330P_0603) on Int MIC

For EMI

P.08

Add Test point (T39 , T40 , T41 , T42)

Add Management Engine JTAG pins

P.27

Add C612 , C614 (0.1u_0402) for +LAN_AVDD

For lower 1000Base-T Comm-Mode O/P Voltage < 50mV

P.27

Add C615 , C616 , C617 (0.1u_0402) for +LAN_AVDDL

For lower 1000Base-T Comm-Mode O/P Voltage < 50mV

P.08

Add U41, R679 , R680 , R681 , R682 , R683 , R684 , R685 , T43

Reserved for Management Engine JTAG debug

P.07

Chipset change as GM(SA00002JT50) / PM(SA00002JJ50)

Version upgrade

P.20 , P.31

Add EC_DVI_DET , EC_GPIOB , EC_GPIOC , R687 , R688 , R691

Reserved for DVI detect delay control (by EC)

P.24

R73 , R148 change from 10_0402 to 100_0402


C128 , C204 change from 0.1U_0402 to 1U_0402
C608 , C609 , C610 change from 330P_0603 to 330P_0402

For USB issue on ICH9M A3 stepping

P.34 , P.35

For 330P_0402 is standard part

P.31

Change R248 as 33K

Board ID upgrade

P.30

Add R692 / R693 (0_0603)

Reserved S3 power rail for check finger print sensor S3 resume too slow
Compal Secret Data
Compal Electronics,

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Inc.

Title

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

49

of

50

PHASE
PAGE
MODIFICATION LIST
PURPOSE
----------------------------------------------------------------------------------------------------------------------------------------------P.20

Add D35

Reserved for HDMI_HPD

P.30

Add R694 / R695 (0_0603)

Reserved for check

P.27

Delete C612 , C614 , C615 , C616 , C617 (0.1u_0402)

No need

P.16

Stuff R689 / R690

Reserved for LAN power saving

P.35

R559 , R560 change from 75 to 54.9 ohm

For FSOV between 420mv~480mv

Chipset change as GM(SA00002JTB0) / PM(SA00002JJA0) /ICH9M(SA00002JH70)

Version upgrade

P.32

R291 , R294 change from 300_0402_5% to 150_0402_5%

For ACER Hank's request to fine tune brighter

P.20

R84 , R85 , R86 , R91 change from 2K_0402_5% to 4.7K_0402_5%

For UMA DVI/HDMI monitor P193WA (x) detect issue (On JAL90)

PCB
ZZZ

IC

For Discrete

U30

LA4221MB Rev0: DA600007R00

CRT

LA4221MB Rev1: DA600007R10

MCH

PM@
C419

LA4221MB with Sub/B Rev1: DAZ04800100

C409
1

PCB 047 LA-4221P REV1 M/B

C401
1

2
R128 PM@

1
0_0402_5%

2
R129 PM@

1
0_0402_5%

2
R119 PM@

1
0_0402_5%

2
R138 PM@

1
0_0402_5%

2
R139 PM@

1
0_0402_5%

2
R140 PM@

1
0_0402_5%

2
R143 PM@

1
0_0402_5%

CANTIGA ES_FCBGA1329

DVT

CANTIGA PM: SA00001ZO30 (S IC EB88CTPM QR34 B0 FCBGA 1329 ES)

PVT

CANTIGA PM: SA00002JJ00 (S IC AC88CTPM QT78 B2 FCBGA 1329 PM)

PM@ 2

PM@ 2
PM@ 2
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J

PVT2 CANTIGA PM: SA00002JJ50 (S IC AC88CTPM QU38 B3 FCBGA 1329 PM)


Pre-MP CANTIGA PM: SA00002JJA0 (S IC AC82PM45 SLB97 B3 FCBGA1329 PM ABO!)
U30

15P_0402_50V8J: SE071150J80
12P_0402_50V8J: SE071120J80

UMAGL@
C420

C410
1

DC Cable

C402
1

CANTIGA ES_FCBGA1329
PM@ 2

PM@ 2
PM@ 2
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J

DVT(Check_TBD) CANTIGA GL: SA000023Z00 (S IC CANTIGA ES FCBGA 1329 MCH GL)

ZZZ

0_0402_5%: SD028000080

DC Cable (65W)
@ PVT(54 Rank)

U10

DC301003R00(CONN SET 048 DCJACK-MB 2DW-G756-I50 65W)

DVT(Check)

ICH9ME@
ICH9-M ES_FCBGA676

ZZZ

ICH9-M: SA00002G120
(S IC AF82801IEM QT10 A3 PBGA 676P ICH9M)
DC Cable (90W)
@ PVT(54 Rank)

DC301003S00(CONN SET 048 DCJACK-MB 2DW-G756-I49 90W)

U6
SPI2MB@
W25X16-VSSIG_SO8

MP
A

Winbond: SA00001KN00
(S IC FL 16MBIT W25X16-VSSIG SOIC 8P)

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4221
Document Number

Rev
C

401552
Friday, May 16, 2008

Sheet
1

50

of

50